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* Merge changes I1bfa797e,I0ec7a70e into integrationManish Pandey2023-05-093-3/+3
|\ | | | | | | | | | | * changes: fix(tree): correct some typos fix(rockchip): use semicolon instead of comma
| * fix(tree): correct some typosElyes Haouas2023-05-093-3/+3
| | | | | | | | | | | | | | found using codespell (https://github.com/codespell-project/codespell). Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373
* | fix(cpus): workaround platforms non-arm interconnectSona Mathew2023-05-052-19/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The workarounds for these below mentioned errata are not implemented in EL3, but the flags can be enabled/disabled at a platform level based on arm/non-arm interconnect IP. The ABI helps assist the Kernel in the process of mitigation for the following errata: Cortex-A715: erratum 2701951 Neoverse V2: erratum 2719103 Cortex-A710: erratum 2701952 Cortex-X2: erratum 2701952 Neoverse N2: erratum 2728475 Neoverse V1: erratum 2701953 Cortex-A78: erratum 2712571 Cortex-A78AE: erratum 2712574 Cortex-A78C: erratum 2712575 EL3 provides an appropriate return value via errata ABI when the kernel makes an SMC call using the EM_CPU_ERRATUM_FEATURES FID with the appropriate erratum ID. Change-Id: I35bd69d812dba37410dd8bc2bbde20d4955b0850 Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
* | refactor(errata_abi): factor in non-arm interconnectSona Mathew2023-05-052-12/+25
| | | | | | | | | | | | | | | | Workaround to help enable the kernel to query errata status using the errata abi feature for platforms with a non-arm interconnect. Change-Id: I47b03eaee5a0a763056ae71883fa30dfacb9b3f7 Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
* | feat(errata_abi): errata management firmware interfaceSona Mathew2023-05-053-1/+602
|/ | | | | | | | | | | | | | | | | | | This patch adds the errata management firmware interface for lower ELs to discover details about CPU erratum. Based on the CPU erratum identifier the interface enables the OS to find the mitigation of an erratum in EL3. The ABI can only be present in a system that is compliant with SMCCCv1.1 or higher. This implements v1.0 of the errata ABI spec. For details on all possible return values, refer the design documentation below: ABI design documentation: https://developer.arm.com/documentation/den0100/1-0?lang=en Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com> Change-Id: I70f0e2569cf92e6e02ad82e3e77874546232b89a
* feat(spmd): introduce platform handler for Group0 interruptMadhukar Pappireddy2023-05-011-1/+8
| | | | | | | | | | | | | This patch introduces a handler for FVP platform to triage Group0 secure interrupts. Currently, it is empty but serves as a placeholder for future Group0 interrupt sources. Moreover, this patch also provides a dummy implementation of the above mentioned platform hook for QEMU, corstone100, n1sdp and hikey960 ports. Change-Id: I01d3451408f47ac313b0af74046cce89f89b85bb Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* feat(spmd): add support for FFA_EL3_INTR_HANDLE_32 ABIMadhukar Pappireddy2023-05-011-0/+41
| | | | | | | | | | | | When Group0 Secure interrupts in secure world get trapped to S-EL2 SPMC, FFA_EL3_INTR_HANDLE ABI is invoked by SPMC to delegate interrupt handling to EL3 firmware (i.e., SPMD). SPMD further delegates to platform handler which successfully handles the Group0 secure interrupt before returning control to SPMC. Change-Id: I8cc0fec20803b96c81582910ad2668e38b167fb8 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* feat(spmd): register handler for group0 interrupt from NWdMadhukar Pappireddy2023-05-011-0/+43
| | | | | | | | | | SPMD registers a generic handler with the interrupt management framework to handle Group0 secure interrupt from normal world. The handler further delegates to the platform for successful handling of the interrupt. Change-Id: I9cdc721810b09e01190cdcab42c50830792a26e2 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* build(trp): sort sections by alignment by defaultChris Kay2023-04-171-0/+6
| | | | | | | | | | This change forces LD to sort all input sections by alignment when allocating them within an output section. This is done in some places explicitly in the linker scripts today, but this makes sure we don't miss any easy targets. Change-Id: Ife89a8bb9e592b55c761d9a3dfefc2aeeb07802f Signed-off-by: Chris Kay <chris.kay@arm.com>
* feat(cpufeat): enable FEAT_SVE for FEAT_STATE_CHECKEDJayanth Dodderi Chidanand2023-03-282-10/+5
| | | | | | | | | | | | | | Add support for runtime detection (ENABLE_SVE_FOR_NS=2), by splitting sve_supported() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we do SVE specific setup. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I1caaba2216e8e2a651452254944a003607503216 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* feat(cpufeat): enable FEAT_SME for FEAT_STATE_CHECKEDJayanth Dodderi Chidanand2023-03-282-4/+4
| | | | | | | | | | | | | | Add support for runtime detection (ENABLE_SME_FOR_NS=2), by splitting feat_sme_supported() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we do SME specific setup. Change the FVP platform default to the now supported dynamic option (=2),so the right decision can be made by the code at runtime. Change-Id: Ida9ccf737db5be20865b84f42b1f9587be0626ab Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* refactor(cpufeat): align FEAT_SEL2 to new feature handlingAndre Przywara2023-03-221-1/+1
| | | | | | | | | In ARMv8.4, the EL2 exception level got added to the secure world. Adapt and rename the existing is_armv8_4_sel2_present() function, to align its handling with the other CPU features. Change-Id: If11e1942fdeb63c63f36ab9e89be810347d1a952 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* refactor(cpufeat): enable FEAT_PAN for FEAT_STATE_CHECKEDAndre Przywara2023-03-221-1/+1
| | | | | | | | | | | | | | | | | At the moment we only support FEAT_PAN to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_FEAT_PAN=2), by splitting is_armv8_1_pan_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we PAN specific setup. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I58e5fe8d3c9332820391c7d93a8fb9dba4cf754a Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* refactor(cpufeat): enable FEAT_VHE for FEAT_STATE_CHECKEDAndre Przywara2023-03-201-1/+1
| | | | | | | | | | | | | | | | | | At the moment we only support FEAT_VHE to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_FEAT_VHE=2), by splitting is_armv8_1_vhe_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access VHE related registers. Also move the context saving code from assembly to C, and use the new is_feat_vhe_supported() function to guard its execution. Enable VHE in its runtime detection version for all FVP builds. Change-Id: Ib397cd0c83e8c709bd6fed603560e39901fa672b Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* feat(spmd): fail safe if SPM fails to initializeOlivier Deprez2023-03-091-6/+6
| | | | | | | | | | | | The spmd_setup function is made fail safe in that a failure in the SPMC manifest parsing, SPMD or SPMC initialization returns a success code to the standard services initialization routine (std_svc_setup). This permits continuing the boot process and initialize services beyond the SPMD to succeed for the system to operate in the normal world. It operates in a degraded mode for the secure world. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: Ida0ac91c17925279a79f112d190f9ad038f518e7
* Merge changes I51c13c52,I3358c51e into integrationManish Pandey2023-02-221-1/+1
|\ | | | | | | | | | | * changes: build: always prefix section names with `.` build: communicate correct page size to linker
| * build: always prefix section names with `.`Chris Kay2023-02-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of our specialized sections are not prefixed with the conventional period. The compiler uses input section names to derive certain other section names (e.g. `.rela.text`, `.relacpu_ops`), and these can be difficult to select in linker scripts when there is a lack of a delimiter. This change introduces the period prefix to all specialized section names. BREAKING-CHANGE: All input and output linker section names have been prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`. Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1c Signed-off-by: Chris Kay <chris.kay@arm.com>
* | Merge "feat(spmd): introduce FFA_PARTITION_INFO_GET_REGS" into integrationOlivier Deprez2023-02-171-0/+46
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| * feat(spmd): introduce FFA_PARTITION_INFO_GET_REGSRaghu Krishnamurthy2023-02-131-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add code in SPMD to forward calls to FFA_PARTITION_INFO_GET_REGS. This is a new ABI that allows getting partition information without the need for rx/tx buffer, that helps in situations where having an rx/tx buffer mapped and available is difficult (ex. uefi runtime services). Currently, the spmc at el3 does not support this new ABI. The new ABI uses registers x8-x17 to return partition information so changes are made to ensure those registers are passed through to the SPMC and restored on the return path. Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com> Change-Id: I1fe5956763e054e4f8d62292fc1247e7120bb5a4
* | build: clarify linker script generationChris Kay2023-02-102-4/+5
|/ | | | | | | | | | | | | | | | | | | | | | | | | The following build system variables have been renamed: - `LINKERFILE` -> `DEFAULT_LINKER_SCRIPT` - `BL_LINKERFILE` -> `DEFAULT_LINKER_SCRIPT_SOURCE` - `<IMAGE>_LINKERFILE` -> `<IMAGE>_DEFAULT_LINKER_SCRIPT_SOURCE` These new names better reflect how each variable is used: 1. the default linker script is passed via `-dT` instead of `-T` 2. linker script source files are first preprocessed Additionally, linker scripts are now placed in the build directory relative to where they exist in the source directory. For example, the `bl32/sp_min/sp_min.ld.S` would now preprocess to `sp_min/sp_min.ld` instead of just `bl32.ld` BREAKING-CHANGE: The `LINKERFILE`, `BL_LINKERFILE` and `<IMAGE_LINKERFILE>` build system variables have been renamed. See the commit message for more information. Change-Id: If8cef65dcb8820e8993736702c8741e97a66e6cc Signed-off-by: Chris Kay <chris.kay@arm.com>
* feat(spmd): copy tos_fw_config in secure regionManish V Badarkhe2023-02-091-1/+112
| | | | | | | | | | | | | | | | | | The tos_fw_config is currently loaded into memory by BL2 and consumed by SPMD (part of BL31) and BL32 firmwares. This does not work in RME-enabled systems as BL31 uses the root PAS memory and does not trust secure PAS memory. A first attempt was made to map the TOS_FW_CONFIG region as root PAS, and then to remap to secure PAS after SPMD consumption, but this was not suitable for RME systems where memory encryption is enabled. This can be solved by copying the TOS FW config (SPMC manifest) from the Root PAS region to the Secure PAS region so that BL32 can consume it. Change-Id: I8eef8345366199cb0e367db883c34a5b5136465d Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* feat(rme): set DRAM information in Boot Manifest platform dataAlexeiFedorov2023-01-172-3/+3
| | | | | | | | | | | | | | | | | | | | | This patch adds support for setting configuration of DRAM banks for FVP model in RMM-EL3 Boot Manifest structure. Structure 'rmm_manifest' is extended with 'plat_dram' structure which contains information about platform's DRAM layout: - number of DRAM banks; - pointer to 'dram_bank[]' array; - check sum: two's complement 64-bit value of the sum of data in 'plat_dram' and 'dram_bank[] array. Each 'dram_bank' structure holds information about DRAM bank base address and its size. This values must be aligned to 4KB page size. The patch increases Boot Manifest minor version to 2 and removes 'typedef rmm_manifest_t' as per "3.4.15.1. Avoid anonymous typedefs of structs/enums in headers" of https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com> Change-Id: I5176caa5780e27d1e0daeb5dea3e40cf6ad5fd12
* Merge changes from topic "bk/warnings" into integrationManish Pandey2023-01-101-2/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: docs: describe the new warning levels build: add -Wunused-const-variable=2 to W=2 build: include -Wextra in generic builds docs(porting-guide): update a reference fix(st-usb): replace redundant checks with asserts fix(brcm): add braces around bodies of conditionals fix(renesas): align incompatible function pointers fix(zynqmp): remove redundant api_version check fix: remove old-style declarations fix: unify fallthrough annotations
| * fix: unify fallthrough annotationsBoyan Karatotev2022-12-011-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Compiling with -Wimplicit-fallthrough=3 (enabled by -Wextra) produces many warnings about fallthrough comments either missing or being wrong. Unify the comments so we comply with -Wextra. Note that Coverity recommends against using the __attribute__ directive. Also, zlib does not build with a higher value of -Wimplicit-fallthrough. Finally, compilers strip comments before expanding macros. As such, checkpatch's fallthrough annotation (or higher levels of the flag) isn't really possible. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I060cf4f8dc04c02cbb45cf4ceb69569a8369ccee
* | Merge "refactor(trng): discarding the used entropy bits" into integrationManish Pandey2023-01-041-2/+88
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| * | refactor(trng): discarding the used entropy bitsJayanth Dodderi Chidanand2022-11-141-2/+88
| |/ | | | | | | | | | | | | | | | | | | | | | | This patch discards all the used entropy bits from the global memory pool after being delivered to the requester (lower exception levels) by overwriting them with zeroes. It effectively implements the requirement, as part of TRNG FW interface listed at DEN0098 (section 1.2). https://developer.arm.com/documentation/den0098/latest Change-Id: I447cbccc1a8ad972418a3569c99f010189d4b2f6 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* | Merge "fix(el3-spmc): report execution state in partition info get" into ↵Olivier Deprez2022-12-202-4/+42
|\ \ | | | | | | | | | integration
| * | fix(el3-spmc): report execution state in partition info getMarc Bonnici2022-11-092-4/+42
| | | | | | | | | | | | | | | | | | | | | | | | Ensure that the correct execution state of an SP is reported as part of an FF-A v1.1 PARTITION_INFO_GET response. Signed-off-by: Marc Bonnici <marc.bonnici@arm.com> Change-Id: I714e53ae71c376463797a42cd5ab7a5e9c687fb7
* | | Merge changes from topic "qemu_sel2" into integrationOlivier Deprez2022-12-151-0/+2
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: docs(build): describes the SPMC_OPTEE build option feat(qemu): support el3 spmc feat(el3-spmc): make platform logical partition optional feat(qemu): support s-el2 spmc feat(qemu): update abi between spmd and spmc fix(sptool): add dependency to SP image
| * | | feat(el3-spmc): make platform logical partition optionalJens Wiklander2022-12-081-0/+2
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | Prior to this commit a logical platform specific partition is added when compiling with SPMC at EL3. Not all platform need to add a logical platform so make this optional. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Change-Id: I3bdd2a91350330c1637e8d84765974bfb6b225d7
* | | Merge changes from topic "ffa_el3_spmc_fixes" into integrationOlivier Deprez2022-12-131-7/+33
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | * changes: fix(tsp): use verbose for power logs fix(el3-spmc): fix coverity scan warnings fix(el3-spmc): improve bound check for descriptor
| * | | fix(el3-spmc): fix coverity scan warningsShruti Gupta2022-12-081-5/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Validate emad descriptor integrity before accessing. Check for NULL pointer access. Signed-off-by: Shruti Gupta <shruti.gupta@arm.com> Change-Id: Id4ff3e5d88be95ca8d067378e344947880ec984b
| * | | fix(el3-spmc): improve bound check for descriptorMarc Bonnici2022-12-081-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure that there is sufficient space in the memory descriptor to accommodate the size of the composite memory struct as part of the descriptor. Signed-off-by: Marc Bonnici <marc.bonnici@arm.com> Change-Id: Iea646b144c59a2a1a171298cabb5f31040a8af31
* | | | Merge "fix(rmmd): add missing padding to RMM Boot Manifest and initialize ↵Alexei Fedorov2022-12-083-0/+32
|\ \ \ \ | |/ / / |/| | | | | | | it" into integration
| * | | fix(rmmd): add missing padding to RMM Boot Manifest and initialize itJavier Almansa Sobrino2022-12-073-0/+32
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch also: * Enforces the check of RES0 fields on EL3-RMM boot interface and manifest * Fixes a couple of nits on the EL3-RMM Boot Interface documentation. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: Idb9e38f9fcda2ba0655646a1e2c4fdbabd5cdc40
* | | fix(trp): preserve RMI SMC X4 when not used as returnAlexeiFedorov2022-12-072-34/+66
|/ / | | | | | | | | | | | | | | | | | | | | | | This patch adds X2-X6 and 'smc_ret' parameters to trp_rmi_handler(). The last 'smc_ret' parameter passed in X7 contains address of 'trp_smc_result' structure on stack to return result of RMI SMC call. This allows to preserve X4 if not used as a return argument as per SMCCCv1.2. The patch also removes use of trp_args_t in RMI handling. Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com> Change-Id: I9e3387a7380b37863eeccc53d13e92e0ac5cffbd
* | Merge changes from topic "ffa_el3_spmc_fixes" into integrationJoanna Farley2022-11-101-9/+25
|\ \ | | | | | | | | | | | | | | | | | | | | | * changes: fix(el3-spmc): check descriptor size for overflow fix(el3-spmc): fix location of fragment length check fix(el3-spmc): fix detection of overlapping memory regions fix(el3-spmc): fix incomplete reclaim validation
| * | fix(el3-spmc): check descriptor size for overflowMarc Bonnici2022-11-071-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure that the provided descriptor size used when reserving space for a memory descriptor does not overflow to prevent scope for memory corruption. Reported by Matt Oh, Google Android Red Team. Reported-by: mattoh@google.com Signed-off-by: Marc Bonnici <marc.bonnici@arm.com> Change-Id: If06985c4de9a88ff82ce60d10e346da948ed383f
| * | fix(el3-spmc): fix location of fragment length checkMarc Bonnici2022-11-071-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure that the fragment_length parameter is validated to prevent a buffer overflow before it is used. Reported by Matt Oh, Google Android Red Team. Reported-by: mattoh@google.com Signed-off-by: Marc Bonnici <marc.bonnici@arm.com> Change-Id: I0323c096ffd988fbd85bbd4ade3abd8427aea977
| * | fix(el3-spmc): fix detection of overlapping memory regionsMarc Bonnici2022-11-071-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current logic does not cover all scenarios of overlapping memory regions. Update the implementation to verify non-overlapping regions instead. Reported by Matt Oh, Google Android Red Team. Reported-by: mattoh@google.com Signed-off-by: Marc Bonnici <marc.bonnici@arm.com> Change-Id: I16c53d081e4455bc0e28399d28a1b27b1a9eb49c
| * | fix(el3-spmc): fix incomplete reclaim validationMarc Bonnici2022-11-071-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure that the full memory transaction descriptor has been transmitted before a request to reclaim the memory transaction is permitted. This prevents any potential accesses to the incomplete descriptor. Reported by Matt Oh, Google Android Red Team. Reported-by: mattoh@google.com Signed-off-by: Marc Bonnici <marc.bonnici@arm.com> Change-Id: I33e993c6b754632051e899ab20edd19b18b6cf65
* | | Merge "refactor(trng): cleanup the existing TRNG support" into integrationManish V Badarkhe2022-11-093-25/+31
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| * | refactor(trng): cleanup the existing TRNG supportJayanth Dodderi Chidanand2022-11-083-25/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the following changes to complete the existing TRNG implementation: 1. Adds a feature specific scope for buildlog generation. 2. Updates the docs on the build flag "TRNG_SUPPORT" and its values. 3. Makefile update and improves the existing comments at few sections for better understanding of the underlying logic. Change-Id: I3f72f0ccd5c94005a2df87158cf23199d2160d37 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* | | feat(drtm): add DRTM parameters structure version checkManish V Badarkhe2022-11-022-3/+10
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | Added DRTM parameters structure version check that as per the current released DRTM specification [1]. Mainly to cater below mentioned in the specification [1] section 3.12 - For a given DRTM major version number this structure will always be extended in a backwards compatible manner. [1]: https://developer.arm.com/documentation/den0113/a Change-Id: I9f312c7f9f20152c5d7e40a22b462c7fe8db70bc Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* | fix(el3-spmc): error handling in allocationvallau012022-11-021-1/+1
| | | | | | | | | | | | | | | | Error check must be done on the previously allocated pointer, not a random one from the code. Change-Id: I1c8253eacbe778cc4a9a8d71081fc615fa7e5293 Signed-off-by: Lukas Hanel <lukas.hanel@trustonic.com>
* | fix(el3-spmc): deadlock when relinquishing memoryvallau012022-11-021-1/+2
| | | | | | | | | | | | | | Do not forget to pass via err_unlock_mailbox: label. Change-Id: Icfb997b1c7cce196003af2c28bffc50dc73e30b4 Signed-off-by: Lukas Hanel <lukas.hanel@trustonic.com>
* | fix(el3-spmc): compute full FF-A V1.1 desc sizevallau012022-11-021-1/+1
|/ | | | | | | | | | | | | | | This patch fixes an issue in spmc_ffa_fill_desc. In order to compute the spmc_shm_get_v1_1_descriptor_size, fragment_length which is a fraction of the descriptor size is used as desc_size parameter. It has to be replaced with the full V1.0 descriptor size(obj->desc_filled). Ran a subset of our tests and they are passing. Change-Id: Ia4bbc5dabf0b77fa53d923ff609ee48ecd5bf549 Signed-off-by: vallau01 <valentin.laurent@trustonic.com> Signed-off-by: Lukas Hanel <lukas.hanel@trustonic.com>
* feat(drtm): flush dcache before DLME launchManish Pandey2022-10-061-12/+33
| | | | | | | | Flush the data cache range before DLME launch to ensure that data passed by DCE preamble is committed. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I9946fd3420a17b86d9f1483e8b2cd5880033454e
* feat(drtm): invalidate icache before DLME launchManish Pandey2022-10-061-2/+11
| | | | | | | | As per DRTM beta0 spec table #28, Before the DLME is called the DCE must invalidate all instruction caches. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I7efbb03d1d13346a8d898882fdbd7bbe8f1d49b2
* feat(drtm): ensure that passed region lies within Non-Secure region of DRAMManish V Badarkhe2022-10-051-8/+15
| | | | | | | | Ensured DLME data region and DRTM parameters are lies within Non-Secure region of DRAM by calling platform function 'plat_drtm_validate_ns_region'. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I93ead775f45ca7748193631f8f9eec4326fcf20a
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