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authorJack Rosenthal <jrosenth@chromium.org>2021-11-04 12:11:58 -0600
committerCommit Bot <commit-bot@chromium.org>2021-11-05 04:22:34 +0000
commit252457d4b21f46889eebad61d4c0a65331919cec (patch)
tree01856c4d31d710b20e85a74c8d7b5836e35c3b98 /baseboard/volteer/power.c
parent08f5a1e6fc2c9467230444ac9b582dcf4d9f0068 (diff)
downloadchrome-ec-stabilize-14469.58.B-ish.tar.gz
In the interest of making long-term branch maintenance incur as little technical debt on us as possible, we should not maintain any files on the branch we are not actually using. This has the added effect of making it extremely clear when merging CLs from the main branch when changes have the possibility to affect us. The follow-on CL adds a convenience script to actually pull updates from the main branch and generate a CL for the update. BUG=b:204206272 BRANCH=ish TEST=make BOARD=arcada_ish && make BOARD=drallion_ish Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Diffstat (limited to 'baseboard/volteer/power.c')
-rw-r--r--baseboard/volteer/power.c56
1 files changed, 0 insertions, 56 deletions
diff --git a/baseboard/volteer/power.c b/baseboard/volteer/power.c
deleted file mode 100644
index fa20cfa93f..0000000000
--- a/baseboard/volteer/power.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "gpio.h"
-#include "hooks.h"
-#include "power/icelake.h"
-
-/*
- * PWROK signal configuration, see the PWROK Generation Flow Diagram (Figure
- * 235) in the Tiger Lake Platform Design Guide for the list of potential
- * signals.
- *
- * Volteer uses this power sequence:
- * GPIO_EN_PPVAR_VCCIN - Turns on the VCCIN rail. Also used as a delay to
- * the VCCST_PWRGD input to the AP so this signal must be delayed
- * 5 ms to meet the tCPU00 timing requirement.
- * GPIO_EC_PCH_SYS_PWROK - Asserts the SYS_PWROK input to the AP. Delayed
- * a total of 50 ms after ALL_SYS_PWRGD input is asserted. See
- * b/144478941 for full discussion.
- *
- * Volteer does not provide direct EC control for the VCCST_PWRGD and PCH_PWROK
- * signals. If your board adds these signals to the EC, copy this array
- * to your board.c file and modify as needed.
- */
-const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {
- {
- .gpio = GPIO_EN_PPVAR_VCCIN,
- .delay_ms = 5,
- },
- {
- .gpio = GPIO_EC_PCH_SYS_PWROK,
- .delay_ms = 50 - 5,
- },
-};
-const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list);
-
-const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {
- /* No delays needed during S0 exit */
- {
- .gpio = GPIO_EC_PCH_SYS_PWROK,
- },
- /* Turn off VCCIN last */
- {
- .gpio = GPIO_EN_PPVAR_VCCIN,
- },
-};
-const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_deassert_list);
-
-static void baseboard_init(void)
-{
- /* Enable monitoring of the PROCHOT input to the EC */
- gpio_enable_interrupt(GPIO_EC_PROCHOT_IN_L);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_DEFAULT);