diff options
author | Tom Hughes <tomhughes@chromium.org> | 2022-09-21 14:08:36 -0700 |
---|---|---|
committer | Tom Hughes <tomhughes@chromium.org> | 2022-09-22 12:59:38 -0700 |
commit | c453fd704268ef72de871b0c5ac7a989de662334 (patch) | |
tree | fcf6ce5810f9ff9e3c8cce434812dd75492269ed /chip/max32660/tmr_regs.h | |
parent | 6c1587ca70f558b4f96b3f0b18ad8b027d3ba99d (diff) | |
parent | 28712dae9d7ed1e694f7622cc083afa71090d4d5 (diff) | |
download | chrome-ec-firmware-fpmcu-dartmonkey-release.tar.gz |
Merge remote-tracking branch cros/main into firmware-fpmcu-dartmonkey-releasefirmware-fpmcu-dartmonkey-release
Generated by: ./util/update_release_branch.py --board dartmonkey --relevant_paths_file
./util/fingerprint-relevant-paths.txt firmware-fpmcu-dartmonkey-release
Relevant changes:
git log --oneline 6c1587ca70..28712dae9d -- board/nocturne_fp
board/dartmonkey common/fpsensor docs/fingerprint driver/fingerprint
util/getversion.sh
ded9307b79 util/getversion.sh: Fix version when not in a git repo
956055e692 board: change Google USB vendor info
71b2ef709d Update license boilerplate text in source code files
33e11afda0 Revert "fpsensor: Build fpsensor source file with C++"
c8d0360723 fpsensor: Build fpsensor source file with C++
bc113abd53 fpsensor: Fix g++ compiler error
150a58a0dc fpsensor: Fix fp_set_sensor_mode return type
b33b5ce85b fpsensor: Remove nested designators for C++ compatibility
2e864b2539 tree-wide: const-ify argv for console commands
56d8b360f9 test: Add test for get ikm failure when seed not set
3a3d6c3690 test: Add test for fpsensor trivial key failure
233e6bbd08 fpsensor_crypto: Abstract calls to hmac_SHA256
0a041b285b docs/fingerprint: Typo correction
c03fab67e2 docs/fingerprint: Fix the path of fputils.py
0b5d4baf5a util/getversion.sh: Fix empty file list handling
6e128fe760 FPMCU dev board environment with Satlab
3eb29b6aa5 builtin: Move ssize_t to sys/types.h
345d62ebd1 docs/fingerprint: Update power numbers for latest dartmonkey release
c25ffdb316 common: Conditionally support printf %l and %i modifiers
9a3c514b45 test: Add a test to check if the debugger is connected
54e603413f Move standard library tests to their own file
43fa6b4bf8 docs/fingerprint: Update power numbers for latest bloonchipper release
25536f9a84 driver/fingerprint/fpc/bep/fpc_sensor_spi.c: Format with clang-format
4face99efd driver/fingerprint/fpc/libfp/fpc_sensor_pal.h: Format with clang-format
738de2b575 trng: Rename rand to trng_rand
14b8270edd docs/fingerprint: Update dragonclaw power numbers
0b268f93d1 driver/fingerprint/fpc/libfp/fpc_private.c: Format with clang-format
f80da163f2 driver/fingerprint/fpc/libfp/fpc_private.h: Format with clang-format
a0751778f4 board/nocturne_fp/ro_workarounds.c: Format with clang-format
5e9c85c9b1 driver/fingerprint/fpc/libfp/fpc_sensor_pal.c: Format with clang-format
c1f9dd3cf8 driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h: Format with clang-format
eb1e1bed8d driver/fingerprint/fpc/libfp/fpc1145_private.h: Format with clang-format
6e7b611821 driver/fingerprint/fpc/bep/fpc_bio_algorithm.h: Format with clang-format
e0589cd5e2 driver/fingerprint/fpc/bep/fpc1035_private.h: Format with clang-format
58f0246dbe board/nocturne_fp/board_ro.c: Format with clang-format
7905e556a0 common/fpsensor/fpsensor_crypto.c: Format with clang-format
21289d170c driver/fingerprint/fpc/bep/fpc1025_private.h: Format with clang-format
98a20f937e common/fpsensor/fpsensor_state.c: Format with clang-format
a2d255d8af common/fpsensor/fpsensor.c: Format with clang-format
84e53a65da board/nocturne_fp/board.h: Format with clang-format
73055eeb3f driver/fingerprint/fpc/bep/fpc_private.c: Format with clang-format
0f7b5cb509 common/fpsensor/fpsensor_private.h: Format with clang-format
1ceade6e65 driver/fingerprint/fpc/bep/fpc_private.h: Format with clang-format
dca9d74321 Revert "trng: Rename rand to trng_rand"
a6b0b3554f trng: Rename rand to trng_rand
28d0b75b70 third_party/boringssl: Remove unused header
BRANCH=None
BUG=b:244387210 b:242720240 b:215613183 b:242720910 b:236386294
BUG=b:234181908 b:244781166 b:234781655 b:234143158 b:234181908
BUG=b:237344361 b:236025198 b:234181908 b:180945056 chromium:1098010
BUG=b:246424843 b:234181908 b:131913998
TEST=`make -j buildall`
TEST=./util/run_device_tests.py --board dartmonkey
Test "aes": PASSED
Test "cec": PASSED
Test "cortexm_fpu": PASSED
Test "crc": PASSED
Test "flash_physical": PASSED
Test "flash_write_protect": PASSED
Test "fpsensor_hw": PASSED
Test "fpsensor_spi_ro": PASSED
Test "fpsensor_spi_rw": PASSED
Test "fpsensor_uart_ro": PASSED
Test "fpsensor_uart_rw": PASSED
Test "mpu_ro": PASSED
Test "mpu_rw": PASSED
Test "mutex": PASSED
Test "pingpong": PASSED
Test "printf": PASSED
Test "queue": PASSED
Test "rollback_region0": PASSED
Test "rollback_region1": PASSED
Test "rollback_entropy": PASSED
Test "rtc": PASSED
Test "sha256": PASSED
Test "sha256_unrolled": PASSED
Test "static_if": PASSED
Test "stdlib": PASSED
Test "system_is_locked_wp_on": PASSED
Test "system_is_locked_wp_off": PASSED
Test "timer_dos": PASSED
Test "utils": PASSED
Test "utils_str": PASSED
Test "panic_data_dartmonkey_v2.0.2887": PASSED
Test "panic_data_nocturne_fp_v2.2.64": PASSED
Test "panic_data_nami_fp_v2.2.144": PASSED
Force-Relevant-Builds: all
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I2c312583a709fedae8fe11d92c22328c3b634bc7
Diffstat (limited to 'chip/max32660/tmr_regs.h')
-rw-r--r-- | chip/max32660/tmr_regs.h | 310 |
1 files changed, 171 insertions, 139 deletions
diff --git a/chip/max32660/tmr_regs.h b/chip/max32660/tmr_regs.h index 946cacbc50..ab3ac5c5ed 100644 --- a/chip/max32660/tmr_regs.h +++ b/chip/max32660/tmr_regs.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -42,11 +42,11 @@ extern "C" { * Structure type to access the TMR Registers. */ typedef struct { - __IO uint32_t cnt; /**< <tt>\b 0x00:<\tt> TMR CNT Register */ - __IO uint32_t cmp; /**< <tt>\b 0x04:<\tt> TMR CMP Register */ - __IO uint32_t pwm; /**< <tt>\b 0x08:<\tt> TMR PWM Register */ - __IO uint32_t intr; /**< <tt>\b 0x0C:<\tt> TMR INTR Register */ - __IO uint32_t cn; /**< <tt>\b 0x10:<\tt> TMR CN Register */ + __IO uint32_t cnt; /**< <tt>\b 0x00:<\tt> TMR CNT Register */ + __IO uint32_t cmp; /**< <tt>\b 0x04:<\tt> TMR CMP Register */ + __IO uint32_t pwm; /**< <tt>\b 0x08:<\tt> TMR PWM Register */ + __IO uint32_t intr; /**< <tt>\b 0x0C:<\tt> TMR INTR Register */ + __IO uint32_t cn; /**< <tt>\b 0x10:<\tt> TMR CN Register */ __IO uint32_t nolcmp; /**< <tt>\b 0x14:<\tt> TMR NOLCMP Register */ } mxc_tmr_regs_t; @@ -54,23 +54,23 @@ typedef struct { * TMR Peripheral Register Offsets from the TMR Base Peripheral * Address. */ -#define MXC_R_TMR_CNT \ - ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: <tt> \ +#define MXC_R_TMR_CNT \ + ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: <tt> \ 0x0x000 */ -#define MXC_R_TMR_CMP \ - ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: <tt> \ +#define MXC_R_TMR_CMP \ + ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: <tt> \ 0x0x004 */ -#define MXC_R_TMR_PWM \ - ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: <tt> \ +#define MXC_R_TMR_PWM \ + ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: <tt> \ 0x0x008 */ -#define MXC_R_TMR_INTR \ - ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: <tt> \ +#define MXC_R_TMR_INTR \ + ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: <tt> \ 0x0x00C */ -#define MXC_R_TMR_CN \ - ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: <tt> \ +#define MXC_R_TMR_CN \ + ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: <tt> \ 0x0x010 */ -#define MXC_R_TMR_NOLCMP \ - ((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: <tt> \ +#define MXC_R_TMR_NOLCMP \ + ((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: <tt> \ 0x0x014 */ /** @@ -78,199 +78,231 @@ typedef struct { * clears the associated interrupt. */ #define MXC_F_TMR_INTR_IRQ_CLR_POS 0 /**< INTR_IRQ_CLR Position */ -#define MXC_F_TMR_INTR_IRQ_CLR \ - ((uint32_t)(0x1UL \ - << MXC_F_TMR_INTR_IRQ_CLR_POS)) /**< INTR_IRQ_CLR Mask */ +#define MXC_F_TMR_INTR_IRQ_CLR \ + ((uint32_t)(0x1UL << MXC_F_TMR_INTR_IRQ_CLR_POS)) /**< INTR_IRQ_CLR \ + Mask */ /** * Timer Control Register. */ #define MXC_F_TMR_CN_TMODE_POS 0 /**< CN_TMODE Position */ -#define MXC_F_TMR_CN_TMODE \ +#define MXC_F_TMR_CN_TMODE \ ((uint32_t)(0x7UL << MXC_F_TMR_CN_TMODE_POS)) /**< CN_TMODE Mask */ -#define MXC_V_TMR_CN_TMODE_ONESHOT \ +#define MXC_V_TMR_CN_TMODE_ONESHOT \ ((uint32_t)0x0UL) /**< CN_TMODE_ONESHOT Value */ -#define MXC_S_TMR_CN_TMODE_ONESHOT \ - (MXC_V_TMR_CN_TMODE_ONESHOT \ - << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_ONESHOT Setting */ -#define MXC_V_TMR_CN_TMODE_CONTINUOUS \ +#define MXC_S_TMR_CN_TMODE_ONESHOT \ + (MXC_V_TMR_CN_TMODE_ONESHOT \ + << MXC_F_TMR_CN_TMODE_POS) /**< \ + CN_TMODE_ONESHOT \ + Setting */ +#define MXC_V_TMR_CN_TMODE_CONTINUOUS \ ((uint32_t)0x1UL) /**< CN_TMODE_CONTINUOUS Value */ -#define MXC_S_TMR_CN_TMODE_CONTINUOUS \ - (MXC_V_TMR_CN_TMODE_CONTINUOUS \ - << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CONTINUOUS Setting */ -#define MXC_V_TMR_CN_TMODE_COUNTER \ +#define MXC_S_TMR_CN_TMODE_CONTINUOUS \ + (MXC_V_TMR_CN_TMODE_CONTINUOUS \ + << MXC_F_TMR_CN_TMODE_POS) /**< \ + CN_TMODE_CONTINUOUS \ + Setting \ + */ +#define MXC_V_TMR_CN_TMODE_COUNTER \ ((uint32_t)0x2UL) /**< CN_TMODE_COUNTER Value */ -#define MXC_S_TMR_CN_TMODE_COUNTER \ - (MXC_V_TMR_CN_TMODE_COUNTER \ - << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COUNTER Setting */ +#define MXC_S_TMR_CN_TMODE_COUNTER \ + (MXC_V_TMR_CN_TMODE_COUNTER \ + << MXC_F_TMR_CN_TMODE_POS) /**< \ + CN_TMODE_COUNTER \ + Setting */ #define MXC_V_TMR_CN_TMODE_PWM ((uint32_t)0x3UL) /**< CN_TMODE_PWM Value */ -#define MXC_S_TMR_CN_TMODE_PWM \ - (MXC_V_TMR_CN_TMODE_PWM \ - << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_PWM Setting */ -#define MXC_V_TMR_CN_TMODE_CAPTURE \ +#define MXC_S_TMR_CN_TMODE_PWM \ + (MXC_V_TMR_CN_TMODE_PWM << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_PWM \ + Setting */ +#define MXC_V_TMR_CN_TMODE_CAPTURE \ ((uint32_t)0x4UL) /**< CN_TMODE_CAPTURE Value */ -#define MXC_S_TMR_CN_TMODE_CAPTURE \ - (MXC_V_TMR_CN_TMODE_CAPTURE \ - << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURE Setting */ -#define MXC_V_TMR_CN_TMODE_COMPARE \ +#define MXC_S_TMR_CN_TMODE_CAPTURE \ + (MXC_V_TMR_CN_TMODE_CAPTURE \ + << MXC_F_TMR_CN_TMODE_POS) /**< \ + CN_TMODE_CAPTURE \ + Setting */ +#define MXC_V_TMR_CN_TMODE_COMPARE \ ((uint32_t)0x5UL) /**< CN_TMODE_COMPARE Value */ -#define MXC_S_TMR_CN_TMODE_COMPARE \ - (MXC_V_TMR_CN_TMODE_COMPARE \ - << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COMPARE Setting */ -#define MXC_V_TMR_CN_TMODE_GATED \ - ((uint32_t)0x6UL) /**< CN_TMODE_GATED Value \ +#define MXC_S_TMR_CN_TMODE_COMPARE \ + (MXC_V_TMR_CN_TMODE_COMPARE \ + << MXC_F_TMR_CN_TMODE_POS) /**< \ + CN_TMODE_COMPARE \ + Setting */ +#define MXC_V_TMR_CN_TMODE_GATED \ + ((uint32_t)0x6UL) /**< CN_TMODE_GATED Value \ */ #define MXC_S_TMR_CN_TMODE_GATED \ - (MXC_V_TMR_CN_TMODE_GATED \ - << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_GATED Setting */ -#define MXC_V_TMR_CN_TMODE_CAPTURECOMPARE \ + (MXC_V_TMR_CN_TMODE_GATED << MXC_F_TMR_CN_TMODE_POS) /**< \ + CN_TMODE_GATED \ + Setting */ +#define MXC_V_TMR_CN_TMODE_CAPTURECOMPARE \ ((uint32_t)0x7UL) /**< CN_TMODE_CAPTURECOMPARE Value */ -#define MXC_S_TMR_CN_TMODE_CAPTURECOMPARE \ - (MXC_V_TMR_CN_TMODE_CAPTURECOMPARE \ - << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURECOMPARE Setting */ +#define MXC_S_TMR_CN_TMODE_CAPTURECOMPARE \ + (MXC_V_TMR_CN_TMODE_CAPTURECOMPARE \ + << MXC_F_TMR_CN_TMODE_POS) /**< \ + CN_TMODE_CAPTURECOMPARE \ + Setting \ + */ #define MXC_F_TMR_CN_PRES_POS 3 /**< CN_PRES Position */ -#define MXC_F_TMR_CN_PRES \ +#define MXC_F_TMR_CN_PRES \ ((uint32_t)(0x7UL << MXC_F_TMR_CN_PRES_POS)) /**< CN_PRES Mask */ -#define MXC_V_TMR_CN_PRES_DIV1 ((uint32_t)0x0UL) /**< CN_PRES_DIV1 Value */ -#define MXC_S_TMR_CN_PRES_DIV1 \ - (MXC_V_TMR_CN_PRES_DIV1 \ - << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV1 Setting */ +#define MXC_V_TMR_CN_PRES_DIV1 ((uint32_t)0x0UL) /**< CN_PRES_DIV1 Value */ +#define MXC_S_TMR_CN_PRES_DIV1 \ + (MXC_V_TMR_CN_PRES_DIV1 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV1 \ + Setting */ #define MXC_V_TMR_CN_PRES_DIV2 ((uint32_t)0x1UL) /**< CN_PRES_DIV2 Value */ -#define MXC_S_TMR_CN_PRES_DIV2 \ - (MXC_V_TMR_CN_PRES_DIV2 \ - << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV2 Setting */ +#define MXC_S_TMR_CN_PRES_DIV2 \ + (MXC_V_TMR_CN_PRES_DIV2 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV2 \ + Setting */ #define MXC_V_TMR_CN_PRES_DIV4 ((uint32_t)0x2UL) /**< CN_PRES_DIV4 Value */ -#define MXC_S_TMR_CN_PRES_DIV4 \ - (MXC_V_TMR_CN_PRES_DIV4 \ - << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV4 Setting */ +#define MXC_S_TMR_CN_PRES_DIV4 \ + (MXC_V_TMR_CN_PRES_DIV4 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV4 \ + Setting */ #define MXC_V_TMR_CN_PRES_DIV8 ((uint32_t)0x3UL) /**< CN_PRES_DIV8 Value */ -#define MXC_S_TMR_CN_PRES_DIV8 \ - (MXC_V_TMR_CN_PRES_DIV8 \ - << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV8 Setting */ +#define MXC_S_TMR_CN_PRES_DIV8 \ + (MXC_V_TMR_CN_PRES_DIV8 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV8 \ + Setting */ #define MXC_V_TMR_CN_PRES_DIV16 ((uint32_t)0x4UL) /**< CN_PRES_DIV16 Value */ -#define MXC_S_TMR_CN_PRES_DIV16 \ - (MXC_V_TMR_CN_PRES_DIV16 \ - << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV16 Setting */ +#define MXC_S_TMR_CN_PRES_DIV16 \ + (MXC_V_TMR_CN_PRES_DIV16 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV16 \ + Setting */ #define MXC_V_TMR_CN_PRES_DIV32 ((uint32_t)0x5UL) /**< CN_PRES_DIV32 Value */ -#define MXC_S_TMR_CN_PRES_DIV32 \ - (MXC_V_TMR_CN_PRES_DIV32 \ - << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV32 Setting */ +#define MXC_S_TMR_CN_PRES_DIV32 \ + (MXC_V_TMR_CN_PRES_DIV32 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV32 \ + Setting */ #define MXC_V_TMR_CN_PRES_DIV64 ((uint32_t)0x6UL) /**< CN_PRES_DIV64 Value */ -#define MXC_S_TMR_CN_PRES_DIV64 \ - (MXC_V_TMR_CN_PRES_DIV64 \ - << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV64 Setting */ -#define MXC_V_TMR_CN_PRES_DIV128 \ - ((uint32_t)0x7UL) /**< CN_PRES_DIV128 Value \ +#define MXC_S_TMR_CN_PRES_DIV64 \ + (MXC_V_TMR_CN_PRES_DIV64 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV64 \ + Setting */ +#define MXC_V_TMR_CN_PRES_DIV128 \ + ((uint32_t)0x7UL) /**< CN_PRES_DIV128 Value \ */ -#define MXC_S_TMR_CN_PRES_DIV128 \ - (MXC_V_TMR_CN_PRES_DIV128 \ - << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV128 Setting */ +#define MXC_S_TMR_CN_PRES_DIV128 \ + (MXC_V_TMR_CN_PRES_DIV128 << MXC_F_TMR_CN_PRES_POS) /**< \ + CN_PRES_DIV128 \ + Setting */ #define MXC_F_TMR_CN_TPOL_POS 6 /**< CN_TPOL Position */ -#define MXC_F_TMR_CN_TPOL \ +#define MXC_F_TMR_CN_TPOL \ ((uint32_t)(0x1UL << MXC_F_TMR_CN_TPOL_POS)) /**< CN_TPOL Mask */ -#define MXC_V_TMR_CN_TPOL_ACTIVEHI \ +#define MXC_V_TMR_CN_TPOL_ACTIVEHI \ ((uint32_t)0x0UL) /**< CN_TPOL_ACTIVEHI Value */ -#define MXC_S_TMR_CN_TPOL_ACTIVEHI \ - (MXC_V_TMR_CN_TPOL_ACTIVEHI \ - << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVEHI Setting */ -#define MXC_V_TMR_CN_TPOL_ACTIVELO \ +#define MXC_S_TMR_CN_TPOL_ACTIVEHI \ + (MXC_V_TMR_CN_TPOL_ACTIVEHI \ + << MXC_F_TMR_CN_TPOL_POS) /**< \ + CN_TPOL_ACTIVEHI \ + Setting */ +#define MXC_V_TMR_CN_TPOL_ACTIVELO \ ((uint32_t)0x1UL) /**< CN_TPOL_ACTIVELO Value */ -#define MXC_S_TMR_CN_TPOL_ACTIVELO \ - (MXC_V_TMR_CN_TPOL_ACTIVELO \ - << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVELO Setting */ +#define MXC_S_TMR_CN_TPOL_ACTIVELO \ + (MXC_V_TMR_CN_TPOL_ACTIVELO \ + << MXC_F_TMR_CN_TPOL_POS) /**< \ + CN_TPOL_ACTIVELO \ + Setting */ #define MXC_F_TMR_CN_TEN_POS 7 /**< CN_TEN Position */ -#define MXC_F_TMR_CN_TEN \ +#define MXC_F_TMR_CN_TEN \ ((uint32_t)(0x1UL << MXC_F_TMR_CN_TEN_POS)) /**< CN_TEN Mask */ -#define MXC_V_TMR_CN_TEN_DIS ((uint32_t)0x0UL) /**< CN_TEN_DIS Value */ +#define MXC_V_TMR_CN_TEN_DIS ((uint32_t)0x0UL) /**< CN_TEN_DIS Value */ #define MXC_S_TMR_CN_TEN_DIS \ - (MXC_V_TMR_CN_TEN_DIS \ - << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_DIS Setting */ + (MXC_V_TMR_CN_TEN_DIS << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_DIS Setting \ + */ #define MXC_V_TMR_CN_TEN_EN ((uint32_t)0x1UL) /**< CN_TEN_EN Value */ -#define MXC_S_TMR_CN_TEN_EN \ - (MXC_V_TMR_CN_TEN_EN << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_EN Setting \ +#define MXC_S_TMR_CN_TEN_EN \ + (MXC_V_TMR_CN_TEN_EN << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_EN Setting \ */ #define MXC_F_TMR_CN_PRES3_POS 8 /**< CN_PRES3 Position */ -#define MXC_F_TMR_CN_PRES3 \ +#define MXC_F_TMR_CN_PRES3 \ ((uint32_t)(0x1UL << MXC_F_TMR_CN_PRES3_POS)) /**< CN_PRES3 Mask */ #define MXC_F_TMR_CN_PWMSYNC_POS 9 /**< CN_PWMSYNC Position */ -#define MXC_F_TMR_CN_PWMSYNC \ - ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask \ +#define MXC_F_TMR_CN_PWMSYNC \ + ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask \ */ -#define MXC_V_TMR_CN_PWMSYNC_DIS \ - ((uint32_t)0x0UL) /**< CN_PWMSYNC_DIS Value \ +#define MXC_V_TMR_CN_PWMSYNC_DIS \ + ((uint32_t)0x0UL) /**< CN_PWMSYNC_DIS Value \ */ -#define MXC_S_TMR_CN_PWMSYNC_DIS \ - (MXC_V_TMR_CN_PWMSYNC_DIS \ - << MXC_F_TMR_CN_PWMSYNC_POS) /**< CN_PWMSYNC_DIS Setting */ +#define MXC_S_TMR_CN_PWMSYNC_DIS \ + (MXC_V_TMR_CN_PWMSYNC_DIS \ + << MXC_F_TMR_CN_PWMSYNC_POS) /**< \ + CN_PWMSYNC_DIS \ + Setting */ #define MXC_V_TMR_CN_PWMSYNC_EN ((uint32_t)0x1UL) /**< CN_PWMSYNC_EN Value */ #define MXC_S_TMR_CN_PWMSYNC_EN \ - (MXC_V_TMR_CN_PWMSYNC_EN \ - << MXC_F_TMR_CN_PWMSYNC_POS) /**< CN_PWMSYNC_EN Setting */ + (MXC_V_TMR_CN_PWMSYNC_EN << MXC_F_TMR_CN_PWMSYNC_POS) /**< \ + CN_PWMSYNC_EN \ + Setting */ #define MXC_F_TMR_CN_NOLHPOL_POS 10 /**< CN_NOLHPOL Position */ -#define MXC_F_TMR_CN_NOLHPOL \ - ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask \ +#define MXC_F_TMR_CN_NOLHPOL \ + ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask \ */ -#define MXC_V_TMR_CN_NOLHPOL_DIS \ - ((uint32_t)0x0UL) /**< CN_NOLHPOL_DIS Value \ +#define MXC_V_TMR_CN_NOLHPOL_DIS \ + ((uint32_t)0x0UL) /**< CN_NOLHPOL_DIS Value \ */ -#define MXC_S_TMR_CN_NOLHPOL_DIS \ - (MXC_V_TMR_CN_NOLHPOL_DIS \ - << MXC_F_TMR_CN_NOLHPOL_POS) /**< CN_NOLHPOL_DIS Setting */ +#define MXC_S_TMR_CN_NOLHPOL_DIS \ + (MXC_V_TMR_CN_NOLHPOL_DIS \ + << MXC_F_TMR_CN_NOLHPOL_POS) /**< \ + CN_NOLHPOL_DIS \ + Setting */ #define MXC_V_TMR_CN_NOLHPOL_EN ((uint32_t)0x1UL) /**< CN_NOLHPOL_EN Value */ #define MXC_S_TMR_CN_NOLHPOL_EN \ - (MXC_V_TMR_CN_NOLHPOL_EN \ - << MXC_F_TMR_CN_NOLHPOL_POS) /**< CN_NOLHPOL_EN Setting */ + (MXC_V_TMR_CN_NOLHPOL_EN << MXC_F_TMR_CN_NOLHPOL_POS) /**< \ + CN_NOLHPOL_EN \ + Setting */ #define MXC_F_TMR_CN_NOLLPOL_POS 11 /**< CN_NOLLPOL Position */ -#define MXC_F_TMR_CN_NOLLPOL \ - ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask \ +#define MXC_F_TMR_CN_NOLLPOL \ + ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask \ */ -#define MXC_V_TMR_CN_NOLLPOL_DIS \ - ((uint32_t)0x0UL) /**< CN_NOLLPOL_DIS Value \ +#define MXC_V_TMR_CN_NOLLPOL_DIS \ + ((uint32_t)0x0UL) /**< CN_NOLLPOL_DIS Value \ */ -#define MXC_S_TMR_CN_NOLLPOL_DIS \ - (MXC_V_TMR_CN_NOLLPOL_DIS \ - << MXC_F_TMR_CN_NOLLPOL_POS) /**< CN_NOLLPOL_DIS Setting */ +#define MXC_S_TMR_CN_NOLLPOL_DIS \ + (MXC_V_TMR_CN_NOLLPOL_DIS \ + << MXC_F_TMR_CN_NOLLPOL_POS) /**< \ + CN_NOLLPOL_DIS \ + Setting */ #define MXC_V_TMR_CN_NOLLPOL_EN ((uint32_t)0x1UL) /**< CN_NOLLPOL_EN Value */ #define MXC_S_TMR_CN_NOLLPOL_EN \ - (MXC_V_TMR_CN_NOLLPOL_EN \ - << MXC_F_TMR_CN_NOLLPOL_POS) /**< CN_NOLLPOL_EN Setting */ + (MXC_V_TMR_CN_NOLLPOL_EN << MXC_F_TMR_CN_NOLLPOL_POS) /**< \ + CN_NOLLPOL_EN \ + Setting */ #define MXC_F_TMR_CN_PWMCKBD_POS 12 /**< CN_PWMCKBD Position */ -#define MXC_F_TMR_CN_PWMCKBD \ - ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask \ +#define MXC_F_TMR_CN_PWMCKBD \ + ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask \ */ -#define MXC_V_TMR_CN_PWMCKBD_DIS \ - ((uint32_t)0x1UL) /**< CN_PWMCKBD_DIS Value \ +#define MXC_V_TMR_CN_PWMCKBD_DIS \ + ((uint32_t)0x1UL) /**< CN_PWMCKBD_DIS Value \ */ -#define MXC_S_TMR_CN_PWMCKBD_DIS \ - (MXC_V_TMR_CN_PWMCKBD_DIS \ - << MXC_F_TMR_CN_PWMCKBD_POS) /**< CN_PWMCKBD_DIS Setting */ +#define MXC_S_TMR_CN_PWMCKBD_DIS \ + (MXC_V_TMR_CN_PWMCKBD_DIS \ + << MXC_F_TMR_CN_PWMCKBD_POS) /**< \ + CN_PWMCKBD_DIS \ + Setting */ #define MXC_V_TMR_CN_PWMCKBD_EN ((uint32_t)0x0UL) /**< CN_PWMCKBD_EN Value */ #define MXC_S_TMR_CN_PWMCKBD_EN \ - (MXC_V_TMR_CN_PWMCKBD_EN \ - << MXC_F_TMR_CN_PWMCKBD_POS) /**< CN_PWMCKBD_EN Setting */ + (MXC_V_TMR_CN_PWMCKBD_EN << MXC_F_TMR_CN_PWMCKBD_POS) /**< \ + CN_PWMCKBD_EN \ + Setting */ /** * Timer Non-Overlapping Compare Register. */ #define MXC_F_TMR_NOLCMP_NOLLCMP_POS 0 /**< NOLCMP_NOLLCMP Position */ #define MXC_F_TMR_NOLCMP_NOLLCMP \ - ((uint32_t)( \ - 0xFFUL \ - << MXC_F_TMR_NOLCMP_NOLLCMP_POS)) /**< NOLCMP_NOLLCMP Mask */ + ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_NOLLCMP_POS)) /**< \ + NOLCMP_NOLLCMP \ + Mask */ #define MXC_F_TMR_NOLCMP_NOLHCMP_POS 8 /**< NOLCMP_NOLHCMP Position */ #define MXC_F_TMR_NOLCMP_NOLHCMP \ - ((uint32_t)( \ - 0xFFUL \ - << MXC_F_TMR_NOLCMP_NOLHCMP_POS)) /**< NOLCMP_NOLHCMP Mask */ + ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_NOLHCMP_POS)) /**< \ + NOLCMP_NOLHCMP \ + Mask */ #ifdef __cplusplus } |