Merge remote-tracking branch cros/main into firmware-fpmcu-dartmonkey-releasefirmware-fpmcu-dartmonkey-release

Generated by: ./util/update_release_branch.py --board dartmonkey --relevant_paths_file
./util/fingerprint-relevant-paths.txt firmware-fpmcu-dartmonkey-release

Relevant changes:

git log --oneline 6c1587ca70..28712dae9d -- board/nocturne_fp
board/dartmonkey common/fpsensor docs/fingerprint driver/fingerprint
util/getversion.sh

ded9307b79 util/getversion.sh: Fix version when not in a git repo
956055e692 board: change Google USB vendor info
71b2ef709d Update license boilerplate text in source code files
33e11afda0 Revert "fpsensor: Build fpsensor source file with C++"
c8d0360723 fpsensor: Build fpsensor source file with C++
bc113abd53 fpsensor: Fix g++ compiler error
150a58a0dc fpsensor: Fix fp_set_sensor_mode return type
b33b5ce85b fpsensor: Remove nested designators for C++ compatibility
2e864b2539 tree-wide: const-ify argv for console commands
56d8b360f9 test: Add test for get ikm failure when seed not set
3a3d6c3690 test: Add test for fpsensor trivial key failure
233e6bbd08 fpsensor_crypto: Abstract calls to hmac_SHA256
0a041b285b docs/fingerprint: Typo correction
c03fab67e2 docs/fingerprint: Fix the path of fputils.py
0b5d4baf5a util/getversion.sh: Fix empty file list handling
6e128fe760 FPMCU dev board environment with Satlab
3eb29b6aa5 builtin: Move ssize_t to sys/types.h
345d62ebd1 docs/fingerprint: Update power numbers for latest dartmonkey release
c25ffdb316 common: Conditionally support printf %l and %i modifiers
9a3c514b45 test: Add a test to check if the debugger is connected
54e603413f Move standard library tests to their own file
43fa6b4bf8 docs/fingerprint: Update power numbers for latest bloonchipper release
25536f9a84 driver/fingerprint/fpc/bep/fpc_sensor_spi.c: Format with clang-format
4face99efd driver/fingerprint/fpc/libfp/fpc_sensor_pal.h: Format with clang-format
738de2b575 trng: Rename rand to trng_rand
14b8270edd docs/fingerprint: Update dragonclaw power numbers
0b268f93d1 driver/fingerprint/fpc/libfp/fpc_private.c: Format with clang-format
f80da163f2 driver/fingerprint/fpc/libfp/fpc_private.h: Format with clang-format
a0751778f4 board/nocturne_fp/ro_workarounds.c: Format with clang-format
5e9c85c9b1 driver/fingerprint/fpc/libfp/fpc_sensor_pal.c: Format with clang-format
c1f9dd3cf8 driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h: Format with clang-format
eb1e1bed8d driver/fingerprint/fpc/libfp/fpc1145_private.h: Format with clang-format
6e7b611821 driver/fingerprint/fpc/bep/fpc_bio_algorithm.h: Format with clang-format
e0589cd5e2 driver/fingerprint/fpc/bep/fpc1035_private.h: Format with clang-format
58f0246dbe board/nocturne_fp/board_ro.c: Format with clang-format
7905e556a0 common/fpsensor/fpsensor_crypto.c: Format with clang-format
21289d170c driver/fingerprint/fpc/bep/fpc1025_private.h: Format with clang-format
98a20f937e common/fpsensor/fpsensor_state.c: Format with clang-format
a2d255d8af common/fpsensor/fpsensor.c: Format with clang-format
84e53a65da board/nocturne_fp/board.h: Format with clang-format
73055eeb3f driver/fingerprint/fpc/bep/fpc_private.c: Format with clang-format
0f7b5cb509 common/fpsensor/fpsensor_private.h: Format with clang-format
1ceade6e65 driver/fingerprint/fpc/bep/fpc_private.h: Format with clang-format
dca9d74321 Revert "trng: Rename rand to trng_rand"
a6b0b3554f trng: Rename rand to trng_rand
28d0b75b70 third_party/boringssl: Remove unused header

BRANCH=None
BUG=b:244387210 b:242720240 b:215613183 b:242720910 b:236386294
BUG=b:234181908 b:244781166 b:234781655 b:234143158 b:234181908
BUG=b:237344361 b:236025198 b:234181908 b:180945056 chromium:1098010
BUG=b:246424843 b:234181908 b:131913998
TEST=`make -j buildall`
TEST=./util/run_device_tests.py --board dartmonkey
     Test "aes": PASSED
     Test "cec": PASSED
     Test "cortexm_fpu": PASSED
     Test "crc": PASSED
     Test "flash_physical": PASSED
     Test "flash_write_protect": PASSED
     Test "fpsensor_hw": PASSED
     Test "fpsensor_spi_ro": PASSED
     Test "fpsensor_spi_rw": PASSED
     Test "fpsensor_uart_ro": PASSED
     Test "fpsensor_uart_rw": PASSED
     Test "mpu_ro": PASSED
     Test "mpu_rw": PASSED
     Test "mutex": PASSED
     Test "pingpong": PASSED
     Test "printf": PASSED
     Test "queue": PASSED
     Test "rollback_region0": PASSED
     Test "rollback_region1": PASSED
     Test "rollback_entropy": PASSED
     Test "rtc": PASSED
     Test "sha256": PASSED
     Test "sha256_unrolled": PASSED
     Test "static_if": PASSED
     Test "stdlib": PASSED
     Test "system_is_locked_wp_on": PASSED
     Test "system_is_locked_wp_off": PASSED
     Test "timer_dos": PASSED
     Test "utils": PASSED
     Test "utils_str": PASSED
     Test "panic_data_dartmonkey_v2.0.2887": PASSED
     Test "panic_data_nocturne_fp_v2.2.64": PASSED
     Test "panic_data_nami_fp_v2.2.144": PASSED
Force-Relevant-Builds: all
Signed-off-by: Tom Hughes <tomhughes@chromium.org>

Change-Id: I2c312583a709fedae8fe11d92c22328c3b634bc7

1 files changed, 40 insertions, 42 deletions

diff --git a/chip/mchp/config_chip.h b/chip/mchp/config_chip.h
index cf7ead512a..4d5836ef42 100644
--- a/chip/mchp/config_chip.h
+++ b/chip/mchp/config_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,11 +20,11 @@
 
 /* Use a bigger console output buffer */
 #undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE	1024
+#define CONFIG_UART_TX_BUF_SIZE 1024
 
 /* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS	250
-#define HOOK_TICK_INTERVAL	(HOOK_TICK_INTERVAL_MS * MSEC)
+#define HOOK_TICK_INTERVAL_MS 250
+#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
 
 /*
  * Enable chip_pre_init called from main
@@ -48,14 +48,14 @@
  * addresses. Define fake peripheral addresses that aren't used by
  * peripherals on the board.
  */
-#define CONFIG_MCHP_I2C0_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C1_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C2_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C3_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C4_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C5_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C6_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C7_SLAVE_ADDRS	0xE3E1
+#define CONFIG_MCHP_I2C0_SLAVE_ADDRS 0xE3E1
+#define CONFIG_MCHP_I2C1_SLAVE_ADDRS 0xE3E1
+#define CONFIG_MCHP_I2C2_SLAVE_ADDRS 0xE3E1
+#define CONFIG_MCHP_I2C3_SLAVE_ADDRS 0xE3E1
+#define CONFIG_MCHP_I2C4_SLAVE_ADDRS 0xE3E1
+#define CONFIG_MCHP_I2C5_SLAVE_ADDRS 0xE3E1
+#define CONFIG_MCHP_I2C6_SLAVE_ADDRS 0xE3E1
+#define CONFIG_MCHP_I2C7_SLAVE_ADDRS 0xE3E1
 
 /************************************************************************/
 /* Memory mapping */
@@ -74,45 +74,44 @@
 /* Define our RAM layout. */
 
 #if defined(CHIP_FAMILY_MEC172X)
-#define CONFIG_MEC_SRAM_BASE_START	0x000C0000
-#define CONFIG_MEC_SRAM_BASE_END	(0x00128000 - (2 * 1024))
+#define CONFIG_MEC_SRAM_BASE_START 0x000C0000
+#define CONFIG_MEC_SRAM_BASE_END (0x00128000 - (2 * 1024))
 #else
-#define CONFIG_MEC_SRAM_BASE_START	0x000E0000
-#define CONFIG_MEC_SRAM_BASE_END	0x00120000
+#define CONFIG_MEC_SRAM_BASE_START 0x000E0000
+#define CONFIG_MEC_SRAM_BASE_END 0x00120000
 #endif
 
-#define CONFIG_MEC_SRAM_SIZE		(CONFIG_MEC_SRAM_BASE_END - \
-					CONFIG_MEC_SRAM_BASE_START)
+#define CONFIG_MEC_SRAM_SIZE \
+	(CONFIG_MEC_SRAM_BASE_END - CONFIG_MEC_SRAM_BASE_START)
 /* 64k Data RAM for RO / RW / loader */
-#define CONFIG_RAM_SIZE			0x00010000
-#define CONFIG_RAM_BASE			(CONFIG_MEC_SRAM_BASE_END - \
-					CONFIG_RAM_SIZE)
+#define CONFIG_RAM_SIZE 0x00010000
+#define CONFIG_RAM_BASE (CONFIG_MEC_SRAM_BASE_END - CONFIG_RAM_SIZE)
 
 /* System stack size */
 /* was 1024, temporarily expanded to 2048 for debug */
-#define CONFIG_STACK_SIZE		2048
+#define CONFIG_STACK_SIZE 2048
 
 /* non-standard task stack sizes */
-#define IDLE_TASK_STACK_SIZE		672
-#define LARGER_TASK_STACK_SIZE		800
-#define VENTI_TASK_STACK_SIZE		928
-#define ULTRA_TASK_STACK_SIZE		1056
-#define TRENTA_TASK_STACK_SIZE		1184
+#define IDLE_TASK_STACK_SIZE 672
+#define LARGER_TASK_STACK_SIZE 800
+#define VENTI_TASK_STACK_SIZE 928
+#define ULTRA_TASK_STACK_SIZE 1056
+#define TRENTA_TASK_STACK_SIZE 1184
 
-#define CHARGER_TASK_STACK_SIZE		1024	/* 640 */
-#define HOOKS_TASK_STACK_SIZE		1024	/* 640 */
-#define CONSOLE_TASK_STACK_SIZE		1024	/* 640 */
-#define HOST_CMD_TASK_STACK_SIZE	1024	/* 640 */
+#define CHARGER_TASK_STACK_SIZE 1024 /* 640 */
+#define HOOKS_TASK_STACK_SIZE 1024 /* 640 */
+#define CONSOLE_TASK_STACK_SIZE 1024 /* 640 */
+#define HOST_CMD_TASK_STACK_SIZE 1024 /* 640 */
 
 /*
  * TODO: Large stack consumption
  * https://code.google.com/p/chrome-os-partner/issues/detail?id=49245
  */
 /* original = 800, if stack exceptions expand to 1024 for debug */
-#define PD_TASK_STACK_SIZE		2048
+#define PD_TASK_STACK_SIZE 2048
 
 /* Default task stack size */
-#define TASK_STACK_SIZE			672
+#define TASK_STACK_SIZE 672
 
 /************************************************************************/
 /* Define our flash layout. */
@@ -134,20 +133,20 @@
 #endif
 
 /* Protect bank size 4K bytes */
-#define CONFIG_FLASH_BANK_SIZE		0x00001000
+#define CONFIG_FLASH_BANK_SIZE 0x00001000
 /* Sector erase size 4K bytes */
-#define CONFIG_FLASH_ERASE_SIZE		0x00001000
+#define CONFIG_FLASH_ERASE_SIZE 0x00001000
 /* Minimum write size */
-#define CONFIG_FLASH_WRITE_SIZE		0x00000004
+#define CONFIG_FLASH_WRITE_SIZE 0x00000004
 
 /* One page size for write */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE	256
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256
 
 /* Program memory base address */
 #if defined(CHIP_FAMILY_MEC172X)
-#define CONFIG_PROGRAM_MEMORY_BASE	0x000C0000
+#define CONFIG_PROGRAM_MEMORY_BASE 0x000C0000
 #else
-#define CONFIG_PROGRAM_MEMORY_BASE	0x000E0000
+#define CONFIG_PROGRAM_MEMORY_BASE 0x000E0000
 #endif
 
 /*
@@ -232,14 +231,13 @@
  * GPIO(PCH_SLP_S0_L, PIN(0x89), GPIO_INPUT | GPIO_PULL_DOWN)
  */
 #define GPIO_BANK(index) ((index) >> 5)
-#define GPIO_BANK_MASK(index) (1ul << ((index) & 0x1F))
+#define GPIO_BANK_MASK(index) (1ul << ((index)&0x1F))
 
 #define GPIO_PIN(index) GPIO_BANK(index), GPIO_BANK_MASK(index)
 #define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m)
 
 #ifndef __ASSEMBLER__
 
-
 #endif /* #ifndef __ASSEMBLER__ */
 
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
+#endif /* __CROS_EC_CONFIG_CHIP_H */