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| author | Leifu Zhao <leifu.zhao@intel.com> | 2020-02-14 10:20:52 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-02-27 00:29:03 +0000 |
| commit | e225427d2a04449d65fbae72932caa8270f182c7 (patch) | |
| tree | 3eda9062fb68d8d243aee5969a430cd84d8a57ae /core | |
| parent | af07a29b0ab75abc03d6d6387257981bd10447b2 (diff) | |
| download | chrome-ec-e225427d2a04449d65fbae72932caa8270f182c7.tar.gz | |
ish: infrastructure changes to support ish5.4 PM
Infrastructure related changes to support enabling power management
for ish5.4 on tgl rvp platform.
BUG=b:149238813
BRANCH=none
TEST=ISH can successfully enter into D0i1/D0i2/D0i3 on tgl rvp.
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
Change-Id: I50b6f1a4fe9c14f9479af2a2a438ec7395ec27a1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2056149
Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Diffstat (limited to 'core')
| -rw-r--r-- | core/minute-ia/interrupts.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/core/minute-ia/interrupts.c b/core/minute-ia/interrupts.c index 714fde239e..3dbb4f85fe 100644 --- a/core/minute-ia/interrupts.c +++ b/core/minute-ia/interrupts.c @@ -151,7 +151,7 @@ static const irq_desc_t system_irqs[] = { LEVEL_INTR(ISH_HPET_TIMER1_IRQ, ISH_HPET_TIMER1_VEC), LEVEL_INTR(ISH_DEBUG_UART_IRQ, ISH_DEBUG_UART_VEC), LEVEL_INTR(ISH_FABRIC_IRQ, ISH_FABRIC_VEC), -#if defined(CONFIG_ISH_PM_RESET_PREP) || defined(CHIP_VARIANT_ISH5P4) +#ifdef CONFIG_ISH_PM_RESET_PREP LEVEL_INTR(ISH_RESET_PREP_IRQ, ISH_RESET_PREP_VEC), #endif #ifdef CONFIG_ISH_PM_D0I1 @@ -159,10 +159,12 @@ static const irq_desc_t system_irqs[] = { #endif #ifdef CONFIG_ISH_PM_D3 LEVEL_INTR(ISH_D3_RISE_IRQ, ISH_D3_RISE_VEC), +#ifndef CONFIG_ISH_NEW_PM LEVEL_INTR(ISH_D3_FALL_IRQ, ISH_D3_FALL_VEC), LEVEL_INTR(ISH_BME_RISE_IRQ, ISH_BME_RISE_VEC), LEVEL_INTR(ISH_BME_FALL_IRQ, ISH_BME_FALL_VEC) #endif +#endif }; /** |