diff options
author | Tom Hughes <tomhughes@chromium.org> | 2022-09-21 14:08:36 -0700 |
---|---|---|
committer | Tom Hughes <tomhughes@chromium.org> | 2022-09-22 12:59:38 -0700 |
commit | c453fd704268ef72de871b0c5ac7a989de662334 (patch) | |
tree | fcf6ce5810f9ff9e3c8cce434812dd75492269ed /driver/tcpm/ps8xxx.h | |
parent | 6c1587ca70f558b4f96b3f0b18ad8b027d3ba99d (diff) | |
parent | 28712dae9d7ed1e694f7622cc083afa71090d4d5 (diff) | |
download | chrome-ec-firmware-fpmcu-dartmonkey-release.tar.gz |
Merge remote-tracking branch cros/main into firmware-fpmcu-dartmonkey-releasefirmware-fpmcu-dartmonkey-release
Generated by: ./util/update_release_branch.py --board dartmonkey --relevant_paths_file
./util/fingerprint-relevant-paths.txt firmware-fpmcu-dartmonkey-release
Relevant changes:
git log --oneline 6c1587ca70..28712dae9d -- board/nocturne_fp
board/dartmonkey common/fpsensor docs/fingerprint driver/fingerprint
util/getversion.sh
ded9307b79 util/getversion.sh: Fix version when not in a git repo
956055e692 board: change Google USB vendor info
71b2ef709d Update license boilerplate text in source code files
33e11afda0 Revert "fpsensor: Build fpsensor source file with C++"
c8d0360723 fpsensor: Build fpsensor source file with C++
bc113abd53 fpsensor: Fix g++ compiler error
150a58a0dc fpsensor: Fix fp_set_sensor_mode return type
b33b5ce85b fpsensor: Remove nested designators for C++ compatibility
2e864b2539 tree-wide: const-ify argv for console commands
56d8b360f9 test: Add test for get ikm failure when seed not set
3a3d6c3690 test: Add test for fpsensor trivial key failure
233e6bbd08 fpsensor_crypto: Abstract calls to hmac_SHA256
0a041b285b docs/fingerprint: Typo correction
c03fab67e2 docs/fingerprint: Fix the path of fputils.py
0b5d4baf5a util/getversion.sh: Fix empty file list handling
6e128fe760 FPMCU dev board environment with Satlab
3eb29b6aa5 builtin: Move ssize_t to sys/types.h
345d62ebd1 docs/fingerprint: Update power numbers for latest dartmonkey release
c25ffdb316 common: Conditionally support printf %l and %i modifiers
9a3c514b45 test: Add a test to check if the debugger is connected
54e603413f Move standard library tests to their own file
43fa6b4bf8 docs/fingerprint: Update power numbers for latest bloonchipper release
25536f9a84 driver/fingerprint/fpc/bep/fpc_sensor_spi.c: Format with clang-format
4face99efd driver/fingerprint/fpc/libfp/fpc_sensor_pal.h: Format with clang-format
738de2b575 trng: Rename rand to trng_rand
14b8270edd docs/fingerprint: Update dragonclaw power numbers
0b268f93d1 driver/fingerprint/fpc/libfp/fpc_private.c: Format with clang-format
f80da163f2 driver/fingerprint/fpc/libfp/fpc_private.h: Format with clang-format
a0751778f4 board/nocturne_fp/ro_workarounds.c: Format with clang-format
5e9c85c9b1 driver/fingerprint/fpc/libfp/fpc_sensor_pal.c: Format with clang-format
c1f9dd3cf8 driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h: Format with clang-format
eb1e1bed8d driver/fingerprint/fpc/libfp/fpc1145_private.h: Format with clang-format
6e7b611821 driver/fingerprint/fpc/bep/fpc_bio_algorithm.h: Format with clang-format
e0589cd5e2 driver/fingerprint/fpc/bep/fpc1035_private.h: Format with clang-format
58f0246dbe board/nocturne_fp/board_ro.c: Format with clang-format
7905e556a0 common/fpsensor/fpsensor_crypto.c: Format with clang-format
21289d170c driver/fingerprint/fpc/bep/fpc1025_private.h: Format with clang-format
98a20f937e common/fpsensor/fpsensor_state.c: Format with clang-format
a2d255d8af common/fpsensor/fpsensor.c: Format with clang-format
84e53a65da board/nocturne_fp/board.h: Format with clang-format
73055eeb3f driver/fingerprint/fpc/bep/fpc_private.c: Format with clang-format
0f7b5cb509 common/fpsensor/fpsensor_private.h: Format with clang-format
1ceade6e65 driver/fingerprint/fpc/bep/fpc_private.h: Format with clang-format
dca9d74321 Revert "trng: Rename rand to trng_rand"
a6b0b3554f trng: Rename rand to trng_rand
28d0b75b70 third_party/boringssl: Remove unused header
BRANCH=None
BUG=b:244387210 b:242720240 b:215613183 b:242720910 b:236386294
BUG=b:234181908 b:244781166 b:234781655 b:234143158 b:234181908
BUG=b:237344361 b:236025198 b:234181908 b:180945056 chromium:1098010
BUG=b:246424843 b:234181908 b:131913998
TEST=`make -j buildall`
TEST=./util/run_device_tests.py --board dartmonkey
Test "aes": PASSED
Test "cec": PASSED
Test "cortexm_fpu": PASSED
Test "crc": PASSED
Test "flash_physical": PASSED
Test "flash_write_protect": PASSED
Test "fpsensor_hw": PASSED
Test "fpsensor_spi_ro": PASSED
Test "fpsensor_spi_rw": PASSED
Test "fpsensor_uart_ro": PASSED
Test "fpsensor_uart_rw": PASSED
Test "mpu_ro": PASSED
Test "mpu_rw": PASSED
Test "mutex": PASSED
Test "pingpong": PASSED
Test "printf": PASSED
Test "queue": PASSED
Test "rollback_region0": PASSED
Test "rollback_region1": PASSED
Test "rollback_entropy": PASSED
Test "rtc": PASSED
Test "sha256": PASSED
Test "sha256_unrolled": PASSED
Test "static_if": PASSED
Test "stdlib": PASSED
Test "system_is_locked_wp_on": PASSED
Test "system_is_locked_wp_off": PASSED
Test "timer_dos": PASSED
Test "utils": PASSED
Test "utils_str": PASSED
Test "panic_data_dartmonkey_v2.0.2887": PASSED
Test "panic_data_nocturne_fp_v2.2.64": PASSED
Test "panic_data_nami_fp_v2.2.144": PASSED
Force-Relevant-Builds: all
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I2c312583a709fedae8fe11d92c22328c3b634bc7
Diffstat (limited to 'driver/tcpm/ps8xxx.h')
-rw-r--r-- | driver/tcpm/ps8xxx.h | 125 |
1 files changed, 65 insertions, 60 deletions
diff --git a/driver/tcpm/ps8xxx.h b/driver/tcpm/ps8xxx.h index eeddd22640..7d873abc85 100644 --- a/driver/tcpm/ps8xxx.h +++ b/driver/tcpm/ps8xxx.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,67 +11,67 @@ #ifndef __CROS_EC_USB_PD_TCPM_PS8XXX_H #define __CROS_EC_USB_PD_TCPM_PS8XXX_H -#define PS8751_P3_TO_P0_FLAGS(p3_flags) ((p3_flags) - 3) -#define PS8751_P3_TO_P1_FLAGS(p3_flags) ((p3_flags) - 2) +#define PS8751_P3_TO_P0_FLAGS(p3_flags) ((p3_flags)-3) +#define PS8751_P3_TO_P1_FLAGS(p3_flags) ((p3_flags)-2) -#define PS8751_BIST_TIMER_FREQ 15000000 -#define PS8751_BIST_DELAY_MS 50 +#define PS8751_BIST_TIMER_FREQ 15000000 +#define PS8751_BIST_DELAY_MS 50 -#define PS8751_BIST_COUNTER (PS8751_BIST_TIMER_FREQ / MSEC \ - * PS8751_BIST_DELAY_MS) +#define PS8751_BIST_COUNTER \ + (PS8751_BIST_TIMER_FREQ / MSEC * PS8751_BIST_DELAY_MS) #define PS8751_BIST_COUNTER_BYTE0 (PS8751_BIST_COUNTER & 0xff) #define PS8751_BIST_COUNTER_BYTE1 ((PS8751_BIST_COUNTER >> 8) & 0xff) #define PS8751_BIST_COUNTER_BYTE2 ((PS8751_BIST_COUNTER >> 16) & 0xff) -#define PS8XXX_REG_RP_DETECT_CONTROL 0x9B -#define RP_DETECT_DISABLE 0x30 +#define PS8XXX_REG_RP_DETECT_CONTROL 0x9B +#define RP_DETECT_DISABLE 0x30 -#define PS8XXX_REG_I2C_DEBUGGING_ENABLE 0xA0 -#define PS8XXX_REG_I2C_DEBUGGING_ENABLE_ON 0x30 -#define PS8XXX_REG_I2C_DEBUGGING_ENABLE_OFF 0x31 /* default */ -#define PS8XXX_REG_BIST_CONT_MODE_BYTE0 0xBC -#define PS8XXX_REG_BIST_CONT_MODE_BYTE1 0xBD -#define PS8XXX_REG_BIST_CONT_MODE_BYTE2 0xBE -#define PS8XXX_REG_BIST_CONT_MODE_CTR 0xBF -#define PS8XXX_REG_DET_CTRL0 0x08 +#define PS8XXX_REG_I2C_DEBUGGING_ENABLE 0xA0 +#define PS8XXX_REG_I2C_DEBUGGING_ENABLE_ON 0x30 +#define PS8XXX_REG_I2C_DEBUGGING_ENABLE_OFF 0x31 /* default */ +#define PS8XXX_REG_BIST_CONT_MODE_BYTE0 0xBC +#define PS8XXX_REG_BIST_CONT_MODE_BYTE1 0xBD +#define PS8XXX_REG_BIST_CONT_MODE_BYTE2 0xBE +#define PS8XXX_REG_BIST_CONT_MODE_CTR 0xBF +#define PS8XXX_REG_DET_CTRL0 0x08 -#define PS8XXX_REG_MUX_USB_DCI_CFG_MODE_MASK 0xC0 -#define PS8XXX_REG_MUX_USB_DCI_CFG_MODE_OFF 0x80 +#define PS8XXX_REG_MUX_USB_DCI_CFG_MODE_MASK 0xC0 +#define PS8XXX_REG_MUX_USB_DCI_CFG_MODE_OFF 0x80 -#define MUX_IN_HPD_ASSERTION_REG 0xD0 -#define IN_HPD BIT(0) +#define MUX_IN_HPD_ASSERTION_REG 0xD0 +#define IN_HPD BIT(0) #define HPD_IRQ BIT(1) -#define PS8XXX_P1_REG_MUX_USB_DCI_CFG 0x4B +#define PS8XXX_P1_REG_MUX_USB_DCI_CFG 0x4B -#define PS8755_P0_REG_SM 0x06 -#define PS8755_P0_REG_SM_VALUE 0x80 +#define PS8755_P0_REG_SM 0x06 +#define PS8755_P0_REG_SM_VALUE 0x80 #if defined(CONFIG_USB_PD_TCPM_PS8751) /* Vendor defined registers */ -#define PS8XXX_REG_VENDOR_ID_L 0x00 -#define PS8XXX_REG_VENDOR_ID_H 0x01 -#define PS8XXX_REG_MUX_DP_EQ_CONFIGURATION 0xD3 -#define PS8XXX_REG_MUX_DP_OUTPUT_CONFIGURATION 0xD4 -#define PS8XXX_REG_MUX_USB_C2SS_EQ 0xE7 -#define PS8XXX_REG_MUX_USB_C2SS_HS_THRESHOLD 0xE8 -#define PS8751_REG_MUX_USB_DCI_CFG 0xED +#define PS8XXX_REG_VENDOR_ID_L 0x00 +#define PS8XXX_REG_VENDOR_ID_H 0x01 +#define PS8XXX_REG_MUX_DP_EQ_CONFIGURATION 0xD3 +#define PS8XXX_REG_MUX_DP_OUTPUT_CONFIGURATION 0xD4 +#define PS8XXX_REG_MUX_USB_C2SS_EQ 0xE7 +#define PS8XXX_REG_MUX_USB_C2SS_HS_THRESHOLD 0xE8 +#define PS8751_REG_MUX_USB_DCI_CFG 0xED #endif /* Vendor defined registers */ -#define PS8815_P1_REG_HW_REVISION 0xF0 +#define PS8815_P1_REG_HW_REVISION 0xF0 /* Vendor defined registers */ -#define PS8815_REG_APTX_EQ_AT_10G 0x20 -#define PS8815_REG_RX_EQ_AT_10G 0x22 -#define PS8815_REG_APTX_EQ_AT_5G 0x24 -#define PS8815_REG_RX_EQ_AT_5G 0x26 +#define PS8815_REG_APTX_EQ_AT_10G 0x20 +#define PS8815_REG_RX_EQ_AT_10G 0x22 +#define PS8815_REG_APTX_EQ_AT_5G 0x24 +#define PS8815_REG_RX_EQ_AT_5G 0x26 -#define PS8815_REG_RESERVED_D1 0xD1 -#define PS8815_REG_RESERVED_D1_FRS_EN BIT(7) -#define PS8815_REG_RESERVED_F4 0xF4 -#define PS8815_REG_RESERVED_F4_FRS_EN BIT(6) +#define PS8815_REG_RESERVED_D1 0xD1 +#define PS8815_REG_RESERVED_D1_FRS_EN BIT(7) +#define PS8815_REG_RESERVED_F4 0xF4 +#define PS8815_REG_RESERVED_F4_FRS_EN BIT(6) /* * Below register is defined from Parade PS8815 Register Table, @@ -79,37 +79,42 @@ */ /* Displayport related settings */ -#define PS8815_REG_DP_EQ_SETTING 0xF8 -#define PS8815_AUTO_EQ_DISABLE BIT(7) -#define PS8815_DPEQ_LOSS_UP_21DB 0x09 -#define PS8815_DPEQ_LOSS_UP_20DB 0x08 -#define PS8815_DPEQ_LOSS_UP_19DB 0x07 -#define PS8815_DPEQ_LOSS_UP_18DB 0x06 -#define PS8815_DPEQ_LOSS_UP_17DB 0x05 -#define PS8815_DPEQ_LOSS_UP_16DB 0x04 -#define PS8815_DPEQ_LOSS_UP_13DB 0x03 -#define PS8815_DPEQ_LOSS_UP_12DB 0x02 -#define PS8815_DPEQ_LOSS_UP_10DB 0x01 -#define PS8815_DPEQ_LOSS_UP_9DB 0x00 -#define PS8815_REG_DP_EQ_COMP_SHIFT 3 -#define PS8815_AUX_INTERCEPTION_DISABLE BIT(1) +#define PS8815_REG_DP_EQ_SETTING 0xF8 +#define PS8815_AUTO_EQ_DISABLE BIT(7) +#define PS8815_DPEQ_LOSS_UP_21DB 0x09 +#define PS8815_DPEQ_LOSS_UP_20DB 0x08 +#define PS8815_DPEQ_LOSS_UP_19DB 0x07 +#define PS8815_DPEQ_LOSS_UP_18DB 0x06 +#define PS8815_DPEQ_LOSS_UP_17DB 0x05 +#define PS8815_DPEQ_LOSS_UP_16DB 0x04 +#define PS8815_DPEQ_LOSS_UP_13DB 0x03 +#define PS8815_DPEQ_LOSS_UP_12DB 0x02 +#define PS8815_DPEQ_LOSS_UP_10DB 0x01 +#define PS8815_DPEQ_LOSS_UP_9DB 0x00 +#define PS8815_REG_DP_EQ_COMP_SHIFT 3 +#define PS8815_AUX_INTERCEPTION_DISABLE BIT(1) /* * PS8805 register to distinguish chip revision * bit 7-4: 1010b is A3 chip, 0000b is A2 chip */ -#define PS8805_P0_REG_CHIP_REVISION 0x62 +#define PS8805_P0_REG_CHIP_REVISION 0x62 +/* + * PS8815 register to differentiate with PS8745: bit 1 = 0 is a PS8815-A2, + * 1 is a PS8745-A2. + */ +#define PS8815_P0_REG_ID 0x2C /* * PS8805 GPIO control register. Note the device I2C address of 0x1A is * independent of the ADDR pin on the chip, and not the same address being used * for TCPCI functions. */ -#define PS8805_VENDOR_DEFINED_I2C_ADDR 0x1A -#define PS8805_REG_GPIO_CONTROL 0x21 -#define PS8805_REG_GPIO_0 BIT(7) -#define PS8805_REG_GPIO_1 BIT(5) -#define PS8805_REG_GPIO_2 BIT(6) +#define PS8805_VENDOR_DEFINED_I2C_ADDR 0x1A +#define PS8805_REG_GPIO_CONTROL 0x21 +#define PS8805_REG_GPIO_0 BIT(7) +#define PS8805_REG_GPIO_1 BIT(5) +#define PS8805_REG_GPIO_2 BIT(6) enum ps8805_gpio { PS8805_GPIO_0, |