diff options
Diffstat (limited to 'baseboard/intelrvp')
| -rw-r--r-- | baseboard/intelrvp/adlrvp.c | 176 | ||||
| -rw-r--r-- | baseboard/intelrvp/adlrvp.h | 68 | ||||
| -rw-r--r-- | baseboard/intelrvp/adlrvp_battery.c | 2 | ||||
| -rw-r--r-- | baseboard/intelrvp/adlrvp_ioex_gpio.inc | 2 | ||||
| -rw-r--r-- | baseboard/intelrvp/baseboard.c | 16 | ||||
| -rw-r--r-- | baseboard/intelrvp/baseboard.h | 58 | ||||
| -rw-r--r-- | baseboard/intelrvp/build.mk | 2 | ||||
| -rw-r--r-- | baseboard/intelrvp/chg_usb_pd.c | 25 | ||||
| -rw-r--r-- | baseboard/intelrvp/chg_usb_pd_mecc_1_0.c | 12 | ||||
| -rw-r--r-- | baseboard/intelrvp/ite_ec.c | 12 | ||||
| -rw-r--r-- | baseboard/intelrvp/ite_ec.h | 14 | ||||
| -rw-r--r-- | baseboard/intelrvp/led.c | 60 | ||||
| -rw-r--r-- | baseboard/intelrvp/led_states.c | 34 | ||||
| -rw-r--r-- | baseboard/intelrvp/led_states.h | 22 | ||||
| -rw-r--r-- | baseboard/intelrvp/mchp_ec.c | 2 | ||||
| -rw-r--r-- | baseboard/intelrvp/mchp_ec.h | 10 | ||||
| -rw-r--r-- | baseboard/intelrvp/npcx_ec.c | 2 | ||||
| -rw-r--r-- | baseboard/intelrvp/npcx_ec.h | 18 | ||||
| -rw-r--r-- | baseboard/intelrvp/usb_pd_policy_mecc_1_0.c | 6 |
19 files changed, 277 insertions, 264 deletions
diff --git a/baseboard/intelrvp/adlrvp.c b/baseboard/intelrvp/adlrvp.c index 4d97418d23..6f301be986 100644 --- a/baseboard/intelrvp/adlrvp.c +++ b/baseboard/intelrvp/adlrvp.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -26,8 +26,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args) +#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ##args) /* TCPC AIC GPIO Configuration */ const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[] = { @@ -93,94 +93,123 @@ BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == CONFIG_USB_PD_PORT_MAX_COUNT); unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); /* USB-C retimer Configuration */ -struct usb_mux usbc0_tcss_usb_mux = { +struct usb_mux bb_retimer0_usb_mux = { .usb_port = TYPE_C_PORT_0, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, + .driver = &bb_usb_retimer, + .hpd_update = bb_retimer_hpd_update, + .i2c_port = I2C_PORT_TYPEC_0, + .i2c_addr_flags = I2C_PORT0_BB_RETIMER_ADDR, +}; +struct usb_mux_chain usbc0_tcss_usb_mux = { + .mux = + &(const struct usb_mux){ + .usb_port = TYPE_C_PORT_0, + .driver = &virtual_usb_mux_driver, + .hpd_update = &virtual_hpd_update, + }, }; #if defined(HAS_TASK_PD_C1) -struct usb_mux usbc1_tcss_usb_mux = { +struct usb_mux bb_retimer1_usb_mux = { .usb_port = TYPE_C_PORT_1, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, + .driver = &bb_usb_retimer, + .hpd_update = bb_retimer_hpd_update, + .i2c_port = I2C_PORT_TYPEC_1, + .i2c_addr_flags = I2C_PORT1_BB_RETIMER_ADDR, +}; +struct usb_mux_chain usbc1_tcss_usb_mux = { + .mux = + &(const struct usb_mux){ + .usb_port = TYPE_C_PORT_1, + .driver = &virtual_usb_mux_driver, + .hpd_update = &virtual_hpd_update, + }, }; #endif #if defined(HAS_TASK_PD_C2) -struct usb_mux usbc2_tcss_usb_mux = { +struct usb_mux bb_retimer2_usb_mux = { .usb_port = TYPE_C_PORT_2, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, + .driver = &bb_usb_retimer, + .hpd_update = bb_retimer_hpd_update, + .i2c_port = I2C_PORT_TYPEC_2, + .i2c_addr_flags = I2C_PORT2_BB_RETIMER_ADDR, +}; +struct usb_mux_chain usbc2_tcss_usb_mux = { + .mux = + &(const struct usb_mux){ + .usb_port = TYPE_C_PORT_2, + .driver = &virtual_usb_mux_driver, + .hpd_update = &virtual_hpd_update, + }, }; #endif #if defined(HAS_TASK_PD_C3) -struct usb_mux usbc3_tcss_usb_mux = { - .usb_port = TYPE_C_PORT_3, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, +struct usb_mux_chain usbc3_tcss_usb_mux = { + .mux = + &(const struct usb_mux){ + .usb_port = TYPE_C_PORT_3, + .driver = &virtual_usb_mux_driver, + .hpd_update = &virtual_hpd_update, + }, }; #endif /* USB muxes Configuration */ -struct usb_mux usb_muxes[] = { +struct usb_mux_chain usb_muxes[] = { [TYPE_C_PORT_0] = { - .usb_port = TYPE_C_PORT_0, - .next_mux = &usbc0_tcss_usb_mux, - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_TYPEC_0, - .i2c_addr_flags = I2C_PORT0_BB_RETIMER_ADDR, + .mux = &bb_retimer0_usb_mux, + .next = &usbc0_tcss_usb_mux, }, #if defined(HAS_TASK_PD_C1) [TYPE_C_PORT_1] = { - .usb_port = TYPE_C_PORT_1, - .next_mux = &usbc1_tcss_usb_mux, - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_TYPEC_1, - .i2c_addr_flags = I2C_PORT1_BB_RETIMER_ADDR, + .mux = &bb_retimer1_usb_mux, + .next = &usbc1_tcss_usb_mux, }, #endif #if defined(HAS_TASK_PD_C2) [TYPE_C_PORT_2] = { - .usb_port = TYPE_C_PORT_2, - .next_mux = &usbc2_tcss_usb_mux, - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_TYPEC_2, - .i2c_addr_flags = I2C_PORT2_BB_RETIMER_ADDR, + .mux = &bb_retimer2_usb_mux, + .next = &usbc2_tcss_usb_mux, }, #endif #if defined(HAS_TASK_PD_C3) [TYPE_C_PORT_3] = { - .usb_port = TYPE_C_PORT_3, - .next_mux = &usbc3_tcss_usb_mux, - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_TYPEC_3, - .i2c_addr_flags = I2C_PORT3_BB_RETIMER_ADDR, + .mux = &(const struct usb_mux) { + .usb_port = TYPE_C_PORT_3, + .driver = &bb_usb_retimer, + .hpd_update = bb_retimer_hpd_update, + .i2c_port = I2C_PORT_TYPEC_3, + .i2c_addr_flags = I2C_PORT3_BB_RETIMER_ADDR, + }, + .next = &usbc3_tcss_usb_mux, }, #endif }; BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT); /* USB Mux Configuration for Soc side BB-Retimers for Dual retimer config */ -struct usb_mux soc_side_bb_retimer0_usb_mux = { - .usb_port = TYPE_C_PORT_0, - .next_mux = &usbc0_tcss_usb_mux, - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_TYPEC_0, - .i2c_addr_flags = I2C_PORT0_BB_RETIMER_SOC_ADDR, +struct usb_mux_chain soc_side_bb_retimer0_usb_mux = { + .mux = + &(const struct usb_mux){ + .usb_port = TYPE_C_PORT_0, + .driver = &bb_usb_retimer, + .hpd_update = bb_retimer_hpd_update, + .i2c_port = I2C_PORT_TYPEC_0, + .i2c_addr_flags = I2C_PORT0_BB_RETIMER_SOC_ADDR, + }, + .next = &usbc0_tcss_usb_mux, }; #if defined(HAS_TASK_PD_C1) -struct usb_mux soc_side_bb_retimer1_usb_mux = { - .usb_port = TYPE_C_PORT_1, - .next_mux = &usbc1_tcss_usb_mux, - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_TYPEC_1, - .i2c_addr_flags = I2C_PORT1_BB_RETIMER_SOC_ADDR, +struct usb_mux_chain soc_side_bb_retimer1_usb_mux = { + .mux = + &(const struct usb_mux){ + .usb_port = TYPE_C_PORT_1, + .driver = &bb_usb_retimer, + .hpd_update = bb_retimer_hpd_update, + .i2c_port = I2C_PORT_TYPEC_1, + .i2c_addr_flags = I2C_PORT1_BB_RETIMER_SOC_ADDR, + }, + .next = &usbc1_tcss_usb_mux, }; #endif @@ -253,8 +282,8 @@ void board_overcurrent_event(int port, int is_overcurrented) { /* Port 0 & 1 and 2 & 3 share same line for over current indication */ #if defined(HAS_TASK_PD_C2) - enum ioex_signal oc_signal = port < TYPE_C_PORT_2 ? - IOEX_USB_C0_C1_OC : IOEX_USB_C2_C3_OC; + enum ioex_signal oc_signal = port < TYPE_C_PORT_2 ? IOEX_USB_C0_C1_OC : + IOEX_USB_C2_C3_OC; #else enum ioex_signal oc_signal = IOEX_USB_C0_C1_OC; #endif @@ -340,11 +369,11 @@ void set_charger_system_voltage(void) * on AC or AC+battery */ if (extpower_is_present() && battery_is_present()) { - bq25710_set_min_system_voltage(CHARGER_SOLO, - battery_get_info()->voltage_min); + bq25710_set_min_system_voltage( + CHARGER_SOLO, battery_get_info()->voltage_min); } else { - bq25710_set_min_system_voltage(CHARGER_SOLO, - battery_get_info()->voltage_max); + bq25710_set_min_system_voltage( + CHARGER_SOLO, battery_get_info()->voltage_max); } break; @@ -353,8 +382,7 @@ void set_charger_system_voltage(void) break; } } -DECLARE_HOOK(HOOK_AC_CHANGE, set_charger_system_voltage, - HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_AC_CHANGE, set_charger_system_voltage, HOOK_PRIO_DEFAULT); static void configure_charger(void) { @@ -379,22 +407,20 @@ static void configure_retimer_usbmux(void) case ADLN_LP5_ERB_SKU_BOARD_ID: case ADLN_LP5_RVP_SKU_BOARD_ID: /* enable TUSB1044RNQR redriver on Port0 */ - usb_muxes[TYPE_C_PORT_0].i2c_addr_flags = - TUSB1064_I2C_ADDR14_FLAGS; - usb_muxes[TYPE_C_PORT_0].driver = - &tusb1064_usb_mux_driver; - usb_muxes[TYPE_C_PORT_0].hpd_update = tusb1044_hpd_update; + bb_retimer0_usb_mux.i2c_addr_flags = TUSB1064_I2C_ADDR14_FLAGS; + bb_retimer0_usb_mux.driver = &tusb1064_usb_mux_driver; + bb_retimer0_usb_mux.hpd_update = tusb1044_hpd_update; #if defined(HAS_TASK_PD_C1) - usb_muxes[TYPE_C_PORT_1].driver = NULL; - usb_muxes[TYPE_C_PORT_1].hpd_update = NULL; + bb_retimer1_usb_mux.driver = NULL; + bb_retimer1_usb_mux.hpd_update = NULL; #endif break; case ADLP_LP5_T4_RVP_SKU_BOARD_ID: /* No retimer on Port-2 */ #if defined(HAS_TASK_PD_C2) - usb_muxes[TYPE_C_PORT_2].driver = NULL; + bb_retimer2_usb_mux.driver = NULL; #endif break; @@ -404,15 +430,13 @@ static void configure_retimer_usbmux(void) * Change the default usb mux config on runtime to support * dual retimer topology. */ - usb_muxes[TYPE_C_PORT_0].next_mux - = &soc_side_bb_retimer0_usb_mux; + usb_muxes[TYPE_C_PORT_0].next = &soc_side_bb_retimer0_usb_mux; #if defined(HAS_TASK_PD_C1) - usb_muxes[TYPE_C_PORT_1].next_mux - = &soc_side_bb_retimer1_usb_mux; + usb_muxes[TYPE_C_PORT_1].next = &soc_side_bb_retimer1_usb_mux; #endif break; - /* Add additional board SKUs */ + /* Add additional board SKUs */ default: break; diff --git a/baseboard/intelrvp/adlrvp.h b/baseboard/intelrvp/adlrvp.h index 9e7db0081c..3e062db223 100644 --- a/baseboard/intelrvp/adlrvp.h +++ b/baseboard/intelrvp/adlrvp.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -15,14 +15,14 @@ /* RVP Board ids */ #define CONFIG_BOARD_VERSION_GPIO -#define ADLM_LP4_RVP1_SKU_BOARD_ID 0x01 -#define ADLM_LP5_RVP2_SKU_BOARD_ID 0x02 -#define ADLM_LP5_RVP3_SKU_BOARD_ID 0x03 -#define ADLN_LP5_ERB_SKU_BOARD_ID 0x06 -#define ADLN_LP5_RVP_SKU_BOARD_ID 0x07 -#define ADLP_DDR5_RVP_SKU_BOARD_ID 0x12 -#define ADLP_LP5_T4_RVP_SKU_BOARD_ID 0x13 -#define ADL_RVP_BOARD_ID(id) ((id) & 0x3F) +#define ADLM_LP4_RVP1_SKU_BOARD_ID 0x01 +#define ADLM_LP5_RVP2_SKU_BOARD_ID 0x02 +#define ADLM_LP5_RVP3_SKU_BOARD_ID 0x03 +#define ADLN_LP5_ERB_SKU_BOARD_ID 0x06 +#define ADLN_LP5_RVP_SKU_BOARD_ID 0x07 +#define ADLP_DDR5_RVP_SKU_BOARD_ID 0x12 +#define ADLP_LP5_T4_RVP_SKU_BOARD_ID 0x13 +#define ADL_RVP_BOARD_ID(id) ((id)&0x3F) /* MECC config */ #define CONFIG_INTEL_RVP_MECC_VERSION_1_0 @@ -35,8 +35,8 @@ /* ADL has new low-power features that require extra-wide virtual wire * pulses. The EDS specifies 100 microseconds. */ -#undef CONFIG_ESPI_DEFAULT_VW_WIDTH_US -#define CONFIG_ESPI_DEFAULT_VW_WIDTH_US 100 +#undef CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US +#define CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US 100 /* USB PD config */ #if defined(HAS_TASK_PD_C3) @@ -50,7 +50,7 @@ #endif #define CONFIG_USB_MUX_VIRTUAL #define CONFIG_USB_MUX_TUSB1044 -#define PD_MAX_POWER_MW 100000 +#define PD_MAX_POWER_MW 100000 #define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY @@ -58,10 +58,10 @@ /* Support NXP PCA9675 I/O expander. */ #define CONFIG_IO_EXPANDER #define CONFIG_IO_EXPANDER_PCA9675 -#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX 0x21 +#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX 0x21 /* DC Jack charge ports */ -#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT +#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT #define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1 #define DEDICATED_CHARGE_PORT CONFIG_USB_PD_PORT_MAX_COUNT @@ -69,38 +69,38 @@ #define CONFIG_USBC_PPC_SN5S330 #define CONFIG_USB_PD_VBUS_DETECT_PPC #define CONFIG_USB_PD_DISCHARGE_PPC -#define I2C_ADDR_SN5S330_TCPC_AIC_PPC 0x40 +#define I2C_ADDR_SN5S330_TCPC_AIC_PPC 0x40 /* TCPC */ #define CONFIG_USB_PD_DISCHARGE #define CONFIG_USB_PD_TCPM_FUSB302 -#define I2C_ADDR_FUSB302_TCPC_AIC 0x22 +#define I2C_ADDR_FUSB302_TCPC_AIC 0x22 /* Config BB retimer */ #define CONFIG_USBC_RETIMER_INTEL_BB #define CONFIG_USBC_RETIMER_FW_UPDATE /* Connector side BB retimers */ -#define I2C_PORT0_BB_RETIMER_ADDR 0x56 +#define I2C_PORT0_BB_RETIMER_ADDR 0x56 #if defined(HAS_TASK_PD_C1) -#define I2C_PORT1_BB_RETIMER_ADDR 0x57 +#define I2C_PORT1_BB_RETIMER_ADDR 0x57 #endif #if defined(HAS_TASK_PD_C2) -#define I2C_PORT2_BB_RETIMER_ADDR 0x58 +#define I2C_PORT2_BB_RETIMER_ADDR 0x58 #endif #if defined(HAS_TASK_PD_C3) -#define I2C_PORT3_BB_RETIMER_ADDR 0x59 +#define I2C_PORT3_BB_RETIMER_ADDR 0x59 #endif /* SOC side BB retimers (dual retimer config) */ -#define I2C_PORT0_BB_RETIMER_SOC_ADDR 0x54 +#define I2C_PORT0_BB_RETIMER_SOC_ADDR 0x54 #if defined(HAS_TASK_PD_C1) -#define I2C_PORT1_BB_RETIMER_SOC_ADDR 0x55 +#define I2C_PORT1_BB_RETIMER_SOC_ADDR 0x55 #endif /* I2C EEPROM */ -#define I2C_ADDR_EEPROM_FLAGS 0x50 -#define I2C_PORT_EEPROM I2C_PORT_PCA9555_BOARD_ID_GPIO +#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_PORT_EEPROM I2C_PORT_PCA9555_BOARD_ID_GPIO /* Enable CBI */ #define CONFIG_CBI_EEPROM @@ -122,9 +122,9 @@ #define CONFIG_USB_PD_TCPC_LOW_POWER /* Config Fan */ -#define CONFIG_FANS 1 -#define BOARD_FAN_MIN_RPM 3000 -#define BOARD_FAN_MAX_RPM 10000 +#define CONFIG_FANS 1 +#define BOARD_FAN_MIN_RPM 3000 +#define BOARD_FAN_MAX_RPM 10000 /* Charger Configs */ #define CONFIG_CHARGER_RUNTIME_CONFIG @@ -133,15 +133,15 @@ /* Charger chip on ADL-N */ #define CONFIG_CHARGER_BQ25720 #define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM -#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70 -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 /* Port 80 */ -#define PORT80_I2C_ADDR MAX695X_I2C_ADDR1_FLAGS +#define PORT80_I2C_ADDR MAX695X_I2C_ADDR1_FLAGS /* Board Id */ -#define I2C_ADDR_PCA9555_BOARD_ID_GPIO 0x22 +#define I2C_ADDR_PCA9555_BOARD_ID_GPIO 0x22 /* * Frequent watchdog timer resets are seen, with the @@ -160,7 +160,7 @@ * Support for EC_CMD_BATTERY_GET_STATIC version 1. */ #define CONFIG_BATTERY_V2 -#define CONFIG_BATTERY_COUNT 1 +#define CONFIG_BATTERY_COUNT 1 #define CONFIG_HOSTCMD_BATTERY_V2 /* Config to indicate battery type doesn't auto detect */ @@ -210,7 +210,7 @@ enum adlrvp_bitbang_i2c_channel { I2C_BITBANG_CHAN_IOEX_0, I2C_BITBANG_CHAN_COUNT }; -#define I2C_BITBANG_PORT_COUNT I2C_BITBANG_CHAN_COUNT +#define I2C_BITBANG_PORT_COUNT I2C_BITBANG_CHAN_COUNT void espi_reset_pin_asserted_interrupt(enum gpio_signal signal); void extpower_interrupt(enum gpio_signal signal); diff --git a/baseboard/intelrvp/adlrvp_battery.c b/baseboard/intelrvp/adlrvp_battery.c index e5bf95827e..f7107cb1a4 100644 --- a/baseboard/intelrvp/adlrvp_battery.c +++ b/baseboard/intelrvp/adlrvp_battery.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/baseboard/intelrvp/adlrvp_ioex_gpio.inc b/baseboard/intelrvp/adlrvp_ioex_gpio.inc index 4519d3d853..b62dcf53a3 100644 --- a/baseboard/intelrvp/adlrvp_ioex_gpio.inc +++ b/baseboard/intelrvp/adlrvp_ioex_gpio.inc @@ -1,6 +1,6 @@ /* -*- mode:c -*- * - * Copyright 2021 The Chromium OS Authors. All rights reserved. + * Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/intelrvp/baseboard.c b/baseboard/intelrvp/baseboard.c index 87b43f2297..e1e0a06943 100644 --- a/baseboard/intelrvp/baseboard.c +++ b/baseboard/intelrvp/baseboard.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -86,14 +86,12 @@ const static struct ec_thermal_config thermal_a = { }; struct ec_thermal_config thermal_params[] = { - [TEMP_SNS_AMBIENT] = thermal_a, - [TEMP_SNS_BATTERY] = thermal_a, + [TEMP_SNS_AMBIENT] = thermal_a, [TEMP_SNS_BATTERY] = thermal_a, [TEMP_SNS_DDR] = thermal_a, #ifdef CONFIG_PECI [TEMP_SNS_PECI] = thermal_a, #endif - [TEMP_SNS_SKIN] = thermal_a, - [TEMP_SNS_VR] = thermal_a, + [TEMP_SNS_SKIN] = thermal_a, [TEMP_SNS_VR] = thermal_a, }; BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT); #endif /* CONFIG_TEMP_SENSOR */ @@ -144,12 +142,12 @@ int ioexpander_read_intelrvp_version(int *port0, int *port1) for (i = 0; i < RVP_VERSION_READ_RETRY_CNT; i++) { rv = pca9555_read(I2C_PORT_PCA9555_BOARD_ID_GPIO, - I2C_ADDR_PCA9555_BOARD_ID_GPIO, - PCA9555_CMD_INPUT_PORT_0, port0); + I2C_ADDR_PCA9555_BOARD_ID_GPIO, + PCA9555_CMD_INPUT_PORT_0, port0); if (!rv && !pca9555_read(I2C_PORT_PCA9555_BOARD_ID_GPIO, - I2C_ADDR_PCA9555_BOARD_ID_GPIO, - PCA9555_CMD_INPUT_PORT_1, port1)) + I2C_ADDR_PCA9555_BOARD_ID_GPIO, + PCA9555_CMD_INPUT_PORT_1, port1)) return 0; msleep(1); diff --git a/baseboard/intelrvp/baseboard.h b/baseboard/intelrvp/baseboard.h index 9b497568e7..b927632fc5 100644 --- a/baseboard/intelrvp/baseboard.h +++ b/baseboard/intelrvp/baseboard.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,22 +12,27 @@ #include "stdbool.h" #ifdef VARIANT_INTELRVP_EC_IT8320 - #include "ite_ec.h" +#include "ite_ec.h" #elif defined(VARIANT_INTELRVP_EC_MCHP) - #include "mchp_ec.h" +#include "mchp_ec.h" #elif defined(VARIANT_INTELRVP_EC_NPCX) - #include "npcx_ec.h" +#include "npcx_ec.h" #else - #error "Define EC chip variant" +#error "Define EC chip variant" #endif /* + * TODO: b/241322365 - Watchdog error are observed if LTO is enabled + * hence disabled it. Enable LTO once the fix is found. + */ + +/* * Allow dangerous commands. * TODO: Remove this config before production. */ #define CONFIG_SYSTEM_UNLOCKED -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) #undef CONFIG_HOSTCMD_DEBUG_MODE /* @@ -51,7 +56,7 @@ #define CONFIG_MAX695X_SEVEN_SEGMENT_DISPLAY /* RVP ID read retry count */ -#define RVP_VERSION_READ_RETRY_CNT 2 +#define RVP_VERSION_READ_RETRY_CNT 2 /* Battery */ #define CONFIG_BATTERY_CUT_OFF @@ -66,7 +71,7 @@ #define CONFIG_CHARGER_INPUT_CURRENT 512 #define CONFIG_CHARGER_SENSE_RESISTOR 5 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 -#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#undef CONFIG_EXTPOWER_DEBOUNCE_MS #define CONFIG_EXTPOWER_DEBOUNCE_MS 200 #define CONFIG_EXTPOWER_GPIO #define CONFIG_TRICKLE_CHARGING @@ -75,8 +80,8 @@ * Don't allow the system to boot to S0 when the battery is low and unable to * communicate on locked systems (which haven't PD negotiated) */ -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001 /* Keyboard */ @@ -109,16 +114,16 @@ /* USB MUX */ #ifdef CONFIG_USB_MUX_VIRTUAL - #define CONFIG_HOSTCMD_LOCATE_CHIP +#define CONFIG_HOSTCMD_LOCATE_CHIP #endif #define CONFIG_USBC_SS_MUX /* SoC / PCH */ #define CONFIG_CHIPSET_RESET_HOOK #define CONFIG_HOST_INTERFACE_ESPI -#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3 -#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4 -#define CONFIG_HOSTCMD_ESPI_VW_SLP_S5 +#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3 +#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4 +#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5 #define CONFIG_MKBP_EVENT #define CONFIG_MKBP_USE_HOST_EVENT #define CONFIG_POWER_BUTTON @@ -152,13 +157,13 @@ /* Temperature sensor */ #ifdef CONFIG_TEMP_SENSOR - #define CONFIG_STEINHART_HART_3V0_22K6_47K_4050B - #define CONFIG_TEMP_SENSOR_POWER - #define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300_A - #define CONFIG_THERMISTOR - #define CONFIG_THROTTLE_AP +#define CONFIG_STEINHART_HART_3V0_22K6_47K_4050B +#define CONFIG_TEMP_SENSOR_POWER +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300_A +#define CONFIG_THERMISTOR +#define CONFIG_THROTTLE_AP #ifdef CONFIG_PECI - #define CONFIG_PECI_COMMON +#define CONFIG_PECI_COMMON #endif /* CONFIG_PECI */ #endif /* CONFIG_TEMP_SENSOR */ @@ -177,10 +182,7 @@ FORWARD_DECLARE_ENUM(tcpc_rp_value); /* PWM channels */ -enum pwm_channel { - PWM_CH_FAN, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_FAN, PWM_CH_COUNT }; /* FAN channels */ enum fan_channel { @@ -211,13 +213,13 @@ enum temp_sensor_id { }; /* TODO(b:132652892): Verify the below numbers. */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* Define typical operating power */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_VOLTAGE_MV 20000 -#define PD_MAX_CURRENT_MA ((PD_MAX_POWER_MW/PD_MAX_VOLTAGE_MV) * 1000) +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_VOLTAGE_MV 20000 +#define PD_MAX_CURRENT_MA ((PD_MAX_POWER_MW / PD_MAX_VOLTAGE_MV) * 1000) #define DC_JACK_MAX_VOLTAGE_MV 19000 /* TCPC gpios */ diff --git a/baseboard/intelrvp/build.mk b/baseboard/intelrvp/build.mk index 21b4a7b0ec..b4cacf4cc2 100644 --- a/baseboard/intelrvp/build.mk +++ b/baseboard/intelrvp/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2018 The Chromium OS Authors. All rights reserved. +# Copyright 2018 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/baseboard/intelrvp/chg_usb_pd.c b/baseboard/intelrvp/chg_usb_pd.c index 1eb82b6688..95aeea0441 100644 --- a/baseboard/intelrvp/chg_usb_pd.c +++ b/baseboard/intelrvp/chg_usb_pd.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -15,8 +15,8 @@ #include "intelrvp.h" #endif /* CONFIG_ZEPHYR */ -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) bool is_typec_port(int port) { @@ -43,8 +43,8 @@ static void board_dc_jack_handle(void) /* System is booted from DC Jack */ if (board_dc_jack_present()) { - charge_dc_jack.current = (PD_MAX_POWER_MW * 1000) / - DC_JACK_MAX_VOLTAGE_MV; + charge_dc_jack.current = + (PD_MAX_POWER_MW * 1000) / DC_JACK_MAX_VOLTAGE_MV; charge_dc_jack.voltage = DC_JACK_MAX_VOLTAGE_MV; } else { charge_dc_jack.current = 0; @@ -52,7 +52,7 @@ static void board_dc_jack_handle(void) } charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED, - DEDICATED_CHARGE_PORT, &charge_dc_jack); + DEDICATED_CHARGE_PORT, &charge_dc_jack); } #endif @@ -75,7 +75,7 @@ static void board_charge_init(void) for (port = 0; port < CHARGE_PORT_COUNT; port++) { for (supplier = 0; supplier < CHARGE_SUPPLIER_COUNT; supplier++) charge_manager_update_charge(supplier, port, - &charge_init); + &charge_init); } #if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 @@ -88,8 +88,7 @@ int board_set_active_charge_port(int port) { int i; /* charge port is a realy physical port */ - int is_real_port = (port >= 0 && - port < CHARGE_PORT_COUNT); + int is_real_port = (port >= 0 && port < CHARGE_PORT_COUNT); /* check if we are source vbus on that port */ int source = board_vbus_source_enabled(port); @@ -127,9 +126,9 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } diff --git a/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c b/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c index 38bd3cef9e..cbc61e8402 100644 --- a/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c +++ b/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,8 +19,8 @@ #include "intelrvp.h" #endif /* CONFIG_ZEPHYR */ -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* Reset PD MCU */ void board_reset_pd_mcu(void) @@ -97,7 +97,7 @@ void ppc_interrupt(enum gpio_signal signal) for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { if (tcpc_aic_gpios[i].ppc_intr_handler && - signal == tcpc_aic_gpios[i].ppc_alert) { + signal == tcpc_aic_gpios[i].ppc_alert) { tcpc_aic_gpios[i].ppc_intr_handler(i); break; } @@ -107,6 +107,6 @@ void ppc_interrupt(enum gpio_signal signal) void board_charging_enable(int port, int enable) { if (ppc_vbus_sink_enable(port, enable)) - CPRINTS("C%d: sink path %s failed", - port, enable ? "en" : "dis"); + CPRINTS("C%d: sink path %s failed", port, + enable ? "en" : "dis"); } diff --git a/baseboard/intelrvp/ite_ec.c b/baseboard/intelrvp/ite_ec.c index bafddc5f9e..76703d4f82 100644 --- a/baseboard/intelrvp/ite_ec.c +++ b/baseboard/intelrvp/ite_ec.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -139,15 +139,15 @@ void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) * enabling the VCONN on respective CC line */ gpio_set_level(tcpc_gpios[port].vconn.cc1_pin, - !tcpc_gpios[port].vconn.pin_pol); + !tcpc_gpios[port].vconn.pin_pol); gpio_set_level(tcpc_gpios[port].vconn.cc2_pin, - !tcpc_gpios[port].vconn.pin_pol); + !tcpc_gpios[port].vconn.pin_pol); if (enabled) gpio_set_level((cc_pin != USBPD_CC_PIN_1) ? - tcpc_gpios[port].vconn.cc2_pin : - tcpc_gpios[port].vconn.cc1_pin, - tcpc_gpios[port].vconn.pin_pol); + tcpc_gpios[port].vconn.cc2_pin : + tcpc_gpios[port].vconn.cc1_pin, + tcpc_gpios[port].vconn.pin_pol); #endif } #endif diff --git a/baseboard/intelrvp/ite_ec.h b/baseboard/intelrvp/ite_ec.h index c773a48b21..7ad147a5f9 100644 --- a/baseboard/intelrvp/ite_ec.h +++ b/baseboard/intelrvp/ite_ec.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -13,13 +13,13 @@ #define CONFIG_IT83XX_VCC_1P8V /* ADC channels */ -#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH13 -#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH15 -#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH6 -#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH1 +#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH13 +#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH15 +#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH6 +#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH1 #ifdef CONFIG_USBC_VCONN - #define CONFIG_USBC_VCONN_SWAP - /* delay to turn on/off vconn */ +#define CONFIG_USBC_VCONN_SWAP +/* delay to turn on/off vconn */ #endif #endif /* __CROS_EC_ITE_EC_H */ diff --git a/baseboard/intelrvp/led.c b/baseboard/intelrvp/led.c index add2ebbe43..10e4e08e63 100644 --- a/baseboard/intelrvp/led.c +++ b/baseboard/intelrvp/led.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -19,30 +19,30 @@ const int led_charge_lvl_1 = 5; const int led_charge_lvl_2 = 97; struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC } }, }; const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_POWER_LED, - EC_LED_ID_BATTERY_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED, + EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -51,15 +51,15 @@ void led_set_color_power(enum ec_led_colors color) if (color == EC_LED_COLOR_WHITE) #ifdef CONFIG_ZEPHYR gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_white_l), - LED_ON_LVL); + LED_ON_LVL); #else gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_ON_LVL); #endif /* CONFIG_ZEPHYR */ else - /* LED_OFF and unsupported colors */ + /* LED_OFF and unsupported colors */ #ifdef CONFIG_ZEPHYR gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_white_l), - LED_OFF_LVL); + LED_OFF_LVL); #else gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_OFF_LVL); #endif /* CONFIG_ZEPHYR */ @@ -70,32 +70,28 @@ void led_set_color_battery(enum ec_led_colors color) switch (color) { case EC_LED_COLOR_RED: #ifdef CONFIG_ZEPHYR - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), - LED_ON_LVL); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), LED_ON_LVL); #else gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL); #endif /* CONFIG_ZEPHYR */ break; case EC_LED_COLOR_AMBER: #ifdef CONFIG_ZEPHYR - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), - LED_ON_LVL); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), LED_ON_LVL); #else gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL); #endif /* CONFIG_ZEPHYR */ break; case EC_LED_COLOR_GREEN: #ifdef CONFIG_ZEPHYR - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), - LED_OFF_LVL); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), LED_OFF_LVL); #else gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); #endif /* CONFIG_ZEPHYR */ break; default: /* LED_OFF and other unsupported colors */ #ifdef CONFIG_ZEPHYR - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), - LED_OFF_LVL); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), LED_OFF_LVL); #else gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); #endif /* CONFIG_ZEPHYR */ diff --git a/baseboard/intelrvp/led_states.c b/baseboard/intelrvp/led_states.c index 5f8768bdd9..8629085c4f 100644 --- a/baseboard/intelrvp/led_states.c +++ b/baseboard/intelrvp/led_states.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -15,11 +15,11 @@ #include "led_common.h" #include "led_states.h" -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) +#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args) static enum led_states led_get_state(void) { - int charge_lvl; + int charge_lvl; enum led_states new_state = LED_NUM_STATES; switch (charge_get_state()) { @@ -55,10 +55,10 @@ static enum led_states led_get_state(void) new_state = STATE_CHARGING_FULL_CHARGE; break; case PWR_STATE_IDLE: /* External power connected in IDLE */ - if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE) - new_state = STATE_FACTORY_TEST; - else - new_state = STATE_DISCHARGE_S0; + new_state = STATE_DISCHARGE_S0; + break; + case PWR_STATE_FORCED_IDLE: + new_state = STATE_FACTORY_TEST; break; default: /* Other states don't alter LED behavior */ @@ -88,14 +88,14 @@ static void led_update_battery(void) ticks = 0; period = led_bat_state_table[led_state][LED_PHASE_0].time + - led_bat_state_table[led_state][LED_PHASE_1].time; - + led_bat_state_table[led_state][LED_PHASE_1].time; } /* If this state is undefined, turn the LED off */ if (period == 0) { CPRINTS("Undefined LED behavior for battery state %d," - "turning off LED", led_state); + "turning off LED", + led_state); led_set_color_battery(LED_OFF); return; } @@ -104,8 +104,8 @@ static void led_update_battery(void) * Determine which phase of the state table to use. The phase is * determined if it falls within first phase time duration. */ - phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ? - 0 : 1; + phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ? 0 : + 1; ticks = (ticks + 1) % period; /* Set the color for the given state and phase */ @@ -141,14 +141,14 @@ static void led_update_power(void) ticks = 0; period = led_pwr_state_table[led_state][LED_PHASE_0].time + - led_pwr_state_table[led_state][LED_PHASE_1].time; - + led_pwr_state_table[led_state][LED_PHASE_1].time; } /* If this state is undefined, turn the LED off */ if (period == 0) { CPRINTS("Undefined LED behavior for power state %d," - "turning off LED", led_state); + "turning off LED", + led_state); led_set_color_power(LED_OFF); return; } @@ -157,8 +157,8 @@ static void led_update_power(void) * Determine which phase of the state table to use. The phase is * determined if it falls within first phase time duration. */ - phase = ticks < led_pwr_state_table[led_state][LED_PHASE_0].time ? - 0 : 1; + phase = ticks < led_pwr_state_table[led_state][LED_PHASE_0].time ? 0 : + 1; ticks = (ticks + 1) % period; /* Set the color for the given state and phase */ diff --git a/baseboard/intelrvp/led_states.h b/baseboard/intelrvp/led_states.h index 907ff5c8b8..3b584c6efc 100644 --- a/baseboard/intelrvp/led_states.h +++ b/baseboard/intelrvp/led_states.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -10,19 +10,15 @@ #include "ec_commands.h" -#define LED_INDEFINITE UINT8_MAX -#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS) -#define LED_OFF EC_LED_COLOR_COUNT +#define LED_INDEFINITE UINT8_MAX +#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS) +#define LED_OFF EC_LED_COLOR_COUNT /* * All LED states should have one phase defined, * and an additional phase can be defined for blinking */ -enum led_phase { - LED_PHASE_0, - LED_PHASE_1, - LED_NUM_PHASES -}; +enum led_phase { LED_PHASE_0, LED_PHASE_1, LED_NUM_PHASES }; /* * STATE_CHARGING_LVL_1 is when 0 <= charge_percentage < led_charge_level_1 @@ -51,10 +47,8 @@ struct led_descriptor { uint8_t time; }; - /* Charging LED state table - defined in board's led.c */ -extern struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES]; +extern struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES]; /* Charging LED state level 1 - defined in board's led.c */ extern const int led_charge_lvl_1; @@ -71,8 +65,8 @@ enum pwr_led_states { }; /* Power LED state table - defined in board's led.c */ -extern const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES]; +extern const struct led_descriptor led_pwr_state_table[PWR_LED_NUM_STATES] + [LED_NUM_PHASES]; /** * Set battery LED color - defined in board's led.c diff --git a/baseboard/intelrvp/mchp_ec.c b/baseboard/intelrvp/mchp_ec.c index f1eb4678c1..7ede17569b 100644 --- a/baseboard/intelrvp/mchp_ec.c +++ b/baseboard/intelrvp/mchp_ec.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/intelrvp/mchp_ec.h b/baseboard/intelrvp/mchp_ec.h index 227ccaef6d..ec1e47c030 100644 --- a/baseboard/intelrvp/mchp_ec.h +++ b/baseboard/intelrvp/mchp_ec.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,10 +9,10 @@ #define __CROS_EC_MCHP_EC_H /* ADC channels */ -#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH7 -#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH4 -#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH3 -#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH1 +#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH7 +#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH4 +#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH3 +#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH1 /* * ADC maximum voltage is a board level configuration. diff --git a/baseboard/intelrvp/npcx_ec.c b/baseboard/intelrvp/npcx_ec.c index d6eca2e55b..a90442e8b1 100644 --- a/baseboard/intelrvp/npcx_ec.c +++ b/baseboard/intelrvp/npcx_ec.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/intelrvp/npcx_ec.h b/baseboard/intelrvp/npcx_ec.h index 52bcb2dae6..5fe6aa9786 100644 --- a/baseboard/intelrvp/npcx_ec.h +++ b/baseboard/intelrvp/npcx_ec.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,20 +19,20 @@ enum mft_channel { #endif /* __ASSEMBLER__ */ /* ADC channels */ -#define ADC_MAX_MVOLT ADC_MAX_VOLT -#define ADC_TEMP_SNS_AMBIENT_CHANNEL NPCX_ADC_CH3 -#define ADC_TEMP_SNS_DDR_CHANNEL NPCX_ADC_CH4 -#define ADC_TEMP_SNS_SKIN_CHANNEL NPCX_ADC_CH2 -#define ADC_TEMP_SNS_VR_CHANNEL NPCX_ADC_CH1 +#define ADC_MAX_MVOLT ADC_MAX_VOLT +#define ADC_TEMP_SNS_AMBIENT_CHANNEL NPCX_ADC_CH3 +#define ADC_TEMP_SNS_DDR_CHANNEL NPCX_ADC_CH4 +#define ADC_TEMP_SNS_SKIN_CHANNEL NPCX_ADC_CH2 +#define ADC_TEMP_SNS_VR_CHANNEL NPCX_ADC_CH1 /* KSO2 is inverted */ -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV /* Fan */ #define CONFIG_PWM -#define PWN_FAN_CHANNEL 3 +#define PWN_FAN_CHANNEL 3 /* GPIO64/65 are used as UART pins. */ -#define NPCX_UART_MODULE2 1 +#define NPCX_UART_MODULE2 1 #endif /* __CROS_EC_NPCX_EC_H */ diff --git a/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c b/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c index 8e06c9f0b3..303d176405 100644 --- a/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c +++ b/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -15,8 +15,8 @@ #include "intelrvp.h" #endif /* CONFIG_ZEPHYR */ -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_set_power_supply_ready(int port) { |