diff options
Diffstat (limited to 'board/genesis/board.h')
| -rw-r--r-- | board/genesis/board.h | 90 |
1 files changed, 43 insertions, 47 deletions
diff --git a/board/genesis/board.h b/board/genesis/board.h index 9c9233590e..41de23b6a8 100644 --- a/board/genesis/board.h +++ b/board/genesis/board.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,8 +12,8 @@ #define CONFIG_UART_TX_BUF_SIZE 4096 /* NPCX7 config */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ /* Internal SPI flash on NPCX796FC is 512 kB */ #define CONFIG_FLASH_SIZE_BYTES (512 * 1024) @@ -40,7 +40,7 @@ #undef CONFIG_HIBERNATE #define CONFIG_HOST_INTERFACE_ESPI #define CONFIG_LED_COMMON -#undef CONFIG_LID_SWITCH +#undef CONFIG_LID_SWITCH #define CONFIG_LTO #define CONFIG_PWM #define CONFIG_VBOOT_EFS2 @@ -118,13 +118,13 @@ /* I2C Bus Configuration */ #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER -#define I2C_PORT_INA NPCX_I2C_PORT0_0 -#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0 -#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0 -#define I2C_PORT_PSE NPCX_I2C_PORT4_1 -#define I2C_PORT_POWER NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_PORT_INA NPCX_I2C_PORT0_0 +#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0 +#define I2C_PORT_PSE NPCX_I2C_PORT4_1 +#define I2C_PORT_POWER NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD) @@ -134,11 +134,11 @@ #include "registers.h" enum adc_channel { - ADC_SNS_PP3300, /* ADC2 */ - ADC_SNS_PP1050, /* ADC7 */ - ADC_VBUS, /* ADC4 */ - ADC_PPVAR_IMON, /* ADC9 */ - ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_SNS_PP3300, /* ADC2 */ + ADC_SNS_PP1050, /* ADC7 */ + ADC_VBUS, /* ADC4 */ + ADC_PPVAR_IMON, /* ADC9 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ /* Number of ADC channels */ ADC_CH_COUNT }; @@ -163,11 +163,7 @@ enum mft_channel { MFT_CH_COUNT, }; -enum temp_sensor_id { - TEMP_SENSOR_CORE, - TEMP_SENSOR_COUNT -}; - +enum temp_sensor_id { TEMP_SENSOR_CORE, TEMP_SENSOR_COUNT }; /* Board specific handlers */ void led_alert(int enable); @@ -179,20 +175,20 @@ void show_critical_error(void); /* * Barrel-jack power (4 bits). */ -#define EC_CFG_BJ_POWER_L 0 -#define EC_CFG_BJ_POWER_H 3 +#define EC_CFG_BJ_POWER_L 0 +#define EC_CFG_BJ_POWER_H 3 #define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L) /* * USB Connector 4 not present (1 bit). */ -#define EC_CFG_NO_USB4_L 4 -#define EC_CFG_NO_USB4_H 4 +#define EC_CFG_NO_USB4_L 4 +#define EC_CFG_NO_USB4_H 4 #define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L) /* * Thermal solution config (3 bits). */ -#define EC_CFG_THERMAL_L 5 -#define EC_CFG_THERMAL_H 7 +#define EC_CFG_THERMAL_L 5 +#define EC_CFG_THERMAL_H 7 #define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L) unsigned int ec_config_get_thermal_solution(void); @@ -200,30 +196,30 @@ unsigned int ec_config_get_thermal_solution(void); #endif /* !__ASSEMBLER__ */ /* Pin renaming */ -#define GPIO_WP_L GPIO_EC_WP_ODL -#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A -#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL -#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL -#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L -#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS -#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L +#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL +#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL +#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS +#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L /* * There is no RSMRST input, so alias it to the output. This short-circuits * common_intel_x86_handle_rsmrst. */ -#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L +#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L #endif /* __CROS_EC_BOARD_H */ |