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-rw-r--r--board/genesis/board.c143
-rw-r--r--board/genesis/board.h90
-rw-r--r--board/genesis/build.mk2
-rw-r--r--board/genesis/ec.tasklist2
-rw-r--r--board/genesis/gpio.inc6
-rw-r--r--board/genesis/led.c14
-rw-r--r--board/genesis/pse.c85
7 files changed, 161 insertions, 181 deletions
diff --git a/board/genesis/board.c b/board/genesis/board.c
index 5305c8d630..5c3f1c5c00 100644
--- a/board/genesis/board.c
+++ b/board/genesis/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -36,8 +36,8 @@
#include "usb_common.h"
#include "util.h"
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
static void power_monitor(void);
DECLARE_DEFERRED(power_monitor);
@@ -49,14 +49,14 @@ static int32_t base_5v_power;
* Power usage for each port as measured or estimated.
* Units are milliwatts (5v x ma current)
*/
-#define PWR_BASE_LOAD (5*1335)
-#define PWR_FRONT_HIGH (5*1500)
-#define PWR_FRONT_LOW (5*900)
-#define PWR_REAR (5*1500)
-#define PWR_HDMI (5*562)
-#define PWR_C_HIGH (5*3740)
-#define PWR_C_LOW (5*2090)
-#define PWR_MAX (5*10000)
+#define PWR_BASE_LOAD (5 * 1335)
+#define PWR_FRONT_HIGH (5 * 1500)
+#define PWR_FRONT_LOW (5 * 900)
+#define PWR_REAR (5 * 1500)
+#define PWR_HDMI (5 * 562)
+#define PWR_C_HIGH (5 * 3740)
+#define PWR_C_LOW (5 * 2090)
+#define PWR_MAX (5 * 10000)
/*
* Update the 5V power usage, assuming no throttling,
@@ -112,69 +112,56 @@ static void port_ocp_interrupt(enum gpio_signal signal)
/******************************************************************************/
/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
/******************************************************************************/
/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
const struct pwm_t pwm_channels[] = {
- [PWM_CH_FAN] = { .channel = 5,
- .flags = PWM_CONFIG_OPEN_DRAIN,
- .freq = 25000},
- [PWM_CH_LED_RED] = { .channel = 0,
- .flags = PWM_CONFIG_DSLEEP,
- .freq = 2000 },
- [PWM_CH_LED_WHITE] = { .channel = 2,
- .flags = PWM_CONFIG_DSLEEP,
- .freq = 2000 },
+ [PWM_CH_FAN] = { .channel = 5,
+ .flags = PWM_CONFIG_OPEN_DRAIN,
+ .freq = 25000 },
+ [PWM_CH_LED_RED] = { .channel = 0,
+ .flags = PWM_CONFIG_DSLEEP,
+ .freq = 2000 },
+ [PWM_CH_LED_WHITE] = { .channel = 2,
+ .flags = PWM_CONFIG_DSLEEP,
+ .freq = 2000 },
};
/******************************************************************************/
/* I2C port map configuration */
const struct i2c_port_t i2c_ports[] = {
- {
- .name = "ina",
- .port = I2C_PORT_INA,
- .kbps = 400,
- .scl = GPIO_I2C0_SCL,
- .sda = GPIO_I2C0_SDA
- },
- {
- .name = "ppc0",
- .port = I2C_PORT_PPC0,
- .kbps = 400,
- .scl = GPIO_I2C1_SCL,
- .sda = GPIO_I2C1_SDA
- },
- {
- .name = "tcpc0",
- .port = I2C_PORT_TCPC0,
- .kbps = 400,
- .scl = GPIO_I2C3_SCL,
- .sda = GPIO_I2C3_SDA
- },
- {
- .name = "pse",
- .port = I2C_PORT_PSE,
- .kbps = 400,
- .scl = GPIO_I2C4_SCL,
- .sda = GPIO_I2C4_SDA
- },
- {
- .name = "power",
- .port = I2C_PORT_POWER,
- .kbps = 400,
- .scl = GPIO_I2C5_SCL,
- .sda = GPIO_I2C5_SDA
- },
- {
- .name = "eeprom",
- .port = I2C_PORT_EEPROM,
- .kbps = 400,
- .scl = GPIO_I2C7_SCL,
- .sda = GPIO_I2C7_SDA
- },
+ { .name = "ina",
+ .port = I2C_PORT_INA,
+ .kbps = 400,
+ .scl = GPIO_I2C0_SCL,
+ .sda = GPIO_I2C0_SDA },
+ { .name = "ppc0",
+ .port = I2C_PORT_PPC0,
+ .kbps = 400,
+ .scl = GPIO_I2C1_SCL,
+ .sda = GPIO_I2C1_SDA },
+ { .name = "tcpc0",
+ .port = I2C_PORT_TCPC0,
+ .kbps = 400,
+ .scl = GPIO_I2C3_SCL,
+ .sda = GPIO_I2C3_SDA },
+ { .name = "pse",
+ .port = I2C_PORT_PSE,
+ .kbps = 400,
+ .scl = GPIO_I2C4_SCL,
+ .sda = GPIO_I2C4_SDA },
+ { .name = "power",
+ .port = I2C_PORT_POWER,
+ .kbps = 400,
+ .scl = GPIO_I2C5_SCL,
+ .sda = GPIO_I2C5_SDA },
+ { .name = "eeprom",
+ .port = I2C_PORT_EEPROM,
+ .kbps = 400,
+ .scl = GPIO_I2C7_SCL,
+ .sda = GPIO_I2C7_SDA },
};
const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -230,15 +217,14 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
/******************************************************************************/
/* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-};
+const enum gpio_signal hibernate_wake_pins[] = {};
const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
/******************************************************************************/
/* Physical fans. These are logically separate from pwm_channels. */
const struct fan_conf fan_conf_0 = {
.flags = FAN_USE_RPM_MODE,
- .ch = MFT_CH_0, /* Use MFT id to control fan */
+ .ch = MFT_CH_0, /* Use MFT id to control fan */
.pgood_gpio = -1,
.enable_gpio = -1,
};
@@ -257,7 +243,7 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
/******************************************************************************/
/* MFT channels. These are logically separate from pwm_channels. */
const struct mft_t mft_channels[] = {
- [MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
+ [MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN },
};
BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
@@ -266,8 +252,8 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
/*
* TODO(b/202062363): Remove when clang is fixed.
*/
-#define THERMAL_A \
- { \
+#define THERMAL_A \
+ { \
.temp_host = { \
[EC_TEMP_THRESH_WARN] = 0, \
[EC_TEMP_THRESH_HIGH] = C_TO_K(78), \
@@ -420,23 +406,23 @@ void board_enable_s0_rails(int enable)
*
* All measurements are in milliwatts.
*/
-#define THROT_TYPE_A BIT(0)
-#define THROT_TYPE_C BIT(1)
-#define THROT_PROCHOT BIT(2)
+#define THROT_TYPE_A BIT(0)
+#define THROT_TYPE_C BIT(1)
+#define THROT_PROCHOT BIT(2)
/*
* Power gain if front USB A ports are limited.
*/
-#define POWER_GAIN_TYPE_A 3200
+#define POWER_GAIN_TYPE_A 3200
/*
* Power gain if Type C port is limited.
*/
-#define POWER_GAIN_TYPE_C 8800
+#define POWER_GAIN_TYPE_C 8800
/*
* Power is averaged over 10 ms, with a reading every 2 ms.
*/
-#define POWER_DELAY_MS 2
-#define POWER_READINGS (10/POWER_DELAY_MS)
+#define POWER_DELAY_MS 2
+#define POWER_READINGS (10 / POWER_DELAY_MS)
static void power_monitor(void)
{
@@ -449,8 +435,7 @@ static void power_monitor(void)
* If CPU is off or suspended, no need to throttle
* or restrict power.
*/
- if (chipset_in_state(CHIPSET_STATE_ANY_OFF |
- CHIPSET_STATE_SUSPEND)) {
+ if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) {
/*
* Slow down monitoring, assume no throttling required.
*/
diff --git a/board/genesis/board.h b/board/genesis/board.h
index 9c9233590e..41de23b6a8 100644
--- a/board/genesis/board.h
+++ b/board/genesis/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -12,8 +12,8 @@
#define CONFIG_UART_TX_BUF_SIZE 4096
/* NPCX7 config */
-#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
-#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
/* Internal SPI flash on NPCX796FC is 512 kB */
#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
@@ -40,7 +40,7 @@
#undef CONFIG_HIBERNATE
#define CONFIG_HOST_INTERFACE_ESPI
#define CONFIG_LED_COMMON
-#undef CONFIG_LID_SWITCH
+#undef CONFIG_LID_SWITCH
#define CONFIG_LTO
#define CONFIG_PWM
#define CONFIG_VBOOT_EFS2
@@ -118,13 +118,13 @@
/* I2C Bus Configuration */
#define CONFIG_I2C
#define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_INA NPCX_I2C_PORT0_0
-#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0
-#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0
-#define I2C_PORT_PSE NPCX_I2C_PORT4_1
-#define I2C_PORT_POWER NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
-#define I2C_ADDR_EEPROM_FLAGS 0x50
+#define I2C_PORT_INA NPCX_I2C_PORT0_0
+#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0
+#define I2C_PORT_PSE NPCX_I2C_PORT4_1
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_ADDR_EEPROM_FLAGS 0x50
#define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD)
@@ -134,11 +134,11 @@
#include "registers.h"
enum adc_channel {
- ADC_SNS_PP3300, /* ADC2 */
- ADC_SNS_PP1050, /* ADC7 */
- ADC_VBUS, /* ADC4 */
- ADC_PPVAR_IMON, /* ADC9 */
- ADC_TEMP_SENSOR_1, /* ADC0 */
+ ADC_SNS_PP3300, /* ADC2 */
+ ADC_SNS_PP1050, /* ADC7 */
+ ADC_VBUS, /* ADC4 */
+ ADC_PPVAR_IMON, /* ADC9 */
+ ADC_TEMP_SENSOR_1, /* ADC0 */
/* Number of ADC channels */
ADC_CH_COUNT
};
@@ -163,11 +163,7 @@ enum mft_channel {
MFT_CH_COUNT,
};
-enum temp_sensor_id {
- TEMP_SENSOR_CORE,
- TEMP_SENSOR_COUNT
-};
-
+enum temp_sensor_id { TEMP_SENSOR_CORE, TEMP_SENSOR_COUNT };
/* Board specific handlers */
void led_alert(int enable);
@@ -179,20 +175,20 @@ void show_critical_error(void);
/*
* Barrel-jack power (4 bits).
*/
-#define EC_CFG_BJ_POWER_L 0
-#define EC_CFG_BJ_POWER_H 3
+#define EC_CFG_BJ_POWER_L 0
+#define EC_CFG_BJ_POWER_H 3
#define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L)
/*
* USB Connector 4 not present (1 bit).
*/
-#define EC_CFG_NO_USB4_L 4
-#define EC_CFG_NO_USB4_H 4
+#define EC_CFG_NO_USB4_L 4
+#define EC_CFG_NO_USB4_H 4
#define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L)
/*
* Thermal solution config (3 bits).
*/
-#define EC_CFG_THERMAL_L 5
-#define EC_CFG_THERMAL_H 7
+#define EC_CFG_THERMAL_L 5
+#define EC_CFG_THERMAL_H 7
#define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L)
unsigned int ec_config_get_thermal_solution(void);
@@ -200,30 +196,30 @@ unsigned int ec_config_get_thermal_solution(void);
#endif /* !__ASSEMBLER__ */
/* Pin renaming */
-#define GPIO_WP_L GPIO_EC_WP_ODL
-#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD
-#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
-#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL
-#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL
-#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
-#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
-#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
-#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
-#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
-#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS
-#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL
+#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS
+#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L
/*
* There is no RSMRST input, so alias it to the output. This short-circuits
* common_intel_x86_handle_rsmrst.
*/
-#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L
#endif /* __CROS_EC_BOARD_H */
diff --git a/board/genesis/build.mk b/board/genesis/build.mk
index 2785133e11..50d3763d2b 100644
--- a/board/genesis/build.mk
+++ b/board/genesis/build.mk
@@ -1,5 +1,5 @@
# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
diff --git a/board/genesis/ec.tasklist b/board/genesis/ec.tasklist
index 3828142c55..c43d643410 100644
--- a/board/genesis/ec.tasklist
+++ b/board/genesis/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
diff --git a/board/genesis/gpio.inc b/board/genesis/gpio.inc
index d8f2989b8e..7d2c33c5a9 100644
--- a/board/genesis/gpio.inc
+++ b/board/genesis/gpio.inc
@@ -1,6 +1,6 @@
/* -*- mode:c -*-
*
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -25,12 +25,12 @@ GPIO_INT(PG_VPRIM_CORE_A_OD, PIN(2, 3), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(PG_PP1050_A_OD, PIN(2, 2), GPIO_INT_BOTH, power_signal_interrupt)
/* EC output, but also interrupt so this can be polled as a power signal */
GPIO_INT(EC_PCH_RSMRST_L, PIN(A, 6), GPIO_OUTPUT | GPIO_INT_F_RISING | GPIO_INT_F_FALLING, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
GPIO_INT(SLP_S4_L, PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
#endif
GPIO_INT(PG_PP2500_DRAM_U_OD, PIN(2, 0), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(PG_PP1200_U_OD, PIN(2, 1), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
GPIO_INT(SLP_S3_L, PIN(A, 5), GPIO_INT_BOTH, slp_s3_interrupt)
#endif
GPIO_INT(PG_PP950_VCCIO_OD, PIN(1, 7), GPIO_INT_BOTH, power_signal_interrupt)
diff --git a/board/genesis/led.c b/board/genesis/led.c
index c562dff27e..9258b6eb6d 100644
--- a/board/genesis/led.c
+++ b/board/genesis/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
@@ -19,16 +19,16 @@
#include "timer.h"
#include "util.h"
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
/*
* Due to the CSME-Lite processing, upon startup the CPU transitions through
* S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
* delay turning off the LED during suspend/shutdown.
*/
-#define LED_CPU_DELAY_MS (2000 * MSEC)
+#define LED_CPU_DELAY_MS (2000 * MSEC)
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
enum led_color {
@@ -89,9 +89,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty)
}
}
-#define LED_PULSE_US (2 * SECOND)
+#define LED_PULSE_US (2 * SECOND)
/* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US (40 * MSEC)
+#define LED_PULSE_TICK_US (40 * MSEC)
/* When pulsing is enabled, brightness is incremented by <duty_inc> every
* <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
@@ -223,7 +223,7 @@ void show_critical_error(void)
set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
}
-static int command_led(int argc, char **argv)
+static int command_led(int argc, const char **argv)
{
enum ec_led_id id = EC_LED_ID_POWER_LED;
diff --git a/board/genesis/pse.c b/board/genesis/pse.c
index 671288ccf5..bda7e1994d 100644
--- a/board/genesis/pse.c
+++ b/board/genesis/pse.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -18,44 +18,44 @@
#include "timer.h"
#include "util.h"
-#define LTC4291_I2C_ADDR 0x2C
-
-#define LTC4291_REG_SUPEVN_COR 0x0B
-#define LTC4291_REG_STATPWR 0x10
-#define LTC4291_REG_STATPIN 0x11
-#define LTC4291_REG_OPMD 0x12
-#define LTC4291_REG_DISENA 0x13
-#define LTC4291_REG_DETENA 0x14
-#define LTC4291_REG_DETPB 0x18
-#define LTC4291_REG_PWRPB 0x19
-#define LTC4291_REG_RSTPB 0x1A
-#define LTC4291_REG_ID 0x1B
-#define LTC4291_REG_DEVID 0x43
-#define LTC4291_REG_HPMD1 0x46
-#define LTC4291_REG_HPMD2 0x4B
-#define LTC4291_REG_HPMD3 0x50
-#define LTC4291_REG_HPMD4 0x55
-#define LTC4291_REG_LPWRPB 0x6E
-
-#define LTC4291_FLD_STATPIN_AUTO BIT(0)
-#define LTC4291_FLD_RSTPB_RSTALL BIT(4)
-
-#define LTC4291_STATPWR_ON_PORT(port) (0x01 << (port))
-#define LTC4291_DETENA_EN_PORT(port) (0x11 << (port))
-#define LTC4291_DETPB_EN_PORT(port) (0x11 << (port))
-#define LTC4291_PWRPB_OFF_PORT(port) (0x10 << (port))
-
-#define LTC4291_OPMD_AUTO 0xFF
-#define LTC4291_DISENA_ALL 0x0F
-#define LTC4291_DETENA_ALL 0xFF
-#define LTC4291_ID 0x64
-#define LTC4291_DEVID 0x38
-#define LTC4291_HPMD_MIN 0x00
-#define LTC4291_HPMD_MAX 0xA8
-
-#define LTC4291_PORT_MAX 4
-
-#define LTC4291_RESET_DELAY_US (20 * MSEC)
+#define LTC4291_I2C_ADDR 0x2C
+
+#define LTC4291_REG_SUPEVN_COR 0x0B
+#define LTC4291_REG_STATPWR 0x10
+#define LTC4291_REG_STATPIN 0x11
+#define LTC4291_REG_OPMD 0x12
+#define LTC4291_REG_DISENA 0x13
+#define LTC4291_REG_DETENA 0x14
+#define LTC4291_REG_DETPB 0x18
+#define LTC4291_REG_PWRPB 0x19
+#define LTC4291_REG_RSTPB 0x1A
+#define LTC4291_REG_ID 0x1B
+#define LTC4291_REG_DEVID 0x43
+#define LTC4291_REG_HPMD1 0x46
+#define LTC4291_REG_HPMD2 0x4B
+#define LTC4291_REG_HPMD3 0x50
+#define LTC4291_REG_HPMD4 0x55
+#define LTC4291_REG_LPWRPB 0x6E
+
+#define LTC4291_FLD_STATPIN_AUTO BIT(0)
+#define LTC4291_FLD_RSTPB_RSTALL BIT(4)
+
+#define LTC4291_STATPWR_ON_PORT(port) (0x01 << (port))
+#define LTC4291_DETENA_EN_PORT(port) (0x11 << (port))
+#define LTC4291_DETPB_EN_PORT(port) (0x11 << (port))
+#define LTC4291_PWRPB_OFF_PORT(port) (0x10 << (port))
+
+#define LTC4291_OPMD_AUTO 0xFF
+#define LTC4291_DISENA_ALL 0x0F
+#define LTC4291_DETENA_ALL 0xFF
+#define LTC4291_ID 0x64
+#define LTC4291_DEVID 0x38
+#define LTC4291_HPMD_MIN 0x00
+#define LTC4291_HPMD_MAX 0xA8
+
+#define LTC4291_PORT_MAX 4
+
+#define LTC4291_RESET_DELAY_US (20 * MSEC)
#define I2C_PSE_READ(reg, data) \
i2c_read8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data))
@@ -63,7 +63,7 @@
#define I2C_PSE_WRITE(reg, data) \
i2c_write8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data))
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
static int pse_write_hpmd(int port, int val)
{
@@ -173,7 +173,7 @@ DECLARE_HOOK(HOOK_CHIPSET_RESUME, pse_init, HOOK_PRIO_DEFAULT);
/* Also reset the PSE on a reboot to toggle the power. */
DECLARE_HOOK(HOOK_CHIPSET_RESET, pse_init, HOOK_PRIO_DEFAULT);
-static int command_pse(int argc, char **argv)
+static int command_pse(int argc, const char **argv)
{
int port;
@@ -205,8 +205,7 @@ static int command_pse(int argc, char **argv)
else
return EC_ERROR_PARAM2;
}
-DECLARE_CONSOLE_COMMAND(pse, command_pse,
- "<port# 0-3> <off | on | min | max>",
+DECLARE_CONSOLE_COMMAND(pse, command_pse, "<port# 0-3> <off | on | min | max>",
"Set PSE port power");
static int ec_command_pse_status(int port, uint8_t *status)
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