diff options
Diffstat (limited to 'board/servo_v4p1')
25 files changed, 581 insertions, 615 deletions
diff --git a/board/servo_v4p1/board.c b/board/servo_v4p1/board.c index 3284b4ef58..c3caa1eff1 100644 --- a/board/servo_v4p1/board.c +++ b/board/servo_v4p1/board.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -85,14 +85,20 @@ static int board_tusb1064_dp_rx_eq_set(const struct usb_mux *me, return rv; } -const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [CHG] = { /* CHG port connected directly to USB 3.0 hub, no mux */ }, - [DUT] = { /* DUT port with UFP mux */ - .usb_port = DUT, - .i2c_port = I2C_PORT_MASTER, - .i2c_addr_flags = TUSB1064_I2C_ADDR10_FLAGS, - .driver = &tusb1064_usb_mux_driver, - .board_set = &board_tusb1064_dp_rx_eq_set, +const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { + [CHG] = { + /* CHG port connected directly to USB 3.0 hub, no mux */ + }, + [DUT] = { + /* DUT port with UFP mux */ + .mux = + &(const struct usb_mux){ + .usb_port = DUT, + .i2c_port = I2C_PORT_MASTER, + .i2c_addr_flags = TUSB1064_I2C_ADDR10_FLAGS, + .driver = &tusb1064_usb_mux_driver, + .board_set = &board_tusb1064_dp_rx_eq_set, + }, } }; @@ -182,9 +188,9 @@ static void tcpc_evt(enum gpio_signal signal) update_status_fusb302b(); } -#define HOST_HUB 0 +#define HOST_HUB 0 struct uhub_i2c_iface_t uhub_config[] = { - {I2C_PORT_MASTER, GL3590_I2C_ADDR0}, + { I2C_PORT_MASTER, GL3590_I2C_ADDR0 }, }; static void host_hub_evt(void) @@ -231,8 +237,8 @@ void ext_hpd_detection_enable(int enable) #include "gpio_list.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) /****************************************************************************** * Board pre-init function. @@ -276,23 +282,22 @@ void board_config_pre_init(void) /* ADC channels */ const struct adc_t adc_channels[] = { /* USB PD CC lines sensing. Converted to mV (3300mV/4096). */ - [ADC_CHG_CC1_PD] = {"CHG_CC1_PD", 3300, 4096, 0, STM32_AIN(2)}, - [ADC_CHG_CC2_PD] = {"CHG_CC2_PD", 3300, 4096, 0, STM32_AIN(4)}, - [ADC_DUT_CC1_PD] = {"DUT_CC1_PD", 3300, 4096, 0, STM32_AIN(0)}, - [ADC_DUT_CC2_PD] = {"DUT_CC2_PD", 3300, 4096, 0, STM32_AIN(5)}, - [ADC_SBU1_DET] = {"SBU1_DET", 3300, 4096, 0, STM32_AIN(3)}, - [ADC_SBU2_DET] = {"SBU2_DET", 3300, 4096, 0, STM32_AIN(7)}, - [ADC_SUB_C_REF] = {"SUB_C_REF", 3300, 4096, 0, STM32_AIN(1)}, + [ADC_CHG_CC1_PD] = { "CHG_CC1_PD", 3300, 4096, 0, STM32_AIN(2) }, + [ADC_CHG_CC2_PD] = { "CHG_CC2_PD", 3300, 4096, 0, STM32_AIN(4) }, + [ADC_DUT_CC1_PD] = { "DUT_CC1_PD", 3300, 4096, 0, STM32_AIN(0) }, + [ADC_DUT_CC2_PD] = { "DUT_CC2_PD", 3300, 4096, 0, STM32_AIN(5) }, + [ADC_SBU1_DET] = { "SBU1_DET", 3300, 4096, 0, STM32_AIN(3) }, + [ADC_SBU2_DET] = { "SBU2_DET", 3300, 4096, 0, STM32_AIN(7) }, + [ADC_SUB_C_REF] = { "SUB_C_REF", 3300, 4096, 0, STM32_AIN(1) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); - /****************************************************************************** * Forward UARTs as a USB serial interface. */ -#define USB_STREAM_RX_SIZE 16 -#define USB_STREAM_TX_SIZE 16 +#define USB_STREAM_RX_SIZE 16 +#define USB_STREAM_TX_SIZE 16 /****************************************************************************** * Forward USART3 as a simple USB serial interface. @@ -301,29 +306,19 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); static struct usart_config const usart3; struct usb_stream_config const usart3_usb; -static struct queue const usart3_to_usb = QUEUE_DIRECT(64, uint8_t, - usart3.producer, usart3_usb.consumer); -static struct queue const usb_to_usart3 = QUEUE_DIRECT(64, uint8_t, - usart3_usb.producer, usart3.consumer); +static struct queue const usart3_to_usb = + QUEUE_DIRECT(64, uint8_t, usart3.producer, usart3_usb.consumer); +static struct queue const usb_to_usart3 = + QUEUE_DIRECT(64, uint8_t, usart3_usb.producer, usart3.consumer); static struct usart_config const usart3 = - USART_CONFIG(usart3_hw, - usart_rx_interrupt, - usart_tx_interrupt, - 115200, - 0, - usart3_to_usb, - usb_to_usart3); - -USB_STREAM_CONFIG(usart3_usb, - USB_IFACE_USART3_STREAM, - USB_STR_USART3_STREAM_NAME, - USB_EP_USART3_STREAM, - USB_STREAM_RX_SIZE, - USB_STREAM_TX_SIZE, - usb_to_usart3, - usart3_to_usb) + USART_CONFIG(usart3_hw, usart_rx_interrupt, usart_tx_interrupt, 115200, + 0, usart3_to_usb, usb_to_usart3); +USB_STREAM_CONFIG(usart3_usb, USB_IFACE_USART3_STREAM, + USB_STR_USART3_STREAM_NAME, USB_EP_USART3_STREAM, + USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, usb_to_usart3, + usart3_to_usb) /****************************************************************************** * Forward USART4 as a simple USB serial interface. @@ -332,46 +327,34 @@ USB_STREAM_CONFIG(usart3_usb, static struct usart_config const usart4; struct usb_stream_config const usart4_usb; -static struct queue const usart4_to_usb = QUEUE_DIRECT(64, uint8_t, - usart4.producer, usart4_usb.consumer); -static struct queue const usb_to_usart4 = QUEUE_DIRECT(64, uint8_t, - usart4_usb.producer, usart4.consumer); +static struct queue const usart4_to_usb = + QUEUE_DIRECT(64, uint8_t, usart4.producer, usart4_usb.consumer); +static struct queue const usb_to_usart4 = + QUEUE_DIRECT(64, uint8_t, usart4_usb.producer, usart4.consumer); static struct usart_config const usart4 = - USART_CONFIG(usart4_hw, - usart_rx_interrupt, - usart_tx_interrupt, - 9600, - 0, - usart4_to_usb, - usb_to_usart4); - -USB_STREAM_CONFIG_USART_IFACE(usart4_usb, - USB_IFACE_USART4_STREAM, - USB_STR_USART4_STREAM_NAME, - USB_EP_USART4_STREAM, - USB_STREAM_RX_SIZE, - USB_STREAM_TX_SIZE, - usb_to_usart4, - usart4_to_usb, - usart4) + USART_CONFIG(usart4_hw, usart_rx_interrupt, usart_tx_interrupt, 9600, 0, + usart4_to_usb, usb_to_usart4); +USB_STREAM_CONFIG_USART_IFACE(usart4_usb, USB_IFACE_USART4_STREAM, + USB_STR_USART4_STREAM_NAME, USB_EP_USART4_STREAM, + USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, + usb_to_usart4, usart4_to_usb, usart4) /* * Define usb interface descriptor for the `EMPTY` usb interface, to satisfy * UEFI and kernel requirements (see b/183857501). */ -const struct usb_interface_descriptor -USB_IFACE_DESC(USB_IFACE_EMPTY) = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = USB_IFACE_EMPTY, - .bAlternateSetting = 0, - .bNumEndpoints = 0, - .bInterfaceClass = USB_CLASS_VENDOR_SPEC, +const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_EMPTY) = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = USB_IFACE_EMPTY, + .bAlternateSetting = 0, + .bNumEndpoints = 0, + .bInterfaceClass = USB_CLASS_VENDOR_SPEC, .bInterfaceSubClass = 0, .bInterfaceProtocol = 0, - .iInterface = 0, + .iInterface = 0, }; /****************************************************************************** @@ -379,40 +362,38 @@ USB_IFACE_DESC(USB_IFACE_EMPTY) = { */ const void *const usb_strings[] = { - [USB_STR_DESC] = usb_string_desc, - [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), - [USB_STR_PRODUCT] = USB_STRING_DESC("Servo V4p1"), - [USB_STR_SERIALNO] = USB_STRING_DESC("1234-a"), - [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), - [USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"), + [USB_STR_DESC] = usb_string_desc, + [USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"), + [USB_STR_PRODUCT] = USB_STRING_DESC("Servo V4p1"), + [USB_STR_SERIALNO] = USB_STRING_DESC("1234-a"), + [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), + [USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"), [USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Servo EC Shell"), - [USB_STR_USART3_STREAM_NAME] = USB_STRING_DESC("DUT UART"), - [USB_STR_USART4_STREAM_NAME] = USB_STRING_DESC("Atmega UART"), - [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), + [USB_STR_USART3_STREAM_NAME] = USB_STRING_DESC("DUT UART"), + [USB_STR_USART4_STREAM_NAME] = USB_STRING_DESC("Atmega UART"), + [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), }; BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT); - - /****************************************************************************** * Support I2C bridging over USB. */ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "master", - .port = I2C_PORT_MASTER, - .kbps = 100, - .scl = GPIO_MASTER_I2C_SCL, - .sda = GPIO_MASTER_I2C_SDA - }, + { .name = "master", + .port = I2C_PORT_MASTER, + .kbps = 100, + .scl = GPIO_MASTER_I2C_SCL, + .sda = GPIO_MASTER_I2C_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); -int usb_i2c_board_is_enabled(void) { return 1; } - +int usb_i2c_board_is_enabled(void) +{ + return 1; +} /****************************************************************************** * Initialize board. @@ -547,18 +528,14 @@ void tick_event(void) DECLARE_HOOK(HOOK_TICK, tick_event, HOOK_PRIO_DEFAULT); struct ioexpander_config_t ioex_config[] = { - [0] = { - .drv = &tca64xxa_ioexpander_drv, + [0] = { .drv = &tca64xxa_ioexpander_drv, .i2c_host_port = TCA6416A_PORT, .i2c_addr_flags = TCA6416A_ADDR, - .flags = IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6416A - }, - [1] = { - .drv = &tca64xxa_ioexpander_drv, + .flags = IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6416A }, + [1] = { .drv = &tca64xxa_ioexpander_drv, .i2c_host_port = TCA6424A_PORT, .i2c_addr_flags = TCA6424A_ADDR, - .flags = IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6424A - } + .flags = IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6424A } }; #endif /* SECTION_IS_RO */ diff --git a/board/servo_v4p1/board.h b/board/servo_v4p1/board.h index 86367a5d0b..b6c7915c6c 100644 --- a/board/servo_v4p1/board.h +++ b/board/servo_v4p1/board.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -58,31 +58,30 @@ #define CONFIG_RAM_BANK_SIZE CONFIG_RAM_SIZE - #define CONFIG_FLASH_PSTATE #define CONFIG_FLASH_PSTATE_BANK -#define CONFIG_SHAREDLIB_SIZE 0 +#define CONFIG_SHAREDLIB_SIZE 0 -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RO_SIZE (92*1024) +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RO_SIZE (92 * 1024) -#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) -#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE +#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) +#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE -#define CONFIG_RW_MEM_OFF (CONFIG_FW_PSTATE_OFF + CONFIG_FW_PSTATE_SIZE) -#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - \ - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF)) +#define CONFIG_RW_MEM_OFF (CONFIG_FW_PSTATE_OFF + CONFIG_FW_PSTATE_SIZE) +#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RW_SIZE \ + (CONFIG_FLASH_SIZE_BYTES - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF)) -#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE +#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE /* Enable USART1,3,4 and USB streams */ #define CONFIG_STREAM_USART @@ -106,7 +105,7 @@ * STM32F072x8 Datasheet. PVD Threshold 1 corresponds to a * falling voltage threshold of min:2.09V, max:2.27V. */ -#define PVD_THRESHOLD (1) +#define PVD_THRESHOLD (1) /* USB Configuration */ #define CONFIG_USB @@ -125,23 +124,23 @@ #define DEFAULT_MAC_ADDR "Uninitialized" /* USB interface indexes (use define rather than enum to expand them) */ -#define USB_IFACE_CONSOLE 0 -#define USB_IFACE_EMPTY 1 -#define USB_IFACE_I2C 2 -#define USB_IFACE_USART3_STREAM 3 -#define USB_IFACE_USART4_STREAM 4 -#define USB_IFACE_UPDATE 5 -#define USB_IFACE_COUNT 6 +#define USB_IFACE_CONSOLE 0 +#define USB_IFACE_EMPTY 1 +#define USB_IFACE_I2C 2 +#define USB_IFACE_USART3_STREAM 3 +#define USB_IFACE_USART4_STREAM 4 +#define USB_IFACE_UPDATE 5 +#define USB_IFACE_COUNT 6 /* USB endpoint indexes (use define rather than enum to expand them) */ -#define USB_EP_CONTROL 0 -#define USB_EP_CONSOLE 1 -#define USB_EP_EMPTY 2 -#define USB_EP_I2C 3 -#define USB_EP_USART3_STREAM 4 -#define USB_EP_USART4_STREAM 5 -#define USB_EP_UPDATE 6 -#define USB_EP_COUNT 7 +#define USB_EP_CONTROL 0 +#define USB_EP_CONSOLE 1 +#define USB_EP_EMPTY 2 +#define USB_EP_I2C 3 +#define USB_EP_USART3_STREAM 4 +#define USB_EP_USART4_STREAM 5 +#define USB_EP_UPDATE 6 +#define USB_EP_COUNT 7 /* Enable console recasting of GPIO type. */ #define CONFIG_CMD_GPIO_EXTENDED @@ -182,7 +181,7 @@ /* PD features */ #define CONFIG_ADC -#undef CONFIG_ADC_WATCHDOG +#undef CONFIG_ADC_WATCHDOG #define CONFIG_BOARD_PRE_INIT /* * If task profiling is enabled then the rx falling edge detection interrupts @@ -196,7 +195,7 @@ #define CONFIG_USB_HUB_GL3590 #define CONFIG_INA231 #define CONFIG_CHARGE_MANAGER -#undef CONFIG_CHARGE_MANAGER_SAFE_MODE +#undef CONFIG_CHARGE_MANAGER_SAFE_MODE #define CONFIG_USB_MUX_TUSB1064 #define CONFIG_USB_POWER_DELIVERY #define CONFIG_USB_PD_TCPMV1 @@ -221,8 +220,8 @@ #define CONFIG_USB_PD_INITIAL_DRP_STATE PD_DRP_FORCE_SINK /* Variable-current Rp no connect and Ra attach macros */ -#define CC_NC(port, cc, sel) (pd_tcpc_cc_nc(port, cc, sel)) -#define CC_RA(port, cc, sel) (pd_tcpc_cc_ra(port, cc, sel)) +#define CC_NC(port, cc, sel) (pd_tcpc_cc_nc(port, cc, sel)) +#define CC_RA(port, cc, sel) (pd_tcpc_cc_ra(port, cc, sel)) /* * These power-supply timing values are now set towards maximum spec limit, @@ -231,14 +230,14 @@ * Currently tuned with the Apple 96W adapter. * TODO: Change to EVENT-based PS_RDY notification (b/214216304) */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY (121*MSEC) -#define PD_POWER_SUPPLY_TURN_OFF_DELAY (461*MSEC) +#define PD_POWER_SUPPLY_TURN_ON_DELAY (121 * MSEC) +#define PD_POWER_SUPPLY_TURN_OFF_DELAY (461 * MSEC) /* Define typical operating power and max power */ #define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 100000 -#define PD_MAX_CURRENT_MA 5000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_MAX_POWER_MW 100000 +#define PD_MAX_CURRENT_MA 5000 +#define PD_MAX_VOLTAGE_MV 20000 /* Add the raw option to the i2c_xfer command */ #define CONFIG_CMD_I2C_XFER_RAW @@ -266,8 +265,7 @@ /* Timer selection */ #define TIM_CLOCK32 2 -#define TIM_ADC 3 - +#define TIM_ADC 3 #include "gpio_signal.h" @@ -286,7 +284,6 @@ enum usb_strings { USB_STR_COUNT }; - /* ADC signal */ enum adc_channel { ADC_CHG_CC1_PD, diff --git a/board/servo_v4p1/build.mk b/board/servo_v4p1/build.mk index 872b4d4281..c1e8db9cd8 100644 --- a/board/servo_v4p1/build.mk +++ b/board/servo_v4p1/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2020 The Chromium OS Authors. All rights reserved. +# Copyright 2020 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/board/servo_v4p1/ccd_measure_sbu.c b/board/servo_v4p1/ccd_measure_sbu.c index b9c9680cc9..41d53ab597 100644 --- a/board/servo_v4p1/ccd_measure_sbu.c +++ b/board/servo_v4p1/ccd_measure_sbu.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,8 +11,8 @@ #include "ioexpanders.h" #include "timer.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) /* * Define voltage thresholds for SBU USB detection. @@ -20,15 +20,15 @@ * Max observed USB low across sampled systems: 666mV * Min observed USB high across sampled systems: 3026mV */ -#define GND_MAX_MV 700 -#define USB_HIGH_MV 2500 -#define SBU_DIRECT 0 -#define SBU_FLIP 1 +#define GND_MAX_MV 700 +#define USB_HIGH_MV 2500 +#define SBU_DIRECT 0 +#define SBU_FLIP 1 -#define MODE_SBU_DISCONNECT 0 -#define MODE_SBU_CONNECT 1 -#define MODE_SBU_FLIP 2 -#define MODE_SBU_OTHER 3 +#define MODE_SBU_DISCONNECT 0 +#define MODE_SBU_CONNECT 1 +#define MODE_SBU_FLIP 2 +#define MODE_SBU_OTHER 3 static void ccd_measure_sbu(void); DECLARE_DEFERRED(ccd_measure_sbu); diff --git a/board/servo_v4p1/ccd_measure_sbu.h b/board/servo_v4p1/ccd_measure_sbu.h index 0dd1ce0de7..8635f892a4 100644 --- a/board/servo_v4p1/ccd_measure_sbu.h +++ b/board/servo_v4p1/ccd_measure_sbu.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/board/servo_v4p1/chg_control.c b/board/servo_v4p1/chg_control.c index 19be03a755..76f3dc9649 100644 --- a/board/servo_v4p1/chg_control.c +++ b/board/servo_v4p1/chg_control.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,7 +10,7 @@ #include "timer.h" #include "usb_pd.h" -#define CHG_P5V_POWER 0 +#define CHG_P5V_POWER 0 #define CHG_VBUS_POWER 1 void chg_reset(void) @@ -55,9 +55,11 @@ void chg_attach_cc_rds(bool en) * Configure USB_CHG_CC1_MCU and USB_CHG_CC2_MCU as * ANALOG input */ - STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - | (3 << (2*2)) | /* PA2 in ANALOG mode */ - (3 << (2*4))); /* PA4 in ANALOG mode */ + STM32_GPIO_MODER(GPIO_A) = + (STM32_GPIO_MODER(GPIO_A) | (3 << (2 * 2)) | /* PA2 in + ANALOG + mode */ + (3 << (2 * 4))); /* PA4 in ANALOG mode */ } else { /* * Configure USB_CHG_CC1_MCU and USB_CHG_CC2_MCU as GPIO and @@ -71,10 +73,12 @@ void chg_attach_cc_rds(bool en) gpio_set_level(GPIO_USB_CHG_CC2_MCU, 1); /* Disable Analog mode and Enable GPO */ - STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - & ~(3 << (2*2) | /* PA2 disable ADC */ - 3 << (2*4))) /* PA4 disable ADC */ - | (1 << (2*2) | /* Set as GPO */ - 1 << (2*4)); /* Set as GPO */ + STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) & + ~(3 << (2 * 2) | /* PA2 disable ADC + */ + 3 << (2 * 4))) /* PA4 disable ADC + */ + | (1 << (2 * 2) | /* Set as GPO */ + 1 << (2 * 4)); /* Set as GPO */ } } diff --git a/board/servo_v4p1/chg_control.h b/board/servo_v4p1/chg_control.h index 8b81708ccc..91e3601ac8 100644 --- a/board/servo_v4p1/chg_control.h +++ b/board/servo_v4p1/chg_control.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -8,11 +8,7 @@ #include <stdbool.h> -enum chg_cc_t { - CHG_OPEN, - CHG_CC1, - CHG_CC2 -}; +enum chg_cc_t { CHG_OPEN, CHG_CC1, CHG_CC2 }; enum chg_power_select_t { CHG_POWER_OFF, diff --git a/board/servo_v4p1/dacs.c b/board/servo_v4p1/dacs.c index 838cdbbc8b..355e27684b 100644 --- a/board/servo_v4p1/dacs.c +++ b/board/servo_v4p1/dacs.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,17 +14,17 @@ #define CC1_DAC_ADDR 0x48 #define CC2_DAC_ADDR 0x49 -#define REG_NOOP 0 -#define REG_DEVID 1 -#define REG_SYNC 2 -#define REG_CONFIG 3 -#define REG_GAIN 4 +#define REG_NOOP 0 +#define REG_DEVID 1 +#define REG_SYNC 2 +#define REG_CONFIG 3 +#define REG_GAIN 4 #define REG_TRIGGER 5 -#define REG_STATUS 7 -#define REG_DAC 8 +#define REG_STATUS 7 +#define REG_DAC 8 -#define DAC1 BIT(0) -#define DAC2 BIT(1) +#define DAC1 BIT(0) +#define DAC2 BIT(1) static uint8_t dac_enabled; @@ -103,7 +103,7 @@ int write_dac(enum dac_t dac, uint16_t value) } #ifdef SECTION_IS_RO -static int cmd_cc_dac(int argc, char *argv[]) +static int cmd_cc_dac(int argc, const char *argv[]) { uint8_t dac; uint64_t mv; @@ -135,7 +135,6 @@ static int cmd_cc_dac(int argc, char *argv[]) } return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(cc_dac, cmd_cc_dac, - "dac <\"on\"|\"off\"|mv>", +DECLARE_CONSOLE_COMMAND(cc_dac, cmd_cc_dac, "dac <\"on\"|\"off\"|mv>", "Set Servo v4.1 CC dacs"); #endif diff --git a/board/servo_v4p1/dacs.h b/board/servo_v4p1/dacs.h index bd0ecd67da..4b2028c648 100644 --- a/board/servo_v4p1/dacs.h +++ b/board/servo_v4p1/dacs.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/board/servo_v4p1/ec.tasklist b/board/servo_v4p1/ec.tasklist index 07250f018e..6c9abf1c07 100644 --- a/board/servo_v4p1/ec.tasklist +++ b/board/servo_v4p1/ec.tasklist @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/board/servo_v4p1/fusb302b.c b/board/servo_v4p1/fusb302b.c index 4e144dec05..e8fdbde68b 100644 --- a/board/servo_v4p1/fusb302b.c +++ b/board/servo_v4p1/fusb302b.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -72,7 +72,6 @@ int init_fusb302b(int p) if (ret) return ret; - ret = tcpc_read(TCPC_REG_INTERRUPTA, &interrupta); if (ret) return ret; @@ -159,7 +158,6 @@ int get_cc(int *cc1, int *cc2) else orig_meas_cc2 = 0; - /* Disable CC2 measurement switch, enable CC1 measurement switch */ reg &= ~TCPC_REG_SWITCHES0_MEAS_CC2; reg |= TCPC_REG_SWITCHES0_MEAS_CC1; diff --git a/board/servo_v4p1/fusb302b.h b/board/servo_v4p1/fusb302b.h index ec89c0c207..cebf5409f5 100644 --- a/board/servo_v4p1/fusb302b.h +++ b/board/servo_v4p1/fusb302b.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -22,173 +22,173 @@ /* FUSB302B11MPX */ #define FUSB302_I2C_ADDR_B11_FLAGS 0x25 -#define TCPC_REG_DEVICE_ID 0x01 - -#define TCPC_REG_SWITCHES0 0x02 -#define TCPC_REG_SWITCHES0_CC2_PU_EN (1<<7) -#define TCPC_REG_SWITCHES0_CC1_PU_EN (1<<6) -#define TCPC_REG_SWITCHES0_VCONN_CC2 (1<<5) -#define TCPC_REG_SWITCHES0_VCONN_CC1 (1<<4) -#define TCPC_REG_SWITCHES0_MEAS_CC2 (1<<3) -#define TCPC_REG_SWITCHES0_MEAS_CC1 (1<<2) -#define TCPC_REG_SWITCHES0_CC2_PD_EN (1<<1) -#define TCPC_REG_SWITCHES0_CC1_PD_EN (1<<0) - -#define TCPC_REG_SWITCHES1 0x03 -#define TCPC_REG_SWITCHES1_POWERROLE (1<<7) -#define TCPC_REG_SWITCHES1_SPECREV1 (1<<6) -#define TCPC_REG_SWITCHES1_SPECREV0 (1<<5) -#define TCPC_REG_SWITCHES1_DATAROLE (1<<4) -#define TCPC_REG_SWITCHES1_AUTO_GCRC (1<<2) -#define TCPC_REG_SWITCHES1_TXCC2_EN (1<<1) -#define TCPC_REG_SWITCHES1_TXCC1_EN (1<<0) - -#define TCPC_REG_MEASURE 0x04 -#define TCPC_REG_MEASURE_MDAC_MASK 0x3F -#define TCPC_REG_MEASURE_VBUS (1<<6) +#define TCPC_REG_DEVICE_ID 0x01 + +#define TCPC_REG_SWITCHES0 0x02 +#define TCPC_REG_SWITCHES0_CC2_PU_EN (1 << 7) +#define TCPC_REG_SWITCHES0_CC1_PU_EN (1 << 6) +#define TCPC_REG_SWITCHES0_VCONN_CC2 (1 << 5) +#define TCPC_REG_SWITCHES0_VCONN_CC1 (1 << 4) +#define TCPC_REG_SWITCHES0_MEAS_CC2 (1 << 3) +#define TCPC_REG_SWITCHES0_MEAS_CC1 (1 << 2) +#define TCPC_REG_SWITCHES0_CC2_PD_EN (1 << 1) +#define TCPC_REG_SWITCHES0_CC1_PD_EN (1 << 0) + +#define TCPC_REG_SWITCHES1 0x03 +#define TCPC_REG_SWITCHES1_POWERROLE (1 << 7) +#define TCPC_REG_SWITCHES1_SPECREV1 (1 << 6) +#define TCPC_REG_SWITCHES1_SPECREV0 (1 << 5) +#define TCPC_REG_SWITCHES1_DATAROLE (1 << 4) +#define TCPC_REG_SWITCHES1_AUTO_GCRC (1 << 2) +#define TCPC_REG_SWITCHES1_TXCC2_EN (1 << 1) +#define TCPC_REG_SWITCHES1_TXCC1_EN (1 << 0) + +#define TCPC_REG_MEASURE 0x04 +#define TCPC_REG_MEASURE_MDAC_MASK 0x3F +#define TCPC_REG_MEASURE_VBUS (1 << 6) /* * MDAC reference voltage step size is 42 mV. Round our thresholds to reduce * maximum error, which also matches suggested thresholds in datasheet * (Table 3. Host Interrupt Summary). */ -#define TCPC_REG_MEASURE_MDAC_MV(mv) (DIV_ROUND_NEAREST((mv), 42) & 0x3f) - -#define TCPC_REG_CONTROL0 0x06 -#define TCPC_REG_CONTROL0_TX_FLUSH (1<<6) -#define TCPC_REG_CONTROL0_INT_MASK (1<<5) -#define TCPC_REG_CONTROL0_HOST_CUR_MASK (3<<2) -#define TCPC_REG_CONTROL0_HOST_CUR_3A0 (3<<2) -#define TCPC_REG_CONTROL0_HOST_CUR_1A5 (2<<2) -#define TCPC_REG_CONTROL0_HOST_CUR_USB (1<<2) -#define TCPC_REG_CONTROL0_TX_START (1<<0) - -#define TCPC_REG_CONTROL1 0x07 -#define TCPC_REG_CONTROL1_ENSOP2DB (1<<6) -#define TCPC_REG_CONTROL1_ENSOP1DB (1<<5) -#define TCPC_REG_CONTROL1_BIST_MODE2 (1<<4) -#define TCPC_REG_CONTROL1_RX_FLUSH (1<<2) -#define TCPC_REG_CONTROL1_ENSOP2 (1<<1) -#define TCPC_REG_CONTROL1_ENSOP1 (1<<0) - -#define TCPC_REG_CONTROL2 0x08 +#define TCPC_REG_MEASURE_MDAC_MV(mv) (DIV_ROUND_NEAREST((mv), 42) & 0x3f) + +#define TCPC_REG_CONTROL0 0x06 +#define TCPC_REG_CONTROL0_TX_FLUSH (1 << 6) +#define TCPC_REG_CONTROL0_INT_MASK (1 << 5) +#define TCPC_REG_CONTROL0_HOST_CUR_MASK (3 << 2) +#define TCPC_REG_CONTROL0_HOST_CUR_3A0 (3 << 2) +#define TCPC_REG_CONTROL0_HOST_CUR_1A5 (2 << 2) +#define TCPC_REG_CONTROL0_HOST_CUR_USB (1 << 2) +#define TCPC_REG_CONTROL0_TX_START (1 << 0) + +#define TCPC_REG_CONTROL1 0x07 +#define TCPC_REG_CONTROL1_ENSOP2DB (1 << 6) +#define TCPC_REG_CONTROL1_ENSOP1DB (1 << 5) +#define TCPC_REG_CONTROL1_BIST_MODE2 (1 << 4) +#define TCPC_REG_CONTROL1_RX_FLUSH (1 << 2) +#define TCPC_REG_CONTROL1_ENSOP2 (1 << 1) +#define TCPC_REG_CONTROL1_ENSOP1 (1 << 0) + +#define TCPC_REG_CONTROL2 0x08 /* two-bit field, valid values below */ -#define TCPC_REG_CONTROL2_MODE_MASK (0x3<<TCPC_REG_CONTROL2_MODE_POS) -#define TCPC_REG_CONTROL2_MODE_DFP (0x3) -#define TCPC_REG_CONTROL2_MODE_UFP (0x2) -#define TCPC_REG_CONTROL2_MODE_DRP (0x1) -#define TCPC_REG_CONTROL2_MODE_POS (1) -#define TCPC_REG_CONTROL2_TOGGLE (1<<0) - -#define TCPC_REG_CONTROL3 0x09 -#define TCPC_REG_CONTROL3_SEND_HARDRESET (1<<6) -#define TCPC_REG_CONTROL3_BIST_TMODE (1<<5) /* 302B Only */ -#define TCPC_REG_CONTROL3_AUTO_HARDRESET (1<<4) -#define TCPC_REG_CONTROL3_AUTO_SOFTRESET (1<<3) +#define TCPC_REG_CONTROL2_MODE_MASK (0x3 << TCPC_REG_CONTROL2_MODE_POS) +#define TCPC_REG_CONTROL2_MODE_DFP (0x3) +#define TCPC_REG_CONTROL2_MODE_UFP (0x2) +#define TCPC_REG_CONTROL2_MODE_DRP (0x1) +#define TCPC_REG_CONTROL2_MODE_POS (1) +#define TCPC_REG_CONTROL2_TOGGLE (1 << 0) + +#define TCPC_REG_CONTROL3 0x09 +#define TCPC_REG_CONTROL3_SEND_HARDRESET (1 << 6) +#define TCPC_REG_CONTROL3_BIST_TMODE (1 << 5) /* 302B Only */ +#define TCPC_REG_CONTROL3_AUTO_HARDRESET (1 << 4) +#define TCPC_REG_CONTROL3_AUTO_SOFTRESET (1 << 3) /* two-bit field */ -#define TCPC_REG_CONTROL3_N_RETRIES (1<<1) -#define TCPC_REG_CONTROL3_N_RETRIES_POS (1) -#define TCPC_REG_CONTROL3_N_RETRIES_SIZE (2) -#define TCPC_REG_CONTROL3_AUTO_RETRY (1<<0) - -#define TCPC_REG_MASK 0x0A -#define TCPC_REG_MASK_VBUSOK (1<<7) -#define TCPC_REG_MASK_ACTIVITY (1<<6) -#define TCPC_REG_MASK_COMP_CHNG (1<<5) -#define TCPC_REG_MASK_CRC_CHK (1<<4) -#define TCPC_REG_MASK_ALERT (1<<3) -#define TCPC_REG_MASK_WAKE (1<<2) -#define TCPC_REG_MASK_COLLISION (1<<1) -#define TCPC_REG_MASK_BC_LVL (1<<0) - -#define TCPC_REG_POWER 0x0B -#define TCPC_REG_POWER_PWR (1<<0) /* four-bit field */ -#define TCPC_REG_POWER_PWR_LOW 0x1 /* Bandgap + Wake circuitry */ -#define TCPC_REG_POWER_PWR_MEDIUM 0x3 /* LOW + Receiver + Current refs */ -#define TCPC_REG_POWER_PWR_HIGH 0x7 /* MEDIUM + Measure block */ -#define TCPC_REG_POWER_PWR_ALL 0xF /* HIGH + Internal Oscillator */ - -#define TCPC_REG_RESET 0x0C -#define TCPC_REG_RESET_PD_RESET (1<<1) -#define TCPC_REG_RESET_SW_RESET (1<<0) - -#define TCPC_REG_MASKA 0x0E -#define TCPC_REG_MASKA_OCP_TEMP (1<<7) -#define TCPC_REG_MASKA_TOGDONE (1<<6) -#define TCPC_REG_MASKA_SOFTFAIL (1<<5) -#define TCPC_REG_MASKA_RETRYFAIL (1<<4) -#define TCPC_REG_MASKA_HARDSENT (1<<3) -#define TCPC_REG_MASKA_TX_SUCCESS (1<<2) -#define TCPC_REG_MASKA_SOFTRESET (1<<1) -#define TCPC_REG_MASKA_HARDRESET (1<<0) - -#define TCPC_REG_MASKB 0x0F -#define TCPC_REG_MASKB_GCRCSENT (1<<0) - -#define TCPC_REG_STATUS0A 0x3C -#define TCPC_REG_STATUS0A_SOFTFAIL (1<<5) -#define TCPC_REG_STATUS0A_RETRYFAIL (1<<4) -#define TCPC_REG_STATUS0A_POWER (1<<2) /* two-bit field */ -#define TCPC_REG_STATUS0A_RX_SOFT_RESET (1<<1) -#define TCPC_REG_STATUS0A_RX_HARD_RESEt (1<<0) - -#define TCPC_REG_STATUS1A 0x3D +#define TCPC_REG_CONTROL3_N_RETRIES (1 << 1) +#define TCPC_REG_CONTROL3_N_RETRIES_POS (1) +#define TCPC_REG_CONTROL3_N_RETRIES_SIZE (2) +#define TCPC_REG_CONTROL3_AUTO_RETRY (1 << 0) + +#define TCPC_REG_MASK 0x0A +#define TCPC_REG_MASK_VBUSOK (1 << 7) +#define TCPC_REG_MASK_ACTIVITY (1 << 6) +#define TCPC_REG_MASK_COMP_CHNG (1 << 5) +#define TCPC_REG_MASK_CRC_CHK (1 << 4) +#define TCPC_REG_MASK_ALERT (1 << 3) +#define TCPC_REG_MASK_WAKE (1 << 2) +#define TCPC_REG_MASK_COLLISION (1 << 1) +#define TCPC_REG_MASK_BC_LVL (1 << 0) + +#define TCPC_REG_POWER 0x0B +#define TCPC_REG_POWER_PWR (1 << 0) /* four-bit field */ +#define TCPC_REG_POWER_PWR_LOW 0x1 /* Bandgap + Wake circuitry */ +#define TCPC_REG_POWER_PWR_MEDIUM 0x3 /* LOW + Receiver + Current refs */ +#define TCPC_REG_POWER_PWR_HIGH 0x7 /* MEDIUM + Measure block */ +#define TCPC_REG_POWER_PWR_ALL 0xF /* HIGH + Internal Oscillator */ + +#define TCPC_REG_RESET 0x0C +#define TCPC_REG_RESET_PD_RESET (1 << 1) +#define TCPC_REG_RESET_SW_RESET (1 << 0) + +#define TCPC_REG_MASKA 0x0E +#define TCPC_REG_MASKA_OCP_TEMP (1 << 7) +#define TCPC_REG_MASKA_TOGDONE (1 << 6) +#define TCPC_REG_MASKA_SOFTFAIL (1 << 5) +#define TCPC_REG_MASKA_RETRYFAIL (1 << 4) +#define TCPC_REG_MASKA_HARDSENT (1 << 3) +#define TCPC_REG_MASKA_TX_SUCCESS (1 << 2) +#define TCPC_REG_MASKA_SOFTRESET (1 << 1) +#define TCPC_REG_MASKA_HARDRESET (1 << 0) + +#define TCPC_REG_MASKB 0x0F +#define TCPC_REG_MASKB_GCRCSENT (1 << 0) + +#define TCPC_REG_STATUS0A 0x3C +#define TCPC_REG_STATUS0A_SOFTFAIL (1 << 5) +#define TCPC_REG_STATUS0A_RETRYFAIL (1 << 4) +#define TCPC_REG_STATUS0A_POWER (1 << 2) /* two-bit field */ +#define TCPC_REG_STATUS0A_RX_SOFT_RESET (1 << 1) +#define TCPC_REG_STATUS0A_RX_HARD_RESEt (1 << 0) + +#define TCPC_REG_STATUS1A 0x3D /* three-bit field, valid values below */ -#define TCPC_REG_STATUS1A_TOGSS (1<<3) -#define TCPC_REG_STATUS1A_TOGSS_RUNNING 0x0 -#define TCPC_REG_STATUS1A_TOGSS_SRC1 0x1 -#define TCPC_REG_STATUS1A_TOGSS_SRC2 0x2 -#define TCPC_REG_STATUS1A_TOGSS_SNK1 0x5 -#define TCPC_REG_STATUS1A_TOGSS_SNK2 0x6 -#define TCPC_REG_STATUS1A_TOGSS_AA 0x7 -#define TCPC_REG_STATUS1A_TOGSS_POS (3) -#define TCPC_REG_STATUS1A_TOGSS_MASK (0x7) - -#define TCPC_REG_STATUS1A_RXSOP2DB (1<<2) -#define TCPC_REG_STATUS1A_RXSOP1DB (1<<1) -#define TCPC_REG_STATUS1A_RXSOP (1<<0) - -#define TCPC_REG_INTERRUPTA 0x3E -#define TCPC_REG_INTERRUPTA_OCP_TEMP (1<<7) -#define TCPC_REG_INTERRUPTA_TOGDONE (1<<6) -#define TCPC_REG_INTERRUPTA_SOFTFAIL (1<<5) -#define TCPC_REG_INTERRUPTA_RETRYFAIL (1<<4) -#define TCPC_REG_INTERRUPTA_HARDSENT (1<<3) -#define TCPC_REG_INTERRUPTA_TX_SUCCESS (1<<2) -#define TCPC_REG_INTERRUPTA_SOFTRESET (1<<1) -#define TCPC_REG_INTERRUPTA_HARDRESET (1<<0) - -#define TCPC_REG_INTERRUPTB 0x3F -#define TCPC_REG_INTERRUPTB_GCRCSENT (1<<0) - -#define TCPC_REG_STATUS0 0x40 -#define TCPC_REG_STATUS0_VBUSOK (1<<7) -#define TCPC_REG_STATUS0_ACTIVITY (1<<6) -#define TCPC_REG_STATUS0_COMP (1<<5) -#define TCPC_REG_STATUS0_CRC_CHK (1<<4) -#define TCPC_REG_STATUS0_ALERT (1<<3) -#define TCPC_REG_STATUS0_WAKE (1<<2) -#define TCPC_REG_STATUS0_BC_LVL1 (1<<1) /* two-bit field */ -#define TCPC_REG_STATUS0_BC_LVL0 (1<<0) /* two-bit field */ - -#define TCPC_REG_STATUS1 0x41 -#define TCPC_REG_STATUS1_RXSOP2 (1<<7) -#define TCPC_REG_STATUS1_RXSOP1 (1<<6) -#define TCPC_REG_STATUS1_RX_EMPTY (1<<5) -#define TCPC_REG_STATUS1_RX_FULL (1<<4) -#define TCPC_REG_STATUS1_TX_EMPTY (1<<3) -#define TCPC_REG_STATUS1_TX_FULL (1<<2) - -#define TCPC_REG_INTERRUPT 0x42 -#define TCPC_REG_INTERRUPT_VBUSOK (1<<7) -#define TCPC_REG_INTERRUPT_ACTIVITY (1<<6) -#define TCPC_REG_INTERRUPT_COMP_CHNG (1<<5) -#define TCPC_REG_INTERRUPT_CRC_CHK (1<<4) -#define TCPC_REG_INTERRUPT_ALERT (1<<3) -#define TCPC_REG_INTERRUPT_WAKE (1<<2) -#define TCPC_REG_INTERRUPT_COLLISION (1<<1) -#define TCPC_REG_INTERRUPT_BC_LVL (1<<0) - -#define TCPC_REG_FIFOS 0x43 +#define TCPC_REG_STATUS1A_TOGSS (1 << 3) +#define TCPC_REG_STATUS1A_TOGSS_RUNNING 0x0 +#define TCPC_REG_STATUS1A_TOGSS_SRC1 0x1 +#define TCPC_REG_STATUS1A_TOGSS_SRC2 0x2 +#define TCPC_REG_STATUS1A_TOGSS_SNK1 0x5 +#define TCPC_REG_STATUS1A_TOGSS_SNK2 0x6 +#define TCPC_REG_STATUS1A_TOGSS_AA 0x7 +#define TCPC_REG_STATUS1A_TOGSS_POS (3) +#define TCPC_REG_STATUS1A_TOGSS_MASK (0x7) + +#define TCPC_REG_STATUS1A_RXSOP2DB (1 << 2) +#define TCPC_REG_STATUS1A_RXSOP1DB (1 << 1) +#define TCPC_REG_STATUS1A_RXSOP (1 << 0) + +#define TCPC_REG_INTERRUPTA 0x3E +#define TCPC_REG_INTERRUPTA_OCP_TEMP (1 << 7) +#define TCPC_REG_INTERRUPTA_TOGDONE (1 << 6) +#define TCPC_REG_INTERRUPTA_SOFTFAIL (1 << 5) +#define TCPC_REG_INTERRUPTA_RETRYFAIL (1 << 4) +#define TCPC_REG_INTERRUPTA_HARDSENT (1 << 3) +#define TCPC_REG_INTERRUPTA_TX_SUCCESS (1 << 2) +#define TCPC_REG_INTERRUPTA_SOFTRESET (1 << 1) +#define TCPC_REG_INTERRUPTA_HARDRESET (1 << 0) + +#define TCPC_REG_INTERRUPTB 0x3F +#define TCPC_REG_INTERRUPTB_GCRCSENT (1 << 0) + +#define TCPC_REG_STATUS0 0x40 +#define TCPC_REG_STATUS0_VBUSOK (1 << 7) +#define TCPC_REG_STATUS0_ACTIVITY (1 << 6) +#define TCPC_REG_STATUS0_COMP (1 << 5) +#define TCPC_REG_STATUS0_CRC_CHK (1 << 4) +#define TCPC_REG_STATUS0_ALERT (1 << 3) +#define TCPC_REG_STATUS0_WAKE (1 << 2) +#define TCPC_REG_STATUS0_BC_LVL1 (1 << 1) /* two-bit field */ +#define TCPC_REG_STATUS0_BC_LVL0 (1 << 0) /* two-bit field */ + +#define TCPC_REG_STATUS1 0x41 +#define TCPC_REG_STATUS1_RXSOP2 (1 << 7) +#define TCPC_REG_STATUS1_RXSOP1 (1 << 6) +#define TCPC_REG_STATUS1_RX_EMPTY (1 << 5) +#define TCPC_REG_STATUS1_RX_FULL (1 << 4) +#define TCPC_REG_STATUS1_TX_EMPTY (1 << 3) +#define TCPC_REG_STATUS1_TX_FULL (1 << 2) + +#define TCPC_REG_INTERRUPT 0x42 +#define TCPC_REG_INTERRUPT_VBUSOK (1 << 7) +#define TCPC_REG_INTERRUPT_ACTIVITY (1 << 6) +#define TCPC_REG_INTERRUPT_COMP_CHNG (1 << 5) +#define TCPC_REG_INTERRUPT_CRC_CHK (1 << 4) +#define TCPC_REG_INTERRUPT_ALERT (1 << 3) +#define TCPC_REG_INTERRUPT_WAKE (1 << 2) +#define TCPC_REG_INTERRUPT_COLLISION (1 << 1) +#define TCPC_REG_INTERRUPT_BC_LVL (1 << 0) + +#define TCPC_REG_FIFOS 0x43 /* Tokens defined for the FUSB302 TX FIFO */ enum fusb302_txfifo_tokens { diff --git a/board/servo_v4p1/gpio.inc b/board/servo_v4p1/gpio.inc index 070aa90098..fe631aca80 100644 --- a/board/servo_v4p1/gpio.inc +++ b/board/servo_v4p1/gpio.inc @@ -1,6 +1,6 @@ /* -*- mode:c -*- * - * Copyright 2020 The Chromium OS Authors. All rights reserved. + * Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/board/servo_v4p1/ina231s.c b/board/servo_v4p1/ina231s.c index 3382686f3f..637a878ef7 100644 --- a/board/servo_v4p1/ina231s.c +++ b/board/servo_v4p1/ina231s.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -7,9 +7,9 @@ #include "ina2xx.h" #include "util.h" -#define PP_DUT_IDX 0 -#define PP_CHG_IDX 1 -#define SR_CHG_IDX 2 +#define PP_DUT_IDX 0 +#define PP_CHG_IDX 1 +#define SR_CHG_IDX 2 void init_ina231s(void) { diff --git a/board/servo_v4p1/ina231s.h b/board/servo_v4p1/ina231s.h index 9c3804e769..6f0828127b 100644 --- a/board/servo_v4p1/ina231s.h +++ b/board/servo_v4p1/ina231s.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/board/servo_v4p1/ioexpanders.c b/board/servo_v4p1/ioexpanders.c index 46dcbcc167..275804de89 100644 --- a/board/servo_v4p1/ioexpanders.c +++ b/board/servo_v4p1/ioexpanders.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,22 +9,22 @@ #include "ioexpander.h" #include "ioexpanders.h" -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) /****************************************************************************** * Initialize IOExpanders. */ -#define PCAL6524HE_PORT TCA6424A_PORT -#define PCAL6524HE_ADDR TCA6424A_ADDR -#define PCAL6524HE_DEVICE_ID_ADDR 0x7c -#define PCAL6524HE_DEVICE_ID_REG 0x46 -#define PCAL6524HE_DEVICE_ID0 0 -#define PCAL6524HE_DEVICE_ID1 0x08 -#define PCAL6524HE_DEVICE_ID2 0x30 -#define PCAL6524HE_INT_MASK_REG_PORT1 0x55 -#define PCAL6524HE_INT_MASK_REG_PORT2 0x56 +#define PCAL6524HE_PORT TCA6424A_PORT +#define PCAL6524HE_ADDR TCA6424A_ADDR +#define PCAL6524HE_DEVICE_ID_ADDR 0x7c +#define PCAL6524HE_DEVICE_ID_REG 0x46 +#define PCAL6524HE_DEVICE_ID0 0 +#define PCAL6524HE_DEVICE_ID1 0x08 +#define PCAL6524HE_DEVICE_ID2 0x30 +#define PCAL6524HE_INT_MASK_REG_PORT1 0x55 +#define PCAL6524HE_INT_MASK_REG_PORT2 0x56 static enum servo_board_id board_id_val = BOARD_ID_UNSET; @@ -51,16 +51,16 @@ int init_ioexpanders(void) /* Attempt to read the device id register of the PCAL6524HE device */ i2c_read_block(PCAL6524HE_PORT, PCAL6524HE_DEVICE_ID_ADDR, - PCAL6524HE_DEVICE_ID_REG, dat, 3); + PCAL6524HE_DEVICE_ID_REG, dat, 3); if (dat[2] == PCAL6524HE_DEVICE_ID2 && - dat[1] == PCAL6524HE_DEVICE_ID1 && - dat[0] == PCAL6524HE_DEVICE_ID0) { + dat[1] == PCAL6524HE_DEVICE_ID1 && + dat[0] == PCAL6524HE_DEVICE_ID0) { ccprintf("Detected PCAL6524HE\n"); i2c_write8(PCAL6524HE_PORT, PCAL6524HE_ADDR, - PCAL6524HE_INT_MASK_REG_PORT1, 0); + PCAL6524HE_INT_MASK_REG_PORT1, 0); i2c_write8(PCAL6524HE_PORT, PCAL6524HE_ADDR, - PCAL6524HE_INT_MASK_REG_PORT2, 0xbe); + PCAL6524HE_INT_MASK_REG_PORT2, 0xbe); } else { ccprintf("Detected TCA6424A\n"); } @@ -74,7 +74,7 @@ int init_ioexpanders(void) } if ((!!(irqs & HOST_CHRG_DET) != bc12_charger) && - (board_id_det() <= BOARD_ID_REV1)) { + (board_id_det() <= BOARD_ID_REV1)) { CPRINTF("BC1.2 charger %s\n", (irqs & HOST_CHRG_DET) ? "plugged" : "unplugged"); bc12_charger = !!(irqs & HOST_CHRG_DET); @@ -220,8 +220,7 @@ inline int board_id_det(void) /* Cache board ID at init */ if (ioex_get_port(IOEX_GET_INFO(IOEX_BOARD_ID_DET0)->ioex, - IOEX_GET_INFO(IOEX_BOARD_ID_DET0)->port, - &id)) + IOEX_GET_INFO(IOEX_BOARD_ID_DET0)->port, &id)) return id; /* Board ID consists of bits 5, 4, and 3 */ @@ -296,8 +295,7 @@ inline int read_faults(void) int val; ioex_get_port(IOEX_GET_INFO(IOEX_USERVO_FAULT_L)->ioex, - IOEX_GET_INFO(IOEX_USERVO_FAULT_L)->port, - &val); + IOEX_GET_INFO(IOEX_USERVO_FAULT_L)->port, &val); return val; } @@ -307,8 +305,7 @@ inline int read_irqs(void) int val; ioex_get_port(IOEX_GET_INFO(IOEX_SYS_PWR_IRQ_ODL)->ioex, - IOEX_GET_INFO(IOEX_SYS_PWR_IRQ_ODL)->port, - &val); + IOEX_GET_INFO(IOEX_SYS_PWR_IRQ_ODL)->port, &val); return val; } @@ -343,9 +340,7 @@ inline int board_id_det(void) int res; /* Cache board ID at init */ - res = i2c_read8(TCA6416A_PORT, - TCA6416A_ADDR, - BOARD_ID_DET_PORT, + res = i2c_read8(TCA6416A_PORT, TCA6416A_ADDR, BOARD_ID_DET_PORT, &id); if (res != EC_SUCCESS) return res; diff --git a/board/servo_v4p1/ioexpanders.h b/board/servo_v4p1/ioexpanders.h index 6565992857..313fea46a4 100644 --- a/board/servo_v4p1/ioexpanders.h +++ b/board/servo_v4p1/ioexpanders.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,10 +10,7 @@ #define BOARD_ID_DET_OFFSET 3 #define BOARD_ID_DET_PORT 1 -enum uservo_fastboot_mux_sel_t { - MUX_SEL_USERVO = 0, - MUX_SEL_FASTBOOT = 1 -}; +enum uservo_fastboot_mux_sel_t { MUX_SEL_USERVO = 0, MUX_SEL_FASTBOOT = 1 }; /* * Initialize Ioexpanders @@ -236,14 +233,14 @@ int get_dut_chg_en(void); */ int host_or_chg_ctl(int en); -#define USERVO_FAULT_L BIT(0) -#define USB3_A0_FAULT_L BIT(1) -#define USB3_A1_FAULT_L BIT(2) -#define USB_DUTCHG_FLT_ODL BIT(3) -#define PP3300_DP_FAULT_L BIT(4) -#define DAC_BUF1_LATCH_FAULT_L BIT(5) -#define DAC_BUF2_LATCH_FAULT_L BIT(6) -#define PP5000_SRC_SEL BIT(7) +#define USERVO_FAULT_L BIT(0) +#define USB3_A0_FAULT_L BIT(1) +#define USB3_A1_FAULT_L BIT(2) +#define USB_DUTCHG_FLT_ODL BIT(3) +#define PP3300_DP_FAULT_L BIT(4) +#define DAC_BUF1_LATCH_FAULT_L BIT(5) +#define DAC_BUF2_LATCH_FAULT_L BIT(6) +#define PP5000_SRC_SEL BIT(7) /** * Read any faults that may have occurred. A fault has occurred if the @@ -271,8 +268,8 @@ int host_or_chg_ctl(int en); */ int read_faults(void); -#define HOST_CHRG_DET BIT(0) -#define SYS_PWR_IRQ_ODL BIT(6) +#define HOST_CHRG_DET BIT(0) +#define SYS_PWR_IRQ_ODL BIT(6) /** * Read irqs which indicate some system event. diff --git a/board/servo_v4p1/pathsel.c b/board/servo_v4p1/pathsel.c index 7b71fba169..eba1733e05 100644 --- a/board/servo_v4p1/pathsel.c +++ b/board/servo_v4p1/pathsel.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/board/servo_v4p1/pathsel.h b/board/servo_v4p1/pathsel.h index 7365d3adf3..5f228aceb9 100644 --- a/board/servo_v4p1/pathsel.h +++ b/board/servo_v4p1/pathsel.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/board/servo_v4p1/pi3usb9201.c b/board/servo_v4p1/pi3usb9201.c index 102eaf790d..976c213c49 100644 --- a/board/servo_v4p1/pi3usb9201.c +++ b/board/servo_v4p1/pi3usb9201.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -6,7 +6,7 @@ #include "i2c.h" #include "pi3usb9201.h" -#define PI3USB9201_ADDR 0x5f +#define PI3USB9201_ADDR 0x5f inline void init_pi3usb9201(void) { @@ -19,7 +19,7 @@ inline void init_pi3usb9201(void) } inline void write_pi3usb9201(enum pi3usb9201_reg_t reg, - enum pi3usb9201_dat_t dat) + enum pi3usb9201_dat_t dat) { i2c_write8(1, PI3USB9201_ADDR, reg, dat); } diff --git a/board/servo_v4p1/pi3usb9201.h b/board/servo_v4p1/pi3usb9201.h index 826db8b871..863fc4129a 100644 --- a/board/servo_v4p1/pi3usb9201.h +++ b/board/servo_v4p1/pi3usb9201.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -6,35 +6,29 @@ #ifndef __CROS_EC_PI3USB9201_H #define __CROS_EC_PI3USB9201_H -enum pi3usb9201_reg_t { - CTRL_REG1, - CTRL_REG2, - CLIENT_STATUS, - HOST_STATUS -}; +enum pi3usb9201_reg_t { CTRL_REG1, CTRL_REG2, CLIENT_STATUS, HOST_STATUS }; enum pi3usb9201_dat_t { - POWER_DOWN = 0x0, - SDP_HOST_MODE = 0x2, - DCP_HOST_MODE = 0x4, - CDP_HOST_MODE = 0x6, - CLIENT_MODE = 0x8, - USB_PATH_ON = 0xe + POWER_DOWN = 0x0, + SDP_HOST_MODE = 0x2, + DCP_HOST_MODE = 0x4, + CDP_HOST_MODE = 0x6, + CLIENT_MODE = 0x8, + USB_PATH_ON = 0xe }; - /* Client Status bits */ -#define CS_DCP BIT(7) -#define CS_SDP BIT(6) -#define CS_CDP BIT(5) -#define CS_1A_CHARGER BIT(3) -#define CS_2A_CHARGER BIT(2) -#define CS_2_4A_CHARGER BIT(1) +#define CS_DCP BIT(7) +#define CS_SDP BIT(6) +#define CS_CDP BIT(5) +#define CS_1A_CHARGER BIT(3) +#define CS_2A_CHARGER BIT(2) +#define CS_2_4A_CHARGER BIT(1) /* Host Status bits */ -#define HS_USB_UNPLUGGED BIT(2) -#define HS_USB_PLUGGED BIT(1) -#define HS_BC1_2 BIT(0) +#define HS_USB_UNPLUGGED BIT(2) +#define HS_USB_PLUGGED BIT(1) +#define HS_BC1_2 BIT(0) /** * Selects Client Mode and client mode detection diff --git a/board/servo_v4p1/usb_pd_config.h b/board/servo_v4p1/usb_pd_config.h index 7e97d68a11..e65ed3cd62 100644 --- a/board/servo_v4p1/usb_pd_config.h +++ b/board/servo_v4p1/usb_pd_config.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -47,26 +47,27 @@ #define CONFIG_HW_CRC /* Servo v4 CC configuration */ -#define CC_DETACH BIT(0) /* Emulate detach: both CC open */ -#define CC_DISABLE_DTS BIT(1) /* Apply resistors to single or both CC? */ -#define CC_ALLOW_SRC BIT(2) /* Allow charge through by policy? */ -#define CC_ENABLE_DRP BIT(3) /* Enable dual-role port */ -#define CC_SNK_WITH_PD BIT(4) /* Force enabling PD comm for sink role */ -#define CC_POLARITY BIT(5) /* CC polarity */ -#define CC_EMCA_SERVO BIT(6) /* - * Emulate Electronically Marked Cable Assembly - * (EMCA) servo (or non-EMCA) - */ -#define CC_FASTBOOT_DFP BIT(7) /* Allow mux uServo->Fastboot on DFP */ +#define CC_DETACH BIT(0) /* Emulate detach: both CC open */ +#define CC_DISABLE_DTS BIT(1) /* Apply resistors to single or both CC? */ +#define CC_ALLOW_SRC BIT(2) /* Allow charge through by policy? */ +#define CC_ENABLE_DRP BIT(3) /* Enable dual-role port */ +#define CC_SNK_WITH_PD BIT(4) /* Force enabling PD comm for sink role */ +#define CC_POLARITY BIT(5) /* CC polarity */ +#define CC_EMCA_SERVO \ + BIT(6) /* \ + * Emulate Electronically Marked Cable Assembly \ + * (EMCA) servo (or non-EMCA) \ + */ +#define CC_FASTBOOT_DFP BIT(7) /* Allow mux uServo->Fastboot on DFP */ /* Servo v4 DP alt-mode configuration */ -#define ALT_DP_ENABLE BIT(0) /* Enable DP alt-mode or not */ -#define ALT_DP_PIN_C BIT(1) /* Pin assignment C supported */ -#define ALT_DP_PIN_D BIT(2) /* Pin assignment D supported */ -#define ALT_DP_MF_PREF BIT(3) /* Multi-Function preferred */ -#define ALT_DP_PLUG BIT(4) /* Plug or receptacle */ -#define ALT_DP_OVERRIDE_HPD BIT(5) /* Override the HPD signal */ -#define ALT_DP_HPD_LVL BIT(6) /* HPD level if overridden */ +#define ALT_DP_ENABLE BIT(0) /* Enable DP alt-mode or not */ +#define ALT_DP_PIN_C BIT(1) /* Pin assignment C supported */ +#define ALT_DP_PIN_D BIT(2) /* Pin assignment D supported */ +#define ALT_DP_MF_PREF BIT(3) /* Multi-Function preferred */ +#define ALT_DP_PLUG BIT(4) /* Plug or receptacle */ +#define ALT_DP_OVERRIDE_HPD BIT(5) /* Override the HPD signal */ +#define ALT_DP_HPD_LVL BIT(6) /* HPD level if overridden */ /* TX uses SPI1 on PB3-4 for CHG port, SPI2 on PB 13-14 for DUT port */ #define SPI_REGS(p) ((p) ? STM32_SPI2_REGS : STM32_SPI1_REGS) @@ -89,14 +90,14 @@ static inline void spi_enable_clock(int port) #define TIM_TX_CCR_IDX(p) ((p) ? TIM_TX_CCR_DUT : TIM_TX_CCR_CHG) #define TIM_RX_CCR_IDX(p) ((p) ? TIM_RX_CCR_DUT : TIM_RX_CCR_CHG) -#define TIM_CCR_CS 1 +#define TIM_CCR_CS 1 /* * EXTI line 21 is connected to the CMP1 output, * EXTI line 22 is connected to the CMP2 output, * CHG uses CMP2, and DUT uses CMP1. */ -#define EXTI_COMP_MASK(p) ((p) ? (1<<21) : BIT(22)) +#define EXTI_COMP_MASK(p) ((p) ? (1 << 21) : BIT(22)) #define IRQ_COMP STM32_IRQ_COMP /* triggers packet detection on comparator falling edge */ @@ -188,13 +189,25 @@ static inline void pd_select_polarity(int port, int polarity) if (port == CHG) { /* CHG use the right comparator inverted input for COMP2 */ STM32_COMP_CSR = (val & ~STM32_COMP_CMP2INSEL_MASK) | - (polarity ? STM32_COMP_CMP2INSEL_INM4 /* PA4: C0_CC2 */ - : STM32_COMP_CMP2INSEL_INM6);/* PA2: C0_CC1 */ + (polarity ? + STM32_COMP_CMP2INSEL_INM4 /* PA4: + C0_CC2 + */ + : + STM32_COMP_CMP2INSEL_INM6); /* PA2: + C0_CC1 + */ } else { /* DUT use the right comparator inverted input for COMP1 */ STM32_COMP_CSR = (val & ~STM32_COMP_CMP1INSEL_MASK) | - (polarity ? STM32_COMP_CMP1INSEL_INM5 /* PA5: C1_CC2 */ - : STM32_COMP_CMP1INSEL_INM6);/* PA0: C1_CC1 */ + (polarity ? + STM32_COMP_CMP1INSEL_INM5 /* PA5: + C1_CC2 + */ + : + STM32_COMP_CMP1INSEL_INM6); /* PA0: + C1_CC1 + */ } } @@ -274,7 +287,6 @@ static inline void pd_config_init(int port, uint8_t power_role) /* Initialize TX pins and put them in Hi-Z */ pd_tx_init(); - } int pd_adc_read(int port, int cc); diff --git a/board/servo_v4p1/usb_pd_policy.c b/board/servo_v4p1/usb_pd_policy.c index 26dc64c7d5..98d6255c29 100644 --- a/board/servo_v4p1/usb_pd_policy.c +++ b/board/servo_v4p1/usb_pd_policy.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -26,57 +26,59 @@ #include "usb_pd_config.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) -#define DUT_PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\ - PDO_FIXED_COMM_CAP) +#define DUT_PDO_FIXED_FLAGS \ + (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP) #define CHG_PDO_FIXED_FLAGS (PDO_FIXED_DATA_SWAP) -#define VBUS_UNCHANGED(curr, pend, new) (curr == new && pend == new) +#define VBUS_UNCHANGED(curr, pend, new) (curr == new &&pend == new) /* Macros to config the PD role */ #define CONF_SET_CLEAR(c, set, clear) ((c | (set)) & ~(clear)) -#define CONF_SRC(c) CONF_SET_CLEAR(c, \ - CC_DISABLE_DTS | CC_ALLOW_SRC, \ - CC_ENABLE_DRP | CC_SNK_WITH_PD) -#define CONF_SNK(c) CONF_SET_CLEAR(c, \ - CC_DISABLE_DTS, \ - CC_ALLOW_SRC | CC_ENABLE_DRP | CC_SNK_WITH_PD) -#define CONF_PDSNK(c) CONF_SET_CLEAR(c, \ - CC_DISABLE_DTS | CC_SNK_WITH_PD, \ - CC_ALLOW_SRC | CC_ENABLE_DRP) -#define CONF_DRP(c) CONF_SET_CLEAR(c, \ - CC_DISABLE_DTS | CC_ALLOW_SRC | CC_ENABLE_DRP, \ - CC_SNK_WITH_PD) -#define CONF_SRCDTS(c) CONF_SET_CLEAR(c, \ - CC_ALLOW_SRC, \ - CC_ENABLE_DRP | CC_DISABLE_DTS | CC_SNK_WITH_PD) -#define CONF_SNKDTS(c) CONF_SET_CLEAR(c, \ - 0, \ - CC_ALLOW_SRC | CC_ENABLE_DRP | \ - CC_DISABLE_DTS | CC_SNK_WITH_PD) -#define CONF_PDSNKDTS(c) CONF_SET_CLEAR(c, \ - CC_SNK_WITH_PD, \ - CC_ALLOW_SRC | CC_ENABLE_DRP | CC_DISABLE_DTS) -#define CONF_DRPDTS(c) CONF_SET_CLEAR(c, \ - CC_ALLOW_SRC | CC_ENABLE_DRP, \ - CC_DISABLE_DTS | CC_SNK_WITH_PD) +#define CONF_SRC(c) \ + CONF_SET_CLEAR(c, CC_DISABLE_DTS | CC_ALLOW_SRC, \ + CC_ENABLE_DRP | CC_SNK_WITH_PD) +#define CONF_SNK(c) \ + CONF_SET_CLEAR(c, CC_DISABLE_DTS, \ + CC_ALLOW_SRC | CC_ENABLE_DRP | CC_SNK_WITH_PD) +#define CONF_PDSNK(c) \ + CONF_SET_CLEAR(c, CC_DISABLE_DTS | CC_SNK_WITH_PD, \ + CC_ALLOW_SRC | CC_ENABLE_DRP) +#define CONF_DRP(c) \ + CONF_SET_CLEAR(c, CC_DISABLE_DTS | CC_ALLOW_SRC | CC_ENABLE_DRP, \ + CC_SNK_WITH_PD) +#define CONF_SRCDTS(c) \ + CONF_SET_CLEAR(c, CC_ALLOW_SRC, \ + CC_ENABLE_DRP | CC_DISABLE_DTS | CC_SNK_WITH_PD) +#define CONF_SNKDTS(c) \ + CONF_SET_CLEAR(c, 0, \ + CC_ALLOW_SRC | CC_ENABLE_DRP | CC_DISABLE_DTS | \ + CC_SNK_WITH_PD) +#define CONF_PDSNKDTS(c) \ + CONF_SET_CLEAR(c, CC_SNK_WITH_PD, \ + CC_ALLOW_SRC | CC_ENABLE_DRP | CC_DISABLE_DTS) +#define CONF_DRPDTS(c) \ + CONF_SET_CLEAR(c, CC_ALLOW_SRC | CC_ENABLE_DRP, \ + CC_DISABLE_DTS | CC_SNK_WITH_PD) +#define CONF_DTSOFF(c) CONF_SET_CLEAR(c, CC_DISABLE_DTS, 0) +#define CONF_DTSON(c) CONF_SET_CLEAR(c, 0, CC_DISABLE_DTS) /* Macros to apply Rd/Rp to CC lines */ -#define DUT_ACTIVE_CC_SET(r, flags) \ - gpio_set_flags(cc_config & CC_POLARITY ? \ - CONCAT2(GPIO_USB_DUT_CC2_, r) : \ - CONCAT2(GPIO_USB_DUT_CC1_, r), \ +#define DUT_ACTIVE_CC_SET(r, flags) \ + gpio_set_flags(cc_config &CC_POLARITY ? \ + CONCAT2(GPIO_USB_DUT_CC2_, r) : \ + CONCAT2(GPIO_USB_DUT_CC1_, r), \ flags) -#define DUT_INACTIVE_CC_SET(r, flags) \ - gpio_set_flags(cc_config & CC_POLARITY ? \ - CONCAT2(GPIO_USB_DUT_CC1_, r) : \ - CONCAT2(GPIO_USB_DUT_CC2_, r), \ +#define DUT_INACTIVE_CC_SET(r, flags) \ + gpio_set_flags(cc_config &CC_POLARITY ? \ + CONCAT2(GPIO_USB_DUT_CC1_, r) : \ + CONCAT2(GPIO_USB_DUT_CC2_, r), \ flags) -#define DUT_BOTH_CC_SET(r, flags) \ - do { \ +#define DUT_BOTH_CC_SET(r, flags) \ + do { \ gpio_set_flags(CONCAT2(GPIO_USB_DUT_CC1_, r), flags); \ gpio_set_flags(CONCAT2(GPIO_USB_DUT_CC2_, r), flags); \ } while (0) @@ -98,15 +100,15 @@ * than 5V. */ static const uint16_t pd_src_voltages_mv[] = { - 5000, 9000, 10000, 12000, 15000, 20000, + 5000, 9000, 10000, 12000, 15000, 20000, }; static uint32_t pd_src_chg_pdo[ARRAY_SIZE(pd_src_voltages_mv)]; static uint8_t chg_pdo_cnt; const uint32_t pd_snk_pdo[] = { - PDO_FIXED(5000, 500, CHG_PDO_FIXED_FLAGS), - PDO_BATT(4750, 21000, 15000), - PDO_VAR(4750, 21000, 3000), + PDO_FIXED(5000, 500, CHG_PDO_FIXED_FLAGS), + PDO_BATT(4750, 21000, 15000), + PDO_VAR(4750, 21000, 3000), }; const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo); @@ -123,15 +125,15 @@ static int cc_config = CC_ALLOW_SRC | CC_EMCA_SERVO; /* Voltage thresholds for no connect in DTS mode */ static int pd_src_vnc_dts[TYPEC_RP_RESERVED][2] = { - {PD_SRC_3_0_VNC_MV, PD_SRC_1_5_VNC_MV}, - {PD_SRC_1_5_VNC_MV, PD_SRC_DEF_VNC_MV}, - {PD_SRC_3_0_VNC_MV, PD_SRC_DEF_VNC_MV}, + { PD_SRC_3_0_VNC_MV, PD_SRC_1_5_VNC_MV }, + { PD_SRC_1_5_VNC_MV, PD_SRC_DEF_VNC_MV }, + { PD_SRC_3_0_VNC_MV, PD_SRC_DEF_VNC_MV }, }; /* Voltage thresholds for Ra attach in DTS mode */ static int pd_src_rd_threshold_dts[TYPEC_RP_RESERVED][2] = { - {PD_SRC_3_0_RD_THRESH_MV, PD_SRC_1_5_RD_THRESH_MV}, - {PD_SRC_1_5_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV}, - {PD_SRC_3_0_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV}, + { PD_SRC_3_0_RD_THRESH_MV, PD_SRC_1_5_RD_THRESH_MV }, + { PD_SRC_1_5_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV }, + { PD_SRC_3_0_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV }, }; /* Voltage thresholds for no connect in normal SRC mode */ static int pd_src_vnc[TYPEC_RP_RESERVED] = { @@ -291,8 +293,8 @@ static void update_ports(void) break; /* Find the 'best' PDO <= voltage */ - pdo_index = - pd_find_pdo_index(pd_get_src_cap_cnt(CHG), + pdo_index = pd_find_pdo_index( + pd_get_src_cap_cnt(CHG), pd_get_src_caps(CHG), pd_src_voltages_mv[i], &pdo); /* Don't duplicate PDOs */ @@ -315,9 +317,9 @@ static void update_ports(void) } else { /* 5V PDO */ pd_src_chg_pdo[0] = PDO_FIXED_VOLT(PD_MIN_MV) | - PDO_FIXED_CURR(vbus[CHG].ma) | - DUT_PDO_FIXED_FLAGS | - PDO_FIXED_UNCONSTRAINED; + PDO_FIXED_CURR(vbus[CHG].ma) | + DUT_PDO_FIXED_FLAGS | + PDO_FIXED_UNCONSTRAINED; chg_pdo_cnt = 1; } @@ -342,8 +344,8 @@ int board_set_active_charge_port(int charge_port) return 0; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { if (port != CHG) return; @@ -389,8 +391,9 @@ int pd_tcpc_cc_nc(int port, int cc_volt, int cc_sel) if (cc_config & CC_DISABLE_DTS) nc = cc_volt >= pd_src_vnc[rp_index]; else - nc = cc_volt >= pd_src_vnc_dts[rp_index][ - cc_config & CC_POLARITY ? !cc_sel : cc_sel]; + nc = cc_volt >= + pd_src_vnc_dts[rp_index] + [cc_config & CC_POLARITY ? !cc_sel : cc_sel]; return nc; } @@ -416,8 +419,10 @@ int pd_tcpc_cc_ra(int port, int cc_volt, int cc_sel) if (cc_config & CC_DISABLE_DTS) ra = cc_volt < pd_src_rd_threshold[rp_index]; else - ra = cc_volt < pd_src_rd_threshold_dts[rp_index][ - cc_config & CC_POLARITY ? !cc_sel : cc_sel]; + ra = cc_volt < + pd_src_rd_threshold_dts[rp_index] + [cc_config & CC_POLARITY ? !cc_sel : + cc_sel]; return ra; } @@ -459,13 +464,11 @@ int pd_adc_read(int port, int cc) * * This is basically a hack faking "vOpen" from TCPCI spec. */ - if ((cc_config & CC_DISABLE_DTS) && - port == DUT && + if ((cc_config & CC_DISABLE_DTS) && port == DUT && cc == ((cc_config & CC_POLARITY) ? 0 : 1)) { - - if ((cc_pull_stored == TYPEC_CC_RD) || - (cc_pull_stored == TYPEC_CC_RA) || - (cc_pull_stored == TYPEC_CC_RA_RD)) + if ((cc_pull_stored == TYPEC_CC_RD) || + (cc_pull_stored == TYPEC_CC_RA) || + (cc_pull_stored == TYPEC_CC_RA_RD)) mv = -1; else if (cc_pull_stored == TYPEC_CC_RP) mv = 3301; @@ -594,7 +597,7 @@ int pd_set_rp_rd(int port, int cc_pull, int rp_value) if (cc_pull == TYPEC_CC_RP) { rv = board_set_rp(rp_value); } else if ((cc_pull == TYPEC_CC_RD) || (cc_pull == TYPEC_CC_RA_RD) || - (cc_pull == TYPEC_CC_RA)) { + (cc_pull == TYPEC_CC_RA)) { /* * The DUT port uses a captive cable. It can present Rd on both * CC1 and CC2. If DTS mode is enabled, then present Rd on both @@ -673,7 +676,7 @@ int charge_manager_get_source_pdo(const uint32_t **src_pdo, const int port) * port, otherwise we provide no power. */ if (charge_port_is_active()) { - *src_pdo = pd_src_chg_pdo; + *src_pdo = pd_src_chg_pdo; pdo_cnt = chg_pdo_cnt; } @@ -697,8 +700,7 @@ __override void pd_transition_voltage(int idx) /* Wait for CHG transition */ deadline.val = get_time().val + PD_T_PS_TRANSITION; CPRINTS("Waiting for CHG port transition"); - while (charge_port_is_active() && - vbus[CHG].mv != mv && + while (charge_port_is_active() && vbus[CHG].mv != mv && get_time().val < deadline.val) msleep(10); @@ -760,8 +762,7 @@ void pd_power_supply_reset(int port) int pd_snk_is_vbus_provided(int port) { - return gpio_get_level(port ? GPIO_USB_DET_PP_DUT : - GPIO_USB_DET_PP_CHG); + return gpio_get_level(port ? GPIO_USB_DET_PP_DUT : GPIO_USB_DET_PP_CHG); } __override int pd_check_power_swap(int port) @@ -778,7 +779,8 @@ __override int pd_check_power_swap(int port) if (port == CHG) return 0; - if (pd_get_power_role(port) == PD_ROLE_SINK && !(cc_config & CC_ALLOW_SRC)) + if (pd_get_power_role(port) == PD_ROLE_SINK && + !(cc_config & CC_ALLOW_SRC)) return 0; if (pd_snk_is_vbus_provided(CHG)) @@ -787,8 +789,7 @@ __override int pd_check_power_swap(int port) return 0; } -__override int pd_check_data_swap(int port, - enum pd_data_role data_role) +__override int pd_check_data_swap(int port, enum pd_data_role data_role) { /* * Servo should allow data role swaps to let DUT see the USB hub, but @@ -800,8 +801,7 @@ __override int pd_check_data_swap(int port, return allow_dr_swap; } -__override void pd_execute_data_swap(int port, - enum pd_data_role data_role) +__override void pd_execute_data_swap(int port, enum pd_data_role data_role) { if (port == CHG) return; @@ -838,12 +838,12 @@ __override void pd_execute_data_swap(int port, uservo_to_host(); break; default: - CPRINTS("C%d: %s: Invalid data_role:%d", port, __func__, data_role); + CPRINTS("C%d: %s: Invalid data_role:%d", port, __func__, + data_role); } } -__override void pd_check_pr_role(int port, - enum pd_power_role pr_role, +__override void pd_check_pr_role(int port, enum pd_power_role pr_role, int flags) { /* @@ -854,9 +854,7 @@ __override void pd_check_pr_role(int port, */ } -__override void pd_check_dr_role(int port, - enum pd_data_role dr_role, - int flags) +__override void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags) { if (port == CHG) return; @@ -866,15 +864,14 @@ __override void pd_check_dr_role(int port, pd_request_data_swap(port); } - /* ----------------- Vendor Defined Messages ------------------ */ /* * DP alt-mode config, user configurable. * Default is the mode disabled, supporting the C and D pin assignment, * multi-function preferred, and a plug. */ -static int alt_dp_config = (ALT_DP_PIN_C | ALT_DP_PIN_D | ALT_DP_MF_PREF | - ALT_DP_PLUG); +static int alt_dp_config = + (ALT_DP_PIN_C | ALT_DP_PIN_D | ALT_DP_MF_PREF | ALT_DP_PLUG); /** * Get the pins based on the user config. @@ -907,8 +904,8 @@ const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */ const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV); const uint32_t vdo_ama = VDO_AMA(CONFIG_USB_PD_IDENTITY_HW_VERS, - CONFIG_USB_PD_IDENTITY_SW_VERS, - 0, 0, 0, 0, /* SS[TR][12] */ + CONFIG_USB_PD_IDENTITY_SW_VERS, 0, 0, 0, + 0, /* SS[TR][12] */ 0, /* Vconn power */ 0, /* Vconn power required */ 0, /* Vbus power required */ @@ -946,13 +943,13 @@ uint32_t vdo_dp_mode[MODE_CNT]; static int svdm_response_modes(int port, uint32_t *payload) { - vdo_dp_mode[0] = - VDO_MODE_DP(0, /* UFP pin cfg supported: none */ - alt_dp_config_pins(), /* DFP pin */ - 1, /* no usb2.0 signalling in AMode */ - alt_dp_config_cable(), /* plug or receptacle */ - MODE_DP_V13, /* DPv1.3 Support, no Gen2 */ - MODE_DP_SNK); /* Its a sink only */ + vdo_dp_mode[0] = VDO_MODE_DP(0, /* UFP pin cfg supported: none */ + alt_dp_config_pins(), /* DFP pin */ + 1, /* no usb2.0 signalling in AMode */ + alt_dp_config_cable(), /* plug or + receptacle */ + MODE_DP_V13, /* DPv1.3 Support, no Gen2 */ + MODE_DP_SNK); /* Its a sink only */ /* CCD uses the SBU lines; don't enable DP when dts-mode enabled */ if (!(cc_config & CC_DISABLE_DTS)) @@ -1007,17 +1004,18 @@ static int dp_status(int port, uint32_t *payload) int dp_enabled = !!(state & USB_PD_MUX_DP_ENABLED); if (opos != OPOS) - return 0; /* NAK */ - - payload[1] = VDO_DP_STATUS( - 0, /* IRQ_HPD */ - hpd, /* HPD_HI|LOW */ - 0, /* request exit DP */ - 0, /* request exit USB */ - (alt_dp_config & ALT_DP_MF_PREF) != 0, /* MF pref */ - dp_enabled, - 0, /* power low */ - hpd ? 0x2 : 0); + return 0; /* NAK */ + + payload[1] = + VDO_DP_STATUS(0, /* IRQ_HPD */ + hpd, /* HPD_HI|LOW */ + 0, /* request exit DP */ + 0, /* request exit USB */ + (alt_dp_config & ALT_DP_MF_PREF) != 0, /* MF + pref + */ + dp_enabled, 0, /* power low */ + hpd ? 0x2 : 0); return 2; } @@ -1038,7 +1036,7 @@ static int svdm_enter_mode(int port, uint32_t *payload) /* SID & mode request is valid */ if ((PD_VDO_VID(payload[0]) != USB_SID_DISPLAYPORT) || (PD_VDO_OPOS(payload[0]) != OPOS)) - return 0; /* NAK */ + return 0; /* NAK */ alt_mode = OPOS; return 1; @@ -1080,7 +1078,7 @@ const struct svdm_response svdm_rsp = { }; __override int pd_custom_vdm(int port, int cnt, uint32_t *payload, - uint32_t **rpayload) + uint32_t **rpayload) { int cmd = PD_VDO_CMD(payload[0]); @@ -1092,7 +1090,7 @@ __override int pd_custom_vdm(int port, int cnt, uint32_t *payload, case VDO_CMD_VERSION: /* guarantee last byte of payload is null character */ *(payload + cnt - 1) = 0; - CPRINTF("ver: %s\n", (char *)(payload+1)); + CPRINTF("ver: %s\n", (char *)(payload + 1)); break; case VDO_CMD_CURRENT: CPRINTF("Current: %dmA\n", payload[1]); @@ -1110,18 +1108,15 @@ static void print_cc_mode(void) /* Get current CCD status */ ccprintf("cc: %s\n", cc_config & CC_DETACH ? "off" : "on"); ccprintf("dts mode: %s\n", cc_config & CC_DISABLE_DTS ? "off" : "on"); - ccprintf("chg mode: %s\n", - get_dut_chg_en() ? "on" : "off"); + ccprintf("chg mode: %s\n", get_dut_chg_en() ? "on" : "off"); ccprintf("chg allowed: %s\n", cc_config & CC_ALLOW_SRC ? "on" : "off"); ccprintf("drp enabled: %s\n", cc_config & CC_ENABLE_DRP ? "on" : "off"); - ccprintf("cc polarity: %s\n", cc_config & CC_POLARITY ? "cc2" : - "cc1"); + ccprintf("cc polarity: %s\n", cc_config & CC_POLARITY ? "cc2" : "cc1"); ccprintf("pd enabled: %s\n", pd_comm_is_enabled(DUT) ? "on" : "off"); - ccprintf("emca: %s\n", cc_config & CC_EMCA_SERVO ? - "emarked" : "non-emarked"); + ccprintf("emca: %s\n", + cc_config & CC_EMCA_SERVO ? "emarked" : "non-emarked"); } - static void do_cc(int cc_config_new) { int chargeable; @@ -1192,7 +1187,7 @@ static void do_cc(int cc_config_new) } } -static int command_cc(int argc, char **argv) +static int command_cc(int argc, const char **argv) { int cc_config_new = cc_config; @@ -1223,6 +1218,10 @@ static int command_cc(int argc, char **argv) cc_config_new = CONF_PDSNKDTS(cc_config_new); else if (!strcasecmp(argv[1], "drpdts")) cc_config_new = CONF_DRPDTS(cc_config_new); + else if (!strcasecmp(argv[1], "dtsoff")) + cc_config_new = CONF_DTSOFF(cc_config_new); + else if (!strcasecmp(argv[1], "dtson")) + cc_config_new = CONF_DTSON(cc_config_new); else if (!strcasecmp(argv[1], "emca")) cc_config_new |= CC_EMCA_SERVO; else if (!strcasecmp(argv[1], "nonemca")) @@ -1245,7 +1244,7 @@ static int command_cc(int argc, char **argv) } DECLARE_CONSOLE_COMMAND(cc, command_cc, "[off|on|src|snk|pdsnk|drp|srcdts|snkdts|pdsnkdts|" - "drpdts|emca|nonemca] [cc1|cc2]", + "drpdts|dtsoff|dtson|emca|nonemca] [cc1|cc2]", "Servo_v4 DTS and CHG mode"); static void fake_disconnect_end(void) @@ -1265,7 +1264,7 @@ static void fake_disconnect_start(void) } DECLARE_DEFERRED(fake_disconnect_start); -static int cmd_fake_disconnect(int argc, char *argv[]) +static int cmd_fake_disconnect(int argc, const char *argv[]) { int delay_ms, duration_ms; char *e; @@ -1287,18 +1286,18 @@ static int cmd_fake_disconnect(int argc, char *argv[]) fake_pd_disconnect_duration_us = duration_ms * MSEC; hook_call_deferred(&fake_disconnect_start_data, delay_ms * MSEC); - ccprintf("Fake disconnect for %d ms starting in %d ms.\n", - duration_ms, delay_ms); + ccprintf("Fake disconnect for %d ms starting in %d ms.\n", duration_ms, + delay_ms); return EC_SUCCESS; } DECLARE_CONSOLE_COMMAND(fakedisconnect, cmd_fake_disconnect, "<delay_ms> <duration_ms>", NULL); -static int cmd_ada_srccaps(int argc, char *argv[]) +static int cmd_ada_srccaps(int argc, const char *argv[]) { int i; - const uint32_t * const ada_srccaps = pd_get_src_caps(CHG); + const uint32_t *const ada_srccaps = pd_get_src_caps(CHG); for (i = 0; i < pd_get_src_cap_cnt(CHG); ++i) { uint32_t max_ma, max_mv, unused; @@ -1314,11 +1313,10 @@ static int cmd_ada_srccaps(int argc, char *argv[]) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(ada_srccaps, cmd_ada_srccaps, - "", +DECLARE_CONSOLE_COMMAND(ada_srccaps, cmd_ada_srccaps, "", "Print adapter SrcCap"); -static int cmd_dp_action(int argc, char *argv[]) +static int cmd_dp_action(int argc, const char *argv[]) { int i; char *e; @@ -1354,8 +1352,7 @@ static int cmd_dp_action(int argc, char *argv[]) } } } - CPRINTS("Pins: %s%s", - (alt_dp_config & ALT_DP_PIN_C) ? "C" : "", + CPRINTS("Pins: %s%s", (alt_dp_config & ALT_DP_PIN_C) ? "C" : "", (alt_dp_config & ALT_DP_PIN_D) ? "D" : ""); } else if (!strcasecmp(argv[1], "mf")) { if (argc >= 3) { @@ -1405,10 +1402,10 @@ static int cmd_dp_action(int argc, char *argv[]) } } CPRINTS("HPD source: %s", - (alt_dp_config & ALT_DP_OVERRIDE_HPD) ? "overridden" - : "external"); + (alt_dp_config & ALT_DP_OVERRIDE_HPD) ? "overridden" : + "external"); CPRINTS("HPD level: %d", get_hpd_level()); - } else if (!strcasecmp(argv[1], "help")) { + } else if (!strcasecmp(argv[1], "help")) { CPRINTS("Usage: usbc_action dp [enable|disable|hpd|mf|pins|" "plug]"); } @@ -1416,7 +1413,7 @@ static int cmd_dp_action(int argc, char *argv[]) return EC_SUCCESS; } -static int cmd_usbc_action(int argc, char *argv[]) +static int cmd_usbc_action(int argc, const char *argv[]) { if (argc >= 2 && !strcasecmp(argv[1], "dp")) return cmd_dp_action(argc - 1, &argv[1]); diff --git a/board/servo_v4p1/usb_sm.c b/board/servo_v4p1/usb_sm.c index 94b5e0c08d..4c448b7c9d 100644 --- a/board/servo_v4p1/usb_sm.c +++ b/board/servo_v4p1/usb_sm.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,8 +11,8 @@ #include "util.h" #ifdef CONFIG_COMMON_RUNTIME -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USB, format, ##args) #else /* CONFIG_COMMON_RUNTIME */ #define CPRINTF(format, args...) #define CPRINTS(format, args...) @@ -22,8 +22,8 @@ struct internal_ctx { usb_state_ptr last_entered; uint32_t running : 1; - uint32_t enter : 1; - uint32_t exit : 1; + uint32_t enter : 1; + uint32_t exit : 1; }; BUILD_ASSERT(sizeof(struct internal_ctx) == member_size(struct sm_ctx, internal)); @@ -64,9 +64,9 @@ static usb_state_ptr shared_parent_state(usb_state_ptr a, usb_state_ptr b) * functions. */ static void call_entry_functions(const int port, - struct internal_ctx *const internal, - const usb_state_ptr stop, - const usb_state_ptr current) + struct internal_ctx *const internal, + const usb_state_ptr stop, + const usb_state_ptr current) { if (current == stop) return; @@ -91,7 +91,7 @@ static void call_entry_functions(const int port, * during an exit function. */ static void call_exit_functions(const int port, const usb_state_ptr stop, - const usb_state_ptr current) + const usb_state_ptr current) { if (current == stop) return; @@ -105,7 +105,7 @@ static void call_exit_functions(const int port, const usb_state_ptr stop, void set_state(const int port, struct sm_ctx *const ctx, const usb_state_ptr new_state) { - struct internal_ctx * const internal = (void *) ctx->internal; + struct internal_ctx *const internal = (void *)ctx->internal; usb_state_ptr last_state; usb_state_ptr shared_parent; @@ -115,8 +115,8 @@ void set_state(const int port, struct sm_ctx *const ctx, * intended state to transition into. */ if (internal->exit) { - CPRINTF("C%d: Ignoring set state to 0x%pP within 0x%pP", - port, new_state, ctx->current); + CPRINTF("C%d: Ignoring set state to 0x%p within 0x%p", port, + new_state, ctx->current); return; } @@ -167,8 +167,8 @@ void set_state(const int port, struct sm_ctx *const ctx, * functions. */ static void call_run_functions(const int port, - const struct internal_ctx *const internal, - const usb_state_ptr current) + const struct internal_ctx *const internal, + const usb_state_ptr current) { if (!current) return; @@ -185,7 +185,7 @@ static void call_run_functions(const int port, void run_state(const int port, struct sm_ctx *const ctx) { - struct internal_ctx * const internal = (void *) ctx->internal; + struct internal_ctx *const internal = (void *)ctx->internal; internal->running = true; call_run_functions(port, internal, ctx->current); diff --git a/board/servo_v4p1/usb_tc_snk_sm.c b/board/servo_v4p1/usb_tc_snk_sm.c index 95586943bf..d76c2fe24f 100644 --- a/board/servo_v4p1/usb_tc_snk_sm.c +++ b/board/servo_v4p1/usb_tc_snk_sm.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,15 +14,15 @@ #include "usb_sm.h" #include "usb_tc_sm.h" -#define EVT_TIMEOUT_NEVER (-1) -#define EVT_TIMEOUT_5MS (5 * MSEC) +#define EVT_TIMEOUT_NEVER (-1) +#define EVT_TIMEOUT_5MS (5 * MSEC) /* * USB Type-C Sink * See Figure 4-13 in Release 1.4 of USB Type-C Spec. */ -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* Type-C Layer Flags */ @@ -36,9 +36,9 @@ enum usb_tc_state { static const struct usb_state tc_states[]; /* TypeC Power strings */ -static const char * const pwr2_5_str = "5V/0.5A"; -static const char * const pwr7_5_str = "5V/1.5A"; -static const char * const pwr15_str = "5V/3A"; +static const char *const pwr2_5_str = "5V/0.5A"; +static const char *const pwr7_5_str = "5V/1.5A"; +static const char *const pwr15_str = "5V/3A"; static struct type_c { /* state machine context */ @@ -101,8 +101,8 @@ static void print_alt_power(void) char const *pwr; cc = tc.polarity ? tc.cc2 : tc.cc1; - if (cc == TYPEC_CC_VOLT_OPEN || - cc == TYPEC_CC_VOLT_RA || cc == TYPEC_CC_VOLT_RD) { + if (cc == TYPEC_CC_VOLT_OPEN || cc == TYPEC_CC_VOLT_RA || + cc == TYPEC_CC_VOLT_RD) { /* Supply removed or not detected */ return; } |