summaryrefslogtreecommitdiff
path: root/chip/it83xx
diff options
context:
space:
mode:
Diffstat (limited to 'chip/it83xx')
-rw-r--r--chip/it83xx/build.mk2
-rw-r--r--chip/it83xx/clock.c17
-rw-r--r--chip/it83xx/ec2i.c2
-rw-r--r--chip/it83xx/i2c.c261
-rw-r--r--chip/it83xx/intc.c2
-rw-r--r--chip/it83xx/intc.h3
-rw-r--r--chip/it83xx/lpc.c12
-rw-r--r--chip/it83xx/registers.h17
-rw-r--r--chip/it83xx/system.c2
9 files changed, 288 insertions, 30 deletions
diff --git a/chip/it83xx/build.mk b/chip/it83xx/build.mk
index bbff9f009b..cffd7c68f8 100644
--- a/chip/it83xx/build.mk
+++ b/chip/it83xx/build.mk
@@ -29,7 +29,7 @@ chip-$(CONFIG_PWM)+=pwm.o
chip-$(CONFIG_ADC)+=adc.o
chip-$(CONFIG_DAC)+=dac.o
chip-$(CONFIG_HOSTCMD_X86)+=lpc.o ec2i.o
-chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o
+chip-$(CONFIG_HOST_INTERFACE_ESPI)+=espi.o
chip-$(CONFIG_SPI_CONTROLLER)+=spi_master.o
chip-$(CONFIG_SPI)+=spi.o
chip-$(CONFIG_PECI)+=peci.o
diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c
index 41f800721a..c1e9df4265 100644
--- a/chip/it83xx/clock.c
+++ b/chip/it83xx/clock.c
@@ -232,7 +232,7 @@ static void clock_set_pll(enum pll_freq_idx idx)
ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ,
1, 1, 5, 1, 0);
task_clear_pending_irq(et_ctrl_regs[LOW_POWER_EXT_TIMER].irq);
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
/*
* Workaround for (b:70537592):
* We have to set chip select pin as input mode in order to
@@ -249,7 +249,7 @@ static void clock_set_pll(enum pll_freq_idx idx)
#endif
/* Update PLL settings. */
clock_pll_changed();
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
#ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
/* Enable eSPI pad after changing PLL sequence. */
espi_enable_pad(1);
@@ -301,7 +301,8 @@ void clock_init(void)
*/
IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & 0x3F) + 0x40;
-#if defined(IT83XX_ESPI_RESET_MODULE_BY_FW) && defined(CONFIG_HOSTCMD_ESPI)
+#if defined(IT83XX_ESPI_RESET_MODULE_BY_FW) && \
+ defined(CONFIG_HOST_INTERFACE_ESPI)
/*
* Because we don't support eSPI HW reset function (b/111480168) on DX
* version, so we have to reset eSPI configurations during init to
@@ -539,7 +540,7 @@ void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
/* EC sleep */
ec_sleep = 1;
#if defined(IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED) && \
-defined(CONFIG_HOSTCMD_ESPI)
+defined(CONFIG_HOST_INTERFACE_ESPI)
/* Disable eSPI pad. */
espi_enable_pad(0);
#endif
@@ -565,7 +566,7 @@ void clock_sleep_mode_wakeup_isr(void)
/* trigger a reboot if wake up EC from sleep mode (system hibernate) */
if (clock_ec_wake_from_sleep()) {
#if defined(IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED) && \
-defined(CONFIG_HOSTCMD_ESPI)
+defined(CONFIG_HOST_INTERFACE_ESPI)
/*
* Enable eSPI pad.
* We will not need to enable eSPI pad here if Dx is able to
@@ -636,6 +637,12 @@ void __ram_code __idle(void)
while (1) {
/* Disable interrupts */
interrupt_disable();
+#ifdef CONFIG_IT83XX_I2C_CMD_QUEUE
+ if (i2c_idle_not_allowed()) {
+ interrupt_enable();
+ continue;
+ }
+#endif
/* Check if the EC can enter deep doze mode or not */
if (DEEP_SLEEP_ALLOWED && clock_allow_low_power_idle()) {
/* reset low power mode hw timer */
diff --git a/chip/it83xx/ec2i.c b/chip/it83xx/ec2i.c
index be02a8f813..5542d455a9 100644
--- a/chip/it83xx/ec2i.c
+++ b/chip/it83xx/ec2i.c
@@ -20,7 +20,7 @@ static const struct ec2i_t keyboard_settings[] = {
/* Set IRQ=01h for logical device */
{HOST_INDEX_IRQNUMX, 0x01},
/* Configure IRQTP for KBC. */
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
/*
* Interrupt request type select (IRQTP) for KBC.
* bit 1, 0: IRQ request is buffered and applied to SERIRQ
diff --git a/chip/it83xx/i2c.c b/chip/it83xx/i2c.c
index 5aa8f8a460..836ee7a82f 100644
--- a/chip/it83xx/i2c.c
+++ b/chip/it83xx/i2c.c
@@ -21,6 +21,48 @@
/* Default maximum time we allow for an I2C transfer */
#define I2C_TIMEOUT_DEFAULT_US (100 * MSEC)
+#ifdef CONFIG_IT83XX_I2C_CMD_QUEUE
+
+#ifdef CHIP_CORE_NDS32
+#error "Remapping DLM base is required on it8320 series"
+#endif
+
+/* It is allowed to configure the size up to 2K bytes. */
+#define I2C_CQ_MODE_MAX_PAYLOAD_SIZE 128
+/* reserved 5 bytes for ID and CMD_x */
+#define I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE (I2C_CQ_MODE_MAX_PAYLOAD_SIZE - 5)
+uint8_t i2c_cq_mode_tx_dlm[I2C_ENHANCED_PORT_COUNT]
+ [I2C_CQ_MODE_MAX_PAYLOAD_SIZE] __aligned(4);
+uint8_t i2c_cq_mode_rx_dlm[I2C_ENHANCED_PORT_COUNT]
+ [I2C_CQ_MODE_MAX_PAYLOAD_SIZE] __aligned(4);
+
+/* Repeat Start */
+#define I2C_CQ_CMD_L_RS BIT(7)
+/*
+ * R/W (Read/ Write) decides the I2C read or write direction
+ * 1: read, 0: write
+ */
+#define I2C_CQ_CMD_L_RW BIT(6)
+/* P (STOP) is the I2C STOP condition */
+#define I2C_CQ_CMD_L_P BIT(5)
+/* E (End) is this device end flag */
+#define I2C_CQ_CMD_L_E BIT(4)
+/* LA (Last ACK) is Last ACK in master receiver */
+#define I2C_CQ_CMD_L_LA BIT(3)
+/* bit[2:0] are number of transfer out or receive data which depends on R/W. */
+#define I2C_CQ_CMD_L_NUM_BIT_2_0 GENMASK(2, 0)
+
+struct i2c_cq_packet {
+ uint8_t id;
+ uint8_t cmd_l;
+ uint8_t cmd_h;
+ uint8_t wdata[0];
+};
+
+/* Preventing CPU going into idle mode during command queue I2C transaction. */
+static uint32_t i2c_idle_disabled;
+#endif /* CONFIG_IT83XX_I2C_CMD_QUEUE */
+
enum enhanced_i2c_transfer_direct {
TX_DIRECT,
RX_DIRECT,
@@ -98,6 +140,8 @@ enum enhanced_i2c_ctl {
E_START_ID = (E_INT_EN | E_MODE_SEL | E_ACK | E_START | E_HW_RST),
/* Generate stop condition */
E_FINISH = (E_INT_EN | E_MODE_SEL | E_ACK | E_STOP | E_HW_RST),
+ /* start with command queue mode */
+ E_START_CQ = (E_INT_EN | E_MODE_SEL | E_ACK | E_START),
};
enum i2c_reset_cause {
@@ -587,11 +631,199 @@ static int enhanced_i2c_error(int p)
return pd->err;
}
-static int i2c_transaction(int p)
+#ifdef CONFIG_IT83XX_I2C_CMD_QUEUE
+static void enhanced_i2c_set_cmd_addr_regs(int p)
+{
+ int dlm_index = p - I2C_STANDARD_PORT_COUNT;
+ int p_ch = i2c_ch_reg_shift(p);
+ uint32_t dlm_base;
+
+ /* set "Address Register" to store the I2C data */
+ dlm_base = (uint32_t)&i2c_cq_mode_rx_dlm[dlm_index] & 0xffffff;
+ IT83XX_I2C_RAMH2A(p_ch) = (dlm_base >> 16) & 0xff;
+ IT83XX_I2C_RAMHA(p_ch) = (dlm_base >> 8) & 0xff;
+ IT83XX_I2C_RAMLA(p_ch) = dlm_base & 0xff;
+
+ /* Set "Command Address Register" to get commands */
+ dlm_base = (uint32_t)&i2c_cq_mode_tx_dlm[dlm_index] & 0xffffff;
+ IT83XX_I2C_CMD_ADDH2(p_ch) = (dlm_base >> 16) & 0xff;
+ IT83XX_I2C_CMD_ADDH(p_ch) = (dlm_base >> 8) & 0xff;
+ IT83XX_I2C_CMD_ADDL(p_ch) = dlm_base & 0xff;
+}
+
+static void i2c_enable_idle(int port)
+{
+ i2c_idle_disabled &= ~BIT(port);
+}
+
+static void i2c_disable_idle(int port)
+{
+ i2c_idle_disabled |= BIT(port);
+}
+
+uint32_t i2c_idle_not_allowed(void)
+{
+ return i2c_idle_disabled;
+}
+
+static int command_i2c_idle_mask(int argc, char **argv)
+{
+ ccprintf("i2c idle mask: %08x\n", i2c_idle_disabled);
+
+ return EC_SUCCESS;
+}
+DECLARE_SAFE_CONSOLE_COMMAND(i2cidlemask, command_i2c_idle_mask,
+ NULL, "Display i2c idle mask");
+
+static void enhanced_i2c_cq_write(int p)
+{
+ struct i2c_port_data *pd = pdata + p;
+ struct i2c_cq_packet *i2c_cq_pckt;
+ uint8_t num_bit_2_0 = (pd->out_size - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0;
+ uint8_t num_bit_10_3 = ((pd->out_size - 1) >> 3) & 0xff;
+ int dlm_index = p - I2C_STANDARD_PORT_COUNT;
+
+ i2c_cq_pckt = (struct i2c_cq_packet *)&i2c_cq_mode_tx_dlm[dlm_index];
+ /* Set commands in RAM. */
+ i2c_cq_pckt->id = pd->addr_8bit;
+ i2c_cq_pckt->cmd_l = I2C_CQ_CMD_L_P | I2C_CQ_CMD_L_E | num_bit_2_0;
+ i2c_cq_pckt->cmd_h = num_bit_10_3;
+ for (int i = 0; i < pd->out_size; i++)
+ i2c_cq_pckt->wdata[i] = pd->out[i];
+}
+
+static void enhanced_i2c_cq_read(int p)
+{
+ struct i2c_port_data *pd = pdata + p;
+ struct i2c_cq_packet *i2c_cq_pckt;
+ uint8_t num_bit_2_0 = (pd->in_size - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0;
+ uint8_t num_bit_10_3 = ((pd->in_size - 1) >> 3) & 0xff;
+ int dlm_index = p - I2C_STANDARD_PORT_COUNT;
+
+ i2c_cq_pckt = (struct i2c_cq_packet *)&i2c_cq_mode_tx_dlm[dlm_index];
+ /* Set commands in RAM. */
+ i2c_cq_pckt->id = pd->addr_8bit;
+ i2c_cq_pckt->cmd_l = I2C_CQ_CMD_L_RW | I2C_CQ_CMD_L_P |
+ I2C_CQ_CMD_L_E | num_bit_2_0;
+ i2c_cq_pckt->cmd_h = num_bit_10_3;
+}
+
+static void enhanced_i2c_cq_write_to_read(int p)
+{
+ struct i2c_port_data *pd = pdata + p;
+ struct i2c_cq_packet *i2c_cq_pckt;
+ uint8_t num_bit_2_0 = (pd->out_size - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0;
+ uint8_t num_bit_10_3 = ((pd->out_size - 1) >> 3) & 0xff;
+ int dlm_index = p - I2C_STANDARD_PORT_COUNT;
+ int i;
+
+ i2c_cq_pckt = (struct i2c_cq_packet *)&i2c_cq_mode_tx_dlm[dlm_index];
+ /* Set commands in RAM. (command byte for write) */
+ i2c_cq_pckt->id = pd->addr_8bit;
+ i2c_cq_pckt->cmd_l = num_bit_2_0;
+ i2c_cq_pckt->cmd_h = num_bit_10_3;
+ for (i = 0; i < pd->out_size; i++)
+ i2c_cq_pckt->wdata[i] = pd->out[i];
+ /* Set commands in RAM. (command byte for read) */
+ num_bit_2_0 = (pd->in_size - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0;
+ num_bit_10_3 = ((pd->in_size - 1) >> 3) & 0xff;
+ i2c_cq_pckt->wdata[i++] = I2C_CQ_CMD_L_RS | I2C_CQ_CMD_L_RW |
+ I2C_CQ_CMD_L_P | I2C_CQ_CMD_L_E | num_bit_2_0;
+ i2c_cq_pckt->wdata[i] = num_bit_10_3;
+}
+
+static int enhanced_i2c_cmd_queue_trans(int p)
+{
+ struct i2c_port_data *pd = pdata + p;
+ int p_ch = i2c_ch_reg_shift(p);
+ int dlm_index = p - I2C_STANDARD_PORT_COUNT;
+
+ /* ISR of command queue mode */
+ if (in_interrupt_context()) {
+ /* device 1 finish IRQ */
+ if (IT83XX_I2C_FST(p_ch) & IT83XX_I2C_FST_DEV1_IRQ) {
+ /* get data if this is a read transaction */
+ for (int i = 0; i < pd->in_size; i++)
+ pd->in[i] = i2c_cq_mode_rx_dlm[dlm_index][i];
+ } else {
+ /* device 1 error have occurred. eg. nack, timeout... */
+ if (IT83XX_I2C_NST(p_ch) & IT83XX_I2C_NST_ID_NACK)
+ pd->err = E_HOSTA_ACK;
+ else
+ pd->err = IT83XX_I2C_STR(p_ch) &
+ E_HOSTA_ANY_ERROR;
+ }
+ /* reset bus */
+ IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST;
+ IT83XX_I2C_CTR1(p_ch) = 0;
+
+ return 0;
+ }
+
+ if ((pd->out_size > I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE) ||
+ (pd->in_size > I2C_CQ_MODE_MAX_PAYLOAD_SIZE)) {
+ pd->err = EC_ERROR_INVAL;
+ return 0;
+ }
+
+ /* State reset and hardware reset */
+ IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST;
+ /* Set "PSR" registers to decide the i2c speed. */
+ IT83XX_I2C_PSR(p_ch) = pdata[p].freq;
+ IT83XX_I2C_HSPR(p_ch) = pdata[p].freq;
+ /* Set time out register. port D, E, or F clock/data low timeout. */
+ IT83XX_I2C_TOR(p_ch) = I2C_CLK_LOW_TIMEOUT;
+
+ /* i2c write to read */
+ if (pd->out_size && pd->in_size)
+ enhanced_i2c_cq_write_to_read(p);
+ /* i2c write */
+ else if (pd->out_size)
+ enhanced_i2c_cq_write(p);
+ /* i2c read */
+ else if (pd->in_size)
+ enhanced_i2c_cq_read(p);
+
+ /* enable i2c module with command queue mode */
+ IT83XX_I2C_CTR1(p_ch) = IT83XX_I2C_MDL_EN | IT83XX_I2C_COMQ_EN;
+ /* one shot on device 1 */
+ IT83XX_I2C_MODE_SEL(p_ch) = 0;
+ IT83XX_I2C_CTR2(p_ch) = 1;
+ /* start */
+ i2c_disable_idle(p);
+ IT83XX_I2C_CTR(p_ch) = E_START_CQ;
+
+ return 0;
+}
+#endif /* CONFIG_IT83XX_I2C_CMD_QUEUE */
+
+static int enhanced_i2c_pio_trans(int p)
{
struct i2c_port_data *pd = pdata + p;
int p_ch;
+ /* no error */
+ if (!(enhanced_i2c_error(p))) {
+ /* i2c write */
+ if (pd->out_size)
+ return enhanced_i2c_tran_write(p);
+ /* i2c read */
+ else if (pd->in_size)
+ return enhanced_i2c_tran_read(p);
+ }
+
+ p_ch = i2c_ch_reg_shift(p);
+ IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST;
+ IT83XX_I2C_CTR1(p_ch) = 0;
+
+ return 0;
+}
+
+static int i2c_transaction(int p)
+{
+ struct i2c_port_data *pd = pdata + p;
+ int ret;
+
if (p < I2C_STANDARD_PORT_COUNT) {
/* any error */
if (IT83XX_SMB_HOSTA(p) & HOSTA_ANY_ERROR) {
@@ -612,18 +844,13 @@ static int i2c_transaction(int p)
/* disable the SMBus host interface */
IT83XX_SMB_HOCTL2(p) = 0x00;
} else {
- /* no error */
- if (!(enhanced_i2c_error(p))) {
- /* i2c write */
- if (pd->out_size)
- return enhanced_i2c_tran_write(p);
- /* i2c read */
- else if (pd->in_size)
- return enhanced_i2c_tran_read(p);
- }
- p_ch = i2c_ch_reg_shift(p);
- IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST;
- IT83XX_I2C_CTR1(p_ch) = 0;
+#ifdef CONFIG_IT83XX_I2C_CMD_QUEUE
+ if (pd->flags == I2C_XFER_SINGLE)
+ ret = enhanced_i2c_cmd_queue_trans(p);
+ else
+#endif
+ ret = enhanced_i2c_pio_trans(p);
+ return ret;
}
/* done doing work */
return 0;
@@ -713,6 +940,10 @@ int chip_i2c_xfer(int port, uint16_t addr_flags,
if (pd->err)
pd->i2ccs = I2C_CH_NORMAL;
+#ifdef CONFIG_IT83XX_I2C_CMD_QUEUE
+ i2c_enable_idle(port);
+#endif
+
return pd->err;
}
@@ -933,6 +1164,10 @@ void i2c_init(void)
IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST;
/* bit1, Module enable */
IT83XX_I2C_CTR1(p_ch) = 0;
+#ifdef CONFIG_IT83XX_I2C_CMD_QUEUE
+ /* set command address registers */
+ enhanced_i2c_set_cmd_addr_regs(p);
+#endif
}
pdata[i].task_waiting = TASK_ID_INVALID;
}
diff --git a/chip/it83xx/intc.c b/chip/it83xx/intc.c
index 5e6fd734c4..45fff30c1e 100644
--- a/chip/it83xx/intc.c
+++ b/chip/it83xx/intc.c
@@ -84,7 +84,7 @@ static void intc_cpu_int_group_12(void)
peci_interrupt();
break;
#endif
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
case IT83XX_IRQ_ESPI:
espi_interrupt();
break;
diff --git a/chip/it83xx/intc.h b/chip/it83xx/intc.h
index 62ceb34576..50d31999f9 100644
--- a/chip/it83xx/intc.h
+++ b/chip/it83xx/intc.h
@@ -50,5 +50,8 @@ void spi_peripheral_int_handler(void);
void lpc_kbc_ibf_interrupt(void);
void lpc_kbc_obe_interrupt(void);
#endif
+#ifdef CONFIG_IT83XX_I2C_CMD_QUEUE
+uint32_t i2c_idle_not_allowed(void);
+#endif
#endif /* __CROS_EC_INTC_H */
diff --git a/chip/it83xx/lpc.c b/chip/it83xx/lpc.c
index 867d9e024f..8a90bd426d 100644
--- a/chip/it83xx/lpc.c
+++ b/chip/it83xx/lpc.c
@@ -136,7 +136,7 @@ static void keyboard_irq_assert(void)
*/
static void lpc_generate_smi(void)
{
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
espi_vw_set_wire(VW_SMI_L, 0);
udelay(65);
espi_vw_set_wire(VW_SMI_L, 1);
@@ -149,7 +149,7 @@ static void lpc_generate_smi(void)
static void lpc_generate_sci(void)
{
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
espi_vw_set_wire(VW_SCI_L, 0);
udelay(65);
espi_vw_set_wire(VW_SCI_L, 1);
@@ -377,7 +377,7 @@ void lpc_clear_acpi_status_mask(uint8_t mask)
pm_set_status(LPC_ACPI_CMD, mask, 0);
}
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
int lpc_get_pltrst_asserted(void)
{
return !gpio_get_level(GPIO_PCH_PLTRST_L);
@@ -688,7 +688,7 @@ static void lpc_init(void)
*/
IT83XX_GCTRL_SPCTRL1 |= 0xC2;
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
gpio_enable_interrupt(GPIO_PCH_PLTRST_L);
#endif
@@ -711,7 +711,7 @@ static void lpc_init(void)
task_clear_pending_irq(IT83XX_IRQ_PMC3_IN);
task_enable_irq(IT83XX_IRQ_PMC3_IN);
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
espi_init();
#endif
/* Sufficiently initialized */
@@ -726,7 +726,7 @@ static void lpc_init(void)
*/
DECLARE_HOOK(HOOK_INIT, lpc_init, HOOK_PRIO_INIT_LPC);
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
void lpcrst_interrupt(enum gpio_signal signal)
{
if (lpc_get_pltrst_asserted())
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h
index 34a2ddd6ae..b752f012d8 100644
--- a/chip/it83xx/registers.h
+++ b/chip/it83xx/registers.h
@@ -1456,7 +1456,7 @@ enum bram_indices {
BRAM_IDX_EC_LOG_STATUS = 0xc,
/* offset 0x0d ~ 0x1f are reserved for future use. */
-#if defined(CONFIG_HOSTCMD_LPC) || defined(CONFIG_HOSTCMD_ESPI)
+#if defined(CONFIG_HOST_INTERFACE_LPC) || defined(CONFIG_HOST_INTERFACE_ESPI)
/*
* offset 0x20 ~ 0x7b are reserved for future use.
* (apply to x86 platform)
@@ -1508,7 +1508,7 @@ enum bram_ec_logs_status {
* And they will be used to save panic data if the GPG1 reset mechanism
* is enabled.
*/
-#if defined(CONFIG_HOSTCMD_LPC) || defined(CONFIG_HOSTCMD_ESPI)
+#if defined(CONFIG_HOST_INTERFACE_LPC) || defined(CONFIG_HOST_INTERFACE_ESPI)
/* offset 0x80 ~ 0xbf */
#define IT83XX_BRAM_BANK1(i) REG8(IT83XX_BRAM_BASE + 0x80 + i)
#else
@@ -1552,7 +1552,20 @@ enum bram_ec_logs_status {
#define IT83XX_I2C_IDR(ch) REG8(IT83XX_I2C_BASE+0x06+(ch << 7))
#define IT83XX_I2C_TOS(ch) REG8(IT83XX_I2C_BASE+0x07+(ch << 7))
#define IT83XX_I2C_CLK_STR (1 << 7)
+#define IT83XX_I2C_STR2(ch) REG8(IT83XX_I2C_BASE+0x12+(ch << 7))
+#define IT83XX_I2C_NST(ch) REG8(IT83XX_I2C_BASE+0x13+(ch << 7))
+#define IT83XX_I2C_NST_CNS BIT(7)
+#define IT83XX_I2C_NST_ID_NACK BIT(3)
+#define IT83XX_I2C_TO_ARB_ST(ch) REG8(IT83XX_I2C_BASE+0x18+(ch << 7))
+#define IT83XX_I2C_ERR_ST(ch) REG8(IT83XX_I2C_BASE+0x19+(ch << 7))
+#define IT83XX_I2C_ERR_ST_DEV1_EIRQ BIT(0)
+#define IT83XX_I2C_FST(ch) REG8(IT83XX_I2C_BASE+0x1b+(ch << 7))
+#define IT83XX_I2C_FST_DEV1_IRQ BIT(4)
+#define IT83XX_I2C_EM(ch) REG8(IT83XX_I2C_BASE+0x1c+(ch << 7))
+#define IT83XX_I2C_EM_DEV1_IRQ BIT(4)
+#define IT83XX_I2C_MODE_SEL(ch) REG8(IT83XX_I2C_BASE+0x1d+(ch << 7))
#define IT83XX_I2C_IDR2(ch) REG8(IT83XX_I2C_BASE+0x1F+(ch << 7))
+#define IT83XX_I2C_CTR2(ch) REG8(IT83XX_I2C_BASE+0x20+(ch << 7))
#define IT83XX_I2C_RAMHA(ch) REG8(IT83XX_I2C_BASE+0x23+(ch << 7))
#define IT83XX_I2C_RAMLA(ch) REG8(IT83XX_I2C_BASE+0x24+(ch << 7))
#define IT83XX_I2C_RAMHA2(ch) REG8(IT83XX_I2C_BASE+0x2B+(ch << 7))
diff --git a/chip/it83xx/system.c b/chip/it83xx/system.c
index 16871e5826..ae7fd627bf 100644
--- a/chip/it83xx/system.c
+++ b/chip/it83xx/system.c
@@ -50,7 +50,7 @@ static void clear_reset_flags(void)
}
DECLARE_HOOK(HOOK_INIT, clear_reset_flags, HOOK_PRIO_LAST);
-#if !defined(CONFIG_HOSTCMD_LPC) && !defined(CONFIG_HOSTCMD_ESPI)
+#if !defined(CONFIG_HOST_INTERFACE_LPC) && !defined(CONFIG_HOST_INTERFACE_ESPI)
static void system_save_panic_data_to_bram(void)
{
uint8_t *ptr = (uint8_t *)PANIC_DATA_PTR;
View Lorry Controller Status