diff options
Diffstat (limited to 'chip/npcx/config_chip-npcx9.h')
| -rw-r--r-- | chip/npcx/config_chip-npcx9.h | 71 |
1 files changed, 35 insertions, 36 deletions
diff --git a/chip/npcx/config_chip-npcx9.h b/chip/npcx/config_chip-npcx9.h index 7f154dbe42..736aef8a1c 100644 --- a/chip/npcx/config_chip-npcx9.h +++ b/chip/npcx/config_chip-npcx9.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -16,8 +16,8 @@ */ /* Chip ID for all variants */ -#define NPCX996F_CHIP_ID 0x21 -#define NPCX993F_CHIP_ID 0x25 +#define NPCX996F_CHIP_ID 0x21 +#define NPCX993F_CHIP_ID 0x25 /*****************************************************************************/ /* Hardware features */ @@ -25,7 +25,8 @@ #define NPCX_EXT32K_OSC_SUPPORT /* External 32KHz crytal osc. input support */ #define NPCX_INT_FLASH_SUPPORT /* Internal flash support */ #define NPCX_LCT_SUPPORT /* Long Countdown Timer support */ -#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power */ +#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power \ + */ #define NPCX_UART_FIFO_SUPPORT /* Number of UART modules. */ @@ -55,10 +56,10 @@ /* PSL_OUT optional configuration */ /* Set PSL_OUT mode to pulse mode */ -#define NPCX_PSL_CFG_PSL_OUT_PULSE BIT(0) +#define NPCX_PSL_CFG_PSL_OUT_PULSE BIT(0) /* set PSL_OUT to open-drain */ -#define NPCX_PSL_CFG_PSL_OUT_OD BIT(1) -#define CONFIG_HIBERNATE_PSL_OUT_FLAGS 0 +#define NPCX_PSL_CFG_PSL_OUT_OD BIT(1) +#define CONFIG_HIBERNATE_PSL_OUT_FLAGS 0 /* * Workaound the issue 3.10 in the NPCX99nF errata rev1.2 @@ -75,36 +76,35 @@ #define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE) #if defined(CHIP_VARIANT_NPCX9M3F) - /* - * 256KB program RAM, but only 512K of Flash. After the boot header is - * added, a 256K image would be too large to fit in either RO or RW - * sections of Flash (each of which is half of it). Because other code - * assumes that image size is a multiple of Flash erase granularity, we - * sacrifice a whole sector. - */ -# define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024 - 0x1000) - /* program memory base address for Code RAM (0x100C0000 - 256KB) */ -# define CONFIG_PROGRAM_MEMORY_BASE 0x10080000 -# define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ - /* Two blocks of data RAM - total size is 64KB */ -# define CONFIG_DATA_RAM_SIZE 0x00010000 -# define CONFIG_RAM_SIZE CONFIG_DATA_RAM_SIZE - - /* Override default NPCX_RAM_SIZE because we're excluding a block. */ -# undef NPCX_RAM_SIZE -# define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + \ - NPCX_PROGRAM_MEMORY_SIZE + 0x1000) +/* + * 256KB program RAM, but only 512K of Flash. After the boot header is + * added, a 256K image would be too large to fit in either RO or RW + * sections of Flash (each of which is half of it). Because other code + * assumes that image size is a multiple of Flash erase granularity, we + * sacrifice a whole sector. + */ +#define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024 - 0x1000) +/* program memory base address for Code RAM (0x100C0000 - 256KB) */ +#define CONFIG_PROGRAM_MEMORY_BASE 0x10080000 +#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ +/* Two blocks of data RAM - total size is 64KB */ +#define CONFIG_DATA_RAM_SIZE 0x00010000 +#define CONFIG_RAM_SIZE CONFIG_DATA_RAM_SIZE + +/* Override default NPCX_RAM_SIZE because we're excluding a block. */ +#undef NPCX_RAM_SIZE +#define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE + 0x1000) #elif defined(CHIP_VARIANT_NPCX9M6F) - /* 192KB RAM for FW code */ -# define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024) - /* program memory base address for Code RAM (0x100C0000 - 192KB) */ -# define CONFIG_PROGRAM_MEMORY_BASE 0x10090000 -# define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ - /* Two blocks of data RAM - total size is 64KB */ -# define CONFIG_DATA_RAM_SIZE 0x00010000 -# define CONFIG_RAM_SIZE CONFIG_DATA_RAM_SIZE +/* 192KB RAM for FW code */ +#define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024) +/* program memory base address for Code RAM (0x100C0000 - 192KB) */ +#define CONFIG_PROGRAM_MEMORY_BASE 0x10090000 +#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ +/* Two blocks of data RAM - total size is 64KB */ +#define CONFIG_DATA_RAM_SIZE 0x00010000 +#define CONFIG_RAM_SIZE CONFIG_DATA_RAM_SIZE #else -# error "Unsupported chip variant" +#error "Unsupported chip variant" #endif /* Internal spi-flash setting */ @@ -112,5 +112,4 @@ #define CONFIG_SPI_FLASH_W25Q40 /* Internal spi flash type */ #define CONFIG_FLASH_SIZE_BYTES 0x00080000 /* 512 KB internal spi flash */ - #endif /* __CROS_EC_CONFIG_CHIP_NPCX9_H */ |