diff options
Diffstat (limited to 'chip/npcx')
73 files changed, 4524 insertions, 4039 deletions
diff --git a/chip/npcx/adc.c b/chip/npcx/adc.c index a31a0376dd..f01419bf67 100644 --- a/chip/npcx/adc.c +++ b/chip/npcx/adc.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,11 +19,11 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) /* Maximum time we allow for an ADC conversion */ -#define ADC_TIMEOUT_US SECOND +#define ADC_TIMEOUT_US SECOND /* * ADC basic clock is from APB1. * In npcx5, APB1 clock frequency is (15 MHz / 4). @@ -34,23 +34,23 @@ * 7.5 MHz. */ #if defined(CHIP_FAMILY_NPCX5) -#define ADC_CLK 2000000 -#define ADC_DLY 0x03 -#define ADC_ADCCNF2 0x8B07 -#define ADC_GENDLY 0x0100 -#define ADC_MEAST 0x0001 +#define ADC_CLK 2000000 +#define ADC_DLY 0x03 +#define ADC_ADCCNF2 0x8B07 +#define ADC_GENDLY 0x0100 +#define ADC_MEAST 0x0001 #else -#define ADC_CLK 7500000 -#define ADC_DLY 0x02 -#define ADC_ADCCNF2 0x8901 -#define ADC_GENDLY 0x0100 -#define ADC_MEAST 0x0405 +#define ADC_CLK 7500000 +#define ADC_DLY 0x02 +#define ADC_ADCCNF2 0x8901 +#define ADC_GENDLY 0x0100 +#define ADC_MEAST 0x0405 #endif /* ADC conversion mode */ enum npcx_adc_conversion_mode { - ADC_CHN_CONVERSION_MODE = 0, - ADC_SCAN_CONVERSION_MODE = 1 + ADC_CHN_CONVERSION_MODE = 0, + ADC_SCAN_CONVERSION_MODE = 1 }; /* Global variables */ @@ -69,7 +69,7 @@ static volatile bool adc_done; */ void adc_freq_changed(void) { - uint8_t prescaler_divider = 0; + uint8_t prescaler_divider = 0; /* Set clock prescaler divider to ADC module*/ prescaler_divider = (uint8_t)(clock_get_apb1_freq() / ADC_CLK); @@ -91,8 +91,8 @@ DECLARE_HOOK(HOOK_FREQ_CHANGE, adc_freq_changed, HOOK_PRIO_DEFAULT); * @return TRUE/FALSE success/fail * @notes set SW-triggered interrupt conversion and one-shot mode in npcx chip */ -static int start_single_and_wait(enum npcx_adc_input_channel input_ch - , int timeout) +static int start_single_and_wait(enum npcx_adc_input_channel input_ch, + int timeout) { int event; @@ -107,7 +107,7 @@ static int start_single_and_wait(enum npcx_adc_input_channel input_ch /* Set ADC conversion code to SW conversion mode */ SET_FIELD(NPCX_ADCCNF, NPCX_ADCCNF_ADCMD_FIELD, - ADC_CHN_CONVERSION_MODE); + ADC_CHN_CONVERSION_MODE); /* Set conversion type to one-shot type */ CLEAR_BIT(NPCX_ADCCNF, NPCX_ADCCNF_ADCRPTC); @@ -124,13 +124,12 @@ static int start_single_and_wait(enum npcx_adc_input_channel input_ch /* Start conversion */ SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_START); -/* - * If tasks have started, we can suspend to the task that called us. - * If not, we need to busy poll for adc to finish before proceeding - */ + /* + * If tasks have started, we can suspend to the task that called us. + * If not, we need to busy poll for adc to finish before proceeding + */ if (IS_ENABLED(CONFIG_KEYBOARD_SCAN_ADC)) { if (!task_start_called()) { - /* Wait for the ADC interrupt to set the flag */ do { usleep(10); @@ -142,7 +141,7 @@ static int start_single_and_wait(enum npcx_adc_input_channel input_ch } else { /* Wait for interrupt */ event = task_wait_event_mask(TASK_EVENT_ADC_DONE, - timeout); + timeout); task_waiting = TASK_ID_INVALID; } @@ -213,8 +212,9 @@ int adc_read_data(enum npcx_adc_input_channel input_ch) uint16_t chn_data; chn_data = NPCX_CHNDAT(adc->input_ch); - value = GET_FIELD(chn_data, NPCX_CHNDAT_CHDAT_FIELD) * - adc->factor_mul / adc->factor_div + adc->shift; + value = GET_FIELD(chn_data, NPCX_CHNDAT_CHDAT_FIELD) * adc->factor_mul / + adc->factor_div + + adc->shift; return value; } @@ -241,11 +241,11 @@ int adc_read_channel(enum adc_channel ch) if (start_single_and_wait(adc->input_ch, ADC_TIMEOUT_US)) { chn_data = NPCX_CHNDAT(adc->input_ch); if ((adc->input_ch == - GET_FIELD(NPCX_ASCADD, NPCX_ASCADD_SADDR_FIELD)) - && (IS_BIT_SET(chn_data, - NPCX_CHNDAT_NEW))) { + GET_FIELD(NPCX_ASCADD, NPCX_ASCADD_SADDR_FIELD)) && + (IS_BIT_SET(chn_data, NPCX_CHNDAT_NEW))) { value = GET_FIELD(chn_data, NPCX_CHNDAT_CHDAT_FIELD) * - adc->factor_mul / adc->factor_div + adc->shift; + adc->factor_mul / adc->factor_div + + adc->shift; } else { value = ADC_READ_ERROR; } @@ -261,7 +261,7 @@ int adc_read_channel(enum adc_channel ch) } else { /* Set ADC conversion code to SW conversion mode */ SET_FIELD(NPCX_ADCCNF, NPCX_ADCCNF_ADCMD_FIELD, - ADC_SCAN_CONVERSION_MODE); + ADC_SCAN_CONVERSION_MODE); /* Set conversion type to repetitive (runs continuously) */ SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_ADCRPTC); /* Start conversion */ @@ -283,8 +283,7 @@ void npcx_adc_thresh_int_enable(int threshold_idx, int enable) enable = !!enable; if ((threshold_idx < 1) || (threshold_idx > NPCX_ADC_THRESH_CNT)) { - CPRINTS("Invalid ADC thresh index! (%d)", - threshold_idx); + CPRINTS("Invalid ADC thresh index! (%d)", threshold_idx); return; } threshold_idx--; /* convert to 0-based */ @@ -313,24 +312,21 @@ void npcx_adc_register_thresh_irq(int threshold_idx, int shift; if ((threshold_idx < 1) || (threshold_idx > NPCX_ADC_THRESH_CNT)) { - CPRINTS("Invalid ADC thresh index! (%d)", - threshold_idx); + CPRINTS("Invalid ADC thresh index! (%d)", threshold_idx); return; } npcx_adc_ch = adc_channels[thresh_cfg->adc_ch].input_ch; if (!thresh_cfg->adc_thresh_cb) { - CPRINTS("No callback for ADC Threshold %d!", - threshold_idx); + CPRINTS("No callback for ADC Threshold %d!", threshold_idx); return; } /* Fill in the table */ - adc_thresh_irqs[threshold_idx-1] = thresh_cfg->adc_thresh_cb; + adc_thresh_irqs[threshold_idx - 1] = thresh_cfg->adc_thresh_cb; /* Select the channel */ - SET_FIELD(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_CHNSEL, - npcx_adc_ch); + SET_FIELD(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_CHNSEL, npcx_adc_ch); if (thresh_cfg->lower_or_higher) SET_BIT(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_L_H); @@ -345,8 +341,7 @@ void npcx_adc_register_thresh_irq(int threshold_idx, raw_val = (thresh_cfg->thresh_assert - shift) * div / mul; CPRINTS("ADC THR%d: Setting THRVAL = %d, L_H: %d", threshold_idx, raw_val, thresh_cfg->lower_or_higher); - SET_FIELD(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_THRVAL, - raw_val); + SET_FIELD(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_THRVAL, raw_val); #if NPCX_FAMILY_VERSION <= NPCX_FAMILY_NPCX7 /* Disable deassertion threshold function */ @@ -396,7 +391,7 @@ static void adc_interrupt(void) IS_BIT_SET(NPCX_THRCTS, i)) { /* avoid clearing other threshold status */ thrcts = NPCX_THRCTS & - ~GENMASK(NPCX_ADC_THRESH_CNT - 1, 0); + ~GENMASK(NPCX_ADC_THRESH_CNT - 1, 0); /* Clear threshold status */ SET_BIT(thrcts, i); NPCX_THRCTS = thrcts; @@ -430,7 +425,7 @@ void adc_init(void) /* Enable ADC clock (bit4 mask = 0x10) */ clock_enable_peripheral(CGC_OFFSET_ADC, CGC_ADC_MASK, - CGC_MODE_RUN | CGC_MODE_SLEEP); + CGC_MODE_RUN | CGC_MODE_SLEEP); /* Set Core Clock Division Factor in order to obtain the ADC clock */ adc_freq_changed(); diff --git a/chip/npcx/adc_chip.h b/chip/npcx/adc_chip.h index 300447df16..5f3862829a 100644 --- a/chip/npcx/adc_chip.h +++ b/chip/npcx/adc_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -32,7 +32,7 @@ enum npcx_adc_input_channel { #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9 NPCX_ADC_CH10, NPCX_ADC_CH11, - #endif +#endif NPCX_ADC_CH_COUNT }; diff --git a/chip/npcx/apm.c b/chip/npcx/apm.c index 4ab64774c1..b66a77a276 100644 --- a/chip/npcx/apm.c +++ b/chip/npcx/apm.c @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,13 +12,12 @@ #include "wov_chip.h" static struct apm_config apm_conf; -static struct apm_auto_gain_config apm_gain_conf; - +static struct apm_auto_gain_config apm_gain_conf; static uint32_t apm_indirect_reg[][3] = { - {(NPCX_APM_BASE_ADDR + 0x034), (NPCX_APM_BASE_ADDR + 0x038)}, - {(NPCX_APM_BASE_ADDR + 0x04C), (NPCX_APM_BASE_ADDR + 0x050)}, - {(NPCX_APM_BASE_ADDR + 0x05C), (NPCX_APM_BASE_ADDR + 0x060)} + { (NPCX_APM_BASE_ADDR + 0x034), (NPCX_APM_BASE_ADDR + 0x038) }, + { (NPCX_APM_BASE_ADDR + 0x04C), (NPCX_APM_BASE_ADDR + 0x050) }, + { (NPCX_APM_BASE_ADDR + 0x05C), (NPCX_APM_BASE_ADDR + 0x060) } }; #define APM_CNTRL_REG 0 @@ -37,11 +36,11 @@ static uint8_t apm_read_indirect_data(enum apm_indirect_reg_offset reg_offset, { /* Set the indirect access address. */ SET_FIELD(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]), - NPCX_APM_CONTROL_ADD, indirect_addr); + NPCX_APM_CONTROL_ADD, indirect_addr); /* Read command. */ CLEAR_BIT(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]), - NPCX_APM_CONTROL_LOAD); + NPCX_APM_CONTROL_LOAD); /* Get the data. */ return REG8(apm_indirect_reg[reg_offset][APM_DATA_REG]); @@ -57,20 +56,20 @@ static uint8_t apm_read_indirect_data(enum apm_indirect_reg_offset reg_offset, * @return None */ static void apm_write_indirect_data(enum apm_indirect_reg_offset reg_offset, - uint8_t indirect_addr, uint8_t value) + uint8_t indirect_addr, uint8_t value) { /* Set the data. */ REG8(apm_indirect_reg[reg_offset][APM_DATA_REG]) = value; /* Set the indirect access address. */ SET_FIELD(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]), - NPCX_APM_CONTROL_ADD, indirect_addr); + NPCX_APM_CONTROL_ADD, indirect_addr); /* Write command. */ SET_BIT(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]), - NPCX_APM_CONTROL_LOAD); + NPCX_APM_CONTROL_LOAD); CLEAR_BIT(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]), - NPCX_APM_CONTROL_LOAD); + NPCX_APM_CONTROL_LOAD); } /** @@ -83,13 +82,13 @@ void apm_set_adc_dmic_config_l(enum apm_dmic_rate rate) { if (rate == APM_DMIC_RATE_0_75) SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_RATE, - APM_DMIC_RATE_3_0); + APM_DMIC_RATE_3_0); else if (rate == APM_DMIC_RATE_1_2) SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_RATE, - APM_DMIC_RATE_2_4); + APM_DMIC_RATE_2_4); else SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_RATE, - rate); + rate); } /** @@ -108,7 +107,7 @@ void apm_set_vad_dmic_rate_l(enum apm_dmic_rate rate) /* Set VAD_0 register. */ if (rate == APM_DMIC_RATE_0_75) SET_FIELD(vad_data, NPCX_VAD_0_VAD_DMIC_FREQ, - APM_DMIC_RATE_3_0); + APM_DMIC_RATE_3_0); else if (rate == APM_DMIC_RATE_1_2) SET_FIELD(vad_data, NPCX_VAD_0_VAD_DMIC_FREQ, APM_DMIC_RATE_2_4); @@ -172,15 +171,15 @@ void apm_init(void) apm_conf.left_chan_gain = 0; apm_conf.right_chan_gain = 0; - apm_gain_conf.stereo_enable = 0; - apm_gain_conf.agc_target = APM_ADC_MAX_TARGET_LEVEL_19_5; - apm_gain_conf.nois_gate_en = 0; + apm_gain_conf.stereo_enable = 0; + apm_gain_conf.agc_target = APM_ADC_MAX_TARGET_LEVEL_19_5; + apm_gain_conf.nois_gate_en = 0; apm_gain_conf.nois_gate_thold = APM_MIN_NOISE_GET_THRESHOLD; - apm_gain_conf.hold_time = APM_HOLD_TIME_128; - apm_gain_conf.attack_time = APM_GAIN_RAMP_TIME_160; - apm_gain_conf.decay_time = APM_GAIN_RAMP_TIME_160; - apm_gain_conf.gain_max = APM_GAIN_VALUE_42_5; - apm_gain_conf.gain_min = APM_GAIN_VALUE_0_0; + apm_gain_conf.hold_time = APM_HOLD_TIME_128; + apm_gain_conf.attack_time = APM_GAIN_RAMP_TIME_160; + apm_gain_conf.decay_time = APM_GAIN_RAMP_TIME_160; + apm_gain_conf.gain_max = APM_GAIN_VALUE_42_5; + apm_gain_conf.gain_min = APM_GAIN_VALUE_0_0; } /** @@ -226,11 +225,11 @@ void apm_enable_vad_interrupt(int enable) void apm_adc_wov_enable(int enable) { if (enable) { - SET_FIELD(NPCX_APM_AICR_ADC, - NPCX_APM_AICR_ADC_ADC_AUDIOIF, 0x00); + SET_FIELD(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_ADC_AUDIOIF, + 0x00); } else { - SET_FIELD(NPCX_APM_AICR_ADC, - NPCX_APM_AICR_ADC_ADC_AUDIOIF, 0x03); + SET_FIELD(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_ADC_AUDIOIF, + 0x03); } } @@ -244,12 +243,12 @@ void apm_adc_enable(int enable) { if (enable) { CLEAR_BIT(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_PD_AICR_ADC); - SET_FIELD(NPCX_APM_AICR_ADC, - NPCX_APM_AICR_ADC_ADC_AUDIOIF, 0x00); + SET_FIELD(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_ADC_AUDIOIF, + 0x00); } else { SET_BIT(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_PD_AICR_ADC); - SET_FIELD(NPCX_APM_AICR_ADC, - NPCX_APM_AICR_ADC_ADC_AUDIOIF, 0x03); + SET_FIELD(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_ADC_AUDIOIF, + 0x03); } } @@ -273,8 +272,8 @@ void apm_adc_set_freq(enum apm_adc_frequency adc_freq) * @return None */ void apm_adc_config(int hpf_enable, - enum apm_adc_wind_noise_filter_mode filter_mode, - enum apm_adc_frequency adc_freq) + enum apm_adc_wind_noise_filter_mode filter_mode, + enum apm_adc_frequency adc_freq) { if (hpf_enable) SET_BIT(NPCX_APM_FCR_ADC, NPCX_APM_FCR_ADC_ADC_HPF); @@ -491,7 +490,8 @@ void apm_vad_restart(void) * @return EC_ERROR_INVAL or EC_SUCCESS */ enum ec_error_list apm_adc_gain_config(enum apm_adc_gain_coupling gain_coupling, - uint8_t left_chan_gain, uint8_t right_chan_gain) + uint8_t left_chan_gain, + uint8_t right_chan_gain) { /* Check parameters validity. */ if ((left_chan_gain > 0x2B) || (right_chan_gain > 0x2B)) @@ -538,8 +538,8 @@ void apm_auto_gain_cntrl_enable(int enable) * @param gain_cfg - struct of apm auto gain config * @return EC_ERROR_INVAL or EC_SUCCESS */ -enum ec_error_list apm_adc_auto_gain_config( - struct apm_auto_gain_config *gain_cfg) +enum ec_error_list +apm_adc_auto_gain_config(struct apm_auto_gain_config *gain_cfg) { uint8_t gain_data = 0; @@ -668,9 +668,8 @@ void apm_set_mode(enum wov_modes wov_mode) break; } - apm_adc_gain_config(apm_conf.gain_coupling, - apm_conf.left_chan_gain, - apm_conf.right_chan_gain); + apm_adc_gain_config(apm_conf.gain_coupling, apm_conf.left_chan_gain, + apm_conf.right_chan_gain); apm_adc_auto_gain_config(&apm_gain_conf); diff --git a/chip/npcx/apm_chip.h b/chip/npcx/apm_chip.h index ad62538374..9b330321ea 100644 --- a/chip/npcx/apm_chip.h +++ b/chip/npcx/apm_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,31 +9,27 @@ #include "common.h" /* MIX indirect registers. */ -#define APM_INDIRECT_MIX_2_REG 0x02 +#define APM_INDIRECT_MIX_2_REG 0x02 /* ADC_AGC indirect registers. */ -#define APM_INDIRECT_ADC_AGC_0_REG 0x00 -#define APM_INDIRECT_ADC_AGC_1_REG 0x01 -#define APM_INDIRECT_ADC_AGC_2_REG 0x02 -#define APM_INDIRECT_ADC_AGC_3_REG 0x03 -#define APM_INDIRECT_ADC_AGC_4_REG 0x04 +#define APM_INDIRECT_ADC_AGC_0_REG 0x00 +#define APM_INDIRECT_ADC_AGC_1_REG 0x01 +#define APM_INDIRECT_ADC_AGC_2_REG 0x02 +#define APM_INDIRECT_ADC_AGC_3_REG 0x03 +#define APM_INDIRECT_ADC_AGC_4_REG 0x04 /* APM_VAD_REG indirect registers. */ -#define APM_INDIRECT_VAD_0_REG 0x00 -#define APM_INDIRECT_VAD_1_REG 0x01 +#define APM_INDIRECT_VAD_0_REG 0x00 +#define APM_INDIRECT_VAD_1_REG 0x01 /* APM macros. */ -#define APM_IS_IRQ_PENDING IS_BIT_SET(NPCX_APM_SR, NPCX_APM_SR_IRQ_PEND) +#define APM_IS_IRQ_PENDING IS_BIT_SET(NPCX_APM_SR, NPCX_APM_SR_IRQ_PEND) #define APM_IS_VOICE_ACTIVITY_DETECTED \ IS_BIT_SET(NPCX_APM_IFR, NPCX_APM_IFR_VAD_DTC) -#define APM_CLEAR_VAD_INTERRUPT SET_BIT(NPCX_APM_IFR, NPCX_APM_IFR_VAD_DTC) +#define APM_CLEAR_VAD_INTERRUPT SET_BIT(NPCX_APM_IFR, NPCX_APM_IFR_VAD_DTC) /* Indirect registers. */ -enum apm_indirect_reg_offset { - APM_MIX_REG = 0, - APM_ADC_AGC_REG, - APM_VAD_REG -}; +enum apm_indirect_reg_offset { APM_MIX_REG = 0, APM_ADC_AGC_REG, APM_VAD_REG }; /* ADC wind noise filter modes. */ enum apm_adc_wind_noise_filter_mode { @@ -60,22 +56,22 @@ enum apm_adc_frequency { /* DMIC source. */ enum apm_dmic_src { APM_CURRENT_DMIC_CHANNEL = 0x01, /* Current channel, left or rigth. */ - APM_AVERAGE_DMIC_CHANNEL = 0x02 /* Average between left & right. */ + APM_AVERAGE_DMIC_CHANNEL = 0x02 /* Average between left & right. */ }; /* ADC digital microphone rate. */ enum apm_dmic_rate { /* 3.0, 2.4 & 1.0 must be 0, 1 & 2 respectively */ - APM_DMIC_RATE_3_0 = 0, /* 3.0 -3.25 MHz (default). */ - APM_DMIC_RATE_2_4, /* 2.4 -2.6 MHz. */ - APM_DMIC_RATE_1_0, /* 1.0 -1.08 MHz. */ - APM_DMIC_RATE_1_2, /* 1.2 MHz. */ - APM_DMIC_RATE_0_75 /* 750 KHz. */ + APM_DMIC_RATE_3_0 = 0, /* 3.0 -3.25 MHz (default). */ + APM_DMIC_RATE_2_4, /* 2.4 -2.6 MHz. */ + APM_DMIC_RATE_1_0, /* 1.0 -1.08 MHz. */ + APM_DMIC_RATE_1_2, /* 1.2 MHz. */ + APM_DMIC_RATE_0_75 /* 750 KHz. */ }; /* Digitla mixer output. */ enum apm_dig_mix { - APM_OUT_MIX_NORMAL_INPUT = 0, /* Default. */ + APM_OUT_MIX_NORMAL_INPUT = 0, /* Default. */ APM_OUT_MIX_CROSS_INPUT, APM_OUT_MIX_MIXED_INPUT, APM_OUT_MIX_NO_INPUT @@ -341,8 +337,8 @@ void apm_adc_set_freq(enum apm_adc_frequency adc_freq); * @return None */ void apm_adc_config(int hpf_enable, - enum apm_adc_wind_noise_filter_mode filter_mode, - enum apm_adc_frequency adc_freq); + enum apm_adc_wind_noise_filter_mode filter_mode, + enum apm_adc_frequency adc_freq); /** * Enables/Disables Digital Microphone. @@ -360,7 +356,7 @@ void apm_dmic_enable(int enable); * @return None */ void apm_digital_mixer_config(enum apm_dig_mix mix_left, - enum apm_dig_mix mix_right); + enum apm_dig_mix mix_right); /** * Enables/Disables the VAD functionality. @@ -422,7 +418,8 @@ void apm_vad_restart(void); * @return EC_ERROR_INVAL or EC_SUCCESS */ enum ec_error_list apm_adc_gain_config(enum apm_adc_gain_coupling gain_coupling, - uint8_t left_chan_gain, uint8_t right_chan_gain); + uint8_t left_chan_gain, + uint8_t right_chan_gain); /** * Enables/Disables the automatic gain. @@ -438,8 +435,8 @@ void apm_auto_gain_cntrl_enable(int enable); * @param gain_cfg - struct of apm auto gain config * @return EC_ERROR_INVAL or EC_SUCCESS */ -enum ec_error_list apm_adc_auto_gain_config( - struct apm_auto_gain_config *gain_cfg); +enum ec_error_list +apm_adc_auto_gain_config(struct apm_auto_gain_config *gain_cfg); /** * Sets APM mode (enables & disables APN sub modules accordingly diff --git a/chip/npcx/audio_codec_dmic.c b/chip/npcx/audio_codec_dmic.c index e242a8b2d2..7e1bfa9bce 100644 --- a/chip/npcx/audio_codec_dmic.c +++ b/chip/npcx/audio_codec_dmic.c @@ -1,5 +1,5 @@ /* - * Copyright 2020 The Chromium OS Authors. All rights reserved. + * Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/npcx/audio_codec_i2s_rx.c b/chip/npcx/audio_codec_i2s_rx.c index 12c4173048..02224be437 100644 --- a/chip/npcx/audio_codec_i2s_rx.c +++ b/chip/npcx/audio_codec_i2s_rx.c @@ -1,5 +1,5 @@ /* - * Copyright 2020 The Chromium OS Authors. All rights reserved. + * Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -8,7 +8,7 @@ #include "ec_commands.h" #include "wov_chip.h" -#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ##args) int audio_codec_i2s_rx_enable(void) { diff --git a/chip/npcx/build.mk b/chip/npcx/build.mk index d7e61de4de..9e046be7ec 100644 --- a/chip/npcx/build.mk +++ b/chip/npcx/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2014 The Chromium OS Authors. All rights reserved. +# Copyright 2014 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/chip/npcx/cec.c b/chip/npcx/cec.c index eb1cfefa0f..39f353b0e3 100644 --- a/chip/npcx/cec.c +++ b/chip/npcx/cec.c @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -22,21 +22,21 @@ #define CPRINTF(...) #define CPRINTS(...) #else -#define CPRINTF(format, args...) cprintf(CC_CEC, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CEC, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CEC, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CEC, format, ##args) #endif /* Time in us to timer clock ticks */ -#define APB1_TICKS(t) ((t) * apb1_freq_div_10k / 100) +#define APB1_TICKS(t) ((t)*apb1_freq_div_10k / 100) #if DEBUG_CEC /* Timer clock ticks to us */ -#define APB1_US(ticks) (100*(ticks)/apb1_freq_div_10k) +#define APB1_US(ticks) (100 * (ticks) / apb1_freq_div_10k) #endif /* Notification from interrupt to CEC task that data has been received */ #define TASK_EVENT_RECEIVED_DATA TASK_EVENT_CUSTOM_BIT(0) -#define TASK_EVENT_OKAY TASK_EVENT_CUSTOM_BIT(1) -#define TASK_EVENT_FAILED TASK_EVENT_CUSTOM_BIT(2) +#define TASK_EVENT_OKAY TASK_EVENT_CUSTOM_BIT(1) +#define TASK_EVENT_FAILED TASK_EVENT_CUSTOM_BIT(2) /* CEC broadcast address. Also the highest possible CEC address */ #define CEC_BROADCAST_ADDR 15 @@ -56,7 +56,7 @@ * free-time period less than in the spec. */ #define NOMINAL_BIT_TICKS APB1_TICKS(2400) - /* Resend */ +/* Resend */ #define FREE_TIME_RS_TICKS (2 * (NOMINAL_BIT_TICKS)) /* New initiator */ #define FREE_TIME_NI_TICKS (4 * (NOMINAL_BIT_TICKS)) @@ -64,33 +64,33 @@ #define FREE_TIME_PI_TICKS (6 * (NOMINAL_BIT_TICKS)) /* Start bit timing */ -#define START_BIT_LOW_TICKS APB1_TICKS(3700) -#define START_BIT_MIN_LOW_TICKS APB1_TICKS(3500) -#define START_BIT_MAX_LOW_TICKS APB1_TICKS(3900) -#define START_BIT_HIGH_TICKS APB1_TICKS(800) -#define START_BIT_MIN_DURATION_TICKS APB1_TICKS(4300) -#define START_BIT_MAX_DURATION_TICKS APB1_TICKS(5700) +#define START_BIT_LOW_TICKS APB1_TICKS(3700) +#define START_BIT_MIN_LOW_TICKS APB1_TICKS(3500) +#define START_BIT_MAX_LOW_TICKS APB1_TICKS(3900) +#define START_BIT_HIGH_TICKS APB1_TICKS(800) +#define START_BIT_MIN_DURATION_TICKS APB1_TICKS(4300) +#define START_BIT_MAX_DURATION_TICKS APB1_TICKS(5700) /* Data bit timing */ -#define DATA_ZERO_LOW_TICKS APB1_TICKS(1500) -#define DATA_ZERO_MIN_LOW_TICKS APB1_TICKS(1300) -#define DATA_ZERO_MAX_LOW_TICKS APB1_TICKS(1700) -#define DATA_ZERO_HIGH_TICKS APB1_TICKS(900) -#define DATA_ZERO_MIN_DURATION_TICKS APB1_TICKS(2050) -#define DATA_ZERO_MAX_DURATION_TICKS APB1_TICKS(2750) - -#define DATA_ONE_LOW_TICKS APB1_TICKS(600) -#define DATA_ONE_MIN_LOW_TICKS APB1_TICKS(400) -#define DATA_ONE_MAX_LOW_TICKS APB1_TICKS(800) -#define DATA_ONE_HIGH_TICKS APB1_TICKS(1800) -#define DATA_ONE_MIN_DURATION_TICKS APB1_TICKS(2050) -#define DATA_ONE_MAX_DURATION_TICKS APB1_TICKS(2750) +#define DATA_ZERO_LOW_TICKS APB1_TICKS(1500) +#define DATA_ZERO_MIN_LOW_TICKS APB1_TICKS(1300) +#define DATA_ZERO_MAX_LOW_TICKS APB1_TICKS(1700) +#define DATA_ZERO_HIGH_TICKS APB1_TICKS(900) +#define DATA_ZERO_MIN_DURATION_TICKS APB1_TICKS(2050) +#define DATA_ZERO_MAX_DURATION_TICKS APB1_TICKS(2750) + +#define DATA_ONE_LOW_TICKS APB1_TICKS(600) +#define DATA_ONE_MIN_LOW_TICKS APB1_TICKS(400) +#define DATA_ONE_MAX_LOW_TICKS APB1_TICKS(800) +#define DATA_ONE_HIGH_TICKS APB1_TICKS(1800) +#define DATA_ONE_MIN_DURATION_TICKS APB1_TICKS(2050) +#define DATA_ONE_MAX_DURATION_TICKS APB1_TICKS(2750) /* Time from low that it should be safe to sample an ACK */ #define NOMINAL_SAMPLE_TIME_TICKS APB1_TICKS(1050) -#define DATA_TIME(type, data) ((data) ? (DATA_ONE_ ## type ## _TICKS) : \ - (DATA_ZERO_ ## type ## _TICKS)) +#define DATA_TIME(type, data) \ + ((data) ? (DATA_ONE_##type##_TICKS) : (DATA_ZERO_##type##_TICKS)) #define DATA_HIGH(data) DATA_TIME(HIGH, data) #define DATA_LOW(data) DATA_TIME(LOW, data) @@ -119,26 +119,26 @@ * sure that if we get a timeout, something is wrong. */ #define CAP_START_LOW_TICKS (START_BIT_MAX_LOW_TICKS + VALID_TOLERANCE_TICKS) -#define CAP_START_HIGH_TICKS (START_BIT_MAX_DURATION_TICKS - \ - START_BIT_MIN_LOW_TICKS + \ - VALID_TOLERANCE_TICKS) +#define CAP_START_HIGH_TICKS \ + (START_BIT_MAX_DURATION_TICKS - START_BIT_MIN_LOW_TICKS + \ + VALID_TOLERANCE_TICKS) #define CAP_DATA_LOW_TICKS (DATA_ZERO_MAX_LOW_TICKS + VALID_TOLERANCE_TICKS) -#define CAP_DATA_HIGH_TICKS (DATA_ONE_MAX_DURATION_TICKS - \ - DATA_ONE_MIN_LOW_TICKS + \ - VALID_TOLERANCE_TICKS) +#define CAP_DATA_HIGH_TICKS \ + (DATA_ONE_MAX_DURATION_TICKS - DATA_ONE_MIN_LOW_TICKS + \ + VALID_TOLERANCE_TICKS) -#define VALID_TIME(type, bit, t) \ - ((t) >= ((bit ## _MIN_ ## type ## _TICKS) - (VALID_TOLERANCE_TICKS)) \ - && (t) <= (bit ##_MAX_ ## type ## _TICKS) + (VALID_TOLERANCE_TICKS)) +#define VALID_TIME(type, bit, t) \ + ((t) >= ((bit##_MIN_##type##_TICKS) - (VALID_TOLERANCE_TICKS)) && \ + (t) <= (bit##_MAX_##type##_TICKS) + (VALID_TOLERANCE_TICKS)) #define VALID_LOW(bit, t) VALID_TIME(LOW, bit, t) -#define VALID_HIGH(bit, low_time, high_time) \ - (((low_time) + (high_time) <= \ - bit ## _MAX_DURATION_TICKS + VALID_TOLERANCE_TICKS) && \ - ((low_time) + (high_time) >= \ - bit ## _MIN_DURATION_TICKS - VALID_TOLERANCE_TICKS)) -#define VALID_DATA_HIGH(data, low_time, high_time) ((data) ? \ - VALID_HIGH(DATA_ONE, low_time, high_time) : \ - VALID_HIGH(DATA_ZERO, low_time, high_time)) +#define VALID_HIGH(bit, low_time, high_time) \ + (((low_time) + (high_time) <= \ + bit##_MAX_DURATION_TICKS + VALID_TOLERANCE_TICKS) && \ + ((low_time) + (high_time) >= \ + bit##_MIN_DURATION_TICKS - VALID_TOLERANCE_TICKS)) +#define VALID_DATA_HIGH(data, low_time, high_time) \ + ((data) ? VALID_HIGH(DATA_ONE, low_time, high_time) : \ + VALID_HIGH(DATA_ZERO, low_time, high_time)) /* * CEC state machine states. Each state typically takes action on entry and @@ -179,10 +179,7 @@ enum cec_state { }; /* Edge to trigger capture timer interrupt on */ -enum cap_edge { - CAP_EDGE_FALLING, - CAP_EDGE_RISING -}; +enum cap_edge { CAP_EDGE_FALLING, CAP_EDGE_RISING }; /* Receive buffer and states */ struct cec_rx { @@ -408,13 +405,13 @@ void enter_state(enum cec_state new_state) break; case CEC_STATE_INITIATOR_EOM_LOW: gpio = 0; - timeout = DATA_LOW(cec_transfer_is_eom(&cec_tx.transfer, - cec_tx.len)); + timeout = DATA_LOW( + cec_transfer_is_eom(&cec_tx.transfer, cec_tx.len)); break; case CEC_STATE_INITIATOR_EOM_HIGH: gpio = 1; - timeout = DATA_HIGH(cec_transfer_is_eom(&cec_tx.transfer, - cec_tx.len)); + timeout = DATA_HIGH( + cec_transfer_is_eom(&cec_tx.transfer, cec_tx.len)); break; case CEC_STATE_INITIATOR_ACK_LOW: gpio = 0; @@ -423,8 +420,8 @@ void enter_state(enum cec_state new_state) case CEC_STATE_INITIATOR_ACK_HIGH: gpio = 1; /* Aim for the middle of the safe sample time */ - timeout = (DATA_ONE_LOW_TICKS + DATA_ZERO_LOW_TICKS)/2 - - DATA_ONE_LOW_TICKS; + timeout = (DATA_ONE_LOW_TICKS + DATA_ZERO_LOW_TICKS) / 2 - + DATA_ONE_LOW_TICKS; break; case CEC_STATE_INITIATOR_ACK_VERIFY: cec_tx.ack = !gpio_get_level(CEC_GPIO_OUT); @@ -523,7 +520,8 @@ void enter_state(enum cec_state new_state) cap_edge = CAP_EDGE_FALLING; timeout = CAP_DATA_HIGH_TICKS; break; - /* No default case, since all states must be handled explicitly */ + /* No default case, since all states must be handled explicitly + */ } if (gpio >= 0) @@ -594,8 +592,7 @@ static void cec_event_timeout(void) cec_tx.len = 0; cec_tx.resends = 0; enter_state(CEC_STATE_IDLE); - task_set_event(TASK_ID_CEC, - TASK_EVENT_OKAY); + task_set_event(TASK_ID_CEC, TASK_EVENT_OKAY); } } else { if (cec_tx.resends < CEC_MAX_RESENDS) { @@ -607,8 +604,7 @@ static void cec_event_timeout(void) cec_tx.len = 0; cec_tx.resends = 0; enter_state(CEC_STATE_IDLE); - task_set_event(TASK_ID_CEC, - TASK_EVENT_FAILED); + task_set_event(TASK_ID_CEC, TASK_EVENT_FAILED); } } break; @@ -645,7 +641,6 @@ static void cec_event_timeout(void) case CEC_STATE_FOLLOWER_DATA_HIGH: enter_state(CEC_STATE_IDLE); break; - } } @@ -672,7 +667,7 @@ static void cec_event_cap(void) break; case CEC_STATE_FOLLOWER_START_LOW: /* Rising edge of start bit, validate low time */ - t = tmr_cap_get(); + t = tmr_cap_get(); if (VALID_LOW(START_BIT, t)) { cec_rx.low_ticks = t; enter_state(CEC_STATE_FOLLOWER_START_HIGH); @@ -942,7 +937,6 @@ static enum ec_status hc_cec_set(struct host_cmd_handler_args *args) } DECLARE_HOST_COMMAND(EC_CMD_CEC_SET, hc_cec_set, EC_VER_MASK(0)); - static enum ec_status hc_cec_get(struct host_cmd_handler_args *args) { struct ec_response_cec_get *response = args->response; @@ -990,13 +984,12 @@ static int cec_get_next_msg(uint8_t *out) } DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_CEC_MESSAGE, cec_get_next_msg); - static void cec_init(void) { int mdl = NPCX_MFT_MODULE_1; /* APB1 is the clock we base the timers on */ - apb1_freq_div_10k = clock_get_apb1_freq()/10000; + apb1_freq_div_10k = clock_get_apb1_freq() / 10000; /* Ensure Multi-Function timer is powered up. */ CLEAR_BIT(NPCX_PWDWN_CTL(mdl), NPCX_PWDWN_CTL1_MFT1_PD); diff --git a/chip/npcx/clock.c b/chip/npcx/clock.c index 4656e83a52..1ab4d1063a 100644 --- a/chip/npcx/clock.c +++ b/chip/npcx/clock.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -26,10 +26,10 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) -#define WAKE_INTERVAL 61 /* Unit: 61 usec */ -#define IDLE_PARAMS 0x7 /* Support deep idle, instant wake-up */ +#define WAKE_INTERVAL 61 /* Unit: 61 usec */ +#define IDLE_PARAMS 0x7 /* Support deep idle, instant wake-up */ /* Low power idle statistics */ #ifdef CONFIG_LOW_POWER_IDLE @@ -40,7 +40,7 @@ static uint64_t idle_dsleep_time_us; * Fixed amount of time to keep the console in use flag true after boot in * order to give a permanent window in which the low speed clock is not used. */ -#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND) +#define CONSOLE_IN_USE_ON_BOOT_TIME (15 * SECOND) static int console_in_use_timeout_sec = 15; static timestamp_t console_expire_time; #endif @@ -79,7 +79,6 @@ void clock_disable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode) /* Set PD bit to 1 */ NPCX_PWDWN_CTL(offset) |= reg_mask; - } /*****************************************************************************/ @@ -100,13 +99,13 @@ void clock_init(void) * unstable for a little which can affect peripheral communication like * eSPI. Skip this if not needed (e.g. RW jump) */ - if (NPCX_HFCGN != HFCGN || NPCX_HFCGML != HFCGML - || NPCX_HFCGMH != HFCGMH) { + if (NPCX_HFCGN != HFCGN || NPCX_HFCGML != HFCGML || + NPCX_HFCGMH != HFCGMH) { /* * Configure frequency multiplier M/N values according to * the requested OSC_CLK (Unit:Hz). */ - NPCX_HFCGN = HFCGN; + NPCX_HFCGN = HFCGN; NPCX_HFCGML = HFCGML; NPCX_HFCGMH = HFCGMH; @@ -119,11 +118,11 @@ void clock_init(void) /* Set all clock prescalers of core and peripherals. */ #if defined(CHIP_FAMILY_NPCX5) - NPCX_HFCGP = (FPRED << 4); + NPCX_HFCGP = (FPRED << 4); NPCX_HFCBCD = (NPCX_HFCBCD & 0xF0) | (APB1DIV | (APB2DIV << 2)); #elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7 - NPCX_HFCGP = ((FPRED << 4) | AHB6DIV); - NPCX_HFCBCD = (FIUDIV << 4); + NPCX_HFCGP = ((FPRED << 4) | AHB6DIV); + NPCX_HFCBCD = (FIUDIV << 4); NPCX_HFCBCD1 = (APB1DIV | (APB2DIV << 4)); #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9 NPCX_HFCBCD2 = (APB3DIV | (APB4DIV << 4)); @@ -143,7 +142,7 @@ void clock_init(void) void clock_turbo(void) { /* Configure Frequency multiplier values to 50MHz */ - NPCX_HFCGN = 0x02; + NPCX_HFCGN = 0x02; NPCX_HFCGML = 0xEC; NPCX_HFCGMH = 0x0B; @@ -255,7 +254,8 @@ int clock_get_apb3_freq(void) void clock_wait_cycles(uint32_t cycles) { asm volatile("1: subs %0, #1\n" - " bne 1b\n" : "+r"(cycles)); + " bne 1b\n" + : "+r"(cycles)); } #ifdef CONFIG_LOW_POWER_IDLE @@ -378,12 +378,11 @@ void __idle(void) * more detail. * Workaround: Apply the same bypass of idle. */ - asm ("push {r0-r5}\n" - "wfi\n" - "ldm %0, {r0-r5}\n" - "pop {r0-r5}\n" - "isb\n" :: "r" (0x100A8000) - ); + asm("push {r0-r5}\n" + "wfi\n" + "ldm %0, {r0-r5}\n" + "pop {r0-r5}\n" + "isb\n" ::"r"(0x100A8000)); /* Get time delay cause of deep idle */ next_evt_us = __hw_clock_get_sleep_time(evt_count); @@ -431,12 +430,11 @@ void __idle(void) * TODO (ML): Workaround method for wfi issue. * Please see task.c for more detail */ - asm ("push {r0-r5}\n" - "wfi\n" - "ldm %0, {r0-r5}\n" - "pop {r0-r5}\n" - "isb\n" :: "r" (0x100A8000) - ); + asm("push {r0-r5}\n" + "wfi\n" + "ldm %0, {r0-r5}\n" + "pop {r0-r5}\n" + "isb\n" ::"r"(0x100A8000)); } /* @@ -448,30 +446,28 @@ void __idle(void) } #endif /* CONFIG_LOW_POWER_IDLE */ - #ifdef CONFIG_LOW_POWER_IDLE /** * Print low power idle statistics */ -static int command_idle_stats(int argc, char **argv) +static int command_idle_stats(int argc, const char **argv) { timestamp_t ts = get_time(); ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt); ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt); ccprintf("Time spent in deep-sleep: %.6llds\n", - idle_dsleep_time_us); + idle_dsleep_time_us); ccprintf("Total time on: %.6llds\n", ts.val); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, - "", - "Print last idle stats"); +DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "", + "Print last idle stats"); /** * Configure deep sleep clock settings. */ -static int command_dsleep(int argc, char **argv) +static int command_dsleep(int argc, const char **argv) { int v; @@ -501,17 +497,16 @@ static int command_dsleep(int argc, char **argv) ccprintf("Sleep mask: %08x\n", (int)sleep_mask); ccprintf("Console in use timeout: %d sec\n", - console_in_use_timeout_sec); + console_in_use_timeout_sec); ccprintf("PMCSR register: 0x%02x\n", NPCX_PMCSR); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep, - "[ on | off | <timeout> sec]", - "Deep sleep clock settings:\nUse 'on' to force deep " - "sleep not to use low speed clock.\nUse 'off' to " - "allow deep sleep to auto-select using the low speed " - "clock.\n" - "Give a timeout value for the console in use timeout.\n" - "See also 'sleepmask'."); +DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep, "[ on | off | <timeout> sec]", + "Deep sleep clock settings:\nUse 'on' to force deep " + "sleep not to use low speed clock.\nUse 'off' to " + "allow deep sleep to auto-select using the low speed " + "clock.\n" + "Give a timeout value for the console in use timeout.\n" + "See also 'sleepmask'."); #endif /* CONFIG_LOW_POWER_IDLE */ diff --git a/chip/npcx/clock_chip.h b/chip/npcx/clock_chip.h index 702b55c52a..c105194fdf 100644 --- a/chip/npcx/clock_chip.h +++ b/chip/npcx/clock_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -95,40 +95,40 @@ * OSC_CLK (Unit:Hz). */ #if (OSC_CLK > 80000000) -#define HFCGN 0x82 /* Set XF_RANGE as 1 if OSC_CLK >= 80MHz */ +#define HFCGN 0x82 /* Set XF_RANGE as 1 if OSC_CLK >= 80MHz */ #else -#define HFCGN 0x02 +#define HFCGN 0x02 #endif -#if (OSC_CLK == 100000000) -#define HFCGMH 0x0B -#define HFCGML 0xEC +#if (OSC_CLK == 100000000) +#define HFCGMH 0x0B +#define HFCGML 0xEC #elif (OSC_CLK == 90000000) -#define HFCGMH 0x0A -#define HFCGML 0xBA +#define HFCGMH 0x0A +#define HFCGML 0xBA #elif (OSC_CLK == 80000000) -#define HFCGMH 0x09 -#define HFCGML 0x89 +#define HFCGMH 0x09 +#define HFCGML 0x89 #elif (OSC_CLK == 66000000) -#define HFCGMH 0x0F -#define HFCGML 0xBC +#define HFCGMH 0x0F +#define HFCGML 0xBC #elif (OSC_CLK == 50000000) -#define HFCGMH 0x0B -#define HFCGML 0xEC +#define HFCGMH 0x0B +#define HFCGML 0xEC #elif (OSC_CLK == 48000000) -#define HFCGMH 0x0B -#define HFCGML 0x72 +#define HFCGMH 0x0B +#define HFCGML 0x72 #elif (OSC_CLK == 40000000) -#define HFCGMH 0x09 -#define HFCGML 0x89 +#define HFCGMH 0x09 +#define HFCGML 0x89 #elif (OSC_CLK == 33000000) -#define HFCGMH 0x07 -#define HFCGML 0xDE +#define HFCGMH 0x07 +#define HFCGML 0xDE #elif (OSC_CLK == 30000000) -#define HFCGMH 0x07 -#define HFCGML 0x27 +#define HFCGMH 0x07 +#define HFCGML 0x27 #elif (OSC_CLK == 26000000) -#define HFCGMH 0x06 -#define HFCGML 0x33 +#define HFCGMH 0x06 +#define HFCGML 0x33 #else #error "Unsupported OSC_CLK Frequency" #endif diff --git a/chip/npcx/config_chip-npcx5.h b/chip/npcx/config_chip-npcx5.h index 434caba1d8..53713b2dfb 100644 --- a/chip/npcx/config_chip-npcx5.h +++ b/chip/npcx/config_chip-npcx5.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,10 +14,10 @@ */ /* Chip ID for all variants */ -#define NPCX585G_CHIP_ID 0x12 -#define NPCX575G_CHIP_ID 0x13 -#define NPCX586G_CHIP_ID 0x16 -#define NPCX576G_CHIP_ID 0x17 +#define NPCX585G_CHIP_ID 0x12 +#define NPCX575G_CHIP_ID 0x13 +#define NPCX586G_CHIP_ID 0x16 +#define NPCX576G_CHIP_ID 0x17 /*****************************************************************************/ /* Hardware features */ @@ -37,18 +37,18 @@ */ #define CONFIG_I2C_MULTI_PORT_CONTROLLER /* Number of I2C controllers */ -#define I2C_CONTROLLER_COUNT 4 +#define I2C_CONTROLLER_COUNT 4 /* Number of I2C ports */ -#define I2C_PORT_COUNT 5 +#define I2C_PORT_COUNT 5 /*****************************************************************************/ /* Memory mapping */ -#define NPCX_BTRAM_SIZE 0x800 /* 2KB data ram used by booter. */ -#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ -#define CONFIG_DATA_RAM_SIZE 0x00008000 /* Size of data RAM */ -#define CONFIG_RAM_SIZE (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE) -#define CONFIG_LPRAM_BASE 0x40001600 /* memory address of lpwr ram */ -#define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */ +#define NPCX_BTRAM_SIZE 0x800 /* 2KB data ram used by booter. */ +#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ +#define CONFIG_DATA_RAM_SIZE 0x00008000 /* Size of data RAM */ +#define CONFIG_RAM_SIZE (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE) +#define CONFIG_LPRAM_BASE 0x40001600 /* memory address of lpwr ram */ +#define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */ /* Use chip variant to specify the size and start address of program memory */ #if defined(CHIP_VARIANT_NPCX5M5G) diff --git a/chip/npcx/config_chip-npcx7.h b/chip/npcx/config_chip-npcx7.h index 8404f16635..e44aebe6cf 100644 --- a/chip/npcx/config_chip-npcx7.h +++ b/chip/npcx/config_chip-npcx7.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -16,26 +16,27 @@ */ /* Chip ID for all variants */ -#define NPCX787G_CHIP_ID 0x1F -#define NPCX796F_A_B_CHIP_ID 0x21 -#define NPCX796F_C_CHIP_ID 0x29 -#define NPCX797F_C_CHIP_ID 0x20 -#define NPCX797W_B_CHIP_ID 0x24 -#define NPCX797W_C_CHIP_ID 0x2C +#define NPCX787G_CHIP_ID 0x1F +#define NPCX796F_A_B_CHIP_ID 0x21 +#define NPCX796F_C_CHIP_ID 0x29 +#define NPCX797F_C_CHIP_ID 0x20 +#define NPCX797W_B_CHIP_ID 0x24 +#define NPCX797W_C_CHIP_ID 0x2C /*****************************************************************************/ /* Hardware features */ /* The optional hardware features depend on chip variant */ -#if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \ +#if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \ defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M7FC) || \ defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC) #define NPCX_INT_FLASH_SUPPORT /* Internal flash support */ -#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power */ +#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power \ + */ #define NPCX_EXT32K_OSC_SUPPORT /* External 32KHz crytal osc. input support */ #endif -#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \ +#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \ defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \ defined(CHIP_VARIANT_NPCX7M7WC) #define NPCX_UART_FIFO_SUPPORT @@ -90,68 +91,68 @@ /*****************************************************************************/ /* Memory mapping */ -#define NPCX_BTRAM_SIZE 0x800 /* 2KB data ram used by booter. */ +#define NPCX_BTRAM_SIZE 0x800 /* 2KB data ram used by booter. */ #define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE) #if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \ defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M6G) - /* 192KB RAM for FW code */ -# define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024) - /* program memory base address for Code RAM (0x100C0000 - 192KB) */ -# define CONFIG_PROGRAM_MEMORY_BASE 0x10090000 -# define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ - /* 62 KB data RAM + 2 KB BT RAM size */ -# define CONFIG_DATA_RAM_SIZE 0x00010000 +/* 192KB RAM for FW code */ +#define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024) +/* program memory base address for Code RAM (0x100C0000 - 192KB) */ +#define CONFIG_PROGRAM_MEMORY_BASE 0x10090000 +#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ +/* 62 KB data RAM + 2 KB BT RAM size */ +#define CONFIG_DATA_RAM_SIZE 0x00010000 #elif defined(CHIP_VARIANT_NPCX7M7WB) - /* 256KB RAM for FW code */ -# define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024) - /* program memory base address for Code RAM (0x100B0000 - 256KB) */ -# define CONFIG_PROGRAM_MEMORY_BASE 0x10070000 -# define CONFIG_RAM_BASE 0x200B0000 /* memory address of data ram */ - /* 126 KB data RAM + 2 KB BT RAM size */ -# define CONFIG_DATA_RAM_SIZE 0x00020000 +/* 256KB RAM for FW code */ +#define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024) +/* program memory base address for Code RAM (0x100B0000 - 256KB) */ +#define CONFIG_PROGRAM_MEMORY_BASE 0x10070000 +#define CONFIG_RAM_BASE 0x200B0000 /* memory address of data ram */ +/* 126 KB data RAM + 2 KB BT RAM size */ +#define CONFIG_DATA_RAM_SIZE 0x00020000 #elif defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WC) - /* - * Code RAM is normally assumed to be same as image size, but since - * we exclude 4k from the image (see NPCX_PROGRAM_MEMORY_SIZE) we - * need to explicitly configure it. This is the actual size of code - * RAM on-chip. - */ -# define CONFIG_CODE_RAM_SIZE (256 * 1024) - /* - * In npcx797wc and npcx797fc, the code RAM size is limited by the - * internal flash size (i.e. 512 KB/2=256 KB.) The driver has to - * re-organize the memory to: - * 1. the overall memory (RAM) layout is re-organized against the - * datasheet: - * In datasheet: 320 KB code RAM + 64 KB data RAM - * After re-organization: 256 KB code RAM + 128 KB data RAM. - * 2. 256KB program RAM, but only 512K of Flash (vs 1M for the - * -WB). After the boot header is added, a 256K image would be - * too large to fit in either RO or RW sections of Flash (each - * of which is half of it). Because other code assumes that - * image size is a multiple of Flash erase granularity, we - * sacrifice a whole sector. - */ -# define NPCX_PROGRAM_MEMORY_SIZE (CONFIG_CODE_RAM_SIZE - 0x1000) - /* program memory base address for Code RAM (0x100B0000 - 256KB) */ -# define CONFIG_PROGRAM_MEMORY_BASE 0x10070000 -# define CONFIG_RAM_BASE 0x200B0000 /* memory address of data ram */ - /* 126 KB data RAM + 2 KB BT RAM size */ -# define CONFIG_DATA_RAM_SIZE 0x00020000 - - /* - * Override default NPCX_RAM_SIZE because NPCX_PROGRAM_MEMORY_SIZE - * is not the actual size of code RAM. - */ -# undef NPCX_RAM_SIZE -# define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + CONFIG_CODE_RAM_SIZE) +/* + * Code RAM is normally assumed to be same as image size, but since + * we exclude 4k from the image (see NPCX_PROGRAM_MEMORY_SIZE) we + * need to explicitly configure it. This is the actual size of code + * RAM on-chip. + */ +#define CONFIG_CODE_RAM_SIZE (256 * 1024) +/* + * In npcx797wc and npcx797fc, the code RAM size is limited by the + * internal flash size (i.e. 512 KB/2=256 KB.) The driver has to + * re-organize the memory to: + * 1. the overall memory (RAM) layout is re-organized against the + * datasheet: + * In datasheet: 320 KB code RAM + 64 KB data RAM + * After re-organization: 256 KB code RAM + 128 KB data RAM. + * 2. 256KB program RAM, but only 512K of Flash (vs 1M for the + * -WB). After the boot header is added, a 256K image would be + * too large to fit in either RO or RW sections of Flash (each + * of which is half of it). Because other code assumes that + * image size is a multiple of Flash erase granularity, we + * sacrifice a whole sector. + */ +#define NPCX_PROGRAM_MEMORY_SIZE (CONFIG_CODE_RAM_SIZE - 0x1000) +/* program memory base address for Code RAM (0x100B0000 - 256KB) */ +#define CONFIG_PROGRAM_MEMORY_BASE 0x10070000 +#define CONFIG_RAM_BASE 0x200B0000 /* memory address of data ram */ +/* 126 KB data RAM + 2 KB BT RAM size */ +#define CONFIG_DATA_RAM_SIZE 0x00020000 + +/* + * Override default NPCX_RAM_SIZE because NPCX_PROGRAM_MEMORY_SIZE + * is not the actual size of code RAM. + */ +#undef NPCX_RAM_SIZE +#define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + CONFIG_CODE_RAM_SIZE) #else -# error "Unsupported chip variant" +#error "Unsupported chip variant" #endif -#define CONFIG_RAM_SIZE (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE) +#define CONFIG_RAM_SIZE (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE) /* no low power ram in npcx7 series */ #endif /* __CROS_EC_CONFIG_CHIP_NPCX7_H */ diff --git a/chip/npcx/config_chip-npcx9.h b/chip/npcx/config_chip-npcx9.h index 7f154dbe42..736aef8a1c 100644 --- a/chip/npcx/config_chip-npcx9.h +++ b/chip/npcx/config_chip-npcx9.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -16,8 +16,8 @@ */ /* Chip ID for all variants */ -#define NPCX996F_CHIP_ID 0x21 -#define NPCX993F_CHIP_ID 0x25 +#define NPCX996F_CHIP_ID 0x21 +#define NPCX993F_CHIP_ID 0x25 /*****************************************************************************/ /* Hardware features */ @@ -25,7 +25,8 @@ #define NPCX_EXT32K_OSC_SUPPORT /* External 32KHz crytal osc. input support */ #define NPCX_INT_FLASH_SUPPORT /* Internal flash support */ #define NPCX_LCT_SUPPORT /* Long Countdown Timer support */ -#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power */ +#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power \ + */ #define NPCX_UART_FIFO_SUPPORT /* Number of UART modules. */ @@ -55,10 +56,10 @@ /* PSL_OUT optional configuration */ /* Set PSL_OUT mode to pulse mode */ -#define NPCX_PSL_CFG_PSL_OUT_PULSE BIT(0) +#define NPCX_PSL_CFG_PSL_OUT_PULSE BIT(0) /* set PSL_OUT to open-drain */ -#define NPCX_PSL_CFG_PSL_OUT_OD BIT(1) -#define CONFIG_HIBERNATE_PSL_OUT_FLAGS 0 +#define NPCX_PSL_CFG_PSL_OUT_OD BIT(1) +#define CONFIG_HIBERNATE_PSL_OUT_FLAGS 0 /* * Workaound the issue 3.10 in the NPCX99nF errata rev1.2 @@ -75,36 +76,35 @@ #define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE) #if defined(CHIP_VARIANT_NPCX9M3F) - /* - * 256KB program RAM, but only 512K of Flash. After the boot header is - * added, a 256K image would be too large to fit in either RO or RW - * sections of Flash (each of which is half of it). Because other code - * assumes that image size is a multiple of Flash erase granularity, we - * sacrifice a whole sector. - */ -# define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024 - 0x1000) - /* program memory base address for Code RAM (0x100C0000 - 256KB) */ -# define CONFIG_PROGRAM_MEMORY_BASE 0x10080000 -# define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ - /* Two blocks of data RAM - total size is 64KB */ -# define CONFIG_DATA_RAM_SIZE 0x00010000 -# define CONFIG_RAM_SIZE CONFIG_DATA_RAM_SIZE - - /* Override default NPCX_RAM_SIZE because we're excluding a block. */ -# undef NPCX_RAM_SIZE -# define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + \ - NPCX_PROGRAM_MEMORY_SIZE + 0x1000) +/* + * 256KB program RAM, but only 512K of Flash. After the boot header is + * added, a 256K image would be too large to fit in either RO or RW + * sections of Flash (each of which is half of it). Because other code + * assumes that image size is a multiple of Flash erase granularity, we + * sacrifice a whole sector. + */ +#define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024 - 0x1000) +/* program memory base address for Code RAM (0x100C0000 - 256KB) */ +#define CONFIG_PROGRAM_MEMORY_BASE 0x10080000 +#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ +/* Two blocks of data RAM - total size is 64KB */ +#define CONFIG_DATA_RAM_SIZE 0x00010000 +#define CONFIG_RAM_SIZE CONFIG_DATA_RAM_SIZE + +/* Override default NPCX_RAM_SIZE because we're excluding a block. */ +#undef NPCX_RAM_SIZE +#define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE + 0x1000) #elif defined(CHIP_VARIANT_NPCX9M6F) - /* 192KB RAM for FW code */ -# define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024) - /* program memory base address for Code RAM (0x100C0000 - 192KB) */ -# define CONFIG_PROGRAM_MEMORY_BASE 0x10090000 -# define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ - /* Two blocks of data RAM - total size is 64KB */ -# define CONFIG_DATA_RAM_SIZE 0x00010000 -# define CONFIG_RAM_SIZE CONFIG_DATA_RAM_SIZE +/* 192KB RAM for FW code */ +#define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024) +/* program memory base address for Code RAM (0x100C0000 - 192KB) */ +#define CONFIG_PROGRAM_MEMORY_BASE 0x10090000 +#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ +/* Two blocks of data RAM - total size is 64KB */ +#define CONFIG_DATA_RAM_SIZE 0x00010000 +#define CONFIG_RAM_SIZE CONFIG_DATA_RAM_SIZE #else -# error "Unsupported chip variant" +#error "Unsupported chip variant" #endif /* Internal spi-flash setting */ @@ -112,5 +112,4 @@ #define CONFIG_SPI_FLASH_W25Q40 /* Internal spi flash type */ #define CONFIG_FLASH_SIZE_BYTES 0x00080000 /* 512 KB internal spi flash */ - #endif /* __CROS_EC_CONFIG_CHIP_NPCX9_H */ diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h index c397161e07..d0bfe0a767 100644 --- a/chip/npcx/config_chip.h +++ b/chip/npcx/config_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -13,20 +13,20 @@ * Set the chip family version to 4 digits to keep the flexibility in case * we need the minor version for chip variants in a family. */ -#define NPCX_FAMILY_NPCX5 5000 -#define NPCX_FAMILY_NPCX7 7000 -#define NPCX_FAMILY_NPCX9 9000 +#define NPCX_FAMILY_NPCX5 5000 +#define NPCX_FAMILY_NPCX7 7000 +#define NPCX_FAMILY_NPCX9 9000 /* Features depend on chip family */ #if defined(CHIP_FAMILY_NPCX5) #include "config_chip-npcx5.h" -#define NPCX_FAMILY_VERSION NPCX_FAMILY_NPCX5 +#define NPCX_FAMILY_VERSION NPCX_FAMILY_NPCX5 #elif defined(CHIP_FAMILY_NPCX7) #include "config_chip-npcx7.h" -#define NPCX_FAMILY_VERSION NPCX_FAMILY_NPCX7 +#define NPCX_FAMILY_VERSION NPCX_FAMILY_NPCX7 #elif defined(CHIP_FAMILY_NPCX9) #include "config_chip-npcx9.h" -#define NPCX_FAMILY_VERSION NPCX_FAMILY_NPCX9 +#define NPCX_FAMILY_VERSION NPCX_FAMILY_NPCX9 #else #error "Unsupported chip family" #endif @@ -46,27 +46,27 @@ * Notice instant wake-up from deep-idle cannot exceed 200 ms */ #define HOOK_TICK_INTERVAL_MS 200 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) +#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) /* System stack size */ -#define CONFIG_STACK_SIZE 1024 +#define CONFIG_STACK_SIZE 1024 /* non-standard task stack sizes */ -#define IDLE_TASK_STACK_SIZE 672 -#define LARGER_TASK_STACK_SIZE 800 -#define VENTI_TASK_STACK_SIZE 928 -#define ULTRA_TASK_STACK_SIZE 1056 -#define TRENTA_TASK_STACK_SIZE 1184 +#define IDLE_TASK_STACK_SIZE 672 +#define LARGER_TASK_STACK_SIZE 800 +#define VENTI_TASK_STACK_SIZE 928 +#define ULTRA_TASK_STACK_SIZE 1056 +#define TRENTA_TASK_STACK_SIZE 1184 -#define CHARGER_TASK_STACK_SIZE 800 -#define HOOKS_TASK_STACK_SIZE 800 -#define CONSOLE_TASK_STACK_SIZE 800 +#define CHARGER_TASK_STACK_SIZE 800 +#define HOOKS_TASK_STACK_SIZE 800 +#define CONSOLE_TASK_STACK_SIZE 800 /* Default task stack size */ -#define TASK_STACK_SIZE 672 +#define TASK_STACK_SIZE 672 /* Address of RAM log used by Booter */ -#define ADDR_BOOT_RAMLOG 0x100C7FC0 +#define ADDR_BOOT_RAMLOG 0x100C7FC0 #include "config_flash_layout.h" @@ -79,7 +79,7 @@ /* Chip needs to do custom pre-init */ #define CONFIG_CHIP_PRE_INIT /* Default use UART1 as console */ -#define CONFIG_CONSOLE_UART 0 +#define CONFIG_CONSOLE_UART 0 #define GPIO_PIN(port, index) GPIO_##port, BIT(index) #define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m) @@ -88,4 +88,4 @@ #define NPCX_SELECT_KSI_TO_GPIO #endif -#endif /* __CROS_EC_CONFIG_CHIP_H */ +#endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/npcx/config_flash_layout.h b/chip/npcx/config_flash_layout.h index 79961548c9..926a03bb3c 100644 --- a/chip/npcx/config_flash_layout.h +++ b/chip/npcx/config_flash_layout.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -18,56 +18,56 @@ #define CONFIG_MAPPED_STORAGE /* Storage is memory-mapped, but program runs from SRAM */ #define CONFIG_MAPPED_STORAGE_BASE 0x64000000 -#undef CONFIG_FLASH_PSTATE +#undef CONFIG_FLASH_PSTATE #if defined(CHIP_VARIANT_NPCX5M5G) -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000 -#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x20000 -#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000 +#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x20000 +#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000 #elif defined(CHIP_VARIANT_NPCX5M6G) -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000 -#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000 -#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000 -#elif defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \ +#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000 +#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000 +#elif defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \ defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M6G) || \ defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WC) -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000 -#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000 -#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000 +#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000 +#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000 #elif defined(CHIP_VARIANT_NPCX7M7WB) -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x80000 -#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x80000 -#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x80000 +#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x80000 +#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x80000 #elif defined(CHIP_VARIANT_NPCX9M3F) || defined(CHIP_VARIANT_NPCX9M6F) -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000 -#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000 -#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000 +#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000 +#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000 #else #error "Unsupported chip variant" #endif /* Header support which is used by booter to copy FW from flash to code ram */ #define NPCX_RO_HEADER -#define CONFIG_RO_HDR_MEM_OFF 0x0 -#define CONFIG_RO_HDR_SIZE 0x40 +#define CONFIG_RO_HDR_MEM_OFF 0x0 +#define CONFIG_RO_HDR_SIZE 0x40 -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE /* RO firmware in program memory - use all of program memory */ -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE NPCX_PROGRAM_MEMORY_SIZE +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_SIZE NPCX_PROGRAM_MEMORY_SIZE /* * ROM resident area in flash used to store data objects that are not copied * into code RAM. Enable using the CONFIG_CHIP_INIT_ROM_REGION option. */ -#define CONFIG_RO_ROM_RESIDENT_MEM_OFF CONFIG_RO_SIZE +#define CONFIG_RO_ROM_RESIDENT_MEM_OFF CONFIG_RO_SIZE #define CONFIG_RO_ROM_RESIDENT_SIZE \ (CONFIG_EC_PROTECTED_STORAGE_SIZE - CONFIG_RO_SIZE) @@ -75,10 +75,10 @@ * RW firmware in program memory - Identical to RO, only one image loaded at * a time. */ -#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF -#define CONFIG_RW_SIZE CONFIG_RO_SIZE +#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF +#define CONFIG_RW_SIZE CONFIG_RO_SIZE -#define CONFIG_RW_ROM_RESIDENT_MEM_OFF CONFIG_RW_SIZE +#define CONFIG_RW_ROM_RESIDENT_MEM_OFF CONFIG_RW_SIZE #define CONFIG_RW_ROM_RESIDENT_SIZE \ (CONFIG_EC_WRITABLE_STORAGE_SIZE - CONFIG_RW_SIZE) @@ -102,8 +102,8 @@ * writable flash regions are not a multiple of 64 KiB, then support * for CONFIG_FLASH_MULTIPLE_REGION must be added. */ -#define CONFIG_FLASH_ERASE_SIZE 0x10000 -#define NPCX_ERASE_COMMAND CMD_BLOCK_64K_ERASE +#define CONFIG_FLASH_ERASE_SIZE 0x10000 +#define NPCX_ERASE_COMMAND CMD_BLOCK_64K_ERASE #if (CONFIG_WP_STORAGE_SIZE != CONFIG_EC_WRITABLE_STORAGE_SIZE) #error "NPCX flash support assumes CONFIG_WP_STORAGE_SIZE and " \ @@ -120,16 +120,16 @@ "size or add support for CONFIG_FLASH_MULTIPLE_REGION." #endif -#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE -#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ +#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE +#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ /* Use 4k sector erase for NPCX monitor flash erase operations. */ -#define NPCX_MONITOR_FLASH_ERASE_SIZE 0x1000 +#define NPCX_MONITOR_FLASH_ERASE_SIZE 0x1000 /* RO image resides at start of protected region, right after header */ -#define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE +#define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE /* RW image resides at start of writable region */ -#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RW_STORAGE_OFF 0 #endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */ diff --git a/chip/npcx/espi.c b/chip/npcx/espi.c index 7248c7711f..d64a22860d 100644 --- a/chip/npcx/espi.c +++ b/chip/npcx/espi.c @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -24,114 +24,114 @@ #define CPRINTS(...) #else #define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) #endif /* Default eSPI configuration for VW events */ struct vwevms_config_t { - uint8_t idx; /* VW index */ - uint8_t idx_en; /* Index enable */ - uint8_t pltrst_en; /* Enable reset by PLTRST assert */ + uint8_t idx; /* VW index */ + uint8_t idx_en; /* Index enable */ + uint8_t pltrst_en; /* Enable reset by PLTRST assert */ uint8_t espirst_en; /* Enable reset by eSPI_RST assert */ - uint8_t int_en; /* Interrupt/Wake-up enable */ + uint8_t int_en; /* Interrupt/Wake-up enable */ }; struct vwevsm_config_t { - uint8_t idx; /* VW index */ - uint8_t idx_en; /* Index enable */ - uint8_t pltrst_en; /* Enable reset by PLTRST assert */ - uint8_t cdrst_en; /* Enable cold reset */ - uint8_t valid; /* Valid VW mask */ + uint8_t idx; /* VW index */ + uint8_t idx_en; /* Index enable */ + uint8_t pltrst_en; /* Enable reset by PLTRST assert */ + uint8_t cdrst_en; /* Enable cold reset */ + uint8_t valid; /* Valid VW mask */ }; /* Default MIWU configurations for VW events */ struct host_wui_item { uint16_t table : 2; /* MIWU table 0-2 */ uint16_t group : 3; /* MIWU group 0-7 */ - uint16_t num : 3; /* MIWU bit 0-7 */ - uint16_t edge : 4; /* MIWU edge trigger type rising/falling/any */ + uint16_t num : 3; /* MIWU bit 0-7 */ + uint16_t edge : 4; /* MIWU edge trigger type rising/falling/any */ }; /* Mapping item between VW signal, index and value */ struct vw_event_t { - uint16_t name; /* Name of signal */ - uint8_t evt_idx; /* VW index of signal */ - uint8_t evt_val; /* VW value of signal */ + uint16_t name; /* Name of signal */ + uint8_t evt_idx; /* VW index of signal */ + uint8_t evt_val; /* VW value of signal */ }; /* Default settings of VWEVMS registers (Please refer Table.43/44) */ static const struct vwevms_config_t espi_in_list[] = { - /* IDX EN ENPL ENESP IE/WE VW Event Bit 0 - 3 (M->S) */ -#ifdef CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST - {0x02, 1, 0, 1, 1}, /* SLP_S3#, SLP_S4#, SLP_S5#, Reserve */ +/* IDX EN ENPL ENESP IE/WE VW Event Bit 0 - 3 (M->S) */ +#ifdef CONFIG_HOST_INTERFACE_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST + { 0x02, 1, 0, 1, 1 }, /* SLP_S3#, SLP_S4#, SLP_S5#, Reserve */ #else - {0x02, 1, 0, 0, 1}, /* SLP_S3#, SLP_S4#, SLP_S5#, Reserve */ + { 0x02, 1, 0, 0, 1 }, /* SLP_S3#, SLP_S4#, SLP_S5#, Reserve */ #endif - {0x03, 1, 0, 1, 1}, /* SUS_STAT#, PLTRST#, ORST_WARN, Reserve */ - {0x07, 1, 1, 1, 1}, /* HRST_WARN, SMIOUT#, NMIOUT#, Reserve */ - {0x41, 1, 0, 1, 1}, /* SUS_WARN#, SPWRDN_ACK, Reserve, SLP_A# */ - {0x42, 1, 0, 0, 1}, /* SLP_LAN#, SLP_WAN#, Reserve, Reserve */ - {0x47, 1, 1, 1, 1}, /* HOST_C10, Reserve, Reserve, Reserve */ + { 0x03, 1, 0, 1, 1 }, /* SUS_STAT#, PLTRST#, ORST_WARN, Reserve */ + { 0x07, 1, 1, 1, 1 }, /* HRST_WARN, SMIOUT#, NMIOUT#, Reserve */ + { 0x41, 1, 0, 1, 1 }, /* SUS_WARN#, SPWRDN_ACK, Reserve, SLP_A# */ + { 0x42, 1, 0, 0, 1 }, /* SLP_LAN#, SLP_WAN#, Reserve, Reserve */ + { 0x47, 1, 1, 1, 1 }, /* HOST_C10, Reserve, Reserve, Reserve */ }; /* Default settings of VWEVSM registers (Please refer Table.43/44) */ static const struct vwevsm_config_t espi_out_list[] = { /* IDX EN ENPL ENCDR VDMASK VW Event Bit 0 - 3 (S->M) */ - {0x04, 1, 0, 0, 0x0D}, /* ORST_ACK, Reserve, WAKE#, PME# */ - {0x05, 1, 0, 0, 0x0F}, /* SLV_BL_DNE, ERR_F, ERR_NF, SLV_BL_STS */ + { 0x04, 1, 0, 0, 0x0D }, /* ORST_ACK, Reserve, WAKE#, PME# */ + { 0x05, 1, 0, 0, 0x0F }, /* SLV_BL_DNE, ERR_F, ERR_NF, SLV_BL_STS */ #ifdef CONFIG_SCI_GPIO - {0x06, 1, 1, 0, 0x0C}, /* SCI#, SMI#, RCIN#, HRST_ACK */ + { 0x06, 1, 1, 0, 0x0C }, /* SCI#, SMI#, RCIN#, HRST_ACK */ #else - {0x06, 1, 1, 0, 0x0F}, /* SCI#, SMI#, RCIN#, HRST_ACK */ + { 0x06, 1, 1, 0, 0x0F }, /* SCI#, SMI#, RCIN#, HRST_ACK */ #endif - {0x40, 1, 0, 0, 0x01}, /* SUS_ACK, Reserve, Reserve, Reserve */ + { 0x40, 1, 0, 0, 0x01 }, /* SUS_ACK, Reserve, Reserve, Reserve */ }; /* eSPI interrupts used in MIWU */ static const struct host_wui_item espi_vw_int_list[] = { /* ESPI_RESET */ - {MIWU_TABLE_0, MIWU_GROUP_5, 5, MIWU_EDGE_FALLING}, + { MIWU_TABLE_0, MIWU_GROUP_5, 5, MIWU_EDGE_FALLING }, /* SLP_S3 */ - {MIWU_TABLE_2, MIWU_GROUP_1, 0, MIWU_EDGE_ANYING}, + { MIWU_TABLE_2, MIWU_GROUP_1, 0, MIWU_EDGE_ANYING }, /* SLP_S4 */ - {MIWU_TABLE_2, MIWU_GROUP_1, 1, MIWU_EDGE_ANYING}, + { MIWU_TABLE_2, MIWU_GROUP_1, 1, MIWU_EDGE_ANYING }, /* SLP_S5 */ - {MIWU_TABLE_2, MIWU_GROUP_1, 2, MIWU_EDGE_ANYING}, + { MIWU_TABLE_2, MIWU_GROUP_1, 2, MIWU_EDGE_ANYING }, /* VW_WIRE_PLTRST */ - {MIWU_TABLE_2, MIWU_GROUP_1, 5, MIWU_EDGE_ANYING}, + { MIWU_TABLE_2, MIWU_GROUP_1, 5, MIWU_EDGE_ANYING }, /* VW_WIRE_OOB_RST_WARN */ - {MIWU_TABLE_2, MIWU_GROUP_1, 6, MIWU_EDGE_ANYING}, + { MIWU_TABLE_2, MIWU_GROUP_1, 6, MIWU_EDGE_ANYING }, /* VW_WIRE_HOST_RST_WARN */ - {MIWU_TABLE_2, MIWU_GROUP_2, 0, MIWU_EDGE_ANYING}, + { MIWU_TABLE_2, MIWU_GROUP_2, 0, MIWU_EDGE_ANYING }, /* VW_WIRE_SUS_WARN */ - {MIWU_TABLE_2, MIWU_GROUP_2, 4, MIWU_EDGE_ANYING}, + { MIWU_TABLE_2, MIWU_GROUP_2, 4, MIWU_EDGE_ANYING }, }; /* VW signals used in eSPI */ static const struct vw_event_t vw_events_list[] = { - {VW_SLP_S3_L, 0x02, 0x01}, /* index 02h (In) */ - {VW_SLP_S4_L, 0x02, 0x02}, - {VW_SLP_S5_L, 0x02, 0x04}, - {VW_SUS_STAT_L, 0x03, 0x01}, /* index 03h (In) */ - {VW_PLTRST_L, 0x03, 0x02}, - {VW_OOB_RST_WARN, 0x03, 0x04}, - {VW_OOB_RST_ACK, 0x04, 0x01}, /* index 04h (Out) */ - {VW_WAKE_L, 0x04, 0x04}, - {VW_PME_L, 0x04, 0x08}, - {VW_ERROR_FATAL, 0x05, 0x02}, /* index 05h (Out) */ - {VW_ERROR_NON_FATAL, 0x05, 0x04}, - {VW_PERIPHERAL_BTLD_STATUS_DONE, 0x05, 0x09}, - {VW_SCI_L, 0x06, 0x01}, /* index 06h (Out) */ - {VW_SMI_L, 0x06, 0x02}, - {VW_RCIN_L, 0x06, 0x04}, - {VW_HOST_RST_ACK, 0x06, 0x08}, - {VW_HOST_RST_WARN, 0x07, 0x01}, /* index 07h (In) */ - {VW_SUS_ACK, 0x40, 0x01}, /* index 40h (Out) */ - {VW_SUS_WARN_L, 0x41, 0x01}, /* index 41h (In) */ - {VW_SUS_PWRDN_ACK_L, 0x41, 0x02}, - {VW_SLP_A_L, 0x41, 0x08}, - {VW_SLP_LAN, 0x42, 0x01}, /* index 42h (In) */ - {VW_SLP_WLAN, 0x42, 0x02}, + { VW_SLP_S3_L, 0x02, 0x01 }, /* index 02h (In) */ + { VW_SLP_S4_L, 0x02, 0x02 }, + { VW_SLP_S5_L, 0x02, 0x04 }, + { VW_SUS_STAT_L, 0x03, 0x01 }, /* index 03h (In) */ + { VW_PLTRST_L, 0x03, 0x02 }, + { VW_OOB_RST_WARN, 0x03, 0x04 }, + { VW_OOB_RST_ACK, 0x04, 0x01 }, /* index 04h (Out) */ + { VW_WAKE_L, 0x04, 0x04 }, + { VW_PME_L, 0x04, 0x08 }, + { VW_ERROR_FATAL, 0x05, 0x02 }, /* index 05h (Out) */ + { VW_ERROR_NON_FATAL, 0x05, 0x04 }, + { VW_PERIPHERAL_BTLD_STATUS_DONE, 0x05, 0x09 }, + { VW_SCI_L, 0x06, 0x01 }, /* index 06h (Out) */ + { VW_SMI_L, 0x06, 0x02 }, + { VW_RCIN_L, 0x06, 0x04 }, + { VW_HOST_RST_ACK, 0x06, 0x08 }, + { VW_HOST_RST_WARN, 0x07, 0x01 }, /* index 07h (In) */ + { VW_SUS_ACK, 0x40, 0x01 }, /* index 40h (Out) */ + { VW_SUS_WARN_L, 0x41, 0x01 }, /* index 41h (In) */ + { VW_SUS_PWRDN_ACK_L, 0x41, 0x02 }, + { VW_SLP_A_L, 0x41, 0x08 }, + { VW_SLP_LAN, 0x42, 0x01 }, /* index 42h (In) */ + { VW_SLP_WLAN, 0x42, 0x02 }, }; /* Flag for boot load signals */ @@ -153,7 +153,7 @@ static void espi_reset_recovery(void) static void espi_vw_config_in(const struct vwevms_config_t *config) { uint32_t val; - uint8_t i, index; + uint8_t i, index; switch (VM_TYPE(config->idx)) { case ESPI_VW_TYPE_SYS_EV: @@ -164,11 +164,10 @@ static void espi_vw_config_in(const struct vwevms_config_t *config) if (index == config->idx) { /* Get Wire field */ val = NPCX_VWEVMS(i) & 0x0F; - val |= VWEVMS_FIELD(config->idx, - config->idx_en, - config->pltrst_en, - config->int_en, - config->espirst_en); + val |= VWEVMS_FIELD(config->idx, config->idx_en, + config->pltrst_en, + config->int_en, + config->espirst_en); NPCX_VWEVMS(i) = val; return; } @@ -196,11 +195,10 @@ static void espi_vw_config_out(const struct vwevsm_config_t *config) if (index == config->idx) { /* Preserve WIRE(3-0) and HW_WIRE (27-24). */ val = NPCX_VWEVSM(i) & 0x0F00000F; - val |= VWEVSM_FIELD(config->idx, - config->idx_en, - config->valid, - config->pltrst_en, - config->cdrst_en); + val |= VWEVSM_FIELD(config->idx, config->idx_en, + config->valid, + config->pltrst_en, + config->cdrst_en); NPCX_VWEVSM(i) = val; return; } @@ -218,8 +216,8 @@ static void espi_enable_vw_int(const struct host_wui_item *vwire_int) { uint8_t table = vwire_int->table; uint8_t group = vwire_int->group; - uint8_t num = vwire_int->num; - uint8_t edge = vwire_int->edge; + uint8_t num = vwire_int->num; + uint8_t edge = vwire_int->edge; /* Set detection mode to edge */ CLEAR_BIT(NPCX_WKMOD(table, group), num); @@ -266,7 +264,7 @@ void espi_vw_power_signal_interrupt(enum espi_vw_signal signal) { if (IS_ENABLED(CONFIG_HOST_ESPI_VW_POWER_SIGNAL)) /* TODO: Add VW handler in power/common.c */ - power_signal_interrupt((enum gpio_signal) signal); + power_signal_interrupt((enum gpio_signal)signal); } void espi_wait_vw_not_dirty(enum espi_vw_signal signal, unsigned int timeout_us) @@ -289,7 +287,7 @@ void espi_wait_vw_not_dirty(enum espi_vw_signal signal, unsigned int timeout_us) timeout = get_time().val + (uint64_t)timeout_us; while ((NPCX_VWEVSM(offset) & VWEVSM_DIRTY(1)) && - (get_time().val < timeout)) { + (get_time().val < timeout)) { udelay(10); } } @@ -609,12 +607,12 @@ static void espi_interrupt(void) * handled by PLTRST separately. */ for (chan = NPCX_ESPI_CH_VW; chan < NPCX_ESPI_CH_COUNT; - chan++) { + chan++) { if (!IS_PERIPHERAL_CHAN_ENABLE(chan) && - IS_HOST_CHAN_EN(chan)) + IS_HOST_CHAN_EN(chan)) ENABLE_ESPI_CHAN(chan); else if (IS_PERIPHERAL_CHAN_ENABLE(chan) && - !IS_HOST_CHAN_EN(chan)) + !IS_HOST_CHAN_EN(chan)) DISABLE_ESPI_CHAN(chan); } @@ -625,9 +623,8 @@ static void espi_interrupt(void) */ if (boot_load_done == 0 && IS_PERIPHERAL_CHAN_ENABLE(NPCX_ESPI_CH_VW)) { - - espi_vw_set_wire( - VW_PERIPHERAL_BTLD_STATUS_DONE, 1); + espi_vw_set_wire(VW_PERIPHERAL_BTLD_STATUS_DONE, + 1); boot_load_done = 1; } } @@ -662,7 +659,7 @@ void espi_init(void) /* Support all I/O modes */ SET_FIELD(NPCX_ESPICFG, NPCX_ESPICFG_IOMODE_FIELD, - NPCX_ESPI_IO_MODE_ALL); + NPCX_ESPI_IO_MODE_ALL); /* Set eSPI speed to max supported */ SET_FIELD(NPCX_ESPICFG, NPCX_ESPICFG_MAXFREQ_FIELD, @@ -681,14 +678,14 @@ void espi_init(void) espi_enable_vw_int(&espi_vw_int_list[i]); } -static int command_espi(int argc, char **argv) +static int command_espi(int argc, const char **argv) { uint32_t chan; char *e; if (argc == 1) { return EC_ERROR_INVAL; - /* Get value of eSPI registers */ + /* Get value of eSPI registers */ } else if (argc == 2) { int i; @@ -697,23 +694,23 @@ static int command_espi(int argc, char **argv) } else if (strcasecmp(argv[1], "vsm") == 0) { for (i = 0; i < ESPI_VWEVSM_NUM; i++) { uint32_t val = NPCX_VWEVSM(i); - uint8_t idx = VWEVSM_IDX_GET(val); + uint8_t idx = VWEVSM_IDX_GET(val); ccprintf("VWEVSM%d: %02x [0x%08x]\n", i, idx, - val); + val); } } else if (strcasecmp(argv[1], "vms") == 0) { for (i = 0; i < ESPI_VWEVMS_NUM; i++) { uint32_t val = NPCX_VWEVMS(i); - uint8_t idx = VWEVMS_IDX_GET(val); + uint8_t idx = VWEVMS_IDX_GET(val); ccprintf("VWEVMS%d: %02x [0x%08x]\n", i, idx, - val); + val); } } - /* Enable/Disable the channels of eSPI */ + /* Enable/Disable the channels of eSPI */ } else if (argc == 3) { - uint32_t m = (uint32_t) strtoi(argv[2], &e, 0); + uint32_t m = (uint32_t)strtoi(argv[2], &e, 0); if (*e) return EC_ERROR_PARAM2; @@ -733,6 +730,5 @@ static int command_espi(int argc, char **argv) } return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(espi, command_espi, - "cfg/vms/vsm/en/dis [channel]", +DECLARE_CONSOLE_COMMAND(espi, command_espi, "cfg/vms/vsm/en/dis [channel]", "eSPI configurations"); diff --git a/chip/npcx/fan.c b/chip/npcx/fan.c index 5b56f33edf..6a246f5c6a 100644 --- a/chip/npcx/fan.c +++ b/chip/npcx/fan.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -25,7 +25,7 @@ #if !(DEBUG_FAN) #define CPRINTS(...) #else -#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_PWM, format, ##args) #endif /* Tacho measurement state */ @@ -92,7 +92,7 @@ static int rpm_pre[FAN_CH_COUNT]; #define TACHO_MAX_CNT (BIT(16) - 1) /* Margin of target rpm */ -#define RPM_MARGIN(rpm_target) (((rpm_target) * RPM_DEVIATION) / 100) +#define RPM_MARGIN(rpm_target) (((rpm_target)*RPM_DEVIATION) / 100) /** * MFT get fan rpm value @@ -144,7 +144,7 @@ static int mft_fan_rpm(int ch) /** * Set fan prescaler based on apb1 clock * - * @param none + * @param ch operation channel * @return none * @notes changed when initial or HOOK_FREQ_CHANGE command */ @@ -154,14 +154,14 @@ void mft_set_apb1_prescaler(int ch) uint16_t prescaler_divider = 0; /* Set clock prescaler divider to MFT module*/ - prescaler_divider = (uint16_t)(clock_get_apb1_freq() - / fan_status[ch].mft_freq); + prescaler_divider = + (uint16_t)(clock_get_apb1_freq() / fan_status[ch].mft_freq); if (prescaler_divider >= 1) prescaler_divider = prescaler_divider - 1; if (prescaler_divider > 0xFF) prescaler_divider = 0xFF; - NPCX_TPRSC(mdl) = (uint8_t) prescaler_divider; + NPCX_TPRSC(mdl) = (uint8_t)prescaler_divider; } /** @@ -184,7 +184,6 @@ static void fan_config(int ch, int enable_mft_read_rpm) /* Need to initialize MFT or not */ if (enable_mft_read_rpm) { - /* Initialize tacho sampling rate */ if (clk_src == TCKC_LFCLK) p_status->mft_freq = INT_32K_CLOCK; @@ -195,7 +194,7 @@ static void fan_config(int ch, int enable_mft_read_rpm) /* Set mode 5 to MFT module */ SET_FIELD(NPCX_TMCTRL(mdl), NPCX_TMCTRL_MDSEL_FIELD, - NPCX_MFT_MDSEL_5); + NPCX_MFT_MDSEL_5); /* Set MFT operation frequency */ if (clk_src == TCKC_PRESCALE_APB1_CLK) @@ -203,11 +202,11 @@ static void fan_config(int ch, int enable_mft_read_rpm) /* Set the low power mode or not. */ UPDATE_BIT(NPCX_TCKC(mdl), NPCX_TCKC_LOW_PWR, - clk_src == TCKC_LFCLK); + clk_src == TCKC_LFCLK); /* Set the default count-down timer. */ NPCX_TCNT1(mdl) = TACHO_MAX_CNT; - NPCX_TCRA(mdl) = TACHO_MAX_CNT; + NPCX_TCRA(mdl) = TACHO_MAX_CNT; /* Set the edge polarity to rising. */ SET_BIT(NPCX_TMCTRL(mdl), NPCX_TMCTRL_TAEDG); @@ -300,7 +299,8 @@ enum fan_status fan_smart_control(int ch, int rpm_actual, int rpm_target) * In this case, don't step the PWM duty too aggressively. * See b:225208265 for more detail. */ - if (rpm_pre[ch] == 0 && rpm_actual == 0) { + if (rpm_pre[ch] == 0 && rpm_actual == 0 && + IS_ENABLED(CONFIG_FAN_BYPASS_SLOW_RESPONSE)) { rpm_diff = RPM_MARGIN(rpm_target) + 1; } else { rpm_diff = rpm_target - rpm_actual; @@ -319,7 +319,7 @@ enum fan_status fan_smart_control(int ch, int rpm_actual, int rpm_target) fan_adjust_duty(ch, rpm_diff, duty); return FAN_STATUS_CHANGING; - /* Decrease PWM duty */ + /* Decrease PWM duty */ } else if (rpm_diff < -RPM_MARGIN(rpm_target)) { if (duty == 1 && rpm_target != 0) return FAN_STATUS_FRUSTRATED; @@ -340,11 +340,12 @@ void fan_tick_func(void) { int ch; - for (ch = 0; ch < FAN_CH_COUNT ; ch++) { + for (ch = 0; ch < FAN_CH_COUNT; ch++) { volatile struct fan_status_t *p_status = fan_status + ch; /* Make sure rpm mode is enabled */ if (p_status->fan_mode != TACHO_FAN_RPM) { - /* Fan in duty mode still want rpm_actual being updated. */ + /* Fan in duty mode still want rpm_actual being updated. + */ p_status->rpm_actual = mft_fan_rpm(ch); if (p_status->rpm_actual > 0) p_status->auto_status = FAN_STATUS_LOCKED; @@ -357,8 +358,8 @@ void fan_tick_func(void) /* Get actual rpm */ p_status->rpm_actual = mft_fan_rpm(ch); /* Do smart fan stuff */ - p_status->auto_status = fan_smart_control(ch, - p_status->rpm_actual, p_status->rpm_target); + p_status->auto_status = fan_smart_control( + ch, p_status->rpm_actual, p_status->rpm_target); } } DECLARE_HOOK(HOOK_TICK, fan_tick_func, HOOK_PRIO_DEFAULT); @@ -530,7 +531,7 @@ enum fan_status fan_get_status(int ch) int fan_is_stalled(int ch) { return fan_get_enabled(ch) && fan_get_duty(ch) && - fan_status[ch].cur_state == TACHO_UNDERFLOW; + fan_status[ch].cur_state == TACHO_UNDERFLOW; } /** diff --git a/chip/npcx/fan_chip.h b/chip/npcx/fan_chip.h index 6fc228ec84..36eb13f4cb 100644 --- a/chip/npcx/fan_chip.h +++ b/chip/npcx/fan_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/npcx/flash.c b/chip/npcx/flash.c index 768c2ced29..390cb1fa64 100644 --- a/chip/npcx/flash.c +++ b/chip/npcx/flash.c @@ -1,10 +1,11 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Flash memory module for Chrome EC */ +#include "builtin/assert.h" #include "flash.h" #include "host_command.h" #include "registers.h" @@ -68,7 +69,7 @@ static void flash_execute_cmd(uint8_t code, uint8_t cts) /* set UMA_CODE */ NPCX_UMA_CODE = code; /* execute UMA flash transaction */ - NPCX_UMA_CTS = cts; + NPCX_UMA_CTS = cts; while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE)) ; } @@ -94,7 +95,7 @@ static int flash_wait_ready(void) flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_ONLY); do { /* Read status register */ - NPCX_UMA_CTS = MASK_RD_1BYTE; + NPCX_UMA_CTS = MASK_RD_1BYTE; while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE)) ; /* Busy bit is clear */ @@ -316,8 +317,8 @@ static int flash_set_status_for_prot(int reg1, int reg2) #endif flash_set_status(reg1, reg2); - spi_flash_reg_to_protect(reg1, reg2, - &addr_prot_start, &addr_prot_length); + spi_flash_reg_to_protect(reg1, reg2, &addr_prot_start, + &addr_prot_length); return EC_SUCCESS; } @@ -328,8 +329,8 @@ static int flash_check_prot_range(unsigned int offset, unsigned int bytes) if (offset + bytes > CONFIG_FLASH_SIZE_BYTES) return EC_ERROR_INVAL; /* Check if ranges overlap */ - if (MAX(addr_prot_start, offset) < MIN(addr_prot_start + - addr_prot_length, offset + bytes)) + if (MAX(addr_prot_start, offset) < + MIN(addr_prot_start + addr_prot_length, offset + bytes)) return EC_ERROR_ACCESS_DENIED; return EC_SUCCESS; @@ -369,7 +370,6 @@ static int flash_check_prot_reg(unsigned int offset, unsigned int bytes) return EC_ERROR_ACCESS_DENIED; return EC_SUCCESS; - } static int flash_write_prot_reg(unsigned int offset, unsigned int bytes, @@ -395,7 +395,7 @@ static int flash_write_prot_reg(unsigned int offset, unsigned int bytes, } static void flash_burst_write(unsigned int dest_addr, unsigned int bytes, - const char *data) + const char *data) { unsigned int i; /* Chip Select down */ @@ -413,15 +413,17 @@ static void flash_burst_write(unsigned int dest_addr, unsigned int bytes, } static int flash_program_bytes(uint32_t offset, uint32_t bytes, - const uint8_t *data) + const uint8_t *data) { int write_size; int rv; while (bytes > 0) { /* Write length can not go beyond the end of the flash page */ - write_size = MIN(bytes, CONFIG_FLASH_WRITE_IDEAL_SIZE - - (offset & (CONFIG_FLASH_WRITE_IDEAL_SIZE - 1))); + write_size = MIN(bytes, + CONFIG_FLASH_WRITE_IDEAL_SIZE - + (offset & + (CONFIG_FLASH_WRITE_IDEAL_SIZE - 1))); /* Enable write */ rv = flash_write_enable(); @@ -436,9 +438,9 @@ static int flash_program_bytes(uint32_t offset, uint32_t bytes, if (rv) return rv; - data += write_size; + data += write_size; offset += write_size; - bytes -= write_size; + bytes -= write_size; } return rv; @@ -467,7 +469,7 @@ int crec_flash_physical_read(int offset, int size, char *data) /* Burst read transaction */ for (idx = 0; idx < size; idx++) { /* 1101 0101 - EXEC, RD, NO CMD, NO ADDR, 4 bytes */ - NPCX_UMA_CTS = MASK_RD_1BYTE; + NPCX_UMA_CTS = MASK_RD_1BYTE; /* wait for UMA to complete */ while (IS_BIT_SET(NPCX_UMA_CTS, EXEC_DONE)) ; @@ -493,8 +495,8 @@ int crec_flash_physical_write(int offset, int size, const char *data) int rv; /* Fail if offset, size, and data aren't at least word-aligned */ - if ((offset | size - | (uint32_t)(uintptr_t)data) & (CONFIG_FLASH_WRITE_SIZE - 1)) + if ((offset | size | (uint32_t)(uintptr_t)data) & + (CONFIG_FLASH_WRITE_SIZE - 1)) return EC_ERROR_INVAL; /* check protection */ @@ -510,7 +512,8 @@ int crec_flash_physical_write(int offset, int size, const char *data) while (size > 0) { /* First write multiples of 256, then (size % 256) last */ write_len = ((size % CONFIG_FLASH_WRITE_IDEAL_SIZE) == size) ? - size : CONFIG_FLASH_WRITE_IDEAL_SIZE; + size : + CONFIG_FLASH_WRITE_IDEAL_SIZE; /* check protection */ if (flash_check_prot_range(dest_addr, write_len)) { @@ -522,9 +525,9 @@ int crec_flash_physical_write(int offset, int size, const char *data) if (rv) break; - data += write_len; + data += write_len; dest_addr += write_len; - size -= write_len; + size -= write_len; } /* Enable tri-state */ @@ -551,7 +554,7 @@ int crec_flash_physical_erase(int offset, int size) /* Alignment has been checked in upper layer */ for (; size > 0; size -= CONFIG_FLASH_ERASE_SIZE, - offset += CONFIG_FLASH_ERASE_SIZE) { + offset += CONFIG_FLASH_ERASE_SIZE) { /* check protection */ if (flash_check_prot_range(offset, CONFIG_FLASH_ERASE_SIZE)) { rv = EC_ERROR_ACCESS_DENIED; @@ -645,7 +648,6 @@ int crec_flash_physical_protect_now(int all) return EC_SUCCESS; } - int crec_flash_physical_protect_at_boot(uint32_t new_flags) { int ret; @@ -657,8 +659,7 @@ int crec_flash_physical_protect_at_boot(uint32_t new_flags) } ret = flash_write_prot_reg(CONFIG_WP_STORAGE_OFF, - CONFIG_WP_STORAGE_SIZE, - 1); + CONFIG_WP_STORAGE_SIZE, 1); /* * Set UMA_LOCK bit for locking all UMA transaction. @@ -672,9 +673,8 @@ int crec_flash_physical_protect_at_boot(uint32_t new_flags) uint32_t crec_flash_physical_get_valid_flags(void) { - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | - EC_FLASH_PROTECT_ALL_NOW; + return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW | + EC_FLASH_PROTECT_ALL_NOW; } uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags) @@ -690,7 +690,7 @@ uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags) * the WP GPIO is asserted. */ if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) && - (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED)) + (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED)) ret |= EC_FLASH_PROTECT_ALL_NOW; return ret; @@ -759,8 +759,7 @@ static enum ec_status flash_command_spi_info(struct host_cmd_handler_args *args) args->response_size = sizeof(*r); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_FLASH_SPI_INFO, - flash_command_spi_info, +DECLARE_HOST_COMMAND(EC_CMD_FLASH_SPI_INFO, flash_command_spi_info, EC_VER_MASK(0)); #endif @@ -788,7 +787,7 @@ static int flash_spi_sel_lock(int enable) /*****************************************************************************/ /* Console commands */ -static int command_flash_spi_sel_lock(int argc, char **argv) +static int command_flash_spi_sel_lock(int argc, const char **argv) { int ena; @@ -801,10 +800,9 @@ static int command_flash_spi_sel_lock(int argc, char **argv) return EC_SUCCESS; } DECLARE_CONSOLE_COMMAND(flash_spi_lock, command_flash_spi_sel_lock, - "[on | off]", - "Lock spi flash interface selection"); + "[on | off]", "Lock spi flash interface selection"); -static int command_flash_tristate(int argc, char **argv) +static int command_flash_tristate(int argc, const char **argv) { int ena; @@ -817,12 +815,11 @@ static int command_flash_tristate(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(flash_tristate, command_flash_tristate, - "[on | off]", +DECLARE_CONSOLE_COMMAND(flash_tristate, command_flash_tristate, "[on | off]", "Tristate spi flash pins"); #endif /* CONFIG_CMD_FLASH_TRISTATE */ -static int command_flash_chip(int argc, char **argv) +static int command_flash_chip(int argc, const char **argv) { uint8_t jedec_id[3]; uint8_t sr1, sr2; @@ -832,10 +829,9 @@ static int command_flash_chip(int argc, char **argv) flash_get_jedec_id(jedec_id); ccprintf("Manufacturer: 0x%02x, DID: 0x%02x%02x\n", jedec_id[0], - jedec_id[1], jedec_id[2]); + jedec_id[1], jedec_id[2]); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(flashchip, command_flash_chip, - NULL, +DECLARE_CONSOLE_COMMAND(flashchip, command_flash_chip, NULL, "Print flash chip info"); diff --git a/chip/npcx/gpio-npcx5.c b/chip/npcx/gpio-npcx5.c index 6742f19369..2201bb65c2 100644 --- a/chip/npcx/gpio-npcx5.c +++ b/chip/npcx/gpio-npcx5.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -48,11 +48,11 @@ DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); * the port, then call the master handler above. */ -#define GPIO_IRQ_FUNC(_irq_func, wui_int) \ -static void _irq_func(void) \ -{ \ - gpio_interrupt(wui_int); \ -} +#define GPIO_IRQ_FUNC(_irq_func, wui_int) \ + static void _irq_func(void) \ + { \ + gpio_interrupt(wui_int); \ + } /* If we need to handle the other type interrupts except GPIO, add code here */ static void __gpio_wk0efgh_interrupt(void) @@ -60,7 +60,7 @@ static void __gpio_wk0efgh_interrupt(void) if (IS_ENABLED(CONFIG_HOSTCMD_X86)) { /* Pending bit 7 or 6 or 5? */ if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6) && - IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) { + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) { /* Disable host wake-up */ CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6); /* Clear pending bit of WUI */ @@ -68,16 +68,18 @@ static void __gpio_wk0efgh_interrupt(void) return; } if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) { - if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 5) - && - IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 5)) { + if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), + 5) && + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), + 5)) { espi_espirst_handler(); return; } } else { - if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 7) - && - IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 7)) { + if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), + 7) && + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), + 7)) { lpc_lreset_pltrst_handler(); return; } @@ -169,30 +171,30 @@ GPIO_IRQ_FUNC(__gpio_wk2fg_interrupt, WUI_INT(MIWU_TABLE_2, MIWU_GROUP_6)); #endif DECLARE_IRQ(NPCX_IRQ_MTC_WKINTAD_0, __gpio_rtc_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0, __gpio_wk0b_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTC_0, __gpio_wk0c_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTEFGH_0, __gpio_wk0efgh_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTA_1, __gpio_wk1a_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTB_1, __gpio_wk1b_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0, __gpio_wk0b_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTC_0, __gpio_wk0c_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTEFGH_0, __gpio_wk0efgh_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTA_1, __gpio_wk1a_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTB_1, __gpio_wk1b_interrupt, 3); #ifdef NPCX_SELECT_KSI_TO_GPIO -DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3); #endif -DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3); #ifdef CONFIG_HOST_INTERFACE_SHI /* * HACK: Make CS GPIO P2 to improve SHI reliability. * TODO: Increase CS-assertion-to-transaction-start delay on host to * accommodate P3 CS interrupt. */ -DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 2); +DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 2); #else -DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 3); #endif -DECLARE_IRQ(NPCX_IRQ_WKINTG_1, __gpio_wk1g_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTH_1, __gpio_wk1h_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTG_1, __gpio_wk1g_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTH_1, __gpio_wk1h_interrupt, 3); #if defined(CHIP_FAMILY_NPCX7) -DECLARE_IRQ(NPCX_IRQ_WKINTFG_2, __gpio_wk2fg_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTFG_2, __gpio_wk2fg_interrupt, 3); #endif #undef GPIO_IRQ_FUNC diff --git a/chip/npcx/gpio-npcx7.c b/chip/npcx/gpio-npcx7.c index 39b939f44c..2201bb65c2 120000..100644 --- a/chip/npcx/gpio-npcx7.c +++ b/chip/npcx/gpio-npcx7.c @@ -1 +1,200 @@ -gpio-npcx5.c
\ No newline at end of file +/* Copyright 2020 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* GPIO module for Chrome EC */ + +#include "clock.h" +#include "common.h" +#include "ec_commands.h" +#include "gpio_chip.h" +#include "hooks.h" +#include "host_command.h" +#include "lpc_chip.h" +#include "registers.h" +#include "task.h" + +/* + * List of GPIO IRQs to enable. Don't automatically enable interrupts for + * the keyboard input GPIO bank - that's handled separately. Of course the + * bank is different for different systems. + */ +static void gpio_init(void) +{ + /* Enable IRQs now that pins are set up */ + task_enable_irq(NPCX_IRQ_MTC_WKINTAD_0); + task_enable_irq(NPCX_IRQ_WKINTEFGH_0); + task_enable_irq(NPCX_IRQ_WKINTC_0); + task_enable_irq(NPCX_IRQ_TWD_WKINTB_0); + task_enable_irq(NPCX_IRQ_WKINTA_1); + task_enable_irq(NPCX_IRQ_WKINTB_1); +#ifdef NPCX_SELECT_KSI_TO_GPIO + task_enable_irq(NPCX_IRQ_KSI_WKINTC_1); +#endif + task_enable_irq(NPCX_IRQ_WKINTD_1); + task_enable_irq(NPCX_IRQ_WKINTE_1); + task_enable_irq(NPCX_IRQ_WKINTF_1); + task_enable_irq(NPCX_IRQ_WKINTG_1); + task_enable_irq(NPCX_IRQ_WKINTH_1); +#if defined(CHIP_FAMILY_NPCX7) + task_enable_irq(NPCX_IRQ_WKINTFG_2); +#endif +} +DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); + +/** + * Handlers for each GPIO port. These read and clear the interrupt bits for + * the port, then call the master handler above. + */ + +#define GPIO_IRQ_FUNC(_irq_func, wui_int) \ + static void _irq_func(void) \ + { \ + gpio_interrupt(wui_int); \ + } + +/* If we need to handle the other type interrupts except GPIO, add code here */ +static void __gpio_wk0efgh_interrupt(void) +{ + if (IS_ENABLED(CONFIG_HOSTCMD_X86)) { + /* Pending bit 7 or 6 or 5? */ + if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6) && + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) { + /* Disable host wake-up */ + CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6); + /* Clear pending bit of WUI */ + SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 6); + return; + } + if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) { + if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), + 5) && + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), + 5)) { + espi_espirst_handler(); + return; + } + } else { + if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), + 7) && + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), + 7)) { + lpc_lreset_pltrst_handler(); + return; + } + } + } + gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_5)); + gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_6)); + gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_7)); + gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_8)); +} + +#ifdef CONFIG_HOSTCMD_RTC +static void set_rtc_host_event(void) +{ + host_set_single_event(EC_HOST_EVENT_RTC); +} +DECLARE_DEFERRED(set_rtc_host_event); +#endif + +static void __gpio_rtc_interrupt(void) +{ + /* Check pending bit 7 */ +#ifdef CONFIG_HOSTCMD_RTC + if (NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_4) & 0x80) { + /* Clear pending bit for WUI */ + SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_4), 7); + hook_call_deferred(&set_rtc_host_event_data, 0); + return; + } +#endif +#if defined(CHIP_FAMILY_NPCX7) && defined(CONFIG_LOW_POWER_IDLE) && \ + (CONFIG_CONSOLE_UART == 1) + /* Handle the interrupt from UART wakeup event */ + if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_1), 6) && + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_1), 6)) { + /* + * Disable WKEN bit to avoid the other unnecessary interrupts + * from the coming data bits after the start bit. (Pending bit + * of CR_SIN is set when a high-to-low transaction occurs.) + */ + CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_1), 6); + /* Clear pending bit for WUI */ + SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_1), 6); + /* Notify the clock module that the console is in use. */ + clock_refresh_console_in_use(); + return; + } +#endif + gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_1)); + gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_4)); +} + +static void __gpio_wk1h_interrupt(void) +{ +#if defined(CHIP_FAMILY_NPCX7) && defined(CONFIG_LOW_POWER_IDLE) && \ + (CONFIG_CONSOLE_UART == 0) + /* Handle the interrupt from UART wakeup event */ + if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_1, MIWU_GROUP_8), 7) && + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_1, MIWU_GROUP_8), 7)) { + /* + * Disable WKEN bit to avoid the other unnecessary interrupts + * from the coming data bits after the start bit. (Pending bit + * of CR_SIN is set when a high-to-low transaction occurs.) + */ + CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_1, MIWU_GROUP_8), 7); + /* Clear pending bit for WUI */ + SET_BIT(NPCX_WKPCL(MIWU_TABLE_1, MIWU_GROUP_8), 7); + /* Notify the clock module that the console is in use. */ + clock_refresh_console_in_use(); + } else +#endif + gpio_interrupt(WUI_INT(MIWU_TABLE_1, MIWU_GROUP_8)); +} + +GPIO_IRQ_FUNC(__gpio_wk0b_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_2)); +GPIO_IRQ_FUNC(__gpio_wk0c_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_3)); +GPIO_IRQ_FUNC(__gpio_wk1a_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_1)); +GPIO_IRQ_FUNC(__gpio_wk1b_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_2)); +#ifdef NPCX_SELECT_KSI_TO_GPIO +/* Declare GPIO irq functions for KSI pins if there's no keyboard scan task, */ +GPIO_IRQ_FUNC(__gpio_wk1c_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_3)); +#endif +GPIO_IRQ_FUNC(__gpio_wk1d_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_4)); +GPIO_IRQ_FUNC(__gpio_wk1e_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_5)); +GPIO_IRQ_FUNC(__gpio_wk1f_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_6)); +GPIO_IRQ_FUNC(__gpio_wk1g_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_7)); +#if defined(CHIP_FAMILY_NPCX7) +GPIO_IRQ_FUNC(__gpio_wk2fg_interrupt, WUI_INT(MIWU_TABLE_2, MIWU_GROUP_6)); +#endif + +DECLARE_IRQ(NPCX_IRQ_MTC_WKINTAD_0, __gpio_rtc_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0, __gpio_wk0b_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTC_0, __gpio_wk0c_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTEFGH_0, __gpio_wk0efgh_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTA_1, __gpio_wk1a_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTB_1, __gpio_wk1b_interrupt, 3); +#ifdef NPCX_SELECT_KSI_TO_GPIO +DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3); +#endif +DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3); +#ifdef CONFIG_HOST_INTERFACE_SHI +/* + * HACK: Make CS GPIO P2 to improve SHI reliability. + * TODO: Increase CS-assertion-to-transaction-start delay on host to + * accommodate P3 CS interrupt. + */ +DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 2); +#else +DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 3); +#endif +DECLARE_IRQ(NPCX_IRQ_WKINTG_1, __gpio_wk1g_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTH_1, __gpio_wk1h_interrupt, 3); +#if defined(CHIP_FAMILY_NPCX7) +DECLARE_IRQ(NPCX_IRQ_WKINTFG_2, __gpio_wk2fg_interrupt, 3); +#endif + +#undef GPIO_IRQ_FUNC diff --git a/chip/npcx/gpio-npcx9.c b/chip/npcx/gpio-npcx9.c index b567f1d1c8..5de8ea3b0a 100644 --- a/chip/npcx/gpio-npcx9.c +++ b/chip/npcx/gpio-npcx9.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -51,11 +51,11 @@ DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); * the port, then call the master handler above. */ -#define GPIO_IRQ_FUNC(_irq_func, wui_int) \ -static void _irq_func(void) \ -{ \ - gpio_interrupt(wui_int); \ -} +#define GPIO_IRQ_FUNC(_irq_func, wui_int) \ + static void _irq_func(void) \ + { \ + gpio_interrupt(wui_int); \ + } /* If we need to handle the other type interrupts except GPIO, add code here */ static void __gpio_host_interrupt(void) @@ -63,7 +63,7 @@ static void __gpio_host_interrupt(void) if (IS_ENABLED(CONFIG_HOSTCMD_X86)) { /* Pending bit 7 or 6 or 5? */ if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6) && - IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) { + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) { /* Disable host wake-up */ CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6); /* Clear pending bit of WUI */ @@ -71,16 +71,18 @@ static void __gpio_host_interrupt(void) return; } if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) { - if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 5) - && - IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 5)) { + if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), + 5) && + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), + 5)) { espi_espirst_handler(); return; } } else { - if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 7) - && - IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 7)) { + if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), + 7) && + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), + 7)) { lpc_lreset_pltrst_handler(); return; } @@ -130,7 +132,6 @@ static void __gpio_cr_sin2_interrupt(void) } #endif gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_1)); - } static void __gpio_wk1h_interrupt(void) @@ -181,32 +182,32 @@ GPIO_IRQ_FUNC(__gpio_wk1f_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_6)); GPIO_IRQ_FUNC(__gpio_wk1g_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_7)); DECLARE_IRQ(NPCX_IRQ_CR_SIN2_WKINTA_0, __gpio_cr_sin2_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0, __gpio_wk0b_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTC_0, __gpio_wk0c_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_MTC_WKINTD_0, __gpio_rtc_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTE_0, __gpio_host_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTF_0, __gpio_wk0f_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTG_0, __gpio_wk0g_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTH_0, __gpio_wk0h_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTA_1, __gpio_wk1a_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTB_1, __gpio_wk1b_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0, __gpio_wk0b_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTC_0, __gpio_wk0c_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_MTC_WKINTD_0, __gpio_rtc_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTE_0, __gpio_host_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTF_0, __gpio_wk0f_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTG_0, __gpio_wk0g_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTH_0, __gpio_wk0h_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTA_1, __gpio_wk1a_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTB_1, __gpio_wk1b_interrupt, 3); #ifdef NPCX_SELECT_KSI_TO_GPIO -DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3); #endif -DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3); #ifdef CONFIG_HOST_INTERFACE_SHI /* * HACK: Make CS GPIO P2 to improve SHI reliability. * TODO: Increase CS-assertion-to-transaction-start delay on host to * accommodate P3 CS interrupt. */ -DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 2); +DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 2); #else -DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 3); #endif -DECLARE_IRQ(NPCX_IRQ_WKINTG_1, __gpio_wk1g_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTH_1, __gpio_wk1h_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_LCT_WKINTF_2, __gpio_lct_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTG_1, __gpio_wk1g_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTH_1, __gpio_wk1h_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_LCT_WKINTF_2, __gpio_lct_interrupt, 3); #undef GPIO_IRQ_FUNC diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c index 5f1e3c78b6..690615729d 100644 --- a/chip/npcx/gpio.c +++ b/chip/npcx/gpio.c @@ -1,10 +1,11 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* GPIO module for Chrome EC */ +#include "builtin/assert.h" #include "common.h" #include "gpio.h" #include "gpio_chip.h" @@ -25,7 +26,7 @@ #define CPRINTS(...) #else #define CPUTS(outstr) cputs(CC_GPIO, outstr) -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) +#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args) #endif /* Constants for GPIO interrupt mapping */ @@ -40,12 +41,12 @@ #define UNIMPLEMENTED(name) #endif static const struct npcx_wui gpio_wui_table[] = { - #include "gpio.wrap" +#include "gpio.wrap" }; struct npcx_gpio { - uint8_t port : 4; - uint8_t bit : 3; + uint8_t port : 4; + uint8_t bit : 3; uint8_t valid : 1; }; @@ -54,21 +55,21 @@ BUILD_ASSERT(sizeof(struct npcx_gpio) == 1); #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9 struct npcx_alt { uint8_t group; - uint8_t bit : 3; - uint8_t inverted : 1; - uint8_t reserved : 4; + uint8_t bit : 3; + uint8_t inverted : 1; + uint8_t reserved : 4; }; #else struct npcx_alt { - uint8_t group : 4; - uint8_t bit : 3; - uint8_t inverted : 1; + uint8_t group : 4; + uint8_t bit : 3; + uint8_t inverted : 1; }; #endif struct gpio_alt_map { struct npcx_gpio gpio; - struct npcx_alt alt; + struct npcx_alt alt; }; #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9 @@ -101,8 +102,7 @@ static uint8_t gpio_is_alt_sel(uint8_t port, uint8_t bit) struct gpio_alt_map const *map; uint8_t alt_mask, devalt; - for (map = ARRAY_BEGIN(gpio_alt_table); - map < ARRAY_END(gpio_alt_table); + for (map = ARRAY_BEGIN(gpio_alt_table); map < ARRAY_END(gpio_alt_table); map++) { if (gpio_match(port, bit, map->gpio)) { alt_mask = 1 << map->alt.bit; @@ -127,8 +127,7 @@ static int gpio_alt_sel(uint8_t port, uint8_t bit, { struct gpio_alt_map const *map; - for (map = ARRAY_BEGIN(gpio_alt_table); - map < ARRAY_END(gpio_alt_table); + for (map = ARRAY_BEGIN(gpio_alt_table); map < ARRAY_END(gpio_alt_table); map++) { if (gpio_match(port, bit, map->gpio)) { uint8_t alt_mask = 1 << map->alt.bit; @@ -140,7 +139,7 @@ static int gpio_alt_sel(uint8_t port, uint8_t bit, if ((func < GPIO_ALT_FUNC_DEFAULT) ^ map->alt.inverted) NPCX_DEVALT(map->alt.group) &= ~alt_mask; else - NPCX_DEVALT(map->alt.group) |= alt_mask; + NPCX_DEVALT(map->alt.group) |= alt_mask; return 1; } @@ -183,7 +182,7 @@ static void gpio_interrupt_type_sel(enum gpio_signal signal, uint32_t flags) NPCX_WKMOD(table, group) &= ~pmask; /* Handle interrupting on both edges */ if ((flags & GPIO_INT_F_RISING) && - (flags & GPIO_INT_F_FALLING)) { + (flags & GPIO_INT_F_FALLING)) { /* Enable any edge */ NPCX_WKAEDG(table, group) |= pmask; } @@ -252,7 +251,7 @@ void gpio_low_voltage_level_sel(uint8_t port, uint8_t bit, uint8_t low_voltage) if (low_voltage) CPRINTS("Warn! No low voltage support in port:0x%x, bit:%d", - port, bit); + port, bit); } /* Set the low voltage detection level by mask */ @@ -290,7 +289,7 @@ static void gpio_enable_wake_up_input(enum gpio_signal signal, int enable) SET_BIT(NPCX_WKINEN(wui->table, wui->group), wui->bit); else CLEAR_BIT(NPCX_WKINEN(wui->table, wui->group), - wui->bit); + wui->bit); } } @@ -317,7 +316,7 @@ BUILD_ASSERT(ARRAY_SIZE(gpio_lvol_table[0].lvol_gpio) == 8); /* IC specific low-level driver */ void gpio_set_alternate_function(uint32_t port, uint32_t mask, - enum gpio_alternate_func func) + enum gpio_alternate_func func) { /* Enable alternative pins by func */ int pin; @@ -340,7 +339,7 @@ void gpio_set_level(enum gpio_signal signal, int value) ASSERT(signal_is_gpio(signal)); if (value) - NPCX_PDOUT(gpio_list[signal].port) |= gpio_list[signal].mask; + NPCX_PDOUT(gpio_list[signal].port) |= gpio_list[signal].mask; else NPCX_PDOUT(gpio_list[signal].port) &= ~gpio_list[signal].mask; } @@ -410,14 +409,14 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) if (flags & GPIO_PULL_UP) { if (flags & GPIO_SEL_1P8V) { CPRINTS("Warn! enable internal PU and low voltage mode" - " at the same time is illegal. port 0x%x, mask 0x%x", - port, mask); + " at the same time is illegal. port 0x%x, mask 0x%x", + port, mask); } else { - NPCX_PPUD(port) &= ~mask; + NPCX_PPUD(port) &= ~mask; NPCX_PPULL(port) |= mask; /* enable pull down/up */ } } else if (flags & GPIO_PULL_DOWN) { - NPCX_PPUD(port) |= mask; + NPCX_PPUD(port) |= mask; NPCX_PPULL(port) |= mask; /* enable pull down/up */ } else { /* No pull up/down */ @@ -455,7 +454,7 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) if (flags & GPIO_OUTPUT) NPCX_PDIR(port) |= mask; - /* Lock GPIO output and configuration if need */ + /* Lock GPIO output and configuration if need */ #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7 if (flags & GPIO_LOCKED) NPCX_PLOCK_CTL(port) |= mask; @@ -598,7 +597,7 @@ void gpio_pre_init(void) * which may or may not be as a GPIO. */ gpio_set_alternate_function(g->port, g->mask, - GPIO_ALT_FUNC_NONE); + GPIO_ALT_FUNC_NONE); } /* The bypass of low voltage IOs for better power consumption */ @@ -649,8 +648,8 @@ void gpio_interrupt(struct npcx_wui wui_int) uint8_t pin_mask = 1 << gpio_wui_table[i].bit; if ((gpio_wui_table[i].table == table) && - (gpio_wui_table[i].group == group) && - (wui_mask & pin_mask)) { + (gpio_wui_table[i].group == group) && + (wui_mask & pin_mask)) { /* Clear pending bit of GPIO */ NPCX_WKPCL(table, group) = pin_mask; /* Execute GPIO's ISR */ @@ -671,7 +670,7 @@ void gpio_interrupt(struct npcx_wui wui_int) * Command used to disable input buffer of gpios one by one to * investigate power consumption */ -static int command_gpiodisable(int argc, char **argv) +static int command_gpiodisable(int argc, const char **argv) { uint8_t i; uint8_t offset; @@ -691,7 +690,7 @@ static int command_gpiodisable(int argc, char **argv) ccprintf("Total GPIO declaration: %d\n", GPIO_COUNT); ccprintf("Total Non-ISR GPIO declaration: %d\n", - non_isr_gpio_num); + non_isr_gpio_num); ccprintf("Next GPIO Num to check by "); ccprintf("\"gpiodisable next\"\n"); ccprintf(" offset: %d\n", offset); @@ -714,8 +713,8 @@ static int command_gpiodisable(int argc, char **argv) offset = idx + GPIO_IH_COUNT; g_list = gpio_list + offset; flags = g_list->flags; - ccprintf("current GPIO : %d %s --> ", - offset, g_list->name); + ccprintf("current GPIO : %d %s --> ", offset, + g_list->name); if (gpio_is_i2c_pin(offset)) { ccprintf("Ignore I2C pin!\n"); idx++; @@ -726,10 +725,10 @@ static int command_gpiodisable(int argc, char **argv) continue; } else { if ((flags & GPIO_INPUT) || - (flags & GPIO_OPEN_DRAIN)) { + (flags & GPIO_OPEN_DRAIN)) { ccprintf("Disable WKINEN!\n"); gpio_enable_wake_up_input( - offset, 0); + offset, 0); idx++; break; } @@ -759,7 +758,7 @@ static int command_gpiodisable(int argc, char **argv) } return EC_ERROR_INVAL; } -DECLARE_CONSOLE_COMMAND(gpiodisable, command_gpiodisable, - "info/list/next/<num> on|off", - "Disable GPIO input buffer to investigate power consumption"); +DECLARE_CONSOLE_COMMAND( + gpiodisable, command_gpiodisable, "info/list/next/<num> on|off", + "Disable GPIO input buffer to investigate power consumption"); #endif diff --git a/chip/npcx/gpio_chip-npcx5.h b/chip/npcx/gpio_chip-npcx5.h index 83916a421b..81ef957236 100644 --- a/chip/npcx/gpio_chip-npcx5.h +++ b/chip/npcx/gpio_chip-npcx5.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -245,7 +245,7 @@ #define NPCX_ALT_GPIO_B_1 ALT(B, 1, NPCX_ALT_INV(A, NO_KSO17_SL)) /* KSO17 */ /* Clock module */ -#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, 32K_OUT_SL)) /* 32KHZ_OUT */ +#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, 32K_OUT_SL)) /* 32KHZ_OUT */ #define NPCX_ALT_GPIO_E_7 ALT(E, 7, NPCX_ALT(A, 32KCLKIN_SL)) /* 32KCLKIN */ /* PS/2 module */ @@ -261,6 +261,7 @@ #define NPCX_ALT_GPIO_A_7 #endif +/* clang-format off */ #define NPCX_ALT_TABLE { \ NPCX_ALT_GPIO_0_3 /* KSO16 */ \ NPCX_ALT_GPIO_0_4 /* KSO13 */ \ @@ -331,54 +332,66 @@ NPCX_ALT_GPIO_D_1 /* SMB3SCL */ \ NPCX_ALT_GPIO_E_7 /* 32KCLKIN */ \ } +/* clang-format on */ /*****************************************************************************/ /* Macro functions for Low-Voltage mapping table */ /* Low-Voltage GPIO Control 0 */ -#define NPCX_LVOL_CTRL_0_0 NPCX_GPIO(B, 5) -#define NPCX_LVOL_CTRL_0_1 NPCX_GPIO(B, 4) -#define NPCX_LVOL_CTRL_0_2 NPCX_GPIO(B, 3) -#define NPCX_LVOL_CTRL_0_3 NPCX_GPIO(B, 2) -#define NPCX_LVOL_CTRL_0_4 NPCX_GPIO(9, 0) -#define NPCX_LVOL_CTRL_0_5 NPCX_GPIO(8, 7) -#define NPCX_LVOL_CTRL_0_6 NPCX_GPIO(0, 0) -#define NPCX_LVOL_CTRL_0_7 NPCX_GPIO(3, 3) +#define NPCX_LVOL_CTRL_0_0 NPCX_GPIO(B, 5) +#define NPCX_LVOL_CTRL_0_1 NPCX_GPIO(B, 4) +#define NPCX_LVOL_CTRL_0_2 NPCX_GPIO(B, 3) +#define NPCX_LVOL_CTRL_0_3 NPCX_GPIO(B, 2) +#define NPCX_LVOL_CTRL_0_4 NPCX_GPIO(9, 0) +#define NPCX_LVOL_CTRL_0_5 NPCX_GPIO(8, 7) +#define NPCX_LVOL_CTRL_0_6 NPCX_GPIO(0, 0) +#define NPCX_LVOL_CTRL_0_7 NPCX_GPIO(3, 3) /* Low-Voltage GPIO Control 1 */ -#define NPCX_LVOL_CTRL_1_0 NPCX_GPIO(9, 2) -#define NPCX_LVOL_CTRL_1_1 NPCX_GPIO(9, 1) -#define NPCX_LVOL_CTRL_1_2 NPCX_GPIO(D, 1) -#define NPCX_LVOL_CTRL_1_3 NPCX_GPIO(D, 0) -#define NPCX_LVOL_CTRL_1_4 NPCX_GPIO(3, 6) -#define NPCX_LVOL_CTRL_1_5 NPCX_GPIO(6, 4) -#define NPCX_LVOL_CTRL_1_6 NPCX_GPIO(6, 5) -#define NPCX_LVOL_CTRL_1_7 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_1_0 NPCX_GPIO(9, 2) +#define NPCX_LVOL_CTRL_1_1 NPCX_GPIO(9, 1) +#define NPCX_LVOL_CTRL_1_2 NPCX_GPIO(D, 1) +#define NPCX_LVOL_CTRL_1_3 NPCX_GPIO(D, 0) +#define NPCX_LVOL_CTRL_1_4 NPCX_GPIO(3, 6) +#define NPCX_LVOL_CTRL_1_5 NPCX_GPIO(6, 4) +#define NPCX_LVOL_CTRL_1_6 NPCX_GPIO(6, 5) +#define NPCX_LVOL_CTRL_1_7 NPCX_GPIO_NONE /* Low-Voltage GPIO Control 2 */ -#define NPCX_LVOL_CTRL_2_0 NPCX_GPIO(7, 4) -#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO(8, 4) -#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO(8, 5) -#define NPCX_LVOL_CTRL_2_3 NPCX_GPIO(7, 3) -#define NPCX_LVOL_CTRL_2_4 NPCX_GPIO(C, 1) -#define NPCX_LVOL_CTRL_2_5 NPCX_GPIO(C, 7) -#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO(E, 7) -#define NPCX_LVOL_CTRL_2_7 NPCX_GPIO(3, 4) +#define NPCX_LVOL_CTRL_2_0 NPCX_GPIO(7, 4) +#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO(8, 4) +#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO(8, 5) +#define NPCX_LVOL_CTRL_2_3 NPCX_GPIO(7, 3) +#define NPCX_LVOL_CTRL_2_4 NPCX_GPIO(C, 1) +#define NPCX_LVOL_CTRL_2_5 NPCX_GPIO(C, 7) +#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO(E, 7) +#define NPCX_LVOL_CTRL_2_7 NPCX_GPIO(3, 4) /* Low-Voltage GPIO Control 3 */ -#define NPCX_LVOL_CTRL_3_0 NPCX_GPIO(C, 6) -#define NPCX_LVOL_CTRL_3_1 NPCX_GPIO(3, 7) -#define NPCX_LVOL_CTRL_3_2 NPCX_GPIO(4, 0) -#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO(7, 1) -#define NPCX_LVOL_CTRL_3_4 NPCX_GPIO(8, 2) -#define NPCX_LVOL_CTRL_3_5 NPCX_GPIO(7, 5) -#define NPCX_LVOL_CTRL_3_6 NPCX_GPIO(8, 0) -#define NPCX_LVOL_CTRL_3_7 NPCX_GPIO(C, 5) +#define NPCX_LVOL_CTRL_3_0 NPCX_GPIO(C, 6) +#define NPCX_LVOL_CTRL_3_1 NPCX_GPIO(3, 7) +#define NPCX_LVOL_CTRL_3_2 NPCX_GPIO(4, 0) +#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO(7, 1) +#define NPCX_LVOL_CTRL_3_4 NPCX_GPIO(8, 2) +#define NPCX_LVOL_CTRL_3_5 NPCX_GPIO(7, 5) +#define NPCX_LVOL_CTRL_3_6 NPCX_GPIO(8, 0) +#define NPCX_LVOL_CTRL_3_7 NPCX_GPIO(C, 5) /* 4 Low-Voltage Control Groups on npcx5 */ -#define NPCX_LVOL_TABLE { { NPCX_LVOL_CTRL_ITEMS(0), }, \ - { NPCX_LVOL_CTRL_ITEMS(1), }, \ - { NPCX_LVOL_CTRL_ITEMS(2), }, \ - { NPCX_LVOL_CTRL_ITEMS(3), }, } +#define NPCX_LVOL_TABLE \ + { \ + { \ + NPCX_LVOL_CTRL_ITEMS(0), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(1), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(2), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(3), \ + }, \ + } #endif /* __CROS_EC_GPIO_CHIP_NPCX5_H */ diff --git a/chip/npcx/gpio_chip-npcx7.h b/chip/npcx/gpio_chip-npcx7.h index 7f815e6d30..39654bc09e 100644 --- a/chip/npcx/gpio_chip-npcx7.h +++ b/chip/npcx/gpio_chip-npcx7.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -82,7 +82,9 @@ #define NPCX_WUI_GPIO_F_0 WUI(0, MIWU_GROUP_8, 5) #define NPCX_WUI_GPIO_F_3 WUI(0, MIWU_GROUP_8, 6) #ifndef NPCX_EXT32K_OSC_SUPPORT -#define NPCX_WUI_GPIO_E_7 WUI(0, MIWU_GROUP_8, 7) /* Used as CLKIN if support */ +#define NPCX_WUI_GPIO_E_7 \ + WUI(0, MIWU_GROUP_8, 7) /* Used as CLKIN if support \ + */ #endif /* MIWU1 */ @@ -151,7 +153,9 @@ #define NPCX_WUI_GPIO_6_3 WUI(1, MIWU_GROUP_7, 3) #define NPCX_WUI_GPIO_6_4 WUI(1, MIWU_GROUP_7, 4) #ifndef NPCX_EXT32K_OSC_SUPPORT -#define NPCX_WUI_GPIO_7_1 WUI(1, MIWU_GROUP_7, 7) /* Used as CLKOUT if support*/ +#define NPCX_WUI_GPIO_7_1 \ + WUI(1, MIWU_GROUP_7, 7) /* Used as CLKOUT if \ + support*/ #endif /* Group H: NPCX_IRQ_WKINTH_1 */ @@ -194,7 +198,7 @@ /* Pin-Mux for PSL/UART2/SMB4_0 */ #ifdef NPCX_PSL_MODE_SUPPORT #if defined(NPCX_SECOND_UART) && (CONFIG_CONSOLE_UART == 1) -#define NPCX_ALT_GPIO_8_6 ALT(8, 6, NPCX_ALT(A, UART2_SL)) /* CR_SOUT2 */ +#define NPCX_ALT_GPIO_8_6 ALT(8, 6, NPCX_ALT(A, UART2_SL)) /* CR_SOUT2 */ #define NPCX_ALT_GPIO_8_5 /* Used as PSL_OUT */ #else #define NPCX_ALT_GPIO_8_6 /* No I2CSDA since GPIO85 used as PSL_OUT */ @@ -214,7 +218,7 @@ /* Pin-Mux for PWM1/SMB6_0 */ #if NPCX7_PWM1_SEL #define NPCX_ALT_GPIO_C_1 /* No I2CSDA since GPIOC2 used as PWM1 */ -#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(4, PWM1_SL)) /* PWM1 */ +#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(4, PWM1_SL)) /* PWM1 */ #else #define NPCX_ALT_GPIO_C_1 ALT(C, 1, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SDA0 */ #define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SCL0 */ @@ -289,7 +293,7 @@ #define NPCX_ALT_GPIO_1_2 ALT(1, 2, NPCX_ALT_INV(8, NO_KSO07_SL)) /* KSO07 */ /* KSO08 & CR_SOUT */ #define NPCX_ALT_GPIO_1_1 ALT(1, 1, NPCX_ALT_INV(9, NO_KSO08_SL)) - /* KSO09 & CR_SIN */ +/* KSO09 & CR_SIN */ #define NPCX_ALT_GPIO_1_0 ALT(1, 0, NPCX_ALT_INV(9, NO_KSO09_SL)) #define NPCX_ALT_GPIO_0_7 ALT(0, 7, NPCX_ALT_INV(9, NO_KSO10_SL)) /* KSO10 */ #define NPCX_ALT_GPIO_0_6 ALT(0, 6, NPCX_ALT_INV(9, NO_KSO11_SL)) /* KSO11 */ @@ -309,17 +313,21 @@ /* Pin-Mux for UART2/32KHZ_OUT */ #if defined(NPCX_SECOND_UART) && (CONFIG_CONSOLE_UART == 1) -#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, UART2_SL)) /* CR_SIN2 */ +#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, UART2_SL)) /* CR_SIN2 */ #else -#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, 32K_OUT_SL)) /* 32KHZ_OUT */ +#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, 32K_OUT_SL)) /* 32KHZ_OUT */ #endif /* PSL module (Optional) */ #ifdef NPCX_PSL_MODE_SUPPORT -#define NPCX_ALT_GPIO_D_2 ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 */ -#define NPCX_ALT_GPIO_0_0 ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 */ -#define NPCX_ALT_GPIO_0_1 ALT(0, 1, NPCX_ALT(D, PSL_IN3_SL)) /* PSL_IN3 */ -#define NPCX_ALT_GPIO_0_2 ALT(0, 2, NPCX_ALT(D, PSL_IN4_SL)) /* PSL_IN4 */ +#define NPCX_ALT_GPIO_D_2 \ + ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 \ + */ +#define NPCX_ALT_GPIO_0_0 \ + ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 \ + */ +#define NPCX_ALT_GPIO_0_1 ALT(0, 1, NPCX_ALT(D, PSL_IN3_SL)) /* PSL_IN3 */ +#define NPCX_ALT_GPIO_0_2 ALT(0, 2, NPCX_ALT(D, PSL_IN4_SL)) /* PSL_IN4 */ #else #define NPCX_ALT_GPIO_D_2 /* NO PSL in NPCX7mnG series */ #define NPCX_ALT_GPIO_0_0 /* NO PSL in NPCX7mnG series */ @@ -328,8 +336,8 @@ #endif /* WOV module (Optional) */ -#if defined(NPCX_WOV_SUPPORT) && \ - (defined(CONFIG_AUDIO_CODEC_I2S_RX) || defined(CONFIG_AUDIO_CODEC_WOV)) +#if defined(NPCX_WOV_SUPPORT) && (defined(CONFIG_AUDIO_CODEC_I2S_RX) || \ + defined(CONFIG_AUDIO_CODEC_WOV)) #define NPCX_ALT_GPIO_9_5 /* Disable SPIP module if WOV is supported */ #define NPCX_ALT_GPIO_A_3 /* Disable SPIP module if WOV is supported */ #define NPCX_ALT_GPIO_A_1 /* Disable SPIP module if WOV is supported */ @@ -356,6 +364,7 @@ #define NPCX_ALT_GPIO_9_7 #endif +/* clang-format off */ #define NPCX_ALT_TABLE { \ NPCX_ALT_GPIO_0_0 /* PSL_IN2 */ \ NPCX_ALT_GPIO_0_1 /* PSL_IN3 */ \ @@ -447,90 +456,110 @@ NPCX_ALT_GPIO_F_4 /* SMB5SDA1 */ \ NPCX_ALT_GPIO_F_5 /* SMB5SCL1 */ \ } +/* clang-format on */ /*****************************************************************************/ /* Macro functions for Low-Voltage mapping table */ /* Low-Voltage GPIO Control 0 */ -#define NPCX_LVOL_CTRL_0_0 NPCX_GPIO(B, 5) -#define NPCX_LVOL_CTRL_0_1 NPCX_GPIO(B, 4) -#define NPCX_LVOL_CTRL_0_2 NPCX_GPIO(B, 3) -#define NPCX_LVOL_CTRL_0_3 NPCX_GPIO(B, 2) -#define NPCX_LVOL_CTRL_0_4 NPCX_GPIO(9, 0) -#define NPCX_LVOL_CTRL_0_5 NPCX_GPIO(8, 7) -#define NPCX_LVOL_CTRL_0_6 NPCX_GPIO(0, 0) -#define NPCX_LVOL_CTRL_0_7 NPCX_GPIO(3, 3) +#define NPCX_LVOL_CTRL_0_0 NPCX_GPIO(B, 5) +#define NPCX_LVOL_CTRL_0_1 NPCX_GPIO(B, 4) +#define NPCX_LVOL_CTRL_0_2 NPCX_GPIO(B, 3) +#define NPCX_LVOL_CTRL_0_3 NPCX_GPIO(B, 2) +#define NPCX_LVOL_CTRL_0_4 NPCX_GPIO(9, 0) +#define NPCX_LVOL_CTRL_0_5 NPCX_GPIO(8, 7) +#define NPCX_LVOL_CTRL_0_6 NPCX_GPIO(0, 0) +#define NPCX_LVOL_CTRL_0_7 NPCX_GPIO(3, 3) /* Low-Voltage GPIO Control 1 */ -#define NPCX_LVOL_CTRL_1_0 NPCX_GPIO(9, 2) -#define NPCX_LVOL_CTRL_1_1 NPCX_GPIO(9, 1) -#define NPCX_LVOL_CTRL_1_2 NPCX_GPIO(D, 1) -#define NPCX_LVOL_CTRL_1_3 NPCX_GPIO(D, 0) -#define NPCX_LVOL_CTRL_1_4 NPCX_GPIO(3, 6) -#define NPCX_LVOL_CTRL_1_5 NPCX_GPIO(6, 4) -#define NPCX_LVOL_CTRL_1_6 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_1_7 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_1_0 NPCX_GPIO(9, 2) +#define NPCX_LVOL_CTRL_1_1 NPCX_GPIO(9, 1) +#define NPCX_LVOL_CTRL_1_2 NPCX_GPIO(D, 1) +#define NPCX_LVOL_CTRL_1_3 NPCX_GPIO(D, 0) +#define NPCX_LVOL_CTRL_1_4 NPCX_GPIO(3, 6) +#define NPCX_LVOL_CTRL_1_5 NPCX_GPIO(6, 4) +#define NPCX_LVOL_CTRL_1_6 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_1_7 NPCX_GPIO_NONE /* Low-Voltage GPIO Control 2 */ -#define NPCX_LVOL_CTRL_2_0 NPCX_GPIO(7, 4) +#define NPCX_LVOL_CTRL_2_0 NPCX_GPIO(7, 4) #ifdef NPCX_PSL_MODE_SUPPORT -#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO_NONE /* Remove 1.8V support since PSL */ -#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO_NONE /* Remove 1.8V support since PSL */ +#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO_NONE /* Remove 1.8V support since PSL */ +#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO_NONE /* Remove 1.8V support since PSL */ #else -#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO(8, 4) -#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO(8, 5) +#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO(8, 4) +#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO(8, 5) #endif -#define NPCX_LVOL_CTRL_2_3 NPCX_GPIO(7, 3) -#define NPCX_LVOL_CTRL_2_4 NPCX_GPIO(C, 1) -#define NPCX_LVOL_CTRL_2_5 NPCX_GPIO(C, 7) +#define NPCX_LVOL_CTRL_2_3 NPCX_GPIO(7, 3) +#define NPCX_LVOL_CTRL_2_4 NPCX_GPIO(C, 1) +#define NPCX_LVOL_CTRL_2_5 NPCX_GPIO(C, 7) #ifdef NPCX_EXT32K_OSC_SUPPORT -#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO_NONE /* Remove 1.8V support since CLKIN */ +#define NPCX_LVOL_CTRL_2_6 \ + NPCX_GPIO_NONE /* Remove 1.8V support since CLKIN \ + */ #else -#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO(E, 7) +#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO(E, 7) #endif -#define NPCX_LVOL_CTRL_2_7 NPCX_GPIO(3, 4) +#define NPCX_LVOL_CTRL_2_7 NPCX_GPIO(3, 4) /* Low-Voltage GPIO Control 3 */ -#define NPCX_LVOL_CTRL_3_0 NPCX_GPIO(C, 6) -#define NPCX_LVOL_CTRL_3_1 NPCX_GPIO(3, 7) -#define NPCX_LVOL_CTRL_3_2 NPCX_GPIO(4, 0) +#define NPCX_LVOL_CTRL_3_0 NPCX_GPIO(C, 6) +#define NPCX_LVOL_CTRL_3_1 NPCX_GPIO(3, 7) +#define NPCX_LVOL_CTRL_3_2 NPCX_GPIO(4, 0) #ifdef NPCX_EXT32K_OSC_SUPPORT -#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO_NONE /* Remove 1.8V support since CLKOUT*/ +#define NPCX_LVOL_CTRL_3_3 \ + NPCX_GPIO_NONE /* Remove 1.8V support since \ + CLKOUT*/ #else -#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO(7, 1) +#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO(7, 1) #endif -#define NPCX_LVOL_CTRL_3_4 NPCX_GPIO(8, 2) -#define NPCX_LVOL_CTRL_3_5 NPCX_GPIO(7, 5) -#define NPCX_LVOL_CTRL_3_6 NPCX_GPIO(8, 0) -#define NPCX_LVOL_CTRL_3_7 NPCX_GPIO(C, 5) +#define NPCX_LVOL_CTRL_3_4 NPCX_GPIO(8, 2) +#define NPCX_LVOL_CTRL_3_5 NPCX_GPIO(7, 5) +#define NPCX_LVOL_CTRL_3_6 NPCX_GPIO(8, 0) +#define NPCX_LVOL_CTRL_3_7 NPCX_GPIO(C, 5) /* Low-Voltage GPIO Control 4 */ -#define NPCX_LVOL_CTRL_4_0 NPCX_GPIO(8, 6) -#define NPCX_LVOL_CTRL_4_1 NPCX_GPIO(C, 2) -#define NPCX_LVOL_CTRL_4_2 NPCX_GPIO(F, 3) -#define NPCX_LVOL_CTRL_4_3 NPCX_GPIO(F, 2) -#define NPCX_LVOL_CTRL_4_4 NPCX_GPIO(F, 5) -#define NPCX_LVOL_CTRL_4_5 NPCX_GPIO(F, 4) -#define NPCX_LVOL_CTRL_4_6 NPCX_GPIO(E, 4) -#define NPCX_LVOL_CTRL_4_7 NPCX_GPIO(E, 3) +#define NPCX_LVOL_CTRL_4_0 NPCX_GPIO(8, 6) +#define NPCX_LVOL_CTRL_4_1 NPCX_GPIO(C, 2) +#define NPCX_LVOL_CTRL_4_2 NPCX_GPIO(F, 3) +#define NPCX_LVOL_CTRL_4_3 NPCX_GPIO(F, 2) +#define NPCX_LVOL_CTRL_4_4 NPCX_GPIO(F, 5) +#define NPCX_LVOL_CTRL_4_5 NPCX_GPIO(F, 4) +#define NPCX_LVOL_CTRL_4_6 NPCX_GPIO(E, 4) +#define NPCX_LVOL_CTRL_4_7 NPCX_GPIO(E, 3) /* Low-Voltage GPIO Control 5 */ -#define NPCX_LVOL_CTRL_5_0 NPCX_GPIO(7, 2) -#define NPCX_LVOL_CTRL_5_1 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_5_2 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_5_3 NPCX_GPIO(5, 0) -#define NPCX_LVOL_CTRL_5_4 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_5_5 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_5_6 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_5_7 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_0 NPCX_GPIO(7, 2) +#define NPCX_LVOL_CTRL_5_1 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_2 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_3 NPCX_GPIO(5, 0) +#define NPCX_LVOL_CTRL_5_4 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_5 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_6 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_7 NPCX_GPIO_NONE /* 6 Low-Voltage Control Groups on npcx7 */ -#define NPCX_LVOL_TABLE { { NPCX_LVOL_CTRL_ITEMS(0), }, \ - { NPCX_LVOL_CTRL_ITEMS(1), }, \ - { NPCX_LVOL_CTRL_ITEMS(2), }, \ - { NPCX_LVOL_CTRL_ITEMS(3), }, \ - { NPCX_LVOL_CTRL_ITEMS(4), }, \ - { NPCX_LVOL_CTRL_ITEMS(5), }, } +#define NPCX_LVOL_TABLE \ + { \ + { \ + NPCX_LVOL_CTRL_ITEMS(0), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(1), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(2), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(3), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(4), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(5), \ + }, \ + } #endif /* __CROS_EC_GPIO_CHIP_NPCX7_H */ diff --git a/chip/npcx/gpio_chip-npcx9.h b/chip/npcx/gpio_chip-npcx9.h index 005a03d83e..aef2f4f044 100644 --- a/chip/npcx/gpio_chip-npcx9.h +++ b/chip/npcx/gpio_chip-npcx9.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -200,7 +200,7 @@ /* Pin-Mux for PWM1/SMB6_0 */ #if NPCX9_PWM1_SEL #define NPCX_ALT_GPIO_C_1 /* No I2CSDA since GPIOC2 used as PWM1 */ -#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(4, PWM1_SL)) /* PWM1 */ +#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(4, PWM1_SL)) /* PWM1 */ #else #define NPCX_ALT_GPIO_C_1 ALT(C, 1, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SDA0 */ #define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SCL0 */ @@ -219,17 +219,17 @@ #define NPCX_ALT_GPIO_3_7 ALT(3, 7, NPCX_ALT(F, ADC5_SL)) /* ADC5 */ #define NPCX_ALT_GPIO_3_4 ALT(3, 4, NPCX_ALT(F, ADC6_SL)) /* ADC6 */ #endif -#define NPCX_ALT_GPIO_F_1 ALT(F, 1, NPCX_ALT(F, ADC8_SL)) /* ADC8 */ -#define NPCX_ALT_GPIO_E_1 ALT(E, 1, NPCX_ALT(F, ADC7_SL)) /* ADC7 */ -#define NPCX_ALT_GPIO_F_0 ALT(F, 0, NPCX_ALT(F, ADC9_SL)) /* ADC9 */ +#define NPCX_ALT_GPIO_F_1 ALT(F, 1, NPCX_ALT(F, ADC8_SL)) /* ADC8 */ +#define NPCX_ALT_GPIO_E_1 ALT(E, 1, NPCX_ALT(F, ADC7_SL)) /* ADC7 */ +#define NPCX_ALT_GPIO_F_0 ALT(F, 0, NPCX_ALT(F, ADC9_SL)) /* ADC9 */ #define NPCX_ALT_GPIO_E_0 ALT(E, 0, NPCX_ALT(F, ADC10_SL)) /* AD10 */ #define NPCX_ALT_GPIO_C_7 ALT(C, 7, NPCX_ALT(F, ADC11_SL)) /* AD11 */ /* PS/2 Module */ -#define NPCX_ALT_GPIO_6_7 ALT(6, 7, NPCX_ALT(3, PS2_0_SL)) /* PS2_CLK0 */ -#define NPCX_ALT_GPIO_7_0 ALT(7, 0, NPCX_ALT(3, PS2_0_SL)) /* PS2_DATA0 */ -#define NPCX_ALT_GPIO_6_2 ALT(6, 2, NPCX_ALT(3, PS2_1_SL)) /* PS2_CLK1 */ -#define NPCX_ALT_GPIO_6_3 ALT(6, 3, NPCX_ALT(3, PS2_1_SL)) /* PS2_DATA1 */ +#define NPCX_ALT_GPIO_6_7 ALT(6, 7, NPCX_ALT(3, PS2_0_SL)) /* PS2_CLK0 */ +#define NPCX_ALT_GPIO_7_0 ALT(7, 0, NPCX_ALT(3, PS2_0_SL)) /* PS2_DATA0 */ +#define NPCX_ALT_GPIO_6_2 ALT(6, 2, NPCX_ALT(3, PS2_1_SL)) /* PS2_CLK1 */ +#define NPCX_ALT_GPIO_6_3 ALT(6, 3, NPCX_ALT(3, PS2_1_SL)) /* PS2_DATA1 */ #if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3) #define NPCX_ALT_GPIO_A_7 ALT(A, 7, NPCX_ALT(C, PS2_3_SL2)) /* PS2_DAT3 */ #else @@ -237,12 +237,19 @@ #endif /* UART Module */ -#define NPCX_ALT_GPIO_6_4 ALT(6, 4, NPCX_ALT(J, CR_SIN1_SL2)) /* CR_SIN1_SL2 */ -#define NPCX_ALT_GPIO_6_5 ALT(6, 5, NPCX_ALT(J, CR_SOUT1_SL2))/* CR_SOUT1_SL2 */ -#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(J, CR_SIN2_SL)) /* CR_SIN2_SL */ -#define NPCX_ALT_GPIO_8_6 ALT(8, 6, NPCX_ALT(J, CR_SOUT2_SL)) /* CR_SOUT2_SL */ -#define NPCX_ALT_GPIO_D_4 ALT(D, 4, NPCX_ALT(J, CR_SIN3_SL)) /* CR_SIN3_SL */ -#define NPCX_ALT_GPIO_D_6 ALT(D, 6, NPCX_ALT(J, CR_SOUT3_SL)) /* CR_SOUT3_SL */ +#define NPCX_ALT_GPIO_6_4 \ + ALT(6, 4, NPCX_ALT(J, CR_SIN1_SL2)) /* CR_SIN1_SL2 \ + */ +#define NPCX_ALT_GPIO_6_5 \ + ALT(6, 5, NPCX_ALT(J, CR_SOUT1_SL2)) /* CR_SOUT1_SL2 */ +#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(J, CR_SIN2_SL)) /* CR_SIN2_SL */ +#define NPCX_ALT_GPIO_8_6 \ + ALT(8, 6, NPCX_ALT(J, CR_SOUT2_SL)) /* CR_SOUT2_SL \ + */ +#define NPCX_ALT_GPIO_D_4 ALT(D, 4, NPCX_ALT(J, CR_SIN3_SL)) /* CR_SIN3_SL */ +#define NPCX_ALT_GPIO_D_6 \ + ALT(D, 6, NPCX_ALT(J, CR_SOUT3_SL)) /* CR_SOUT3_SL \ + */ /* PWM Module */ #define NPCX_ALT_GPIO_C_3 ALT(C, 3, NPCX_ALT(4, PWM0_SL)) /* PWM0 */ @@ -282,7 +289,7 @@ #define NPCX_ALT_GPIO_1_2 ALT(1, 2, NPCX_ALT_INV(8, NO_KSO07_SL)) /* KSO07 */ /* KSO08 & CR_SOUT */ #define NPCX_ALT_GPIO_1_1 ALT(1, 1, NPCX_ALT_INV(9, NO_KSO08_SL)) - /* KSO09 & CR_SIN */ +/* KSO09 & CR_SIN */ #define NPCX_ALT_GPIO_1_0 ALT(1, 0, NPCX_ALT_INV(9, NO_KSO09_SL)) #define NPCX_ALT_GPIO_0_7 ALT(0, 7, NPCX_ALT_INV(9, NO_KSO10_SL)) /* KSO10 */ #define NPCX_ALT_GPIO_0_6 ALT(0, 6, NPCX_ALT_INV(9, NO_KSO11_SL)) /* KSO11 */ @@ -294,17 +301,22 @@ #define NPCX_ALT_GPIO_B_1 ALT(B, 1, NPCX_ALT_INV(A, NO_KSO17_SL)) /* KSO17 */ /* PSL module */ -#define NPCX_ALT_GPIO_D_2 ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 */ -#define NPCX_ALT_GPIO_0_0 ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 */ -#define NPCX_ALT_GPIO_0_1 ALT(0, 1, NPCX_ALT(D, PSL_IN3_SL)) /* PSL_IN3 */ -#define NPCX_ALT_GPIO_0_2 ALT(0, 2, NPCX_ALT(D, PSL_IN4_SL)) /* PSL_IN4 */ -#define NPCX_ALT_GPIO_D_7 ALT(D, 7, NPCX_ALT(G, PSL_GPO_SL)) /* PSL_GPO */ +#define NPCX_ALT_GPIO_D_2 \ + ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 \ + */ +#define NPCX_ALT_GPIO_0_0 \ + ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 \ + */ +#define NPCX_ALT_GPIO_0_1 ALT(0, 1, NPCX_ALT(D, PSL_IN3_SL)) /* PSL_IN3 */ +#define NPCX_ALT_GPIO_0_2 ALT(0, 2, NPCX_ALT(D, PSL_IN4_SL)) /* PSL_IN4 */ +#define NPCX_ALT_GPIO_D_7 ALT(D, 7, NPCX_ALT(G, PSL_GPO_SL)) /* PSL_GPO */ /* SPI Module */ #define NPCX_ALT_GPIO_9_5 ALT(9, 5, NPCX_ALT(0, SPIP_SL)) /* SPIP_MISO */ #define NPCX_ALT_GPIO_A_3 ALT(A, 3, NPCX_ALT(0, SPIP_SL)) /* SPIP_MOSI */ #define NPCX_ALT_GPIO_A_1 ALT(A, 1, NPCX_ALT(0, SPIP_SL)) /* SPIP_SCLK */ +/* clang-format off */ #define NPCX_ALT_TABLE { \ NPCX_ALT_GPIO_0_0 /* PSL_IN2 */ \ NPCX_ALT_GPIO_0_1 /* PSL_IN3 */ \ @@ -395,76 +407,92 @@ NPCX_ALT_GPIO_F_4 /* SMB5SDA1 */ \ NPCX_ALT_GPIO_F_5 /* SMB5SCL1 */ \ } +/* clang-format on */ /*****************************************************************************/ /* Macro functions for Low-Voltage mapping table */ /* Low-Voltage GPIO Control 0 */ -#define NPCX_LVOL_CTRL_0_0 NPCX_GPIO(B, 5) -#define NPCX_LVOL_CTRL_0_1 NPCX_GPIO(B, 4) -#define NPCX_LVOL_CTRL_0_2 NPCX_GPIO(B, 3) -#define NPCX_LVOL_CTRL_0_3 NPCX_GPIO(B, 2) -#define NPCX_LVOL_CTRL_0_4 NPCX_GPIO(9, 0) -#define NPCX_LVOL_CTRL_0_5 NPCX_GPIO(8, 7) -#define NPCX_LVOL_CTRL_0_6 NPCX_GPIO(0, 0) -#define NPCX_LVOL_CTRL_0_7 NPCX_GPIO(3, 3) +#define NPCX_LVOL_CTRL_0_0 NPCX_GPIO(B, 5) +#define NPCX_LVOL_CTRL_0_1 NPCX_GPIO(B, 4) +#define NPCX_LVOL_CTRL_0_2 NPCX_GPIO(B, 3) +#define NPCX_LVOL_CTRL_0_3 NPCX_GPIO(B, 2) +#define NPCX_LVOL_CTRL_0_4 NPCX_GPIO(9, 0) +#define NPCX_LVOL_CTRL_0_5 NPCX_GPIO(8, 7) +#define NPCX_LVOL_CTRL_0_6 NPCX_GPIO(0, 0) +#define NPCX_LVOL_CTRL_0_7 NPCX_GPIO(3, 3) /* Low-Voltage GPIO Control 1 */ -#define NPCX_LVOL_CTRL_1_0 NPCX_GPIO(9, 2) -#define NPCX_LVOL_CTRL_1_1 NPCX_GPIO(9, 1) -#define NPCX_LVOL_CTRL_1_2 NPCX_GPIO(D, 1) -#define NPCX_LVOL_CTRL_1_3 NPCX_GPIO(D, 0) -#define NPCX_LVOL_CTRL_1_4 NPCX_GPIO(3, 6) -#define NPCX_LVOL_CTRL_1_5 NPCX_GPIO(6, 4) -#define NPCX_LVOL_CTRL_1_6 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_1_7 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_1_0 NPCX_GPIO(9, 2) +#define NPCX_LVOL_CTRL_1_1 NPCX_GPIO(9, 1) +#define NPCX_LVOL_CTRL_1_2 NPCX_GPIO(D, 1) +#define NPCX_LVOL_CTRL_1_3 NPCX_GPIO(D, 0) +#define NPCX_LVOL_CTRL_1_4 NPCX_GPIO(3, 6) +#define NPCX_LVOL_CTRL_1_5 NPCX_GPIO(6, 4) +#define NPCX_LVOL_CTRL_1_6 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_1_7 NPCX_GPIO_NONE /* Low-Voltage GPIO Control 2 */ -#define NPCX_LVOL_CTRL_2_0 NPCX_GPIO(7, 4) -#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_2_3 NPCX_GPIO(7, 3) -#define NPCX_LVOL_CTRL_2_4 NPCX_GPIO(C, 1) -#define NPCX_LVOL_CTRL_2_5 NPCX_GPIO(C, 7) -#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_2_7 NPCX_GPIO(3, 4) +#define NPCX_LVOL_CTRL_2_0 NPCX_GPIO(7, 4) +#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_2_3 NPCX_GPIO(7, 3) +#define NPCX_LVOL_CTRL_2_4 NPCX_GPIO(C, 1) +#define NPCX_LVOL_CTRL_2_5 NPCX_GPIO(C, 7) +#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_2_7 NPCX_GPIO(3, 4) /* Low-Voltage GPIO Control 3 */ -#define NPCX_LVOL_CTRL_3_0 NPCX_GPIO(C, 6) -#define NPCX_LVOL_CTRL_3_1 NPCX_GPIO(3, 7) -#define NPCX_LVOL_CTRL_3_2 NPCX_GPIO(4, 0) -#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_3_4 NPCX_GPIO(8, 2) -#define NPCX_LVOL_CTRL_3_5 NPCX_GPIO(7, 5) -#define NPCX_LVOL_CTRL_3_6 NPCX_GPIO(8, 0) -#define NPCX_LVOL_CTRL_3_7 NPCX_GPIO(C, 5) +#define NPCX_LVOL_CTRL_3_0 NPCX_GPIO(C, 6) +#define NPCX_LVOL_CTRL_3_1 NPCX_GPIO(3, 7) +#define NPCX_LVOL_CTRL_3_2 NPCX_GPIO(4, 0) +#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_3_4 NPCX_GPIO(8, 2) +#define NPCX_LVOL_CTRL_3_5 NPCX_GPIO(7, 5) +#define NPCX_LVOL_CTRL_3_6 NPCX_GPIO(8, 0) +#define NPCX_LVOL_CTRL_3_7 NPCX_GPIO(C, 5) /* Low-Voltage GPIO Control 4 */ -#define NPCX_LVOL_CTRL_4_0 NPCX_GPIO(8, 6) -#define NPCX_LVOL_CTRL_4_1 NPCX_GPIO(C, 2) -#define NPCX_LVOL_CTRL_4_2 NPCX_GPIO(F, 3) -#define NPCX_LVOL_CTRL_4_3 NPCX_GPIO(F, 2) -#define NPCX_LVOL_CTRL_4_4 NPCX_GPIO(F, 5) -#define NPCX_LVOL_CTRL_4_5 NPCX_GPIO(F, 4) -#define NPCX_LVOL_CTRL_4_6 NPCX_GPIO(E, 4) -#define NPCX_LVOL_CTRL_4_7 NPCX_GPIO(E, 3) +#define NPCX_LVOL_CTRL_4_0 NPCX_GPIO(8, 6) +#define NPCX_LVOL_CTRL_4_1 NPCX_GPIO(C, 2) +#define NPCX_LVOL_CTRL_4_2 NPCX_GPIO(F, 3) +#define NPCX_LVOL_CTRL_4_3 NPCX_GPIO(F, 2) +#define NPCX_LVOL_CTRL_4_4 NPCX_GPIO(F, 5) +#define NPCX_LVOL_CTRL_4_5 NPCX_GPIO(F, 4) +#define NPCX_LVOL_CTRL_4_6 NPCX_GPIO(E, 4) +#define NPCX_LVOL_CTRL_4_7 NPCX_GPIO(E, 3) /* Low-Voltage GPIO Control 5 */ -#define NPCX_LVOL_CTRL_5_0 NPCX_GPIO(7, 2) -#define NPCX_LVOL_CTRL_5_1 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_5_2 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_5_3 NPCX_GPIO(5, 0) -#define NPCX_LVOL_CTRL_5_4 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_5_5 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_5_6 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_5_7 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_0 NPCX_GPIO(7, 2) +#define NPCX_LVOL_CTRL_5_1 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_2 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_3 NPCX_GPIO(5, 0) +#define NPCX_LVOL_CTRL_5_4 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_5 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_6 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_7 NPCX_GPIO_NONE /* 6 Low-Voltage Control Groups on npcx7 */ -#define NPCX_LVOL_TABLE { { NPCX_LVOL_CTRL_ITEMS(0), }, \ - { NPCX_LVOL_CTRL_ITEMS(1), }, \ - { NPCX_LVOL_CTRL_ITEMS(2), }, \ - { NPCX_LVOL_CTRL_ITEMS(3), }, \ - { NPCX_LVOL_CTRL_ITEMS(4), }, \ - { NPCX_LVOL_CTRL_ITEMS(5), }, } +#define NPCX_LVOL_TABLE \ + { \ + { \ + NPCX_LVOL_CTRL_ITEMS(0), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(1), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(2), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(3), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(4), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(5), \ + }, \ + } #endif /* __CROS_EC_GPIO_CHIP_NPCX9_H */ diff --git a/chip/npcx/gpio_chip.h b/chip/npcx/gpio_chip.h index 2d0b2b4e9b..5f60cdfb40 100644 --- a/chip/npcx/gpio_chip.h +++ b/chip/npcx/gpio_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,37 +9,40 @@ struct npcx_wui { uint8_t table : 2; uint8_t group : 3; - uint8_t bit : 3; + uint8_t bit : 3; }; /* Macros to initialize the MIWU mapping table. */ #define NPCX_WUI_GPIO_PIN(port, index) NPCX_WUI_GPIO_##port##_##index -#define WUI(tbl, grp, idx) ((struct npcx_wui) { .table = tbl, .group = grp, \ - .bit = idx }) -#define WUI_INT(tbl, grp) WUI(tbl, grp, 0) -#define WUI_NONE ((struct npcx_wui) { .table = MIWU_TABLE_COUNT, .group = 0, \ - .bit = 0 }) +#define WUI(tbl, grp, idx) \ + ((struct npcx_wui){ .table = tbl, .group = grp, .bit = idx }) +#define WUI_INT(tbl, grp) WUI(tbl, grp, 0) +#define WUI_NONE \ + ((struct npcx_wui){ .table = MIWU_TABLE_COUNT, .group = 0, .bit = 0 }) /* Macros to initialize the alternative and low voltage mapping table. */ -#define NPCX_GPIO_NONE ((struct npcx_gpio) {.port = 0, .bit = 0, .valid = 0}) -#define NPCX_GPIO(grp, pin) ((struct npcx_gpio) {.port = GPIO_PORT_##grp, \ - .bit = pin, .valid = 1}) +#define NPCX_GPIO_NONE ((struct npcx_gpio){ .port = 0, .bit = 0, .valid = 0 }) +#define NPCX_GPIO(grp, pin) \ + ((struct npcx_gpio){ .port = GPIO_PORT_##grp, .bit = pin, .valid = 1 }) -#define NPCX_ALT(grp, pin) ((struct npcx_alt) {.group = ALT_GROUP_##grp, \ - .bit = NPCX_DEVALT##grp##_##pin, .inverted = 0 }) -#define NPCX_ALT_INV(grp, pin) ((struct npcx_alt) {.group = ALT_GROUP_##grp, \ - .bit = NPCX_DEVALT##grp##_##pin, .inverted = 1 }) -#define ALT(port, index, _alt) { .gpio = NPCX_GPIO(port, index), \ - .alt = (_alt) }, +#define NPCX_ALT(grp, pin) \ + ((struct npcx_alt){ .group = ALT_GROUP_##grp, \ + .bit = NPCX_DEVALT##grp##_##pin, \ + .inverted = 0 }) +#define NPCX_ALT_INV(grp, pin) \ + ((struct npcx_alt){ .group = ALT_GROUP_##grp, \ + .bit = NPCX_DEVALT##grp##_##pin, \ + .inverted = 1 }) +#define ALT(port, index, _alt) \ + { .gpio = NPCX_GPIO(port, index), .alt = (_alt) }, -#define NPCX_LVOL_CTRL_ITEMS(ctrl) { NPCX_LVOL_CTRL_##ctrl##_0, \ - NPCX_LVOL_CTRL_##ctrl##_1, \ - NPCX_LVOL_CTRL_##ctrl##_2, \ - NPCX_LVOL_CTRL_##ctrl##_3, \ - NPCX_LVOL_CTRL_##ctrl##_4, \ - NPCX_LVOL_CTRL_##ctrl##_5, \ - NPCX_LVOL_CTRL_##ctrl##_6, \ - NPCX_LVOL_CTRL_##ctrl##_7, } +#define NPCX_LVOL_CTRL_ITEMS(ctrl) \ + { \ + NPCX_LVOL_CTRL_##ctrl##_0, NPCX_LVOL_CTRL_##ctrl##_1, \ + NPCX_LVOL_CTRL_##ctrl##_2, NPCX_LVOL_CTRL_##ctrl##_3, \ + NPCX_LVOL_CTRL_##ctrl##_4, NPCX_LVOL_CTRL_##ctrl##_5, \ + NPCX_LVOL_CTRL_##ctrl##_6, NPCX_LVOL_CTRL_##ctrl##_7, \ + } /** * Switch NPCX UART pins back to normal GPIOs. diff --git a/chip/npcx/header.c b/chip/npcx/header.c index 0ba3ee59d6..2db7d9094c 100644 --- a/chip/npcx/header.c +++ b/chip/npcx/header.c @@ -1,5 +1,5 @@ /* - * Copyright 2015 The Chromium OS Authors. All rights reserved. + * Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -16,59 +16,60 @@ #include "registers.h" /* Signature used by fw header */ -#define SIG_FW_EC 0x2A3B4D5E +#define SIG_FW_EC 0x2A3B4D5E /* Definition used by error detection configuration */ -#define CHECK_CRC 0x00 -#define CHECK_CHECKSUM 0x01 -#define ERROR_DETECTION_EN 0x02 +#define CHECK_CRC 0x00 +#define CHECK_CHECKSUM 0x01 +#define ERROR_DETECTION_EN 0x02 #define ERROR_DETECTION_DIS 0x00 /* Code RAM addresses use by header */ /* Put FW at the begin of CODE RAM */ -#define FW_START_ADDR CONFIG_PROGRAM_MEMORY_BASE +#define FW_START_ADDR CONFIG_PROGRAM_MEMORY_BASE /* TODO: It will be filled automatically by ECST */ /* The entry point of reset handler (filled by ECST tool)*/ -#define FW_ENTRY_ADDR 0x100A8169 +#define FW_ENTRY_ADDR 0x100A8169 /* Error detection addresses use by header (A offset relative to flash image) */ -#define ERRCHK_START_ADDR 0x0 -#define ERRCHK_END_ADDR 0x0 +#define ERRCHK_START_ADDR 0x0 +#define ERRCHK_END_ADDR 0x0 /* Firmware Size -> Booter loads RO region after hard reset (16 bytes aligned)*/ -#define FW_SIZE CONFIG_RO_SIZE +#define FW_SIZE CONFIG_RO_SIZE /* FW Header used by NPCX5M5G Booter */ struct __packed fw_header_t { - uint32_t anchor; /* A constant used to verify FW header */ - uint16_t ext_anchor; /* Enable/disable firmware header CRC check */ - uint8_t spi_max_freq; /* Spi maximum allowable clock frequency */ - uint8_t spi_read_mode; /* Spi read mode used for firmware loading */ - uint8_t cfg_err_detect; /* FW load error detection configuration */ - uint32_t fw_load_addr; /* Firmware load start address */ - uint32_t fw_entry; /* Firmware entry point */ + uint32_t anchor; /* A constant used to verify FW header */ + uint16_t ext_anchor; /* Enable/disable firmware header CRC check */ + uint8_t spi_max_freq; /* Spi maximum allowable clock frequency */ + uint8_t spi_read_mode; /* Spi read mode used for firmware loading */ + uint8_t cfg_err_detect; /* FW load error detection configuration */ + uint32_t fw_load_addr; /* Firmware load start address */ + uint32_t fw_entry; /* Firmware entry point */ uint32_t err_detect_start_addr; /* FW error detect start address */ - uint32_t err_detect_end_addr; /* FW error detect end address */ - uint32_t fw_length; /* Firmware length in bytes */ - uint8_t flash_size; /* Indicate SPI flash size */ - uint8_t reserved[26]; /* Reserved bytes */ - uint32_t sig_header; /* The CRC signature of the firmware header */ - uint32_t sig_fw_image; /* The CRC or Checksum of the firmware image */ + uint32_t err_detect_end_addr; /* FW error detect end address */ + uint32_t fw_length; /* Firmware length in bytes */ + uint8_t flash_size; /* Indicate SPI flash size */ + uint8_t reserved[26]; /* Reserved bytes */ + uint32_t sig_header; /* The CRC signature of the firmware header */ + uint32_t sig_fw_image; /* The CRC or Checksum of the firmware image */ } __aligned(1); -__keep __attribute__ ((section(".header"))) +__keep __attribute__((section(".header"))) const struct fw_header_t fw_header = { /* 00 */ SIG_FW_EC, /* 04 */ 0x54E1, /* Header CRC check Enable/Disable -> AB1Eh/54E1h */ - /* 06 */ 0x04, /* 20/25/33/40/50 MHz -> 00/01/02/03/04h */ - /* 07 */ 0x03, /* Normal/Fast/Rev/D_IO/Q_IO Mode -> 00/01/02/03/04h */ - /* 08 */ 0x00, /* Disable CRC check functionality */ + /* 06 */ 0x04, /* 20/25/33/40/50 MHz -> 00/01/02/03/04h */ + /* 07 */ 0x03, /* Normal/Fast/Rev/D_IO/Q_IO Mode -> 00/01/02/03/04h */ + /* 08 */ 0x00, /* Disable CRC check functionality */ /* 09 */ FW_START_ADDR, - /* 0D */ FW_ENTRY_ADDR,/* Filling by ECST tool with -usearmrst option */ + /* 0D */ FW_ENTRY_ADDR, /* Filling by ECST tool with -usearmrst option + */ /* 11 */ ERRCHK_START_ADDR, /* 15 */ ERRCHK_END_ADDR, - /* 19 */ FW_SIZE,/* Filling by ECST tool */ - /* 1D */ 0x0F, /* Flash Size 1/2/4/8/16 Mbytes -> 01/03/07/0F/1Fh */ + /* 19 */ FW_SIZE, /* Filling by ECST tool */ + /* 1D */ 0x0F, /* Flash Size 1/2/4/8/16 Mbytes -> 01/03/07/0F/1Fh */ /* 1E-3F Other fields are filled by ECST tool or reserved */ }; diff --git a/chip/npcx/hwtimer.c b/chip/npcx/hwtimer.c index b479f237c0..dfa06f69b2 100644 --- a/chip/npcx/hwtimer.c +++ b/chip/npcx/hwtimer.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,10 +19,10 @@ #include "util.h" /* Depth of event timer */ -#define TICK_EVT_DEPTH 16 /* Depth of event timer Unit: bits */ -#define TICK_EVT_INTERVAL BIT(TICK_EVT_DEPTH) /* Unit: us */ +#define TICK_EVT_DEPTH 16 /* Depth of event timer Unit: bits */ +#define TICK_EVT_INTERVAL BIT(TICK_EVT_DEPTH) /* Unit: us */ #define TICK_EVT_INTERVAL_MASK (TICK_EVT_INTERVAL - 1) /* Mask of interval */ -#define TICK_EVT_MAX_CNT (TICK_EVT_INTERVAL - 1) /* Maximum event counter */ +#define TICK_EVT_MAX_CNT (TICK_EVT_INTERVAL - 1) /* Maximum event counter */ /* Time when event will be expired unit:us */ static volatile uint32_t evt_expired_us; @@ -39,7 +39,7 @@ static volatile uint32_t cur_cnt_us_dbg; #define CPRINTS(...) #else #define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) #endif /*****************************************************************************/ @@ -48,7 +48,7 @@ void init_hw_timer(int itim_no, enum ITIM_SOURCE_CLOCK_T source) { /* Select which clock to use for this timer */ UPDATE_BIT(NPCX_ITCTS(itim_no), NPCX_ITCTS_CKSEL, - source != ITIM_SOURCE_CLOCK_APB2); + source != ITIM_SOURCE_CLOCK_APB2); /* Clear timeout status */ SET_BIT(NPCX_ITCTS(itim_no), NPCX_ITCTS_TO_STS); @@ -64,8 +64,8 @@ void init_hw_timer(int itim_no, enum ITIM_SOURCE_CLOCK_T source) /* HWTimer event handlers */ void __hw_clock_event_set(uint32_t deadline) { - fp_t inv_evt_tick = FLOAT_TO_FP(INT_32K_CLOCK/(float)SECOND); - int32_t evt_cnt_us; + fp_t inv_evt_tick = FLOAT_TO_FP(INT_32K_CLOCK / (float)SECOND); + int32_t evt_cnt_us; /* Is deadline min value? */ if (evt_expired_us != 0 && evt_expired_us < deadline) return; @@ -87,10 +87,10 @@ void __hw_clock_event_set(uint32_t deadline) * ITIM count down : event expired : Unit: 1/32768 sec * It must exceed evt_expired_us for process_timers function */ - evt_cnt = FP_TO_INT((fp_inter_t)(evt_cnt_us) * inv_evt_tick); + evt_cnt = FP_TO_INT((fp_inter_t)(evt_cnt_us)*inv_evt_tick); if (evt_cnt > TICK_EVT_MAX_CNT) { - CPRINTS("Event overflow! 0x%08x, us is %d", - evt_cnt, evt_cnt_us); + CPRINTS("Event overflow! 0x%08x, us is %d", evt_cnt, + evt_cnt_us); evt_cnt = TICK_EVT_MAX_CNT; } @@ -136,16 +136,17 @@ uint16_t __hw_clock_event_count(void) /* Returns time delay cause of deep idle */ uint32_t __hw_clock_get_sleep_time(uint16_t pre_evt_cnt) { - fp_t evt_tick = FLOAT_TO_FP(SECOND/(float)INT_32K_CLOCK); + fp_t evt_tick = FLOAT_TO_FP(SECOND / (float)INT_32K_CLOCK); uint32_t sleep_time; uint16_t cnt = __hw_clock_event_count(); /* Event has been triggered but timer ISR doesn't handle it */ if (IS_BIT_SET(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_TO_STS)) - sleep_time = FP_TO_INT((fp_inter_t)(pre_evt_cnt+1) * evt_tick); + sleep_time = + FP_TO_INT((fp_inter_t)(pre_evt_cnt + 1) * evt_tick); /* Event hasn't been triggered */ else - sleep_time = FP_TO_INT((fp_inter_t)(pre_evt_cnt+1 - cnt) * + sleep_time = FP_TO_INT((fp_inter_t)(pre_evt_cnt + 1 - cnt) * evt_tick); return sleep_time; @@ -194,7 +195,6 @@ static void __hw_clock_event_irq(void) if (evt_expired_us == 0) __hw_clock_event_set(EVT_MAX_EXPIRED_US); #endif - } DECLARE_IRQ(ITIM_INT(ITIM_EVENT_NO), __hw_clock_event_irq, 3); @@ -295,10 +295,9 @@ static void update_prescaler(void) * Ttick_unit = (PRE_8+1) * Tapb2_clk * PRE_8 = (Ttick_unit/Tapb2_clk) -1 */ - NPCX_ITPRE(ITIM_SYSTEM_NO) = (clock_get_apb2_freq() / SECOND) - 1; + NPCX_ITPRE(ITIM_SYSTEM_NO) = (clock_get_apb2_freq() / SECOND) - 1; /* Set event tick unit = 1/32768 sec */ NPCX_ITPRE(ITIM_EVENT_NO) = 0; - } DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT); @@ -311,10 +310,10 @@ void __hw_early_init_hwtimer(uint32_t start_t) /* Enable clock for ITIM peripheral */ clock_enable_peripheral(CGC_OFFSET_TIMER, CGC_TIMER_MASK, - CGC_MODE_RUN | CGC_MODE_SLEEP); + CGC_MODE_RUN | CGC_MODE_SLEEP); /* init tick & event timer first */ - init_hw_timer(ITIM_SYSTEM_NO, ITIM_SOURCE_CLOCK_APB2); + init_hw_timer(ITIM_SYSTEM_NO, ITIM_SOURCE_CLOCK_APB2); init_hw_timer(ITIM_EVENT_NO, ITIM_SOURCE_CLOCK_32K); /* Set initial prescaler */ diff --git a/chip/npcx/hwtimer_chip.h b/chip/npcx/hwtimer_chip.h index 987f3b52bd..7964d9619b 100644 --- a/chip/npcx/hwtimer_chip.h +++ b/chip/npcx/hwtimer_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,14 +9,14 @@ #define __CROS_EC_HWTIMER_CHIP_H /* Use ITIM32 as main hardware timer */ -#define TICK_ITIM32_MAX_CNT 0xFFFFFFFF +#define TICK_ITIM32_MAX_CNT 0xFFFFFFFF /* Maximum deadline of event */ -#define EVT_MAX_EXPIRED_US TICK_ITIM32_MAX_CNT +#define EVT_MAX_EXPIRED_US TICK_ITIM32_MAX_CNT /* Clock source for ITIM16 */ enum ITIM_SOURCE_CLOCK_T { ITIM_SOURCE_CLOCK_APB2 = 0, - ITIM_SOURCE_CLOCK_32K = 1, + ITIM_SOURCE_CLOCK_32K = 1, }; /** diff --git a/chip/npcx/i2c-npcx5.c b/chip/npcx/i2c-npcx5.c index 89b5ec8072..ef04b447c6 100644 --- a/chip/npcx/i2c-npcx5.c +++ b/chip/npcx/i2c-npcx5.c @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -32,7 +32,7 @@ void i2c_select_port(int port) /* Select IO pins for multi-ports I2C controllers */ UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB0SEL, - (port == NPCX_I2C_PORT0_1)); + (port == NPCX_I2C_PORT0_1)); } int i2c_is_raw_mode(int port) diff --git a/chip/npcx/i2c-npcx7.c b/chip/npcx/i2c-npcx7.c index 3f27aff49e..427b9cae9f 100644 --- a/chip/npcx/i2c-npcx7.c +++ b/chip/npcx/i2c-npcx7.c @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -37,13 +37,13 @@ void i2c_select_port(int port) /* Select I2C ports for the same controller */ else if (port <= NPCX_I2C_PORT4_1) { UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB4SEL, - (port == NPCX_I2C_PORT4_1)); + (port == NPCX_I2C_PORT4_1)); } else if (port <= NPCX_I2C_PORT5_1) { UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB5SEL, - (port == NPCX_I2C_PORT5_1)); + (port == NPCX_I2C_PORT5_1)); } else { UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB6SEL, - (port == NPCX_I2C_PORT6_1)); + (port == NPCX_I2C_PORT6_1)); } } @@ -52,7 +52,7 @@ int i2c_is_raw_mode(int port) int group, bit; if (port == NPCX_I2C_PORT4_1 || port == NPCX_I2C_PORT5_1 || - port == NPCX_I2C_PORT6_1) { + port == NPCX_I2C_PORT6_1) { group = 6; bit = 7 - (port - NPCX_I2C_PORT4_1) / 2; } else { diff --git a/chip/npcx/i2c-npcx9.c b/chip/npcx/i2c-npcx9.c index b1b16a3198..427b9cae9f 120000..100644 --- a/chip/npcx/i2c-npcx9.c +++ b/chip/npcx/i2c-npcx9.c @@ -1 +1,70 @@ -i2c-npcx7.c
\ No newline at end of file +/* Copyright 2017 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* I2C module driver depends on chip series for Chrome EC */ + +#include "common.h" +#include "i2c.h" +#include "i2c_chip.h" +#include "registers.h" +#include "util.h" + +/*****************************************************************************/ +/* IC specific low-level driver depends on chip series */ + +int i2c_port_to_controller(int port) +{ + if (port < 0 || port >= I2C_PORT_COUNT) + return -1; + + if (port <= NPCX_I2C_PORT3_0) + return port; +#ifndef NPCX_PSL_MODE_SUPPORT + else if (port == NPCX_I2C_PORT4_0) + return 4; +#endif + else /* If port >= NPCX_I2C_PORT4_1 */ + return 4 + ((port - NPCX_I2C_PORT4_1 + 1) / 2); +} + +void i2c_select_port(int port) +{ + /* Only I2C 4/5/6 have multiple ports in series npcx7 */ + if (port <= NPCX_I2C_PORT3_0 || port >= NPCX_I2C_PORT7_0) + return; + /* Select I2C ports for the same controller */ + else if (port <= NPCX_I2C_PORT4_1) { + UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB4SEL, + (port == NPCX_I2C_PORT4_1)); + } else if (port <= NPCX_I2C_PORT5_1) { + UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB5SEL, + (port == NPCX_I2C_PORT5_1)); + } else { + UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB6SEL, + (port == NPCX_I2C_PORT6_1)); + } +} + +int i2c_is_raw_mode(int port) +{ + int group, bit; + + if (port == NPCX_I2C_PORT4_1 || port == NPCX_I2C_PORT5_1 || + port == NPCX_I2C_PORT6_1) { + group = 6; + bit = 7 - (port - NPCX_I2C_PORT4_1) / 2; + } else { + group = 2; + if (port <= NPCX_I2C_PORT3_0) + bit = 2 * port; + else + bit = I2C_PORT_COUNT - port; + } + + if (IS_BIT_SET(NPCX_DEVALT(group), bit)) + return 0; + else + return 1; +} diff --git a/chip/npcx/i2c.c b/chip/npcx/i2c.c index a7c389f1b3..ebfba26c58 100644 --- a/chip/npcx/i2c.c +++ b/chip/npcx/i2c.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -24,8 +24,8 @@ #define CPRINTF(...) #else #define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args) #endif /* Timeout for device should be available after reset (SMBus spec. unit:ms) */ @@ -41,54 +41,54 @@ * I2C module that supports FIFO mode has 32 bytes Tx FIFO and * 32 bytes Rx FIFO. */ -#define NPCX_I2C_FIFO_MAX_SIZE 32 +#define NPCX_I2C_FIFO_MAX_SIZE 32 /* Macro functions of I2C */ #define I2C_START(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_START) -#define I2C_STOP(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_STOP) -#define I2C_NACK(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_ACK) +#define I2C_STOP(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_STOP) +#define I2C_NACK(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_ACK) /* I2C module automatically stall bus after sending peripheral address */ #define I2C_STALL(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_STASTRE) #define I2C_WRITE_BYTE(ctrl, data) (NPCX_SMBSDA(ctrl) = data) -#define I2C_READ_BYTE(ctrl, data) (data = NPCX_SMBSDA(ctrl)) +#define I2C_READ_BYTE(ctrl, data) (data = NPCX_SMBSDA(ctrl)) #define I2C_TX_FIFO_OCCUPIED(ctrl) (NPCX_SMBTXF_STS(ctrl) & 0x3F) #define I2C_TX_FIFO_AVAILABLE(ctrl) \ - (NPCX_I2C_FIFO_MAX_SIZE - I2C_TX_FIFO_OCCUPIED(ctrl)) + (NPCX_I2C_FIFO_MAX_SIZE - I2C_TX_FIFO_OCCUPIED(ctrl)) #define I2C_RX_FIFO_OCCUPIED(ctrl) (NPCX_SMBRXF_STS(ctrl) & 0x3F) #define I2C_RX_FIFO_AVAILABLE(ctrl) \ - (NPCX_I2C_FIFO_MAX_SIZE - I2C_RX_FIFO_OCCUPIED(ctrl)) + (NPCX_I2C_FIFO_MAX_SIZE - I2C_RX_FIFO_OCCUPIED(ctrl)) /* Drive the SCL signal to low */ -#define I2C_SCL_STALL(ctrl) \ - (NPCX_SMBCTL3(ctrl) = \ - (NPCX_SMBCTL3(ctrl) & ~BIT(NPCX_SMBCTL3_SCL_LVL)) | \ - BIT(NPCX_SMBCTL3_SDA_LVL)) +#define I2C_SCL_STALL(ctrl) \ + (NPCX_SMBCTL3(ctrl) = \ + (NPCX_SMBCTL3(ctrl) & ~BIT(NPCX_SMBCTL3_SCL_LVL)) | \ + BIT(NPCX_SMBCTL3_SDA_LVL)) /* * Release the SCL signal to be pulled up to high level. * Note: The SCL might be still driven low either by I2C module or external * devices connected to ths bus. */ -#define I2C_SCL_FREE(ctrl) \ - (NPCX_SMBCTL3(ctrl) |= BIT(NPCX_SMBCTL3_SCL_LVL) | \ - BIT(NPCX_SMBCTL3_SDA_LVL)) +#define I2C_SCL_FREE(ctrl) \ + (NPCX_SMBCTL3(ctrl) |= BIT(NPCX_SMBCTL3_SCL_LVL) | \ + BIT(NPCX_SMBCTL3_SDA_LVL)) /* Error values that functions can return */ enum smb_error { - SMB_OK = 0, /* No error */ - SMB_CH_OCCUPIED, /* Channel is already occupied */ - SMB_MEM_POOL_INIT_ERROR, /* Memory pool initialization error */ - SMB_BUS_FREQ_ERROR, /* SMbus freq was not valid */ - SMB_INVLAID_REGVALUE, /* Invalid SMbus register value */ - SMB_UNEXIST_CH_ERROR, /* Channel does not exist */ - SMB_NO_SUPPORT_PTL, /* Not support SMBus Protocol */ - SMB_BUS_ERROR, /* Encounter bus error */ - SMB_NO_ADDRESS_MATCH, /* No peripheral address match */ - /* (Controller Mode) */ - SMB_READ_DATA_ERROR, /* Read data for SDA error */ - SMB_READ_OVERFLOW_ERROR, /* Read data over than we predict */ - SMB_TIMEOUT_ERROR, /* Timeout expired */ - SMB_MODULE_ISBUSY, /* Module is occupied by other device */ - SMB_BUS_BUSY, /* SMBus is occupied by other device */ + SMB_OK = 0, /* No error */ + SMB_CH_OCCUPIED, /* Channel is already occupied */ + SMB_MEM_POOL_INIT_ERROR, /* Memory pool initialization error */ + SMB_BUS_FREQ_ERROR, /* SMbus freq was not valid */ + SMB_INVLAID_REGVALUE, /* Invalid SMbus register value */ + SMB_UNEXIST_CH_ERROR, /* Channel does not exist */ + SMB_NO_SUPPORT_PTL, /* Not support SMBus Protocol */ + SMB_BUS_ERROR, /* Encounter bus error */ + SMB_NO_ADDRESS_MATCH, /* No peripheral address match */ + /* (Controller Mode) */ + SMB_READ_DATA_ERROR, /* Read data for SDA error */ + SMB_READ_OVERFLOW_ERROR, /* Read data over than we predict */ + SMB_TIMEOUT_ERROR, /* Timeout expired */ + SMB_MODULE_ISBUSY, /* Module is occupied by other device */ + SMB_BUS_BUSY, /* SMBus is occupied by other device */ }; /* @@ -108,18 +108,18 @@ enum smb_oper_state_t { /* I2C controller state data */ struct i2c_status { - int flags; /* Flags (I2C_XFER_*) */ - const uint8_t *tx_buf; /* Entry pointer of transmit buffer */ - uint8_t *rx_buf; /* Entry pointer of receive buffer */ - uint16_t sz_txbuf; /* Size of Tx buffer in bytes */ - uint16_t sz_rxbuf; /* Size of rx buffer in bytes */ - uint16_t idx_buf; /* Current index of Tx/Rx buffer */ - uint16_t addr_flags;/* Target address */ - enum smb_oper_state_t oper_state;/* Smbus operation state */ - enum smb_error err_code; /* Error code */ - int task_waiting; /* Task waiting on controller */ - uint32_t timeout_us;/* Transaction timeout */ - uint16_t kbps; /* Speed */ + int flags; /* Flags (I2C_XFER_*) */ + const uint8_t *tx_buf; /* Entry pointer of transmit buffer */ + uint8_t *rx_buf; /* Entry pointer of receive buffer */ + uint16_t sz_txbuf; /* Size of Tx buffer in bytes */ + uint16_t sz_rxbuf; /* Size of rx buffer in bytes */ + uint16_t idx_buf; /* Current index of Tx/Rx buffer */ + uint16_t addr_flags; /* Target address */ + enum smb_oper_state_t oper_state; /* Smbus operation state */ + enum smb_error err_code; /* Error code */ + int task_waiting; /* Task waiting on controller */ + uint32_t timeout_us; /* Transaction timeout */ + uint16_t kbps; /* Speed */ }; /* I2C controller state data array */ static struct i2c_status i2c_stsobjs[I2C_CONTROLLER_COUNT]; @@ -127,27 +127,29 @@ static struct i2c_status i2c_stsobjs[I2C_CONTROLLER_COUNT]; /* I2C timing setting */ struct i2c_timing { uint8_t clock; /* I2C source clock. (Unit: MHz)*/ - uint8_t HLDT; /* I2C hold-time. (Unit: clocks) */ - uint8_t k1; /* k1 = SCL low-time (Unit: clocks) */ - uint8_t k2; /* k2 = SCL high-time (Unit: clocks) */ + uint8_t HLDT; /* I2C hold-time. (Unit: clocks) */ + uint8_t k1; /* k1 = SCL low-time (Unit: clocks) */ + uint8_t k2; /* k2 = SCL high-time (Unit: clocks) */ }; /* I2C timing setting array of 400K & 1M Hz */ static const struct i2c_timing i2c_400k_timings[] = { - {20, 7, 32, 22}, - {15, 7, 24, 18},}; + { 20, 7, 32, 22 }, + { 15, 7, 24, 18 }, +}; const unsigned int i2c_400k_timing_used = ARRAY_SIZE(i2c_400k_timings); static const struct i2c_timing i2c_1m_timings[] = { - {20, 7, 16, 10}, - {15, 7, 14, 10},}; + { 20, 7, 16, 10 }, + { 15, 7, 14, 10 }, +}; const unsigned int i2c_1m_timing_used = ARRAY_SIZE(i2c_1m_timings); /* IRQ for each port */ const uint32_t i2c_irqs[I2C_CONTROLLER_COUNT] = { - NPCX_IRQ_SMB1, NPCX_IRQ_SMB2, NPCX_IRQ_SMB3, NPCX_IRQ_SMB4, + NPCX_IRQ_SMB1, NPCX_IRQ_SMB2, NPCX_IRQ_SMB3, NPCX_IRQ_SMB4, #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7 - NPCX_IRQ_SMB5, NPCX_IRQ_SMB6, NPCX_IRQ_SMB7, NPCX_IRQ_SMB8, + NPCX_IRQ_SMB5, NPCX_IRQ_SMB6, NPCX_IRQ_SMB7, NPCX_IRQ_SMB8, #endif }; BUILD_ASSERT(ARRAY_SIZE(i2c_irqs) == I2C_CONTROLLER_COUNT); @@ -198,8 +200,8 @@ static void i2c_abort_data(int controller) SET_BIT(NPCX_SMBST(controller), NPCX_SMBST_NEGACK); /* Wait till STOP condition is generated */ - if (i2c_wait_stop_completed(controller, I2C_MAX_TIMEOUT) - != EC_SUCCESS) { + if (i2c_wait_stop_completed(controller, I2C_MAX_TIMEOUT) != + EC_SUCCESS) { cprintf(CC_I2C, "Abort i2c %02x fail!\n", controller); /* Clear BB (BUS BUSY) bit */ SET_BIT(NPCX_SMBCST(controller), NPCX_SMBCST_BB); @@ -219,8 +221,9 @@ static int i2c_reset(int controller) while (--timeout) { /* WAIT FOR SCL & SDA IS HIGH */ - if (IS_BIT_SET(NPCX_SMBCTL3(controller), NPCX_SMBCTL3_SCL_LVL) - && IS_BIT_SET(NPCX_SMBCTL3(controller), NPCX_SMBCTL3_SDA_LVL)) + if (IS_BIT_SET(NPCX_SMBCTL3(controller), + NPCX_SMBCTL3_SCL_LVL) && + IS_BIT_SET(NPCX_SMBCTL3(controller), NPCX_SMBCTL3_SDA_LVL)) break; msleep(1); } @@ -306,9 +309,8 @@ static void i2c_fifo_write_data(int controller) } for (i = 0; i < len; i++) { I2C_WRITE_BYTE(controller, - p_status->tx_buf[p_status->idx_buf++]); - CPRINTF("%02x ", - p_status->tx_buf[p_status->idx_buf - 1]); + p_status->tx_buf[p_status->idx_buf++]); + CPRINTF("%02x ", p_status->tx_buf[p_status->idx_buf - 1]); } CPRINTF("\n"); } @@ -355,7 +357,7 @@ enum smb_error i2c_controller_transaction(int controller) * is set simultaneously. */ if (p_status->sz_rxbuf == 1 && - (p_status->flags & I2C_XFER_STOP)) { + (p_status->flags & I2C_XFER_STOP)) { /* * Since SCL is released after reading last * byte from previous transaction, adding a @@ -375,30 +377,30 @@ enum smb_error i2c_controller_transaction(int controller) } } else cprintf(CC_I2C, "Unexpected i2c state machine! %d\n", - p_status->oper_state); + p_status->oper_state); if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) { if (p_status->sz_rxbuf > 0) { if (p_status->sz_rxbuf > NPCX_I2C_FIFO_MAX_SIZE) { /* Set RX threshold = FIFO_MAX_SIZE */ SET_FIELD(NPCX_SMBRXF_CTL(controller), - NPCX_SMBRXF_CTL_RX_THR, - NPCX_I2C_FIFO_MAX_SIZE); + NPCX_SMBRXF_CTL_RX_THR, + NPCX_I2C_FIFO_MAX_SIZE); } else { /* * set RX threshold = remaining data bytes * (it should be <= FIFO_MAX_SIZE) */ SET_FIELD(NPCX_SMBRXF_CTL(controller), - NPCX_SMBRXF_CTL_RX_THR, - p_status->sz_rxbuf); + NPCX_SMBRXF_CTL_RX_THR, + p_status->sz_rxbuf); /* * Set LAST bit generate the NACK at the * last byte of the data group in FIFO */ if (p_status->flags & I2C_XFER_STOP) { SET_BIT(NPCX_SMBRXF_CTL(controller), - NPCX_SMBRXF_CTL_LAST); + NPCX_SMBRXF_CTL_LAST); } } @@ -412,7 +414,7 @@ enum smb_error i2c_controller_transaction(int controller) /* Generate a START condition */ if (p_status->oper_state == SMB_CONTROLLER_START || - p_status->oper_state == SMB_REPEAT_START) { + p_status->oper_state == SMB_REPEAT_START) { I2C_START(controller); CPUTS("ST"); } @@ -421,8 +423,8 @@ enum smb_error i2c_controller_transaction(int controller) task_enable_irq(i2c_irqs[controller]); /* Wait for transfer complete or timeout */ - events = task_wait_event_mask(TASK_EVENT_I2C_IDLE, - p_status->timeout_us); + events = + task_wait_event_mask(TASK_EVENT_I2C_IDLE, p_status->timeout_us); /* Disable event and error interrupts */ task_disable_irq(i2c_irqs[controller]); @@ -452,8 +454,9 @@ enum smb_error i2c_controller_transaction(int controller) i2c_recovery(controller, p_status); /* Wait till STOP condition is generated for normal transaction */ - if (p_status->err_code == SMB_OK && i2c_wait_stop_completed(controller, - I2C_MIN_TIMEOUT) != EC_SUCCESS) { + if (p_status->err_code == SMB_OK && + i2c_wait_stop_completed(controller, I2C_MIN_TIMEOUT) != + EC_SUCCESS) { cprintf(CC_I2C, "STOP fail! scl %02x is held by slave device!\n", controller); @@ -476,7 +479,7 @@ void i2c_done(int controller) /* Clear RXF_TXE bit (RX FIFO full/TX FIFO empty) */ if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) NPCX_SMBFIF_CTS(controller) = - BIT(NPCX_SMBFIF_CTS_RXF_TXE); + BIT(NPCX_SMBFIF_CTS_RXF_TXE); /* Clear SDAST by writing mock byte */ I2C_WRITE_BYTE(controller, 0xFF); @@ -485,8 +488,9 @@ void i2c_done(int controller) /* Set error code */ p_status->err_code = SMB_OK; /* Set SMB status if we need stall bus */ - p_status->oper_state = (p_status->flags & I2C_XFER_STOP) - ? SMB_IDLE : SMB_WRITE_SUSPEND; + p_status->oper_state = (p_status->flags & I2C_XFER_STOP) ? + SMB_IDLE : + SMB_WRITE_SUSPEND; /* * Disable interrupt for i2c controller stall SCL * and forbid SDAST generate interrupt @@ -540,7 +544,7 @@ static void i2c_handle_receive(int controller) /* Read to buf. Skip last byte if meet SMB_FAKE_READ_OPER */ if (p_status->oper_state == SMB_FAKE_READ_OPER && - p_status->idx_buf == (p_status->sz_rxbuf - 1)) + p_status->idx_buf == (p_status->sz_rxbuf - 1)) p_status->idx_buf++; else p_status->rx_buf[p_status->idx_buf++] = data; @@ -548,8 +552,9 @@ static void i2c_handle_receive(int controller) /* last byte is read - end of transaction */ if (p_status->idx_buf == p_status->sz_rxbuf) { /* Set current status */ - p_status->oper_state = (p_status->flags & I2C_XFER_STOP) - ? SMB_IDLE : SMB_READ_SUSPEND; + p_status->oper_state = (p_status->flags & I2C_XFER_STOP) ? + SMB_IDLE : + SMB_READ_SUSPEND; /* Set error code */ p_status->err_code = SMB_OK; /* Notify upper layer of missing data */ @@ -623,35 +628,33 @@ static void i2c_fifo_handle_receive(int controller) if (remaining_bytes > 0) { if (remaining_bytes > NPCX_I2C_FIFO_MAX_SIZE) { SET_FIELD(NPCX_SMBRXF_CTL(controller), - NPCX_SMBRXF_CTL_RX_THR, - NPCX_I2C_FIFO_MAX_SIZE); + NPCX_SMBRXF_CTL_RX_THR, + NPCX_I2C_FIFO_MAX_SIZE); } else { SET_FIELD(NPCX_SMBRXF_CTL(controller), - NPCX_SMBRXF_CTL_RX_THR, - remaining_bytes); + NPCX_SMBRXF_CTL_RX_THR, + remaining_bytes); if (p_status->flags & I2C_XFER_STOP) { SET_BIT(NPCX_SMBRXF_CTL(controller), - NPCX_SMBRXF_CTL_LAST); + NPCX_SMBRXF_CTL_LAST); CPRINTS("-FGNA"); } } - } i2c_stall_bus(controller, 0); - } /* last byte is read - end of transaction */ if (p_status->idx_buf == p_status->sz_rxbuf) { /* Set current status */ - p_status->oper_state = (p_status->flags & I2C_XFER_STOP) - ? SMB_IDLE : SMB_READ_SUSPEND; + p_status->oper_state = (p_status->flags & I2C_XFER_STOP) ? + SMB_IDLE : + SMB_READ_SUSPEND; /* Set error code */ p_status->err_code = SMB_OK; /* Notify upper layer of missing data */ task_set_event(p_status->task_waiting, TASK_EVENT_I2C_IDLE); CPUTS("-END"); } - } static void i2c_handle_sda_irq(int controller) @@ -660,10 +663,10 @@ static void i2c_handle_sda_irq(int controller) uint8_t addr_8bit = I2C_STRIP_FLAGS(p_status->addr_flags) << 1; /* 1 Issue Start is successful ie. write address byte */ - if (p_status->oper_state == SMB_CONTROLLER_START - || p_status->oper_state == SMB_REPEAT_START) { + if (p_status->oper_state == SMB_CONTROLLER_START || + p_status->oper_state == SMB_REPEAT_START) { /* Prepare address byte */ - if (p_status->sz_txbuf == 0) {/* Receive mode */ + if (p_status->sz_txbuf == 0) { /* Receive mode */ p_status->oper_state = SMB_READ_OPER; /* * Receiving one or zero bytes - stall bus after @@ -676,7 +679,7 @@ static void i2c_handle_sda_irq(int controller) /* Write the address to the bus R bit*/ I2C_WRITE_BYTE(controller, (addr_8bit | 0x1)); CPRINTS("-ARR-0x%02x", addr_8bit); - } else {/* Transmit mode */ + } else { /* Transmit mode */ p_status->oper_state = SMB_WRITE_OPER; /* Write the address to the bus W bit*/ I2C_WRITE_BYTE(controller, addr_8bit); @@ -720,14 +723,13 @@ static void i2c_handle_sda_irq(int controller) * in the SMBnTXF_CTL register. */ if (p_status->sz_rxbuf == 1 && - (p_status->flags & I2C_XFER_STOP) && - !IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) { + (p_status->flags & I2C_XFER_STOP) && + !IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) { I2C_NACK(controller); CPUTS("-GNA"); } /* Write the address to the bus R bit*/ - I2C_WRITE_BYTE(controller, - (addr_8bit | 0x1)); + I2C_WRITE_BYTE(controller, (addr_8bit | 0x1)); CPUTS("-ARR"); } } @@ -749,7 +751,7 @@ static void i2c_handle_sda_irq(int controller) * operation) */ else if (p_status->oper_state == SMB_READ_OPER || - p_status->oper_state == SMB_FAKE_READ_OPER) { + p_status->oper_state == SMB_FAKE_READ_OPER) { if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) i2c_fifo_handle_receive(controller); else @@ -826,7 +828,7 @@ static void i2c_controller_int_handler(int controller) * register. */ else if ((p_status->flags & I2C_XFER_STOP) && - !IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) { + !IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) { I2C_NACK(controller); } @@ -840,9 +842,10 @@ static void i2c_controller_int_handler(int controller) #if DEBUG_I2C /* SDAST still issued with unexpected state machine */ if (IS_BIT_SET(NPCX_SMBST(controller), NPCX_SMBST_SDAST) && - p_status->oper_state != SMB_WRITE_SUSPEND) { + p_status->oper_state != SMB_WRITE_SUSPEND) { cprints(CC_I2C, "i2c %d unknown state %d, error %d\n", - controller, p_status->oper_state, p_status->err_code); + controller, p_status->oper_state, + p_status->err_code); } #endif } @@ -858,15 +861,39 @@ void handle_interrupt(int controller) i2c_controller_int_handler(controller); } -static void i2c0_interrupt(void) { handle_interrupt(0); } -static void i2c1_interrupt(void) { handle_interrupt(1); } -static void i2c2_interrupt(void) { handle_interrupt(2); } -static void i2c3_interrupt(void) { handle_interrupt(3); } +static void i2c0_interrupt(void) +{ + handle_interrupt(0); +} +static void i2c1_interrupt(void) +{ + handle_interrupt(1); +} +static void i2c2_interrupt(void) +{ + handle_interrupt(2); +} +static void i2c3_interrupt(void) +{ + handle_interrupt(3); +} #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7 -static void i2c4_interrupt(void) { handle_interrupt(4); } -static void i2c5_interrupt(void) { handle_interrupt(5); } -static void i2c6_interrupt(void) { handle_interrupt(6); } -static void i2c7_interrupt(void) { handle_interrupt(7); } +static void i2c4_interrupt(void) +{ + handle_interrupt(4); +} +static void i2c5_interrupt(void) +{ + handle_interrupt(5); +} +static void i2c6_interrupt(void) +{ + handle_interrupt(6); +} +static void i2c7_interrupt(void) +{ + handle_interrupt(7); +} #endif DECLARE_IRQ(NPCX_IRQ_SMB1, i2c0_interrupt, 4); @@ -892,14 +919,12 @@ void i2c_set_timeout(int port, uint32_t timeout) return; /* Param is port, but timeout is stored by-controller. */ - i2c_stsobjs[ctrl].timeout_us = - timeout ? timeout : I2C_TIMEOUT_DEFAULT_US; + i2c_stsobjs[ctrl].timeout_us = timeout ? timeout : + I2C_TIMEOUT_DEFAULT_US; } -int chip_i2c_xfer(const int port, - const uint16_t addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags) +int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out, + int out_size, uint8_t *in, int in_size, int flags) { volatile struct i2c_status *p_status; int ctrl = i2c_port_to_controller(port); @@ -921,23 +946,23 @@ int chip_i2c_xfer(const int port, i2c_select_port(port); /* Copy data to controller struct */ - p_status->flags = flags; - p_status->tx_buf = out; - p_status->sz_txbuf = out_size; - p_status->rx_buf = in; - p_status->sz_rxbuf = in_size; + p_status->flags = flags; + p_status->tx_buf = out; + p_status->sz_txbuf = out_size; + p_status->rx_buf = in; + p_status->sz_rxbuf = in_size; p_status->addr_flags = addr_flags; /* Reset index & error */ - p_status->idx_buf = 0; - p_status->err_code = SMB_OK; + p_status->idx_buf = 0; + p_status->err_code = SMB_OK; /* Make sure we're in a good state to start */ if ((flags & I2C_XFER_START) && - /* Ignore busy bus for repeated start */ - p_status->oper_state != SMB_WRITE_SUSPEND && - (i2c_bus_busy(ctrl) - || (i2c_get_line_levels(port) != I2C_LINE_IDLE))) { + /* Ignore busy bus for repeated start */ + p_status->oper_state != SMB_WRITE_SUSPEND && + (i2c_bus_busy(ctrl) || + (i2c_get_line_levels(port) != I2C_LINE_IDLE))) { int ret; /* Attempt to unwedge the i2c port */ @@ -974,7 +999,7 @@ int chip_i2c_xfer(const int port, int i2c_get_line_levels(int port) { return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) | - (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); + (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); } int i2c_raw_get_scl(int port) @@ -989,8 +1014,9 @@ int i2c_raw_get_scl(int port) if (i2c_is_raw_mode(port)) return gpio_get_level(g); else - return IS_BIT_SET(NPCX_SMBCTL3( - i2c_port_to_controller(port)), NPCX_SMBCTL3_SCL_LVL); + return IS_BIT_SET( + NPCX_SMBCTL3(i2c_port_to_controller(port)), + NPCX_SMBCTL3_SCL_LVL); } /* If no SCL pin defined for this port, then return 1 to appear idle */ @@ -1009,11 +1035,11 @@ int i2c_raw_get_sda(int port) if (i2c_is_raw_mode(port)) return gpio_get_level(g); else - return IS_BIT_SET(NPCX_SMBCTL3( - i2c_port_to_controller(port)), NPCX_SMBCTL3_SDA_LVL); + return IS_BIT_SET( + NPCX_SMBCTL3(i2c_port_to_controller(port)), + NPCX_SMBCTL3_SDA_LVL); } - /* If no SDA pin defined for this port, then return 1 to appear idle */ return 1; } @@ -1032,8 +1058,8 @@ static void i2c_port_set_freq(const int ctrl, const int bus_freq_kbps) * SMB0/1/4/5/6/7 use APB3 clock * SMB2/3 use APB2 clock */ - freq = (ctrl < 2 || ctrl > 3) ? - clock_get_apb3_freq() : clock_get_apb2_freq(); + freq = (ctrl < 2 || ctrl > 3) ? clock_get_apb3_freq() : + clock_get_apb2_freq(); #else /* CHIP_FAMILY_NPCX5 */ /* * SMB0/1 use core clock @@ -1051,7 +1077,7 @@ static void i2c_port_set_freq(const int ctrl, const int bus_freq_kbps) * fSCL = fCLK / (4*SCLFRQ) * SCLFRQ = ceil(fCLK/(4*fSCL)) */ - scl_freq = DIV_ROUND_UP(freq, bus_freq_kbps*4000); /* Unit in bps */ + scl_freq = DIV_ROUND_UP(freq, bus_freq_kbps * 4000); /* Unit in bps */ /* Normal mode if I2C freq is under 100kHz */ if (bus_freq_kbps <= 100) { @@ -1089,19 +1115,19 @@ static void i2c_port_set_freq(const int ctrl, const int bus_freq_kbps) } for (j = 0; j < i2c_timing_used; j++, pTiming++) { - if (pTiming->clock == (freq/SECOND)) { + if (pTiming->clock == (freq / SECOND)) { i2c_stsobjs[ctrl].kbps = bus_freq_kbps; /* Set SCLH(L)T and hold-time */ - NPCX_SMBSCLLT(ctrl) = pTiming->k1/2; - NPCX_SMBSCLHT(ctrl) = pTiming->k2/2; - SET_FIELD(NPCX_SMBCTL4(ctrl), - NPCX_SMBCTL4_HLDT_FIELD, pTiming->HLDT); + NPCX_SMBSCLLT(ctrl) = pTiming->k1 / 2; + NPCX_SMBSCLHT(ctrl) = pTiming->k2 / 2; + SET_FIELD(NPCX_SMBCTL4(ctrl), NPCX_SMBCTL4_HLDT_FIELD, + pTiming->HLDT); break; } } if (j == i2c_timing_used) - cprints(CC_I2C, "Error: I2C %d: src clk %d not supported", - ctrl, freq / SECOND); + cprints(CC_I2C, "Error: I2C %d: src clk %d not supported", ctrl, + freq / SECOND); } /* Hooks */ @@ -1187,10 +1213,10 @@ void i2c_init(void) /* Enable clock for I2C peripheral */ clock_enable_peripheral(CGC_OFFSET_I2C, CGC_I2C_MASK, - CGC_MODE_RUN | CGC_MODE_SLEEP); + CGC_MODE_RUN | CGC_MODE_SLEEP); #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7 clock_enable_peripheral(CGC_OFFSET_I2C2, CGC_I2C_MASK2, - CGC_MODE_RUN | CGC_MODE_SLEEP); + CGC_MODE_RUN | CGC_MODE_SLEEP); #endif /* Set I2C freq */ diff --git a/chip/npcx/i2c_chip.h b/chip/npcx/i2c_chip.h index 014e6cddf2..d1a7cf6851 100644 --- a/chip/npcx/i2c_chip.h +++ b/chip/npcx/i2c_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/npcx/keyboard_raw.c b/chip/npcx/keyboard_raw.c index 5d73765bff..cb2be7911e 100644 --- a/chip/npcx/keyboard_raw.c +++ b/chip/npcx/keyboard_raw.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -20,7 +20,7 @@ void keyboard_raw_init(void) { /* Enable clock for KBS peripheral */ clock_enable_peripheral(CGC_OFFSET_KBS, CGC_KBS_MASK, - CGC_MODE_RUN | CGC_MODE_SLEEP); + CGC_MODE_RUN | CGC_MODE_SLEEP); /* Ensure top-level interrupt is disabled */ keyboard_raw_enable_interrupt(0); @@ -63,7 +63,7 @@ void keyboard_raw_init(void) NPCX_WKEN(MIWU_TABLE_WKKEY, MIWU_GROUP_WKKEY) = 0xFF; /* Select high to low transition (falling edge) */ - NPCX_WKEDG(MIWU_TABLE_WKKEY, MIWU_GROUP_WKKEY) = 0xFF; + NPCX_WKEDG(MIWU_TABLE_WKKEY, MIWU_GROUP_WKKEY) = 0xFF; /* Enable interrupt of WK KBS */ keyboard_raw_enable_interrupt(1); diff --git a/chip/npcx/lct.c b/chip/npcx/lct.c index e23fa3bf6a..19568cac44 100644 --- a/chip/npcx/lct.c +++ b/chip/npcx/lct.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -13,10 +13,10 @@ #include "timer.h" #include "util.h" -#define LCT_CLK_ENABLE_DELAY_USEC 150 +#define LCT_CLK_ENABLE_DELAY_USEC 150 -#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) void npcx_lct_sel_power_src(enum NPCX_LCT_PWR_SRC pwr_src) { @@ -93,7 +93,6 @@ void npcx_lct_config(int seconds, int psl_ena, int int_ena) if (int_ena) SET_BIT(NPCX_LCTCONT, NPCX_LCTCONT_EVEN); - } uint32_t npcx_lct_get_time(void) @@ -102,21 +101,17 @@ uint32_t npcx_lct_get_time(void) uint8_t week, day, hour, minute; do { - week = NPCX_LCTWEEK; - day = NPCX_LCTDAY; - hour = NPCX_LCTHOUR; + week = NPCX_LCTWEEK; + day = NPCX_LCTDAY; + hour = NPCX_LCTHOUR; minute = NPCX_LCTMINUTE; second = NPCX_LCTSECOND; - } while (week != NPCX_LCTWEEK || - day != NPCX_LCTDAY || - hour != NPCX_LCTHOUR || - minute != NPCX_LCTMINUTE || + } while (week != NPCX_LCTWEEK || day != NPCX_LCTDAY || + hour != NPCX_LCTHOUR || minute != NPCX_LCTMINUTE || second != NPCX_LCTSECOND); - second += minute * SECS_PER_MINUTE + - hour * SECS_PER_HOUR + - day * SECS_PER_DAY + - week * SECS_PER_WEEK; + second += minute * SECS_PER_MINUTE + hour * SECS_PER_HOUR + + day * SECS_PER_DAY + week * SECS_PER_WEEK; return second; } @@ -148,7 +143,7 @@ static void npcx_lct_init(void) DECLARE_HOOK(HOOK_INIT, npcx_lct_init, HOOK_PRIO_DEFAULT); #ifdef CONFIG_CMD_RTC_ALARM -static int command_lctalarm(int argc, char **argv) +static int command_lctalarm(int argc, const char **argv) { char *e; int seconds; @@ -164,9 +159,9 @@ static int command_lctalarm(int argc, char **argv) npcx_lct_config(seconds, 0, 1); task_disable_irq(NPCX_IRQ_LCT_WKINTF_2); /* Enable wake-up input sources & clear pending bit */ - NPCX_WKPCL(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK; + NPCX_WKPCL(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK; NPCX_WKINEN(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK; - NPCX_WKEN(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK; + NPCX_WKEN(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK; task_enable_irq(NPCX_IRQ_LCT_WKINTF_2); npcx_lct_enable(1); diff --git a/chip/npcx/lct_chip.h b/chip/npcx/lct_chip.h index 197c189f43..8b4ee804cf 100644 --- a/chip/npcx/lct_chip.h +++ b/chip/npcx/lct_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,10 +10,7 @@ #define NPCX_LCT_MAX (16 * SECS_PER_WEEK - 1) -enum NPCX_LCT_PWR_SRC { - NPCX_LCT_PWR_SRC_VCC1, - NPCX_LCT_PWR_SRC_VSBY -}; +enum NPCX_LCT_PWR_SRC { NPCX_LCT_PWR_SRC_VCC1, NPCX_LCT_PWR_SRC_VSBY }; void npcx_lct_config(int seconds, int psl_ena, int int_ena); void npcx_lct_enable(uint8_t enable); @@ -25,4 +22,4 @@ int npcx_lct_is_event_set(void); /* return the current time of LCT in second */ uint32_t npcx_lct_get_time(void); -#endif /* __CROS_EC_LCT_CHIP_H */ +#endif /* __CROS_EC_LCT_CHIP_H */ diff --git a/chip/npcx/lfw/ec_lfw.h b/chip/npcx/lfw/ec_lfw.h index 88c0a9ed83..3b7e4da459 100644 --- a/chip/npcx/lfw/ec_lfw.h +++ b/chip/npcx/lfw/ec_lfw.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index ec99df9eb3..48e094f3fc 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -33,30 +33,30 @@ #define CPRINTS(...) #else #define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) #endif /* PM channel definitions */ -#define PMC_ACPI PM_CHAN_1 +#define PMC_ACPI PM_CHAN_1 #define PMC_HOST_CMD PM_CHAN_2 /* Microseconds to wait for eSPI VW changes to propagate */ -#define ESPI_DIRTY_WAIT_TIME_US 150 +#define ESPI_DIRTY_WAIT_TIME_US 150 -#define PORT80_MAX_BUF_SIZE 16 +#define PORT80_MAX_BUF_SIZE 16 static uint16_t port80_buf[PORT80_MAX_BUF_SIZE]; -static struct host_packet lpc_packet; -static struct host_cmd_handler_args host_cmd_args; -static uint8_t host_cmd_flags; /* Flags from host command */ -static uint8_t shm_mem_host_cmd[256] __aligned(8); -static uint8_t shm_memmap[256] __aligned(8); +static struct host_packet lpc_packet; +static struct host_cmd_handler_args host_cmd_args; +static uint8_t host_cmd_flags; /* Flags from host command */ +static uint8_t shm_mem_host_cmd[256] __aligned(8); +static uint8_t shm_memmap[256] __aligned(8); /* Params must be 32-bit aligned */ static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4); static int init_done; -static struct ec_lpc_host_args * const lpc_host_args = - (struct ec_lpc_host_args *)shm_mem_host_cmd; +static struct ec_lpc_host_args *const lpc_host_args = + (struct ec_lpc_host_args *)shm_mem_host_cmd; /*****************************************************************************/ /* IC specific low-level driver */ @@ -152,7 +152,7 @@ static void lpc_generate_smi(void) /* Generate a falling edge */ espi_wait_vw_not_dirty(VW_SMI_L, ESPI_DIRTY_WAIT_TIME_US); NPCX_HIPMIC(PMC_ACPI) = NPCX_VW_SMI(0); - udelay(CONFIG_ESPI_DEFAULT_VW_WIDTH_US); + udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US); espi_wait_vw_not_dirty(VW_SMI_L, ESPI_DIRTY_WAIT_TIME_US); /* Set signal high */ @@ -160,10 +160,10 @@ static void lpc_generate_smi(void) #else /* SET SMIB bit to pull SMI_L to high.*/ SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIB); - udelay(CONFIG_ESPI_DEFAULT_VW_WIDTH_US); + udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US); /* Generate a falling edge */ CLEAR_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIB); - udelay(CONFIG_ESPI_DEFAULT_VW_WIDTH_US); + udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US); /* Set signal high */ SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIB); #endif @@ -199,7 +199,7 @@ static void lpc_generate_sci(void) /* Generate a falling edge */ espi_wait_vw_not_dirty(VW_SCI_L, ESPI_DIRTY_WAIT_TIME_US); NPCX_HIPMIC(PMC_ACPI) = NPCX_VW_SCI(0); - udelay(CONFIG_ESPI_DEFAULT_VW_WIDTH_US); + udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US); espi_wait_vw_not_dirty(VW_SCI_L, ESPI_DIRTY_WAIT_TIME_US); /* Set signal high */ @@ -207,10 +207,10 @@ static void lpc_generate_sci(void) #else /* Set SCIB bit to pull SCI_L to high.*/ SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SCIB); - udelay(CONFIG_ESPI_DEFAULT_VW_WIDTH_US); + udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US); /* Generate a falling edge */ CLEAR_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SCIB); - udelay(CONFIG_ESPI_DEFAULT_VW_WIDTH_US); + udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US); /* Set signal high */ SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SCIB); #endif @@ -260,15 +260,13 @@ static void lpc_send_response(struct host_cmd_handler_args *args) } /* New-style response */ - lpc_host_args->flags = - (host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) | - EC_HOST_ARGS_FLAG_TO_HOST; + lpc_host_args->flags = (host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) | + EC_HOST_ARGS_FLAG_TO_HOST; lpc_host_args->data_size = size; csum = args->command + lpc_host_args->flags + - lpc_host_args->command_version + - lpc_host_args->data_size; + lpc_host_args->command_version + lpc_host_args->data_size; for (i = 0, out = (uint8_t *)args->response; i < size; i++, out++) csum += *out; @@ -300,13 +298,13 @@ static void lpc_send_response_packet(struct host_packet *pkt) int lpc_keyboard_has_char(void) { /* if OBF bit is '1', that mean still have a data in DBBOUT */ - return (NPCX_HIKMST&0x01) ? 1 : 0; + return (NPCX_HIKMST & 0x01) ? 1 : 0; } int lpc_keyboard_input_pending(void) { /* if IBF bit is '1', that mean still have a data in DBBIN */ - return (NPCX_HIKMST&0x02) ? 1 : 0; + return (NPCX_HIKMST & 0x02) ? 1 : 0; } /* Put a char to host buffer by HIKDO and send IRQ if specified. */ @@ -407,7 +405,7 @@ void lpc_update_host_event_status(void) /* Copy host events to mapped memory */ *(host_event_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) = - lpc_get_host_events(); + lpc_get_host_events(); lpc_task_enable_irq(); @@ -571,9 +569,9 @@ static void lpc_pmc_ibf_interrupt(void) /* Channel-2 for Host Command usage , so the argument data had been * put on the share memory firstly*/ if (NPCX_HIPMST(PMC_ACPI) & 0x02) - handle_acpi_write((NPCX_HIPMST(PMC_ACPI)&0x08) ? 1 : 0); + handle_acpi_write((NPCX_HIPMST(PMC_ACPI) & 0x08) ? 1 : 0); else if (NPCX_HIPMST(PMC_HOST_CMD) & 0x02) - handle_host_write((NPCX_HIPMST(PMC_HOST_CMD)&0x08) ? 1 : 0); + handle_host_write((NPCX_HIPMST(PMC_HOST_CMD) & 0x08) ? 1 : 0); } DECLARE_IRQ(NPCX_IRQ_PM_CHAN_IBF, lpc_pmc_ibf_interrupt, 4); @@ -591,7 +589,7 @@ static void lpc_port80_interrupt(void) /* buffer Port80 data to the local buffer if FIFO is not empty */ while (IS_BIT_SET(NPCX_DP80STS, NPCX_DP80STS_FNE) && - (count < ARRAY_SIZE(port80_buf))) + (count < ARRAY_SIZE(port80_buf))) port80_buf[count++] = NPCX_DP80BUF; for (i = 0; i < count; i++) { @@ -690,8 +688,7 @@ void host_register_init(void) /* LDN register = 0x0F(SHM) */ sib_write_reg(SIO_OFFSET, 0x07, 0x0F); /* WIN1&2 mapping to IO */ - sib_write_reg(SIO_OFFSET, 0xF1, - sib_read_reg(SIO_OFFSET, 0xF1) | 0x30); + sib_write_reg(SIO_OFFSET, 0xF1, sib_read_reg(SIO_OFFSET, 0xF1) | 0x30); /* WIN1 as Host Command on the IO:0x0800 */ sib_write_reg(SIO_OFFSET, 0xF5, 0x08); sib_write_reg(SIO_OFFSET, 0xF4, 0x00); @@ -711,7 +708,6 @@ void host_register_init(void) sib_write_reg(SIO_OFFSET, 0x30, 0x01); CPRINTS("Host settings are done!"); - } #ifdef CONFIG_CHIPSET_RESET_HOOK @@ -735,7 +731,7 @@ void lpc_lreset_pltrst_handler(void) int pltrst_asserted; /* Clear pending bit of WUI */ - SET_BIT(NPCX_WKPCL(MIWU_TABLE_0 , MIWU_GROUP_5), 7); + SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 7); /* Ignore PLTRST# from SOC if it is not valid */ if (chipset_pltrst_is_valid && !chipset_pltrst_is_valid()) @@ -770,7 +766,7 @@ static void lpc_init(void) { /* Enable clock for LPC peripheral */ clock_enable_peripheral(CGC_OFFSET_LPC, CGC_LPC_MASK, - CGC_MODE_RUN | CGC_MODE_SLEEP); + CGC_MODE_RUN | CGC_MODE_SLEEP); /* * In npcx5/7, the host interface type (HIF_TYP_SEL in the DEVCNT * register) is updated by booter after VCC1 Power-Up reset according to @@ -839,8 +835,8 @@ static void lpc_init(void) /* We support LPC args and version 3 protocol */ *(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) = - EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED | - EC_HOST_CMD_FLAG_VERSION_3; + EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED | + EC_HOST_CMD_FLAG_VERSION_3; /* * Clear processing flag before enabling lpc's interrupts in case @@ -854,7 +850,7 @@ static void lpc_init(void) /* * Set required control value (avoid setting HOSTWAIT bit at this stage) */ - NPCX_SMC_CTL = NPCX_SMC_CTL&~0x7F; + NPCX_SMC_CTL = NPCX_SMC_CTL & ~0x7F; /* Clear status */ NPCX_SMC_STS = NPCX_SMC_STS; @@ -903,8 +899,8 @@ static void lpc_init(void) CLEAR_BIT(NPCX_HIPMCTL(PMC_ACPI), NPCX_HIPMCTL_SCIPOL); CLEAR_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIPOL); /* Set SMIB/SCIB to make sure SMI/SCI are high at init */ - NPCX_HIPMIC(PMC_ACPI) = NPCX_HIPMIC(PMC_ACPI) - | BIT(NPCX_HIPMIC_SMIB) | BIT(NPCX_HIPMIC_SCIB); + NPCX_HIPMIC(PMC_ACPI) = NPCX_HIPMIC(PMC_ACPI) | BIT(NPCX_HIPMIC_SMIB) | + BIT(NPCX_HIPMIC_SCIB); #ifndef CONFIG_SCI_GPIO /* * Allow SMI/SCI generated from PM module. @@ -973,12 +969,11 @@ static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, - lpc_get_protocol_info, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, lpc_get_protocol_info, + EC_VER_MASK(0)); #if DEBUG_LPC -static int command_lpc(int argc, char **argv) +static int command_lpc(int argc, const char **argv) { if (argc == 1) return EC_ERROR_PARAM1; diff --git a/chip/npcx/lpc_chip.h b/chip/npcx/lpc_chip.h index 607fdde5fa..872b20f915 100644 --- a/chip/npcx/lpc_chip.h +++ b/chip/npcx/lpc_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/npcx/peci.c b/chip/npcx/peci.c index 6f82b932b0..7c213648f4 100644 --- a/chip/npcx/peci.c +++ b/chip/npcx/peci.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,31 +19,29 @@ #include "temp_sensor.h" #include "util.h" - /* Initial PECI baud rate */ -#define PECI_BAUD_RATE 750000 - -#define TEMP_AVG_LENGTH 4 /* Should be power of 2 */ +#define PECI_BAUD_RATE 750000 +#define TEMP_AVG_LENGTH 4 /* Should be power of 2 */ /* PECI Time-out */ -#define PECI_DONE_TIMEOUT_US (10*MSEC) +#define PECI_DONE_TIMEOUT_US (10 * MSEC) -#define NULL_PENDING_TASK_ID 0xFFFFFFFF -#define PECI_MAX_FIFO_SIZE 16 -#define PROC_SOCKET 0x30 +#define NULL_PENDING_TASK_ID 0xFFFFFFFF +#define PECI_MAX_FIFO_SIZE 16 +#define PROC_SOCKET 0x30 /* PECI Command Code */ enum peci_command_t { - PECI_COMMAND_PING = 0x00, - PECI_COMMAND_GET_DIB = 0xF7, - PECI_COMMAND_GET_TEMP = 0x01, - PECI_COMMAND_RD_PKG_CFG = 0xA1, - PECI_COMMAND_WR_PKG_CFG = 0xA5, - PECI_COMMAND_RD_IAMSR = 0xB1, - PECI_COMMAND_RD_PCI_CFG = 0x61, - PECI_COMMAND_RD_PCI_CFG_LOCAL = 0xE1, - PECI_COMMAND_WR_PCI_CFG_LOCAL = 0xE5, - PECI_COMMAND_NONE = 0xFF + PECI_COMMAND_PING = 0x00, + PECI_COMMAND_GET_DIB = 0xF7, + PECI_COMMAND_GET_TEMP = 0x01, + PECI_COMMAND_RD_PKG_CFG = 0xA1, + PECI_COMMAND_WR_PKG_CFG = 0xA5, + PECI_COMMAND_RD_IAMSR = 0xB1, + PECI_COMMAND_RD_PCI_CFG = 0x61, + PECI_COMMAND_RD_PCI_CFG_LOCAL = 0xE1, + PECI_COMMAND_WR_PCI_CFG_LOCAL = 0xE5, + PECI_COMMAND_NONE = 0xFF }; #define PECI_COMMAND_GET_TEMP_WR_LENS 0x00 @@ -68,12 +66,8 @@ static int peci_pending_task_id; * @param *wr_data Buffer pointer of write data * @return TASK_EVENT_PECI_DONE that mean slave had a response */ -static uint32_t peci_trans( - uint8_t wr_length, - uint8_t rd_length, - enum peci_command_t cmd_code, - uint8_t *wr_data -) +static uint32_t peci_trans(uint8_t wr_length, uint8_t rd_length, + enum peci_command_t cmd_code, uint8_t *wr_data) { uint32_t events; /* Ensure no PECI transaction is in progress */ @@ -100,7 +94,7 @@ static uint32_t peci_trans( /* Write-Length */ if (cmd_code != PECI_COMMAND_PING) { if ((cmd_code == PECI_COMMAND_WR_PKG_CFG) || - (cmd_code == PECI_COMMAND_WR_PCI_CFG_LOCAL)) { + (cmd_code == PECI_COMMAND_WR_PCI_CFG_LOCAL)) { /*CMD+AWFCS*/ NPCX_PECI_WR_LENGTH = wr_length + 2; /* Enable AWFCS */ @@ -110,7 +104,7 @@ static uint32_t peci_trans( NPCX_PECI_WR_LENGTH = wr_length + 1; /* Enable AWFCS */ CLEAR_BIT(NPCX_PECI_CTL_STS, - NPCX_PECI_CTL_STS_AWFCS_EN); + NPCX_PECI_CTL_STS_AWFCS_EN); } } @@ -119,9 +113,7 @@ static uint32_t peci_trans( /* It should be using a interrupt , don't waste cpu computing power */ peci_pending_task_id = task_get_current(); - return task_wait_event_mask(TASK_EVENT_PECI_DONE, - PECI_DONE_TIMEOUT_US); - + return task_wait_event_mask(TASK_EVENT_PECI_DONE, PECI_DONE_TIMEOUT_US); } /** @@ -143,8 +135,8 @@ int peci_get_cpu_temp(void) /* Start PECI trans */ events = peci_trans(PECI_COMMAND_GET_TEMP_WR_LENS, - PECI_COMMAND_GET_TEMP_RD_LENS, - PECI_COMMAND_GET_TEMP, NULL); + PECI_COMMAND_GET_TEMP_RD_LENS, + PECI_COMMAND_GET_TEMP, NULL); /* if return DONE , that mean slave had a PECI response */ if ((events & TASK_EVENT_PECI_DONE) == TASK_EVENT_PECI_DONE) { /* check CRC & ABRT */ @@ -223,7 +215,7 @@ static void peci_freq_changed(void) * Maximum bit rate should not extend the field's boundaries. */ if (freq != 0) { - baud = (uint8_t)(freq / (4 * PECI_BAUD_RATE)) - 1; + baud = (uint8_t)(freq / (4 * PECI_BAUD_RATE)) - 1; /* Set maximum PECI baud rate (bit0 - bit4) */ if (baud > 0x1F) baud = 0x1F; @@ -247,7 +239,7 @@ static void peci_init(void) /* Enable clock for PECI peripheral */ clock_enable_peripheral(CGC_OFFSET_PECI, CGC_PECI_MASK, - CGC_MODE_RUN | CGC_MODE_SLEEP); + CGC_MODE_RUN | CGC_MODE_SLEEP); /* Set PECI freq */ peci_freq_changed(); @@ -269,7 +261,8 @@ static void peci_init(void) DECLARE_HOOK(HOOK_INIT, peci_init, HOOK_PRIO_DEFAULT); /* If received a PECI DONE interrupt, post the event to PECI task */ -static void peci_done_interrupt(void){ +static void peci_done_interrupt(void) +{ if (peci_pending_task_id != NULL_PENDING_TASK_ID) task_set_event(peci_pending_task_id, TASK_EVENT_PECI_DONE); peci_sts = NPCX_PECI_CTL_STS & 0x18; @@ -283,7 +276,7 @@ DECLARE_IRQ(NPCX_IRQ_PECI, peci_done_interrupt, 4); /*****************************************************************************/ /* Console commands */ -static int command_peci_temp(int argc, char **argv) +static int command_peci_temp(int argc, const char **argv) { int t = peci_get_cpu_temp(); if (t == -1) { @@ -293,6 +286,5 @@ static int command_peci_temp(int argc, char **argv) ccprintf("CPU temp = %d K = %d\n", t, K_TO_C(t)); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(pecitemp, command_peci_temp, - NULL, - "Print CPU temperature"); +DECLARE_CONSOLE_COMMAND(pecitemp, command_peci_temp, NULL, + "Print CPU temperature"); diff --git a/chip/npcx/ps2.c b/chip/npcx/ps2.c index 13a1ff6d57..a8a65e63ea 100644 --- a/chip/npcx/ps2.c +++ b/chip/npcx/ps2.c @@ -1,5 +1,5 @@ /* - * Copyright 2019 The Chromium OS Authors. All rights reserved. + * Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -16,25 +16,25 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_PS2, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_PS2, format, ## args) +#define CPRINTS(format, args...) cprints(CC_PS2, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_PS2, format, ##args) #if !(DEBUG_PS2) #define DEBUG_CPRINTS(...) #define DEBUG_CPRINTF(...) #else -#define DEBUG_CPRINTS(format, args...) cprints(CC_PS2, format, ## args) -#define DEBUG_CPRINTF(format, args...) cprintf(CC_PS2, format, ## args) +#define DEBUG_CPRINTS(format, args...) cprints(CC_PS2, format, ##args) +#define DEBUG_CPRINTF(format, args...) cprintf(CC_PS2, format, ##args) #endif /* * Set WDAT3-0 and clear CLK3-0 in the PSOSIG register to * reset the shift mechanism. */ -#define PS2_SHIFT_MECH_RESET 0x47 +#define PS2_SHIFT_MECH_RESET 0x47 -#define PS2_TRANSACTION_TIMEOUT (20 * MSEC) -#define PS2_BUSY_RETRY 10 +#define PS2_TRANSACTION_TIMEOUT (20 * MSEC) +#define PS2_BUSY_RETRY 10 enum ps2_input_debounce_cycle { PS2_IDB_1_CYCLE, @@ -60,7 +60,7 @@ struct ps2_data { void (*rx_handler_cb)(uint8_t data); }; static struct ps2_data ps2_ch_data[NPCX_PS2_CH_COUNT] = { - [0 ... (NPCX_PS2_CH_COUNT - 1)] = { PS2_RX_MODE, NULL } + [0 ...(NPCX_PS2_CH_COUNT - 1)] = { PS2_RX_MODE, NULL } }; /* @@ -76,7 +76,7 @@ static void ps2_init(void) { /* Disable the power down bit of PS/2 */ clock_enable_peripheral(CGC_OFFSET_PS2, CGC_PS2_MASK, - CGC_MODE_RUN | CGC_MODE_SLEEP); + CGC_MODE_RUN | CGC_MODE_SLEEP); /* Disable shift mechanism and configure PS/2 to received mode. */ NPCX_PS2_PSCON = 0x0; @@ -90,10 +90,9 @@ static void ps2_init(void) * [4] - : WUE = 1: Wake-Up Enable * [7] - : CLK_SEL = 1: Select Free-Run clock as the basic clock */ - NPCX_PS2_PSIEN = BIT(NPCX_PS2_PSIEN_SOTIE) | - BIT(NPCX_PS2_PSIEN_EOTIE) | - BIT(NPCX_PS2_PSIEN_PS2_WUE) | - BIT(NPCX_PS2_PSIEN_PS2_CLK_SEL); + NPCX_PS2_PSIEN = BIT(NPCX_PS2_PSIEN_SOTIE) | BIT(NPCX_PS2_PSIEN_EOTIE) | + BIT(NPCX_PS2_PSIEN_PS2_WUE) | + BIT(NPCX_PS2_PSIEN_PS2_CLK_SEL); /* Enable weak internal pull-up */ SET_BIT(NPCX_PS2_PSCON, NPCX_PS2_PSCON_WPUED); @@ -106,8 +105,7 @@ static void ps2_init(void) } DECLARE_HOOK(HOOK_INIT, ps2_init, HOOK_PRIO_DEFAULT); -void ps2_enable_channel(int channel, int enable, - void (*callback)(uint8_t data)) +void ps2_enable_channel(int channel, int enable, void (*callback)(uint8_t data)) { if (channel >= NPCX_PS2_CH_COUNT) { CPRINTS("Err:PS/2 CH exceed %d", NPCX_PS2_CH_COUNT); @@ -125,7 +123,7 @@ void ps2_enable_channel(int channel, int enable, /* Enable the relevant channel clock */ SET_BIT(NPCX_PS2_PSOSIG, NPCX_PS2_PSOSIG_CLK(channel)); } else { - channel_enabled_mask &= ~BIT(NPCX_PS2_PSOSIG_CLK(channel)); + channel_enabled_mask &= ~BIT(NPCX_PS2_PSOSIG_CLK(channel)); /* Disable the relevant channel clock */ CLEAR_BIT(NPCX_PS2_PSOSIG, NPCX_PS2_PSOSIG_CLK(channel)); ps2_ch_data[channel].rx_handler_cb = NULL; @@ -144,7 +142,9 @@ static int ps2_is_busy(void) * (due to Shift Mechanism is reset) */ return (IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_SOT) | - IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_EOT)) ? 1 : 0; + IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_EOT)) ? + 1 : + 0; } int ps2_transmit_byte(int channel, uint8_t data) @@ -194,7 +194,7 @@ int ps2_transmit_byte(int channel, uint8_t data) /* Wait for interrupt */ event = task_wait_event_mask(TASK_EVENT_PS2_DONE, - PS2_TRANSACTION_TIMEOUT); + PS2_TRANSACTION_TIMEOUT); task_waiting = TASK_ID_INVALID; if (event == TASK_EVENT_TIMER) { @@ -216,7 +216,6 @@ int ps2_transmit_byte(int channel, uint8_t data) DEBUG_CPRINTF("Evt:0x%08x\n", event); return (event == TASK_EVENT_PS2_DONE) ? EC_SUCCESS : EC_ERROR_TIMEOUT; - } static void ps2_stop_inactive_ch_clk(uint8_t active_ch) @@ -224,20 +223,17 @@ static void ps2_stop_inactive_ch_clk(uint8_t active_ch) uint8_t mask; mask = ~NPCX_PS2_PSOSIG_CLK_MASK_ALL | - BIT(NPCX_PS2_PSOSIG_CLK(active_ch)); + BIT(NPCX_PS2_PSOSIG_CLK(active_ch)); NPCX_PS2_PSOSIG &= mask; - } static int ps2_is_rx_error(uint8_t ch) { - uint8_t status; + uint8_t status; status = NPCX_PS2_PSTAT & - (BIT(NPCX_PS2_PSTAT_PERR) | - BIT(NPCX_PS2_PSTAT_RFERR)); + (BIT(NPCX_PS2_PSTAT_PERR) | BIT(NPCX_PS2_PSTAT_RFERR)); if (status) { - if (status & BIT(NPCX_PS2_PSTAT_PERR)) CPRINTF("PS2 CH %d RX parity error\n", ch); if (status & BIT(NPCX_PS2_PSTAT_RFERR)) @@ -270,7 +266,7 @@ static void ps2_int_handler(void) /* PS/2 Start of Transaction */ if (IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_SOT) && - IS_BIT_SET(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_SOTIE)) { + IS_BIT_SET(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_SOTIE)) { DEBUG_CPRINTF("SOT-"); /* * Once set, SOT is not cleared until the shift mechanism @@ -278,7 +274,7 @@ static void ps2_int_handler(void) * first occurrence of an SOT interrupt. */ CLEAR_BIT(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_SOTIE); - /* PS/2 End of Transaction */ + /* PS/2 End of Transaction */ } else if (IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_EOT)) { DEBUG_CPRINTF("EOT-"); CLEAR_BIT(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_EOTIE); @@ -298,7 +294,7 @@ static void ps2_int_handler(void) if (!ps2_is_rx_error(active_ch)) { uint8_t data_read = NPCX_PS2_PSDAT; struct ps2_data *ps2_ptr = - &ps2_ch_data[active_ch]; + &ps2_ch_data[active_ch]; DEBUG_CPRINTF("Recv:0x%02x", data_read); if (ps2_ptr->rx_handler_cb) @@ -316,12 +312,11 @@ static void ps2_int_handler(void) SET_BIT(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_EOTIE); } DEBUG_CPRINTF("\n"); - } DECLARE_IRQ(NPCX_IRQ_PS2, ps2_int_handler, 5); #ifdef CONFIG_CMD_PS2 -static int command_ps2ench(int argc, char **argv) +static int command_ps2ench(int argc, const char **argv) { uint8_t ch; uint8_t enable; @@ -341,11 +336,10 @@ static int command_ps2ench(int argc, char **argv) return 0; } -DECLARE_CONSOLE_COMMAND(ps2ench, command_ps2ench, - "ps2_ench channel 1|0", +DECLARE_CONSOLE_COMMAND(ps2ench, command_ps2ench, "ps2_ench channel 1|0", "Enable/Disable PS/2 channel"); -static int command_ps2write(int argc, char **argv) +static int command_ps2write(int argc, const char **argv) { uint8_t ch, data; char *e; @@ -360,7 +354,6 @@ static int command_ps2write(int argc, char **argv) ps2_transmit_byte(ch, data); return 0; } -DECLARE_CONSOLE_COMMAND(ps2write, command_ps2write, - "ps2_write channel data", - "Write data byte to PS/2 channel "); +DECLARE_CONSOLE_COMMAND(ps2write, command_ps2write, "ps2_write channel data", + "Write data byte to PS/2 channel "); #endif diff --git a/chip/npcx/ps2_chip.h b/chip/npcx/ps2_chip.h index d88e6791ad..871b1ab6e5 100644 --- a/chip/npcx/ps2_chip.h +++ b/chip/npcx/ps2_chip.h @@ -1,5 +1,5 @@ /* - * Copyright 2019 The Chromium OS Authors. All rights reserved. + * Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -21,4 +21,4 @@ void ps2_enable_channel(int channel, int enable, void (*callback)(uint8_t data)); int ps2_transmit_byte(int channel, uint8_t data); -#endif /* __CROS_EC_PS2_CHIP_H */ +#endif /* __CROS_EC_PS2_CHIP_H */ diff --git a/chip/npcx/pwm.c b/chip/npcx/pwm.c index b2016906b3..53a278a0ba 100644 --- a/chip/npcx/pwm.c +++ b/chip/npcx/pwm.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -8,7 +8,7 @@ * On this chip, the PWM logic is implemented by the hardware FAN modules. */ -#include "assert.h" +#include "builtin/assert.h" #include "clock.h" #include "clock_chip.h" #include "console.h" @@ -23,7 +23,7 @@ #if !(DEBUG_PWM) #define CPRINTS(...) #else -#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_PWM, format, ##args) #endif /* pwm resolution for each channel */ @@ -31,20 +31,20 @@ static uint32_t pwm_res[PWM_CH_COUNT]; /* PWM clock source */ enum npcx_pwm_source_clock { - NPCX_PWM_CLOCK_APB2_LFCLK = 0, - NPCX_PWM_CLOCK_FX = 1, - NPCX_PWM_CLOCK_FR = 2, - NPCX_PWM_CLOCK_RESERVED = 3, - NPCX_PWM_CLOCK_UNDEF = 0xFF + NPCX_PWM_CLOCK_APB2_LFCLK = 0, + NPCX_PWM_CLOCK_FX = 1, + NPCX_PWM_CLOCK_FR = 2, + NPCX_PWM_CLOCK_RESERVED = 3, + NPCX_PWM_CLOCK_UNDEF = 0xFF }; /* PWM heartbeat mode */ enum npcx_pwm_heartbeat_mode { - NPCX_PWM_HBM_NORMAL = 0, - NPCX_PWM_HBM_25 = 1, - NPCX_PWM_HBM_50 = 2, - NPCX_PWM_HBM_100 = 3, - NPCX_PWM_HBM_UNDEF = 0xFF + NPCX_PWM_HBM_NORMAL = 0, + NPCX_PWM_HBM_25 = 1, + NPCX_PWM_HBM_50 = 2, + NPCX_PWM_HBM_100 = 3, + NPCX_PWM_HBM_UNDEF = 0xFF }; /** @@ -146,7 +146,7 @@ void pwm_set_raw_duty(enum pwm_channel ch, uint16_t duty) /* Assume the fan control is active high and invert it ourselves */ UPDATE_BIT(NPCX_PWMCTL(mdl), NPCX_PWMCTL_INVP, - (pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW)); + (pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW)); CPRINTS("initial freq=0x%x", pwm_channels[ch].freq); CPRINTS("duty_cycle_cnt=%d", duty); @@ -189,7 +189,7 @@ uint16_t pwm_get_raw_duty(enum pwm_channel ch) * so scale to 0 - 0xffff */ return DIV_ROUND_NEAREST(NPCX_DCR(mdl) * EC_PWM_MAX_DUTY, - pwm_res[ch]); + pwm_res[ch]); } /** @@ -206,22 +206,22 @@ void pwm_config(enum pwm_channel ch) /* Set PWM heartbeat mode is no heartbeat */ SET_FIELD(NPCX_PWMCTL(mdl), NPCX_PWMCTL_HB_DC_CTL_FIELD, - NPCX_PWM_HBM_NORMAL); + NPCX_PWM_HBM_NORMAL); /* Select default CLK or LFCLK clock input to PWM module */ SET_FIELD(NPCX_PWMCTLEX(mdl), NPCX_PWMCTLEX_FCK_SEL_FIELD, - NPCX_PWM_CLOCK_APB2_LFCLK); + NPCX_PWM_CLOCK_APB2_LFCLK); /* Set PWM polarity normal first */ CLEAR_BIT(NPCX_PWMCTL(mdl), NPCX_PWMCTL_INVP); /* Select PWM clock source */ UPDATE_BIT(NPCX_PWMCTL(mdl), NPCX_PWMCTL_CKSEL, - (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP)); + (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP)); /* Select PWM IO type */ UPDATE_BIT(NPCX_PWMCTLEX(mdl), NPCX_PWMCTLEX_OD_OUT, - (pwm_channels[ch].flags & PWM_CONFIG_OPEN_DRAIN)); + (pwm_channels[ch].flags & PWM_CONFIG_OPEN_DRAIN)); /* Set PWM operation frequency */ pwm_set_freq(ch, pwm_channels[ch].freq); diff --git a/chip/npcx/pwm_chip.h b/chip/npcx/pwm_chip.h index 7acfef81e5..714ecfb4a3 100644 --- a/chip/npcx/pwm_chip.h +++ b/chip/npcx/pwm_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/npcx/registers-npcx5.h b/chip/npcx/registers-npcx5.h index c441c1c926..b7302bdd13 100644 --- a/chip/npcx/registers-npcx5.h +++ b/chip/npcx/registers-npcx5.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,87 +19,87 @@ #endif /* NPCX-IRQ numbers */ -#define NPCX_IRQ0_NOUSED NPCX_IRQ_0 -#define NPCX_IRQ1_NOUSED NPCX_IRQ_1 -#define NPCX_IRQ_KBSCAN NPCX_IRQ_2 -#define NPCX_IRQ_PM_CHAN_OBE NPCX_IRQ_3 -#define NPCX_IRQ_PECI NPCX_IRQ_4 -#define NPCX_IRQ5_NOUSED NPCX_IRQ_5 -#define NPCX_IRQ_PORT80 NPCX_IRQ_6 -#define NPCX_IRQ_MTC_WKINTAD_0 NPCX_IRQ_7 -#define NPCX_IRQ_MTC NPCX_IRQ_MTC_WKINTAD_0 -#define NPCX_IRQ8_NOUSED NPCX_IRQ_8 -#define NPCX_IRQ_MFT_1 NPCX_IRQ_9 -#define NPCX_IRQ_ADC NPCX_IRQ_10 -#define NPCX_IRQ_WKINTEFGH_0 NPCX_IRQ_11 -#define NPCX_IRQ_GDMA NPCX_IRQ_12 -#define NPCX_IRQ_SMB1 NPCX_IRQ_13 -#define NPCX_IRQ_SMB2 NPCX_IRQ_14 -#define NPCX_IRQ_WKINTC_0 NPCX_IRQ_15 -#define NPCX_IRQ16_NOUSED NPCX_IRQ_16 -#define NPCX_IRQ_ITIM16_3 NPCX_IRQ_17 -#define NPCX_IRQ_SHI NPCX_IRQ_18 -#define NPCX_IRQ_ESPI NPCX_IRQ_18 -#define NPCX_IRQ19_NOUSED NPCX_IRQ_19 -#define NPCX_IRQ20_NOUSED NPCX_IRQ_20 -#define NPCX_IRQ_PS2 NPCX_IRQ_21 -#define NPCX_IRQ22_NOUSED NPCX_IRQ_22 -#define NPCX_IRQ_MFT_2 NPCX_IRQ_23 -#define NPCX_IRQ_SHM NPCX_IRQ_24 -#define NPCX_IRQ_KBC_IBF NPCX_IRQ_25 -#define NPCX_IRQ_PM_CHAN_IBF NPCX_IRQ_26 -#define NPCX_IRQ_ITIM16_2 NPCX_IRQ_27 -#define NPCX_IRQ_ITIM16_1 NPCX_IRQ_28 -#define NPCX_IRQ29_NOUSED NPCX_IRQ_29 -#define NPCX_IRQ30_NOUSED NPCX_IRQ_30 -#define NPCX_IRQ_TWD_WKINTB_0 NPCX_IRQ_31 -#define NPCX_IRQ32_NOUSED NPCX_IRQ_32 -#define NPCX_IRQ_UART NPCX_IRQ_33 -#define NPCX_IRQ34_NOUSED NPCX_IRQ_34 -#define NPCX_IRQ35_NOUSED NPCX_IRQ_35 -#define NPCX_IRQ_SMB3 NPCX_IRQ_36 -#define NPCX_IRQ_SMB4 NPCX_IRQ_37 -#define NPCX_IRQ38_NOUSED NPCX_IRQ_38 -#define NPCX_IRQ39_NOUSED NPCX_IRQ_39 -#define NPCX_IRQ40_NOUSED NPCX_IRQ_40 -#define NPCX_IRQ_MFT_3 NPCX_IRQ_41 -#define NPCX_IRQ42_NOUSED NPCX_IRQ_42 -#define NPCX_IRQ_ITIM16_4 NPCX_IRQ_43 -#define NPCX_IRQ_ITIM16_5 NPCX_IRQ_44 -#define NPCX_IRQ_ITIM16_6 NPCX_IRQ_45 -#define NPCX_IRQ_ITIM32 NPCX_IRQ_46 -#define NPCX_IRQ_WKINTA_1 NPCX_IRQ_47 -#define NPCX_IRQ_WKINTB_1 NPCX_IRQ_48 -#define NPCX_IRQ_KSI_WKINTC_1 NPCX_IRQ_49 -#define NPCX_IRQ_WKINTD_1 NPCX_IRQ_50 -#define NPCX_IRQ_WKINTE_1 NPCX_IRQ_51 -#define NPCX_IRQ_WKINTF_1 NPCX_IRQ_52 -#define NPCX_IRQ_WKINTG_1 NPCX_IRQ_53 -#define NPCX_IRQ_WKINTH_1 NPCX_IRQ_54 -#define NPCX_IRQ55_NOUSED NPCX_IRQ_55 -#define NPCX_IRQ_KBC_OBE NPCX_IRQ_56 -#define NPCX_IRQ_SPI NPCX_IRQ_57 -#define NPCX_IRQ58_NOUSED NPCX_IRQ_58 -#define NPCX_IRQ_WKINTFG_2 NPCX_IRQ_59 -#define NPCX_IRQ_WKINTA_2 NPCX_IRQ_60 -#define NPCX_IRQ_WKINTB_2 NPCX_IRQ_61 -#define NPCX_IRQ_WKINTC_2 NPCX_IRQ_62 -#define NPCX_IRQ_WKINTD_2 NPCX_IRQ_63 +#define NPCX_IRQ0_NOUSED NPCX_IRQ_0 +#define NPCX_IRQ1_NOUSED NPCX_IRQ_1 +#define NPCX_IRQ_KBSCAN NPCX_IRQ_2 +#define NPCX_IRQ_PM_CHAN_OBE NPCX_IRQ_3 +#define NPCX_IRQ_PECI NPCX_IRQ_4 +#define NPCX_IRQ5_NOUSED NPCX_IRQ_5 +#define NPCX_IRQ_PORT80 NPCX_IRQ_6 +#define NPCX_IRQ_MTC_WKINTAD_0 NPCX_IRQ_7 +#define NPCX_IRQ_MTC NPCX_IRQ_MTC_WKINTAD_0 +#define NPCX_IRQ8_NOUSED NPCX_IRQ_8 +#define NPCX_IRQ_MFT_1 NPCX_IRQ_9 +#define NPCX_IRQ_ADC NPCX_IRQ_10 +#define NPCX_IRQ_WKINTEFGH_0 NPCX_IRQ_11 +#define NPCX_IRQ_GDMA NPCX_IRQ_12 +#define NPCX_IRQ_SMB1 NPCX_IRQ_13 +#define NPCX_IRQ_SMB2 NPCX_IRQ_14 +#define NPCX_IRQ_WKINTC_0 NPCX_IRQ_15 +#define NPCX_IRQ16_NOUSED NPCX_IRQ_16 +#define NPCX_IRQ_ITIM16_3 NPCX_IRQ_17 +#define NPCX_IRQ_SHI NPCX_IRQ_18 +#define NPCX_IRQ_ESPI NPCX_IRQ_18 +#define NPCX_IRQ19_NOUSED NPCX_IRQ_19 +#define NPCX_IRQ20_NOUSED NPCX_IRQ_20 +#define NPCX_IRQ_PS2 NPCX_IRQ_21 +#define NPCX_IRQ22_NOUSED NPCX_IRQ_22 +#define NPCX_IRQ_MFT_2 NPCX_IRQ_23 +#define NPCX_IRQ_SHM NPCX_IRQ_24 +#define NPCX_IRQ_KBC_IBF NPCX_IRQ_25 +#define NPCX_IRQ_PM_CHAN_IBF NPCX_IRQ_26 +#define NPCX_IRQ_ITIM16_2 NPCX_IRQ_27 +#define NPCX_IRQ_ITIM16_1 NPCX_IRQ_28 +#define NPCX_IRQ29_NOUSED NPCX_IRQ_29 +#define NPCX_IRQ30_NOUSED NPCX_IRQ_30 +#define NPCX_IRQ_TWD_WKINTB_0 NPCX_IRQ_31 +#define NPCX_IRQ32_NOUSED NPCX_IRQ_32 +#define NPCX_IRQ_UART NPCX_IRQ_33 +#define NPCX_IRQ34_NOUSED NPCX_IRQ_34 +#define NPCX_IRQ35_NOUSED NPCX_IRQ_35 +#define NPCX_IRQ_SMB3 NPCX_IRQ_36 +#define NPCX_IRQ_SMB4 NPCX_IRQ_37 +#define NPCX_IRQ38_NOUSED NPCX_IRQ_38 +#define NPCX_IRQ39_NOUSED NPCX_IRQ_39 +#define NPCX_IRQ40_NOUSED NPCX_IRQ_40 +#define NPCX_IRQ_MFT_3 NPCX_IRQ_41 +#define NPCX_IRQ42_NOUSED NPCX_IRQ_42 +#define NPCX_IRQ_ITIM16_4 NPCX_IRQ_43 +#define NPCX_IRQ_ITIM16_5 NPCX_IRQ_44 +#define NPCX_IRQ_ITIM16_6 NPCX_IRQ_45 +#define NPCX_IRQ_ITIM32 NPCX_IRQ_46 +#define NPCX_IRQ_WKINTA_1 NPCX_IRQ_47 +#define NPCX_IRQ_WKINTB_1 NPCX_IRQ_48 +#define NPCX_IRQ_KSI_WKINTC_1 NPCX_IRQ_49 +#define NPCX_IRQ_WKINTD_1 NPCX_IRQ_50 +#define NPCX_IRQ_WKINTE_1 NPCX_IRQ_51 +#define NPCX_IRQ_WKINTF_1 NPCX_IRQ_52 +#define NPCX_IRQ_WKINTG_1 NPCX_IRQ_53 +#define NPCX_IRQ_WKINTH_1 NPCX_IRQ_54 +#define NPCX_IRQ55_NOUSED NPCX_IRQ_55 +#define NPCX_IRQ_KBC_OBE NPCX_IRQ_56 +#define NPCX_IRQ_SPI NPCX_IRQ_57 +#define NPCX_IRQ58_NOUSED NPCX_IRQ_58 +#define NPCX_IRQ_WKINTFG_2 NPCX_IRQ_59 +#define NPCX_IRQ_WKINTA_2 NPCX_IRQ_60 +#define NPCX_IRQ_WKINTB_2 NPCX_IRQ_61 +#define NPCX_IRQ_WKINTC_2 NPCX_IRQ_62 +#define NPCX_IRQ_WKINTD_2 NPCX_IRQ_63 /* Modules Map */ /* Miscellaneous Device Control (MDC) registers */ -#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x007) +#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x007) /* MDC register fields */ -#define NPCX_FWCTRL_RO_REGION 0 -#define NPCX_FWCTRL_FW_SLOT 1 +#define NPCX_FWCTRL_RO_REGION 0 +#define NPCX_FWCTRL_FW_SLOT 1 -#define NPCX_ITIM32_BASE_ADDR 0x400BC000 -#define NPCX_CR_UART_BASE_ADDR(mdl) (0x400C4000 + ((mdl) * 0x2000L)) -#define NPCX_SMB_BASE_ADDR(mdl) (((mdl) < 2) ? \ - (0x40009000 + ((mdl) * 0x2000L)) : \ - (0x400C0000 + (((mdl) - 2) * 0x2000L))) +#define NPCX_ITIM32_BASE_ADDR 0x400BC000 +#define NPCX_CR_UART_BASE_ADDR(mdl) (0x400C4000 + ((mdl)*0x2000L)) +#define NPCX_SMB_BASE_ADDR(mdl) \ + (((mdl) < 2) ? (0x40009000 + ((mdl)*0x2000L)) : \ + (0x400C0000 + (((mdl)-2) * 0x2000L))) enum { NPCX_UART_PORT0 = 0, /* UART port 0 */ @@ -129,39 +129,39 @@ enum { ALT_GROUP_COUNT }; -#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n)) +#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n)) -#define NPCX_LV_GPIO_CTL(n) REG8(NPCX_SCFG_BASE_ADDR + 0x02A + (n)) +#define NPCX_LV_GPIO_CTL(n) REG8(NPCX_SCFG_BASE_ADDR + 0x02A + (n)) /* pin-mux for JTAG */ -#define NPCX_DEVALT5_NJEN1_EN 1 -#define NPCX_DEVALT5_NJEN0_EN 2 +#define NPCX_DEVALT5_NJEN1_EN 1 +#define NPCX_DEVALT5_NJEN0_EN 2 /* pin-mux for I2C */ -#define NPCX_DEVALT2_I2C0_0_SL 0 -#define NPCX_DEVALT2_I2C0_1_SL 1 -#define NPCX_DEVALT2_I2C1_0_SL 2 -#define NPCX_DEVALT2_I2C2_0_SL 4 -#define NPCX_DEVALT2_I2C3_0_SL 6 +#define NPCX_DEVALT2_I2C0_0_SL 0 +#define NPCX_DEVALT2_I2C0_1_SL 1 +#define NPCX_DEVALT2_I2C1_0_SL 2 +#define NPCX_DEVALT2_I2C2_0_SL 4 +#define NPCX_DEVALT2_I2C3_0_SL 6 /* pin-mux for UART */ -#define NPCX_DEVALTA_UART_SL1 7 -#define NPCX_DEVALTC_UART_SL2 0 +#define NPCX_DEVALTA_UART_SL1 7 +#define NPCX_DEVALTC_UART_SL2 0 /* pin-mux for Misc. */ /* External 32KHz crytal osc. input support */ -#define NPCX_DEVALTA_32KCLKIN_SL 3 +#define NPCX_DEVALTA_32KCLKIN_SL 3 /* SMBus register fields */ -#define NPCX_SMBSEL_SMB0SEL 0 +#define NPCX_SMBSEL_SMB0SEL 0 /* SMB enumeration: I2C port definitions. */ enum { - NPCX_I2C_PORT0_0 = 0, /* I2C port 0, bus 0 */ - NPCX_I2C_PORT0_1, /* I2C port 0, bus 1 */ - NPCX_I2C_PORT1, /* I2C port 1 */ - NPCX_I2C_PORT2, /* I2C port 2 */ - NPCX_I2C_PORT3, /* I2C port 3 */ + NPCX_I2C_PORT0_0 = 0, /* I2C port 0, bus 0 */ + NPCX_I2C_PORT0_1, /* I2C port 0, bus 1 */ + NPCX_I2C_PORT1, /* I2C port 1 */ + NPCX_I2C_PORT2, /* I2C port 2 */ + NPCX_I2C_PORT3, /* I2C port 3 */ NPCX_I2C_COUNT, }; @@ -195,32 +195,31 @@ enum NPCX_PMC_PWDWN_CTL_T { NPCX_PMC_PWDWN_CNT, }; -#define CGC_I2C_MASK (BIT(NPCX_PWDWN_CTL3_SMB0_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB2_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB3_PD)) +#define CGC_I2C_MASK \ + (BIT(NPCX_PWDWN_CTL3_SMB0_PD) | BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \ + BIT(NPCX_PWDWN_CTL3_SMB2_PD) | BIT(NPCX_PWDWN_CTL3_SMB3_PD)) /* BBRAM register fields */ #define NPCX_BKUP_STS_ALL_MASK BIT(NPCX_BKUP_STS_IBBR) -#define NPCX_BBRAM_SIZE 64 /* Size of BBRAM */ +#define NPCX_BBRAM_SIZE 64 /* Size of BBRAM */ /* ITIM registers */ -#define NPCX_ITCNT8(n) REG8(NPCX_ITIM_BASE_ADDR(n) + 0x000) -#define NPCX_ITCNT16(n) REG16(NPCX_ITIM_BASE_ADDR(n) + 0x002) +#define NPCX_ITCNT8(n) REG8(NPCX_ITIM_BASE_ADDR(n) + 0x000) +#define NPCX_ITCNT16(n) REG16(NPCX_ITIM_BASE_ADDR(n) + 0x002) /* ITIM32 registers */ -#define NPCX_ITCNT32 REG32(NPCX_ITIM32_BASE_ADDR + 0x008) +#define NPCX_ITCNT32 REG32(NPCX_ITIM32_BASE_ADDR + 0x008) /* Timer counter register used for 1 micro-second system tick */ -#define NPCX_ITCNT_SYSTEM NPCX_ITCNT32 +#define NPCX_ITCNT_SYSTEM NPCX_ITCNT32 /* Timer counter register used for others */ -#define NPCX_ITCNT NPCX_ITCNT16 +#define NPCX_ITCNT NPCX_ITCNT16 /* ITIM module No. used for event */ -#define ITIM_EVENT_NO ITIM16_1 +#define ITIM_EVENT_NO ITIM16_1 /* ITIM module No. used for watchdog */ -#define ITIM_WDG_NO ITIM16_5 +#define ITIM_WDG_NO ITIM16_5 /* ITIM module No. used for 1 micro-second system tick */ -#define ITIM_SYSTEM_NO ITIM32 +#define ITIM_SYSTEM_NO ITIM32 /* ITIM enumeration */ enum ITIM_MODULE_T { @@ -235,11 +234,11 @@ enum ITIM_MODULE_T { }; /* Serial Host Interface (SHI) Registers */ -#define NPCX_OBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n)) -#define NPCX_IBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x060 + (n)) +#define NPCX_OBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n)) +#define NPCX_IBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x060 + (n)) /* Bit field manipulation for VWEVMS Value */ -#define VWEVMS_INTWK_EN VWEVMS_INT_EN +#define VWEVMS_INTWK_EN VWEVMS_INT_EN /* eSPI max supported frequency */ enum { @@ -253,35 +252,35 @@ enum { /* eSPI max frequency support per FMCLK */ #if (FMCLK <= 33000000) -#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_33 +#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_33 #elif (FMCLK <= 48000000) -#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_50 +#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_50 #else -#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_66 +#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_66 #endif /* MIWU registers */ -#define NPCX_WKEDG_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x00 + \ - ((n) * 2L) + ((n) < 5 ? 0 : 0x1E)) -#define NPCX_WKAEDG_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x01 + \ - ((n) * 2L) + ((n) < 5 ? 0 : 0x1E)) -#define NPCX_WKPND_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x0A + \ - ((n) * 4L) + ((n) < 5 ? 0 : 0x10)) -#define NPCX_WKPCL_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x0C + \ - ((n) * 4L) + ((n) < 5 ? 0 : 0x10)) -#define NPCX_WKEN_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x1E + \ - ((n) * 2L) + ((n) < 5 ? 0 : 0x12)) -#define NPCX_WKINEN_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x1F + \ - ((n) * 2L) + ((n) < 5 ? 0 : 0x12)) -#define NPCX_WKMOD_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x70 + (n)) - -#define NPCX_WKEDG(port, n) REG8(NPCX_WKEDG_ADDR(port, n)) -#define NPCX_WKAEDG(port, n) REG8(NPCX_WKAEDG_ADDR(port, n)) -#define NPCX_WKPND(port, n) REG8(NPCX_WKPND_ADDR(port, n)) -#define NPCX_WKPCL(port, n) REG8(NPCX_WKPCL_ADDR(port, n)) -#define NPCX_WKEN(port, n) REG8(NPCX_WKEN_ADDR(port, n)) -#define NPCX_WKINEN(port, n) REG8(NPCX_WKINEN_ADDR(port, n)) -#define NPCX_WKMOD(port, n) REG8(NPCX_WKMOD_ADDR(port, n)) +#define NPCX_WKEDG_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x00 + ((n)*2L) + ((n) < 5 ? 0 : 0x1E)) +#define NPCX_WKAEDG_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x01 + ((n)*2L) + ((n) < 5 ? 0 : 0x1E)) +#define NPCX_WKPND_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x0A + ((n)*4L) + ((n) < 5 ? 0 : 0x10)) +#define NPCX_WKPCL_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x0C + ((n)*4L) + ((n) < 5 ? 0 : 0x10)) +#define NPCX_WKEN_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x1E + ((n)*2L) + ((n) < 5 ? 0 : 0x12)) +#define NPCX_WKINEN_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x1F + ((n)*2L) + ((n) < 5 ? 0 : 0x12)) +#define NPCX_WKMOD_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x70 + (n)) + +#define NPCX_WKEDG(port, n) REG8(NPCX_WKEDG_ADDR(port, n)) +#define NPCX_WKAEDG(port, n) REG8(NPCX_WKAEDG_ADDR(port, n)) +#define NPCX_WKPND(port, n) REG8(NPCX_WKPND_ADDR(port, n)) +#define NPCX_WKPCL(port, n) REG8(NPCX_WKPCL_ADDR(port, n)) +#define NPCX_WKEN(port, n) REG8(NPCX_WKEN_ADDR(port, n)) +#define NPCX_WKINEN(port, n) REG8(NPCX_WKINEN_ADDR(port, n)) +#define NPCX_WKMOD(port, n) REG8(NPCX_WKMOD_ADDR(port, n)) /* UART registers and functions */ #if NPCX_UART_MODULE2 @@ -289,22 +288,22 @@ enum { * To be used as 2nd parameter to NPCX_WK*() macro, table (1st parameter) is * always 1 == MIWU_TABLE_1. */ -#define NPCX_UART_WK_GROUP 6 -#define NPCX_UART_WK_BIT 4 -#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTG_1 -#define NPCX_UART_DEVALT NPCX_DEVALT(0x0C) -#define NPCX_UART_DEVALT_SL NPCX_DEVALTC_UART_SL2 -#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0A) -#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTA_UART_SL1 +#define NPCX_UART_WK_GROUP 6 +#define NPCX_UART_WK_BIT 4 +#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTG_1 +#define NPCX_UART_DEVALT NPCX_DEVALT(0x0C) +#define NPCX_UART_DEVALT_SL NPCX_DEVALTC_UART_SL2 +#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0A) +#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTA_UART_SL1 #else /* !NPCX_UART_MODULE2 */ -#define NPCX_UART_WK_GROUP 1 -#define NPCX_UART_WK_BIT 0 -#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTB_1 -#define NPCX_UART_DEVALT NPCX_DEVALT(0x0A) -#define NPCX_UART_DEVALT_SL NPCX_DEVALTA_UART_SL1 -#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0C) -#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTC_UART_SL2 +#define NPCX_UART_WK_GROUP 1 +#define NPCX_UART_WK_BIT 0 +#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTB_1 +#define NPCX_UART_DEVALT NPCX_DEVALT(0x0A) +#define NPCX_UART_DEVALT_SL NPCX_DEVALTA_UART_SL1 +#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0C) +#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTC_UART_SL2 #endif /* NPCX_UART_MODULE2 */ /* This routine checks pending bit of GPIO wake-up functionality */ @@ -328,8 +327,7 @@ static inline void uart_clear_pending_wakeup(void) /* This routine enables wake-up functionality from GPIO on UART rx pin */ static inline void uart_enable_wakeup(int enable) { - UPDATE_BIT(NPCX_WKEN(1, NPCX_UART_WK_GROUP), NPCX_UART_WK_BIT, - enable); + UPDATE_BIT(NPCX_WKEN(1, NPCX_UART_WK_GROUP), NPCX_UART_WK_BIT, enable); } /* This routine checks functionality is UART rx or not */ @@ -339,50 +337,50 @@ static inline int npcx_is_uart(void) } /* ADC Registers */ -#define NPCX_ADCSTS REG16(NPCX_ADC_BASE_ADDR + 0x000) -#define NPCX_ADCCNF REG16(NPCX_ADC_BASE_ADDR + 0x002) -#define NPCX_ATCTL REG16(NPCX_ADC_BASE_ADDR + 0x004) -#define NPCX_ASCADD REG16(NPCX_ADC_BASE_ADDR + 0x006) -#define NPCX_ADCCS REG16(NPCX_ADC_BASE_ADDR + 0x008) +#define NPCX_ADCSTS REG16(NPCX_ADC_BASE_ADDR + 0x000) +#define NPCX_ADCCNF REG16(NPCX_ADC_BASE_ADDR + 0x002) +#define NPCX_ATCTL REG16(NPCX_ADC_BASE_ADDR + 0x004) +#define NPCX_ASCADD REG16(NPCX_ADC_BASE_ADDR + 0x006) +#define NPCX_ADCCS REG16(NPCX_ADC_BASE_ADDR + 0x008) /* NOTE: These are 1-based for the threshold detectors. */ -#define NPCX_THRCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x012 + (2L*(n))) -#define NPCX_THRCTS REG16(NPCX_ADC_BASE_ADDR + 0x01A) -#define NPCX_THR_DCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x038 + (2L*(n))) +#define NPCX_THRCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x012 + (2L * (n))) +#define NPCX_THRCTS REG16(NPCX_ADC_BASE_ADDR + 0x01A) +#define NPCX_THR_DCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x038 + (2L * (n))) /* NOTE: This is 0-based for the ADC channels. */ -#define NPCX_CHNDAT(n) REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L*(n))) -#define NPCX_ADCCNF2 REG16(NPCX_ADC_BASE_ADDR + 0x020) -#define NPCX_GENDLY REG16(NPCX_ADC_BASE_ADDR + 0x022) -#define NPCX_MEAST REG16(NPCX_ADC_BASE_ADDR + 0x026) +#define NPCX_CHNDAT(n) REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L * (n))) +#define NPCX_ADCCNF2 REG16(NPCX_ADC_BASE_ADDR + 0x020) +#define NPCX_GENDLY REG16(NPCX_ADC_BASE_ADDR + 0x022) +#define NPCX_MEAST REG16(NPCX_ADC_BASE_ADDR + 0x026) /* ADC register fields */ -#define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6) -#define NPCX_ATCTL_DLY_FIELD FIELD(8, 3) -#define NPCX_ASCADD_SADDR_FIELD FIELD(0, 5) -#define NPCX_ADCSTS_EOCEV 0 -#define NPCX_ADCCNF_ADCMD_FIELD FIELD(1, 2) -#define NPCX_ADCCNF_ADCRPTC 3 -#define NPCX_ADCCNF_INTECEN 6 -#define NPCX_ADCCNF_START 4 -#define NPCX_ADCCNF_ADCEN 0 -#define NPCX_ADCCNF_STOP 11 -#define NPCX_CHNDAT_CHDAT_FIELD FIELD(0, 10) -#define NPCX_CHNDAT_NEW 15 -#define NPCX_THRCTL_THEN 15 -#define NPCX_THRCTL_L_H 14 -#define NPCX_THRCTL_CHNSEL FIELD(10, 4) -#define NPCX_THRCTL_THRVAL FIELD(0, 10) -#define NPCX_THRCTS_ADC_WKEN 15 -#define NPCX_THRCTS_THR3_IEN 10 -#define NPCX_THRCTS_THR2_IEN 9 -#define NPCX_THRCTS_THR1_IEN 8 -#define NPCX_THRCTS_ADC_EVENT 7 -#define NPCX_THRCTS_THR3_STS 2 -#define NPCX_THRCTS_THR2_STS 1 -#define NPCX_THRCTS_THR1_STS 0 -#define NPCX_THR_DCTL_THRD_EN 15 -#define NPCX_THR_DCTL_THR_DVAL FIELD(0, 10) - -#define NPCX_ADC_THRESH1 1 -#define NPCX_ADC_THRESH2 2 -#define NPCX_ADC_THRESH3 3 -#define NPCX_ADC_THRESH_CNT 3 +#define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6) +#define NPCX_ATCTL_DLY_FIELD FIELD(8, 3) +#define NPCX_ASCADD_SADDR_FIELD FIELD(0, 5) +#define NPCX_ADCSTS_EOCEV 0 +#define NPCX_ADCCNF_ADCMD_FIELD FIELD(1, 2) +#define NPCX_ADCCNF_ADCRPTC 3 +#define NPCX_ADCCNF_INTECEN 6 +#define NPCX_ADCCNF_START 4 +#define NPCX_ADCCNF_ADCEN 0 +#define NPCX_ADCCNF_STOP 11 +#define NPCX_CHNDAT_CHDAT_FIELD FIELD(0, 10) +#define NPCX_CHNDAT_NEW 15 +#define NPCX_THRCTL_THEN 15 +#define NPCX_THRCTL_L_H 14 +#define NPCX_THRCTL_CHNSEL FIELD(10, 4) +#define NPCX_THRCTL_THRVAL FIELD(0, 10) +#define NPCX_THRCTS_ADC_WKEN 15 +#define NPCX_THRCTS_THR3_IEN 10 +#define NPCX_THRCTS_THR2_IEN 9 +#define NPCX_THRCTS_THR1_IEN 8 +#define NPCX_THRCTS_ADC_EVENT 7 +#define NPCX_THRCTS_THR3_STS 2 +#define NPCX_THRCTS_THR2_STS 1 +#define NPCX_THRCTS_THR1_STS 0 +#define NPCX_THR_DCTL_THRD_EN 15 +#define NPCX_THR_DCTL_THR_DVAL FIELD(0, 10) + +#define NPCX_ADC_THRESH1 1 +#define NPCX_ADC_THRESH2 2 +#define NPCX_ADC_THRESH3 3 +#define NPCX_ADC_THRESH_CNT 3 diff --git a/chip/npcx/registers-npcx7.h b/chip/npcx/registers-npcx7.h index 535abfbf0f..2a4334149f 100644 --- a/chip/npcx/registers-npcx7.h +++ b/chip/npcx/registers-npcx7.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -24,106 +24,104 @@ #endif /* NPCX-IRQ numbers */ -#define NPCX_IRQ0_NOUSED NPCX_IRQ_0 -#define NPCX_IRQ1_NOUSED NPCX_IRQ_1 -#define NPCX_IRQ_KBSCAN NPCX_IRQ_2 -#define NPCX_IRQ_PM_CHAN_OBE NPCX_IRQ_3 +#define NPCX_IRQ0_NOUSED NPCX_IRQ_0 +#define NPCX_IRQ1_NOUSED NPCX_IRQ_1 +#define NPCX_IRQ_KBSCAN NPCX_IRQ_2 +#define NPCX_IRQ_PM_CHAN_OBE NPCX_IRQ_3 #ifdef NPCX_WOV_SUPPORT -#define NPCX_IRQ4_NOUSED NPCX_IRQ_4 +#define NPCX_IRQ4_NOUSED NPCX_IRQ_4 #else -#define NPCX_IRQ_PECI NPCX_IRQ_4 +#define NPCX_IRQ_PECI NPCX_IRQ_4 #endif -#define NPCX_IRQ5_NOUSED NPCX_IRQ_5 -#define NPCX_IRQ_PORT80 NPCX_IRQ_6 -#define NPCX_IRQ_MTC_WKINTAD_0 NPCX_IRQ_7 -#define NPCX_IRQ_MTC NPCX_IRQ_MTC_WKINTAD_0 -#define NPCX_IRQ_SMB8 NPCX_IRQ_8 -#define NPCX_IRQ_MFT_1 NPCX_IRQ_9 -#define NPCX_IRQ_ADC NPCX_IRQ_10 -#define NPCX_IRQ_WKINTEFGH_0 NPCX_IRQ_11 -#define NPCX_IRQ_GDMA NPCX_IRQ_12 -#define NPCX_IRQ_SMB1 NPCX_IRQ_13 -#define NPCX_IRQ_SMB2 NPCX_IRQ_14 -#define NPCX_IRQ_WKINTC_0 NPCX_IRQ_15 -#define NPCX_IRQ_SMB7 NPCX_IRQ_16 -#define NPCX_IRQ_ITIM16_3 NPCX_IRQ_17 -#define NPCX_IRQ_SHI NPCX_IRQ_18 -#define NPCX_IRQ_ESPI NPCX_IRQ_18 -#define NPCX_IRQ_SMB5 NPCX_IRQ_19 -#define NPCX_IRQ_SMB6 NPCX_IRQ_20 -#define NPCX_IRQ_PS2 NPCX_IRQ_21 +#define NPCX_IRQ5_NOUSED NPCX_IRQ_5 +#define NPCX_IRQ_PORT80 NPCX_IRQ_6 +#define NPCX_IRQ_MTC_WKINTAD_0 NPCX_IRQ_7 +#define NPCX_IRQ_MTC NPCX_IRQ_MTC_WKINTAD_0 +#define NPCX_IRQ_SMB8 NPCX_IRQ_8 +#define NPCX_IRQ_MFT_1 NPCX_IRQ_9 +#define NPCX_IRQ_ADC NPCX_IRQ_10 +#define NPCX_IRQ_WKINTEFGH_0 NPCX_IRQ_11 +#define NPCX_IRQ_GDMA NPCX_IRQ_12 +#define NPCX_IRQ_SMB1 NPCX_IRQ_13 +#define NPCX_IRQ_SMB2 NPCX_IRQ_14 +#define NPCX_IRQ_WKINTC_0 NPCX_IRQ_15 +#define NPCX_IRQ_SMB7 NPCX_IRQ_16 +#define NPCX_IRQ_ITIM16_3 NPCX_IRQ_17 +#define NPCX_IRQ_SHI NPCX_IRQ_18 +#define NPCX_IRQ_ESPI NPCX_IRQ_18 +#define NPCX_IRQ_SMB5 NPCX_IRQ_19 +#define NPCX_IRQ_SMB6 NPCX_IRQ_20 +#define NPCX_IRQ_PS2 NPCX_IRQ_21 #ifdef NPCX_WOV_SUPPORT -#define NPCX_IRQ_WOV NPCX_IRQ_22 +#define NPCX_IRQ_WOV NPCX_IRQ_22 #else -#define NPCX_IRQ22_NOUSED NPCX_IRQ_22 +#define NPCX_IRQ22_NOUSED NPCX_IRQ_22 #endif -#define NPCX_IRQ_MFT_2 NPCX_IRQ_23 -#define NPCX_IRQ_SHM NPCX_IRQ_24 -#define NPCX_IRQ_KBC_IBF NPCX_IRQ_25 -#define NPCX_IRQ_PM_CHAN_IBF NPCX_IRQ_26 -#define NPCX_IRQ_ITIM16_2 NPCX_IRQ_27 -#define NPCX_IRQ_ITIM16_1 NPCX_IRQ_28 -#define NPCX_IRQ29_NOUSED NPCX_IRQ_29 -#define NPCX_IRQ30_NOUSED NPCX_IRQ_30 -#define NPCX_IRQ_TWD_WKINTB_0 NPCX_IRQ_31 -#define NPCX_IRQ_UART2 NPCX_IRQ_32 -#define NPCX_IRQ_UART NPCX_IRQ_33 -#define NPCX_IRQ34_NOUSED NPCX_IRQ_34 -#define NPCX_IRQ35_NOUSED NPCX_IRQ_35 -#define NPCX_IRQ_SMB3 NPCX_IRQ_36 -#define NPCX_IRQ_SMB4 NPCX_IRQ_37 -#define NPCX_IRQ38_NOUSED NPCX_IRQ_38 -#define NPCX_IRQ39_NOUSED NPCX_IRQ_39 -#define NPCX_IRQ40_NOUSED NPCX_IRQ_40 -#define NPCX_IRQ_MFT_3 NPCX_IRQ_41 -#define NPCX_IRQ42_NOUSED NPCX_IRQ_42 -#define NPCX_IRQ_ITIM16_4 NPCX_IRQ_43 -#define NPCX_IRQ_ITIM16_5 NPCX_IRQ_44 -#define NPCX_IRQ_ITIM16_6 NPCX_IRQ_45 -#define NPCX_IRQ_ITIM32 NPCX_IRQ_46 -#define NPCX_IRQ_WKINTA_1 NPCX_IRQ_47 -#define NPCX_IRQ_WKINTB_1 NPCX_IRQ_48 -#define NPCX_IRQ_KSI_WKINTC_1 NPCX_IRQ_49 -#define NPCX_IRQ_WKINTD_1 NPCX_IRQ_50 -#define NPCX_IRQ_WKINTE_1 NPCX_IRQ_51 -#define NPCX_IRQ_WKINTF_1 NPCX_IRQ_52 -#define NPCX_IRQ_WKINTG_1 NPCX_IRQ_53 -#define NPCX_IRQ_WKINTH_1 NPCX_IRQ_54 -#define NPCX_IRQ55_NOUSED NPCX_IRQ_55 -#define NPCX_IRQ_KBC_OBE NPCX_IRQ_56 -#define NPCX_IRQ_SPI NPCX_IRQ_57 +#define NPCX_IRQ_MFT_2 NPCX_IRQ_23 +#define NPCX_IRQ_SHM NPCX_IRQ_24 +#define NPCX_IRQ_KBC_IBF NPCX_IRQ_25 +#define NPCX_IRQ_PM_CHAN_IBF NPCX_IRQ_26 +#define NPCX_IRQ_ITIM16_2 NPCX_IRQ_27 +#define NPCX_IRQ_ITIM16_1 NPCX_IRQ_28 +#define NPCX_IRQ29_NOUSED NPCX_IRQ_29 +#define NPCX_IRQ30_NOUSED NPCX_IRQ_30 +#define NPCX_IRQ_TWD_WKINTB_0 NPCX_IRQ_31 +#define NPCX_IRQ_UART2 NPCX_IRQ_32 +#define NPCX_IRQ_UART NPCX_IRQ_33 +#define NPCX_IRQ34_NOUSED NPCX_IRQ_34 +#define NPCX_IRQ35_NOUSED NPCX_IRQ_35 +#define NPCX_IRQ_SMB3 NPCX_IRQ_36 +#define NPCX_IRQ_SMB4 NPCX_IRQ_37 +#define NPCX_IRQ38_NOUSED NPCX_IRQ_38 +#define NPCX_IRQ39_NOUSED NPCX_IRQ_39 +#define NPCX_IRQ40_NOUSED NPCX_IRQ_40 +#define NPCX_IRQ_MFT_3 NPCX_IRQ_41 +#define NPCX_IRQ42_NOUSED NPCX_IRQ_42 +#define NPCX_IRQ_ITIM16_4 NPCX_IRQ_43 +#define NPCX_IRQ_ITIM16_5 NPCX_IRQ_44 +#define NPCX_IRQ_ITIM16_6 NPCX_IRQ_45 +#define NPCX_IRQ_ITIM32 NPCX_IRQ_46 +#define NPCX_IRQ_WKINTA_1 NPCX_IRQ_47 +#define NPCX_IRQ_WKINTB_1 NPCX_IRQ_48 +#define NPCX_IRQ_KSI_WKINTC_1 NPCX_IRQ_49 +#define NPCX_IRQ_WKINTD_1 NPCX_IRQ_50 +#define NPCX_IRQ_WKINTE_1 NPCX_IRQ_51 +#define NPCX_IRQ_WKINTF_1 NPCX_IRQ_52 +#define NPCX_IRQ_WKINTG_1 NPCX_IRQ_53 +#define NPCX_IRQ_WKINTH_1 NPCX_IRQ_54 +#define NPCX_IRQ55_NOUSED NPCX_IRQ_55 +#define NPCX_IRQ_KBC_OBE NPCX_IRQ_56 +#define NPCX_IRQ_SPI NPCX_IRQ_57 #ifdef NPCX_ITIM64_SUPPORT -#define NPCX_IRQ_ITIM64 NPCX_IRQ_58 +#define NPCX_IRQ_ITIM64 NPCX_IRQ_58 #else -#define NPCX_IRQ58_NOUSED NPCX_IRQ_58 +#define NPCX_IRQ58_NOUSED NPCX_IRQ_58 #endif -#define NPCX_IRQ_WKINTFG_2 NPCX_IRQ_59 -#define NPCX_IRQ_WKINTA_2 NPCX_IRQ_60 -#define NPCX_IRQ_WKINTB_2 NPCX_IRQ_61 -#define NPCX_IRQ_WKINTC_2 NPCX_IRQ_62 -#define NPCX_IRQ_WKINTD_2 NPCX_IRQ_63 +#define NPCX_IRQ_WKINTFG_2 NPCX_IRQ_59 +#define NPCX_IRQ_WKINTA_2 NPCX_IRQ_60 +#define NPCX_IRQ_WKINTB_2 NPCX_IRQ_61 +#define NPCX_IRQ_WKINTC_2 NPCX_IRQ_62 +#define NPCX_IRQ_WKINTD_2 NPCX_IRQ_63 /* Modules Map */ /* Miscellaneous Device Control (MDC) registers */ -#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x007) +#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x007) /* MDC register fields */ -#define NPCX_FWCTRL_RO_REGION 0 -#define NPCX_FWCTRL_FW_SLOT 1 - -#define NPCX_ITIM32_BASE_ADDR 0x400BC000 -#define NPCX_CR_UART_BASE_ADDR(mdl) (0x400C4000 + ((mdl) * 0x2000L)) -#define NPCX_SMB_BASE_ADDR(mdl) (((mdl) < 2) ? \ - (0x40009000 + ((mdl) * 0x2000L)) : \ - ((mdl) < 4) ? \ - (0x400C0000 + (((mdl) - 2) * 0x2000L)) : \ - ((mdl) == 4) ? \ - (0x40008000) : \ - (0x40017000 + (((mdl) - 5) * 0x1000L))) - -#define NPCX_HFCBCD1 REG8(NPCX_HFCG_BASE_ADDR + 0x012) -#define NPCX_HFCBCD2 REG8(NPCX_HFCG_BASE_ADDR + 0x014) +#define NPCX_FWCTRL_RO_REGION 0 +#define NPCX_FWCTRL_FW_SLOT 1 + +#define NPCX_ITIM32_BASE_ADDR 0x400BC000 +#define NPCX_CR_UART_BASE_ADDR(mdl) (0x400C4000 + ((mdl)*0x2000L)) +#define NPCX_SMB_BASE_ADDR(mdl) \ + (((mdl) < 2) ? (0x40009000 + ((mdl)*0x2000L)) : \ + ((mdl) < 4) ? (0x400C0000 + (((mdl)-2) * 0x2000L)) : \ + ((mdl) == 4) ? (0x40008000) : \ + (0x40017000 + (((mdl)-5) * 0x1000L))) + +#define NPCX_HFCBCD1 REG8(NPCX_HFCG_BASE_ADDR + 0x012) +#define NPCX_HFCBCD2 REG8(NPCX_HFCG_BASE_ADDR + 0x014) enum { NPCX_UART_PORT0 = 0, /* UART port 0 */ @@ -135,44 +133,44 @@ enum { #ifdef NPCX_UART_FIFO_SUPPORT /* UART registers only used for FIFO mode */ -#define NPCX_UFTSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x020) -#define NPCX_UFRSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x022) -#define NPCX_UFTCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x024) -#define NPCX_UFRCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x026) +#define NPCX_UFTSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x020) +#define NPCX_UFRSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x022) +#define NPCX_UFTCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x024) +#define NPCX_UFRCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x026) /* UART FIFO register fields */ -#define NPCX_UMDSL_FIFO_MD 0 - -#define NPCX_UFTSTS_TEMPTY_LVL FIELD(0, 5) -#define NPCX_UFTSTS_TEMPTY_LVL_STS 5 -#define NPCX_UFTSTS_TFIFO_EMPTY_STS 6 -#define NPCX_UFTSTS_NXMIP 7 - -#define NPCX_UFRSTS_RFULL_LVL_STS 5 -#define NPCX_UFRSTS_RFIFO_NEMPTY_STS 6 -#define NPCX_UFRSTS_ERR 7 - -#define NPCX_UFTCTL_TEMPTY_LVL_SEL FIELD(0, 5) -#define NPCX_UFTCTL_TEMPTY_LVL_EN 5 -#define NPCX_UFTCTL_TEMPTY_EN 6 -#define NPCX_UFTCTL_NXMIPEN 7 - -#define NPCX_UFRCTL_RFULL_LVL_SEL FIELD(0, 5) -#define NPCX_UFRCTL_RFULL_LVL_EN 5 -#define NPCX_UFRCTL_RNEMPTY_EN 6 -#define NPCX_UFRCTL_ERR_EN 7 +#define NPCX_UMDSL_FIFO_MD 0 + +#define NPCX_UFTSTS_TEMPTY_LVL FIELD(0, 5) +#define NPCX_UFTSTS_TEMPTY_LVL_STS 5 +#define NPCX_UFTSTS_TFIFO_EMPTY_STS 6 +#define NPCX_UFTSTS_NXMIP 7 + +#define NPCX_UFRSTS_RFULL_LVL_STS 5 +#define NPCX_UFRSTS_RFIFO_NEMPTY_STS 6 +#define NPCX_UFRSTS_ERR 7 + +#define NPCX_UFTCTL_TEMPTY_LVL_SEL FIELD(0, 5) +#define NPCX_UFTCTL_TEMPTY_LVL_EN 5 +#define NPCX_UFTCTL_TEMPTY_EN 6 +#define NPCX_UFTCTL_NXMIPEN 7 + +#define NPCX_UFRCTL_RFULL_LVL_SEL FIELD(0, 5) +#define NPCX_UFRCTL_RFULL_LVL_EN 5 +#define NPCX_UFRCTL_RNEMPTY_EN 6 +#define NPCX_UFRCTL_ERR_EN 7 #endif /* KBSCAN register fields */ -#define NPCX_KBHDRV_FIELD FIELD(6, 2) +#define NPCX_KBHDRV_FIELD FIELD(6, 2) /* GLUE registers */ #ifdef NPCX_PSL_MODE_SUPPORT -#define NPCX_GLUE_PSL_CTS REG8(NPCX_GLUE_REGS_BASE + 0x027) +#define NPCX_GLUE_PSL_CTS REG8(NPCX_GLUE_REGS_BASE + 0x027) #endif /* GPIO registers */ -#define NPCX_PLOCK_CTL(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x007) +#define NPCX_PLOCK_CTL(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x007) /* System Configuration (SCFG) Registers */ @@ -197,112 +195,112 @@ enum { ALT_GROUP_COUNT }; -#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n)) +#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n)) -#define NPCX_LV_GPIO_CTL_ADDR(n) (((n) < 5) ? \ - (NPCX_SCFG_BASE_ADDR + 0x02A + (n)) :\ - (NPCX_SCFG_BASE_ADDR + 0x026)) -#define NPCX_LV_GPIO_CTL(n) REG8(NPCX_LV_GPIO_CTL_ADDR(n)) +#define NPCX_LV_GPIO_CTL_ADDR(n) \ + (((n) < 5) ? (NPCX_SCFG_BASE_ADDR + 0x02A + (n)) : \ + (NPCX_SCFG_BASE_ADDR + 0x026)) +#define NPCX_LV_GPIO_CTL(n) REG8(NPCX_LV_GPIO_CTL_ADDR(n)) /* pin-mux for I2C */ -#define NPCX_DEVALT2_I2C0_0_SL 0 -#define NPCX_DEVALT2_I2C7_0_SL 1 -#define NPCX_DEVALT2_I2C1_0_SL 2 -#define NPCX_DEVALT2_I2C6_0_SL 3 -#define NPCX_DEVALT2_I2C2_0_SL 4 -#define NPCX_DEVALT2_I2C5_0_SL 5 -#define NPCX_DEVALT2_I2C3_0_SL 6 -#define NPCX_DEVALT2_I2C4_0_SL 7 -#define NPCX_DEVALT6_I2C6_1_SL 5 -#define NPCX_DEVALT6_I2C5_1_SL 6 -#define NPCX_DEVALT6_I2C4_1_SL 7 +#define NPCX_DEVALT2_I2C0_0_SL 0 +#define NPCX_DEVALT2_I2C7_0_SL 1 +#define NPCX_DEVALT2_I2C1_0_SL 2 +#define NPCX_DEVALT2_I2C6_0_SL 3 +#define NPCX_DEVALT2_I2C2_0_SL 4 +#define NPCX_DEVALT2_I2C5_0_SL 5 +#define NPCX_DEVALT2_I2C3_0_SL 6 +#define NPCX_DEVALT2_I2C4_0_SL 7 +#define NPCX_DEVALT6_I2C6_1_SL 5 +#define NPCX_DEVALT6_I2C5_1_SL 6 +#define NPCX_DEVALT6_I2C4_1_SL 7 /* pin-mux for JTAG */ -#define NPCX_DEVALT5_NJEN1_EN 1 -#define NPCX_DEVALT5_NJEN0_EN 2 +#define NPCX_DEVALT5_NJEN1_EN 1 +#define NPCX_DEVALT5_NJEN0_EN 2 /* pin-mux for ADC */ -#define NPCX_DEVALTF_ADC5_SL 0 -#define NPCX_DEVALTF_ADC6_SL 1 -#define NPCX_DEVALTF_ADC7_SL 2 -#define NPCX_DEVALTF_ADC8_SL 3 -#define NPCX_DEVALTF_ADC9_SL 4 +#define NPCX_DEVALTF_ADC5_SL 0 +#define NPCX_DEVALTF_ADC6_SL 1 +#define NPCX_DEVALTF_ADC7_SL 2 +#define NPCX_DEVALTF_ADC8_SL 3 +#define NPCX_DEVALTF_ADC9_SL 4 /* pin-mux for PSL */ #ifdef NPCX_PSL_MODE_SUPPORT -#define NPCX_DEVALTD_PSL_IN1_AHI 0 -#define NPCX_DEVALTD_NPSL_IN1_SL 1 -#define NPCX_DEVALTD_PSL_IN2_AHI 2 -#define NPCX_DEVALTD_NPSL_IN2_SL 3 -#define NPCX_DEVALTD_PSL_IN3_AHI 4 -#define NPCX_DEVALTD_PSL_IN3_SL 5 -#define NPCX_DEVALTD_PSL_IN4_AHI 6 -#define NPCX_DEVALTD_PSL_IN4_SL 7 +#define NPCX_DEVALTD_PSL_IN1_AHI 0 +#define NPCX_DEVALTD_NPSL_IN1_SL 1 +#define NPCX_DEVALTD_PSL_IN2_AHI 2 +#define NPCX_DEVALTD_NPSL_IN2_SL 3 +#define NPCX_DEVALTD_PSL_IN3_AHI 4 +#define NPCX_DEVALTD_PSL_IN3_SL 5 +#define NPCX_DEVALTD_PSL_IN4_AHI 6 +#define NPCX_DEVALTD_PSL_IN4_SL 7 #endif #ifdef CHIP_VARIANT_NPCX7M6G /* External 32KHz crytal osc. input support */ -#define NPCX_DEVALTA_32KCLKIN_SL 3 +#define NPCX_DEVALTA_32KCLKIN_SL 3 #endif /* pin-mux for UART */ -#define NPCX_DEVALTA_UART_SL1 7 -#define NPCX_DEVALTC_UART_SL2 0 +#define NPCX_DEVALTA_UART_SL1 7 +#define NPCX_DEVALTC_UART_SL2 0 #ifdef NPCX_SECOND_UART /* Secondary UART selection */ -#define NPCX_DEVALTA_UART2_SL 5 +#define NPCX_DEVALTA_UART2_SL 5 #endif /* SHI module version 2 enable bit */ -#define NPCX_DEVALTF_SHI_NEW 7 +#define NPCX_DEVALTF_SHI_NEW 7 #ifdef NPCX_WOV_SUPPORT /* pin-mux for WoV */ -#define NPCX_DEVALTE_WOV_SL 0 -#define NPCX_DEVALTE_I2S_SL 1 -#define NPCX_DEVALTE_DMCLK_FAST 2 +#define NPCX_DEVALTE_WOV_SL 0 +#define NPCX_DEVALTE_I2S_SL 1 +#define NPCX_DEVALTE_DMCLK_FAST 2 #endif /* SMBus register fields */ -#define NPCX_SMBSEL_SMB4SEL 4 -#define NPCX_SMBSEL_SMB5SEL 5 -#define NPCX_SMBSEL_SMB6SEL 6 +#define NPCX_SMBSEL_SMB4SEL 4 +#define NPCX_SMBSEL_SMB5SEL 5 +#define NPCX_SMBSEL_SMB6SEL 6 /* SMB enumeration: I2C port definitions */ enum { - NPCX_I2C_PORT0_0 = 0, /* I2C port 0, bus 0 */ - NPCX_I2C_PORT1_0, /* I2C port 1, bus 0 */ - NPCX_I2C_PORT2_0, /* I2C port 2, bus 0 */ - NPCX_I2C_PORT3_0, /* I2C port 3, bus 0 */ + NPCX_I2C_PORT0_0 = 0, /* I2C port 0, bus 0 */ + NPCX_I2C_PORT1_0, /* I2C port 1, bus 0 */ + NPCX_I2C_PORT2_0, /* I2C port 2, bus 0 */ + NPCX_I2C_PORT3_0, /* I2C port 3, bus 0 */ #ifdef CHIP_VARIANT_NPCX7M6G - NPCX_I2C_PORT4_0, /* I2C port 4, bus 0 */ + NPCX_I2C_PORT4_0, /* I2C port 4, bus 0 */ #endif - NPCX_I2C_PORT4_1, /* I2C port 4, bus 1 */ - NPCX_I2C_PORT5_0, /* I2C port 5, bus 0 */ - NPCX_I2C_PORT5_1, /* I2C port 5, bus 1 */ - NPCX_I2C_PORT6_0, /* I2C port 6, bus 0 */ - NPCX_I2C_PORT6_1, /* I2C port 6, bus 1 */ - NPCX_I2C_PORT7_0, /* I2C port 7, bus 0 */ + NPCX_I2C_PORT4_1, /* I2C port 4, bus 1 */ + NPCX_I2C_PORT5_0, /* I2C port 5, bus 0 */ + NPCX_I2C_PORT5_1, /* I2C port 5, bus 1 */ + NPCX_I2C_PORT6_0, /* I2C port 6, bus 0 */ + NPCX_I2C_PORT6_1, /* I2C port 6, bus 1 */ + NPCX_I2C_PORT7_0, /* I2C port 7, bus 0 */ NPCX_I2C_COUNT, }; /* Power Management Controller (PMC) Registers */ -#define NPCX_FMUL_WIN_DLY REG8(NPCX_PMC_BASE_ADDR + 0x010) -#define NPCX_RAM_PD(offset) REG8(NPCX_PMC_BASE_ADDR + 0x020 + (offset)) +#define NPCX_FMUL_WIN_DLY REG8(NPCX_PMC_BASE_ADDR + 0x010) +#define NPCX_RAM_PD(offset) REG8(NPCX_PMC_BASE_ADDR + 0x020 + (offset)) /* PMC register fields */ -#define NPCX_PWDWN_CTL3_SMB4_PD 4 -#define NPCX_PWDWN_CTL7_SMB5_PD 0 -#define NPCX_PWDWN_CTL7_SMB6_PD 1 -#define NPCX_PWDWN_CTL7_SMB7_PD 2 +#define NPCX_PWDWN_CTL3_SMB4_PD 4 +#define NPCX_PWDWN_CTL7_SMB5_PD 0 +#define NPCX_PWDWN_CTL7_SMB6_PD 1 +#define NPCX_PWDWN_CTL7_SMB7_PD 2 #ifdef NPCX_ITIM64_SUPPORT -#define NPCX_PWDWN_CTL7_ITIM64_PD 5 +#define NPCX_PWDWN_CTL7_ITIM64_PD 5 #endif #ifdef NPCX_SECOND_UART -#define NPCX_PWDWN_CTL7_UART2_PD 6 +#define NPCX_PWDWN_CTL7_UART2_PD 6 #endif #ifdef NPCX_WOV_SUPPORT -#define NPCX_PWDWN_CTL7_WOV_PD 7 +#define NPCX_PWDWN_CTL7_WOV_PD 7 #endif /* @@ -328,7 +326,7 @@ enum { CGC_OFFSET_UART2 = 6, #endif #ifdef NPCX_WOV_SUPPORT - CGC_OFFSET_WOV = 6, + CGC_OFFSET_WOV = 6, #endif }; @@ -343,53 +341,52 @@ enum NPCX_PMC_PWDWN_CTL_T { NPCX_PMC_PWDWN_CNT, }; -#define CGC_I2C_MASK (BIT(NPCX_PWDWN_CTL3_SMB0_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB2_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB3_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB4_PD)) -#define CGC_I2C_MASK2 (BIT(NPCX_PWDWN_CTL7_SMB5_PD) | \ - BIT(NPCX_PWDWN_CTL7_SMB6_PD) | \ - BIT(NPCX_PWDWN_CTL7_SMB7_PD)) +#define CGC_I2C_MASK \ + (BIT(NPCX_PWDWN_CTL3_SMB0_PD) | BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \ + BIT(NPCX_PWDWN_CTL3_SMB2_PD) | BIT(NPCX_PWDWN_CTL3_SMB3_PD) | \ + BIT(NPCX_PWDWN_CTL3_SMB4_PD)) +#define CGC_I2C_MASK2 \ + (BIT(NPCX_PWDWN_CTL7_SMB5_PD) | BIT(NPCX_PWDWN_CTL7_SMB6_PD) | \ + BIT(NPCX_PWDWN_CTL7_SMB7_PD)) #ifdef NPCX_SECOND_UART -#define CGC_UART2_MASK BIT(NPCX_PWDWN_CTL7_UART2_PD) +#define CGC_UART2_MASK BIT(NPCX_PWDWN_CTL7_UART2_PD) #endif #ifdef NPCX_WOV_SUPPORT -#define CGC_WOV_MASK BIT(NPCX_PWDWN_CTL7_WOV_PD) +#define CGC_WOV_MASK BIT(NPCX_PWDWN_CTL7_WOV_PD) #endif /* BBRAM register fields */ -#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \ +#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \ defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \ defined(CHIP_VARIANT_NPCX7M7WC) -#define NPCX_BKUP_STS_VSBY_STS 1 -#define NPCX_BKUP_STS_VCC1_STS 0 -#define NPCX_BKUP_STS_ALL_MASK \ +#define NPCX_BKUP_STS_VSBY_STS 1 +#define NPCX_BKUP_STS_VCC1_STS 0 +#define NPCX_BKUP_STS_ALL_MASK \ (BIT(NPCX_BKUP_STS_IBBR) | BIT(NPCX_BKUP_STS_VSBY_STS) | \ - BIT(NPCX_BKUP_STS_VCC1_STS)) -#define NPCX_BBRAM_SIZE 128 /* Size of BBRAM */ + BIT(NPCX_BKUP_STS_VCC1_STS)) +#define NPCX_BBRAM_SIZE 128 /* Size of BBRAM */ #else #define NPCX_BKUP_STS_ALL_MASK BIT(NPCX_BKUP_STS_IBBR) -#define NPCX_BBRAM_SIZE 64 /* Size of BBRAM */ +#define NPCX_BBRAM_SIZE 64 /* Size of BBRAM */ #endif /* ITIM16 registers */ -#define NPCX_ITCNT8(n) REG8(NPCX_ITIM_BASE_ADDR(n) + 0x000) -#define NPCX_ITCNT16(n) REG16(NPCX_ITIM_BASE_ADDR(n) + 0x002) +#define NPCX_ITCNT8(n) REG8(NPCX_ITIM_BASE_ADDR(n) + 0x000) +#define NPCX_ITCNT16(n) REG16(NPCX_ITIM_BASE_ADDR(n) + 0x002) /* ITIM32 registers */ -#define NPCX_ITCNT32 REG32(NPCX_ITIM32_BASE_ADDR + 0x008) +#define NPCX_ITCNT32 REG32(NPCX_ITIM32_BASE_ADDR + 0x008) /* Timer counter register used for 1 micro-second system tick */ -#define NPCX_ITCNT_SYSTEM NPCX_ITCNT32 +#define NPCX_ITCNT_SYSTEM NPCX_ITCNT32 /* Timer counter register used for others */ -#define NPCX_ITCNT NPCX_ITCNT16 +#define NPCX_ITCNT NPCX_ITCNT16 /* ITIM module No. used for event */ -#define ITIM_EVENT_NO ITIM16_1 +#define ITIM_EVENT_NO ITIM16_1 /* ITIM module No. used for watchdog */ -#define ITIM_WDG_NO ITIM16_5 +#define ITIM_WDG_NO ITIM16_5 /* ITIM module No. used for 1 micro-second system tick */ -#define ITIM_SYSTEM_NO ITIM32 +#define ITIM_SYSTEM_NO ITIM32 /* ITIM enumeration */ enum ITIM_MODULE_T { @@ -404,56 +401,56 @@ enum ITIM_MODULE_T { }; /* Serial Host Interface (SHI) Registers - only available on SHI Version 2 */ -#define NPCX_SHICFG3 REG8(NPCX_SHI_BASE_ADDR + 0x00C) -#define NPCX_SHICFG4 REG8(NPCX_SHI_BASE_ADDR + 0x00D) -#define NPCX_SHICFG5 REG8(NPCX_SHI_BASE_ADDR + 0x00E) -#define NPCX_EVSTAT2 REG8(NPCX_SHI_BASE_ADDR + 0x00F) -#define NPCX_EVENABLE2 REG8(NPCX_SHI_BASE_ADDR + 0x010) -#define NPCX_OBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n)) -#define NPCX_IBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x0A0 + (n)) +#define NPCX_SHICFG3 REG8(NPCX_SHI_BASE_ADDR + 0x00C) +#define NPCX_SHICFG4 REG8(NPCX_SHI_BASE_ADDR + 0x00D) +#define NPCX_SHICFG5 REG8(NPCX_SHI_BASE_ADDR + 0x00E) +#define NPCX_EVSTAT2 REG8(NPCX_SHI_BASE_ADDR + 0x00F) +#define NPCX_EVENABLE2 REG8(NPCX_SHI_BASE_ADDR + 0x010) +#define NPCX_OBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n)) +#define NPCX_IBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x0A0 + (n)) /* SHI register fields */ -#define NPCX_SHICFG3_OBUFLVLDIS 7 -#define NPCX_SHICFG4_IBUFLVLDIS 7 -#define NPCX_SHICFG5_IBUFLVL2 FIELD(0, 6) -#define NPCX_SHICFG5_IBUFLVL2DIS 7 -#define NPCX_EVSTAT2_IBHF2 0 -#define NPCX_EVSTAT2_CSNRE 1 -#define NPCX_EVSTAT2_CSNFE 2 -#define NPCX_EVENABLE2_IBHF2EN 0 -#define NPCX_EVENABLE2_CSNREEN 1 -#define NPCX_EVENABLE2_CSNFEEN 2 +#define NPCX_SHICFG3_OBUFLVLDIS 7 +#define NPCX_SHICFG4_IBUFLVLDIS 7 +#define NPCX_SHICFG5_IBUFLVL2 FIELD(0, 6) +#define NPCX_SHICFG5_IBUFLVL2DIS 7 +#define NPCX_EVSTAT2_IBHF2 0 +#define NPCX_EVSTAT2_CSNRE 1 +#define NPCX_EVSTAT2_CSNFE 2 +#define NPCX_EVENABLE2_IBHF2EN 0 +#define NPCX_EVENABLE2_CSNREEN 1 +#define NPCX_EVENABLE2_CSNFEEN 2 /* eSPI register fields */ -#define NPCX_ESPIIE_BMTXDONEIE 19 -#define NPCX_ESPIIE_PBMRXIE 20 -#define NPCX_ESPIIE_PMSGRXIE 21 -#define NPCX_ESPIIE_BMBURSTERRIE 22 -#define NPCX_ESPIIE_BMBURSTDONEIE 23 - -#define NPCX_ESPIWE_PBMRXWE 20 -#define NPCX_ESPIWE_PMSGRXWE 21 - -#define NPCX_ESPISTS_VWUPDW 17 -#define NPCX_ESPISTS_BMTXDONE 19 -#define NPCX_ESPISTS_PBMRX 20 -#define NPCX_ESPISTS_PMSGRX 21 -#define NPCX_ESPISTS_BMBURSTERR 22 -#define NPCX_ESPISTS_BMBURSTDONE 23 -#define NPCX_ESPISTS_ESPIRST_LVL 24 - -#define ESPIIE_BMTXDONE BIT(NPCX_ESPIIE_BMTXDONEIE) -#define ESPIIE_PBMRX BIT(NPCX_ESPIIE_PBMRXIE) -#define ESPIIE_PMSGRX BIT(NPCX_ESPIIE_PMSGRXIE) -#define ESPIIE_BMBURSTERR BIT(NPCX_ESPIIE_BMBURSTERRIE) -#define ESPIIE_BMBURSTDONE BIT(NPCX_ESPIIE_BMBURSTDONEIE) - -#define ESPIWE_PBMRX BIT(NPCX_ESPIWE_PBMRXWE) -#define ESPIWE_PMSGRX BIT(NPCX_ESPIWE_PMSGRXWE) +#define NPCX_ESPIIE_BMTXDONEIE 19 +#define NPCX_ESPIIE_PBMRXIE 20 +#define NPCX_ESPIIE_PMSGRXIE 21 +#define NPCX_ESPIIE_BMBURSTERRIE 22 +#define NPCX_ESPIIE_BMBURSTDONEIE 23 + +#define NPCX_ESPIWE_PBMRXWE 20 +#define NPCX_ESPIWE_PMSGRXWE 21 + +#define NPCX_ESPISTS_VWUPDW 17 +#define NPCX_ESPISTS_BMTXDONE 19 +#define NPCX_ESPISTS_PBMRX 20 +#define NPCX_ESPISTS_PMSGRX 21 +#define NPCX_ESPISTS_BMBURSTERR 22 +#define NPCX_ESPISTS_BMBURSTDONE 23 +#define NPCX_ESPISTS_ESPIRST_LVL 24 + +#define ESPIIE_BMTXDONE BIT(NPCX_ESPIIE_BMTXDONEIE) +#define ESPIIE_PBMRX BIT(NPCX_ESPIIE_PBMRXIE) +#define ESPIIE_PMSGRX BIT(NPCX_ESPIIE_PMSGRXIE) +#define ESPIIE_BMBURSTERR BIT(NPCX_ESPIIE_BMBURSTERRIE) +#define ESPIIE_BMBURSTDONE BIT(NPCX_ESPIIE_BMBURSTDONEIE) + +#define ESPIWE_PBMRX BIT(NPCX_ESPIWE_PBMRXWE) +#define ESPIWE_PMSGRX BIT(NPCX_ESPIWE_PMSGRXWE) /* Bit field manipulation for VWEVMS Value */ -#define VWEVMS_WK_EN(e) (((e)<<20) & 0x00100000) -#define VWEVMS_INTWK_EN(e) (VWEVMS_INT_EN(e) | VWEVMS_WK_EN(e)) +#define VWEVMS_WK_EN(e) (((e) << 20) & 0x00100000) +#define VWEVMS_INTWK_EN(e) (VWEVMS_INT_EN(e) | VWEVMS_WK_EN(e)) /* eSPI max supported frequency */ enum { @@ -466,41 +463,41 @@ enum { /* eSPI max frequency support per FMCLK */ #if (FMCLK <= 33000000) -#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_33 +#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_33 #else -#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_50 +#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_50 #endif /* UART registers */ -#define NPCX_UART_WK_GROUP MIWU_GROUP_8 -#define NPCX_UART_WK_BIT 7 +#define NPCX_UART_WK_GROUP MIWU_GROUP_8 +#define NPCX_UART_WK_BIT 7 #ifdef NPCX_SECOND_UART -#define NPCX_UART2_WK_GROUP MIWU_GROUP_1 -#define NPCX_UART2_WK_BIT 6 +#define NPCX_UART2_WK_GROUP MIWU_GROUP_1 +#define NPCX_UART2_WK_BIT 6 #endif /* MIWU registers */ -#define NPCX_WKEDG_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x00 + \ - ((n) * 2L) + ((n) < 5 ? 0 : 0x1E)) -#define NPCX_WKAEDG_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x01 + \ - ((n) * 2L) + ((n) < 5 ? 0 : 0x1E)) -#define NPCX_WKPND_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x0A + \ - ((n) * 4L) + ((n) < 5 ? 0 : 0x10)) -#define NPCX_WKPCL_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x0C + \ - ((n) * 4L) + ((n) < 5 ? 0 : 0x10)) -#define NPCX_WKEN_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x1E + \ - ((n) * 2L) + ((n) < 5 ? 0 : 0x12)) -#define NPCX_WKINEN_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x1F + \ - ((n) * 2L) + ((n) < 5 ? 0 : 0x12)) -#define NPCX_WKMOD_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x70 + (n)) - -#define NPCX_WKEDG(port, n) REG8(NPCX_WKEDG_ADDR(port, n)) -#define NPCX_WKAEDG(port, n) REG8(NPCX_WKAEDG_ADDR(port, n)) -#define NPCX_WKPND(port, n) REG8(NPCX_WKPND_ADDR(port, n)) -#define NPCX_WKPCL(port, n) REG8(NPCX_WKPCL_ADDR(port, n)) -#define NPCX_WKEN(port, n) REG8(NPCX_WKEN_ADDR(port, n)) -#define NPCX_WKINEN(port, n) REG8(NPCX_WKINEN_ADDR(port, n)) -#define NPCX_WKMOD(port, n) REG8(NPCX_WKMOD_ADDR(port, n)) +#define NPCX_WKEDG_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x00 + ((n)*2L) + ((n) < 5 ? 0 : 0x1E)) +#define NPCX_WKAEDG_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x01 + ((n)*2L) + ((n) < 5 ? 0 : 0x1E)) +#define NPCX_WKPND_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x0A + ((n)*4L) + ((n) < 5 ? 0 : 0x10)) +#define NPCX_WKPCL_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x0C + ((n)*4L) + ((n) < 5 ? 0 : 0x10)) +#define NPCX_WKEN_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x1E + ((n)*2L) + ((n) < 5 ? 0 : 0x12)) +#define NPCX_WKINEN_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x1F + ((n)*2L) + ((n) < 5 ? 0 : 0x12)) +#define NPCX_WKMOD_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x70 + (n)) + +#define NPCX_WKEDG(port, n) REG8(NPCX_WKEDG_ADDR(port, n)) +#define NPCX_WKAEDG(port, n) REG8(NPCX_WKAEDG_ADDR(port, n)) +#define NPCX_WKPND(port, n) REG8(NPCX_WKPND_ADDR(port, n)) +#define NPCX_WKPCL(port, n) REG8(NPCX_WKPCL_ADDR(port, n)) +#define NPCX_WKEN(port, n) REG8(NPCX_WKEN_ADDR(port, n)) +#define NPCX_WKINEN(port, n) REG8(NPCX_WKINEN_ADDR(port, n)) +#define NPCX_WKMOD(port, n) REG8(NPCX_WKMOD_ADDR(port, n)) /* UART registers and functions */ #if NPCX_UART_MODULE2 @@ -508,64 +505,64 @@ enum { * To be used as 2nd parameter to NPCX_WK*() macro, table (1st parameter) is * always 1 == MIWU_TABLE_1. */ -#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTG_1 -#define NPCX_UART_DEVALT NPCX_DEVALT(0x0C) -#define NPCX_UART_DEVALT_SL NPCX_DEVALTC_UART_SL2 -#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0A) -#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTA_UART_SL1 +#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTG_1 +#define NPCX_UART_DEVALT NPCX_DEVALT(0x0C) +#define NPCX_UART_DEVALT_SL NPCX_DEVALTC_UART_SL2 +#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0A) +#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTA_UART_SL1 #else /* !NPCX_UART_MODULE2 */ -#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTB_1 -#define NPCX_UART_DEVALT NPCX_DEVALT(0x0A) -#define NPCX_UART_DEVALT_SL NPCX_DEVALTA_UART_SL1 -#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0C) -#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTC_UART_SL2 +#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTB_1 +#define NPCX_UART_DEVALT NPCX_DEVALT(0x0A) +#define NPCX_UART_DEVALT_SL NPCX_DEVALTA_UART_SL1 +#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0C) +#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTC_UART_SL2 #endif /* NPCX_UART_MODULE2 */ /* ADC Registers */ -#define NPCX_ADCSTS REG16(NPCX_ADC_BASE_ADDR + 0x000) -#define NPCX_ADCCNF REG16(NPCX_ADC_BASE_ADDR + 0x002) -#define NPCX_ATCTL REG16(NPCX_ADC_BASE_ADDR + 0x004) -#define NPCX_ASCADD REG16(NPCX_ADC_BASE_ADDR + 0x006) -#define NPCX_ADCCS REG16(NPCX_ADC_BASE_ADDR + 0x008) +#define NPCX_ADCSTS REG16(NPCX_ADC_BASE_ADDR + 0x000) +#define NPCX_ADCCNF REG16(NPCX_ADC_BASE_ADDR + 0x002) +#define NPCX_ATCTL REG16(NPCX_ADC_BASE_ADDR + 0x004) +#define NPCX_ASCADD REG16(NPCX_ADC_BASE_ADDR + 0x006) +#define NPCX_ADCCS REG16(NPCX_ADC_BASE_ADDR + 0x008) /* NOTE: These are 1-based for the threshold detectors. */ -#define NPCX_THRCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x012 + (2L*(n))) -#define NPCX_THRCTS REG16(NPCX_ADC_BASE_ADDR + 0x01A) -#define NPCX_THR_DCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x038 + (2L*(n))) +#define NPCX_THRCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x012 + (2L * (n))) +#define NPCX_THRCTS REG16(NPCX_ADC_BASE_ADDR + 0x01A) +#define NPCX_THR_DCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x038 + (2L * (n))) /* NOTE: This is 0-based for the ADC channels. */ -#define NPCX_CHNDAT(n) REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L*(n))) -#define NPCX_ADCCNF2 REG16(NPCX_ADC_BASE_ADDR + 0x020) -#define NPCX_GENDLY REG16(NPCX_ADC_BASE_ADDR + 0x022) -#define NPCX_MEAST REG16(NPCX_ADC_BASE_ADDR + 0x026) +#define NPCX_CHNDAT(n) REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L * (n))) +#define NPCX_ADCCNF2 REG16(NPCX_ADC_BASE_ADDR + 0x020) +#define NPCX_GENDLY REG16(NPCX_ADC_BASE_ADDR + 0x022) +#define NPCX_MEAST REG16(NPCX_ADC_BASE_ADDR + 0x026) /* ADC register fields */ -#define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6) -#define NPCX_ATCTL_DLY_FIELD FIELD(8, 3) -#define NPCX_ASCADD_SADDR_FIELD FIELD(0, 5) -#define NPCX_ADCSTS_EOCEV 0 -#define NPCX_ADCCNF_ADCMD_FIELD FIELD(1, 2) -#define NPCX_ADCCNF_ADCRPTC 3 -#define NPCX_ADCCNF_INTECEN 6 -#define NPCX_ADCCNF_START 4 -#define NPCX_ADCCNF_ADCEN 0 -#define NPCX_ADCCNF_STOP 11 -#define NPCX_CHNDAT_CHDAT_FIELD FIELD(0, 10) -#define NPCX_CHNDAT_NEW 15 -#define NPCX_THRCTL_THEN 15 -#define NPCX_THRCTL_L_H 14 -#define NPCX_THRCTL_CHNSEL FIELD(10, 4) -#define NPCX_THRCTL_THRVAL FIELD(0, 10) -#define NPCX_THRCTS_ADC_WKEN 15 -#define NPCX_THRCTS_THR3_IEN 10 -#define NPCX_THRCTS_THR2_IEN 9 -#define NPCX_THRCTS_THR1_IEN 8 -#define NPCX_THRCTS_ADC_EVENT 7 -#define NPCX_THRCTS_THR3_STS 2 -#define NPCX_THRCTS_THR2_STS 1 -#define NPCX_THRCTS_THR1_STS 0 -#define NPCX_THR_DCTL_THRD_EN 15 -#define NPCX_THR_DCTL_THR_DVAL FIELD(0, 10) - -#define NPCX_ADC_THRESH1 1 -#define NPCX_ADC_THRESH2 2 -#define NPCX_ADC_THRESH3 3 -#define NPCX_ADC_THRESH_CNT 3 +#define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6) +#define NPCX_ATCTL_DLY_FIELD FIELD(8, 3) +#define NPCX_ASCADD_SADDR_FIELD FIELD(0, 5) +#define NPCX_ADCSTS_EOCEV 0 +#define NPCX_ADCCNF_ADCMD_FIELD FIELD(1, 2) +#define NPCX_ADCCNF_ADCRPTC 3 +#define NPCX_ADCCNF_INTECEN 6 +#define NPCX_ADCCNF_START 4 +#define NPCX_ADCCNF_ADCEN 0 +#define NPCX_ADCCNF_STOP 11 +#define NPCX_CHNDAT_CHDAT_FIELD FIELD(0, 10) +#define NPCX_CHNDAT_NEW 15 +#define NPCX_THRCTL_THEN 15 +#define NPCX_THRCTL_L_H 14 +#define NPCX_THRCTL_CHNSEL FIELD(10, 4) +#define NPCX_THRCTL_THRVAL FIELD(0, 10) +#define NPCX_THRCTS_ADC_WKEN 15 +#define NPCX_THRCTS_THR3_IEN 10 +#define NPCX_THRCTS_THR2_IEN 9 +#define NPCX_THRCTS_THR1_IEN 8 +#define NPCX_THRCTS_ADC_EVENT 7 +#define NPCX_THRCTS_THR3_STS 2 +#define NPCX_THRCTS_THR2_STS 1 +#define NPCX_THRCTS_THR1_STS 0 +#define NPCX_THR_DCTL_THRD_EN 15 +#define NPCX_THR_DCTL_THR_DVAL FIELD(0, 10) + +#define NPCX_ADC_THRESH1 1 +#define NPCX_ADC_THRESH2 2 +#define NPCX_ADC_THRESH3 3 +#define NPCX_ADC_THRESH_CNT 3 diff --git a/chip/npcx/registers-npcx9.h b/chip/npcx/registers-npcx9.h index 2f2a22405a..11cac561d7 100644 --- a/chip/npcx/registers-npcx9.h +++ b/chip/npcx/registers-npcx9.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,157 +19,155 @@ #endif /* NPCX-IRQ numbers */ -#define NPCX_IRQ0_NOUSED NPCX_IRQ_0 -#define NPCX_IRQ1_NOUSED NPCX_IRQ_1 -#define NPCX_IRQ_KBSCAN NPCX_IRQ_2 -#define NPCX_IRQ_PM_CHAN_OBE NPCX_IRQ_3 -#define NPCX_IRQ_PECI NPCX_IRQ_4 -#define NPCX_IRQ_MTC_WKINTD_0 NPCX_IRQ_5 -#define NPCX_IRQ_MTC NPCX_IRQ_MTC_WKINTD_0 -#define NPCX_IRQ_PORT80 NPCX_IRQ_6 -#define NPCX_IRQ_CR_SIN2_WKINTA_0 NPCX_IRQ_7 -#define NPCX_IRQ_SMB8 NPCX_IRQ_8 -#define NPCX_IRQ_MFT_1 NPCX_IRQ_9 -#define NPCX_IRQ_ADC NPCX_IRQ_10 -#define NPCX_IRQ_WKINTE_0 NPCX_IRQ_11 -#define NPCX_IRQ_GDMA NPCX_IRQ_12 -#define NPCX_IRQ_SMB1 NPCX_IRQ_13 -#define NPCX_IRQ_SMB2 NPCX_IRQ_14 -#define NPCX_IRQ_WKINTC_0 NPCX_IRQ_15 -#define NPCX_IRQ_SMB7 NPCX_IRQ_16 -#define NPCX_IRQ_ITIM32_3 NPCX_IRQ_17 -#define NPCX_IRQ_SHI NPCX_IRQ_18 -#define NPCX_IRQ_ESPI NPCX_IRQ_18 -#define NPCX_IRQ_SMB5 NPCX_IRQ_19 -#define NPCX_IRQ_SMB6 NPCX_IRQ_20 -#define NPCX_IRQ_PS2 NPCX_IRQ_21 -#define NPCX_IRQ22_NOUSED NPCX_IRQ_22 -#define NPCX_IRQ_MFT_2 NPCX_IRQ_23 -#define NPCX_IRQ_SHM NPCX_IRQ_24 -#define NPCX_IRQ_KBC_IBF NPCX_IRQ_25 -#define NPCX_IRQ_PM_CHAN_IBF NPCX_IRQ_26 -#define NPCX_IRQ_ITIM32_2 NPCX_IRQ_27 -#define NPCX_IRQ_ITIM32_1 NPCX_IRQ_28 -#define NPCX_I3C_MDMA5 NPCX_IRQ_29 -#define NPCX_IRQ30_NOUSED NPCX_IRQ_30 -#define NPCX_IRQ_TWD_WKINTB_0 NPCX_IRQ_31 -#define NPCX_IRQ_UART2 NPCX_IRQ_32 -#define NPCX_IRQ_UART NPCX_IRQ_33 -#define NPCX_IRQ34_NOUSED NPCX_IRQ_34 -#define NPCX_IRQ_WKINTF_0 NPCX_IRQ_35 -#define NPCX_IRQ_SMB3 NPCX_IRQ_36 -#define NPCX_IRQ_SMB4 NPCX_IRQ_37 -#define NPCX_IRQ_UART3 NPCX_IRQ_38 -#define NPCX_IRQ_UART4 NPCX_IRQ_39 -#define NPCX_IRQ40_NOUSED NPCX_IRQ_40 -#define NPCX_IRQ_MFT_3 NPCX_IRQ_41 -#define NPCX_IRQ_WKINTG_0 NPCX_IRQ_42 -#define NPCX_IRQ_ITIM32_4 NPCX_IRQ_43 -#define NPCX_IRQ_ITIM32_5 NPCX_IRQ_44 -#define NPCX_IRQ_ITIM32_6 NPCX_IRQ_45 -#define NPCX_IRQ_WKINTH_0 NPCX_IRQ_46 -#define NPCX_IRQ_WKINTA_1 NPCX_IRQ_47 -#define NPCX_IRQ_WKINTB_1 NPCX_IRQ_48 -#define NPCX_IRQ_KSI_WKINTC_1 NPCX_IRQ_49 -#define NPCX_IRQ_WKINTD_1 NPCX_IRQ_50 -#define NPCX_IRQ_WKINTE_1 NPCX_IRQ_51 -#define NPCX_IRQ_WKINTF_1 NPCX_IRQ_52 -#define NPCX_IRQ_WKINTG_1 NPCX_IRQ_53 -#define NPCX_IRQ_WKINTH_1 NPCX_IRQ_54 -#define NPCX_WKINTG_2 NPCX_IRQ_55 -#define NPCX_IRQ_KBC_OBE NPCX_IRQ_56 -#define NPCX_IRQ_SPI NPCX_IRQ_57 -#define NPCX_IRQ_ITIM64 NPCX_IRQ_58 -#define NPCX_IRQ_LCT_WKINTF_2 NPCX_IRQ_59 -#define NPCX_IRQ_WKINTA_2 NPCX_IRQ_60 -#define NPCX_IRQ_WKINTB_2 NPCX_IRQ_61 -#define NPCX_IRQ_WKINTC_2 NPCX_IRQ_62 -#define NPCX_IRQ_WKINTD_2 NPCX_IRQ_63 +#define NPCX_IRQ0_NOUSED NPCX_IRQ_0 +#define NPCX_IRQ1_NOUSED NPCX_IRQ_1 +#define NPCX_IRQ_KBSCAN NPCX_IRQ_2 +#define NPCX_IRQ_PM_CHAN_OBE NPCX_IRQ_3 +#define NPCX_IRQ_PECI NPCX_IRQ_4 +#define NPCX_IRQ_MTC_WKINTD_0 NPCX_IRQ_5 +#define NPCX_IRQ_MTC NPCX_IRQ_MTC_WKINTD_0 +#define NPCX_IRQ_PORT80 NPCX_IRQ_6 +#define NPCX_IRQ_CR_SIN2_WKINTA_0 NPCX_IRQ_7 +#define NPCX_IRQ_SMB8 NPCX_IRQ_8 +#define NPCX_IRQ_MFT_1 NPCX_IRQ_9 +#define NPCX_IRQ_ADC NPCX_IRQ_10 +#define NPCX_IRQ_WKINTE_0 NPCX_IRQ_11 +#define NPCX_IRQ_GDMA NPCX_IRQ_12 +#define NPCX_IRQ_SMB1 NPCX_IRQ_13 +#define NPCX_IRQ_SMB2 NPCX_IRQ_14 +#define NPCX_IRQ_WKINTC_0 NPCX_IRQ_15 +#define NPCX_IRQ_SMB7 NPCX_IRQ_16 +#define NPCX_IRQ_ITIM32_3 NPCX_IRQ_17 +#define NPCX_IRQ_SHI NPCX_IRQ_18 +#define NPCX_IRQ_ESPI NPCX_IRQ_18 +#define NPCX_IRQ_SMB5 NPCX_IRQ_19 +#define NPCX_IRQ_SMB6 NPCX_IRQ_20 +#define NPCX_IRQ_PS2 NPCX_IRQ_21 +#define NPCX_IRQ22_NOUSED NPCX_IRQ_22 +#define NPCX_IRQ_MFT_2 NPCX_IRQ_23 +#define NPCX_IRQ_SHM NPCX_IRQ_24 +#define NPCX_IRQ_KBC_IBF NPCX_IRQ_25 +#define NPCX_IRQ_PM_CHAN_IBF NPCX_IRQ_26 +#define NPCX_IRQ_ITIM32_2 NPCX_IRQ_27 +#define NPCX_IRQ_ITIM32_1 NPCX_IRQ_28 +#define NPCX_I3C_MDMA5 NPCX_IRQ_29 +#define NPCX_IRQ30_NOUSED NPCX_IRQ_30 +#define NPCX_IRQ_TWD_WKINTB_0 NPCX_IRQ_31 +#define NPCX_IRQ_UART2 NPCX_IRQ_32 +#define NPCX_IRQ_UART NPCX_IRQ_33 +#define NPCX_IRQ34_NOUSED NPCX_IRQ_34 +#define NPCX_IRQ_WKINTF_0 NPCX_IRQ_35 +#define NPCX_IRQ_SMB3 NPCX_IRQ_36 +#define NPCX_IRQ_SMB4 NPCX_IRQ_37 +#define NPCX_IRQ_UART3 NPCX_IRQ_38 +#define NPCX_IRQ_UART4 NPCX_IRQ_39 +#define NPCX_IRQ40_NOUSED NPCX_IRQ_40 +#define NPCX_IRQ_MFT_3 NPCX_IRQ_41 +#define NPCX_IRQ_WKINTG_0 NPCX_IRQ_42 +#define NPCX_IRQ_ITIM32_4 NPCX_IRQ_43 +#define NPCX_IRQ_ITIM32_5 NPCX_IRQ_44 +#define NPCX_IRQ_ITIM32_6 NPCX_IRQ_45 +#define NPCX_IRQ_WKINTH_0 NPCX_IRQ_46 +#define NPCX_IRQ_WKINTA_1 NPCX_IRQ_47 +#define NPCX_IRQ_WKINTB_1 NPCX_IRQ_48 +#define NPCX_IRQ_KSI_WKINTC_1 NPCX_IRQ_49 +#define NPCX_IRQ_WKINTD_1 NPCX_IRQ_50 +#define NPCX_IRQ_WKINTE_1 NPCX_IRQ_51 +#define NPCX_IRQ_WKINTF_1 NPCX_IRQ_52 +#define NPCX_IRQ_WKINTG_1 NPCX_IRQ_53 +#define NPCX_IRQ_WKINTH_1 NPCX_IRQ_54 +#define NPCX_WKINTG_2 NPCX_IRQ_55 +#define NPCX_IRQ_KBC_OBE NPCX_IRQ_56 +#define NPCX_IRQ_SPI NPCX_IRQ_57 +#define NPCX_IRQ_ITIM64 NPCX_IRQ_58 +#define NPCX_IRQ_LCT_WKINTF_2 NPCX_IRQ_59 +#define NPCX_IRQ_WKINTA_2 NPCX_IRQ_60 +#define NPCX_IRQ_WKINTB_2 NPCX_IRQ_61 +#define NPCX_IRQ_WKINTC_2 NPCX_IRQ_62 +#define NPCX_IRQ_WKINTD_2 NPCX_IRQ_63 /* MIWU definition */ -#define LCT_WUI_GROUP MIWU_GROUP_6 -#define LCT_WUI_MASK MASK_PIN7 +#define LCT_WUI_GROUP MIWU_GROUP_6 +#define LCT_WUI_MASK MASK_PIN7 /* Modules Map */ /* Miscellaneous Device Control (MDC) registers */ -#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x009) +#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x009) /* MDC register fields */ -#define NPCX_FWCTRL_RO_REGION 6 -#define NPCX_FWCTRL_FW_SLOT 7 - -#define NPCX_CR_UART_BASE_ADDR(mdl) (0x400E0000 + ((mdl) * 0x2000L)) -#define NPCX_LCT_BASE_ADDR 0x400D7000 -#define NPCX_SMB_BASE_ADDR(mdl) (((mdl) < 2) ? \ - (0x40009000 + ((mdl) * 0x2000L)) : \ - ((mdl) < 4) ? \ - (0x400C0000 + (((mdl) - 2) * 0x2000L)) : \ - ((mdl) == 4) ? \ - (0x40008000) : \ - (0x40017000 + (((mdl) - 5) * 0x1000L))) - -#define NPCX_HFCBCD1 REG8(NPCX_HFCG_BASE_ADDR + 0x012) -#define NPCX_HFCBCD2 REG8(NPCX_HFCG_BASE_ADDR + 0x014) +#define NPCX_FWCTRL_RO_REGION 6 +#define NPCX_FWCTRL_FW_SLOT 7 + +#define NPCX_CR_UART_BASE_ADDR(mdl) (0x400E0000 + ((mdl)*0x2000L)) +#define NPCX_LCT_BASE_ADDR 0x400D7000 +#define NPCX_SMB_BASE_ADDR(mdl) \ + (((mdl) < 2) ? (0x40009000 + ((mdl)*0x2000L)) : \ + ((mdl) < 4) ? (0x400C0000 + (((mdl)-2) * 0x2000L)) : \ + ((mdl) == 4) ? (0x40008000) : \ + (0x40017000 + (((mdl)-5) * 0x1000L))) + +#define NPCX_HFCBCD1 REG8(NPCX_HFCG_BASE_ADDR + 0x012) +#define NPCX_HFCBCD2 REG8(NPCX_HFCG_BASE_ADDR + 0x014) enum { - NPCX_UART_PORT0 = 0, /* UART port 0 */ - NPCX_UART_PORT1 = 1, /* UART port 1 */ - NPCX_UART_PORT2 = 2, /* UART port 2 */ - NPCX_UART_PORT3 = 3, /* UART port 3 */ + NPCX_UART_PORT0 = 0, /* UART port 0 */ + NPCX_UART_PORT1 = 1, /* UART port 1 */ + NPCX_UART_PORT2 = 2, /* UART port 2 */ + NPCX_UART_PORT3 = 3, /* UART port 3 */ NPCX_UART_COUNT }; - /* UART registers only used for FIFO mode */ -#define NPCX_UFTSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x020) -#define NPCX_UFRSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x022) -#define NPCX_UFTCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x024) -#define NPCX_UFRCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x026) +/* UART registers only used for FIFO mode */ +#define NPCX_UFTSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x020) +#define NPCX_UFRSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x022) +#define NPCX_UFTCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x024) +#define NPCX_UFRCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x026) /* UART FIFO register fields */ -#define NPCX_UMDSL_FIFO_MD 0 +#define NPCX_UMDSL_FIFO_MD 0 -#define NPCX_UFTSTS_TEMPTY_LVL FIELD(0, 5) -#define NPCX_UFTSTS_TEMPTY_LVL_STS 5 -#define NPCX_UFTSTS_TFIFO_EMPTY_STS 6 -#define NPCX_UFTSTS_NXMIP 7 +#define NPCX_UFTSTS_TEMPTY_LVL FIELD(0, 5) +#define NPCX_UFTSTS_TEMPTY_LVL_STS 5 +#define NPCX_UFTSTS_TFIFO_EMPTY_STS 6 +#define NPCX_UFTSTS_NXMIP 7 -#define NPCX_UFRSTS_RFULL_LVL_STS 5 -#define NPCX_UFRSTS_RFIFO_NEMPTY_STS 6 -#define NPCX_UFRSTS_ERR 7 +#define NPCX_UFRSTS_RFULL_LVL_STS 5 +#define NPCX_UFRSTS_RFIFO_NEMPTY_STS 6 +#define NPCX_UFRSTS_ERR 7 -#define NPCX_UFTCTL_TEMPTY_LVL_SEL FIELD(0, 5) -#define NPCX_UFTCTL_TEMPTY_LVL_EN 5 -#define NPCX_UFTCTL_TEMPTY_EN 6 -#define NPCX_UFTCTL_NXMIPEN 7 +#define NPCX_UFTCTL_TEMPTY_LVL_SEL FIELD(0, 5) +#define NPCX_UFTCTL_TEMPTY_LVL_EN 5 +#define NPCX_UFTCTL_TEMPTY_EN 6 +#define NPCX_UFTCTL_NXMIPEN 7 -#define NPCX_UFRCTL_RFULL_LVL_SEL FIELD(0, 5) -#define NPCX_UFRCTL_RFULL_LVL_EN 5 -#define NPCX_UFRCTL_RNEMPTY_EN 6 -#define NPCX_UFRCTL_ERR_EN 7 +#define NPCX_UFRCTL_RFULL_LVL_SEL FIELD(0, 5) +#define NPCX_UFRCTL_RFULL_LVL_EN 5 +#define NPCX_UFRCTL_RNEMPTY_EN 6 +#define NPCX_UFRCTL_ERR_EN 7 /* KBSCAN register fields */ -#define NPCX_KBHDRV_FIELD FIELD(6, 2) +#define NPCX_KBHDRV_FIELD FIELD(6, 2) /* GLUE registers */ -#define NPCX_GLUE_PSL_CTS REG8(NPCX_GLUE_REGS_BASE + 0x027) -#define NPCX_GLUE_PSL_MCTL1 REG8(NPCX_GLUE_REGS_BASE + 0x034) -#define NPCX_GLUE_PSL_MCTL2 REG8(NPCX_GLUE_REGS_BASE + 0x038) +#define NPCX_GLUE_PSL_CTS REG8(NPCX_GLUE_REGS_BASE + 0x027) +#define NPCX_GLUE_PSL_MCTL1 REG8(NPCX_GLUE_REGS_BASE + 0x034) +#define NPCX_GLUE_PSL_MCTL2 REG8(NPCX_GLUE_REGS_BASE + 0x038) /* PSL register fields */ -#define NPCX_GLUE_PSL_MCTL1_VCC1_RST_PSL 7 -#define NPCX_GLUE_PSL_MCTL1_PSL_GPO_CTL 6 -#define NPCX_GLUE_PSL_MCTL1_LCT_EV 4 -#define NPCX_GLUE_PSL_MCTL1_VCC1_RST_EV 3 -#define NPCX_GLUE_PSL_MCTL1_PLS_EN 1 -#define NPCX_GLUE_PSL_MCTL1_OD_EN 0 - -#define NPCX_GLUE_PSL_MCTL2_VCC1_RST_PSL_LK 7 -#define NPCX_GLUE_PSL_MCTL2_PSL_GP_EN 6 -#define NPCX_GLUE_PSL_MCTL2_AC_IN_BLOCK_EN 3 -#define NPCX_GLUE_PSL_MCTL2_AC_IN_SEL FIELD(0, 1) +#define NPCX_GLUE_PSL_MCTL1_VCC1_RST_PSL 7 +#define NPCX_GLUE_PSL_MCTL1_PSL_GPO_CTL 6 +#define NPCX_GLUE_PSL_MCTL1_LCT_EV 4 +#define NPCX_GLUE_PSL_MCTL1_VCC1_RST_EV 3 +#define NPCX_GLUE_PSL_MCTL1_PLS_EN 1 +#define NPCX_GLUE_PSL_MCTL1_OD_EN 0 + +#define NPCX_GLUE_PSL_MCTL2_VCC1_RST_PSL_LK 7 +#define NPCX_GLUE_PSL_MCTL2_PSL_GP_EN 6 +#define NPCX_GLUE_PSL_MCTL2_AC_IN_BLOCK_EN 3 +#define NPCX_GLUE_PSL_MCTL2_AC_IN_SEL FIELD(0, 1) /* GPIO registers */ -#define NPCX_PLOCK_CTL(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x007) +#define NPCX_PLOCK_CTL(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x007) /* System Configuration (SCFG) Registers */ @@ -197,105 +195,105 @@ enum { ALT_GROUP_COUNT }; -#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n)) +#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n)) -#define NPCX_LV_GPIO_CTL_ADDR(n) (((n) < 5) ? \ - (NPCX_SCFG_BASE_ADDR + 0x02A + (n)) :\ - (NPCX_SCFG_BASE_ADDR + 0x026)) -#define NPCX_LV_GPIO_CTL(n) REG8(NPCX_LV_GPIO_CTL_ADDR(n)) +#define NPCX_LV_GPIO_CTL_ADDR(n) \ + (((n) < 5) ? (NPCX_SCFG_BASE_ADDR + 0x02A + (n)) : \ + (NPCX_SCFG_BASE_ADDR + 0x026)) +#define NPCX_LV_GPIO_CTL(n) REG8(NPCX_LV_GPIO_CTL_ADDR(n)) /* Device Alternate Function Lock */ -#define NPCX_DEVALT_LK(n) REG8(NPCX_SCFG_BASE_ADDR + 0x210 + (n)) +#define NPCX_DEVALT_LK(n) REG8(NPCX_SCFG_BASE_ADDR + 0x210 + (n)) /* pin-mux for I2C */ -#define NPCX_DEVALT2_I2C0_0_SL 0 -#define NPCX_DEVALT2_I2C7_0_SL 1 -#define NPCX_DEVALT2_I2C1_0_SL 2 -#define NPCX_DEVALT2_I2C6_0_SL 3 -#define NPCX_DEVALT2_I2C2_0_SL 4 -#define NPCX_DEVALT2_I2C5_0_SL 5 -#define NPCX_DEVALT2_I2C3_0_SL 6 -#define NPCX_DEVALT6_I2C6_1_SL 5 -#define NPCX_DEVALT6_I2C5_1_SL 6 -#define NPCX_DEVALT6_I2C4_1_SL 7 +#define NPCX_DEVALT2_I2C0_0_SL 0 +#define NPCX_DEVALT2_I2C7_0_SL 1 +#define NPCX_DEVALT2_I2C1_0_SL 2 +#define NPCX_DEVALT2_I2C6_0_SL 3 +#define NPCX_DEVALT2_I2C2_0_SL 4 +#define NPCX_DEVALT2_I2C5_0_SL 5 +#define NPCX_DEVALT2_I2C3_0_SL 6 +#define NPCX_DEVALT6_I2C6_1_SL 5 +#define NPCX_DEVALT6_I2C5_1_SL 6 +#define NPCX_DEVALT6_I2C4_1_SL 7 /* pin-mux for ADC */ -#define NPCX_DEVALTF_ADC5_SL 0 -#define NPCX_DEVALTF_ADC6_SL 1 -#define NPCX_DEVALTF_ADC7_SL 2 -#define NPCX_DEVALTF_ADC8_SL 3 -#define NPCX_DEVALTF_ADC9_SL 4 -#define NPCX_DEVALTF_ADC10_SL 5 -#define NPCX_DEVALTF_ADC11_SL 6 +#define NPCX_DEVALTF_ADC5_SL 0 +#define NPCX_DEVALTF_ADC6_SL 1 +#define NPCX_DEVALTF_ADC7_SL 2 +#define NPCX_DEVALTF_ADC8_SL 3 +#define NPCX_DEVALTF_ADC9_SL 4 +#define NPCX_DEVALTF_ADC10_SL 5 +#define NPCX_DEVALTF_ADC11_SL 6 /* pin-mux for PSL */ -#define NPCX_DEVALTD_PSL_IN1_AHI 0 -#define NPCX_DEVALTD_NPSL_IN1_SL 1 -#define NPCX_DEVALTD_PSL_IN2_AHI 2 -#define NPCX_DEVALTD_NPSL_IN2_SL 3 -#define NPCX_DEVALTD_PSL_IN3_AHI 4 -#define NPCX_DEVALTD_PSL_IN3_SL 5 -#define NPCX_DEVALTD_PSL_IN4_AHI 6 -#define NPCX_DEVALTD_PSL_IN4_SL 7 +#define NPCX_DEVALTD_PSL_IN1_AHI 0 +#define NPCX_DEVALTD_NPSL_IN1_SL 1 +#define NPCX_DEVALTD_PSL_IN2_AHI 2 +#define NPCX_DEVALTD_NPSL_IN2_SL 3 +#define NPCX_DEVALTD_PSL_IN3_AHI 4 +#define NPCX_DEVALTD_PSL_IN3_SL 5 +#define NPCX_DEVALTD_PSL_IN4_AHI 6 +#define NPCX_DEVALTD_PSL_IN4_SL 7 /* pin-mux for Misc. */ /* pin-mux for UART */ -#define NPCX_DEVALTJ_CR_SIN1_SL1 0 -#define NPCX_DEVALTJ_CR_SOUT1_SL1 1 -#define NPCX_DEVALTJ_CR_SIN1_SL2 2 -#define NPCX_DEVALTJ_CR_SOUT1_SL2 3 -#define NPCX_DEVALTJ_CR_SIN2_SL 4 -#define NPCX_DEVALTJ_CR_SOUT2_SL 5 -#define NPCX_DEVALTJ_CR_SIN3_SL 6 -#define NPCX_DEVALTJ_CR_SOUT3_SL 7 -#define NPCX_DEVALTE_CR_SIN4_SL 6 -#define NPCX_DEVALTE_CR_SOUT4_SL 7 +#define NPCX_DEVALTJ_CR_SIN1_SL1 0 +#define NPCX_DEVALTJ_CR_SOUT1_SL1 1 +#define NPCX_DEVALTJ_CR_SIN1_SL2 2 +#define NPCX_DEVALTJ_CR_SOUT1_SL2 3 +#define NPCX_DEVALTJ_CR_SIN2_SL 4 +#define NPCX_DEVALTJ_CR_SOUT2_SL 5 +#define NPCX_DEVALTJ_CR_SIN3_SL 6 +#define NPCX_DEVALTJ_CR_SOUT3_SL 7 +#define NPCX_DEVALTE_CR_SIN4_SL 6 +#define NPCX_DEVALTE_CR_SOUT4_SL 7 /* SHI module version 2 enable bit */ -#define NPCX_DEVALTF_SHI_NEW 7 +#define NPCX_DEVALTF_SHI_NEW 7 /* VCC_RST Pull-Up Disable */ -#define NPCX_DEVALTG_VCC1_RST_PUD 5 -#define NPCX_DEVALTG_PSL_OUT_SL 6 -#define NPCX_DEVALTG_PSL_GPO_SL 7 +#define NPCX_DEVALTG_VCC1_RST_PUD 5 +#define NPCX_DEVALTG_PSL_OUT_SL 6 +#define NPCX_DEVALTG_PSL_GPO_SL 7 /* SMBus register fields */ -#define NPCX_SMBSEL_SMB4SEL 4 -#define NPCX_SMBSEL_SMB5SEL 5 -#define NPCX_SMBSEL_SMB6SEL 6 +#define NPCX_SMBSEL_SMB4SEL 4 +#define NPCX_SMBSEL_SMB5SEL 5 +#define NPCX_SMBSEL_SMB6SEL 6 /* pin-mux for JTAG */ -#define NPCX_JEN_CTL1 REG8(NPCX_SCFG_BASE_ADDR + 0x120) -#define NPCX_JEN_CTL1_JEN_EN_FIELD FIELD(0, 4) -#define NPCX_JEN_CTL1_JEN_EN_DIS 0x06 -#define NPCX_JEN_CTL1_JEN_EN_ENA 0x09 +#define NPCX_JEN_CTL1 REG8(NPCX_SCFG_BASE_ADDR + 0x120) +#define NPCX_JEN_CTL1_JEN_EN_FIELD FIELD(0, 4) +#define NPCX_JEN_CTL1_JEN_EN_DIS 0x06 +#define NPCX_JEN_CTL1_JEN_EN_ENA 0x09 /* SMB enumeration: I2C port definitions. */ enum { - NPCX_I2C_PORT0_0 = 0, /* I2C port 0, bus 0 */ - NPCX_I2C_PORT1_0, /* I2C port 1, bus 0 */ - NPCX_I2C_PORT2_0, /* I2C port 2, bus 0 */ - NPCX_I2C_PORT3_0, /* I2C port 3, bus 0 */ - NPCX_I2C_PORT4_1, /* I2C port 4, bus 1 */ - NPCX_I2C_PORT5_0, /* I2C port 5, bus 0 */ - NPCX_I2C_PORT5_1, /* I2C port 5, bus 1 */ - NPCX_I2C_PORT6_0, /* I2C port 6, bus 0 */ - NPCX_I2C_PORT6_1, /* I2C port 6, bus 1 */ - NPCX_I2C_PORT7_0, /* I2C port 7, bus 0 */ + NPCX_I2C_PORT0_0 = 0, /* I2C port 0, bus 0 */ + NPCX_I2C_PORT1_0, /* I2C port 1, bus 0 */ + NPCX_I2C_PORT2_0, /* I2C port 2, bus 0 */ + NPCX_I2C_PORT3_0, /* I2C port 3, bus 0 */ + NPCX_I2C_PORT4_1, /* I2C port 4, bus 1 */ + NPCX_I2C_PORT5_0, /* I2C port 5, bus 0 */ + NPCX_I2C_PORT5_1, /* I2C port 5, bus 1 */ + NPCX_I2C_PORT6_0, /* I2C port 6, bus 0 */ + NPCX_I2C_PORT6_1, /* I2C port 6, bus 1 */ + NPCX_I2C_PORT7_0, /* I2C port 7, bus 0 */ NPCX_I2C_COUNT, }; /* Power Management Controller (PMC) Registers */ -#define NPCX_FMUL_WIN_DLY REG8(NPCX_PMC_BASE_ADDR + 0x010) -#define NPCX_RAM_PD(offset) REG8(NPCX_PMC_BASE_ADDR + 0x020 + (offset)) +#define NPCX_FMUL_WIN_DLY REG8(NPCX_PMC_BASE_ADDR + 0x010) +#define NPCX_RAM_PD(offset) REG8(NPCX_PMC_BASE_ADDR + 0x020 + (offset)) /* PMC register fields */ -#define NPCX_PWDWN_CTL3_SMB4_PD 4 -#define NPCX_PWDWN_CTL7_SMB5_PD 0 -#define NPCX_PWDWN_CTL7_SMB6_PD 1 -#define NPCX_PWDWN_CTL7_SMB7_PD 2 -#define NPCX_PWDWN_CTL7_ITIM64_PD 5 -#define NPCX_PWDWN_CTL7_UART2_PD 6 +#define NPCX_PWDWN_CTL3_SMB4_PD 4 +#define NPCX_PWDWN_CTL7_SMB5_PD 0 +#define NPCX_PWDWN_CTL7_SMB6_PD 1 +#define NPCX_PWDWN_CTL7_SMB7_PD 2 +#define NPCX_PWDWN_CTL7_ITIM64_PD 5 +#define NPCX_PWDWN_CTL7_UART2_PD 6 /* * PMC enumeration: @@ -331,38 +329,37 @@ enum NPCX_PMC_PWDWN_CTL_T { NPCX_PMC_PWDWN_CNT, }; -#define CGC_I2C_MASK (BIT(NPCX_PWDWN_CTL3_SMB0_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB2_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB3_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB4_PD)) -#define CGC_I2C_MASK2 (BIT(NPCX_PWDWN_CTL7_SMB5_PD) | \ - BIT(NPCX_PWDWN_CTL7_SMB6_PD) | \ - BIT(NPCX_PWDWN_CTL7_SMB7_PD)) -#define CGC_UART2_MASK BIT(NPCX_PWDWN_CTL7_UART2_PD) +#define CGC_I2C_MASK \ + (BIT(NPCX_PWDWN_CTL3_SMB0_PD) | BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \ + BIT(NPCX_PWDWN_CTL3_SMB2_PD) | BIT(NPCX_PWDWN_CTL3_SMB3_PD) | \ + BIT(NPCX_PWDWN_CTL3_SMB4_PD)) +#define CGC_I2C_MASK2 \ + (BIT(NPCX_PWDWN_CTL7_SMB5_PD) | BIT(NPCX_PWDWN_CTL7_SMB6_PD) | \ + BIT(NPCX_PWDWN_CTL7_SMB7_PD)) +#define CGC_UART2_MASK BIT(NPCX_PWDWN_CTL7_UART2_PD) /* BBRAM register fields */ -#define NPCX_BKUP_STS_VSBY_STS 1 -#define NPCX_BKUP_STS_VCC1_STS 0 -#define NPCX_BKUP_STS_ALL_MASK \ +#define NPCX_BKUP_STS_VSBY_STS 1 +#define NPCX_BKUP_STS_VCC1_STS 0 +#define NPCX_BKUP_STS_ALL_MASK \ (BIT(NPCX_BKUP_STS_IBBR) | BIT(NPCX_BKUP_STS_VSBY_STS) | \ - BIT(NPCX_BKUP_STS_VCC1_STS)) -#define NPCX_BBRAM_SIZE 128 /* Size of BBRAM */ + BIT(NPCX_BKUP_STS_VCC1_STS)) +#define NPCX_BBRAM_SIZE 128 /* Size of BBRAM */ /* ITIM registers */ -#define NPCX_ITCNT32(n) REG32(NPCX_ITIM_BASE_ADDR(n) + 0x008) +#define NPCX_ITCNT32(n) REG32(NPCX_ITIM_BASE_ADDR(n) + 0x008) /* Timer counter register used for 1 micro-second system tick */ -#define NPCX_ITCNT_SYSTEM NPCX_ITCNT32(ITIM32_6) +#define NPCX_ITCNT_SYSTEM NPCX_ITCNT32(ITIM32_6) /* Timer counter register used for others */ -#define NPCX_ITCNT NPCX_ITCNT32 +#define NPCX_ITCNT NPCX_ITCNT32 /* ITIM module No. used for event */ -#define ITIM_EVENT_NO ITIM32_1 +#define ITIM_EVENT_NO ITIM32_1 /* ITIM module No. used for watchdog */ -#define ITIM_WDG_NO ITIM32_5 +#define ITIM_WDG_NO ITIM32_5 /* ITIM module No. used for 1 micro-second system tick */ -#define ITIM_SYSTEM_NO ITIM32_6 +#define ITIM_SYSTEM_NO ITIM32_6 /* ITIM enumeration */ enum ITIM_MODULE_T { @@ -376,56 +373,56 @@ enum ITIM_MODULE_T { }; /* Serial Host Interface (SHI) Registers - only available on SHI Version 2 */ -#define NPCX_SHICFG3 REG8(NPCX_SHI_BASE_ADDR + 0x00C) -#define NPCX_SHICFG4 REG8(NPCX_SHI_BASE_ADDR + 0x00D) -#define NPCX_SHICFG5 REG8(NPCX_SHI_BASE_ADDR + 0x00E) -#define NPCX_EVSTAT2 REG8(NPCX_SHI_BASE_ADDR + 0x00F) -#define NPCX_EVENABLE2 REG8(NPCX_SHI_BASE_ADDR + 0x010) -#define NPCX_OBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n)) -#define NPCX_IBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x0A0 + (n)) +#define NPCX_SHICFG3 REG8(NPCX_SHI_BASE_ADDR + 0x00C) +#define NPCX_SHICFG4 REG8(NPCX_SHI_BASE_ADDR + 0x00D) +#define NPCX_SHICFG5 REG8(NPCX_SHI_BASE_ADDR + 0x00E) +#define NPCX_EVSTAT2 REG8(NPCX_SHI_BASE_ADDR + 0x00F) +#define NPCX_EVENABLE2 REG8(NPCX_SHI_BASE_ADDR + 0x010) +#define NPCX_OBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n)) +#define NPCX_IBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x0A0 + (n)) /* SHI register fields */ -#define NPCX_SHICFG3_OBUFLVLDIS 7 -#define NPCX_SHICFG4_IBUFLVLDIS 7 -#define NPCX_SHICFG5_IBUFLVL2 FIELD(0, 6) -#define NPCX_SHICFG5_IBUFLVL2DIS 7 -#define NPCX_EVSTAT2_IBHF2 0 -#define NPCX_EVSTAT2_CSNRE 1 -#define NPCX_EVSTAT2_CSNFE 2 -#define NPCX_EVENABLE2_IBHF2EN 0 -#define NPCX_EVENABLE2_CSNREEN 1 -#define NPCX_EVENABLE2_CSNFEEN 2 +#define NPCX_SHICFG3_OBUFLVLDIS 7 +#define NPCX_SHICFG4_IBUFLVLDIS 7 +#define NPCX_SHICFG5_IBUFLVL2 FIELD(0, 6) +#define NPCX_SHICFG5_IBUFLVL2DIS 7 +#define NPCX_EVSTAT2_IBHF2 0 +#define NPCX_EVSTAT2_CSNRE 1 +#define NPCX_EVSTAT2_CSNFE 2 +#define NPCX_EVENABLE2_IBHF2EN 0 +#define NPCX_EVENABLE2_CSNREEN 1 +#define NPCX_EVENABLE2_CSNFEEN 2 /* eSPI register fields */ -#define NPCX_ESPIIE_BMTXDONEIE 19 -#define NPCX_ESPIIE_PBMRXIE 20 -#define NPCX_ESPIIE_PMSGRXIE 21 -#define NPCX_ESPIIE_BMBURSTERRIE 22 -#define NPCX_ESPIIE_BMBURSTDONEIE 23 - -#define NPCX_ESPIWE_PBMRXWE 20 -#define NPCX_ESPIWE_PMSGRXWE 21 - -#define NPCX_ESPISTS_VWUPDW 17 -#define NPCX_ESPISTS_BMTXDONE 19 -#define NPCX_ESPISTS_PBMRX 20 -#define NPCX_ESPISTS_PMSGRX 21 -#define NPCX_ESPISTS_BMBURSTERR 22 -#define NPCX_ESPISTS_BMBURSTDONE 23 -#define NPCX_ESPISTS_ESPIRST_LVL 24 - -#define ESPIIE_BMTXDONE BIT(NPCX_ESPIIE_BMTXDONEIE) -#define ESPIIE_PBMRX BIT(NPCX_ESPIIE_PBMRXIE) -#define ESPIIE_PMSGRX BIT(NPCX_ESPIIE_PMSGRXIE) -#define ESPIIE_BMBURSTERR BIT(NPCX_ESPIIE_BMBURSTERRIE) -#define ESPIIE_BMBURSTDONE BIT(NPCX_ESPIIE_BMBURSTDONEIE) - -#define ESPIWE_PBMRX BIT(NPCX_ESPIWE_PBMRXWE) -#define ESPIWE_PMSGRX BIT(NPCX_ESPIWE_PMSGRXWE) +#define NPCX_ESPIIE_BMTXDONEIE 19 +#define NPCX_ESPIIE_PBMRXIE 20 +#define NPCX_ESPIIE_PMSGRXIE 21 +#define NPCX_ESPIIE_BMBURSTERRIE 22 +#define NPCX_ESPIIE_BMBURSTDONEIE 23 + +#define NPCX_ESPIWE_PBMRXWE 20 +#define NPCX_ESPIWE_PMSGRXWE 21 + +#define NPCX_ESPISTS_VWUPDW 17 +#define NPCX_ESPISTS_BMTXDONE 19 +#define NPCX_ESPISTS_PBMRX 20 +#define NPCX_ESPISTS_PMSGRX 21 +#define NPCX_ESPISTS_BMBURSTERR 22 +#define NPCX_ESPISTS_BMBURSTDONE 23 +#define NPCX_ESPISTS_ESPIRST_LVL 24 + +#define ESPIIE_BMTXDONE BIT(NPCX_ESPIIE_BMTXDONEIE) +#define ESPIIE_PBMRX BIT(NPCX_ESPIIE_PBMRXIE) +#define ESPIIE_PMSGRX BIT(NPCX_ESPIIE_PMSGRXIE) +#define ESPIIE_BMBURSTERR BIT(NPCX_ESPIIE_BMBURSTERRIE) +#define ESPIIE_BMBURSTDONE BIT(NPCX_ESPIIE_BMBURSTDONEIE) + +#define ESPIWE_PBMRX BIT(NPCX_ESPIWE_PBMRXWE) +#define ESPIWE_PMSGRX BIT(NPCX_ESPIWE_PMSGRXWE) /* Bit field manipulation for VWEVMS Value */ -#define VWEVMS_WK_EN(e) (((e)<<20) & 0x00100000) -#define VWEVMS_INTWK_EN(e) (VWEVMS_INT_EN(e) | VWEVMS_WK_EN(e)) +#define VWEVMS_WK_EN(e) (((e) << 20) & 0x00100000) +#define VWEVMS_INTWK_EN(e) (VWEVMS_INT_EN(e) | VWEVMS_WK_EN(e)) /* eSPI max supported frequency */ enum { @@ -449,61 +446,55 @@ enum { /* eSPI max frequency support per FMCLK */ #if (FMCLK <= 33000000) -#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_33 +#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_33 #else -#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_50 +#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_50 #endif /* UART registers */ -#define NPCX_UART_WK_GROUP MIWU_GROUP_8 -#define NPCX_UART_WK_BIT 7 -#define NPCX_UART2_WK_GROUP MIWU_GROUP_1 -#define NPCX_UART2_WK_BIT 6 +#define NPCX_UART_WK_GROUP MIWU_GROUP_8 +#define NPCX_UART_WK_BIT 7 +#define NPCX_UART2_WK_GROUP MIWU_GROUP_1 +#define NPCX_UART2_WK_BIT 6 /* MIWU registers */ -#define NPCX_WKEDG_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x00 + \ - ((n) * 0x10)) -#define NPCX_WKAEDG_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x01 + \ - ((n) * 0x10)) -#define NPCX_WKMOD_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x02 + \ - ((n) * 0x10)) -#define NPCX_WKPND_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x03 + \ - ((n) * 0x10)) -#define NPCX_WKPCL_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x04 + \ - ((n) * 0x10)) -#define NPCX_WKEN_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x05 + \ - ((n) * 0x10)) -#define NPCX_WKST_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x06 + \ - ((n) * 0x10)) -#define NPCX_WKINEN_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x07 + \ - ((n) * 0x10)) - -#define NPCX_WKEDG(port, n) REG8(NPCX_WKEDG_ADDR(port, n)) -#define NPCX_WKAEDG(port, n) REG8(NPCX_WKAEDG_ADDR(port, n)) -#define NPCX_WKPND(port, n) REG8(NPCX_WKPND_ADDR(port, n)) -#define NPCX_WKPCL(port, n) REG8(NPCX_WKPCL_ADDR(port, n)) -#define NPCX_WKEN(port, n) REG8(NPCX_WKEN_ADDR(port, n)) -#define NPCX_WKST(port, n) REG8(NPCX_WKST_ADDR(port, n)) -#define NPCX_WKINEN(port, n) REG8(NPCX_WKINEN_ADDR(port, n)) -#define NPCX_WKMOD(port, n) REG8(NPCX_WKMOD_ADDR(port, n)) +#define NPCX_WKEDG_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x00 + ((n)*0x10)) +#define NPCX_WKAEDG_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x01 + ((n)*0x10)) +#define NPCX_WKMOD_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x02 + ((n)*0x10)) +#define NPCX_WKPND_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x03 + ((n)*0x10)) +#define NPCX_WKPCL_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x04 + ((n)*0x10)) +#define NPCX_WKEN_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x05 + ((n)*0x10)) +#define NPCX_WKST_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x06 + ((n)*0x10)) +#define NPCX_WKINEN_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x07 + ((n)*0x10)) + +#define NPCX_WKEDG(port, n) REG8(NPCX_WKEDG_ADDR(port, n)) +#define NPCX_WKAEDG(port, n) REG8(NPCX_WKAEDG_ADDR(port, n)) +#define NPCX_WKPND(port, n) REG8(NPCX_WKPND_ADDR(port, n)) +#define NPCX_WKPCL(port, n) REG8(NPCX_WKPCL_ADDR(port, n)) +#define NPCX_WKEN(port, n) REG8(NPCX_WKEN_ADDR(port, n)) +#define NPCX_WKST(port, n) REG8(NPCX_WKST_ADDR(port, n)) +#define NPCX_WKINEN(port, n) REG8(NPCX_WKINEN_ADDR(port, n)) +#define NPCX_WKMOD(port, n) REG8(NPCX_WKMOD_ADDR(port, n)) /* LCT register */ -#define NPCX_LCTCONT REG8(NPCX_LCT_BASE_ADDR + 0x002) -#define NPCX_LCTSTAT REG8(NPCX_LCT_BASE_ADDR + 0x004) -#define NPCX_LCTSECOND REG8(NPCX_LCT_BASE_ADDR + 0x005) -#define NPCX_LCTMINUTE REG8(NPCX_LCT_BASE_ADDR + 0x006) -#define NPCX_LCTHOUR REG8(NPCX_LCT_BASE_ADDR + 0x008) -#define NPCX_LCTDAY REG8(NPCX_LCT_BASE_ADDR + 0x00A) -#define NPCX_LCTWEEK REG8(NPCX_LCT_BASE_ADDR + 0x00C) +#define NPCX_LCTCONT REG8(NPCX_LCT_BASE_ADDR + 0x002) +#define NPCX_LCTSTAT REG8(NPCX_LCT_BASE_ADDR + 0x004) +#define NPCX_LCTSECOND REG8(NPCX_LCT_BASE_ADDR + 0x005) +#define NPCX_LCTMINUTE REG8(NPCX_LCT_BASE_ADDR + 0x006) +#define NPCX_LCTHOUR REG8(NPCX_LCT_BASE_ADDR + 0x008) +#define NPCX_LCTDAY REG8(NPCX_LCT_BASE_ADDR + 0x00A) +#define NPCX_LCTWEEK REG8(NPCX_LCT_BASE_ADDR + 0x00C) /* LCTCONT fields */ -#define NPCX_LCTCONT_EN 0 -#define NPCX_LCTCONT_EN_FIELD FIELD(0, 1) -#define NPCX_LCTCONT_EVEN 1 -#define NPCX_LCTCONT_PSL_EN 2 -#define NPCX_LCTCONT_CLK_EN 6 -#define NPCX_LCTCONT_VSBY_PWR 7 +#define NPCX_LCTCONT_EN 0 +#define NPCX_LCTCONT_EN_FIELD FIELD(0, 1) +#define NPCX_LCTCONT_EVEN 1 +#define NPCX_LCTCONT_PSL_EN 2 +#define NPCX_LCTCONT_CLK_EN 6 +#define NPCX_LCTCONT_VSBY_PWR 7 /* LCTSTAT fields */ -#define NPCX_LCTSTAT_EVST 0 +#define NPCX_LCTSTAT_EVST 0 /* UART registers and functions */ #if NPCX_UART_MODULE2 @@ -512,73 +503,73 @@ enum { * always 1 == MIWU_TABLE_1. */ #define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTG_1 -#define NPCX_UART_DEVALT NPCX_DEVALT(ALT_GROUP_J) -#define NPCX_UART_DEVALT_SIN_SL NPCX_DEVALTJ_CR_SIN1_SL2 -#define NPCX_UART_DEVALT_SOUT_SL NPCX_DEVALTJ_CR_SOUT1_SL2 -#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(ALT_GROUP_J) -#define NPCX_UART_ALT_DEVALT_SIN_SL NPCX_DEVALTJ_CR_SIN1_SL1 -#define NPCX_UART_ALT_DEVALT_SOUT_SL NPCX_DEVALTJ_CR_SOUT1_SL1 +#define NPCX_UART_DEVALT NPCX_DEVALT(ALT_GROUP_J) +#define NPCX_UART_DEVALT_SIN_SL NPCX_DEVALTJ_CR_SIN1_SL2 +#define NPCX_UART_DEVALT_SOUT_SL NPCX_DEVALTJ_CR_SOUT1_SL2 +#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(ALT_GROUP_J) +#define NPCX_UART_ALT_DEVALT_SIN_SL NPCX_DEVALTJ_CR_SIN1_SL1 +#define NPCX_UART_ALT_DEVALT_SOUT_SL NPCX_DEVALTJ_CR_SOUT1_SL1 #else /* !NPCX_UART_MODULE2 */ -#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTB_1 -#define NPCX_UART_DEVALT NPCX_DEVALT(ALT_GROUP_J) -#define NPCX_UART_DEVALT_SIN_SL NPCX_DEVALTJ_CR_SIN1_SL1 -#define NPCX_UART_DEVALT_SOUT_SL NPCX_DEVALTJ_CR_SOUT1_SL1 -#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(ALT_GROUP_J) -#define NPCX_UART_ALT_DEVALT_SIN_SL NPCX_DEVALTJ_CR_SIN1_SL2 -#define NPCX_UART_ALT_DEVALT_SOUT_SL NPCX_DEVALTJ_CR_SOUT1_SL2 +#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTB_1 +#define NPCX_UART_DEVALT NPCX_DEVALT(ALT_GROUP_J) +#define NPCX_UART_DEVALT_SIN_SL NPCX_DEVALTJ_CR_SIN1_SL1 +#define NPCX_UART_DEVALT_SOUT_SL NPCX_DEVALTJ_CR_SOUT1_SL1 +#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(ALT_GROUP_J) +#define NPCX_UART_ALT_DEVALT_SIN_SL NPCX_DEVALTJ_CR_SIN1_SL2 +#define NPCX_UART_ALT_DEVALT_SOUT_SL NPCX_DEVALTJ_CR_SOUT1_SL2 #endif /* NPCX_UART_MODULE2 */ /* ADC register */ -#define NPCX_ADCSTS REG16(NPCX_ADC_BASE_ADDR + 0x000) -#define NPCX_ADCCNF REG16(NPCX_ADC_BASE_ADDR + 0x002) -#define NPCX_ATCTL REG16(NPCX_ADC_BASE_ADDR + 0x004) -#define NPCX_ASCADD REG16(NPCX_ADC_BASE_ADDR + 0x006) -#define NPCX_ADCCS REG16(NPCX_ADC_BASE_ADDR + 0x008) -#define NPCX_THRCTS REG16(NPCX_ADC_BASE_ADDR + 0x01A) -#define NPCX_ADCCNF2 REG16(NPCX_ADC_BASE_ADDR + 0x020) -#define NPCX_GENDLY REG16(NPCX_ADC_BASE_ADDR + 0x022) -#define NPCX_MEAST REG16(NPCX_ADC_BASE_ADDR + 0x026) +#define NPCX_ADCSTS REG16(NPCX_ADC_BASE_ADDR + 0x000) +#define NPCX_ADCCNF REG16(NPCX_ADC_BASE_ADDR + 0x002) +#define NPCX_ATCTL REG16(NPCX_ADC_BASE_ADDR + 0x004) +#define NPCX_ASCADD REG16(NPCX_ADC_BASE_ADDR + 0x006) +#define NPCX_ADCCS REG16(NPCX_ADC_BASE_ADDR + 0x008) +#define NPCX_THRCTS REG16(NPCX_ADC_BASE_ADDR + 0x01A) +#define NPCX_ADCCNF2 REG16(NPCX_ADC_BASE_ADDR + 0x020) +#define NPCX_GENDLY REG16(NPCX_ADC_BASE_ADDR + 0x022) +#define NPCX_MEAST REG16(NPCX_ADC_BASE_ADDR + 0x026) /* NOTE: This is 0-based for the ADC channels. */ -#define NPCX_CHNDAT(n) REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L*(n))) +#define NPCX_CHNDAT(n) REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L * (n))) /* NOTE: These are 1-based for the threshold detectors. */ -#define NPCX_THRCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x05E + (2L*(n))) +#define NPCX_THRCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x05E + (2L * (n))) /* ADC register fields */ -#define NPCX_ADCSTS_EOCEV 0 -#define NPCX_ADCCNF_ADCMD_FIELD FIELD(1, 2) -#define NPCX_ADCCNF_ADCRPTC 3 -#define NPCX_ADCCNF_INTECEN 6 -#define NPCX_ADCCNF_START 4 -#define NPCX_ADCCNF_ADCEN 0 -#define NPCX_ADCCNF_STOP 11 -#define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6) -#define NPCX_ATCTL_DLY_FIELD FIELD(8, 3) -#define NPCX_ASCADD_SADDR_FIELD FIELD(0, 5) -#define NPCX_THRCTS_ADC_WKEN 15 -#define NPCX_THRCTS_THR6_IEN 13 -#define NPCX_THRCTS_THR5_IEN 12 -#define NPCX_THRCTS_THR4_IEN 11 -#define NPCX_THRCTS_THR3_IEN 10 -#define NPCX_THRCTS_THR2_IEN 9 -#define NPCX_THRCTS_THR1_IEN 8 -#define NPCX_THRCTS_ADC_EVENT 7 -#define NPCX_THRCTS_THR6_STS 5 -#define NPCX_THRCTS_THR5_STS 4 -#define NPCX_THRCTS_THR4_STS 3 -#define NPCX_THRCTS_THR3_STS 2 -#define NPCX_THRCTS_THR2_STS 1 -#define NPCX_THRCTS_THR1_STS 0 -#define NPCX_CHNDAT_CHDAT_FIELD FIELD(0, 10) -#define NPCX_CHNDAT_NEW 15 -#define NPCX_THRCTL_THEN 15 -#define NPCX_THRCTL_L_H 14 -#define NPCX_THRCTL_CHNSEL FIELD(10, 4) -#define NPCX_THRCTL_THRVAL FIELD(0, 10) - -#define NPCX_ADC_THRESH1 1 -#define NPCX_ADC_THRESH2 2 -#define NPCX_ADC_THRESH3 3 -#define NPCX_ADC_THRESH4 4 -#define NPCX_ADC_THRESH5 5 -#define NPCX_ADC_THRESH6 6 -#define NPCX_ADC_THRESH_CNT 6 +#define NPCX_ADCSTS_EOCEV 0 +#define NPCX_ADCCNF_ADCMD_FIELD FIELD(1, 2) +#define NPCX_ADCCNF_ADCRPTC 3 +#define NPCX_ADCCNF_INTECEN 6 +#define NPCX_ADCCNF_START 4 +#define NPCX_ADCCNF_ADCEN 0 +#define NPCX_ADCCNF_STOP 11 +#define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6) +#define NPCX_ATCTL_DLY_FIELD FIELD(8, 3) +#define NPCX_ASCADD_SADDR_FIELD FIELD(0, 5) +#define NPCX_THRCTS_ADC_WKEN 15 +#define NPCX_THRCTS_THR6_IEN 13 +#define NPCX_THRCTS_THR5_IEN 12 +#define NPCX_THRCTS_THR4_IEN 11 +#define NPCX_THRCTS_THR3_IEN 10 +#define NPCX_THRCTS_THR2_IEN 9 +#define NPCX_THRCTS_THR1_IEN 8 +#define NPCX_THRCTS_ADC_EVENT 7 +#define NPCX_THRCTS_THR6_STS 5 +#define NPCX_THRCTS_THR5_STS 4 +#define NPCX_THRCTS_THR4_STS 3 +#define NPCX_THRCTS_THR3_STS 2 +#define NPCX_THRCTS_THR2_STS 1 +#define NPCX_THRCTS_THR1_STS 0 +#define NPCX_CHNDAT_CHDAT_FIELD FIELD(0, 10) +#define NPCX_CHNDAT_NEW 15 +#define NPCX_THRCTL_THEN 15 +#define NPCX_THRCTL_L_H 14 +#define NPCX_THRCTL_CHNSEL FIELD(10, 4) +#define NPCX_THRCTL_THRVAL FIELD(0, 10) + +#define NPCX_ADC_THRESH1 1 +#define NPCX_ADC_THRESH2 2 +#define NPCX_ADC_THRESH3 3 +#define NPCX_ADC_THRESH4 4 +#define NPCX_ADC_THRESH5 5 +#define NPCX_ADC_THRESH6 6 +#define NPCX_ADC_THRESH_CNT 6 diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index 8f0c7431a6..922d787323 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -17,28 +17,32 @@ * Macro Functions */ /* Bit functions */ -#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit))) -#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit)))) -#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1)) -#define UPDATE_BIT(reg, bit, cond) { if (cond) \ - SET_BIT(reg, bit); \ - else \ - CLEAR_BIT(reg, bit); } +#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit))) +#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit)))) +#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1)) +#define UPDATE_BIT(reg, bit, cond) \ + { \ + if (cond) \ + SET_BIT(reg, bit); \ + else \ + CLEAR_BIT(reg, bit); \ + } /* Field functions */ -#define GET_POS_FIELD(pos, size) pos -#define GET_SIZE_FIELD(pos, size) size -#define FIELD_POS(field) GET_POS_##field -#define FIELD_SIZE(field) GET_SIZE_##field +#define GET_POS_FIELD(pos, size) pos +#define GET_SIZE_FIELD(pos, size) size +#define FIELD_POS(field) GET_POS_##field +#define FIELD_SIZE(field) GET_SIZE_##field /* Read field functions */ #define GET_FIELD(reg, field) \ _GET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field)) -#define _GET_FIELD_(reg, f_pos, f_size) (((reg)>>(f_pos)) & ((1<<(f_size))-1)) +#define _GET_FIELD_(reg, f_pos, f_size) \ + (((reg) >> (f_pos)) & ((1 << (f_size)) - 1)) /* Write field functions */ #define SET_FIELD(reg, field, value) \ _SET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field), value) -#define _SET_FIELD_(reg, f_pos, f_size, value) \ - ((reg) = ((reg) & (~(((1 << (f_size))-1) << (f_pos)))) \ - | ((value) << (f_pos))) +#define _SET_FIELD_(reg, f_pos, f_size, value) \ + ((reg) = ((reg) & (~(((1 << (f_size)) - 1) << (f_pos)))) | \ + ((value) << (f_pos))) /******************************************************************************/ /* @@ -46,216 +50,212 @@ */ /* Global Definition */ -#define I2C_7BITS_ADDR 0 +#define I2C_7BITS_ADDR 0 /* Switcher of features */ -#define SUPPORT_LCT 1 -#define SUPPORT_WDG 1 -#define SUPPORT_P80_SEG 0 /* Note: it uses KSO10 & KSO11 */ +#define SUPPORT_LCT 1 +#define SUPPORT_WDG 1 +#define SUPPORT_P80_SEG 0 /* Note: it uses KSO10 & KSO11 */ /* Switcher of debugging */ -#define DEBUG_GPIO 0 -#define DEBUG_I2C 0 -#define DEBUG_TMR 0 -#define DEBUG_WDG 0 -#define DEBUG_FAN 0 -#define DEBUG_PWM 0 -#define DEBUG_SPI 0 -#define DEBUG_FLH 0 -#define DEBUG_PECI 0 -#define DEBUG_SHI 0 -#define DEBUG_CLK 0 -#define DEBUG_LPC 0 -#define DEBUG_ESPI 0 -#define DEBUG_CEC 0 -#define DEBUG_SIB 0 -#define DEBUG_PS2 0 +#define DEBUG_GPIO 0 +#define DEBUG_I2C 0 +#define DEBUG_TMR 0 +#define DEBUG_WDG 0 +#define DEBUG_FAN 0 +#define DEBUG_PWM 0 +#define DEBUG_SPI 0 +#define DEBUG_FLH 0 +#define DEBUG_PECI 0 +#define DEBUG_SHI 0 +#define DEBUG_CLK 0 +#define DEBUG_LPC 0 +#define DEBUG_ESPI 0 +#define DEBUG_CEC 0 +#define DEBUG_SIB 0 +#define DEBUG_PS2 0 /* Modules Map */ -#define NPCX_ESPI_BASE_ADDR 0x4000A000 -#define NPCX_MDC_BASE_ADDR 0x4000C000 -#define NPCX_PMC_BASE_ADDR 0x4000D000 -#define NPCX_SIB_BASE_ADDR 0x4000E000 -#define NPCX_SHI_BASE_ADDR 0x4000F000 -#define NPCX_SHM_BASE_ADDR 0x40010000 -#define NPCX_GDMA_BASE_ADDR 0x40011000 -#define NPCX_FIU_BASE_ADDR 0x40020000 -#define NPCX_KBSCAN_REGS_BASE 0x400A3000 -#define NPCX_WOV_BASE_ADDR 0x400A4000 -#define NPCX_APM_BASE_ADDR 0x400A4800 -#define NPCX_GLUE_REGS_BASE 0x400A5000 -#define NPCX_BBRAM_BASE_ADDR 0x400AF000 -#define NPCX_PS2_BASE_ADDR 0x400B1000 -#define NPCX_HFCG_BASE_ADDR 0x400B5000 -#define NPCX_LFCG_BASE_ADDR 0x400B5100 -#define NPCX_FMUL2_BASE_ADDR 0x400B5200 -#define NPCX_MTC_BASE_ADDR 0x400B7000 -#define NPCX_MSWC_BASE_ADDR 0x400C1000 -#define NPCX_SCFG_BASE_ADDR 0x400C3000 -#define NPCX_KBC_BASE_ADDR 0x400C7000 -#define NPCX_ADC_BASE_ADDR 0x400D1000 -#define NPCX_SPI_BASE_ADDR 0x400D2000 -#define NPCX_PECI_BASE_ADDR 0x400D4000 -#define NPCX_TWD_BASE_ADDR 0x400D8000 +#define NPCX_ESPI_BASE_ADDR 0x4000A000 +#define NPCX_MDC_BASE_ADDR 0x4000C000 +#define NPCX_PMC_BASE_ADDR 0x4000D000 +#define NPCX_SIB_BASE_ADDR 0x4000E000 +#define NPCX_SHI_BASE_ADDR 0x4000F000 +#define NPCX_SHM_BASE_ADDR 0x40010000 +#define NPCX_GDMA_BASE_ADDR 0x40011000 +#define NPCX_FIU_BASE_ADDR 0x40020000 +#define NPCX_KBSCAN_REGS_BASE 0x400A3000 +#define NPCX_WOV_BASE_ADDR 0x400A4000 +#define NPCX_APM_BASE_ADDR 0x400A4800 +#define NPCX_GLUE_REGS_BASE 0x400A5000 +#define NPCX_BBRAM_BASE_ADDR 0x400AF000 +#define NPCX_PS2_BASE_ADDR 0x400B1000 +#define NPCX_HFCG_BASE_ADDR 0x400B5000 +#define NPCX_LFCG_BASE_ADDR 0x400B5100 +#define NPCX_FMUL2_BASE_ADDR 0x400B5200 +#define NPCX_MTC_BASE_ADDR 0x400B7000 +#define NPCX_MSWC_BASE_ADDR 0x400C1000 +#define NPCX_SCFG_BASE_ADDR 0x400C3000 +#define NPCX_KBC_BASE_ADDR 0x400C7000 +#define NPCX_ADC_BASE_ADDR 0x400D1000 +#define NPCX_SPI_BASE_ADDR 0x400D2000 +#define NPCX_PECI_BASE_ADDR 0x400D4000 +#define NPCX_TWD_BASE_ADDR 0x400D8000 /* Multi-Modules Map */ -#define NPCX_PWM_BASE_ADDR(mdl) (0x40080000 + ((mdl) * 0x2000L)) -#define NPCX_GPIO_BASE_ADDR(mdl) (0x40081000 + ((mdl) * 0x2000L)) -#define NPCX_ITIM_BASE_ADDR(mdl) (0x400B0000 + ((mdl) * 0x2000L)) -#define NPCX_MIWU_BASE_ADDR(mdl) (0x400BB000 + ((mdl) * 0x2000L)) -#define NPCX_MFT_BASE_ADDR(mdl) (0x400E1000 + ((mdl) * 0x2000L)) -#define NPCX_PM_CH_BASE_ADDR(mdl) (0x400C9000 + ((mdl) * 0x2000L)) +#define NPCX_PWM_BASE_ADDR(mdl) (0x40080000 + ((mdl)*0x2000L)) +#define NPCX_GPIO_BASE_ADDR(mdl) (0x40081000 + ((mdl)*0x2000L)) +#define NPCX_ITIM_BASE_ADDR(mdl) (0x400B0000 + ((mdl)*0x2000L)) +#define NPCX_MIWU_BASE_ADDR(mdl) (0x400BB000 + ((mdl)*0x2000L)) +#define NPCX_MFT_BASE_ADDR(mdl) (0x400E1000 + ((mdl)*0x2000L)) +#define NPCX_PM_CH_BASE_ADDR(mdl) (0x400C9000 + ((mdl)*0x2000L)) /* * NPCX-IRQ numbers */ -#define NPCX_IRQ_0 0 -#define NPCX_IRQ_1 1 -#define NPCX_IRQ_2 2 -#define NPCX_IRQ_3 3 -#define NPCX_IRQ_4 4 -#define NPCX_IRQ_5 5 -#define NPCX_IRQ_6 6 -#define NPCX_IRQ_7 7 -#define NPCX_IRQ_8 8 -#define NPCX_IRQ_9 9 -#define NPCX_IRQ_10 10 -#define NPCX_IRQ_11 11 -#define NPCX_IRQ_12 12 -#define NPCX_IRQ_13 13 -#define NPCX_IRQ_14 14 -#define NPCX_IRQ_15 15 -#define NPCX_IRQ_16 16 -#define NPCX_IRQ_17 17 -#define NPCX_IRQ_18 18 -#define NPCX_IRQ_19 19 -#define NPCX_IRQ_20 20 -#define NPCX_IRQ_21 21 -#define NPCX_IRQ_22 22 -#define NPCX_IRQ_23 23 -#define NPCX_IRQ_24 24 -#define NPCX_IRQ_25 25 -#define NPCX_IRQ_26 26 -#define NPCX_IRQ_27 27 -#define NPCX_IRQ_28 28 -#define NPCX_IRQ_29 29 -#define NPCX_IRQ_30 30 -#define NPCX_IRQ_31 31 -#define NPCX_IRQ_32 32 -#define NPCX_IRQ_33 33 -#define NPCX_IRQ_34 34 -#define NPCX_IRQ_35 35 -#define NPCX_IRQ_36 36 -#define NPCX_IRQ_37 37 -#define NPCX_IRQ_38 38 -#define NPCX_IRQ_39 39 -#define NPCX_IRQ_40 40 -#define NPCX_IRQ_41 41 -#define NPCX_IRQ_42 42 -#define NPCX_IRQ_43 43 -#define NPCX_IRQ_44 44 -#define NPCX_IRQ_45 45 -#define NPCX_IRQ_46 46 -#define NPCX_IRQ_47 47 -#define NPCX_IRQ_48 48 -#define NPCX_IRQ_49 49 -#define NPCX_IRQ_50 50 -#define NPCX_IRQ_51 51 -#define NPCX_IRQ_52 52 -#define NPCX_IRQ_53 53 -#define NPCX_IRQ_54 54 -#define NPCX_IRQ_55 55 -#define NPCX_IRQ_56 56 -#define NPCX_IRQ_57 57 -#define NPCX_IRQ_58 58 -#define NPCX_IRQ_59 59 -#define NPCX_IRQ_60 60 -#define NPCX_IRQ_61 61 -#define NPCX_IRQ_62 62 -#define NPCX_IRQ_63 63 - -#define NPCX_IRQ_COUNT 64 +#define NPCX_IRQ_0 0 +#define NPCX_IRQ_1 1 +#define NPCX_IRQ_2 2 +#define NPCX_IRQ_3 3 +#define NPCX_IRQ_4 4 +#define NPCX_IRQ_5 5 +#define NPCX_IRQ_6 6 +#define NPCX_IRQ_7 7 +#define NPCX_IRQ_8 8 +#define NPCX_IRQ_9 9 +#define NPCX_IRQ_10 10 +#define NPCX_IRQ_11 11 +#define NPCX_IRQ_12 12 +#define NPCX_IRQ_13 13 +#define NPCX_IRQ_14 14 +#define NPCX_IRQ_15 15 +#define NPCX_IRQ_16 16 +#define NPCX_IRQ_17 17 +#define NPCX_IRQ_18 18 +#define NPCX_IRQ_19 19 +#define NPCX_IRQ_20 20 +#define NPCX_IRQ_21 21 +#define NPCX_IRQ_22 22 +#define NPCX_IRQ_23 23 +#define NPCX_IRQ_24 24 +#define NPCX_IRQ_25 25 +#define NPCX_IRQ_26 26 +#define NPCX_IRQ_27 27 +#define NPCX_IRQ_28 28 +#define NPCX_IRQ_29 29 +#define NPCX_IRQ_30 30 +#define NPCX_IRQ_31 31 +#define NPCX_IRQ_32 32 +#define NPCX_IRQ_33 33 +#define NPCX_IRQ_34 34 +#define NPCX_IRQ_35 35 +#define NPCX_IRQ_36 36 +#define NPCX_IRQ_37 37 +#define NPCX_IRQ_38 38 +#define NPCX_IRQ_39 39 +#define NPCX_IRQ_40 40 +#define NPCX_IRQ_41 41 +#define NPCX_IRQ_42 42 +#define NPCX_IRQ_43 43 +#define NPCX_IRQ_44 44 +#define NPCX_IRQ_45 45 +#define NPCX_IRQ_46 46 +#define NPCX_IRQ_47 47 +#define NPCX_IRQ_48 48 +#define NPCX_IRQ_49 49 +#define NPCX_IRQ_50 50 +#define NPCX_IRQ_51 51 +#define NPCX_IRQ_52 52 +#define NPCX_IRQ_53 53 +#define NPCX_IRQ_54 54 +#define NPCX_IRQ_55 55 +#define NPCX_IRQ_56 56 +#define NPCX_IRQ_57 57 +#define NPCX_IRQ_58 58 +#define NPCX_IRQ_59 59 +#define NPCX_IRQ_60 60 +#define NPCX_IRQ_61 61 +#define NPCX_IRQ_62 62 +#define NPCX_IRQ_63 63 + +#define NPCX_IRQ_COUNT 64 /******************************************************************************/ /* High Frequency Clock Generator (HFCG) registers */ -#define NPCX_HFCGCTRL REG8(NPCX_HFCG_BASE_ADDR + 0x000) -#define NPCX_HFCGML REG8(NPCX_HFCG_BASE_ADDR + 0x002) -#define NPCX_HFCGMH REG8(NPCX_HFCG_BASE_ADDR + 0x004) -#define NPCX_HFCGN REG8(NPCX_HFCG_BASE_ADDR + 0x006) -#define NPCX_HFCGP REG8(NPCX_HFCG_BASE_ADDR + 0x008) -#define NPCX_HFCBCD REG8(NPCX_HFCG_BASE_ADDR + 0x010) +#define NPCX_HFCGCTRL REG8(NPCX_HFCG_BASE_ADDR + 0x000) +#define NPCX_HFCGML REG8(NPCX_HFCG_BASE_ADDR + 0x002) +#define NPCX_HFCGMH REG8(NPCX_HFCG_BASE_ADDR + 0x004) +#define NPCX_HFCGN REG8(NPCX_HFCG_BASE_ADDR + 0x006) +#define NPCX_HFCGP REG8(NPCX_HFCG_BASE_ADDR + 0x008) +#define NPCX_HFCBCD REG8(NPCX_HFCG_BASE_ADDR + 0x010) /* HFCG register fields */ -#define NPCX_HFCGCTRL_LOAD 0 -#define NPCX_HFCGCTRL_LOCK 2 -#define NPCX_HFCGCTRL_CLK_CHNG 7 +#define NPCX_HFCGCTRL_LOAD 0 +#define NPCX_HFCGCTRL_LOCK 2 +#define NPCX_HFCGCTRL_CLK_CHNG 7 /******************************************************************************/ /* Low Frequency Clock Generator (LFCG) registers */ -#define NPCX_LFCGCTL REG8(NPCX_LFCG_BASE_ADDR + 0x000) -#define NPCX_HFRDI REG16(NPCX_LFCG_BASE_ADDR + 0x002) -#define NPCX_HFRDF REG16(NPCX_LFCG_BASE_ADDR + 0x004) -#define NPCX_FRCDIV REG16(NPCX_LFCG_BASE_ADDR + 0x006) -#define NPCX_DIVCOR1 REG16(NPCX_LFCG_BASE_ADDR + 0x008) -#define NPCX_DIVCOR2 REG16(NPCX_LFCG_BASE_ADDR + 0x00A) -#define NPCX_LFCGCTL2 REG8(NPCX_LFCG_BASE_ADDR + 0x014) +#define NPCX_LFCGCTL REG8(NPCX_LFCG_BASE_ADDR + 0x000) +#define NPCX_HFRDI REG16(NPCX_LFCG_BASE_ADDR + 0x002) +#define NPCX_HFRDF REG16(NPCX_LFCG_BASE_ADDR + 0x004) +#define NPCX_FRCDIV REG16(NPCX_LFCG_BASE_ADDR + 0x006) +#define NPCX_DIVCOR1 REG16(NPCX_LFCG_BASE_ADDR + 0x008) +#define NPCX_DIVCOR2 REG16(NPCX_LFCG_BASE_ADDR + 0x00A) +#define NPCX_LFCGCTL2 REG8(NPCX_LFCG_BASE_ADDR + 0x014) /* LFCG register fields */ -#define NPCX_LFCGCTL_XTCLK_VAL 7 -#define NPCX_LFCGCTL2_XT_OSC_SL_EN 6 +#define NPCX_LFCGCTL_XTCLK_VAL 7 +#define NPCX_LFCGCTL2_XT_OSC_SL_EN 6 /******************************************************************************/ /* CR UART Register */ -#define NPCX_UTBUF(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x000) -#define NPCX_URBUF(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x002) -#define NPCX_UICTRL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x004) -#define NPCX_USTAT(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x006) -#define NPCX_UFRS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x008) -#define NPCX_UMDSL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00A) -#define NPCX_UBAUD(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00C) -#define NPCX_UPSR(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00E) +#define NPCX_UTBUF(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x000) +#define NPCX_URBUF(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x002) +#define NPCX_UICTRL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x004) +#define NPCX_USTAT(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x006) +#define NPCX_UFRS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x008) +#define NPCX_UMDSL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00A) +#define NPCX_UBAUD(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00C) +#define NPCX_UPSR(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00E) /******************************************************************************/ /* KBSCAN registers */ -#define NPCX_KBSIN REG8(NPCX_KBSCAN_REGS_BASE + 0x04) -#define NPCX_KBSINPU REG8(NPCX_KBSCAN_REGS_BASE + 0x05) -#define NPCX_KBSOUT0 REG16(NPCX_KBSCAN_REGS_BASE + 0x06) -#define NPCX_KBSOUT1 REG16(NPCX_KBSCAN_REGS_BASE + 0x08) -#define NPCX_KBS_BUF_INDX REG8(NPCX_KBSCAN_REGS_BASE + 0x0A) -#define NPCX_KBS_BUF_DATA REG8(NPCX_KBSCAN_REGS_BASE + 0x0B) -#define NPCX_KBSEVT REG8(NPCX_KBSCAN_REGS_BASE + 0x0C) -#define NPCX_KBSCTL REG8(NPCX_KBSCAN_REGS_BASE + 0x0D) -#define NPCX_KBS_CFG_INDX REG8(NPCX_KBSCAN_REGS_BASE + 0x0E) -#define NPCX_KBS_CFG_DATA REG8(NPCX_KBSCAN_REGS_BASE + 0x0F) +#define NPCX_KBSIN REG8(NPCX_KBSCAN_REGS_BASE + 0x04) +#define NPCX_KBSINPU REG8(NPCX_KBSCAN_REGS_BASE + 0x05) +#define NPCX_KBSOUT0 REG16(NPCX_KBSCAN_REGS_BASE + 0x06) +#define NPCX_KBSOUT1 REG16(NPCX_KBSCAN_REGS_BASE + 0x08) +#define NPCX_KBS_BUF_INDX REG8(NPCX_KBSCAN_REGS_BASE + 0x0A) +#define NPCX_KBS_BUF_DATA REG8(NPCX_KBSCAN_REGS_BASE + 0x0B) +#define NPCX_KBSEVT REG8(NPCX_KBSCAN_REGS_BASE + 0x0C) +#define NPCX_KBSCTL REG8(NPCX_KBSCAN_REGS_BASE + 0x0D) +#define NPCX_KBS_CFG_INDX REG8(NPCX_KBSCAN_REGS_BASE + 0x0E) +#define NPCX_KBS_CFG_DATA REG8(NPCX_KBSCAN_REGS_BASE + 0x0F) /* KBSCAN register fields */ -#define NPCX_KBSBUFINDX 0 -#define NPCX_KBSDONE 0 -#define NPCX_KBSERR 1 -#define NPCX_KBSSTART 0 -#define NPCX_KBSMODE 1 -#define NPCX_KBSIEN 2 -#define NPCX_KBSINC 3 -#define NPCX_KBSCFGINDX 0 +#define NPCX_KBSBUFINDX 0 +#define NPCX_KBSDONE 0 +#define NPCX_KBSERR 1 +#define NPCX_KBSSTART 0 +#define NPCX_KBSMODE 1 +#define NPCX_KBSIEN 2 +#define NPCX_KBSINC 3 +#define NPCX_KBSCFGINDX 0 /* KBSCAN definitions */ -#define KB_ROW_NUM 8 /* Rows numbers of keyboard matrix */ -#define KB_COL_NUM 18 /* Columns numbers of keyboard matrix */ -#define KB_ROW_MASK ((1<<KB_ROW_NUM) - 1) /* Mask of rows of keyboard matrix */ +#define KB_ROW_NUM 8 /* Rows numbers of keyboard matrix */ +#define KB_COL_NUM 18 /* Columns numbers of keyboard matrix */ +#define KB_ROW_MASK \ + ((1 << KB_ROW_NUM) - 1) /* Mask of rows of keyboard matrix */ /******************************************************************************/ /* GLUE registers */ -#define NPCX_GLUE_SDPD0 REG8(NPCX_GLUE_REGS_BASE + 0x010) -#define NPCX_GLUE_SDPD1 REG8(NPCX_GLUE_REGS_BASE + 0x012) -#define NPCX_GLUE_SDP_CTS REG8(NPCX_GLUE_REGS_BASE + 0x014) -#define NPCX_GLUE_SMBSEL REG8(NPCX_GLUE_REGS_BASE + 0x021) +#define NPCX_GLUE_SDPD0 REG8(NPCX_GLUE_REGS_BASE + 0x010) +#define NPCX_GLUE_SDPD1 REG8(NPCX_GLUE_REGS_BASE + 0x012) +#define NPCX_GLUE_SDP_CTS REG8(NPCX_GLUE_REGS_BASE + 0x014) +#define NPCX_GLUE_SMBSEL REG8(NPCX_GLUE_REGS_BASE + 0x021) /******************************************************************************/ /* MIWU enumeration */ -enum { - MIWU_TABLE_0, - MIWU_TABLE_1, - MIWU_TABLE_2, - MIWU_TABLE_COUNT -}; +enum { MIWU_TABLE_0, MIWU_TABLE_1, MIWU_TABLE_2, MIWU_TABLE_COUNT }; enum { MIWU_GROUP_1, @@ -281,13 +281,13 @@ enum { /******************************************************************************/ /* GPIO registers */ -#define NPCX_PDOUT(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x000) -#define NPCX_PDIN(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x001) -#define NPCX_PDIR(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x002) -#define NPCX_PPULL(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x003) -#define NPCX_PPUD(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x004) -#define NPCX_PENVDD(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x005) -#define NPCX_PTYPE(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x006) +#define NPCX_PDOUT(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x000) +#define NPCX_PDIN(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x001) +#define NPCX_PDIR(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x002) +#define NPCX_PPULL(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x003) +#define NPCX_PPUD(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x004) +#define NPCX_PENVDD(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x005) +#define NPCX_PTYPE(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x006) /* GPIO enumeration */ enum { @@ -342,954 +342,949 @@ enum { /******************************************************************************/ /* MSWC Registers */ -#define NPCX_MSWCTL1 REG8(NPCX_MSWC_BASE_ADDR + 0x000) -#define NPCX_MSWCTL2 REG8(NPCX_MSWC_BASE_ADDR + 0x002) -#define NPCX_HCBAL REG8(NPCX_MSWC_BASE_ADDR + 0x008) -#define NPCX_HCBAH REG8(NPCX_MSWC_BASE_ADDR + 0x00A) -#define NPCX_SRID_CR REG8(NPCX_MSWC_BASE_ADDR + 0x01C) -#define NPCX_SID_CR REG8(NPCX_MSWC_BASE_ADDR + 0x020) -#define NPCX_DEVICE_ID_CR REG8(NPCX_MSWC_BASE_ADDR + 0x022) +#define NPCX_MSWCTL1 REG8(NPCX_MSWC_BASE_ADDR + 0x000) +#define NPCX_MSWCTL2 REG8(NPCX_MSWC_BASE_ADDR + 0x002) +#define NPCX_HCBAL REG8(NPCX_MSWC_BASE_ADDR + 0x008) +#define NPCX_HCBAH REG8(NPCX_MSWC_BASE_ADDR + 0x00A) +#define NPCX_SRID_CR REG8(NPCX_MSWC_BASE_ADDR + 0x01C) +#define NPCX_SID_CR REG8(NPCX_MSWC_BASE_ADDR + 0x020) +#define NPCX_DEVICE_ID_CR REG8(NPCX_MSWC_BASE_ADDR + 0x022) /* MSWC register fields */ -#define NPCX_MSWCTL1_HRSTOB 0 -#define NPCS_MSWCTL1_HWPRON 1 -#define NPCX_MSWCTL1_PLTRST_ACT 2 -#define NPCX_MSWCTL1_VHCFGA 3 -#define NPCX_MSWCTL1_HCFGLK 4 -#define NPCX_MSWCTL1_PWROFFB 6 -#define NPCX_MSWCTL1_A20MB 7 +#define NPCX_MSWCTL1_HRSTOB 0 +#define NPCS_MSWCTL1_HWPRON 1 +#define NPCX_MSWCTL1_PLTRST_ACT 2 +#define NPCX_MSWCTL1_VHCFGA 3 +#define NPCX_MSWCTL1_HCFGLK 4 +#define NPCX_MSWCTL1_PWROFFB 6 +#define NPCX_MSWCTL1_A20MB 7 /******************************************************************************/ /* System Configuration (SCFG) Registers */ -#define NPCX_DEVCNT REG8(NPCX_SCFG_BASE_ADDR + 0x000) -#define NPCX_STRPST REG8(NPCX_SCFG_BASE_ADDR + 0x001) -#define NPCX_RSTCTL REG8(NPCX_SCFG_BASE_ADDR + 0x002) -#define NPCX_DEV_CTL4 REG8(NPCX_SCFG_BASE_ADDR + 0x006) -#define NPCX_LFCGCALCNT REG8(NPCX_SCFG_BASE_ADDR + 0x021) -#define NPCX_PUPD_EN0 REG8(NPCX_SCFG_BASE_ADDR + 0x028) -#define NPCX_PUPD_EN1 REG8(NPCX_SCFG_BASE_ADDR + 0x029) -#define NPCX_SCFG_VER REG8(NPCX_SCFG_BASE_ADDR + 0x02F) - -#define TEST_BKSL REG8(NPCX_SCFG_BASE_ADDR + 0x037) -#define TEST0 REG8(NPCX_SCFG_BASE_ADDR + 0x038) -#define BLKSEL 0 +#define NPCX_DEVCNT REG8(NPCX_SCFG_BASE_ADDR + 0x000) +#define NPCX_STRPST REG8(NPCX_SCFG_BASE_ADDR + 0x001) +#define NPCX_RSTCTL REG8(NPCX_SCFG_BASE_ADDR + 0x002) +#define NPCX_DEV_CTL4 REG8(NPCX_SCFG_BASE_ADDR + 0x006) +#define NPCX_LFCGCALCNT REG8(NPCX_SCFG_BASE_ADDR + 0x021) +#define NPCX_PUPD_EN0 REG8(NPCX_SCFG_BASE_ADDR + 0x028) +#define NPCX_PUPD_EN1 REG8(NPCX_SCFG_BASE_ADDR + 0x029) +#define NPCX_SCFG_VER REG8(NPCX_SCFG_BASE_ADDR + 0x02F) + +#define TEST_BKSL REG8(NPCX_SCFG_BASE_ADDR + 0x037) +#define TEST0 REG8(NPCX_SCFG_BASE_ADDR + 0x038) +#define BLKSEL 0 /* SCFG register fields */ -#define NPCX_DEVCNT_F_SPI_TRIS 6 -#define NPCX_DEVCNT_HIF_TYP_SEL_FIELD FIELD(2, 2) -#define NPCX_DEVCNT_JEN1_HEN 5 -#define NPCX_DEVCNT_JEN0_HEN 4 -#define NPCX_STRPST_TRIST 1 -#define NPCX_STRPST_TEST 2 -#define NPCX_STRPST_JEN1 4 -#define NPCX_STRPST_JEN0 5 -#define NPCX_STRPST_SPI_COMP 7 -#define NPCX_RSTCTL_VCC1_RST_STS 0 -#define NPCX_RSTCTL_DBGRST_STS 1 -#define NPCX_RSTCTL_VCC1_RST_SCRATCH 3 -#define NPCX_RSTCTL_LRESET_PLTRST_MODE 5 -#define NPCX_RSTCTL_HIPRST_MODE 6 -#define NPCX_DEV_CTL4_F_SPI_SLLK 2 -#define NPCX_DEV_CTL4_SPI_SP_SEL 4 -#define NPCX_DEV_CTL4_WP_IF 5 -#define NPCX_DEV_CTL4_VCC1_RST_LK 6 -#define NPCX_DEVPU0_I2C0_0_PUE 0 -#define NPCX_DEVPU0_I2C0_1_PUE 1 -#define NPCX_DEVPU0_I2C1_0_PUE 2 -#define NPCX_DEVPU0_I2C2_0_PUE 4 -#define NPCX_DEVPU0_I2C3_0_PUE 6 -#define NPCX_DEVPU1_F_SPI_PUD_EN 7 +#define NPCX_DEVCNT_F_SPI_TRIS 6 +#define NPCX_DEVCNT_HIF_TYP_SEL_FIELD FIELD(2, 2) +#define NPCX_DEVCNT_JEN1_HEN 5 +#define NPCX_DEVCNT_JEN0_HEN 4 +#define NPCX_STRPST_TRIST 1 +#define NPCX_STRPST_TEST 2 +#define NPCX_STRPST_JEN1 4 +#define NPCX_STRPST_JEN0 5 +#define NPCX_STRPST_SPI_COMP 7 +#define NPCX_RSTCTL_VCC1_RST_STS 0 +#define NPCX_RSTCTL_DBGRST_STS 1 +#define NPCX_RSTCTL_VCC1_RST_SCRATCH 3 +#define NPCX_RSTCTL_LRESET_PLTRST_MODE 5 +#define NPCX_RSTCTL_HIPRST_MODE 6 +#define NPCX_DEV_CTL4_F_SPI_SLLK 2 +#define NPCX_DEV_CTL4_SPI_SP_SEL 4 +#define NPCX_DEV_CTL4_WP_IF 5 +#define NPCX_DEV_CTL4_VCC1_RST_LK 6 +#define NPCX_DEVPU0_I2C0_0_PUE 0 +#define NPCX_DEVPU0_I2C0_1_PUE 1 +#define NPCX_DEVPU0_I2C1_0_PUE 2 +#define NPCX_DEVPU0_I2C2_0_PUE 4 +#define NPCX_DEVPU0_I2C3_0_PUE 6 +#define NPCX_DEVPU1_F_SPI_PUD_EN 7 /* DEVALT */ /* pin-mux for SPI/FIU */ -#define NPCX_DEVALT0_SPIP_SL 0 -#define NPCX_DEVALT0_GPIO_NO_SPIP 3 -#define NPCX_DEVALT0_F_SPI_CS1_2 4 -#define NPCX_DEVALT0_F_SPI_CS1_1 5 -#define NPCX_DEVALT0_F_SPI_QUAD 6 -#define NPCX_DEVALT0_NO_F_SPI 7 +#define NPCX_DEVALT0_SPIP_SL 0 +#define NPCX_DEVALT0_GPIO_NO_SPIP 3 +#define NPCX_DEVALT0_F_SPI_CS1_2 4 +#define NPCX_DEVALT0_F_SPI_CS1_1 5 +#define NPCX_DEVALT0_F_SPI_QUAD 6 +#define NPCX_DEVALT0_NO_F_SPI 7 /* pin-mux for LPC/eSPI */ -#define NPCX_DEVALT1_KBRST_SL 0 -#define NPCX_DEVALT1_A20M_SL 1 -#define NPCX_DEVALT1_SMI_SL 2 -#define NPCX_DEVALT1_EC_SCI_SL 3 -#define NPCX_DEVALT1_NO_PWRGD 4 -#define NPCX_DEVALT1_RST_OUT_SL 5 -#define NPCX_DEVALT1_CLKRN_SL 6 -#define NPCX_DEVALT1_NO_LPC_ESPI 7 +#define NPCX_DEVALT1_KBRST_SL 0 +#define NPCX_DEVALT1_A20M_SL 1 +#define NPCX_DEVALT1_SMI_SL 2 +#define NPCX_DEVALT1_EC_SCI_SL 3 +#define NPCX_DEVALT1_NO_PWRGD 4 +#define NPCX_DEVALT1_RST_OUT_SL 5 +#define NPCX_DEVALT1_CLKRN_SL 6 +#define NPCX_DEVALT1_NO_LPC_ESPI 7 /* pin-mux for PS2 */ -#define NPCX_DEVALT3_PS2_0_SL 0 -#define NPCX_DEVALT3_PS2_1_SL 1 -#define NPCX_DEVALT3_PS2_2_SL 2 -#define NPCX_DEVALT3_PS2_3_SL 3 -#define NPCX_DEVALTC_PS2_3_SL2 3 +#define NPCX_DEVALT3_PS2_0_SL 0 +#define NPCX_DEVALT3_PS2_1_SL 1 +#define NPCX_DEVALT3_PS2_2_SL 2 +#define NPCX_DEVALT3_PS2_3_SL 3 +#define NPCX_DEVALTC_PS2_3_SL2 3 /* pin-mux for Tacho */ -#define NPCX_DEVALT3_TA1_SL1 4 -#define NPCX_DEVALT3_TB1_SL1 5 -#define NPCX_DEVALT3_TA2_SL1 6 -#define NPCX_DEVALT3_TB2_SL1 7 -#define NPCX_DEVALTC_TA1_SL2 4 -#define NPCX_DEVALTC_TB1_SL2 5 -#define NPCX_DEVALTC_TA2_SL2 6 -#define NPCX_DEVALTC_TB2_SL2 7 +#define NPCX_DEVALT3_TA1_SL1 4 +#define NPCX_DEVALT3_TB1_SL1 5 +#define NPCX_DEVALT3_TA2_SL1 6 +#define NPCX_DEVALT3_TB2_SL1 7 +#define NPCX_DEVALTC_TA1_SL2 4 +#define NPCX_DEVALTC_TB1_SL2 5 +#define NPCX_DEVALTC_TA2_SL2 6 +#define NPCX_DEVALTC_TB2_SL2 7 /* pin-mux for PWM */ -#define NPCX_DEVALT4_PWM0_SL 0 -#define NPCX_DEVALT4_PWM1_SL 1 -#define NPCX_DEVALT4_PWM2_SL 2 -#define NPCX_DEVALT4_PWM3_SL 3 -#define NPCX_DEVALT4_PWM4_SL 4 -#define NPCX_DEVALT4_PWM5_SL 5 -#define NPCX_DEVALT4_PWM6_SL 6 -#define NPCX_DEVALT4_PWM7_SL 7 +#define NPCX_DEVALT4_PWM0_SL 0 +#define NPCX_DEVALT4_PWM1_SL 1 +#define NPCX_DEVALT4_PWM2_SL 2 +#define NPCX_DEVALT4_PWM3_SL 3 +#define NPCX_DEVALT4_PWM4_SL 4 +#define NPCX_DEVALT4_PWM5_SL 5 +#define NPCX_DEVALT4_PWM6_SL 6 +#define NPCX_DEVALT4_PWM7_SL 7 /* pin-mux for JTAG */ -#define NPCX_DEVALT5_TRACE_EN 0 +#define NPCX_DEVALT5_TRACE_EN 0 /* pin-mux for ADC */ -#define NPCX_DEVALT6_ADC0_SL 0 -#define NPCX_DEVALT6_ADC1_SL 1 -#define NPCX_DEVALT6_ADC2_SL 2 -#define NPCX_DEVALT6_ADC3_SL 3 -#define NPCX_DEVALT6_ADC4_SL 4 +#define NPCX_DEVALT6_ADC0_SL 0 +#define NPCX_DEVALT6_ADC1_SL 1 +#define NPCX_DEVALT6_ADC2_SL 2 +#define NPCX_DEVALT6_ADC3_SL 3 +#define NPCX_DEVALT6_ADC4_SL 4 /* pin-mux for Keyboard */ -#define NPCX_DEVALT7_NO_KSI0_SL 0 -#define NPCX_DEVALT7_NO_KSI1_SL 1 -#define NPCX_DEVALT7_NO_KSI2_SL 2 -#define NPCX_DEVALT7_NO_KSI3_SL 3 -#define NPCX_DEVALT7_NO_KSI4_SL 4 -#define NPCX_DEVALT7_NO_KSI5_SL 5 -#define NPCX_DEVALT7_NO_KSI6_SL 6 -#define NPCX_DEVALT7_NO_KSI7_SL 7 -#define NPCX_DEVALT8_NO_KSO00_SL 0 -#define NPCX_DEVALT8_NO_KSO01_SL 1 -#define NPCX_DEVALT8_NO_KSO02_SL 2 -#define NPCX_DEVALT8_NO_KSO03_SL 3 -#define NPCX_DEVALT8_NO_KSO04_SL 4 -#define NPCX_DEVALT8_NO_KSO05_SL 5 -#define NPCX_DEVALT8_NO_KSO06_SL 6 -#define NPCX_DEVALT8_NO_KSO07_SL 7 -#define NPCX_DEVALT9_NO_KSO08_SL 0 -#define NPCX_DEVALT9_NO_KSO09_SL 1 -#define NPCX_DEVALT9_NO_KSO10_SL 2 -#define NPCX_DEVALT9_NO_KSO11_SL 3 -#define NPCX_DEVALT9_NO_KSO12_SL 4 -#define NPCX_DEVALT9_NO_KSO13_SL 5 -#define NPCX_DEVALT9_NO_KSO14_SL 6 -#define NPCX_DEVALT9_NO_KSO15_SL 7 -#define NPCX_DEVALTA_NO_KSO16_SL 0 -#define NPCX_DEVALTA_NO_KSO17_SL 1 +#define NPCX_DEVALT7_NO_KSI0_SL 0 +#define NPCX_DEVALT7_NO_KSI1_SL 1 +#define NPCX_DEVALT7_NO_KSI2_SL 2 +#define NPCX_DEVALT7_NO_KSI3_SL 3 +#define NPCX_DEVALT7_NO_KSI4_SL 4 +#define NPCX_DEVALT7_NO_KSI5_SL 5 +#define NPCX_DEVALT7_NO_KSI6_SL 6 +#define NPCX_DEVALT7_NO_KSI7_SL 7 +#define NPCX_DEVALT8_NO_KSO00_SL 0 +#define NPCX_DEVALT8_NO_KSO01_SL 1 +#define NPCX_DEVALT8_NO_KSO02_SL 2 +#define NPCX_DEVALT8_NO_KSO03_SL 3 +#define NPCX_DEVALT8_NO_KSO04_SL 4 +#define NPCX_DEVALT8_NO_KSO05_SL 5 +#define NPCX_DEVALT8_NO_KSO06_SL 6 +#define NPCX_DEVALT8_NO_KSO07_SL 7 +#define NPCX_DEVALT9_NO_KSO08_SL 0 +#define NPCX_DEVALT9_NO_KSO09_SL 1 +#define NPCX_DEVALT9_NO_KSO10_SL 2 +#define NPCX_DEVALT9_NO_KSO11_SL 3 +#define NPCX_DEVALT9_NO_KSO12_SL 4 +#define NPCX_DEVALT9_NO_KSO13_SL 5 +#define NPCX_DEVALT9_NO_KSO14_SL 6 +#define NPCX_DEVALT9_NO_KSO15_SL 7 +#define NPCX_DEVALTA_NO_KSO16_SL 0 +#define NPCX_DEVALTA_NO_KSO17_SL 1 /* pin-mux for Others */ -#define NPCX_DEVALTA_32K_OUT_SL 2 -#define NPCX_DEVALTA_NO_VCC1_RST 4 -#define NPCX_DEVALTA_NO_PECI_EN 6 -#define NPCX_DEVALTC_SHI_SL 1 +#define NPCX_DEVALTA_32K_OUT_SL 2 +#define NPCX_DEVALTA_NO_VCC1_RST 4 +#define NPCX_DEVALTA_NO_PECI_EN 6 +#define NPCX_DEVALTC_SHI_SL 1 /* Others bit definitions */ -#define NPCX_LFCGCALCNT_LPREG_CTL_EN 1 +#define NPCX_LFCGCALCNT_LPREG_CTL_EN 1 /******************************************************************************/ /* Development and Debug Support (DBG) Registers */ -#define NPCX_DBGCTRL REG8(NPCX_SCFG_BASE_ADDR + 0x074) -#define NPCX_DBGFRZEN1 REG8(NPCX_SCFG_BASE_ADDR + 0x076) -#define NPCX_DBGFRZEN2 REG8(NPCX_SCFG_BASE_ADDR + 0x077) -#define NPCX_DBGFRZEN3 REG8(NPCX_SCFG_BASE_ADDR + 0x078) +#define NPCX_DBGCTRL REG8(NPCX_SCFG_BASE_ADDR + 0x074) +#define NPCX_DBGFRZEN1 REG8(NPCX_SCFG_BASE_ADDR + 0x076) +#define NPCX_DBGFRZEN2 REG8(NPCX_SCFG_BASE_ADDR + 0x077) +#define NPCX_DBGFRZEN3 REG8(NPCX_SCFG_BASE_ADDR + 0x078) /* DBG register fields */ -#define NPCX_DBGFRZEN3_GLBL_FRZ_DIS 7 +#define NPCX_DBGFRZEN3_GLBL_FRZ_DIS 7 /******************************************************************************/ /* SMBus Registers */ -#define NPCX_SMBSDA(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x000) -#define NPCX_SMBST(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x002) -#define NPCX_SMBCST(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x004) -#define NPCX_SMBCTL1(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x006) -#define NPCX_SMBADDR1(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x008) -#define NPCX_SMBTMR_ST(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x009) -#define NPCX_SMBCTL2(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x00A) -#define NPCX_SMBTMR_EN(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x00B) -#define NPCX_SMBADDR2(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x00C) -#define NPCX_SMBCTL3(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x00E) +#define NPCX_SMBSDA(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x000) +#define NPCX_SMBST(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x002) +#define NPCX_SMBCST(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x004) +#define NPCX_SMBCTL1(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x006) +#define NPCX_SMBADDR1(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x008) +#define NPCX_SMBTMR_ST(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x009) +#define NPCX_SMBCTL2(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x00A) +#define NPCX_SMBTMR_EN(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x00B) +#define NPCX_SMBADDR2(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x00C) +#define NPCX_SMBCTL3(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x00E) /* SMB Registers in bank 0 */ -#define NPCX_SMBADDR3(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x010) -#define NPCX_SMBADDR7(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x011) -#define NPCX_SMBADDR4(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x012) -#define NPCX_SMBADDR8(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x013) -#define NPCX_SMBADDR5(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x014) -#define NPCX_SMBADDR6(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x016) -#define NPCX_SMBCST2(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x018) -#define NPCX_SMBCST3(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x019) -#define NPCX_SMBCTL4(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01A) -#define NPCX_SMBSCLLT(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01C) -#define NPCX_SMBFIF_CTL(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01D) -#define NPCX_SMBSCLHT(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01E) +#define NPCX_SMBADDR3(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x010) +#define NPCX_SMBADDR7(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x011) +#define NPCX_SMBADDR4(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x012) +#define NPCX_SMBADDR8(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x013) +#define NPCX_SMBADDR5(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x014) +#define NPCX_SMBADDR6(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x016) +#define NPCX_SMBCST2(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x018) +#define NPCX_SMBCST3(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x019) +#define NPCX_SMBCTL4(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01A) +#define NPCX_SMBSCLLT(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01C) +#define NPCX_SMBFIF_CTL(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01D) +#define NPCX_SMBSCLHT(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01E) /* SMB Registers in bank 1 */ -#define NPCX_SMBFIF_CTS(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x010) -#define NPCX_SMBTXF_CTL(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x012) -#define NPCX_SMB_T_OUT(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x014) +#define NPCX_SMBFIF_CTS(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x010) +#define NPCX_SMBTXF_CTL(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x012) +#define NPCX_SMB_T_OUT(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x014) /* * These two registers are the same as in bank 0 * #define NPCX_SMBCST2(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x018) * #define NPCX_SMBCST3(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x019) */ -#define NPCX_SMBTXF_STS(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01A) -#define NPCX_SMBRXF_STS(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01C) -#define NPCX_SMBRXF_CTL(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01E) +#define NPCX_SMBTXF_STS(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01A) +#define NPCX_SMBRXF_STS(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01C) +#define NPCX_SMBRXF_CTL(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01E) /* SMBus register fields */ -#define NPCX_SMBST_XMIT 0 -#define NPCX_SMBST_MASTER 1 -#define NPCX_SMBST_NMATCH 2 -#define NPCX_SMBST_STASTR 3 -#define NPCX_SMBST_NEGACK 4 -#define NPCX_SMBST_BER 5 -#define NPCX_SMBST_SDAST 6 -#define NPCX_SMBST_SLVSTP 7 -#define NPCX_SMBCST_BUSY 0 -#define NPCX_SMBCST_BB 1 -#define NPCX_SMBCST_MATCH 2 -#define NPCX_SMBCST_GCMATCH 3 -#define NPCX_SMBCST_TSDA 4 -#define NPCX_SMBCST_TGSCL 5 -#define NPCX_SMBCST_MATCHAF 6 -#define NPCX_SMBCST_ARPMATCH 7 -#define NPCX_SMBCST2_MATCHA1F 0 -#define NPCX_SMBCST2_MATCHA2F 1 -#define NPCX_SMBCST2_MATCHA3F 2 -#define NPCX_SMBCST2_MATCHA4F 3 -#define NPCX_SMBCST2_MATCHA5F 4 -#define NPCX_SMBCST2_MATCHA6F 5 -#define NPCX_SMBCST2_MATCHA7F 6 -#define NPCX_SMBCST2_INTSTS 7 -#define NPCX_SMBCST3_MATCHA8F 0 -#define NPCX_SMBCST3_MATCHA9F 1 -#define NPCX_SMBCST3_MATCHA10F 2 -#define NPCX_SMBCTL1_START 0 -#define NPCX_SMBCTL1_STOP 1 -#define NPCX_SMBCTL1_INTEN 2 -#define NPCX_SMBCTL1_ACK 4 -#define NPCX_SMBCTL1_GCMEN 5 -#define NPCX_SMBCTL1_NMINTE 6 -#define NPCX_SMBCTL1_STASTRE 7 -#define NPCX_SMBCTL2_ENABLE 0 -#define NPCX_SMBCTL2_SCLFRQ7_FIELD FIELD(1, 7) -#define NPCX_SMBCTL3_ARPMEN 2 -#define NPCX_SMBCTL3_SCLFRQ2_FIELD FIELD(0, 2) -#define NPCX_SMBCTL3_IDL_START 3 -#define NPCX_SMBCTL3_400K 4 -#define NPCX_SMBCTL3_BNK_SEL 5 -#define NPCX_SMBCTL3_SDA_LVL 6 -#define NPCX_SMBCTL3_SCL_LVL 7 -#define NPCX_SMBCTL4_HLDT_FIELD FIELD(0, 6) -#define NPCX_SMBCTL4_LVL_WE 7 -#define NPCX_SMBADDR1_SAEN 7 -#define NPCX_SMBADDR2_SAEN 7 -#define NPCX_SMBADDR3_SAEN 7 -#define NPCX_SMBADDR4_SAEN 7 -#define NPCX_SMBADDR5_SAEN 7 -#define NPCX_SMBADDR6_SAEN 7 -#define NPCX_SMBADDR7_SAEN 7 -#define NPCX_SMBADDR8_SAEN 7 -#define NPCX_SMBFIF_CTS_RXF_TXE 1 -#define NPCX_SMBFIF_CTS_CLR_FIFO 6 - -#define NPCX_SMBFIF_CTL_FIFO_EN 4 - -#define NPCX_SMBRXF_STS_RX_THST 6 +#define NPCX_SMBST_XMIT 0 +#define NPCX_SMBST_MASTER 1 +#define NPCX_SMBST_NMATCH 2 +#define NPCX_SMBST_STASTR 3 +#define NPCX_SMBST_NEGACK 4 +#define NPCX_SMBST_BER 5 +#define NPCX_SMBST_SDAST 6 +#define NPCX_SMBST_SLVSTP 7 +#define NPCX_SMBCST_BUSY 0 +#define NPCX_SMBCST_BB 1 +#define NPCX_SMBCST_MATCH 2 +#define NPCX_SMBCST_GCMATCH 3 +#define NPCX_SMBCST_TSDA 4 +#define NPCX_SMBCST_TGSCL 5 +#define NPCX_SMBCST_MATCHAF 6 +#define NPCX_SMBCST_ARPMATCH 7 +#define NPCX_SMBCST2_MATCHA1F 0 +#define NPCX_SMBCST2_MATCHA2F 1 +#define NPCX_SMBCST2_MATCHA3F 2 +#define NPCX_SMBCST2_MATCHA4F 3 +#define NPCX_SMBCST2_MATCHA5F 4 +#define NPCX_SMBCST2_MATCHA6F 5 +#define NPCX_SMBCST2_MATCHA7F 6 +#define NPCX_SMBCST2_INTSTS 7 +#define NPCX_SMBCST3_MATCHA8F 0 +#define NPCX_SMBCST3_MATCHA9F 1 +#define NPCX_SMBCST3_MATCHA10F 2 +#define NPCX_SMBCTL1_START 0 +#define NPCX_SMBCTL1_STOP 1 +#define NPCX_SMBCTL1_INTEN 2 +#define NPCX_SMBCTL1_ACK 4 +#define NPCX_SMBCTL1_GCMEN 5 +#define NPCX_SMBCTL1_NMINTE 6 +#define NPCX_SMBCTL1_STASTRE 7 +#define NPCX_SMBCTL2_ENABLE 0 +#define NPCX_SMBCTL2_SCLFRQ7_FIELD FIELD(1, 7) +#define NPCX_SMBCTL3_ARPMEN 2 +#define NPCX_SMBCTL3_SCLFRQ2_FIELD FIELD(0, 2) +#define NPCX_SMBCTL3_IDL_START 3 +#define NPCX_SMBCTL3_400K 4 +#define NPCX_SMBCTL3_BNK_SEL 5 +#define NPCX_SMBCTL3_SDA_LVL 6 +#define NPCX_SMBCTL3_SCL_LVL 7 +#define NPCX_SMBCTL4_HLDT_FIELD FIELD(0, 6) +#define NPCX_SMBCTL4_LVL_WE 7 +#define NPCX_SMBADDR1_SAEN 7 +#define NPCX_SMBADDR2_SAEN 7 +#define NPCX_SMBADDR3_SAEN 7 +#define NPCX_SMBADDR4_SAEN 7 +#define NPCX_SMBADDR5_SAEN 7 +#define NPCX_SMBADDR6_SAEN 7 +#define NPCX_SMBADDR7_SAEN 7 +#define NPCX_SMBADDR8_SAEN 7 +#define NPCX_SMBFIF_CTS_RXF_TXE 1 +#define NPCX_SMBFIF_CTS_CLR_FIFO 6 + +#define NPCX_SMBFIF_CTL_FIFO_EN 4 + +#define NPCX_SMBRXF_STS_RX_THST 6 /* RX FIFO threshold */ -#define NPCX_SMBRXF_CTL_RX_THR FIELD(0, 6) +#define NPCX_SMBRXF_CTL_RX_THR FIELD(0, 6) /* * In controller receiving mode, last byte in FIFO should send ACK or NACK */ -#define NPCX_SMBRXF_CTL_LAST 7 +#define NPCX_SMBRXF_CTL_LAST 7 /******************************************************************************/ /* Power Management Controller (PMC) Registers */ -#define NPCX_PMCSR REG8(NPCX_PMC_BASE_ADDR + 0x000) -#define NPCX_ENIDL_CTL REG8(NPCX_PMC_BASE_ADDR + 0x003) -#define NPCX_DISIDL_CTL REG8(NPCX_PMC_BASE_ADDR + 0x004) -#define NPCX_DISIDL_CTL1 REG8(NPCX_PMC_BASE_ADDR + 0x005) -#define NPCX_PWDWN_CTL_ADDR(offset) (((offset) < 6) ? \ - (NPCX_PMC_BASE_ADDR + 0x008 + (offset)) : \ - (NPCX_PMC_BASE_ADDR + 0x024 + (offset) - 6)) -#define NPCX_PWDWN_CTL(offset) REG8(NPCX_PWDWN_CTL_ADDR(offset)) +#define NPCX_PMCSR REG8(NPCX_PMC_BASE_ADDR + 0x000) +#define NPCX_ENIDL_CTL REG8(NPCX_PMC_BASE_ADDR + 0x003) +#define NPCX_DISIDL_CTL REG8(NPCX_PMC_BASE_ADDR + 0x004) +#define NPCX_DISIDL_CTL1 REG8(NPCX_PMC_BASE_ADDR + 0x005) +#define NPCX_PWDWN_CTL_ADDR(offset) \ + (((offset) < 6) ? (NPCX_PMC_BASE_ADDR + 0x008 + (offset)) : \ + (NPCX_PMC_BASE_ADDR + 0x024 + (offset)-6)) +#define NPCX_PWDWN_CTL(offset) REG8(NPCX_PWDWN_CTL_ADDR(offset)) /* PMC register fields */ -#define NPCX_PMCSR_DI_INSTW 0 -#define NPCX_PMCSR_DHF 1 -#define NPCX_PMCSR_IDLE 2 -#define NPCX_PMCSR_NWBI 3 -#define NPCX_PMCSR_OHFC 6 -#define NPCX_PMCSR_OLFC 7 -#define NPCX_DISIDL_CTL_RAM_DID 5 -#define NPCX_ENIDL_CTL_ADC_LFSL 7 -#define NPCX_ENIDL_CTL_LP_WK_CTL 6 -#define NPCX_ENIDL_CTL_PECI_ENI 2 -#define NPCX_ENIDL_CTL_ADC_ACC_DIS 1 -#define NPCX_PWDWN_CTL1_KBS_PD 0 -#define NPCX_PWDWN_CTL1_SDP_PD 1 -#define NPCX_PWDWN_CTL1_FIU_PD 2 -#define NPCX_PWDWN_CTL1_PS2_PD 3 -#define NPCX_PWDWN_CTL1_UART_PD 4 -#define NPCX_PWDWN_CTL1_MFT1_PD 5 -#define NPCX_PWDWN_CTL1_MFT2_PD 6 -#define NPCX_PWDWN_CTL1_MFT3_PD 7 -#define NPCX_PWDWN_CTL2_PWM0_PD 0 -#define NPCX_PWDWN_CTL2_PWM1_PD 1 -#define NPCX_PWDWN_CTL2_PWM2_PD 2 -#define NPCX_PWDWN_CTL2_PWM3_PD 3 -#define NPCX_PWDWN_CTL2_PWM4_PD 4 -#define NPCX_PWDWN_CTL2_PWM5_PD 5 -#define NPCX_PWDWN_CTL2_PWM6_PD 6 -#define NPCX_PWDWN_CTL2_PWM7_PD 7 -#define NPCX_PWDWN_CTL3_SMB0_PD 0 -#define NPCX_PWDWN_CTL3_SMB1_PD 1 -#define NPCX_PWDWN_CTL3_SMB2_PD 2 -#define NPCX_PWDWN_CTL3_SMB3_PD 3 -#define NPCX_PWDWN_CTL3_GMDA_PD 7 -#define NPCX_PWDWN_CTL4_ITIM1_PD 0 -#define NPCX_PWDWN_CTL4_ITIM2_PD 1 -#define NPCX_PWDWN_CTL4_ITIM3_PD 2 -#define NPCX_PWDWN_CTL4_ADC_PD 4 -#define NPCX_PWDWN_CTL4_PECI_PD 5 -#define NPCX_PWDWN_CTL4_PWM6_PD 6 -#define NPCX_PWDWN_CTL4_SPIP_PD 7 -#define NPCX_PWDWN_CTL5_SHI_PD 1 -#define NPCX_PWDWN_CTL5_MRFSH_DIS 2 -#define NPCX_PWDWN_CTL5_C2HACC_PD 3 -#define NPCX_PWDWN_CTL5_SHM_REG_PD 4 -#define NPCX_PWDWN_CTL5_SHM_PD 5 -#define NPCX_PWDWN_CTL5_DP80_PD 6 -#define NPCX_PWDWN_CTL5_MSWC_PD 7 -#define NPCX_PWDWN_CTL6_ITIM4_PD 0 -#define NPCX_PWDWN_CTL6_ITIM5_PD 1 -#define NPCX_PWDWN_CTL6_ITIM6_PD 2 -#define NPCX_PWDWN_CTL6_ESPI_PD 7 +#define NPCX_PMCSR_DI_INSTW 0 +#define NPCX_PMCSR_DHF 1 +#define NPCX_PMCSR_IDLE 2 +#define NPCX_PMCSR_NWBI 3 +#define NPCX_PMCSR_OHFC 6 +#define NPCX_PMCSR_OLFC 7 +#define NPCX_DISIDL_CTL_RAM_DID 5 +#define NPCX_ENIDL_CTL_ADC_LFSL 7 +#define NPCX_ENIDL_CTL_LP_WK_CTL 6 +#define NPCX_ENIDL_CTL_PECI_ENI 2 +#define NPCX_ENIDL_CTL_ADC_ACC_DIS 1 +#define NPCX_PWDWN_CTL1_KBS_PD 0 +#define NPCX_PWDWN_CTL1_SDP_PD 1 +#define NPCX_PWDWN_CTL1_FIU_PD 2 +#define NPCX_PWDWN_CTL1_PS2_PD 3 +#define NPCX_PWDWN_CTL1_UART_PD 4 +#define NPCX_PWDWN_CTL1_MFT1_PD 5 +#define NPCX_PWDWN_CTL1_MFT2_PD 6 +#define NPCX_PWDWN_CTL1_MFT3_PD 7 +#define NPCX_PWDWN_CTL2_PWM0_PD 0 +#define NPCX_PWDWN_CTL2_PWM1_PD 1 +#define NPCX_PWDWN_CTL2_PWM2_PD 2 +#define NPCX_PWDWN_CTL2_PWM3_PD 3 +#define NPCX_PWDWN_CTL2_PWM4_PD 4 +#define NPCX_PWDWN_CTL2_PWM5_PD 5 +#define NPCX_PWDWN_CTL2_PWM6_PD 6 +#define NPCX_PWDWN_CTL2_PWM7_PD 7 +#define NPCX_PWDWN_CTL3_SMB0_PD 0 +#define NPCX_PWDWN_CTL3_SMB1_PD 1 +#define NPCX_PWDWN_CTL3_SMB2_PD 2 +#define NPCX_PWDWN_CTL3_SMB3_PD 3 +#define NPCX_PWDWN_CTL3_GMDA_PD 7 +#define NPCX_PWDWN_CTL4_ITIM1_PD 0 +#define NPCX_PWDWN_CTL4_ITIM2_PD 1 +#define NPCX_PWDWN_CTL4_ITIM3_PD 2 +#define NPCX_PWDWN_CTL4_ADC_PD 4 +#define NPCX_PWDWN_CTL4_PECI_PD 5 +#define NPCX_PWDWN_CTL4_PWM6_PD 6 +#define NPCX_PWDWN_CTL4_SPIP_PD 7 +#define NPCX_PWDWN_CTL5_SHI_PD 1 +#define NPCX_PWDWN_CTL5_MRFSH_DIS 2 +#define NPCX_PWDWN_CTL5_C2HACC_PD 3 +#define NPCX_PWDWN_CTL5_SHM_REG_PD 4 +#define NPCX_PWDWN_CTL5_SHM_PD 5 +#define NPCX_PWDWN_CTL5_DP80_PD 6 +#define NPCX_PWDWN_CTL5_MSWC_PD 7 +#define NPCX_PWDWN_CTL6_ITIM4_PD 0 +#define NPCX_PWDWN_CTL6_ITIM5_PD 1 +#define NPCX_PWDWN_CTL6_ITIM6_PD 2 +#define NPCX_PWDWN_CTL6_ESPI_PD 7 /* TODO: set PD masks based upon actual peripheral usage */ -#define CGC_KBS_MASK BIT(NPCX_PWDWN_CTL1_KBS_PD) -#define CGC_UART_MASK BIT(NPCX_PWDWN_CTL1_UART_PD) -#define CGC_FAN_MASK (BIT(NPCX_PWDWN_CTL1_MFT1_PD) | \ - BIT(NPCX_PWDWN_CTL1_MFT2_PD)) -#define CGC_FIU_MASK BIT(NPCX_PWDWN_CTL1_FIU_PD) -#define CGC_PS2_MASK BIT(NPCX_PWDWN_CTL1_PS2_PD) -#define CGC_ADC_MASK BIT(NPCX_PWDWN_CTL4_ADC_PD) -#define CGC_PECI_MASK BIT(NPCX_PWDWN_CTL4_PECI_PD) -#define CGC_SPI_MASK BIT(NPCX_PWDWN_CTL4_SPIP_PD) -#define CGC_TIMER_MASK (BIT(NPCX_PWDWN_CTL4_ITIM1_PD) | \ - BIT(NPCX_PWDWN_CTL4_ITIM2_PD) | \ - BIT(NPCX_PWDWN_CTL4_ITIM3_PD)) -#define CGC_LPC_MASK (BIT(NPCX_PWDWN_CTL5_C2HACC_PD) | \ - BIT(NPCX_PWDWN_CTL5_SHM_REG_PD) | \ - BIT(NPCX_PWDWN_CTL5_SHM_PD) | \ - BIT(NPCX_PWDWN_CTL5_DP80_PD) | \ - BIT(NPCX_PWDWN_CTL5_MSWC_PD)) -#define CGC_ESPI_MASK BIT(NPCX_PWDWN_CTL6_ESPI_PD) +#define CGC_KBS_MASK BIT(NPCX_PWDWN_CTL1_KBS_PD) +#define CGC_UART_MASK BIT(NPCX_PWDWN_CTL1_UART_PD) +#define CGC_FAN_MASK \ + (BIT(NPCX_PWDWN_CTL1_MFT1_PD) | BIT(NPCX_PWDWN_CTL1_MFT2_PD)) +#define CGC_FIU_MASK BIT(NPCX_PWDWN_CTL1_FIU_PD) +#define CGC_PS2_MASK BIT(NPCX_PWDWN_CTL1_PS2_PD) +#define CGC_ADC_MASK BIT(NPCX_PWDWN_CTL4_ADC_PD) +#define CGC_PECI_MASK BIT(NPCX_PWDWN_CTL4_PECI_PD) +#define CGC_SPI_MASK BIT(NPCX_PWDWN_CTL4_SPIP_PD) +#define CGC_TIMER_MASK \ + (BIT(NPCX_PWDWN_CTL4_ITIM1_PD) | BIT(NPCX_PWDWN_CTL4_ITIM2_PD) | \ + BIT(NPCX_PWDWN_CTL4_ITIM3_PD)) +#define CGC_LPC_MASK \ + (BIT(NPCX_PWDWN_CTL5_C2HACC_PD) | BIT(NPCX_PWDWN_CTL5_SHM_REG_PD) | \ + BIT(NPCX_PWDWN_CTL5_SHM_PD) | BIT(NPCX_PWDWN_CTL5_DP80_PD) | \ + BIT(NPCX_PWDWN_CTL5_MSWC_PD)) +#define CGC_ESPI_MASK BIT(NPCX_PWDWN_CTL6_ESPI_PD) /******************************************************************************/ /* Flash Interface Unit (FIU) Registers */ -#define NPCX_FIU_CFG REG8(NPCX_FIU_BASE_ADDR + 0x000) -#define NPCX_BURST_CFG REG8(NPCX_FIU_BASE_ADDR + 0x001) -#define NPCX_RESP_CFG REG8(NPCX_FIU_BASE_ADDR + 0x002) -#define NPCX_SPI_FL_CFG REG8(NPCX_FIU_BASE_ADDR + 0x014) -#define NPCX_UMA_CODE REG8(NPCX_FIU_BASE_ADDR + 0x016) -#define NPCX_UMA_AB0 REG8(NPCX_FIU_BASE_ADDR + 0x017) -#define NPCX_UMA_AB1 REG8(NPCX_FIU_BASE_ADDR + 0x018) -#define NPCX_UMA_AB2 REG8(NPCX_FIU_BASE_ADDR + 0x019) -#define NPCX_UMA_DB0 REG8(NPCX_FIU_BASE_ADDR + 0x01A) -#define NPCX_UMA_DB1 REG8(NPCX_FIU_BASE_ADDR + 0x01B) -#define NPCX_UMA_DB2 REG8(NPCX_FIU_BASE_ADDR + 0x01C) -#define NPCX_UMA_DB3 REG8(NPCX_FIU_BASE_ADDR + 0x01D) -#define NPCX_UMA_CTS REG8(NPCX_FIU_BASE_ADDR + 0x01E) -#define NPCX_UMA_ECTS REG8(NPCX_FIU_BASE_ADDR + 0x01F) -#define NPCX_UMA_DB0_3 REG32(NPCX_FIU_BASE_ADDR + 0x020) -#define NPCX_FIU_RD_CMD REG8(NPCX_FIU_BASE_ADDR + 0x030) -#define NPCX_FIU_DMM_CYC REG8(NPCX_FIU_BASE_ADDR + 0x032) -#define NPCX_FIU_EXT_CFG REG8(NPCX_FIU_BASE_ADDR + 0x033) -#define NPCX_FIU_UMA_AB0_3 REG32(NPCX_FIU_BASE_ADDR + 0x034) +#define NPCX_FIU_CFG REG8(NPCX_FIU_BASE_ADDR + 0x000) +#define NPCX_BURST_CFG REG8(NPCX_FIU_BASE_ADDR + 0x001) +#define NPCX_RESP_CFG REG8(NPCX_FIU_BASE_ADDR + 0x002) +#define NPCX_SPI_FL_CFG REG8(NPCX_FIU_BASE_ADDR + 0x014) +#define NPCX_UMA_CODE REG8(NPCX_FIU_BASE_ADDR + 0x016) +#define NPCX_UMA_AB0 REG8(NPCX_FIU_BASE_ADDR + 0x017) +#define NPCX_UMA_AB1 REG8(NPCX_FIU_BASE_ADDR + 0x018) +#define NPCX_UMA_AB2 REG8(NPCX_FIU_BASE_ADDR + 0x019) +#define NPCX_UMA_DB0 REG8(NPCX_FIU_BASE_ADDR + 0x01A) +#define NPCX_UMA_DB1 REG8(NPCX_FIU_BASE_ADDR + 0x01B) +#define NPCX_UMA_DB2 REG8(NPCX_FIU_BASE_ADDR + 0x01C) +#define NPCX_UMA_DB3 REG8(NPCX_FIU_BASE_ADDR + 0x01D) +#define NPCX_UMA_CTS REG8(NPCX_FIU_BASE_ADDR + 0x01E) +#define NPCX_UMA_ECTS REG8(NPCX_FIU_BASE_ADDR + 0x01F) +#define NPCX_UMA_DB0_3 REG32(NPCX_FIU_BASE_ADDR + 0x020) +#define NPCX_FIU_RD_CMD REG8(NPCX_FIU_BASE_ADDR + 0x030) +#define NPCX_FIU_DMM_CYC REG8(NPCX_FIU_BASE_ADDR + 0x032) +#define NPCX_FIU_EXT_CFG REG8(NPCX_FIU_BASE_ADDR + 0x033) +#define NPCX_FIU_UMA_AB0_3 REG32(NPCX_FIU_BASE_ADDR + 0x034) /* FIU register fields */ -#define NPCX_RESP_CFG_IAD_EN 0 -#define NPCX_RESP_CFG_DEV_SIZE_EX 2 -#define NPCX_UMA_CTS_A_SIZE 3 -#define NPCX_UMA_CTS_C_SIZE 4 -#define NPCX_UMA_CTS_RD_WR 5 -#define NPCX_UMA_CTS_DEV_NUM 6 -#define NPCX_UMA_CTS_EXEC_DONE 7 -#define NPCX_UMA_ECTS_SW_CS0 0 -#define NPCX_UMA_ECTS_SW_CS1 1 -#define NPCX_UMA_ECTS_SEC_CS 2 -#define NPCX_UMA_ECTS_UMA_LOCK 3 +#define NPCX_RESP_CFG_IAD_EN 0 +#define NPCX_RESP_CFG_DEV_SIZE_EX 2 +#define NPCX_UMA_CTS_A_SIZE 3 +#define NPCX_UMA_CTS_C_SIZE 4 +#define NPCX_UMA_CTS_RD_WR 5 +#define NPCX_UMA_CTS_DEV_NUM 6 +#define NPCX_UMA_CTS_EXEC_DONE 7 +#define NPCX_UMA_ECTS_SW_CS0 0 +#define NPCX_UMA_ECTS_SW_CS1 1 +#define NPCX_UMA_ECTS_SEC_CS 2 +#define NPCX_UMA_ECTS_UMA_LOCK 3 /******************************************************************************/ /* Shared Memory (SHM) Registers */ -#define NPCX_SMC_STS REG8(NPCX_SHM_BASE_ADDR + 0x000) -#define NPCX_SMC_CTL REG8(NPCX_SHM_BASE_ADDR + 0x001) -#define NPCX_SHM_CTL REG8(NPCX_SHM_BASE_ADDR + 0x002) -#define NPCX_IMA_WIN_SIZE REG8(NPCX_SHM_BASE_ADDR + 0x005) -#define NPCX_WIN_SIZE REG8(NPCX_SHM_BASE_ADDR + 0x007) -#define NPCX_SHAW_SEM(win) REG8(NPCX_SHM_BASE_ADDR + 0x008 + (win)) -#define NPCX_IMA_SEM REG8(NPCX_SHM_BASE_ADDR + 0x00B) -#define NPCX_SHCFG REG8(NPCX_SHM_BASE_ADDR + 0x00E) -#define NPCX_WIN_WR_PROT(win) REG8(NPCX_SHM_BASE_ADDR + 0x010 + (win*2L)) -#define NPCX_WIN_RD_PROT(win) REG8(NPCX_SHM_BASE_ADDR + 0x011 + (win*2L)) -#define NPCX_IMA_WR_PROT REG8(NPCX_SHM_BASE_ADDR + 0x016) -#define NPCX_IMA_RD_PROT REG8(NPCX_SHM_BASE_ADDR + 0x017) -#define NPCX_WIN_BASE(win) REG32(NPCX_SHM_BASE_ADDR + 0x020 + (win*4L)) - -#define NPCX_PWIN_BASEI(win) REG16(NPCX_SHM_BASE_ADDR + 0x020 + (win*4L)) -#define NPCX_PWIN_SIZEI(win) REG16(NPCX_SHM_BASE_ADDR + 0x022 + (win*4L)) - -#define NPCX_IMA_BASE REG32(NPCX_SHM_BASE_ADDR + 0x02C) -#define NPCX_RST_CFG REG8(NPCX_SHM_BASE_ADDR + 0x03A) -#define NPCX_DP80BUF REG16(NPCX_SHM_BASE_ADDR + 0x040) -#define NPCX_DP80STS REG8(NPCX_SHM_BASE_ADDR + 0x042) -#define NPCX_DP80CTL REG8(NPCX_SHM_BASE_ADDR + 0x044) -#define NPCX_HOFS_STS REG8(NPCX_SHM_BASE_ADDR + 0x048) -#define NPCX_HOFS_CTL REG8(NPCX_SHM_BASE_ADDR + 0x049) -#define NPCX_COFS2 REG16(NPCX_SHM_BASE_ADDR + 0x04A) -#define NPCX_COFS1 REG16(NPCX_SHM_BASE_ADDR + 0x04C) -#define NPCX_IHOFS2 REG16(NPCX_SHM_BASE_ADDR + 0x050) -#define NPCX_IHOFS1 REG16(NPCX_SHM_BASE_ADDR + 0x052) -#define NPCX_SHM_VER REG8(NPCX_SHM_BASE_ADDR + 0x07F) +#define NPCX_SMC_STS REG8(NPCX_SHM_BASE_ADDR + 0x000) +#define NPCX_SMC_CTL REG8(NPCX_SHM_BASE_ADDR + 0x001) +#define NPCX_SHM_CTL REG8(NPCX_SHM_BASE_ADDR + 0x002) +#define NPCX_IMA_WIN_SIZE REG8(NPCX_SHM_BASE_ADDR + 0x005) +#define NPCX_WIN_SIZE REG8(NPCX_SHM_BASE_ADDR + 0x007) +#define NPCX_SHAW_SEM(win) REG8(NPCX_SHM_BASE_ADDR + 0x008 + (win)) +#define NPCX_IMA_SEM REG8(NPCX_SHM_BASE_ADDR + 0x00B) +#define NPCX_SHCFG REG8(NPCX_SHM_BASE_ADDR + 0x00E) +#define NPCX_WIN_WR_PROT(win) REG8(NPCX_SHM_BASE_ADDR + 0x010 + (win * 2L)) +#define NPCX_WIN_RD_PROT(win) REG8(NPCX_SHM_BASE_ADDR + 0x011 + (win * 2L)) +#define NPCX_IMA_WR_PROT REG8(NPCX_SHM_BASE_ADDR + 0x016) +#define NPCX_IMA_RD_PROT REG8(NPCX_SHM_BASE_ADDR + 0x017) +#define NPCX_WIN_BASE(win) REG32(NPCX_SHM_BASE_ADDR + 0x020 + (win * 4L)) + +#define NPCX_PWIN_BASEI(win) REG16(NPCX_SHM_BASE_ADDR + 0x020 + (win * 4L)) +#define NPCX_PWIN_SIZEI(win) REG16(NPCX_SHM_BASE_ADDR + 0x022 + (win * 4L)) + +#define NPCX_IMA_BASE REG32(NPCX_SHM_BASE_ADDR + 0x02C) +#define NPCX_RST_CFG REG8(NPCX_SHM_BASE_ADDR + 0x03A) +#define NPCX_DP80BUF REG16(NPCX_SHM_BASE_ADDR + 0x040) +#define NPCX_DP80STS REG8(NPCX_SHM_BASE_ADDR + 0x042) +#define NPCX_DP80CTL REG8(NPCX_SHM_BASE_ADDR + 0x044) +#define NPCX_HOFS_STS REG8(NPCX_SHM_BASE_ADDR + 0x048) +#define NPCX_HOFS_CTL REG8(NPCX_SHM_BASE_ADDR + 0x049) +#define NPCX_COFS2 REG16(NPCX_SHM_BASE_ADDR + 0x04A) +#define NPCX_COFS1 REG16(NPCX_SHM_BASE_ADDR + 0x04C) +#define NPCX_IHOFS2 REG16(NPCX_SHM_BASE_ADDR + 0x050) +#define NPCX_IHOFS1 REG16(NPCX_SHM_BASE_ADDR + 0x052) +#define NPCX_SHM_VER REG8(NPCX_SHM_BASE_ADDR + 0x07F) /* SHM register fields */ -#define NPCX_SMC_STS_HRERR 0 -#define NPCX_SMC_STS_HWERR 1 -#define NPCX_SMC_STS_HSEM1W 4 -#define NPCX_SMC_STS_HSEM2W 5 -#define NPCX_SMC_STS_SHM_ACC 6 -#define NPCX_SMC_CTL_HERR_IE 2 -#define NPCX_SMC_CTL_HSEM1_IE 3 -#define NPCX_SMC_CTL_HSEM2_IE 4 -#define NPCX_SMC_CTL_ACC_IE 5 -#define NPCX_SMC_CTL_PREF_EN 6 -#define NPCX_SMC_CTL_HOSTWAIT 7 -#define NPCX_FLASH_SIZE_STALL_HOST 6 -#define NPCX_FLASH_SIZE_RD_BURST 7 -#define NPCX_WIN_PROT_RW1L_RP 0 -#define NPCX_WIN_PROT_RW1L_WP 1 -#define NPCX_WIN_PROT_RW1H_RP 2 -#define NPCX_WIN_PROT_RW1H_WP 3 -#define NPCX_WIN_PROT_RW2L_RP 4 -#define NPCX_WIN_PROT_RW2L_WP 5 -#define NPCX_WIN_PROT_RW2H_RP 6 -#define NPCX_WIN_PROT_RW2H_WP 7 -#define NPCX_PWIN_SIZEI_RPROT 13 -#define NPCX_PWIN_SIZEI_WPROT 14 -#define NPCX_CSEM2 6 -#define NPCX_CSEM3 7 -#define NPCX_DP80BUF_OFFS_FIELD FIELD(8, 3) -#define NPCX_DP80STS_FWR 5 -#define NPCX_DP80STS_FNE 6 -#define NPCX_DP80STS_FOR 7 -#define NPCX_DP80CTL_DP80EN 0 -#define NPCX_DP80CTL_SYNCEN 1 -#define NPCX_DP80CTL_RFIFO 4 -#define NPCX_DP80CTL_CIEN 5 +#define NPCX_SMC_STS_HRERR 0 +#define NPCX_SMC_STS_HWERR 1 +#define NPCX_SMC_STS_HSEM1W 4 +#define NPCX_SMC_STS_HSEM2W 5 +#define NPCX_SMC_STS_SHM_ACC 6 +#define NPCX_SMC_CTL_HERR_IE 2 +#define NPCX_SMC_CTL_HSEM1_IE 3 +#define NPCX_SMC_CTL_HSEM2_IE 4 +#define NPCX_SMC_CTL_ACC_IE 5 +#define NPCX_SMC_CTL_PREF_EN 6 +#define NPCX_SMC_CTL_HOSTWAIT 7 +#define NPCX_FLASH_SIZE_STALL_HOST 6 +#define NPCX_FLASH_SIZE_RD_BURST 7 +#define NPCX_WIN_PROT_RW1L_RP 0 +#define NPCX_WIN_PROT_RW1L_WP 1 +#define NPCX_WIN_PROT_RW1H_RP 2 +#define NPCX_WIN_PROT_RW1H_WP 3 +#define NPCX_WIN_PROT_RW2L_RP 4 +#define NPCX_WIN_PROT_RW2L_WP 5 +#define NPCX_WIN_PROT_RW2H_RP 6 +#define NPCX_WIN_PROT_RW2H_WP 7 +#define NPCX_PWIN_SIZEI_RPROT 13 +#define NPCX_PWIN_SIZEI_WPROT 14 +#define NPCX_CSEM2 6 +#define NPCX_CSEM3 7 +#define NPCX_DP80BUF_OFFS_FIELD FIELD(8, 3) +#define NPCX_DP80STS_FWR 5 +#define NPCX_DP80STS_FNE 6 +#define NPCX_DP80STS_FOR 7 +#define NPCX_DP80CTL_DP80EN 0 +#define NPCX_DP80CTL_SYNCEN 1 +#define NPCX_DP80CTL_RFIFO 4 +#define NPCX_DP80CTL_CIEN 5 /******************************************************************************/ /* KBC Registers */ -#define NPCX_HICTRL REG8(NPCX_KBC_BASE_ADDR + 0x000) -#define NPCX_HIIRQC REG8(NPCX_KBC_BASE_ADDR + 0x002) -#define NPCX_HIKMST REG8(NPCX_KBC_BASE_ADDR + 0x004) -#define NPCX_HIKDO REG8(NPCX_KBC_BASE_ADDR + 0x006) -#define NPCX_HIMDO REG8(NPCX_KBC_BASE_ADDR + 0x008) -#define NPCX_KBCVER REG8(NPCX_KBC_BASE_ADDR + 0x009) -#define NPCX_HIKMDI REG8(NPCX_KBC_BASE_ADDR + 0x00A) -#define NPCX_SHIKMDI REG8(NPCX_KBC_BASE_ADDR + 0x00B) +#define NPCX_HICTRL REG8(NPCX_KBC_BASE_ADDR + 0x000) +#define NPCX_HIIRQC REG8(NPCX_KBC_BASE_ADDR + 0x002) +#define NPCX_HIKMST REG8(NPCX_KBC_BASE_ADDR + 0x004) +#define NPCX_HIKDO REG8(NPCX_KBC_BASE_ADDR + 0x006) +#define NPCX_HIMDO REG8(NPCX_KBC_BASE_ADDR + 0x008) +#define NPCX_KBCVER REG8(NPCX_KBC_BASE_ADDR + 0x009) +#define NPCX_HIKMDI REG8(NPCX_KBC_BASE_ADDR + 0x00A) +#define NPCX_SHIKMDI REG8(NPCX_KBC_BASE_ADDR + 0x00B) /* KBC register field */ -#define NPCX_HICTRL_OBFKIE 0 /* Automatic Serial IRQ1 for KBC */ -#define NPCX_HICTRL_OBFMIE 1 /* Automatic Serial IRQ12 for Mouse*/ -#define NPCX_HICTRL_OBECIE 2 /* KBC OBE interrupt enable */ -#define NPCX_HICTRL_IBFCIE 3 /* KBC IBF interrupt enable */ -#define NPCX_HICTRL_PMIHIE 4 /* Automatic Serial IRQ11 for PMC1 */ -#define NPCX_HICTRL_PMIOCIE 5 /* PMC1 OBE interrupt enable */ -#define NPCX_HICTRL_PMICIE 6 /* PMC1 IBF interrupt enable */ -#define NPCX_HICTRL_FW_OBF 7 /* Firmware control over OBF */ - -#define NPCX_HIKMST_OBF 0 /* KB output buffer is full */ +#define NPCX_HICTRL_OBFKIE 0 /* Automatic Serial IRQ1 for KBC */ +#define NPCX_HICTRL_OBFMIE 1 /* Automatic Serial IRQ12 for Mouse*/ +#define NPCX_HICTRL_OBECIE 2 /* KBC OBE interrupt enable */ +#define NPCX_HICTRL_IBFCIE 3 /* KBC IBF interrupt enable */ +#define NPCX_HICTRL_PMIHIE 4 /* Automatic Serial IRQ11 for PMC1 */ +#define NPCX_HICTRL_PMIOCIE 5 /* PMC1 OBE interrupt enable */ +#define NPCX_HICTRL_PMICIE 6 /* PMC1 IBF interrupt enable */ +#define NPCX_HICTRL_FW_OBF 7 /* Firmware control over OBF */ + +#define NPCX_HIKMST_OBF 0 /* KB output buffer is full */ /******************************************************************************/ /* PM Channel Registers */ -#define NPCX_HIPMST(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x000) -#define NPCX_HIPMDO(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x002) -#define NPCX_HIPMDI(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x004) -#define NPCX_SHIPMDI(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x005) -#define NPCX_HIPMDOC(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x006) -#define NPCX_HIPMDOM(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x008) -#define NPCX_HIPMDIC(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00A) -#define NPCX_HIPMCTL(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00C) -#define NPCX_HIPMCTL2(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00D) -#define NPCX_HIPMIC(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00E) -#define NPCX_HIPMIE(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x010) +#define NPCX_HIPMST(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x000) +#define NPCX_HIPMDO(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x002) +#define NPCX_HIPMDI(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x004) +#define NPCX_SHIPMDI(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x005) +#define NPCX_HIPMDOC(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x006) +#define NPCX_HIPMDOM(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x008) +#define NPCX_HIPMDIC(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00A) +#define NPCX_HIPMCTL(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00C) +#define NPCX_HIPMCTL2(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00D) +#define NPCX_HIPMIC(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00E) +#define NPCX_HIPMIE(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x010) /* PM Channel register field */ /* NPCX_HIPMIE */ -#define NPCX_HIPMIE_SCIE 1 -#define NPCX_HIPMIE_SMIE 2 +#define NPCX_HIPMIE_SCIE 1 +#define NPCX_HIPMIE_SMIE 2 /* NPCX_HIPMCTL */ -#define NPCX_HIPMCTL_IBFIE 0 -#define NPCX_HIPMCTL_SCIPOL 6 +#define NPCX_HIPMCTL_IBFIE 0 +#define NPCX_HIPMCTL_SCIPOL 6 /* NPCX_HIPMST */ -#define NPCX_HIPMST_F0 2 /* EC_LPC_CMDR_BUSY */ -#define NPCX_HIPMST_ST0 4 /* EC_LPC_CMDR_ACPI_BRST */ -#define NPCX_HIPMST_ST1 5 /* EC_LPC_CMDR_SCI */ -#define NPCX_HIPMST_ST2 6 /* EC_LPC_CMDR_SMI */ +#define NPCX_HIPMST_F0 2 /* EC_LPC_CMDR_BUSY */ +#define NPCX_HIPMST_ST0 4 /* EC_LPC_CMDR_ACPI_BRST */ +#define NPCX_HIPMST_ST1 5 /* EC_LPC_CMDR_SCI */ +#define NPCX_HIPMST_ST2 6 /* EC_LPC_CMDR_SMI */ /* NPCX_HIPMIC */ -#define NPCX_HIPMIC_SMIB 1 -#define NPCX_HIPMIC_SCIB 2 -#define NPCX_HIPMIC_SMIPOL 6 +#define NPCX_HIPMIC_SMIB 1 +#define NPCX_HIPMIC_SCIB 2 +#define NPCX_HIPMIC_SMIPOL 6 /* * PM Channel enumeration */ -enum PM_CHANNEL_T { - PM_CHAN_1, - PM_CHAN_2, - PM_CHAN_3, - PM_CHAN_4 -}; +enum PM_CHANNEL_T { PM_CHAN_1, PM_CHAN_2, PM_CHAN_3, PM_CHAN_4 }; /******************************************************************************/ /* SuperI/O Internal Bus (SIB) Registers */ -#define NPCX_IHIOA REG16(NPCX_SIB_BASE_ADDR + 0x000) -#define NPCX_IHD REG8(NPCX_SIB_BASE_ADDR + 0x002) -#define NPCX_LKSIOHA REG16(NPCX_SIB_BASE_ADDR + 0x004) -#define NPCX_SIOLV REG16(NPCX_SIB_BASE_ADDR + 0x006) -#define NPCX_CRSMAE REG16(NPCX_SIB_BASE_ADDR + 0x008) -#define NPCX_SIBCTRL REG8(NPCX_SIB_BASE_ADDR + 0x00A) -#define NPCX_C2H_VER REG8(NPCX_SIB_BASE_ADDR + 0x00E) +#define NPCX_IHIOA REG16(NPCX_SIB_BASE_ADDR + 0x000) +#define NPCX_IHD REG8(NPCX_SIB_BASE_ADDR + 0x002) +#define NPCX_LKSIOHA REG16(NPCX_SIB_BASE_ADDR + 0x004) +#define NPCX_SIOLV REG16(NPCX_SIB_BASE_ADDR + 0x006) +#define NPCX_CRSMAE REG16(NPCX_SIB_BASE_ADDR + 0x008) +#define NPCX_SIBCTRL REG8(NPCX_SIB_BASE_ADDR + 0x00A) +#define NPCX_C2H_VER REG8(NPCX_SIB_BASE_ADDR + 0x00E) /* SIB register fields */ -#define NPCX_SIBCTRL_CSAE 0 -#define NPCX_SIBCTRL_CSRD 1 -#define NPCX_SIBCTRL_CSWR 2 -#define NPCX_LKSIOHA_LKCFG 0 -#define NPCX_LKSIOHA_LKHIKBD 11 -#define NPCX_CRSMAE_CFGAE 0 -#define NPCX_CRSMAE_HIKBDAE 11 +#define NPCX_SIBCTRL_CSAE 0 +#define NPCX_SIBCTRL_CSRD 1 +#define NPCX_SIBCTRL_CSWR 2 +#define NPCX_LKSIOHA_LKCFG 0 +#define NPCX_LKSIOHA_LKHIKBD 11 +#define NPCX_CRSMAE_CFGAE 0 +#define NPCX_CRSMAE_HIKBDAE 11 /******************************************************************************/ /* Battery-Backed RAM (BBRAM) Registers */ -#define NPCX_BKUP_STS REG8(NPCX_BBRAM_BASE_ADDR + 0x100) -#define NPCX_BBRAM(offset) REG8(NPCX_BBRAM_BASE_ADDR + offset) +#define NPCX_BKUP_STS REG8(NPCX_BBRAM_BASE_ADDR + 0x100) +#define NPCX_BBRAM(offset) REG8(NPCX_BBRAM_BASE_ADDR + offset) /* BBRAM register fields */ -#define NPCX_BKUP_STS_IBBR 7 +#define NPCX_BKUP_STS_IBBR 7 /******************************************************************************/ /* Timer Watch Dog (TWD) Registers */ -#define NPCX_TWCFG REG8(NPCX_TWD_BASE_ADDR + 0x000) -#define NPCX_TWCP REG8(NPCX_TWD_BASE_ADDR + 0x002) -#define NPCX_TWDT0 REG16(NPCX_TWD_BASE_ADDR + 0x004) -#define NPCX_T0CSR REG8(NPCX_TWD_BASE_ADDR + 0x006) -#define NPCX_WDCNT REG8(NPCX_TWD_BASE_ADDR + 0x008) -#define NPCX_WDSDM REG8(NPCX_TWD_BASE_ADDR + 0x00A) -#define NPCX_TWMT0 REG16(NPCX_TWD_BASE_ADDR + 0x00C) -#define NPCX_TWMWD REG8(NPCX_TWD_BASE_ADDR + 0x00E) -#define NPCX_WDCP REG8(NPCX_TWD_BASE_ADDR + 0x010) +#define NPCX_TWCFG REG8(NPCX_TWD_BASE_ADDR + 0x000) +#define NPCX_TWCP REG8(NPCX_TWD_BASE_ADDR + 0x002) +#define NPCX_TWDT0 REG16(NPCX_TWD_BASE_ADDR + 0x004) +#define NPCX_T0CSR REG8(NPCX_TWD_BASE_ADDR + 0x006) +#define NPCX_WDCNT REG8(NPCX_TWD_BASE_ADDR + 0x008) +#define NPCX_WDSDM REG8(NPCX_TWD_BASE_ADDR + 0x00A) +#define NPCX_TWMT0 REG16(NPCX_TWD_BASE_ADDR + 0x00C) +#define NPCX_TWMWD REG8(NPCX_TWD_BASE_ADDR + 0x00E) +#define NPCX_WDCP REG8(NPCX_TWD_BASE_ADDR + 0x010) /* TWD register fields */ -#define NPCX_TWCFG_LTWCFG 0 -#define NPCX_TWCFG_LTWCP 1 -#define NPCX_TWCFG_LTWDT0 2 -#define NPCX_TWCFG_LWDCNT 3 -#define NPCX_TWCFG_WDCT0I 4 -#define NPCX_TWCFG_WDSDME 5 -#define NPCX_TWCFG_WDRST_MODE 6 -#define NPCX_TWCFG_WDC2POR 7 -#define NPCX_T0CSR_RST 0 -#define NPCX_T0CSR_TC 1 -#define NPCX_T0CSR_WDLTD 3 -#define NPCX_T0CSR_WDRST_STS 4 -#define NPCX_T0CSR_WD_RUN 5 -#define NPCX_T0CSR_TESDIS 7 +#define NPCX_TWCFG_LTWCFG 0 +#define NPCX_TWCFG_LTWCP 1 +#define NPCX_TWCFG_LTWDT0 2 +#define NPCX_TWCFG_LWDCNT 3 +#define NPCX_TWCFG_WDCT0I 4 +#define NPCX_TWCFG_WDSDME 5 +#define NPCX_TWCFG_WDRST_MODE 6 +#define NPCX_TWCFG_WDC2POR 7 +#define NPCX_T0CSR_RST 0 +#define NPCX_T0CSR_TC 1 +#define NPCX_T0CSR_WDLTD 3 +#define NPCX_T0CSR_WDRST_STS 4 +#define NPCX_T0CSR_WD_RUN 5 +#define NPCX_T0CSR_TESDIS 7 /******************************************************************************/ /* SPI Register */ -#define NPCX_SPI_DATA REG16(NPCX_SPI_BASE_ADDR + 0x00) -#define NPCX_SPI_CTL1 REG16(NPCX_SPI_BASE_ADDR + 0x02) -#define NPCX_SPI_STAT REG8(NPCX_SPI_BASE_ADDR + 0x04) +#define NPCX_SPI_DATA REG16(NPCX_SPI_BASE_ADDR + 0x00) +#define NPCX_SPI_CTL1 REG16(NPCX_SPI_BASE_ADDR + 0x02) +#define NPCX_SPI_STAT REG8(NPCX_SPI_BASE_ADDR + 0x04) /* SPI register fields */ -#define NPCX_SPI_CTL1_SPIEN 0 -#define NPCX_SPI_CTL1_SNM 1 -#define NPCX_SPI_CTL1_MOD 2 -#define NPCX_SPI_CTL1_EIR 5 -#define NPCX_SPI_CTL1_EIW 6 -#define NPCX_SPI_CTL1_SCM 7 -#define NPCX_SPI_CTL1_SCIDL 8 -#define NPCX_SPI_CTL1_SCDV 9 -#define NPCX_SPI_STAT_BSY 0 -#define NPCX_SPI_STAT_RBF 1 +#define NPCX_SPI_CTL1_SPIEN 0 +#define NPCX_SPI_CTL1_SNM 1 +#define NPCX_SPI_CTL1_MOD 2 +#define NPCX_SPI_CTL1_EIR 5 +#define NPCX_SPI_CTL1_EIW 6 +#define NPCX_SPI_CTL1_SCM 7 +#define NPCX_SPI_CTL1_SCIDL 8 +#define NPCX_SPI_CTL1_SCDV 9 +#define NPCX_SPI_STAT_BSY 0 +#define NPCX_SPI_STAT_RBF 1 /******************************************************************************/ /* PECI Registers */ -#define NPCX_PECI_CTL_STS REG8(NPCX_PECI_BASE_ADDR + 0x000) -#define NPCX_PECI_RD_LENGTH REG8(NPCX_PECI_BASE_ADDR + 0x001) -#define NPCX_PECI_ADDR REG8(NPCX_PECI_BASE_ADDR + 0x002) -#define NPCX_PECI_CMD REG8(NPCX_PECI_BASE_ADDR + 0x003) -#define NPCX_PECI_CTL2 REG8(NPCX_PECI_BASE_ADDR + 0x004) -#define NPCX_PECI_INDEX REG8(NPCX_PECI_BASE_ADDR + 0x005) -#define NPCX_PECI_IDATA REG8(NPCX_PECI_BASE_ADDR + 0x006) -#define NPCX_PECI_WR_LENGTH REG8(NPCX_PECI_BASE_ADDR + 0x007) -#define NPCX_PECI_CFG REG8(NPCX_PECI_BASE_ADDR + 0x009) -#define NPCX_PECI_RATE REG8(NPCX_PECI_BASE_ADDR + 0x00F) -#define NPCX_PECI_DATA_IN(i) REG8(NPCX_PECI_BASE_ADDR + 0x010 + (i)) -#define NPCX_PECI_DATA_OUT(i) REG8(NPCX_PECI_BASE_ADDR + 0x010 + (i)) +#define NPCX_PECI_CTL_STS REG8(NPCX_PECI_BASE_ADDR + 0x000) +#define NPCX_PECI_RD_LENGTH REG8(NPCX_PECI_BASE_ADDR + 0x001) +#define NPCX_PECI_ADDR REG8(NPCX_PECI_BASE_ADDR + 0x002) +#define NPCX_PECI_CMD REG8(NPCX_PECI_BASE_ADDR + 0x003) +#define NPCX_PECI_CTL2 REG8(NPCX_PECI_BASE_ADDR + 0x004) +#define NPCX_PECI_INDEX REG8(NPCX_PECI_BASE_ADDR + 0x005) +#define NPCX_PECI_IDATA REG8(NPCX_PECI_BASE_ADDR + 0x006) +#define NPCX_PECI_WR_LENGTH REG8(NPCX_PECI_BASE_ADDR + 0x007) +#define NPCX_PECI_CFG REG8(NPCX_PECI_BASE_ADDR + 0x009) +#define NPCX_PECI_RATE REG8(NPCX_PECI_BASE_ADDR + 0x00F) +#define NPCX_PECI_DATA_IN(i) REG8(NPCX_PECI_BASE_ADDR + 0x010 + (i)) +#define NPCX_PECI_DATA_OUT(i) REG8(NPCX_PECI_BASE_ADDR + 0x010 + (i)) /* PECI register fields */ -#define NPCX_PECI_CTL_STS_START_BUSY 0 -#define NPCX_PECI_CTL_STS_DONE 1 -#define NPCX_PECI_CTL_STS_AVL_ERR 2 -#define NPCX_PECI_CTL_STS_CRC_ERR 3 -#define NPCX_PECI_CTL_STS_ABRT_ERR 4 -#define NPCX_PECI_CTL_STS_AWFCS_EN 5 -#define NPCX_PECI_CTL_STS_DONE_EN 6 -#define NPCX_ESTRPST_PECIST 0 -#define SFT_STRP_CFG_CK50 5 +#define NPCX_PECI_CTL_STS_START_BUSY 0 +#define NPCX_PECI_CTL_STS_DONE 1 +#define NPCX_PECI_CTL_STS_AVL_ERR 2 +#define NPCX_PECI_CTL_STS_CRC_ERR 3 +#define NPCX_PECI_CTL_STS_ABRT_ERR 4 +#define NPCX_PECI_CTL_STS_AWFCS_EN 5 +#define NPCX_PECI_CTL_STS_DONE_EN 6 +#define NPCX_ESTRPST_PECIST 0 +#define SFT_STRP_CFG_CK50 5 /******************************************************************************/ /* PWM Registers */ -#define NPCX_PRSC(n) REG16(NPCX_PWM_BASE_ADDR(n) + 0x000) -#define NPCX_CTR(n) REG16(NPCX_PWM_BASE_ADDR(n) + 0x002) -#define NPCX_PWMCTL(n) REG8(NPCX_PWM_BASE_ADDR(n) + 0x004) -#define NPCX_DCR(n) REG16(NPCX_PWM_BASE_ADDR(n) + 0x006) -#define NPCX_PWMCTLEX(n) REG8(NPCX_PWM_BASE_ADDR(n) + 0x00C) +#define NPCX_PRSC(n) REG16(NPCX_PWM_BASE_ADDR(n) + 0x000) +#define NPCX_CTR(n) REG16(NPCX_PWM_BASE_ADDR(n) + 0x002) +#define NPCX_PWMCTL(n) REG8(NPCX_PWM_BASE_ADDR(n) + 0x004) +#define NPCX_DCR(n) REG16(NPCX_PWM_BASE_ADDR(n) + 0x006) +#define NPCX_PWMCTLEX(n) REG8(NPCX_PWM_BASE_ADDR(n) + 0x00C) /* PWM register fields */ -#define NPCX_PWMCTL_INVP 0 -#define NPCX_PWMCTL_CKSEL 1 -#define NPCX_PWMCTL_HB_DC_CTL_FIELD FIELD(2, 2) -#define NPCX_PWMCTL_PWR 7 -#define NPCX_PWMCTLEX_FCK_SEL_FIELD FIELD(4, 2) -#define NPCX_PWMCTLEX_OD_OUT 7 +#define NPCX_PWMCTL_INVP 0 +#define NPCX_PWMCTL_CKSEL 1 +#define NPCX_PWMCTL_HB_DC_CTL_FIELD FIELD(2, 2) +#define NPCX_PWMCTL_PWR 7 +#define NPCX_PWMCTLEX_FCK_SEL_FIELD FIELD(4, 2) +#define NPCX_PWMCTLEX_OD_OUT 7 /******************************************************************************/ /* MFT Registers */ -#define NPCX_TCNT1(n) REG16(NPCX_MFT_BASE_ADDR(n) + 0x000) -#define NPCX_TCRA(n) REG16(NPCX_MFT_BASE_ADDR(n) + 0x002) -#define NPCX_TCRB(n) REG16(NPCX_MFT_BASE_ADDR(n) + 0x004) -#define NPCX_TCNT2(n) REG16(NPCX_MFT_BASE_ADDR(n) + 0x006) -#define NPCX_TPRSC(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x008) -#define NPCX_TCKC(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x00A) -#define NPCX_TMCTRL(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x00C) -#define NPCX_TECTRL(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x00E) -#define NPCX_TECLR(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x010) -#define NPCX_TIEN(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x012) -#define NPCX_TWUEN(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x01A) -#define NPCX_TCFG(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x01C) +#define NPCX_TCNT1(n) REG16(NPCX_MFT_BASE_ADDR(n) + 0x000) +#define NPCX_TCRA(n) REG16(NPCX_MFT_BASE_ADDR(n) + 0x002) +#define NPCX_TCRB(n) REG16(NPCX_MFT_BASE_ADDR(n) + 0x004) +#define NPCX_TCNT2(n) REG16(NPCX_MFT_BASE_ADDR(n) + 0x006) +#define NPCX_TPRSC(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x008) +#define NPCX_TCKC(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x00A) +#define NPCX_TMCTRL(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x00C) +#define NPCX_TECTRL(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x00E) +#define NPCX_TECLR(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x010) +#define NPCX_TIEN(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x012) +#define NPCX_TWUEN(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x01A) +#define NPCX_TCFG(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x01C) /* MFT register fields */ -#define NPCX_TMCTRL_MDSEL_FIELD FIELD(0, 3) -#define NPCX_TCKC_LOW_PWR 7 -#define NPCX_TCKC_PLS_ACC_CLK 6 -#define NPCX_TCKC_C1CSEL_FIELD FIELD(0, 3) -#define NPCX_TCKC_C2CSEL_FIELD FIELD(3, 3) -#define NPCX_TMCTRL_TAEN 5 -#define NPCX_TMCTRL_TBEN 6 -#define NPCX_TMCTRL_TAEDG 3 -#define NPCX_TMCTRL_TBEDG 4 -#define NPCX_TCFG_TADBEN 6 -#define NPCX_TCFG_TBDBEN 7 -#define NPCX_TECTRL_TAPND 0 -#define NPCX_TECTRL_TBPND 1 -#define NPCX_TECTRL_TCPND 2 -#define NPCX_TECTRL_TDPND 3 -#define NPCX_TECLR_TACLR 0 -#define NPCX_TECLR_TBCLR 1 -#define NPCX_TECLR_TCCLR 2 -#define NPCX_TECLR_TDCLR 3 -#define NPCX_TIEN_TAIEN 0 -#define NPCX_TIEN_TBIEN 1 -#define NPCX_TIEN_TCIEN 2 -#define NPCX_TIEN_TDIEN 3 -#define NPCX_TWUEN_TAWEN 0 -#define NPCX_TWUEN_TBWEN 1 -#define NPCX_TWUEN_TCWEN 2 -#define NPCX_TWUEN_TDWEN 3 +#define NPCX_TMCTRL_MDSEL_FIELD FIELD(0, 3) +#define NPCX_TCKC_LOW_PWR 7 +#define NPCX_TCKC_PLS_ACC_CLK 6 +#define NPCX_TCKC_C1CSEL_FIELD FIELD(0, 3) +#define NPCX_TCKC_C2CSEL_FIELD FIELD(3, 3) +#define NPCX_TMCTRL_TAEN 5 +#define NPCX_TMCTRL_TBEN 6 +#define NPCX_TMCTRL_TAEDG 3 +#define NPCX_TMCTRL_TBEDG 4 +#define NPCX_TCFG_TADBEN 6 +#define NPCX_TCFG_TBDBEN 7 +#define NPCX_TECTRL_TAPND 0 +#define NPCX_TECTRL_TBPND 1 +#define NPCX_TECTRL_TCPND 2 +#define NPCX_TECTRL_TDPND 3 +#define NPCX_TECLR_TACLR 0 +#define NPCX_TECLR_TBCLR 1 +#define NPCX_TECLR_TCCLR 2 +#define NPCX_TECLR_TDCLR 3 +#define NPCX_TIEN_TAIEN 0 +#define NPCX_TIEN_TBIEN 1 +#define NPCX_TIEN_TCIEN 2 +#define NPCX_TIEN_TDIEN 3 +#define NPCX_TWUEN_TAWEN 0 +#define NPCX_TWUEN_TBWEN 1 +#define NPCX_TWUEN_TCWEN 2 +#define NPCX_TWUEN_TDWEN 3 /******************************************************************************/ /* ITIM16/32 Define */ -#define ITIM_INT(module) CONCAT2(NPCX_IRQ_, module) +#define ITIM_INT(module) CONCAT2(NPCX_IRQ_, module) /* ITIM16/32 register */ -#define NPCX_ITPRE(n) REG8(NPCX_ITIM_BASE_ADDR(n) + 0x001) -#define NPCX_ITCTS(n) REG8(NPCX_ITIM_BASE_ADDR(n) + 0x004) +#define NPCX_ITPRE(n) REG8(NPCX_ITIM_BASE_ADDR(n) + 0x001) +#define NPCX_ITCTS(n) REG8(NPCX_ITIM_BASE_ADDR(n) + 0x004) /* ITIM16 register fields */ -#define NPCX_ITCTS_TO_STS 0 -#define NPCX_ITCTS_TO_IE 2 -#define NPCX_ITCTS_TO_WUE 3 -#define NPCX_ITCTS_CKSEL 4 -#define NPCX_ITCTS_ITEN 7 +#define NPCX_ITCTS_TO_STS 0 +#define NPCX_ITCTS_TO_IE 2 +#define NPCX_ITCTS_TO_WUE 3 +#define NPCX_ITCTS_CKSEL 4 +#define NPCX_ITCTS_ITEN 7 /******************************************************************************/ /* Serial Host Interface (SHI) Registers */ -#define NPCX_SHICFG1 REG8(NPCX_SHI_BASE_ADDR + 0x001) -#define NPCX_SHICFG2 REG8(NPCX_SHI_BASE_ADDR + 0x002) -#define NPCX_I2CADDR1 REG8(NPCX_SHI_BASE_ADDR + 0x003) -#define NPCX_I2CADDR2 REG8(NPCX_SHI_BASE_ADDR + 0x004) -#define NPCX_EVENABLE REG8(NPCX_SHI_BASE_ADDR + 0x005) -#define NPCX_EVSTAT REG8(NPCX_SHI_BASE_ADDR + 0x006) -#define NPCX_SHI_CAPABILITY REG8(NPCX_SHI_BASE_ADDR + 0x007) -#define NPCX_STATUS REG8(NPCX_SHI_BASE_ADDR + 0x008) -#define NPCX_IBUFSTAT REG8(NPCX_SHI_BASE_ADDR + 0x00A) -#define NPCX_OBUFSTAT REG8(NPCX_SHI_BASE_ADDR + 0x00B) +#define NPCX_SHICFG1 REG8(NPCX_SHI_BASE_ADDR + 0x001) +#define NPCX_SHICFG2 REG8(NPCX_SHI_BASE_ADDR + 0x002) +#define NPCX_I2CADDR1 REG8(NPCX_SHI_BASE_ADDR + 0x003) +#define NPCX_I2CADDR2 REG8(NPCX_SHI_BASE_ADDR + 0x004) +#define NPCX_EVENABLE REG8(NPCX_SHI_BASE_ADDR + 0x005) +#define NPCX_EVSTAT REG8(NPCX_SHI_BASE_ADDR + 0x006) +#define NPCX_SHI_CAPABILITY REG8(NPCX_SHI_BASE_ADDR + 0x007) +#define NPCX_STATUS REG8(NPCX_SHI_BASE_ADDR + 0x008) +#define NPCX_IBUFSTAT REG8(NPCX_SHI_BASE_ADDR + 0x00A) +#define NPCX_OBUFSTAT REG8(NPCX_SHI_BASE_ADDR + 0x00B) /* SHI register fields */ -#define NPCX_SHICFG1_EN 0 -#define NPCX_SHICFG1_MODE 1 -#define NPCX_SHICFG1_WEN 2 -#define NPCX_SHICFG1_AUTIBF 3 -#define NPCX_SHICFG1_AUTOBE 4 -#define NPCX_SHICFG1_DAS 5 -#define NPCX_SHICFG1_CPOL 6 -#define NPCX_SHICFG1_IWRAP 7 -#define NPCX_SHICFG2_SIMUL 0 -#define NPCX_SHICFG2_BUSY 1 -#define NPCX_SHICFG2_ONESHOT 2 -#define NPCX_SHICFG2_SLWU 3 -#define NPCX_SHICFG2_REEN 4 -#define NPCX_SHICFG2_RESTART 5 -#define NPCX_SHICFG2_REEVEN 6 -#define NPCX_EVENABLE_OBEEN 0 -#define NPCX_EVENABLE_OBHEEN 1 -#define NPCX_EVENABLE_IBFEN 2 -#define NPCX_EVENABLE_IBHFEN 3 -#define NPCX_EVENABLE_EOREN 4 -#define NPCX_EVENABLE_EOWEN 5 -#define NPCX_EVENABLE_STSREN 6 -#define NPCX_EVENABLE_IBOREN 7 -#define NPCX_EVSTAT_OBE 0 -#define NPCX_EVSTAT_OBHE 1 -#define NPCX_EVSTAT_IBF 2 -#define NPCX_EVSTAT_IBHF 3 -#define NPCX_EVSTAT_EOR 4 -#define NPCX_EVSTAT_EOW 5 -#define NPCX_EVSTAT_STSR 6 -#define NPCX_EVSTAT_IBOR 7 -#define NPCX_STATUS_OBES 6 -#define NPCX_STATUS_IBFS 7 +#define NPCX_SHICFG1_EN 0 +#define NPCX_SHICFG1_MODE 1 +#define NPCX_SHICFG1_WEN 2 +#define NPCX_SHICFG1_AUTIBF 3 +#define NPCX_SHICFG1_AUTOBE 4 +#define NPCX_SHICFG1_DAS 5 +#define NPCX_SHICFG1_CPOL 6 +#define NPCX_SHICFG1_IWRAP 7 +#define NPCX_SHICFG2_SIMUL 0 +#define NPCX_SHICFG2_BUSY 1 +#define NPCX_SHICFG2_ONESHOT 2 +#define NPCX_SHICFG2_SLWU 3 +#define NPCX_SHICFG2_REEN 4 +#define NPCX_SHICFG2_RESTART 5 +#define NPCX_SHICFG2_REEVEN 6 +#define NPCX_EVENABLE_OBEEN 0 +#define NPCX_EVENABLE_OBHEEN 1 +#define NPCX_EVENABLE_IBFEN 2 +#define NPCX_EVENABLE_IBHFEN 3 +#define NPCX_EVENABLE_EOREN 4 +#define NPCX_EVENABLE_EOWEN 5 +#define NPCX_EVENABLE_STSREN 6 +#define NPCX_EVENABLE_IBOREN 7 +#define NPCX_EVSTAT_OBE 0 +#define NPCX_EVSTAT_OBHE 1 +#define NPCX_EVSTAT_IBF 2 +#define NPCX_EVSTAT_IBHF 3 +#define NPCX_EVSTAT_EOR 4 +#define NPCX_EVSTAT_EOW 5 +#define NPCX_EVSTAT_STSR 6 +#define NPCX_EVSTAT_IBOR 7 +#define NPCX_STATUS_OBES 6 +#define NPCX_STATUS_IBFS 7 /******************************************************************************/ /* Monotonic Counter (MTC) Registers */ -#define NPCX_TTC REG32(NPCX_MTC_BASE_ADDR + 0x000) -#define NPCX_WTC REG32(NPCX_MTC_BASE_ADDR + 0x004) -#define NPCX_MTCTST REG8(NPCX_MTC_BASE_ADDR + 0x008) -#define NPCX_MTCVER REG8(NPCX_MTC_BASE_ADDR + 0x00C) +#define NPCX_TTC REG32(NPCX_MTC_BASE_ADDR + 0x000) +#define NPCX_WTC REG32(NPCX_MTC_BASE_ADDR + 0x004) +#define NPCX_MTCTST REG8(NPCX_MTC_BASE_ADDR + 0x008) +#define NPCX_MTCVER REG8(NPCX_MTC_BASE_ADDR + 0x00C) /* MTC register fields */ -#define NPCX_WTC_PTO 30 -#define NPCX_WTC_WIE 31 +#define NPCX_WTC_PTO 30 +#define NPCX_WTC_WIE 31 /******************************************************************************/ /* Low Power RAM definitions */ -#define NPCX_LPRAM_CTRL REG32(0x40001044) +#define NPCX_LPRAM_CTRL REG32(0x40001044) /******************************************************************************/ /* eSPI Registers */ -#define NPCX_ESPIID REG32(NPCX_ESPI_BASE_ADDR + 0X00) -#define NPCX_ESPICFG REG32(NPCX_ESPI_BASE_ADDR + 0X04) -#define NPCX_ESPISTS REG32(NPCX_ESPI_BASE_ADDR + 0X08) -#define NPCX_ESPIIE REG32(NPCX_ESPI_BASE_ADDR + 0X0C) -#define NPCX_ESPIWE REG32(NPCX_ESPI_BASE_ADDR + 0X10) -#define NPCX_VWREGIDX REG32(NPCX_ESPI_BASE_ADDR + 0X14) -#define NPCX_VWREGDATA REG32(NPCX_ESPI_BASE_ADDR + 0X18) -#define NPCX_OOBCTL REG32(NPCX_ESPI_BASE_ADDR + 0X24) -#define NPCX_FLASHRXRDHEAD REG32(NPCX_ESPI_BASE_ADDR + 0X28) -#define NPCX_FLASHTXWRHEAD REG32(NPCX_ESPI_BASE_ADDR + 0X2C) -#define NPCX_FLASHCFG REG32(NPCX_ESPI_BASE_ADDR + 0X34) -#define NPCX_FLASHCTL REG32(NPCX_ESPI_BASE_ADDR + 0X38) -#define NPCX_ESPIERR REG32(NPCX_ESPI_BASE_ADDR + 0X3C) - -#define NPCX_ONLY_ESPI_REG1 REG8(NPCX_ESPI_BASE_ADDR + 0XF0) -#define NPCX_ONLY_ESPI_REG2 REG8(NPCX_ESPI_BASE_ADDR + 0XF1) - -#define NPCX_ONLY_ESPI_REG1_UNLOCK_REG2 0x55 -#define NPCX_ONLY_ESPI_REG1_LOCK_REG2 0 -#define NPCX_ONLY_ESPI_REG2_TRANS_END_CONFIG 4 +#define NPCX_ESPIID REG32(NPCX_ESPI_BASE_ADDR + 0X00) +#define NPCX_ESPICFG REG32(NPCX_ESPI_BASE_ADDR + 0X04) +#define NPCX_ESPISTS REG32(NPCX_ESPI_BASE_ADDR + 0X08) +#define NPCX_ESPIIE REG32(NPCX_ESPI_BASE_ADDR + 0X0C) +#define NPCX_ESPIWE REG32(NPCX_ESPI_BASE_ADDR + 0X10) +#define NPCX_VWREGIDX REG32(NPCX_ESPI_BASE_ADDR + 0X14) +#define NPCX_VWREGDATA REG32(NPCX_ESPI_BASE_ADDR + 0X18) +#define NPCX_OOBCTL REG32(NPCX_ESPI_BASE_ADDR + 0X24) +#define NPCX_FLASHRXRDHEAD REG32(NPCX_ESPI_BASE_ADDR + 0X28) +#define NPCX_FLASHTXWRHEAD REG32(NPCX_ESPI_BASE_ADDR + 0X2C) +#define NPCX_FLASHCFG REG32(NPCX_ESPI_BASE_ADDR + 0X34) +#define NPCX_FLASHCTL REG32(NPCX_ESPI_BASE_ADDR + 0X38) +#define NPCX_ESPIERR REG32(NPCX_ESPI_BASE_ADDR + 0X3C) + +#define NPCX_ONLY_ESPI_REG1 REG8(NPCX_ESPI_BASE_ADDR + 0XF0) +#define NPCX_ONLY_ESPI_REG2 REG8(NPCX_ESPI_BASE_ADDR + 0XF1) + +#define NPCX_ONLY_ESPI_REG1_UNLOCK_REG2 0x55 +#define NPCX_ONLY_ESPI_REG1_LOCK_REG2 0 +#define NPCX_ONLY_ESPI_REG2_TRANS_END_CONFIG 4 /* eSPI Virtual Wire channel registers */ -#define NPCX_VWEVSM(n) REG32(NPCX_ESPI_BASE_ADDR + 0x100 + (4*(n))) -#define NPCX_VWEVMS(n) REG32(NPCX_ESPI_BASE_ADDR + 0x140 + (4*(n))) -#define NPCX_VWCTL REG32(NPCX_ESPI_BASE_ADDR + 0x2FC) +#define NPCX_VWEVSM(n) REG32(NPCX_ESPI_BASE_ADDR + 0x100 + (4 * (n))) +#define NPCX_VWEVMS(n) REG32(NPCX_ESPI_BASE_ADDR + 0x140 + (4 * (n))) +#define NPCX_VWCTL REG32(NPCX_ESPI_BASE_ADDR + 0x2FC) /* eSPI register fields */ -#define NPCX_ESPICFG_PCHANEN 0 -#define NPCX_ESPICFG_VWCHANEN 1 -#define NPCX_ESPICFG_OOBCHANEN 2 -#define NPCX_ESPICFG_FLASHCHANEN 3 -#define NPCX_ESPICFG_HPCHANEN 4 -#define NPCX_ESPICFG_HVWCHANEN 5 -#define NPCX_ESPICFG_HOOBCHANEN 6 -#define NPCX_ESPICFG_HFLASHCHANEN 7 -#define NPCX_ESPICFG_IOMODE_FIELD FIELD(8, 2) -#define NPCX_ESPICFG_MAXFREQ_FIELD FIELD(10, 3) -#define NPCX_ESPICFG_OPFREQ_FIELD FIELD(17, 3) -#define NPCX_ESPICFG_IOMODESEL_FIELD FIELD(20, 2) -#define NPCX_ESPICFG_ALERT_MODE 22 -#define NPCX_ESPICFG_CRC_CHK 23 -#define NPCX_ESPICFG_PCCHN_SUPP 24 -#define NPCX_ESPICFG_VWCHN_SUPP 25 -#define NPCX_ESPICFG_OOBCHN_SUPP 26 -#define NPCX_ESPICFG_FLASHCHN_SUPP 27 -#define NPCX_ESPIERR_INVCMD 0 /* Invalid Command Type */ -#define NPCX_ESPIERR_INVCYC 1 /* Invalid Cycle Type */ -#define NPCX_ESPIERR_CRCERR 2 /* Transaction CRC Error */ -#define NPCX_ESPIERR_ABCOMP 3 /* Abnormal Completion */ -#define NPCX_ESPIERR_PROTERR 4 /* Protocol Error */ -#define NPCX_ESPIERR_BADSIZE 5 /* Bad Size */ -#define NPCX_ESPIERR_NPBADALN 6 /* NPPC Bad Address Alignment */ -#define NPCX_ESPIERR_PCBADALN 7 /* PPC Bad Address Alignment */ -#define NPCX_ESPIERR_UNCMD 9 /* Unsupported Command */ -#define NPCX_ESPIERR_EXTRACYC 10 /* Extra eSPI Clock Cycles */ -#define NPCX_ESPIERR_VWERR 11 /* Virtual Channel Access Error */ -#define NPCX_ESPIERR_UNPBM 14 /* Unsuccessful Bus Completion */ -#define NPCX_ESPIERR_UNFLASH 15 /* Unsuccessful Flash Completion */ -#define NPCX_ESPIIE_IBRSTIE 0 -#define NPCX_ESPIIE_CFGUPDIE 1 -#define NPCX_ESPIIE_BERRIE 2 -#define NPCX_ESPIIE_OOBRXIE 3 -#define NPCX_ESPIIE_FLASHRXIE 4 -#define NPCX_ESPIIE_SFLASHRDIE 5 -#define NPCX_ESPIIE_PERACCIE 6 -#define NPCX_ESPIIE_DFRDIE 7 -#define NPCX_ESPIIE_VWUPDIE 8 -#define NPCX_ESPIIE_ESPIRSTIE 9 -#define NPCX_ESPIIE_PLTRSTIE 10 -#define NPCX_ESPIIE_AMERRIE 15 -#define NPCX_ESPIIE_AMDONEIE 16 -#define NPCX_ESPIWE_IBRSTWE 0 -#define NPCX_ESPIWE_CFGUPDWE 1 -#define NPCX_ESPIWE_BERRWE 2 -#define NPCX_ESPIWE_OOBRXWE 3 -#define NPCX_ESPIWE_FLASHRXWE 4 -#define NPCX_ESPIWE_PERACCWE 6 -#define NPCX_ESPIWE_DFRDWE 7 -#define NPCX_ESPIWE_VWUPDWE 8 -#define NPCX_ESPIWE_ESPIRSTWE 9 -#define NPCX_ESPISTS_IBRST 0 -#define NPCX_ESPISTS_CFGUPD 1 -#define NPCX_ESPISTS_BERR 2 -#define NPCX_ESPISTS_OOBRX 3 -#define NPCX_ESPISTS_FLASHRX 4 -#define NPCX_ESPISTS_SFLASHRD 5 -#define NPCX_ESPISTS_PERACC 6 -#define NPCX_ESPISTS_DFRD 7 -#define NPCX_ESPISTS_VWUPD 8 -#define NPCX_ESPISTS_ESPIRST 9 -#define NPCX_ESPISTS_PLTRST 10 -#define NPCX_ESPISTS_AMERR 15 -#define NPCX_ESPISTS_AMDONE 16 +#define NPCX_ESPICFG_PCHANEN 0 +#define NPCX_ESPICFG_VWCHANEN 1 +#define NPCX_ESPICFG_OOBCHANEN 2 +#define NPCX_ESPICFG_FLASHCHANEN 3 +#define NPCX_ESPICFG_HPCHANEN 4 +#define NPCX_ESPICFG_HVWCHANEN 5 +#define NPCX_ESPICFG_HOOBCHANEN 6 +#define NPCX_ESPICFG_HFLASHCHANEN 7 +#define NPCX_ESPICFG_IOMODE_FIELD FIELD(8, 2) +#define NPCX_ESPICFG_MAXFREQ_FIELD FIELD(10, 3) +#define NPCX_ESPICFG_OPFREQ_FIELD FIELD(17, 3) +#define NPCX_ESPICFG_IOMODESEL_FIELD FIELD(20, 2) +#define NPCX_ESPICFG_ALERT_MODE 22 +#define NPCX_ESPICFG_CRC_CHK 23 +#define NPCX_ESPICFG_PCCHN_SUPP 24 +#define NPCX_ESPICFG_VWCHN_SUPP 25 +#define NPCX_ESPICFG_OOBCHN_SUPP 26 +#define NPCX_ESPICFG_FLASHCHN_SUPP 27 +#define NPCX_ESPIERR_INVCMD 0 /* Invalid Command Type */ +#define NPCX_ESPIERR_INVCYC 1 /* Invalid Cycle Type */ +#define NPCX_ESPIERR_CRCERR 2 /* Transaction CRC Error */ +#define NPCX_ESPIERR_ABCOMP 3 /* Abnormal Completion */ +#define NPCX_ESPIERR_PROTERR 4 /* Protocol Error */ +#define NPCX_ESPIERR_BADSIZE 5 /* Bad Size */ +#define NPCX_ESPIERR_NPBADALN 6 /* NPPC Bad Address Alignment */ +#define NPCX_ESPIERR_PCBADALN 7 /* PPC Bad Address Alignment */ +#define NPCX_ESPIERR_UNCMD 9 /* Unsupported Command */ +#define NPCX_ESPIERR_EXTRACYC 10 /* Extra eSPI Clock Cycles */ +#define NPCX_ESPIERR_VWERR 11 /* Virtual Channel Access Error */ +#define NPCX_ESPIERR_UNPBM 14 /* Unsuccessful Bus Completion */ +#define NPCX_ESPIERR_UNFLASH 15 /* Unsuccessful Flash Completion */ +#define NPCX_ESPIIE_IBRSTIE 0 +#define NPCX_ESPIIE_CFGUPDIE 1 +#define NPCX_ESPIIE_BERRIE 2 +#define NPCX_ESPIIE_OOBRXIE 3 +#define NPCX_ESPIIE_FLASHRXIE 4 +#define NPCX_ESPIIE_SFLASHRDIE 5 +#define NPCX_ESPIIE_PERACCIE 6 +#define NPCX_ESPIIE_DFRDIE 7 +#define NPCX_ESPIIE_VWUPDIE 8 +#define NPCX_ESPIIE_ESPIRSTIE 9 +#define NPCX_ESPIIE_PLTRSTIE 10 +#define NPCX_ESPIIE_AMERRIE 15 +#define NPCX_ESPIIE_AMDONEIE 16 +#define NPCX_ESPIWE_IBRSTWE 0 +#define NPCX_ESPIWE_CFGUPDWE 1 +#define NPCX_ESPIWE_BERRWE 2 +#define NPCX_ESPIWE_OOBRXWE 3 +#define NPCX_ESPIWE_FLASHRXWE 4 +#define NPCX_ESPIWE_PERACCWE 6 +#define NPCX_ESPIWE_DFRDWE 7 +#define NPCX_ESPIWE_VWUPDWE 8 +#define NPCX_ESPIWE_ESPIRSTWE 9 +#define NPCX_ESPISTS_IBRST 0 +#define NPCX_ESPISTS_CFGUPD 1 +#define NPCX_ESPISTS_BERR 2 +#define NPCX_ESPISTS_OOBRX 3 +#define NPCX_ESPISTS_FLASHRX 4 +#define NPCX_ESPISTS_SFLASHRD 5 +#define NPCX_ESPISTS_PERACC 6 +#define NPCX_ESPISTS_DFRD 7 +#define NPCX_ESPISTS_VWUPD 8 +#define NPCX_ESPISTS_ESPIRST 9 +#define NPCX_ESPISTS_PLTRST 10 +#define NPCX_ESPISTS_AMERR 15 +#define NPCX_ESPISTS_AMDONE 16 /* eSPI Virtual Wire channel register fields */ -#define NPCX_VWEVSM_WIRE FIELD(0, 4) -#define NPCX_VWEVMS_WIRE FIELD(0, 4) -#define NPCX_VWEVSM_VALID FIELD(4, 4) -#define NPCX_VWEVMS_VALID FIELD(4, 4) +#define NPCX_VWEVSM_WIRE FIELD(0, 4) +#define NPCX_VWEVMS_WIRE FIELD(0, 4) +#define NPCX_VWEVSM_VALID FIELD(4, 4) +#define NPCX_VWEVMS_VALID FIELD(4, 4) /* Macro functions for eSPI CFG & IE */ -#define IS_PERIPHERAL_CHAN_ENABLE(ch) IS_BIT_SET(NPCX_ESPICFG, ch) -#define IS_HOST_CHAN_EN(ch) IS_BIT_SET(NPCX_ESPICFG, (ch+4)) -#define ENABLE_ESPI_CHAN(ch) SET_BIT(NPCX_ESPICFG, ch) -#define DISABLE_ESPI_CHAN(ch) CLEAR_BIT(NPCX_ESPICFG, ch) +#define IS_PERIPHERAL_CHAN_ENABLE(ch) IS_BIT_SET(NPCX_ESPICFG, ch) +#define IS_HOST_CHAN_EN(ch) IS_BIT_SET(NPCX_ESPICFG, (ch + 4)) +#define ENABLE_ESPI_CHAN(ch) SET_BIT(NPCX_ESPICFG, ch) +#define DISABLE_ESPI_CHAN(ch) CLEAR_BIT(NPCX_ESPICFG, ch) /* ESPI Peripheral Channel Support Definitions */ -#define ESPI_SUPP_CH_PC BIT(NPCX_ESPICFG_PCCHN_SUPP) -#define ESPI_SUPP_CH_VM BIT(NPCX_ESPICFG_VWCHN_SUPP) -#define ESPI_SUPP_CH_OOB BIT(NPCX_ESPICFG_OOBCHN_SUPP) -#define ESPI_SUPP_CH_FLASH BIT(NPCX_ESPICFG_FLASHCHN_SUPP) -#define ESPI_SUPP_CH_ALL (ESPI_SUPP_CH_PC | ESPI_SUPP_CH_VM | \ - ESPI_SUPP_CH_OOB | ESPI_SUPP_CH_FLASH) +#define ESPI_SUPP_CH_PC BIT(NPCX_ESPICFG_PCCHN_SUPP) +#define ESPI_SUPP_CH_VM BIT(NPCX_ESPICFG_VWCHN_SUPP) +#define ESPI_SUPP_CH_OOB BIT(NPCX_ESPICFG_OOBCHN_SUPP) +#define ESPI_SUPP_CH_FLASH BIT(NPCX_ESPICFG_FLASHCHN_SUPP) +#define ESPI_SUPP_CH_ALL \ + (ESPI_SUPP_CH_PC | ESPI_SUPP_CH_VM | ESPI_SUPP_CH_OOB | \ + ESPI_SUPP_CH_FLASH) /* ESPI Interrupts Enable Definitions */ -#define ESPIIE_IBRST BIT(NPCX_ESPIIE_IBRSTIE) -#define ESPIIE_CFGUPD BIT(NPCX_ESPIIE_CFGUPDIE) -#define ESPIIE_BERR BIT(NPCX_ESPIIE_BERRIE) -#define ESPIIE_OOBRX BIT(NPCX_ESPIIE_OOBRXIE) -#define ESPIIE_FLASHRX BIT(NPCX_ESPIIE_FLASHRXIE) -#define ESPIIE_SFLASHRD BIT(NPCX_ESPIIE_SFLASHRDIE) -#define ESPIIE_PERACC BIT(NPCX_ESPIIE_PERACCIE) -#define ESPIIE_DFRD BIT(NPCX_ESPIIE_DFRDIE) -#define ESPIIE_VWUPD BIT(NPCX_ESPIIE_VWUPDIE) -#define ESPIIE_ESPIRST BIT(NPCX_ESPIIE_ESPIRSTIE) -#define ESPIIE_PLTRST BIT(NPCX_ESPIIE_PLTRSTIE) -#define ESPIIE_AMERR BIT(NPCX_ESPIIE_AMERRIE) -#define ESPIIE_AMDONE BIT(NPCX_ESPIIE_AMDONEIE) +#define ESPIIE_IBRST BIT(NPCX_ESPIIE_IBRSTIE) +#define ESPIIE_CFGUPD BIT(NPCX_ESPIIE_CFGUPDIE) +#define ESPIIE_BERR BIT(NPCX_ESPIIE_BERRIE) +#define ESPIIE_OOBRX BIT(NPCX_ESPIIE_OOBRXIE) +#define ESPIIE_FLASHRX BIT(NPCX_ESPIIE_FLASHRXIE) +#define ESPIIE_SFLASHRD BIT(NPCX_ESPIIE_SFLASHRDIE) +#define ESPIIE_PERACC BIT(NPCX_ESPIIE_PERACCIE) +#define ESPIIE_DFRD BIT(NPCX_ESPIIE_DFRDIE) +#define ESPIIE_VWUPD BIT(NPCX_ESPIIE_VWUPDIE) +#define ESPIIE_ESPIRST BIT(NPCX_ESPIIE_ESPIRSTIE) +#define ESPIIE_PLTRST BIT(NPCX_ESPIIE_PLTRSTIE) +#define ESPIIE_AMERR BIT(NPCX_ESPIIE_AMERRIE) +#define ESPIIE_AMDONE BIT(NPCX_ESPIIE_AMDONEIE) /* eSPI Interrupts for VW */ -#define ESPIIE_VW (ESPIIE_VWUPD | ESPIIE_PLTRST) +#define ESPIIE_VW (ESPIIE_VWUPD | ESPIIE_PLTRST) /* eSPI Interrupts for Generic */ -#define ESPIIE_GENERIC (ESPIIE_IBRST | ESPIIE_CFGUPD | \ - ESPIIE_BERR | ESPIIE_ESPIRST) +#define ESPIIE_GENERIC \ + (ESPIIE_IBRST | ESPIIE_CFGUPD | ESPIIE_BERR | ESPIIE_ESPIRST) /* ESPI Wake-up Enable Definitions */ -#define ESPIWE_IBRST BIT(NPCX_ESPIWE_IBRSTWE) -#define ESPIWE_CFGUPD BIT(NPCX_ESPIWE_CFGUPDWE) -#define ESPIWE_BERR BIT(NPCX_ESPIWE_BERRWE) -#define ESPIWE_OOBRX BIT(NPCX_ESPIWE_OOBRXWE) -#define ESPIWE_FLASHRX BIT(NPCX_ESPIWE_FLASHRXWE) -#define ESPIWE_PERACC BIT(NPCX_ESPIWE_PERACCWE) -#define ESPIWE_DFRD BIT(NPCX_ESPIWE_DFRDWE) -#define ESPIWE_VWUPD BIT(NPCX_ESPIWE_VWUPDWE) -#define ESPIWE_ESPIRST BIT(NPCX_ESPIWE_ESPIRSTWE) +#define ESPIWE_IBRST BIT(NPCX_ESPIWE_IBRSTWE) +#define ESPIWE_CFGUPD BIT(NPCX_ESPIWE_CFGUPDWE) +#define ESPIWE_BERR BIT(NPCX_ESPIWE_BERRWE) +#define ESPIWE_OOBRX BIT(NPCX_ESPIWE_OOBRXWE) +#define ESPIWE_FLASHRX BIT(NPCX_ESPIWE_FLASHRXWE) +#define ESPIWE_PERACC BIT(NPCX_ESPIWE_PERACCWE) +#define ESPIWE_DFRD BIT(NPCX_ESPIWE_DFRDWE) +#define ESPIWE_VWUPD BIT(NPCX_ESPIWE_VWUPDWE) +#define ESPIWE_ESPIRST BIT(NPCX_ESPIWE_ESPIRSTWE) /* eSPI Wake-up enable for VW */ -#define ESPIWE_VW ESPIWE_VWUPD +#define ESPIWE_VW ESPIWE_VWUPD /* eSPI Wake-up enable for Generic */ -#define ESPIWE_GENERIC (ESPIWE_IBRST | ESPIWE_CFGUPD | \ - ESPIWE_BERR) +#define ESPIWE_GENERIC (ESPIWE_IBRST | ESPIWE_CFGUPD | ESPIWE_BERR) /* Macro functions for eSPI VW */ -#define ESPI_VWEVMS_NUM 12 -#define ESPI_VWEVSM_NUM 10 -#define ESPI_VW_IDX_WIRE_NUM 4 +#define ESPI_VWEVMS_NUM 12 +#define ESPI_VWEVSM_NUM 10 +#define ESPI_VW_IDX_WIRE_NUM 4 /* Determine Virtual Wire type */ -#define VM_TYPE(i) ((i >= 0 && i <= 1) ? ESPI_VW_TYPE_INT_EV : \ - (i >= 2 && i <= 7) ? ESPI_VW_TYPE_SYS_EV : \ - (i >= 64 && i <= 127) ? ESPI_VW_TYPE_PLT : \ - (i >= 128 && i <= 255) ? ESPI_VW_TYPE_GPIO : \ - ESPI_VW_TYPE_NONE) +#define VM_TYPE(i) \ + ((i >= 0 && i <= 1) ? ESPI_VW_TYPE_INT_EV : \ + (i >= 2 && i <= 7) ? ESPI_VW_TYPE_SYS_EV : \ + (i >= 64 && i <= 127) ? ESPI_VW_TYPE_PLT : \ + (i >= 128 && i <= 255) ? ESPI_VW_TYPE_GPIO : \ + ESPI_VW_TYPE_NONE) /* Bit field manipulation for VWEVMS Value */ -#define VWEVMS_INX(i) ((i<<8) & 0x00007F00) -#define VWEVMS_INX_EN(n) ((n<<15) & 0x00008000) -#define VWEVMS_PLTRST_EN(p) ((p<<17) & 0x00020000) -#define VWEVMS_INT_EN(e) ((e<<18) & 0x00040000) -#define VWEVMS_ESPIRST_EN(r) ((r<<19) & 0x00080000) -#define VWEVMS_FIELD(i, n, p, e, r) (VWEVMS_INX(i) | VWEVMS_INX_EN(n) | \ - VWEVMS_PLTRST_EN(p) | VWEVMS_INTWK_EN(e) | \ - VWEVMS_ESPIRST_EN(r)) -#define VWEVMS_IDX_GET(reg) (((reg & 0x00007F00)>>8)) +#define VWEVMS_INX(i) ((i << 8) & 0x00007F00) +#define VWEVMS_INX_EN(n) ((n << 15) & 0x00008000) +#define VWEVMS_PLTRST_EN(p) ((p << 17) & 0x00020000) +#define VWEVMS_INT_EN(e) ((e << 18) & 0x00040000) +#define VWEVMS_ESPIRST_EN(r) ((r << 19) & 0x00080000) +#define VWEVMS_FIELD(i, n, p, e, r) \ + (VWEVMS_INX(i) | VWEVMS_INX_EN(n) | VWEVMS_PLTRST_EN(p) | \ + VWEVMS_INTWK_EN(e) | VWEVMS_ESPIRST_EN(r)) +#define VWEVMS_IDX_GET(reg) (((reg & 0x00007F00) >> 8)) /* Bit field manipulation for VWEVSM Value */ -#define VWEVSM_VALID_N(v) ((v<<4) & 0x000000F0) -#define VWEVSM_INX(i) ((i<<8) & 0x00007F00) -#define VWEVSM_INX_EN(n) ((n<<15) & 0x00008000) -#define VWEVSM_DIRTY(d) ((d<<16) & 0x00010000) -#define VWEVSM_PLTRST_EN(p) ((p<<17) & 0x00020000) -#define VWEVSM_CDRST_EN(c) ((c<<19) & 0x00080000) -#define VWEVSM_FIELD(i, n, v, p, c) (VWEVSM_INX(i) | VWEVSM_INX_EN(n) | \ - VWEVSM_VALID_N(v) | VWEVSM_PLTRST_EN(p) |\ - VWEVSM_CDRST_EN(c)) -#define VWEVSM_IDX_GET(reg) (((reg & 0x00007F00)>>8)) +#define VWEVSM_VALID_N(v) ((v << 4) & 0x000000F0) +#define VWEVSM_INX(i) ((i << 8) & 0x00007F00) +#define VWEVSM_INX_EN(n) ((n << 15) & 0x00008000) +#define VWEVSM_DIRTY(d) ((d << 16) & 0x00010000) +#define VWEVSM_PLTRST_EN(p) ((p << 17) & 0x00020000) +#define VWEVSM_CDRST_EN(c) ((c << 19) & 0x00080000) +#define VWEVSM_FIELD(i, n, v, p, c) \ + (VWEVSM_INX(i) | VWEVSM_INX_EN(n) | VWEVSM_VALID_N(v) | \ + VWEVSM_PLTRST_EN(p) | VWEVSM_CDRST_EN(c)) +#define VWEVSM_IDX_GET(reg) (((reg & 0x00007F00) >> 8)) /* define macro to handle SMI/SCI Virtual Wire */ /* Read SMI VWire status from VWEVSM(offset 2) register. */ -#define SMI_STATUS_MASK ((uint8_t) (NPCX_VWEVSM(2) & 0x00000002)) +#define SMI_STATUS_MASK ((uint8_t)(NPCX_VWEVSM(2) & 0x00000002)) /* * Read SCI VWire status from VWEVSM(offset 2) register. * Left shift 2 to meet the SCIB field in HIPMIC register. */ -#define SCI_STATUS_MASK (((uint8_t) (NPCX_VWEVSM(2) & 0x00000001)) << 2) -#define SCIB_MASK(v) (v << NPCX_HIPMIC_SCIB) -#define SMIB_MASK(v) (v << NPCX_HIPMIC_SMIB) -#define NPCX_VW_SCI(level) ((NPCX_HIPMIC(PM_CHAN_1) & 0xF9) | \ - SMI_STATUS_MASK | SCIB_MASK(level)) -#define NPCX_VW_SMI(level) ((NPCX_HIPMIC(PM_CHAN_1) & 0xF9) | \ - SCI_STATUS_MASK | SMIB_MASK(level)) +#define SCI_STATUS_MASK (((uint8_t)(NPCX_VWEVSM(2) & 0x00000001)) << 2) +#define SCIB_MASK(v) (v << NPCX_HIPMIC_SCIB) +#define SMIB_MASK(v) (v << NPCX_HIPMIC_SMIB) +#define NPCX_VW_SCI(level) \ + ((NPCX_HIPMIC(PM_CHAN_1) & 0xF9) | SMI_STATUS_MASK | SCIB_MASK(level)) +#define NPCX_VW_SMI(level) \ + ((NPCX_HIPMIC(PM_CHAN_1) & 0xF9) | SCI_STATUS_MASK | SMIB_MASK(level)) /* eSPI enumeration */ /* eSPI channels */ @@ -1306,374 +1301,367 @@ enum { /* eSPI IO modes */ enum { NPCX_ESPI_IO_MODE_SINGLE = 0, - NPCX_ESPI_IO_MODE_DUAL = 1, - NPCX_ESPI_IO_MODE_QUAD = 2, - NPCX_ESPI_IO_MODE_ALL = 3, - NPCX_ESPI_IO_MODE_NONE = 0xFF + NPCX_ESPI_IO_MODE_DUAL = 1, + NPCX_ESPI_IO_MODE_QUAD = 2, + NPCX_ESPI_IO_MODE_ALL = 3, + NPCX_ESPI_IO_MODE_NONE = 0xFF }; /* eSPI IO mode selected */ enum { NPCX_ESPI_IO_MODE_SEL_SINGLE = 0, - NPCX_ESPI_IO_MODE_SEL_DUAL = 1, - NPCX_ESPI_IO_MODE_SEL_QUARD = 2, - NPCX_ESPI_IO_MODE_SEL_NONE = 0xFF + NPCX_ESPI_IO_MODE_SEL_DUAL = 1, + NPCX_ESPI_IO_MODE_SEL_QUARD = 2, + NPCX_ESPI_IO_MODE_SEL_NONE = 0xFF }; /* VW types */ enum { - ESPI_VW_TYPE_INT_EV, /* Interrupt event */ - ESPI_VW_TYPE_SYS_EV, /* System Event */ - ESPI_VW_TYPE_PLT, /* Platform specific */ - ESPI_VW_TYPE_GPIO, /* General Purpose I/O Expander */ + ESPI_VW_TYPE_INT_EV, /* Interrupt event */ + ESPI_VW_TYPE_SYS_EV, /* System Event */ + ESPI_VW_TYPE_PLT, /* Platform specific */ + ESPI_VW_TYPE_GPIO, /* General Purpose I/O Expander */ ESPI_VW_TYPE_NUM, ESPI_VW_TYPE_NONE = 0xFF }; /******************************************************************************/ /* GDMA (General DMA) Registers */ -#define NPCX_GDMA_CTL REG32(NPCX_GDMA_BASE_ADDR + 0x000) -#define NPCX_GDMA_SRCB REG32(NPCX_GDMA_BASE_ADDR + 0x004) -#define NPCX_GDMA_DSTB REG32(NPCX_GDMA_BASE_ADDR + 0x008) -#define NPCX_GDMA_TCNT REG32(NPCX_GDMA_BASE_ADDR + 0x00C) -#define NPCX_GDMA_CSRC REG32(NPCX_GDMA_BASE_ADDR + 0x010) -#define NPCX_GDMA_CDST REG32(NPCX_GDMA_BASE_ADDR + 0x014) -#define NPCX_GDMA_CTCNT REG32(NPCX_GDMA_BASE_ADDR + 0x018) - +#define NPCX_GDMA_CTL REG32(NPCX_GDMA_BASE_ADDR + 0x000) +#define NPCX_GDMA_SRCB REG32(NPCX_GDMA_BASE_ADDR + 0x004) +#define NPCX_GDMA_DSTB REG32(NPCX_GDMA_BASE_ADDR + 0x008) +#define NPCX_GDMA_TCNT REG32(NPCX_GDMA_BASE_ADDR + 0x00C) +#define NPCX_GDMA_CSRC REG32(NPCX_GDMA_BASE_ADDR + 0x010) +#define NPCX_GDMA_CDST REG32(NPCX_GDMA_BASE_ADDR + 0x014) +#define NPCX_GDMA_CTCNT REG32(NPCX_GDMA_BASE_ADDR + 0x018) /******************************************************************************/ /* GDMA register fields */ -#define NPCX_GDMA_CTL_GDMAEN 0 -#define NPCX_GDMA_CTL_GDMAMS FIELD(2, 2) -#define NPCX_GDMA_CTL_DADIR 4 -#define NPCX_GDMA_CTL_SADIR 5 -#define NPCX_GDMA_CTL_SAFIX 7 -#define NPCX_GDMA_CTL_SIEN 8 -#define NPCX_GDMA_CTL_BME 9 -#define NPCX_GDMA_CTL_SBMS 11 -#define NPCX_GDMA_CTL_TWS FIELD(12, 2) -#define NPCX_GDMA_CTL_DM 15 -#define NPCX_GDMA_CTL_SOFTREQ 16 -#define NPCX_GDMA_CTL_TC 18 -#define NPCX_GDMA_CTL_GDMAERR 20 -#define NPCX_GDMA_CTL_BLOCK_BUG_CORRECTION_DISABLE 26 +#define NPCX_GDMA_CTL_GDMAEN 0 +#define NPCX_GDMA_CTL_GDMAMS FIELD(2, 2) +#define NPCX_GDMA_CTL_DADIR 4 +#define NPCX_GDMA_CTL_SADIR 5 +#define NPCX_GDMA_CTL_SAFIX 7 +#define NPCX_GDMA_CTL_SIEN 8 +#define NPCX_GDMA_CTL_BME 9 +#define NPCX_GDMA_CTL_SBMS 11 +#define NPCX_GDMA_CTL_TWS FIELD(12, 2) +#define NPCX_GDMA_CTL_DM 15 +#define NPCX_GDMA_CTL_SOFTREQ 16 +#define NPCX_GDMA_CTL_TC 18 +#define NPCX_GDMA_CTL_GDMAERR 20 +#define NPCX_GDMA_CTL_BLOCK_BUG_CORRECTION_DISABLE 26 /******************************************************************************/ /* Nuvoton internal used only registers */ -#define NPCX_INTERNAL_CTRL1 REG8(0x400DB000) -#define NPCX_INTERNAL_CTRL2 REG8(0x400DD000) -#define NPCX_INTERNAL_CTRL3 REG8(0x400DF000) +#define NPCX_INTERNAL_CTRL1 REG8(0x400DB000) +#define NPCX_INTERNAL_CTRL2 REG8(0x400DD000) +#define NPCX_INTERNAL_CTRL3 REG8(0x400DF000) /******************************************************************************/ /* Optional M4 Registers */ -#define CPU_DHCSR REG32(0xE000EDF0) -#define CPU_MPU_CTRL REG32(0xE000ED94) -#define CPU_MPU_RNR REG32(0xE000ED98) -#define CPU_MPU_RBAR REG32(0xE000ED9C) -#define CPU_MPU_RASR REG32(0xE000EDA0) - +#define CPU_DHCSR REG32(0xE000EDF0) +#define CPU_MPU_CTRL REG32(0xE000ED94) +#define CPU_MPU_RNR REG32(0xE000ED98) +#define CPU_MPU_RBAR REG32(0xE000ED9C) +#define CPU_MPU_RASR REG32(0xE000EDA0) /******************************************************************************/ /* Flash Utiltiy definition */ /* * Flash commands for the W25Q16CV SPI flash */ -#define CMD_READ_ID 0x9F -#define CMD_READ_MAN_DEV_ID 0x90 -#define CMD_WRITE_EN 0x06 -#define CMD_WRITE_STATUS 0x50 -#define CMD_READ_STATUS_REG 0x05 -#define CMD_READ_STATUS_REG2 0x35 -#define CMD_WRITE_STATUS_REG 0x01 -#define CMD_FLASH_PROGRAM 0x02 -#define CMD_SECTOR_ERASE 0x20 -#define CMD_BLOCK_32K_ERASE 0x52 -#define CMD_BLOCK_64K_ERASE 0xd8 -#define CMD_PROGRAM_UINT_SIZE 0x08 -#define CMD_PAGE_SIZE 0x00 -#define CMD_READ_ID_TYPE 0x47 -#define CMD_FAST_READ 0x0B +#define CMD_READ_ID 0x9F +#define CMD_READ_MAN_DEV_ID 0x90 +#define CMD_WRITE_EN 0x06 +#define CMD_WRITE_STATUS 0x50 +#define CMD_READ_STATUS_REG 0x05 +#define CMD_READ_STATUS_REG2 0x35 +#define CMD_WRITE_STATUS_REG 0x01 +#define CMD_FLASH_PROGRAM 0x02 +#define CMD_SECTOR_ERASE 0x20 +#define CMD_BLOCK_32K_ERASE 0x52 +#define CMD_BLOCK_64K_ERASE 0xd8 +#define CMD_PROGRAM_UINT_SIZE 0x08 +#define CMD_PAGE_SIZE 0x00 +#define CMD_READ_ID_TYPE 0x47 +#define CMD_FAST_READ 0x0B /* * Status registers for the W25Q16CV SPI flash */ -#define SPI_FLASH_SR2_SUS BIT(7) -#define SPI_FLASH_SR2_CMP BIT(6) -#define SPI_FLASH_SR2_LB3 BIT(5) -#define SPI_FLASH_SR2_LB2 BIT(4) -#define SPI_FLASH_SR2_LB1 BIT(3) -#define SPI_FLASH_SR2_QE BIT(1) -#define SPI_FLASH_SR2_SRP1 BIT(0) -#define SPI_FLASH_SR1_SRP0 BIT(7) -#define SPI_FLASH_SR1_SEC BIT(6) -#define SPI_FLASH_SR1_TB BIT(5) -#define SPI_FLASH_SR1_BP2 BIT(4) -#define SPI_FLASH_SR1_BP1 BIT(3) -#define SPI_FLASH_SR1_BP0 BIT(2) -#define SPI_FLASH_SR1_WEL BIT(1) -#define SPI_FLASH_SR1_BUSY BIT(0) - +#define SPI_FLASH_SR2_SUS BIT(7) +#define SPI_FLASH_SR2_CMP BIT(6) +#define SPI_FLASH_SR2_LB3 BIT(5) +#define SPI_FLASH_SR2_LB2 BIT(4) +#define SPI_FLASH_SR2_LB1 BIT(3) +#define SPI_FLASH_SR2_QE BIT(1) +#define SPI_FLASH_SR2_SRP1 BIT(0) +#define SPI_FLASH_SR1_SRP0 BIT(7) +#define SPI_FLASH_SR1_SEC BIT(6) +#define SPI_FLASH_SR1_TB BIT(5) +#define SPI_FLASH_SR1_BP2 BIT(4) +#define SPI_FLASH_SR1_BP1 BIT(3) +#define SPI_FLASH_SR1_BP0 BIT(2) +#define SPI_FLASH_SR1_WEL BIT(1) +#define SPI_FLASH_SR1_BUSY BIT(0) /* 0: F_CS0 1: F_CS1_1(GPIO86) 2:F_CS1_2(GPIOA6) */ -#define FIU_CHIP_SELECT 0 +#define FIU_CHIP_SELECT 0 /* Create UMA control mask */ -#define MASK(bit) (0x1 << (bit)) -#define A_SIZE 0x03 /* 0: No ADR field 1: 3-bytes ADR field */ -#define C_SIZE 0x04 /* 0: 1-Byte CMD field 1:No CMD field */ -#define RD_WR 0x05 /* 0: Read 1: Write */ -#define DEV_NUM 0x06 /* 0: PVT is used 1: SHD is used */ -#define EXEC_DONE 0x07 -#define D_SIZE_1 0x01 -#define D_SIZE_2 0x02 -#define D_SIZE_3 0x03 -#define D_SIZE_4 0x04 -#define FLASH_SEL MASK(DEV_NUM) - -#define MASK_CMD_ONLY (MASK(EXEC_DONE) | FLASH_SEL) -#define MASK_CMD_ADR (MASK(EXEC_DONE) | FLASH_SEL | MASK(A_SIZE)) -#define MASK_CMD_ADR_WR (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \ - |MASK(A_SIZE) | D_SIZE_1) -#define MASK_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_1) -#define MASK_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_2) -#define MASK_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_3) -#define MASK_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_4) -#define MASK_CMD_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_1) -#define MASK_CMD_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_2) -#define MASK_CMD_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_3) -#define MASK_CMD_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_4) -#define MASK_CMD_WR_ONLY (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR)) -#define MASK_CMD_WR_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \ - | MASK(C_SIZE) | D_SIZE_1) -#define MASK_CMD_WR_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \ - | MASK(C_SIZE) | D_SIZE_2) -#define MASK_CMD_WR_ADR (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \ - | MASK(A_SIZE)) +#define MASK(bit) (0x1 << (bit)) +#define A_SIZE 0x03 /* 0: No ADR field 1: 3-bytes ADR field */ +#define C_SIZE 0x04 /* 0: 1-Byte CMD field 1:No CMD field */ +#define RD_WR 0x05 /* 0: Read 1: Write */ +#define DEV_NUM 0x06 /* 0: PVT is used 1: SHD is used */ +#define EXEC_DONE 0x07 +#define D_SIZE_1 0x01 +#define D_SIZE_2 0x02 +#define D_SIZE_3 0x03 +#define D_SIZE_4 0x04 +#define FLASH_SEL MASK(DEV_NUM) + +#define MASK_CMD_ONLY (MASK(EXEC_DONE) | FLASH_SEL) +#define MASK_CMD_ADR (MASK(EXEC_DONE) | FLASH_SEL | MASK(A_SIZE)) +#define MASK_CMD_ADR_WR \ + (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(A_SIZE) | D_SIZE_1) +#define MASK_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_1) +#define MASK_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_2) +#define MASK_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_3) +#define MASK_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_4) +#define MASK_CMD_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_1) +#define MASK_CMD_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_2) +#define MASK_CMD_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_3) +#define MASK_CMD_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_4) +#define MASK_CMD_WR_ONLY (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR)) +#define MASK_CMD_WR_1BYTE \ + (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(C_SIZE) | D_SIZE_1) +#define MASK_CMD_WR_2BYTE \ + (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(C_SIZE) | D_SIZE_2) +#define MASK_CMD_WR_ADR \ + (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(A_SIZE)) /******************************************************************************/ /* APM (Audio Processing Module) Registers */ -#define NPCX_APM_SR REG8(NPCX_APM_BASE_ADDR + 0x000) -#define NPCX_APM_SR2 REG8(NPCX_APM_BASE_ADDR + 0x004) -#define NPCX_APM_ICR REG8(NPCX_APM_BASE_ADDR + 0x008) -#define NPCX_APM_IMR REG8(NPCX_APM_BASE_ADDR + 0x00C) -#define NPCX_APM_IFR REG8(NPCX_APM_BASE_ADDR + 0x010) -#define NPCX_APM_CR_APM REG8(NPCX_APM_BASE_ADDR + 0x014) -#define NPCX_APM_CR_CK REG8(NPCX_APM_BASE_ADDR + 0x018) -#define NPCX_APM_AICR_ADC REG8(NPCX_APM_BASE_ADDR + 0x01C) -#define NPCX_APM_FCR_ADC REG8(NPCX_APM_BASE_ADDR + 0x020) -#define NPCX_APM_CR_DMIC REG8(NPCX_APM_BASE_ADDR + 0x02C) -#define NPCX_APM_CR_ADC REG8(NPCX_APM_BASE_ADDR + 0x030) -#define NPCX_APM_CR_MIX REG8(NPCX_APM_BASE_ADDR + 0x034) -#define NPCX_APM_DR_MIX REG8(NPCX_APM_BASE_ADDR + 0x038) -#define NPCX_APM_GCR_ADCL REG8(NPCX_APM_BASE_ADDR + 0x03C) -#define NPCX_APM_GCR_ADCR REG8(NPCX_APM_BASE_ADDR + 0x040) -#define NPCX_APM_GCR_MIXADCL REG8(NPCX_APM_BASE_ADDR + 0x044) -#define NPCX_APM_GCR_MIXADCR REG8(NPCX_APM_BASE_ADDR + 0x048) -#define NPCX_APM_CR_ADC_AGC REG8(NPCX_APM_BASE_ADDR + 0x04C) -#define NPCX_APM_DR_ADC_AGC REG8(NPCX_APM_BASE_ADDR + 0x050) -#define NPCX_APM_SR_ADC_AGCDGL REG8(NPCX_APM_BASE_ADDR + 0x054) -#define NPCX_APM_SR_ADC_AGCDGR REG8(NPCX_APM_BASE_ADDR + 0x058) -#define NPCX_APM_CR_VAD REG8(NPCX_APM_BASE_ADDR + 0x05C) -#define NPCX_APM_DR_VAD REG8(NPCX_APM_BASE_ADDR + 0x060) -#define NPCX_APM_CR_VAD_CMD REG8(NPCX_APM_BASE_ADDR + 0x064) -#define NPCX_APM_CR_TR REG8(NPCX_APM_BASE_ADDR + 0x068) -#define NPCX_APM_DR_TR REG8(NPCX_APM_BASE_ADDR + 0x06C) -#define NPCX_APM_SR_TR1 REG8(NPCX_APM_BASE_ADDR + 0x070) -#define NPCX_APM_SR_TR_SRCADC REG8(NPCX_APM_BASE_ADDR + 0x074) +#define NPCX_APM_SR REG8(NPCX_APM_BASE_ADDR + 0x000) +#define NPCX_APM_SR2 REG8(NPCX_APM_BASE_ADDR + 0x004) +#define NPCX_APM_ICR REG8(NPCX_APM_BASE_ADDR + 0x008) +#define NPCX_APM_IMR REG8(NPCX_APM_BASE_ADDR + 0x00C) +#define NPCX_APM_IFR REG8(NPCX_APM_BASE_ADDR + 0x010) +#define NPCX_APM_CR_APM REG8(NPCX_APM_BASE_ADDR + 0x014) +#define NPCX_APM_CR_CK REG8(NPCX_APM_BASE_ADDR + 0x018) +#define NPCX_APM_AICR_ADC REG8(NPCX_APM_BASE_ADDR + 0x01C) +#define NPCX_APM_FCR_ADC REG8(NPCX_APM_BASE_ADDR + 0x020) +#define NPCX_APM_CR_DMIC REG8(NPCX_APM_BASE_ADDR + 0x02C) +#define NPCX_APM_CR_ADC REG8(NPCX_APM_BASE_ADDR + 0x030) +#define NPCX_APM_CR_MIX REG8(NPCX_APM_BASE_ADDR + 0x034) +#define NPCX_APM_DR_MIX REG8(NPCX_APM_BASE_ADDR + 0x038) +#define NPCX_APM_GCR_ADCL REG8(NPCX_APM_BASE_ADDR + 0x03C) +#define NPCX_APM_GCR_ADCR REG8(NPCX_APM_BASE_ADDR + 0x040) +#define NPCX_APM_GCR_MIXADCL REG8(NPCX_APM_BASE_ADDR + 0x044) +#define NPCX_APM_GCR_MIXADCR REG8(NPCX_APM_BASE_ADDR + 0x048) +#define NPCX_APM_CR_ADC_AGC REG8(NPCX_APM_BASE_ADDR + 0x04C) +#define NPCX_APM_DR_ADC_AGC REG8(NPCX_APM_BASE_ADDR + 0x050) +#define NPCX_APM_SR_ADC_AGCDGL REG8(NPCX_APM_BASE_ADDR + 0x054) +#define NPCX_APM_SR_ADC_AGCDGR REG8(NPCX_APM_BASE_ADDR + 0x058) +#define NPCX_APM_CR_VAD REG8(NPCX_APM_BASE_ADDR + 0x05C) +#define NPCX_APM_DR_VAD REG8(NPCX_APM_BASE_ADDR + 0x060) +#define NPCX_APM_CR_VAD_CMD REG8(NPCX_APM_BASE_ADDR + 0x064) +#define NPCX_APM_CR_TR REG8(NPCX_APM_BASE_ADDR + 0x068) +#define NPCX_APM_DR_TR REG8(NPCX_APM_BASE_ADDR + 0x06C) +#define NPCX_APM_SR_TR1 REG8(NPCX_APM_BASE_ADDR + 0x070) +#define NPCX_APM_SR_TR_SRCADC REG8(NPCX_APM_BASE_ADDR + 0x074) /******************************************************************************/ /* APM register fields */ -#define NPCX_APM_SR_IRQ_PEND 6 -#define NPCX_APM_SR2_SMUTEIP 6 -#define NPCX_APM_ICR_INTR_MODE FIELD(6, 2) -#define NPCX_APM_IMR_VAD_DTC_MASK 6 -#define NPCX_APM_IFR_VAD_DTC 6 -#define NPCX_APM_CR_APM_PD 0 -#define NPCX_APM_CR_APM_AGC_DIS FIELD(1, 2) -#define NPCX_APM_CR_CK_MCLK_FREQ FIELD(0, 2) -#define NPCX_APM_AICR_ADC_ADC_AUDIOIF FIELD(0, 2) -#define NPCX_APM_AICR_ADC_PD_AICR_ADC 4 -#define NPCX_APM_AICR_ADC_ADC_ADWL FIELD(6, 2) -#define NPCX_APM_FCR_ADC_ADC_FREQ FIELD(0, 4) -#define NPCX_APM_FCR_ADC_ADC_WNF FIELD(4, 2) -#define NPCX_APM_FCR_ADC_ADC_HPF 6 -#define NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT FIELD(0, 2) -#define NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT FIELD(2, 2) -#define NPCX_APM_CR_DMIC_ADC_DMIC_RATE FIELD(4, 3) -#define NPCX_APM_CR_DMIC_PD_DMIC 7 -#define NPCX_APM_CR_ADC_ADC_SOFT_MUTE 7 -#define NPCX_APM_CR_MIX_MIX_ADD FIELD(0, 6) -#define NPCX_APM_CR_MIX_MIX_LOAD 6 -#define NPCX_APM_DR_MIX_MIX_DATA FIELD(0, 8) -#define NPCX_APM_MIX_2_AIADCR_SEL FIELD(4, 2) -#define NPCX_APM_MIX_2_AIADCL_SEL FIELD(6, 2) -#define NPCX_APM_GCR_ADCL_GIDL FIELD(0, 6) -#define NPCX_APM_GCR_ADCL_LRGID 7 -#define NPCX_APM_GCR_ADCR_GIDR FIELD(0, 6) -#define NPCX_APM_GCR_MIXADCL_GIMIXL FIELD(0, 6) -#define NPCX_APM_GCR_MIXADCR_GIMIXR FIELD(0, 6) -#define NPCX_APM_CR_ADC_AGC_ADC_AGC_ADD FIELD(0, 6) -#define NPCX_APM_CR_ADC_AGC_ADC_AGC_LOAD 6 -#define NPCX_APM_CR_ADC_AGC_ADC_AGC_EN 7 -#define NPCX_APM_DR_ADC_AGC_ADC_AGC_DATA FIELD(0, 8) -#define NPCX_ADC_AGC_0_AGC_TARGET FIELD(2, 4) -#define NPCX_ADC_AGC_0_AGC_STEREO 6 -#define NPCX_ADC_AGC_1_HOLD FIELD(0, 4) -#define NPCX_ADC_AGC_1_NG_THR FIELD(4, 3) -#define NPCX_ADC_AGC_1_NG_EN 7 -#define NPCX_ADC_AGC_2_DCY FIELD(0, 4) -#define NPCX_ADC_AGC_2_ATK FIELD(4, 4) -#define NPCX_ADC_AGC_3_AGC_MAX FIELD(0, 5) -#define NPCX_ADC_AGC_4_AGC_MIN FIELD(0, 5) -#define NPCX_APM_CR_VAD_VAD_ADD FIELD(0, 6) -#define NPCX_APM_CR_VAD_VAD_LOAD 6 -#define NPCX_APM_CR_VAD_VAD_EN 7 -#define NPCX_APM_DR_VAD_VAD_DATA FIELD(0, 8) -#define NPCX_APM_CR_VAD_CMD_VAD_RESTART 0 -#define NPCX_APM_CR_TR_FAST_ON 7 -#define NPCX_VAD_0_VAD_INSEL FIELD(0, 2) -#define NPCX_VAD_0_VAD_DMIC_FREQ FIELD(2, 3) -#define NPCX_VAD_0_VAD_ADC_WAKEUP 5 -#define NPCX_VAD_0_ZCD_EN 6 -#define NPCX_VAD_1_VAD_POWER_SENS FIELD(0, 5) -#define NPCX_APM_CONTROL_ADD FIELD(0, 6) -#define NPCX_APM_CONTROL_LOAD 6 +#define NPCX_APM_SR_IRQ_PEND 6 +#define NPCX_APM_SR2_SMUTEIP 6 +#define NPCX_APM_ICR_INTR_MODE FIELD(6, 2) +#define NPCX_APM_IMR_VAD_DTC_MASK 6 +#define NPCX_APM_IFR_VAD_DTC 6 +#define NPCX_APM_CR_APM_PD 0 +#define NPCX_APM_CR_APM_AGC_DIS FIELD(1, 2) +#define NPCX_APM_CR_CK_MCLK_FREQ FIELD(0, 2) +#define NPCX_APM_AICR_ADC_ADC_AUDIOIF FIELD(0, 2) +#define NPCX_APM_AICR_ADC_PD_AICR_ADC 4 +#define NPCX_APM_AICR_ADC_ADC_ADWL FIELD(6, 2) +#define NPCX_APM_FCR_ADC_ADC_FREQ FIELD(0, 4) +#define NPCX_APM_FCR_ADC_ADC_WNF FIELD(4, 2) +#define NPCX_APM_FCR_ADC_ADC_HPF 6 +#define NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT FIELD(0, 2) +#define NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT FIELD(2, 2) +#define NPCX_APM_CR_DMIC_ADC_DMIC_RATE FIELD(4, 3) +#define NPCX_APM_CR_DMIC_PD_DMIC 7 +#define NPCX_APM_CR_ADC_ADC_SOFT_MUTE 7 +#define NPCX_APM_CR_MIX_MIX_ADD FIELD(0, 6) +#define NPCX_APM_CR_MIX_MIX_LOAD 6 +#define NPCX_APM_DR_MIX_MIX_DATA FIELD(0, 8) +#define NPCX_APM_MIX_2_AIADCR_SEL FIELD(4, 2) +#define NPCX_APM_MIX_2_AIADCL_SEL FIELD(6, 2) +#define NPCX_APM_GCR_ADCL_GIDL FIELD(0, 6) +#define NPCX_APM_GCR_ADCL_LRGID 7 +#define NPCX_APM_GCR_ADCR_GIDR FIELD(0, 6) +#define NPCX_APM_GCR_MIXADCL_GIMIXL FIELD(0, 6) +#define NPCX_APM_GCR_MIXADCR_GIMIXR FIELD(0, 6) +#define NPCX_APM_CR_ADC_AGC_ADC_AGC_ADD FIELD(0, 6) +#define NPCX_APM_CR_ADC_AGC_ADC_AGC_LOAD 6 +#define NPCX_APM_CR_ADC_AGC_ADC_AGC_EN 7 +#define NPCX_APM_DR_ADC_AGC_ADC_AGC_DATA FIELD(0, 8) +#define NPCX_ADC_AGC_0_AGC_TARGET FIELD(2, 4) +#define NPCX_ADC_AGC_0_AGC_STEREO 6 +#define NPCX_ADC_AGC_1_HOLD FIELD(0, 4) +#define NPCX_ADC_AGC_1_NG_THR FIELD(4, 3) +#define NPCX_ADC_AGC_1_NG_EN 7 +#define NPCX_ADC_AGC_2_DCY FIELD(0, 4) +#define NPCX_ADC_AGC_2_ATK FIELD(4, 4) +#define NPCX_ADC_AGC_3_AGC_MAX FIELD(0, 5) +#define NPCX_ADC_AGC_4_AGC_MIN FIELD(0, 5) +#define NPCX_APM_CR_VAD_VAD_ADD FIELD(0, 6) +#define NPCX_APM_CR_VAD_VAD_LOAD 6 +#define NPCX_APM_CR_VAD_VAD_EN 7 +#define NPCX_APM_DR_VAD_VAD_DATA FIELD(0, 8) +#define NPCX_APM_CR_VAD_CMD_VAD_RESTART 0 +#define NPCX_APM_CR_TR_FAST_ON 7 +#define NPCX_VAD_0_VAD_INSEL FIELD(0, 2) +#define NPCX_VAD_0_VAD_DMIC_FREQ FIELD(2, 3) +#define NPCX_VAD_0_VAD_ADC_WAKEUP 5 +#define NPCX_VAD_0_ZCD_EN 6 +#define NPCX_VAD_1_VAD_POWER_SENS FIELD(0, 5) +#define NPCX_APM_CONTROL_ADD FIELD(0, 6) +#define NPCX_APM_CONTROL_LOAD 6 /******************************************************************************/ /* FMUL2 (Frequency Multiplier Module 2) Registers */ -#define NPCX_FMUL2_FM2CTRL REG8(NPCX_FMUL2_BASE_ADDR + 0x000) -#define NPCX_FMUL2_FM2ML REG8(NPCX_FMUL2_BASE_ADDR + 0x002) -#define NPCX_FMUL2_FM2MH REG8(NPCX_FMUL2_BASE_ADDR + 0x004) -#define NPCX_FMUL2_FM2N REG8(NPCX_FMUL2_BASE_ADDR + 0x006) -#define NPCX_FMUL2_FM2P REG8(NPCX_FMUL2_BASE_ADDR + 0x008) -#define NPCX_FMUL2_FM2_VER REG8(NPCX_FMUL2_BASE_ADDR + 0x00A) +#define NPCX_FMUL2_FM2CTRL REG8(NPCX_FMUL2_BASE_ADDR + 0x000) +#define NPCX_FMUL2_FM2ML REG8(NPCX_FMUL2_BASE_ADDR + 0x002) +#define NPCX_FMUL2_FM2MH REG8(NPCX_FMUL2_BASE_ADDR + 0x004) +#define NPCX_FMUL2_FM2N REG8(NPCX_FMUL2_BASE_ADDR + 0x006) +#define NPCX_FMUL2_FM2P REG8(NPCX_FMUL2_BASE_ADDR + 0x008) +#define NPCX_FMUL2_FM2_VER REG8(NPCX_FMUL2_BASE_ADDR + 0x00A) /******************************************************************************/ /* FMUL2 register fields */ -#define NPCX_FMUL2_FM2CTRL_LOAD2 0 -#define NPCX_FMUL2_FM2CTRL_LOCK2 2 -#define NPCX_FMUL2_FM2CTRL_FMUL2_DIS 5 -#define NPCX_FMUL2_FM2CTRL_TUNE_DIS 6 -#define NPCX_FMUL2_FM2CTRL_CLK2_CHNG 7 -#define NPCX_FMUL2_FM2N_FM2N FIELD(0, 6) -#define NPCX_FMUL2_FM2P_WFPRED FIELD(4, 4) +#define NPCX_FMUL2_FM2CTRL_LOAD2 0 +#define NPCX_FMUL2_FM2CTRL_LOCK2 2 +#define NPCX_FMUL2_FM2CTRL_FMUL2_DIS 5 +#define NPCX_FMUL2_FM2CTRL_TUNE_DIS 6 +#define NPCX_FMUL2_FM2CTRL_CLK2_CHNG 7 +#define NPCX_FMUL2_FM2N_FM2N FIELD(0, 6) +#define NPCX_FMUL2_FM2P_WFPRED FIELD(4, 4) /******************************************************************************/ /* WOV (Wake-on-Voice) Registers */ -#define NPCX_WOV_CLOCK_CNTL REG32(NPCX_WOV_BASE_ADDR + 0x000) -#define NPCX_WOV_PLL_CNTL1 REG32(NPCX_WOV_BASE_ADDR + 0x004) -#define NPCX_WOV_PLL_CNTL2 REG32(NPCX_WOV_BASE_ADDR + 0x008) -#define NPCX_WOV_FIFO_CNT REG32(NPCX_WOV_BASE_ADDR + 0x00C) -#define NPCX_WOV_FIFO_OUT REG32(NPCX_WOV_BASE_ADDR + 0x010) -#define NPCX_WOV_STATUS REG32(NPCX_WOV_BASE_ADDR + 0x014) -#define NPCX_WOV_WOV_INTEN REG32(NPCX_WOV_BASE_ADDR + 0x018) -#define NPCX_WOV_APM_CTRL REG32(NPCX_WOV_BASE_ADDR + 0x01C) -#define NPCX_WOV_I2S_CNTL(n) REG32(NPCX_WOV_BASE_ADDR + 0x020 + (4*n)) -#define NPCX_WOV_VERSION REG32(NPCX_WOV_BASE_ADDR + 0x030) +#define NPCX_WOV_CLOCK_CNTL REG32(NPCX_WOV_BASE_ADDR + 0x000) +#define NPCX_WOV_PLL_CNTL1 REG32(NPCX_WOV_BASE_ADDR + 0x004) +#define NPCX_WOV_PLL_CNTL2 REG32(NPCX_WOV_BASE_ADDR + 0x008) +#define NPCX_WOV_FIFO_CNT REG32(NPCX_WOV_BASE_ADDR + 0x00C) +#define NPCX_WOV_FIFO_OUT REG32(NPCX_WOV_BASE_ADDR + 0x010) +#define NPCX_WOV_STATUS REG32(NPCX_WOV_BASE_ADDR + 0x014) +#define NPCX_WOV_WOV_INTEN REG32(NPCX_WOV_BASE_ADDR + 0x018) +#define NPCX_WOV_APM_CTRL REG32(NPCX_WOV_BASE_ADDR + 0x01C) +#define NPCX_WOV_I2S_CNTL(n) REG32(NPCX_WOV_BASE_ADDR + 0x020 + (4 * n)) +#define NPCX_WOV_VERSION REG32(NPCX_WOV_BASE_ADDR + 0x030) /******************************************************************************/ /* WOV register fields */ -#define NPCX_WOV_CLOCK_CNT_CLK_SEL 0 -#define NPCX_WOV_CLOCK_CNT_DMIC_EN 3 -#define NPCX_WOV_CLOCK_CNT_PLL_EDIV_SEL 7 -#define NPCX_WOV_CLOCK_CNT_PLL_EDIV FIELD(8, 7) -#define NPCX_WOV_CLOCK_CNT_PLL_EDIV_DC FIELD(16, 7) -#define NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_EN 24 -#define NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_SEL 25 -#define NPCX_WOV_FIFO_CNT_FIFO_ITHRSH FIELD(0, 6) -#define NPCX_WOV_FIFO_CNT_FIFO_WTHRSH FIELD(6, 6) -#define NPCX_WOV_FIFO_CNT_I2S_FFRST 13 -#define NPCX_WOV_FIFO_CNT_CORE_FFRST 14 -#define NPCX_WOV_FIFO_CNT_CFIFO_ISEL FIELD(16, 3) -#define NPCX_WOV_STATUS_CFIFO_CNT FIELD(0, 8) -#define NPCX_WOV_STATUS_CFIFO_NE 8 -#define NPCX_WOV_STATUS_CFIFO_OIT 9 -#define NPCX_WOV_STATUS_CFIFO_OWT 10 -#define NPCX_WOV_STATUS_CFIFO_OVRN 11 -#define NPCX_WOV_STATUS_I2S_FIFO_OVRN 12 -#define NPCX_WOV_STATUS_I2S_FIFO_UNDRN 13 -#define NPCX_WOV_STATUS_BITS FIELD(9, 6) -#define NPCX_WOV_INTEN_VAD_INTEN 0 -#define NPCX_WOV_INTEN_VAD_WKEN 1 -#define NPCX_WOV_INTEN_CFIFO_NE_IE 8 -#define NPCX_WOV_INTEN_CFIFO_OIT_IE 9 -#define NPCX_WOV_INTEN_CFIFO_OWT_WE 10 -#define NPCX_WOV_INTEN_CFIFO_OVRN_IE 11 -#define NPCX_WOV_INTEN_I2S_FIFO_OVRN_IE 12 -#define NPCX_WOV_INTEN_I2S_FIFO_UNDRN_IE 13 -#define NPCX_WOV_APM_CTRL_APM_RST 0 -#define NPCX_WOV_PLL_CNTL1_PLL_PWDEN 0 -#define NPCX_WOV_PLL_CNTL1_PLL_OTDV1 FIELD(4, 4) -#define NPCX_WOV_PLL_CNTL1_PLL_OTDV2 FIELD(8, 4) -#define NPCX_WOV_PLL_CNTL1_PLL_LOCKI 15 -#define NPCX_WOV_PLL_CNTL2_PLL_FBDV FIELD(0, 12) -#define NPCX_WOV_PLL_CNTL2_PLL_INDV FIELD(12, 4) -#define NPCX_WOV_I2S_CNTL_I2S_BCNT FIELD(0, 5) -#define NPCX_WOV_I2S_CNTL_I2S_TRIG 5 -#define NPCX_WOV_I2S_CNTL_I2S_LBHIZ 6 -#define NPCX_WOV_I2S_CNTL_I2S_ST_DEL FIELD(7, 9) -#define NPCX_WOV_I2S_CNTL_I2S_CHAN FIELD(0, 16) -#define NPCX_WOV_I2S_CNTL0_I2S_HIZD 16 -#define NPCX_WOV_I2S_CNTL0_I2S_HIZ 17 -#define NPCX_WOV_I2S_CNTL0_I2S_SCLK_INV 18 -#define NPCX_WOV_I2S_CNTL0_I2S_OPS 19 -#define NPCX_WOV_I2S_CNTL0_I2S_OPE 20 -#define NPCX_WOV_I2S_CNTL0_I2S_IPS 21 -#define NPCX_WOV_I2S_CNTL0_I2S_IPE 22 -#define NPCX_WOV_I2S_CNTL0_I2S_TST 23 -#define NPCX_WOV_I2S_CNTL1_I2S_CHN1_DIS 24 +#define NPCX_WOV_CLOCK_CNT_CLK_SEL 0 +#define NPCX_WOV_CLOCK_CNT_DMIC_EN 3 +#define NPCX_WOV_CLOCK_CNT_PLL_EDIV_SEL 7 +#define NPCX_WOV_CLOCK_CNT_PLL_EDIV FIELD(8, 7) +#define NPCX_WOV_CLOCK_CNT_PLL_EDIV_DC FIELD(16, 7) +#define NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_EN 24 +#define NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_SEL 25 +#define NPCX_WOV_FIFO_CNT_FIFO_ITHRSH FIELD(0, 6) +#define NPCX_WOV_FIFO_CNT_FIFO_WTHRSH FIELD(6, 6) +#define NPCX_WOV_FIFO_CNT_I2S_FFRST 13 +#define NPCX_WOV_FIFO_CNT_CORE_FFRST 14 +#define NPCX_WOV_FIFO_CNT_CFIFO_ISEL FIELD(16, 3) +#define NPCX_WOV_STATUS_CFIFO_CNT FIELD(0, 8) +#define NPCX_WOV_STATUS_CFIFO_NE 8 +#define NPCX_WOV_STATUS_CFIFO_OIT 9 +#define NPCX_WOV_STATUS_CFIFO_OWT 10 +#define NPCX_WOV_STATUS_CFIFO_OVRN 11 +#define NPCX_WOV_STATUS_I2S_FIFO_OVRN 12 +#define NPCX_WOV_STATUS_I2S_FIFO_UNDRN 13 +#define NPCX_WOV_STATUS_BITS FIELD(9, 6) +#define NPCX_WOV_INTEN_VAD_INTEN 0 +#define NPCX_WOV_INTEN_VAD_WKEN 1 +#define NPCX_WOV_INTEN_CFIFO_NE_IE 8 +#define NPCX_WOV_INTEN_CFIFO_OIT_IE 9 +#define NPCX_WOV_INTEN_CFIFO_OWT_WE 10 +#define NPCX_WOV_INTEN_CFIFO_OVRN_IE 11 +#define NPCX_WOV_INTEN_I2S_FIFO_OVRN_IE 12 +#define NPCX_WOV_INTEN_I2S_FIFO_UNDRN_IE 13 +#define NPCX_WOV_APM_CTRL_APM_RST 0 +#define NPCX_WOV_PLL_CNTL1_PLL_PWDEN 0 +#define NPCX_WOV_PLL_CNTL1_PLL_OTDV1 FIELD(4, 4) +#define NPCX_WOV_PLL_CNTL1_PLL_OTDV2 FIELD(8, 4) +#define NPCX_WOV_PLL_CNTL1_PLL_LOCKI 15 +#define NPCX_WOV_PLL_CNTL2_PLL_FBDV FIELD(0, 12) +#define NPCX_WOV_PLL_CNTL2_PLL_INDV FIELD(12, 4) +#define NPCX_WOV_I2S_CNTL_I2S_BCNT FIELD(0, 5) +#define NPCX_WOV_I2S_CNTL_I2S_TRIG 5 +#define NPCX_WOV_I2S_CNTL_I2S_LBHIZ 6 +#define NPCX_WOV_I2S_CNTL_I2S_ST_DEL FIELD(7, 9) +#define NPCX_WOV_I2S_CNTL_I2S_CHAN FIELD(0, 16) +#define NPCX_WOV_I2S_CNTL0_I2S_HIZD 16 +#define NPCX_WOV_I2S_CNTL0_I2S_HIZ 17 +#define NPCX_WOV_I2S_CNTL0_I2S_SCLK_INV 18 +#define NPCX_WOV_I2S_CNTL0_I2S_OPS 19 +#define NPCX_WOV_I2S_CNTL0_I2S_OPE 20 +#define NPCX_WOV_I2S_CNTL0_I2S_IPS 21 +#define NPCX_WOV_I2S_CNTL0_I2S_IPE 22 +#define NPCX_WOV_I2S_CNTL0_I2S_TST 23 +#define NPCX_WOV_I2S_CNTL1_I2S_CHN1_DIS 24 /******************************************************************************/ /* PS/2 registers */ -#define NPCX_PS2_PSDAT REG8(NPCX_PS2_BASE_ADDR + 0x000) -#define NPCX_PS2_PSTAT REG8(NPCX_PS2_BASE_ADDR + 0x002) -#define NPCX_PS2_PSCON REG8(NPCX_PS2_BASE_ADDR + 0x004) -#define NPCX_PS2_PSOSIG REG8(NPCX_PS2_BASE_ADDR + 0x006) -#define NPCX_PS2_PSISIG REG8(NPCX_PS2_BASE_ADDR + 0x008) -#define NPCX_PS2_PSIEN REG8(NPCX_PS2_BASE_ADDR + 0x00A) +#define NPCX_PS2_PSDAT REG8(NPCX_PS2_BASE_ADDR + 0x000) +#define NPCX_PS2_PSTAT REG8(NPCX_PS2_BASE_ADDR + 0x002) +#define NPCX_PS2_PSCON REG8(NPCX_PS2_BASE_ADDR + 0x004) +#define NPCX_PS2_PSOSIG REG8(NPCX_PS2_BASE_ADDR + 0x006) +#define NPCX_PS2_PSISIG REG8(NPCX_PS2_BASE_ADDR + 0x008) +#define NPCX_PS2_PSIEN REG8(NPCX_PS2_BASE_ADDR + 0x00A) /* PS/2 register field */ -#define NPCX_PS2_PSTAT_SOT 0 -#define NPCX_PS2_PSTAT_EOT 1 -#define NPCX_PS2_PSTAT_PERR 2 -#define NPCX_PS2_PSTAT_ACH FIELD(3, 3) -#define NPCX_PS2_PSTAT_RFERR 6 - -#define NPCX_PS2_PSCON_EN 0 -#define NPCX_PS2_PSCON_XMT 1 -#define NPCX_PS2_PSCON_HDRV FIELD(2, 2) -#define NPCX_PS2_PSCON_IDB FIELD(4, 3) -#define NPCX_PS2_PSCON_WPUED 7 - -#define NPCX_PS2_PSOSIG_WDAT0 0 -#define NPCX_PS2_PSOSIG_WDAT1 1 -#define NPCX_PS2_PSOSIG_WDAT2 2 -#define NPCX_PS2_PSOSIG_CLK0 3 -#define NPCX_PS2_PSOSIG_CLK1 4 -#define NPCX_PS2_PSOSIG_CLK2 5 -#define NPCX_PS2_PSOSIG_WDAT3 6 -#define NPCX_PS2_PSOSIG_CLK3 7 -#define NPCX_PS2_PSOSIG_CLK(n) (((n) < NPCX_PS2_CH3) ? \ - ((n) + 3) : 7) -#define NPCX_PS2_PSOSIG_WDAT(n) (((n) < NPCX_PS2_CH3) ? \ - ((n) + 0) : 6) -#define NPCX_PS2_PSOSIG_CLK_MASK_ALL \ - (BIT(NPCX_PS2_PSOSIG_CLK0) | \ - BIT(NPCX_PS2_PSOSIG_CLK1) | \ - BIT(NPCX_PS2_PSOSIG_CLK2) | \ - BIT(NPCX_PS2_PSOSIG_CLK3)) - -#define NPCX_PS2_PSISIG_RDAT0 0 -#define NPCX_PS2_PSISIG_RDAT1 1 -#define NPCX_PS2_PSISIG_RDAT2 2 -#define NPCX_PS2_PSISIG_RCLK0 3 -#define NPCX_PS2_PSISIG_RCLK1 4 -#define NPCX_PS2_PSISIG_RCLK2 5 -#define NPCX_PS2_PSISIG_RDAT3 6 -#define NPCX_PS2_PSISIG_RCLK3 7 -#define NPCX_PS2_PSIEN_SOTIE 0 -#define NPCX_PS2_PSIEN_EOTIE 1 -#define NPCX_PS2_PSIEN_PS2_WUE 4 -#define NPCX_PS2_PSIEN_PS2_CLK_SEL 7 +#define NPCX_PS2_PSTAT_SOT 0 +#define NPCX_PS2_PSTAT_EOT 1 +#define NPCX_PS2_PSTAT_PERR 2 +#define NPCX_PS2_PSTAT_ACH FIELD(3, 3) +#define NPCX_PS2_PSTAT_RFERR 6 + +#define NPCX_PS2_PSCON_EN 0 +#define NPCX_PS2_PSCON_XMT 1 +#define NPCX_PS2_PSCON_HDRV FIELD(2, 2) +#define NPCX_PS2_PSCON_IDB FIELD(4, 3) +#define NPCX_PS2_PSCON_WPUED 7 + +#define NPCX_PS2_PSOSIG_WDAT0 0 +#define NPCX_PS2_PSOSIG_WDAT1 1 +#define NPCX_PS2_PSOSIG_WDAT2 2 +#define NPCX_PS2_PSOSIG_CLK0 3 +#define NPCX_PS2_PSOSIG_CLK1 4 +#define NPCX_PS2_PSOSIG_CLK2 5 +#define NPCX_PS2_PSOSIG_WDAT3 6 +#define NPCX_PS2_PSOSIG_CLK3 7 +#define NPCX_PS2_PSOSIG_CLK(n) (((n) < NPCX_PS2_CH3) ? ((n) + 3) : 7) +#define NPCX_PS2_PSOSIG_WDAT(n) (((n) < NPCX_PS2_CH3) ? ((n) + 0) : 6) +#define NPCX_PS2_PSOSIG_CLK_MASK_ALL \ + (BIT(NPCX_PS2_PSOSIG_CLK0) | BIT(NPCX_PS2_PSOSIG_CLK1) | \ + BIT(NPCX_PS2_PSOSIG_CLK2) | BIT(NPCX_PS2_PSOSIG_CLK3)) + +#define NPCX_PS2_PSISIG_RDAT0 0 +#define NPCX_PS2_PSISIG_RDAT1 1 +#define NPCX_PS2_PSISIG_RDAT2 2 +#define NPCX_PS2_PSISIG_RCLK0 3 +#define NPCX_PS2_PSISIG_RCLK1 4 +#define NPCX_PS2_PSISIG_RCLK2 5 +#define NPCX_PS2_PSISIG_RDAT3 6 +#define NPCX_PS2_PSISIG_RCLK3 7 +#define NPCX_PS2_PSIEN_SOTIE 0 +#define NPCX_PS2_PSIEN_EOTIE 1 +#define NPCX_PS2_PSIEN_PS2_WUE 4 +#define NPCX_PS2_PSIEN_PS2_CLK_SEL 7 #ifndef CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC extern const enum gpio_signal hibernate_wake_pins[]; diff --git a/chip/npcx/rom_chip.h b/chip/npcx/rom_chip.h index bb66f95e88..44c9c1a2a4 100644 --- a/chip/npcx/rom_chip.h +++ b/chip/npcx/rom_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -42,25 +42,23 @@ enum API_RETURN_STATUS_T { /* * Macro functions of ROM api functions */ -#define ADDR_DOWNLOAD_FROM_FLASH (*(volatile uint32_t *) 0x40) +#define ADDR_DOWNLOAD_FROM_FLASH (*(volatile uint32_t *)0x40) #define download_from_flash(src_offset, dest_addr, size, sign, exe_addr, \ - status) \ - (((download_from_flash_ptr) ADDR_DOWNLOAD_FROM_FLASH) \ - (src_offset, dest_addr, size, sign, exe_addr, status)) + status) \ + (((download_from_flash_ptr)ADDR_DOWNLOAD_FROM_FLASH)( \ + src_offset, dest_addr, size, sign, exe_addr, status)) /******************************************************************************/ /* * Declarations of ROM api functions */ -typedef void (*download_from_flash_ptr) ( +typedef void (*download_from_flash_ptr)( uint32_t src_offset, /* The offset of the data to be downloaded */ - uint32_t dest_addr, /* The address of the downloaded data in the RAM*/ - uint32_t size, /* Number of bytes to download */ + uint32_t dest_addr, /* The address of the downloaded data in the RAM*/ + uint32_t size, /* Number of bytes to download */ enum API_SIGN_OPTIONS_T sign, /* Need CRC check or not */ uint32_t exe_addr, /* jump to this address after download if not zero */ enum API_RETURN_STATUS_T *status /* Status fo download */ ); - - #endif /* __CROS_EC_ROM_CHIP_H_ */ diff --git a/chip/npcx/sha256_chip.c b/chip/npcx/sha256_chip.c index 6d2d938895..e2590cad65 100644 --- a/chip/npcx/sha256_chip.c +++ b/chip/npcx/sha256_chip.c @@ -1,10 +1,11 @@ /* - * Copyright 2020 The Chromium OS Authors. All rights reserved. + * Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* SHA256 module for Chrome EC */ +#include "builtin/assert.h" #include "common.h" #include "sha256.h" #include "util.h" @@ -31,7 +32,7 @@ enum ncl_sha_type { * The base address of the table that holds the function pointer for each * SHA256 API in ROM. */ -#define NCL_SHA_BASE_ADDR 0x00000100UL +#define NCL_SHA_BASE_ADDR 0x00000100UL struct ncl_sha { /* Get the SHA context size required by SHA APIs. */ uint32_t (*get_context_size)(void); @@ -57,7 +58,8 @@ struct ncl_sha { enum ncl_status (*finish)(void *ctx, uint8_t *hashDigest); /* Perform a complete SHA calculation */ enum ncl_status (*calc)(void *ctx, enum ncl_sha_type type, - const uint8_t *data, uint32_t Len, uint8_t *hashDigest); + const uint8_t *data, uint32_t Len, + uint8_t *hashDigest); /* Power on/off the SHA module. */ enum ncl_status (*power)(void *ctx, uint8_t enable); /* Reset the SHA hardware and terminate any in-progress operations. */ @@ -95,9 +97,9 @@ uint8_t *SHA256_final(struct sha256_ctx *ctx) return ctx->buf; } -static void hmac_SHA256_step(uint8_t *output, uint8_t mask, - const uint8_t *key, const int key_len, - const uint8_t *data, const int data_len) +static void hmac_SHA256_step(uint8_t *output, uint8_t mask, const uint8_t *key, + const int key_len, const uint8_t *data, + const int data_len) { struct sha256_ctx hmac_ctx; uint8_t *key_pad = hmac_ctx.buf; @@ -120,7 +122,7 @@ static void hmac_SHA256_step(uint8_t *output, uint8_t mask, * hmac_SHA256_step. */ void hmac_SHA256(uint8_t *output, const uint8_t *key, const int key_len, - const uint8_t *message, const int message_len) + const uint8_t *message, const int message_len) { /* This code does not support key_len > block_size. */ ASSERT(key_len <= SHA256_BLOCK_SIZE); @@ -137,5 +139,5 @@ void hmac_SHA256(uint8_t *output, const uint8_t *key, const int key_len, * output = hash(o_key_pad || output) */ hmac_SHA256_step(output, 0x5c, key, key_len, output, - SHA256_DIGEST_SIZE); + SHA256_DIGEST_SIZE); } diff --git a/chip/npcx/sha256_chip.h b/chip/npcx/sha256_chip.h index 3b9586d962..3c7773d112 100644 --- a/chip/npcx/sha256_chip.h +++ b/chip/npcx/sha256_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -8,7 +8,7 @@ #include "common.h" -#define NPCX_SHA256_HANDLE_SIZE 212 +#define NPCX_SHA256_HANDLE_SIZE 212 struct sha256_ctx { /* the context handle required for SHA256 API */ uint8_t handle[NPCX_SHA256_HANDLE_SIZE]; @@ -22,4 +22,4 @@ struct sha256_ctx { void SHA256_abort(struct sha256_ctx *ctx); -#endif /* __CROS_EC_SHA256_CHIP_H */ +#endif /* __CROS_EC_SHA256_CHIP_H */ diff --git a/chip/npcx/shi.c b/chip/npcx/shi.c index 48b56d18ef..d5f19c9191 100644 --- a/chip/npcx/shi.c +++ b/chip/npcx/shi.c @@ -1,5 +1,5 @@ /* - * Copyright 2015 The Chromium OS Authors. All rights reserved. + * Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,6 +10,7 @@ * This uses Input/Output buffer to handle SPI transmission and reception. */ +#include "builtin/assert.h" #include "chipset.h" #include "clock.h" #include "console.h" @@ -24,8 +25,8 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_SPI, outstr) -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SPI, format, ##args) #if !(DEBUG_SHI) #define DEBUG_CPUTS(...) @@ -33,39 +34,42 @@ #define DEBUG_CPRINTF(...) #else #define DEBUG_CPUTS(outstr) cputs(CC_SPI, outstr) -#define DEBUG_CPRINTS(format, args...) cprints(CC_SPI, format, ## args) -#define DEBUG_CPRINTF(format, args...) cprintf(CC_SPI, format, ## args) +#define DEBUG_CPRINTS(format, args...) cprints(CC_SPI, format, ##args) +#define DEBUG_CPRINTF(format, args...) cprintf(CC_SPI, format, ##args) #endif /* SHI Bus definition */ #ifdef NPCX_SHI_V2 -#define SHI_OBUF_FULL_SIZE 128 /* Full output buffer size */ -#define SHI_IBUF_FULL_SIZE 128 /* Full input buffer size */ +#define SHI_OBUF_FULL_SIZE 128 /* Full output buffer size */ +#define SHI_IBUF_FULL_SIZE 128 /* Full input buffer size */ /* Configure the IBUFLVL2 = the size of V3 protocol header */ #define SHI_IBUFLVL2_THRESHOLD (sizeof(struct ec_host_request)) #else -#define SHI_OBUF_FULL_SIZE 64 /* Full output buffer size */ -#define SHI_IBUF_FULL_SIZE 64 /* Full input buffer size */ +#define SHI_OBUF_FULL_SIZE 64 /* Full output buffer size */ +#define SHI_IBUF_FULL_SIZE 64 /* Full input buffer size */ #endif -#define SHI_OBUF_HALF_SIZE (SHI_OBUF_FULL_SIZE/2) /* Half output buffer size */ -#define SHI_IBUF_HALF_SIZE (SHI_IBUF_FULL_SIZE/2) /* Half input buffer size */ +#define SHI_OBUF_HALF_SIZE \ + (SHI_OBUF_FULL_SIZE / 2) /* Half output buffer size */ +#define SHI_IBUF_HALF_SIZE \ + (SHI_IBUF_FULL_SIZE / 2) /* Half input buffer size */ /* Start address of SHI output buffer */ -#define SHI_OBUF_START_ADDR (volatile uint8_t *)(NPCX_SHI_BASE_ADDR + 0x020) +#define SHI_OBUF_START_ADDR (volatile uint8_t *)(NPCX_SHI_BASE_ADDR + 0x020) /* Middle address of SHI output buffer */ -#define SHI_OBUF_HALF_ADDR (SHI_OBUF_START_ADDR + SHI_OBUF_HALF_SIZE) +#define SHI_OBUF_HALF_ADDR (SHI_OBUF_START_ADDR + SHI_OBUF_HALF_SIZE) /* Top address of SHI output buffer */ -#define SHI_OBUF_FULL_ADDR (SHI_OBUF_START_ADDR + SHI_IBUF_FULL_SIZE) +#define SHI_OBUF_FULL_ADDR (SHI_OBUF_START_ADDR + SHI_IBUF_FULL_SIZE) /* * Valid offset of SHI output buffer to write. * When SIMUL bit is set, IBUFPTR can be used instead of OBUFPTR */ -#define SHI_OBUF_VALID_OFFSET ((shi_read_buf_pointer() + \ - SHI_OUT_PREAMBLE_LENGTH) % SHI_OBUF_FULL_SIZE) +#define SHI_OBUF_VALID_OFFSET \ + ((shi_read_buf_pointer() + SHI_OUT_PREAMBLE_LENGTH) % \ + SHI_OBUF_FULL_SIZE) /* Start address of SHI input buffer */ -#define SHI_IBUF_START_ADDR (&NPCX_IBUF(0)) +#define SHI_IBUF_START_ADDR (&NPCX_IBUF(0)) /* Current address of SHI input buffer */ -#define SHI_IBUF_CUR_ADDR (SHI_IBUF_START_ADDR + shi_read_buf_pointer()) +#define SHI_IBUF_CUR_ADDR (SHI_IBUF_START_ADDR + shi_read_buf_pointer()) /* * Timeout to wait for SHI request packet @@ -106,12 +110,11 @@ */ #define SHI_PROTO3_OVERHEAD (EC_SPI_PAST_END_LENGTH + EC_SPI_FRAME_START_LENGTH) - #ifdef NPCX_SHI_BYPASS_OVER_256B /* The boundary which SHI will output invalid data on MISO. */ #define SHI_BYPASS_BOUNDARY 256 /* Increase FRAME_START_LENGTH in case shi outputs invalid FRAME_START byte */ -#undef EC_SPI_FRAME_START_LENGTH +#undef EC_SPI_FRAME_START_LENGTH #define EC_SPI_FRAME_START_LENGTH 2 #endif @@ -141,10 +144,9 @@ BUILD_ASSERT(SHI_MAX_RESPONSE_SIZE <= SHI_BYPASS_BOUNDARY); */ #define SHI_OUT_START_PAD (4 * (EC_SPI_FRAME_START_LENGTH / 4 + 1)) #define SHI_OUT_END_PAD (4 * (EC_SPI_PAST_END_LENGTH / 4 + 1)) -static uint8_t out_msg_padded[SHI_OUT_START_PAD + - SHI_MAX_RESPONSE_SIZE + +static uint8_t out_msg_padded[SHI_OUT_START_PAD + SHI_MAX_RESPONSE_SIZE + SHI_OUT_END_PAD] __aligned(4); -static uint8_t * const out_msg = +static uint8_t *const out_msg = out_msg_padded + SHI_OUT_START_PAD - EC_SPI_FRAME_START_LENGTH; static uint8_t in_msg[SHI_MAX_REQUEST_SIZE] __aligned(4); @@ -176,18 +178,18 @@ volatile enum shi_state state; /* SHI bus parameters */ struct shi_bus_parameters { - uint8_t *rx_msg; /* Entry pointer of msg rx buffer */ - uint8_t *tx_msg; /* Entry pointer of msg tx buffer */ + uint8_t *rx_msg; /* Entry pointer of msg rx buffer */ + uint8_t *tx_msg; /* Entry pointer of msg tx buffer */ volatile uint8_t *rx_buf; /* Entry pointer of receive buffer */ volatile uint8_t *tx_buf; /* Entry pointer of transmit buffer */ - uint16_t sz_received; /* Size of received data in bytes */ - uint16_t sz_sending; /* Size of sending data in bytes */ - uint16_t sz_request; /* request bytes need to receive */ - uint16_t sz_response; /* response bytes need to receive */ - timestamp_t rx_deadline; /* deadline of receiving */ - uint8_t pre_ibufstat; /* Previous IBUFSTAT value */ + uint16_t sz_received; /* Size of received data in bytes */ + uint16_t sz_sending; /* Size of sending data in bytes */ + uint16_t sz_request; /* request bytes need to receive */ + uint16_t sz_response; /* response bytes need to receive */ + timestamp_t rx_deadline; /* deadline of receiving */ + uint8_t pre_ibufstat; /* Previous IBUFSTAT value */ #ifdef NPCX_SHI_BYPASS_OVER_256B - uint16_t bytes_in_256b; /* Sent bytes in 256 bytes boundary */ + uint16_t bytes_in_256b; /* Sent bytes in 256 bytes boundary */ #endif } shi_params; @@ -222,7 +224,7 @@ static void shi_send_response_packet(struct host_packet *pkt) interrupt_disable(); if (state == SHI_STATE_PROCESSING) { /* Append our past-end byte, which we reserved space for. */ - ((uint8_t *) pkt->response)[pkt->response_size + 0] = + ((uint8_t *)pkt->response)[pkt->response_size + 0] = EC_SPI_PAST_END; /* Computing sending bytes of response */ @@ -266,8 +268,8 @@ void shi_handle_host_package(void) /* Need to receive data from buffer */ return; else { - uint16_t remain_bytes = shi_params.sz_request - - shi_params.sz_received; + uint16_t remain_bytes = + shi_params.sz_request - shi_params.sz_received; /* Read remaining bytes from input buffer directly */ if (!shi_read_inbuf_wait(remain_bytes)) @@ -287,7 +289,6 @@ void shi_handle_host_package(void) shi_packet.request_max = sizeof(in_msg); shi_packet.request_size = shi_params.sz_request; - #ifdef NPCX_SHI_BYPASS_OVER_256B /* Move FRAME_START to second byte */ out_msg[0] = EC_SPI_PROCESSING; @@ -324,7 +325,7 @@ static void shi_parse_header(void) if (in_msg[0] == EC_HOST_REQUEST_VERSION) { /* Protocol version 3 */ - struct ec_host_request *r = (struct ec_host_request *) in_msg; + struct ec_host_request *r = (struct ec_host_request *)in_msg; int pkt_size; /* * If request is over 32 bytes, @@ -371,8 +372,8 @@ static void shi_fill_out_status(uint8_t status) * be done within this gap. No racing happens. */ start = SHI_OBUF_VALID_OFFSET; - end = ((start + SHI_OBUF_FULL_SIZE - SHI_OUT_PREAMBLE_LENGTH) - % SHI_OBUF_FULL_SIZE); + end = ((start + SHI_OBUF_FULL_SIZE - SHI_OUT_PREAMBLE_LENGTH) % + SHI_OBUF_FULL_SIZE); fill_ptr = (uint8_t *)SHI_OBUF_START_ADDR + start; fill_end = (uint8_t *)SHI_OBUF_START_ADDR + end; @@ -388,17 +389,17 @@ static void shi_fill_out_status(uint8_t status) } #ifdef NPCX_SHI_V2 - /* - * This routine configures at which level the Input Buffer Half Full 2(IBHF2)) - * event triggers an interrupt to core. - */ +/* + * This routine configures at which level the Input Buffer Half Full 2(IBHF2)) + * event triggers an interrupt to core. + */ static void shi_sec_ibf_int_enable(int enable) { if (enable) { /* Setup IBUFLVL2 threshold and enable it */ SET_BIT(NPCX_SHICFG5, NPCX_SHICFG5_IBUFLVL2DIS); SET_FIELD(NPCX_SHICFG5, NPCX_SHICFG5_IBUFLVL2, - SHI_IBUFLVL2_THRESHOLD); + SHI_IBUFLVL2_THRESHOLD); CLEAR_BIT(NPCX_SHICFG5, NPCX_SHICFG5_IBUFLVL2DIS); /* Enable IBHF2 event */ SET_BIT(NPCX_EVENABLE2, NPCX_EVENABLE2_IBHF2EN); @@ -436,9 +437,9 @@ static int shi_is_cs_glitch(void) */ static void shi_write_half_outbuf(void) { - const uint8_t size = MIN(SHI_OBUF_HALF_SIZE, - shi_params.sz_response - - shi_params.sz_sending); + const uint8_t size = + MIN(SHI_OBUF_HALF_SIZE, + shi_params.sz_response - shi_params.sz_sending); uint8_t *obuf_ptr = (uint8_t *)shi_params.tx_buf; const uint8_t *obuf_end = obuf_ptr + size; uint8_t *msg_ptr = shi_params.tx_msg; @@ -468,8 +469,8 @@ static void shi_write_first_pkg_outbuf(uint16_t szbytes) * If response package is across 256 bytes boundary, * bypass needs to extend PROCESSING bytes after reaching the boundary. */ - if (shi_params.bytes_in_256b + SHI_OBUF_FULL_SIZE + szbytes - > SHI_BYPASS_BOUNDARY) { + if (shi_params.bytes_in_256b + SHI_OBUF_FULL_SIZE + szbytes > + SHI_BYPASS_BOUNDARY) { state = SHI_STATE_WAIT_ALIGNMENT; /* Set pointer of output buffer to the start address */ shi_params.tx_buf = SHI_OBUF_START_ADDR; @@ -485,7 +486,7 @@ static void shi_write_first_pkg_outbuf(uint16_t szbytes) /* Fill up to OBUF mid point, or OBUF end */ size = MIN(SHI_OBUF_HALF_SIZE - (offset % SHI_OBUF_HALF_SIZE), - szbytes - shi_params.sz_sending); + szbytes - shi_params.sz_sending); obuf_end = obuf_ptr + size; while (obuf_ptr != obuf_end) *(obuf_ptr++) = *(msg_ptr++); @@ -520,8 +521,8 @@ static void shi_read_half_inbuf(void) /* Restore data to msg buffer */ *(shi_params.rx_msg++) = *(shi_params.rx_buf++); shi_params.sz_received++; - } while (shi_params.sz_received % SHI_IBUF_HALF_SIZE - && shi_params.sz_received != shi_params.sz_request); + } while (shi_params.sz_received % SHI_IBUF_HALF_SIZE && + shi_params.sz_received != shi_params.sz_request); } /* @@ -601,7 +602,7 @@ static void shi_handle_cs_assert(void) if (state == SHI_STATE_DISABLED) return; - /* SHI V2 module filters cs glitch by hardware automatically */ + /* SHI V2 module filters cs glitch by hardware automatically */ #ifndef NPCX_SHI_V2 /* * IBUFSTAT resets on the 7th clock cycle after CS assertion, which @@ -725,7 +726,7 @@ static void shi_int_handler(void) DEBUG_CPRINTF("CNL-"); return; - /* Next transaction but we're not ready */ + /* Next transaction but we're not ready */ } else if (state == SHI_STATE_CNL_RESP_NOT_RDY) return; @@ -754,8 +755,8 @@ static void shi_int_handler(void) return shi_handle_host_package(); } else if (state == SHI_STATE_SENDING) { /* Write data from msg buffer to output buffer */ - if (shi_params.tx_buf == SHI_OBUF_START_ADDR + - SHI_OBUF_FULL_SIZE) { + if (shi_params.tx_buf == + SHI_OBUF_START_ADDR + SHI_OBUF_FULL_SIZE) { /* Write data from bottom address again */ shi_params.tx_buf = SHI_OBUF_START_ADDR; return shi_write_half_outbuf(); @@ -770,8 +771,8 @@ static void shi_int_handler(void) * If pointer of output buffer will reach 256 bytes * boundary soon, start to fill response data. */ - if (shi_params.bytes_in_256b == SHI_BYPASS_BOUNDARY - - SHI_OBUF_FULL_SIZE) { + if (shi_params.bytes_in_256b == + SHI_BYPASS_BOUNDARY - SHI_OBUF_FULL_SIZE) { state = SHI_STATE_SENDING; DEBUG_CPRINTF("SND-"); return shi_write_half_outbuf(); @@ -805,8 +806,9 @@ static void shi_int_handler(void) if (IS_BIT_SET(stat_reg, NPCX_EVSTAT_IBF)) { #ifdef NPCX_SHI_BYPASS_OVER_256B /* Record the sent bytes within 256B boundary */ - shi_params.bytes_in_256b = (shi_params.bytes_in_256b + - SHI_OBUF_FULL_SIZE) % SHI_BYPASS_BOUNDARY; + shi_params.bytes_in_256b = + (shi_params.bytes_in_256b + SHI_OBUF_FULL_SIZE) % + SHI_BYPASS_BOUNDARY; #endif if (state == SHI_STATE_RECEIVING) { /* read data from input to msg buffer */ @@ -816,16 +818,16 @@ static void shi_int_handler(void) return shi_handle_host_package(); } else if (state == SHI_STATE_SENDING) /* Write data from msg buffer to output buffer */ - if (shi_params.tx_buf == SHI_OBUF_START_ADDR + - SHI_OBUF_HALF_SIZE) + if (shi_params.tx_buf == + SHI_OBUF_START_ADDR + SHI_OBUF_HALF_SIZE) return shi_write_half_outbuf(); else /* ignore it */ return; else if (state == SHI_STATE_PROCESSING #ifdef NPCX_SHI_BYPASS_OVER_256B - || state == SHI_STATE_WAIT_ALIGNMENT + || state == SHI_STATE_WAIT_ALIGNMENT #endif - ) + ) /* Wait for host handles request */ return; else @@ -850,7 +852,6 @@ void shi_cs_event(enum gpio_signal signal) #else shi_handle_cs_assert(); #endif - } /*****************************************************************************/ @@ -960,9 +961,7 @@ static void shi_reenable_on_sysjump(void) shi_enable(); } /* Call hook after chipset sets initial power state */ -DECLARE_HOOK(HOOK_INIT, - shi_reenable_on_sysjump, - HOOK_PRIO_POST_CHIPSET); +DECLARE_HOOK(HOOK_INIT, shi_reenable_on_sysjump, HOOK_PRIO_POST_CHIPSET); /* Disable SHI bus */ static void shi_disable(void) @@ -1079,4 +1078,4 @@ static enum ec_status shi_get_protocol_info(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, shi_get_protocol_info, -EC_VER_MASK(0)); + EC_VER_MASK(0)); diff --git a/chip/npcx/shi_chip.h b/chip/npcx/shi_chip.h index 3fd73e8119..9d41a2dcab 100644 --- a/chip/npcx/shi_chip.h +++ b/chip/npcx/shi_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/npcx/sib.c b/chip/npcx/sib.c index 424048518e..e8dbd5039d 100644 --- a/chip/npcx/sib.c +++ b/chip/npcx/sib.c @@ -1,5 +1,5 @@ /* - * Copyright 2019 The Chromium OS Authors. All rights reserved. + * Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -28,7 +28,7 @@ /* Console output macros */ #ifdef DEBUG_SIB #define CPUTS(outstr) cputs(CC_SYSTEM, outstr) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) #else #define CPUTS(...) #define CPRINTS(...) @@ -110,8 +110,7 @@ uint8_t sib_read_kbc_reg(uint8_t io_offset) } /* Super-IO read/write function */ -void sib_write_reg(uint8_t io_offset, uint8_t index_value, - uint8_t io_data) +void sib_write_reg(uint8_t io_offset, uint8_t index_value, uint8_t io_data) { /* Disable interrupts */ interrupt_disable(); @@ -132,7 +131,7 @@ void sib_write_reg(uint8_t io_offset, uint8_t index_value, sib_wait_host_write_done(); /* Specify the io_offset A0 = 1. the data register is accessed */ - NPCX_IHIOA = io_offset+1; + NPCX_IHIOA = io_offset + 1; /* Write the data. This starts the write access to the host module */ NPCX_IHD = io_data; /* Wait while Core write operation is in progress */ @@ -170,7 +169,7 @@ uint8_t sib_read_reg(uint8_t io_offset, uint8_t index_value) sib_wait_host_write_done(); /* Specify the io_offset A0 = 1. the data register is accessed */ - NPCX_IHIOA = io_offset+1; + NPCX_IHIOA = io_offset + 1; /* Start a Core read from host module */ SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSRD); /* Wait while Core read operation is in progress */ diff --git a/chip/npcx/sib_chip.h b/chip/npcx/sib_chip.h index 1687c90925..570fe6b0ec 100644 --- a/chip/npcx/sib_chip.h +++ b/chip/npcx/sib_chip.h @@ -1,5 +1,5 @@ /* - * Copyright 2019 The Chromium OS Authors. All rights reserved. + * Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -7,15 +7,14 @@ /* NPCX-specific SIB module for Chrome EC */ /* Super-IO index and register definitions */ -#define INDEX_SID 0x20 -#define INDEX_CHPREV 0x24 -#define INDEX_SRID 0x27 +#define INDEX_SID 0x20 +#define INDEX_CHPREV 0x24 +#define INDEX_SRID 0x27 -#define SIO_OFFSET 0x4E +#define SIO_OFFSET 0x4E /* Super-IO register write function */ -void sib_write_reg(uint8_t io_offset, uint8_t index_value, - uint8_t io_data); +void sib_write_reg(uint8_t io_offset, uint8_t index_value, uint8_t io_data); /* Super-IO register read function */ uint8_t sib_read_reg(uint8_t io_offset, uint8_t index_value); /* Emulate host to read Keyboard I/O */ diff --git a/chip/npcx/spi.c b/chip/npcx/spi.c index 55fa8f85ab..0161ce63ef 100644 --- a/chip/npcx/spi.c +++ b/chip/npcx/spi.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -22,11 +22,11 @@ #define CPRINTS(...) #else #define CPUTS(outstr) cputs(CC_SPI, outstr) -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args) #endif /* SPI IP as SPI controller */ -#define SPI_CLK 8000000 +#define SPI_CLK 8000000 /** * Clear SPI data buffer. * @@ -49,19 +49,20 @@ static void clear_databuf(void) */ void spi_freq_changed(void) { - uint8_t prescaler_divider = 0; + uint8_t prescaler_divider = 0; /* Set clock prescaler divider to SPI module*/ - prescaler_divider = (uint8_t)((uint32_t)clock_get_apb2_freq() - / 2 / SPI_CLK); + prescaler_divider = + (uint8_t)((uint32_t)clock_get_apb2_freq() / 2 / SPI_CLK); if (prescaler_divider >= 1) prescaler_divider = prescaler_divider - 1; if (prescaler_divider > 0x7F) prescaler_divider = 0x7F; /* Set core clock division factor in order to obtain the SPI clock */ - NPCX_SPI_CTL1 = (NPCX_SPI_CTL1&(~(((1<<7)-1)<<NPCX_SPI_CTL1_SCDV))) - |(prescaler_divider<<NPCX_SPI_CTL1_SCDV); + NPCX_SPI_CTL1 = + (NPCX_SPI_CTL1 & (~(((1 << 7) - 1) << NPCX_SPI_CTL1_SCDV))) | + (prescaler_divider << NPCX_SPI_CTL1_SCDV); } DECLARE_HOOK(HOOK_FREQ_CHANGE, spi_freq_changed, HOOK_PRIO_FIRST); @@ -105,7 +106,6 @@ int spi_enable(const struct spi_device_t *spi_device, int enable) return EC_SUCCESS; } - /** * Flush an SPI transaction and receive data from peripheral. * @@ -118,8 +118,8 @@ int spi_enable(const struct spi_device_t *spi_device, int enable) * @notes set controller transaction mode in npcx chip */ int spi_transaction(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) + const uint8_t *txdata, int txlen, uint8_t *rxdata, + int rxlen) { int i = 0; enum gpio_signal gpio = spi_device->gpio_cs; @@ -143,7 +143,7 @@ int spi_transaction(const struct spi_device_t *spi_device, while (IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_BSY)) ; /* Write the data */ - NPCX_SPI_DATA = txdata[i]; + NPCX_SPI_DATA = txdata[i]; CPRINTS("txdata[i]=%x", txdata[i]); /* Waiting till reading is finished */ while (!IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_RBF)) @@ -158,7 +158,7 @@ int spi_transaction(const struct spi_device_t *spi_device, while (IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_BSY)) ; /* Write the (unused) data */ - NPCX_SPI_DATA = 0; + NPCX_SPI_DATA = 0; /* Wait till reading is finished */ while (!IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_RBF)) ; @@ -184,7 +184,7 @@ static void spi_init(void) int i; /* Enable clock for SPI peripheral */ clock_enable_peripheral(CGC_OFFSET_SPI, CGC_SPI_MASK, - CGC_MODE_RUN | CGC_MODE_SLEEP); + CGC_MODE_RUN | CGC_MODE_SLEEP); /* Disabling spi module */ for (i = 0; i < spi_devices_used; i++) @@ -205,8 +205,8 @@ static void spi_init(void) CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_SCIDL); CPRINTS("nSPI_COMP=%x", IS_BIT_SET(NPCX_STRPST, NPCX_STRPST_SPI_COMP)); - CPRINTS("SPI_SP_SEL=%x", IS_BIT_SET(NPCX_DEV_CTL4, - NPCX_DEV_CTL4_SPI_SP_SEL)); + CPRINTS("SPI_SP_SEL=%x", + IS_BIT_SET(NPCX_DEV_CTL4, NPCX_DEV_CTL4_SPI_SP_SEL)); /* Cleaning junk data in the buffer */ clear_databuf(); } @@ -216,7 +216,7 @@ DECLARE_HOOK(HOOK_INIT, spi_init, HOOK_PRIO_INIT_SPI); /* Console commands */ #ifdef CONFIG_CMD_SPI_FLASH static int printrx(const char *desc, const uint8_t *txdata, int txlen, - int rxlen) + int rxlen) { uint8_t rxdata[32]; int rv; @@ -233,13 +233,13 @@ static int printrx(const char *desc, const uint8_t *txdata, int txlen, return EC_SUCCESS; } -static int command_spirom(int argc, char **argv) +static int command_spirom(int argc, const char **argv) { - uint8_t txmandev[] = {0x90, 0x00, 0x00, 0x00}; - uint8_t txjedec[] = {0x9f}; - uint8_t txunique[] = {0x4b, 0x00, 0x00, 0x00, 0x00}; - uint8_t txsr1[] = {0x05}; - uint8_t txsr2[] = {0x35}; + uint8_t txmandev[] = { 0x90, 0x00, 0x00, 0x00 }; + uint8_t txjedec[] = { 0x9f }; + uint8_t txunique[] = { 0x4b, 0x00, 0x00, 0x00, 0x00 }; + uint8_t txsr1[] = { 0x05 }; + uint8_t txsr2[] = { 0x35 }; spi_enable(SPI_FLASH_DEVICE, 1); @@ -253,7 +253,6 @@ static int command_spirom(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(spirom, command_spirom, - NULL, - "Test reading SPI EEPROM"); +DECLARE_CONSOLE_COMMAND(spirom, command_spirom, NULL, + "Test reading SPI EEPROM"); #endif diff --git a/chip/npcx/spiflashfw/monitor_hdr.c b/chip/npcx/spiflashfw/monitor_hdr.c index 219a037d27..09606c4c31 100644 --- a/chip/npcx/spiflashfw/monitor_hdr.c +++ b/chip/npcx/spiflashfw/monitor_hdr.c @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -20,7 +20,7 @@ const struct monitor_header_tag monitor_hdr = { * programed into the SPI flash. */ CONFIG_PROGRAM_MEMORY_BASE, - /* 0x0C:The Flash start address to be programmed*/ +/* 0x0C:The Flash start address to be programmed*/ #ifdef SECTION_IS_RO /* Default: RO image is programed from the start of SPI flash */ CONFIG_EC_PROTECTED_STORAGE_OFF, diff --git a/chip/npcx/spiflashfw/npcx_monitor.c b/chip/npcx/spiflashfw/npcx_monitor.c index f22037f8de..5b7a767992 100644 --- a/chip/npcx/spiflashfw/npcx_monitor.c +++ b/chip/npcx/spiflashfw/npcx_monitor.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -49,7 +49,7 @@ void sspi_flash_execute_cmd(uint8_t code, uint8_t cts) /* set UMA_CODE */ NPCX_UMA_CODE = code; /* execute UMA flash transaction */ - NPCX_UMA_CTS = cts; + NPCX_UMA_CTS = cts; while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE)) ; } @@ -76,7 +76,7 @@ void sspi_flash_wait_ready(void) sspi_flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_ONLY); do { /* Read status register */ - NPCX_UMA_CTS = MASK_RD_1BYTE; + NPCX_UMA_CTS = MASK_RD_1BYTE; while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE)) ; } while (NPCX_UMA_DB0 & mask); /* Wait for Busy clear */ @@ -108,7 +108,7 @@ void sspi_flash_set_address(uint32_t dest_addr) } void sspi_flash_burst_write(unsigned int dest_addr, unsigned int bytes, - const char *data) + const char *data) { unsigned int i; /* Chip Select down. */ @@ -197,7 +197,7 @@ void sspi_flash_physical_erase(int offset, int size) /* Alignment has been checked in upper layer */ for (; size > 0; size -= NPCX_MONITOR_FLASH_ERASE_SIZE, - offset += NPCX_MONITOR_FLASH_ERASE_SIZE) { + offset += NPCX_MONITOR_FLASH_ERASE_SIZE) { /* Enable write */ sspi_flash_write_enable(); /* Set erase address */ @@ -221,7 +221,7 @@ int sspi_flash_verify(int offset, int size, const char *data) uint8_t cmp_data; ptr_flash = (uint8_t *)(CONFIG_MAPPED_STORAGE_BASE + offset); - ptr_mram = (uint8_t *)data; + ptr_mram = (uint8_t *)data; result = 1; /* Disable tri-state */ @@ -255,12 +255,11 @@ int sspi_flash_get_image_used(const char *fw_base) for (size--; size > 0 && image[size] != 0xea; size--) ; - return size ? size + 1 : 0; /* 0xea byte IS part of the image */ - + return size ? size + 1 : 0; /* 0xea byte IS part of the image */ } /* Entry function of spi upload function */ -uint32_t __attribute__ ((section(".startup_text"))) +uint32_t __attribute__((section(".startup_text"))) sspi_flash_upload(int spi_offset, int spi_size) { /* @@ -315,7 +314,7 @@ sspi_flash_upload(int spi_offset, int spi_size) /* Start to write */ if (image_base != NULL) sspi_flash_physical_write(spi_offset, sz_image, - image_base); + image_base); /* Verify data */ if (sspi_flash_verify(spi_offset, sz_image, image_base)) *flag_upload |= 0x02; diff --git a/chip/npcx/spiflashfw/npcx_monitor.h b/chip/npcx/spiflashfw/npcx_monitor.h index f4f30454d2..54303958d6 100644 --- a/chip/npcx/spiflashfw/npcx_monitor.h +++ b/chip/npcx/spiflashfw/npcx_monitor.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -7,11 +7,11 @@ #include <stdint.h> -#define NPCX_MONITOR_UUT_TAG 0xA5075001 -#define NPCX_MONITOR_HEADER_ADDR 0x200C3000 +#define NPCX_MONITOR_UUT_TAG 0xA5075001 +#define NPCX_MONITOR_HEADER_ADDR 0x200C3000 /* Flag to record the progress of programming SPI flash */ -#define SPI_PROGRAMMING_FLAG 0x200C4000 +#define SPI_PROGRAMMING_FLAG 0x200C4000 struct monitor_header_tag { /* offset 0x00: TAG NPCX_MONITOR_TAG */ @@ -23,9 +23,9 @@ struct monitor_header_tag { /* offset 0x0C: The Flash address to be programmed (Absolute address) */ uint32_t dest_addr; /* offset 0x10: Maximum allowable flash clock frequency */ - uint8_t max_clock; + uint8_t max_clock; /* offset 0x11: SPI Flash read mode */ - uint8_t read_mode; + uint8_t read_mode; /* offset 0x12: Reserved */ uint16_t reserved; } __packed; diff --git a/chip/npcx/spiflashfw/npcx_monitor.ld b/chip/npcx/spiflashfw/npcx_monitor.ld index ae7760c519..434945b04c 100644 --- a/chip/npcx/spiflashfw/npcx_monitor.ld +++ b/chip/npcx/spiflashfw/npcx_monitor.ld @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/chip/npcx/system-npcx5.c b/chip/npcx/system-npcx5.c index 4dd12fbae2..08aafe422d 100644 --- a/chip/npcx/system-npcx5.c +++ b/chip/npcx/system-npcx5.c @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -6,6 +6,7 @@ #include <stdnoreturn.h> /* System module driver depends on chip series for Chrome EC */ +#include "builtin/assert.h" #include "common.h" #include "console.h" #include "cpu.h" @@ -39,9 +40,9 @@ void system_mpu_config(void) CPU_MPU_CTRL = 0x7; /* Create a new MPU Region to allow execution from low-power ram */ - CPU_MPU_RNR = REGION_CHIP_RESERVED; + CPU_MPU_RNR = REGION_CHIP_RESERVED; CPU_MPU_RASR = CPU_MPU_RASR & 0xFFFFFFFE; /* Disable region */ - CPU_MPU_RBAR = CONFIG_LPRAM_BASE; /* Set region base address */ + CPU_MPU_RBAR = CONFIG_LPRAM_BASE; /* Set region base address */ /* * Set region size & attribute and enable region * [31:29] - Reserved. @@ -61,7 +62,7 @@ void system_mpu_config(void) /** * hibernate function in low power ram for npcx5 series. */ -noreturn void __keep __attribute__ ((section(".lowpower_ram"))) +noreturn void __keep __attribute__((section(".lowpower_ram"))) __enter_hibernate_in_lpram(void) { /* @@ -69,10 +70,8 @@ __enter_hibernate_in_lpram(void) * Our bypass needs stack instructions but FW will turn off main ram * later for better power consumption. */ - asm ( - "ldr r0, =0x40001800\n" - "mov sp, r0\n" - ); + asm("ldr r0, =0x40001800\n" + "mov sp, r0\n"); /* Disable Code RAM first */ SET_BIT(NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_5), NPCX_PWDWN_CTL5_MRFSH_DIS); @@ -88,13 +87,12 @@ __enter_hibernate_in_lpram(void) * wake-up from deep idle. * Workaround: Apply the same bypass of idle but don't enable interrupt. */ - asm ( - "push {r0-r5}\n" /* Save needed registers */ - "ldr r0, =0x40001600\n" /* Set r0 to Suspend RAM addr */ - "wfi\n" /* Wait for int to enter idle */ - "ldm r0, {r0-r5}\n" /* Add a delay after WFI */ - "pop {r0-r5}\n" /* Restore regs before enabling ints */ - "isb\n" /* Flush the cpu pipeline */ + asm("push {r0-r5}\n" /* Save needed registers */ + "ldr r0, =0x40001600\n" /* Set r0 to Suspend RAM addr */ + "wfi\n" /* Wait for int to enter idle */ + "ldm r0, {r0-r5}\n" /* Add a delay after WFI */ + "pop {r0-r5}\n" /* Restore regs before enabling ints */ + "isb\n" /* Flush the cpu pipeline */ ); /* RTC wake-up */ @@ -129,7 +127,7 @@ void __hibernate_npcx_series(void) { int i; void (*__hibernate_in_lpram)(void) = - (void(*)(void))(__lpram_fw_start | 0x01); + (void (*)(void))(__lpram_fw_start | 0x01); /* Enable power for the Low Power RAM */ CLEAR_BIT(NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_6), 6); @@ -140,7 +138,7 @@ void __hibernate_npcx_series(void) /* Copy the __enter_hibernate_in_lpram instructions to LPRAM */ for (i = 0; i < &__flash_lpfw_end - &__flash_lpfw_start; i++) *((uint32_t *)__lpram_fw_start + i) = - *(&__flash_lpfw_start + i); + *(&__flash_lpfw_start + i); /* execute hibernate func in LPRAM */ __hibernate_in_lpram(); @@ -148,7 +146,7 @@ void __hibernate_npcx_series(void) #ifdef CONFIG_EXTERNAL_STORAGE /* Sysjump utilities in low power ram for npcx5 series. */ -noreturn void __keep __attribute__ ((section(".lowpower_ram2"))) +noreturn void __keep __attribute__((section(".lowpower_ram2"))) __start_gdma(uint32_t exeAddr) { /* Enable GDMA now */ @@ -159,7 +157,7 @@ __start_gdma(uint32_t exeAddr) /* Wait for transfer to complete/fail */ while (!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_TC) && - !IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR)) + !IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR)) ; /* Disable GDMA now */ @@ -186,7 +184,7 @@ __start_gdma(uint32_t exeAddr) /* Bypass for GMDA issue of ROM api utilities only on npcx5 series. */ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, - uint32_t size, uint32_t exeAddr) + uint32_t size, uint32_t exeAddr) { int i; uint8_t chunkSize = 16; /* 4 data burst mode. ie.16 bytes */ @@ -195,7 +193,7 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, * it's a thumb branch for cortex-m series CPU. */ void (*__start_gdma_in_lpram)(uint32_t) = - (void(*)(uint32_t))(__lpram_lfw_start | 0x01); + (void (*)(uint32_t))(__lpram_lfw_start | 0x01); /* * Before enabling burst mode for better performance of GDMA, it's @@ -203,7 +201,7 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, * are 16 bytes aligned in case failure occurs. */ ASSERT((size % chunkSize) == 0 && (srcAddr % chunkSize) == 0 && - (dstAddr % chunkSize) == 0); + (dstAddr % chunkSize) == 0); /* Check valid address for jumpiing */ ASSERT(exeAddr != 0x0); @@ -253,7 +251,7 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, /* Copy the __start_gdma_in_lpram instructions to LPRAM */ for (i = 0; i < &__flash_lplfw_end - &__flash_lplfw_start; i++) *((uint32_t *)__lpram_lfw_start + i) = - *(&__flash_lplfw_start + i); + *(&__flash_lplfw_start + i); /* Start GDMA in Suspend RAM */ __start_gdma_in_lpram(exeAddr); diff --git a/chip/npcx/system-npcx7.c b/chip/npcx/system-npcx7.c index abbb6755c3..5cacbec749 100644 --- a/chip/npcx/system-npcx7.c +++ b/chip/npcx/system-npcx7.c @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -6,6 +6,7 @@ #include <stdnoreturn.h> /* System module driver depends on chip series for Chrome EC */ +#include "builtin/assert.h" #include "common.h" #include "console.h" #include "cpu.h" @@ -21,13 +22,13 @@ #include "system_chip.h" #include "rom_chip.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) /* Macros for last 32K ram block */ #define LAST_RAM_BLK ((NPCX_RAM_SIZE / (32 * 1024)) - 1) /* Higher bits are reserved and need to be masked */ -#define RAM_PD_MASK (~BIT(LAST_RAM_BLK)) +#define RAM_PD_MASK (~BIT(LAST_RAM_BLK)) /*****************************************************************************/ /* IC specific low-level driver depends on chip series */ @@ -83,11 +84,11 @@ void system_enter_psl_mode(void) NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_PSL; #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9 - /* - * If pulse mode is enabled, the VCC power is turned off by the - * external component (Ex: PMIC) but PSL_OUT. So we can just return - * here. - */ + /* + * If pulse mode is enabled, the VCC power is turned off by the + * external component (Ex: PMIC) but PSL_OUT. So we can just return + * here. + */ if (IS_BIT_SET(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_PLS_EN)) return; #endif @@ -113,8 +114,7 @@ static void system_psl_type_sel(enum psl_pin_t psl_pin, uint32_t flags) /* Set PSL input events' type as level or edge trigger */ if ((flags & GPIO_INT_F_HIGH) || (flags & GPIO_INT_F_LOW)) CLEAR_BIT(NPCX_GLUE_PSL_CTS, psl_pin + 4); - else if ((flags & GPIO_INT_F_RISING) || - (flags & GPIO_INT_F_FALLING)) + else if ((flags & GPIO_INT_F_RISING) || (flags & GPIO_INT_F_FALLING)) SET_BIT(NPCX_GLUE_PSL_CTS, psl_pin + 4); /* @@ -145,7 +145,7 @@ int system_config_psl_mode(enum gpio_signal signal) * Hibernate function in last 32K ram block for npcx7 series. * Do not use global variable since we also turn off data ram. */ -noreturn void __keep __attribute__ ((section(".after_init"))) +noreturn void __keep __attribute__((section(".after_init"))) __enter_hibernate_in_last_block(void) { /* @@ -164,7 +164,7 @@ __enter_hibernate_in_last_block(void) NPCX_PMCSR = 0x6; /* Enter deep idle, wake-up by GPIOs or RTC */ - asm volatile ("wfi"); + asm volatile("wfi"); /* RTC wake-up */ if (IS_BIT_SET(NPCX_WTC, NPCX_WTC_PTO)) @@ -208,8 +208,8 @@ void __hibernate_npcx_series(void) __enter_hibernate_in_psl(); #else /* Make sure this is located in the last 32K code RAM block */ - ASSERT((uint32_t)(&__after_init_end) - CONFIG_PROGRAM_MEMORY_BASE - < (32*1024)); + ASSERT((uint32_t)(&__after_init_end) - CONFIG_PROGRAM_MEMORY_BASE < + (32 * 1024)); /* Execute hibernate func in last 32K block */ __enter_hibernate_in_last_block(); diff --git a/chip/npcx/system-npcx9.c b/chip/npcx/system-npcx9.c index 48088614a0..5cacbec749 120000..100644 --- a/chip/npcx/system-npcx9.c +++ b/chip/npcx/system-npcx9.c @@ -1 +1,231 @@ -system-npcx7.c
\ No newline at end of file +/* Copyright 2017 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <stdnoreturn.h> + +/* System module driver depends on chip series for Chrome EC */ +#include "builtin/assert.h" +#include "common.h" +#include "console.h" +#include "cpu.h" +#include "ec_commands.h" +#include "hooks.h" +#include "lct_chip.h" +#include "registers.h" +#include "system.h" +#include "task.h" +#include "util.h" +#include "gpio.h" +#include "hwtimer_chip.h" +#include "system_chip.h" +#include "rom_chip.h" + +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) + +/* Macros for last 32K ram block */ +#define LAST_RAM_BLK ((NPCX_RAM_SIZE / (32 * 1024)) - 1) +/* Higher bits are reserved and need to be masked */ +#define RAM_PD_MASK (~BIT(LAST_RAM_BLK)) + +/*****************************************************************************/ +/* IC specific low-level driver depends on chip series */ + +void system_mpu_config(void) +{ +} + +#ifdef CONFIG_HIBERNATE_PSL +#ifndef NPCX_PSL_MODE_SUPPORT +#error "Do not enable CONFIG_HIBERNATE_PSL if npcx ec doesn't support PSL mode!" +#endif + +static enum psl_pin_t system_gpio_to_psl(enum gpio_signal signal) +{ + enum psl_pin_t psl_no; + const struct gpio_info *g = gpio_list + signal; + + if (g->port == GPIO_PORT_D && g->mask == MASK_PIN2) /* GPIOD2 */ + psl_no = PSL_IN1; + else if (g->port == GPIO_PORT_0 && (g->mask & 0x07)) /* GPIO00/01/02 */ + psl_no = GPIO_MASK_TO_NUM(g->mask) + 1; + else + psl_no = PSL_NONE; + + return psl_no; +} + +#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9 +void system_set_psl_gpo(int level) +{ + if (level) + SET_BIT(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_PSL_GPO_CTL); + else + CLEAR_BIT(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_PSL_GPO_CTL); +} +#endif + +void system_enter_psl_mode(void) +{ + /* Configure pins from GPIOs to PSL which rely on VSBY power rail. */ + gpio_config_module(MODULE_PMU, 1); + + /* + * In npcx7, only physical PSL_IN pins can pull PSL_OUT to high and + * reboot ec. + * In npcx9, LCT timeout event can also pull PSL_OUT. + * We won't decide the wake cause now but only mark we are entering + * hibernation via PSL. + * The actual wakeup cause will be checked by the PSL input event bits + * when ec reboots. + */ + NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_PSL; + +#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9 + /* + * If pulse mode is enabled, the VCC power is turned off by the + * external component (Ex: PMIC) but PSL_OUT. So we can just return + * here. + */ + if (IS_BIT_SET(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_PLS_EN)) + return; +#endif + + /* + * Pull PSL_OUT (GPIO85) to low to cut off ec's VCC power rail by + * setting bit 5 of PDOUT(8). + */ + SET_BIT(NPCX_PDOUT(GPIO_PORT_8), 5); +} + +/* Hibernate function implemented by PSL (Power Switch Logic) mode. */ +noreturn void __keep __enter_hibernate_in_psl(void) +{ + system_enter_psl_mode(); + /* Spin and wait for PSL cuts power; should never return */ + while (1) + ; +} + +static void system_psl_type_sel(enum psl_pin_t psl_pin, uint32_t flags) +{ + /* Set PSL input events' type as level or edge trigger */ + if ((flags & GPIO_INT_F_HIGH) || (flags & GPIO_INT_F_LOW)) + CLEAR_BIT(NPCX_GLUE_PSL_CTS, psl_pin + 4); + else if ((flags & GPIO_INT_F_RISING) || (flags & GPIO_INT_F_FALLING)) + SET_BIT(NPCX_GLUE_PSL_CTS, psl_pin + 4); + + /* + * Set PSL input events' polarity is low (high-to-low) active or + * high (low-to-high) active + */ + if (flags & GPIO_HIB_WAKE_HIGH) + SET_BIT(NPCX_DEVALT(ALT_GROUP_D), 2 * psl_pin); + else + CLEAR_BIT(NPCX_DEVALT(ALT_GROUP_D), 2 * psl_pin); +} + +int system_config_psl_mode(enum gpio_signal signal) +{ + enum psl_pin_t psl_no; + const struct gpio_info *g = gpio_list + signal; + + psl_no = system_gpio_to_psl(signal); + if (psl_no == PSL_NONE) + return 0; + + system_psl_type_sel(psl_no, g->flags); + return 1; +} + +#else +/** + * Hibernate function in last 32K ram block for npcx7 series. + * Do not use global variable since we also turn off data ram. + */ +noreturn void __keep __attribute__((section(".after_init"))) +__enter_hibernate_in_last_block(void) +{ + /* + * The hibernate utility is located in the last block of RAM. The size + * of each RAM block is 32KB. We turn off all blocks except last one + * for better power consumption. + */ + NPCX_RAM_PD(0) = RAM_PD_MASK & 0xFF; +#if defined(CHIP_FAMILY_NPCX7) + NPCX_RAM_PD(1) = (RAM_PD_MASK >> 8) & 0x0F; +#elif defined(CHIP_FAMILY_NPCX9) + NPCX_RAM_PD(1) = (RAM_PD_MASK >> 8) & 0x7F; +#endif + + /* Set deep idle mode */ + NPCX_PMCSR = 0x6; + + /* Enter deep idle, wake-up by GPIOs or RTC */ + asm volatile("wfi"); + + /* RTC wake-up */ + if (IS_BIT_SET(NPCX_WTC, NPCX_WTC_PTO)) + /* + * Mark wake-up reason for hibernate + * Do not call bbram_data_write directly cause of + * no stack. + */ + NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_MTC; +#ifdef NPCX_LCT_SUPPORT + else if (IS_BIT_SET(NPCX_LCTSTAT, NPCX_LCTSTAT_EVST)) { + NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_LCT; + /* Clear LCT event */ + NPCX_LCTSTAT = BIT(NPCX_LCTSTAT_EVST); + } +#endif + else + /* Otherwise, we treat it as GPIOs wake-up */ + NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_PIN; + + /* Start a watchdog reset */ + NPCX_WDCNT = 0x01; + /* Reload and restart Timer 0 */ + SET_BIT(NPCX_T0CSR, NPCX_T0CSR_RST); + /* Wait for timer is loaded and restart */ + while (IS_BIT_SET(NPCX_T0CSR, NPCX_T0CSR_RST)) + ; + + /* Spin and wait for reboot; should never return */ + while (1) + ; +} +#endif + +/** + * Hibernate function for different Nuvoton chip series. + */ +void __hibernate_npcx_series(void) +{ +#ifdef CONFIG_HIBERNATE_PSL + __enter_hibernate_in_psl(); +#else + /* Make sure this is located in the last 32K code RAM block */ + ASSERT((uint32_t)(&__after_init_end) - CONFIG_PROGRAM_MEMORY_BASE < + (32 * 1024)); + + /* Execute hibernate func in last 32K block */ + __enter_hibernate_in_last_block(); +#endif +} + +#if defined(CONFIG_HIBERNATE_PSL) +static void report_psl_wake_source(void) +{ + if (!(system_get_reset_flags() & EC_RESET_FLAG_HIBERNATE)) + return; + + CPRINTS("PSL_CTS: 0x%x", NPCX_GLUE_PSL_CTS & 0xf); +#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9 + CPRINTS("PSL_MCTL1 event: 0x%x", NPCX_GLUE_PSL_MCTL1 & 0x18); +#endif +} +DECLARE_HOOK(HOOK_INIT, report_psl_wake_source, HOOK_PRIO_DEFAULT); +#endif diff --git a/chip/npcx/system.c b/chip/npcx/system.c index 4a2450ee5f..958d873401 100644 --- a/chip/npcx/system.c +++ b/chip/npcx/system.c @@ -1,10 +1,11 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* System module for Chrome EC : NPCX hardware specific implementation */ +#include "builtin/assert.h" #include "clock.h" #include "clock_chip.h" #include "common.h" @@ -15,6 +16,7 @@ #include "host_command.h" #include "hwtimer_chip.h" #include "lct_chip.h" +#include "panic.h" #include "registers.h" #include "rom_chip.h" #include "sib_chip.h" @@ -27,27 +29,27 @@ /* Delay after writing TTC for value to latch */ #define MTC_TTC_LOAD_DELAY_US 250 -#define MTC_ALARM_MASK (BIT(25) - 1) -#define MTC_WUI_GROUP MIWU_GROUP_4 -#define MTC_WUI_MASK MASK_PIN7 +#define MTC_ALARM_MASK (BIT(25) - 1) +#define MTC_WUI_GROUP MIWU_GROUP_4 +#define MTC_WUI_MASK MASK_PIN7 /* ROM address of chip revision */ #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9 -#define CHIP_REV_ADDR 0x0000FFFC -#define CHIP_REV_STR_SIZE 12 +#define CHIP_REV_ADDR 0x0000FFFC +#define CHIP_REV_STR_SIZE 12 #define PWDWN_8_RESERVED_SET_MASK 0x30 #else -#define CHIP_REV_ADDR 0x00007FFC -#define CHIP_REV_STR_SIZE 6 +#define CHIP_REV_ADDR 0x00007FFC +#define CHIP_REV_STR_SIZE 6 #endif /* Legacy SuperI/O Configuration D register offset */ -#define SIOCFD_REG_OFFSET 0x2D +#define SIOCFD_REG_OFFSET 0x2D /* Console output macros */ #define CPUTS(outstr) cputs(CC_SYSTEM, outstr) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) #if defined(NPCX_LCT_SUPPORT) /* A flag for waking up from hibernate mode by RTC overflow event */ @@ -91,8 +93,7 @@ void system_watchdog_reset(void) /* Return true if index is stored as a single byte in bbram */ static int bbram_is_byte_access(enum bbram_data_index index) { - return index == BBRM_DATA_INDEX_PD0 || - index == BBRM_DATA_INDEX_PD1 || + return index == BBRM_DATA_INDEX_PD0 || index == BBRM_DATA_INDEX_PD1 || index == BBRM_DATA_INDEX_PD2 || index == BBRM_DATA_INDEX_PANIC_FLAGS; } @@ -106,7 +107,7 @@ void system_check_bbram_on_reset(void) * dropped, print a warning message. */ if (IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_SCRATCH) || - IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_STS)) + IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_STS)) CPRINTF("VBAT drop!\n"); /* @@ -177,7 +178,7 @@ static int bbram_data_write(enum bbram_data_index index, uint32_t value) /* Write BBRAM */ NPCX_BBRAM(index) = value & 0xFF; if (bytes == 4) { - NPCX_BBRAM(index + 1) = (value >> 8) & 0xFF; + NPCX_BBRAM(index + 1) = (value >> 8) & 0xFF; NPCX_BBRAM(index + 2) = (value >> 16) & 0xFF; NPCX_BBRAM(index + 3) = (value >> 24) & 0xFF; } @@ -260,14 +261,14 @@ void system_set_rtc(uint32_t seconds) * 2. LREG1, LREG3 and LREG4 store exception, reason and info in case of * software panic. */ -#define BKUP_CFSR (BBRM_DATA_INDEX_PANIC_BKUP + 0) -#define BKUP_HFSR (BBRM_DATA_INDEX_PANIC_BKUP + 4) -#define BKUP_BFAR (BBRM_DATA_INDEX_PANIC_BKUP + 8) -#define BKUP_LREG1 (BBRM_DATA_INDEX_PANIC_BKUP + 12) -#define BKUP_LREG3 (BBRM_DATA_INDEX_PANIC_BKUP + 16) -#define BKUP_LREG4 (BBRM_DATA_INDEX_PANIC_BKUP + 20) +#define BKUP_CFSR (BBRM_DATA_INDEX_PANIC_BKUP + 0) +#define BKUP_HFSR (BBRM_DATA_INDEX_PANIC_BKUP + 4) +#define BKUP_BFAR (BBRM_DATA_INDEX_PANIC_BKUP + 8) +#define BKUP_LREG1 (BBRM_DATA_INDEX_PANIC_BKUP + 12) +#define BKUP_LREG3 (BBRM_DATA_INDEX_PANIC_BKUP + 16) +#define BKUP_LREG4 (BBRM_DATA_INDEX_PANIC_BKUP + 20) -#define BKUP_PANIC_DATA_VALID BIT(0) +#define BKUP_PANIC_DATA_VALID BIT(0) void chip_panic_data_backup(void) { @@ -336,10 +337,10 @@ static void chip_set_hib_flag(uint32_t *flags, uint32_t hib_wake_flags) #ifdef NPCX_LCT_SUPPORT if (npcx_lct_is_event_set()) { *flags |= EC_RESET_FLAG_RTC_ALARM | - EC_RESET_FLAG_HIBERNATE; + EC_RESET_FLAG_HIBERNATE; /* Is RTC overflow event? */ if (bbram_data_read(BBRM_DATA_INDEX_LCT_TIME) == - NPCX_LCT_MAX) { + NPCX_LCT_MAX) { /* * Mark it as RTC overflow event and handle it * in hook init function later for logging info. @@ -350,22 +351,21 @@ static void chip_set_hib_flag(uint32_t *flags, uint32_t hib_wake_flags) return; } #endif - *flags |= EC_RESET_FLAG_WAKE_PIN | - EC_RESET_FLAG_HIBERNATE; + *flags |= EC_RESET_FLAG_WAKE_PIN | EC_RESET_FLAG_HIBERNATE; } else { /* Hibernate via non-PSL */ #ifdef NPCX_LCT_SUPPORT if (hib_wake_flags & HIBERNATE_WAKE_LCT) { *flags |= EC_RESET_FLAG_RTC_ALARM | - EC_RESET_FLAG_HIBERNATE; + EC_RESET_FLAG_HIBERNATE; return; } #endif if (hib_wake_flags & HIBERNATE_WAKE_PIN) { *flags |= EC_RESET_FLAG_WAKE_PIN | - EC_RESET_FLAG_HIBERNATE; + EC_RESET_FLAG_HIBERNATE; } else if (hib_wake_flags & HIBERNATE_WAKE_MTC) { *flags |= EC_RESET_FLAG_RTC_ALARM | - EC_RESET_FLAG_HIBERNATE; + EC_RESET_FLAG_HIBERNATE; } } } @@ -420,9 +420,9 @@ static void check_reset_cause(void) * clear the flag so later code will * not wait for the second reset. */ - flags = - (flags & ~EC_RESET_FLAG_INITIAL_PWR) - | EC_RESET_FLAG_POWER_ON; + flags = (flags & + ~EC_RESET_FLAG_INITIAL_PWR) | + EC_RESET_FLAG_POWER_ON; else /* * No previous power-on flag, @@ -452,8 +452,8 @@ static void check_reset_cause(void) * No second reset after power-on, so * set the flags according to the restart reason. */ - flags |= reset ? EC_RESET_FLAG_RESET_PIN - : EC_RESET_FLAG_POWER_ON; + flags |= reset ? EC_RESET_FLAG_RESET_PIN : + EC_RESET_FLAG_POWER_ON; #endif } chip_save_reset_flags(chip_flags); @@ -480,7 +480,7 @@ static void check_reset_cause(void) * cause is panic reason or not. */ if (!(flags & (EC_RESET_FLAG_SOFT | EC_RESET_FLAG_HARD | - EC_RESET_FLAG_HIBERNATE))) + EC_RESET_FLAG_HIBERNATE))) flags |= EC_RESET_FLAG_WATCHDOG; /* Clear watchdog reset status initially*/ @@ -499,10 +499,10 @@ static void system_set_gpios_and_wakeup_inputs_hibernate(void) int table, i; /* Disable all MIWU inputs before entering hibernate */ - for (table = MIWU_TABLE_0 ; table < MIWU_TABLE_2 ; table++) { - for (i = 0 ; i < 8 ; i++) { + for (table = MIWU_TABLE_0; table < MIWU_TABLE_2; table++) { + for (i = 0; i < 8; i++) { /* Disable all wake-ups */ - NPCX_WKEN(table, i) = 0x00; + NPCX_WKEN(table, i) = 0x00; /* Clear all pending bits of wake-ups */ NPCX_WKPCL(table, i) = 0xFF; /* @@ -515,7 +515,7 @@ static void system_set_gpios_and_wakeup_inputs_hibernate(void) #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7 /* Disable MIWU 2 group 6 inputs which used for the additional GPIOs */ - NPCX_WKEN(MIWU_TABLE_2, MIWU_GROUP_6) = 0x00; + NPCX_WKEN(MIWU_TABLE_2, MIWU_GROUP_6) = 0x00; NPCX_WKPCL(MIWU_TABLE_2, MIWU_GROUP_6) = 0xFF; NPCX_WKINEN(MIWU_TABLE_2, MIWU_GROUP_6) = 0x00; #endif @@ -553,9 +553,9 @@ static void system_set_lct_alarm(uint32_t seconds, uint32_t microseconds) npcx_lct_config(seconds, 0, 1); task_disable_irq(NPCX_IRQ_LCT_WKINTF_2); /* Enable wake-up input sources & clear pending bit */ - NPCX_WKPCL(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK; + NPCX_WKPCL(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK; NPCX_WKINEN(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK; - NPCX_WKEN(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK; + NPCX_WKEN(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK; task_enable_irq(NPCX_IRQ_LCT_WKINTF_2); #endif npcx_lct_enable(1); @@ -628,10 +628,10 @@ void __enter_hibernate(uint32_t seconds, uint32_t microseconds) board_hibernate_late(); /* Clear all pending IRQ otherwise wfi will have no affect */ - for (i = NPCX_IRQ_0 ; i < NPCX_IRQ_COUNT ; i++) + for (i = NPCX_IRQ_0; i < NPCX_IRQ_COUNT; i++) task_clear_pending_irq(i); - /* Set the timer interrupt for wake up. */ + /* Set the timer interrupt for wake up. */ #ifdef NPCX_LCT_SUPPORT if (seconds || microseconds) { system_set_lct_alarm(seconds, microseconds); @@ -726,9 +726,9 @@ void system_set_rtc_alarm(uint32_t seconds, uint32_t microseconds) task_enable_irq(NPCX_IRQ_MTC); /* Enable wake-up input sources & clear pending bit */ - NPCX_WKPCL(MIWU_TABLE_0, MTC_WUI_GROUP) |= MTC_WUI_MASK; + NPCX_WKPCL(MIWU_TABLE_0, MTC_WUI_GROUP) |= MTC_WUI_MASK; NPCX_WKINEN(MIWU_TABLE_0, MTC_WUI_GROUP) |= MTC_WUI_MASK; - NPCX_WKEN(MIWU_TABLE_0, MTC_WUI_GROUP) |= MTC_WUI_MASK; + NPCX_WKEN(MIWU_TABLE_0, MTC_WUI_GROUP) |= MTC_WUI_MASK; } void system_reset_rtc_alarm(void) @@ -835,7 +835,7 @@ void chip_pre_init(void) } #else if (GET_FIELD(NPCX_JEN_CTL1, NPCX_JEN_CTL1_JEN_EN_FIELD) == - NPCX_JEN_CTL1_JEN_EN_ENA) { + NPCX_JEN_CTL1_JEN_EN_ENA) { SET_FIELD(NPCX_JEN_CTL1, NPCX_JEN_CTL1_JEN_EN_FIELD, NPCX_JEN_CTL1_JEN_EN_DIS); system_disable_host_sel_jtag(); @@ -871,20 +871,20 @@ void system_pre_init(void) pwdwn6 = 0x70 | #if NPCX_FAMILY_VERSION <= NPCX_FAMILY_NPCX7 - /* - * Don't set PD of ITIM6 for NPCX9 and later chips because - * they use it as the system timer. - */ - BIT(NPCX_PWDWN_CTL6_ITIM6_PD) | + /* + * Don't set PD of ITIM6 for NPCX9 and later chips because + * they use it as the system timer. + */ + BIT(NPCX_PWDWN_CTL6_ITIM6_PD) | #endif - BIT(NPCX_PWDWN_CTL6_ITIM4_PD); + BIT(NPCX_PWDWN_CTL6_ITIM4_PD); #if !defined(CONFIG_HOST_INTERFACE_ESPI) pwdwn6 |= 1 << NPCX_PWDWN_CTL6_ESPI_PD; #endif NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_6) = pwdwn6; #if defined(CHIP_FAMILY_NPCX7) -#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \ +#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \ defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \ defined(CHIP_VARIANT_NPCX7M7WC) /* Power down UART2, SMB5-7, ITIM64, and WoV */ @@ -949,34 +949,34 @@ void system_pre_init(void) * hibernation. */ SET_BIT(NPCX_GLUE_PSL_MCTL1, - NPCX_GLUE_PSL_MCTL1_VCC1_RST_PSL); + NPCX_GLUE_PSL_MCTL1_VCC1_RST_PSL); /* Disable VCC_RST Pull-Up */ SET_BIT(NPCX_DEVALT(ALT_GROUP_G), - NPCX_DEVALTG_VCC1_RST_PUD); + NPCX_DEVALTG_VCC1_RST_PUD); /* * Lock this bit itself and VCC1_RST_PSL in the * PSL_MCTL1 register to read-only. */ SET_BIT(NPCX_GLUE_PSL_MCTL2, - NPCX_GLUE_PSL_MCTL2_VCC1_RST_PSL_LK); + NPCX_GLUE_PSL_MCTL2_VCC1_RST_PSL_LK); } /* Don't set PSL_OUT to open-drain if it is the level mode */ ASSERT((opt_flag & NPCX_PSL_CFG_PSL_OUT_PULSE) || - !(opt_flag & NPCX_PSL_CFG_PSL_OUT_OD)); + !(opt_flag & NPCX_PSL_CFG_PSL_OUT_OD)); if (opt_flag & NPCX_PSL_CFG_PSL_OUT_OD) SET_BIT(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_OD_EN); else CLEAR_BIT(NPCX_GLUE_PSL_MCTL1, - NPCX_GLUE_PSL_MCTL1_OD_EN); + NPCX_GLUE_PSL_MCTL1_OD_EN); if (opt_flag & NPCX_PSL_CFG_PSL_OUT_PULSE) SET_BIT(NPCX_GLUE_PSL_MCTL1, - NPCX_GLUE_PSL_MCTL1_PLS_EN); + NPCX_GLUE_PSL_MCTL1_PLS_EN); else CLEAR_BIT(NPCX_GLUE_PSL_MCTL1, - NPCX_GLUE_PSL_MCTL1_PLS_EN); + NPCX_GLUE_PSL_MCTL1_PLS_EN); } #endif } @@ -1027,7 +1027,7 @@ const char *system_get_chip_vendor(void) case 0x20: return "Nuvoton"; default: - *p = system_to_hex(fam_id >> 4); + *p = system_to_hex(fam_id >> 4); *(p + 1) = system_to_hex(fam_id); *(p + 2) = '\0'; return str; @@ -1070,7 +1070,7 @@ const char *system_get_chip_name(void) return "NPCX993F"; #endif default: - *p = system_to_hex(chip_id >> 4); + *p = system_to_hex(chip_id >> 4); *(p + 1) = system_to_hex(chip_id); *(p + 2) = '\0'; return str; @@ -1106,7 +1106,7 @@ const char *system_get_chip_revision(void) break; case 0x07: if (chip_id == NPCX796F_A_B_CHIP_ID || - chip_id == NPCX797W_B_CHIP_ID) + chip_id == NPCX797W_B_CHIP_ID) *p++ = 'B'; else *p++ = 'C'; @@ -1188,7 +1188,7 @@ static void system_init_check_rtc_wakeup_event(void) * also supported, determine whether ec is woken up by RTC with overflow * event (16 weeks). If so, let it go to hibernate mode immediately. */ - if (is_rtc_overflow_event){ + if (is_rtc_overflow_event) { CPRINTS("Hibernate due to RTC overflow event"); system_hibernate(0, 0); } @@ -1207,7 +1207,7 @@ void print_system_rtc(enum console_channel ch) } #ifdef CONFIG_CMD_RTC -static int command_system_rtc(int argc, char **argv) +static int command_system_rtc(int argc, const char **argv) { if (argc == 3 && !strcasecmp(argv[1], "set")) { char *e; @@ -1224,15 +1224,14 @@ static int command_system_rtc(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc, - "[set <seconds>]", - "Get/set real-time clock"); +DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc, "[set <seconds>]", + "Get/set real-time clock"); #ifdef CONFIG_CMD_RTC_ALARM /** * Test the RTC alarm by setting an interrupt on RTC match. */ -static int command_rtc_alarm_test(int argc, char **argv) +static int command_rtc_alarm_test(int argc, const char **argv) { int s = 1, us = 0; char *e; @@ -1244,13 +1243,11 @@ static int command_rtc_alarm_test(int argc, char **argv) s = strtoi(argv[1], &e, 10); if (*e) return EC_ERROR_PARAM1; - } if (argc > 2) { us = strtoi(argv[2], &e, 10); if (*e) return EC_ERROR_PARAM2; - } system_set_rtc_alarm(s, us); @@ -1258,8 +1255,7 @@ static int command_rtc_alarm_test(int argc, char **argv) return EC_SUCCESS; } DECLARE_CONSOLE_COMMAND(rtc_alarm, command_rtc_alarm_test, - "[seconds [microseconds]]", - "Test alarm"); + "[seconds [microseconds]]", "Test alarm"); #endif /* CONFIG_CMD_RTC_ALARM */ #endif /* CONFIG_CMD_RTC */ @@ -1276,9 +1272,8 @@ static enum ec_status system_rtc_get_value(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE, - system_rtc_get_value, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE, system_rtc_get_value, + EC_VER_MASK(0)); static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args) { @@ -1287,9 +1282,8 @@ static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args) system_set_rtc(p->time); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE, - system_rtc_set_value, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE, system_rtc_set_value, + EC_VER_MASK(0)); static enum ec_status system_rtc_set_alarm(struct host_cmd_handler_args *args) { @@ -1298,9 +1292,8 @@ static enum ec_status system_rtc_set_alarm(struct host_cmd_handler_args *args) system_set_rtc_alarm(p->time, 0); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_ALARM, - system_rtc_set_alarm, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_ALARM, system_rtc_set_alarm, + EC_VER_MASK(0)); static enum ec_status system_rtc_get_alarm(struct host_cmd_handler_args *args) { @@ -1311,9 +1304,8 @@ static enum ec_status system_rtc_get_alarm(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_ALARM, - system_rtc_get_alarm, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_ALARM, system_rtc_get_alarm, + EC_VER_MASK(0)); #endif /* CONFIG_HOSTCMD_RTC */ #ifdef CONFIG_EXTERNAL_STORAGE @@ -1330,28 +1322,28 @@ void system_jump_to_booter(void) */ switch (system_get_shrspi_image_copy()) { case EC_IMAGE_RW: - flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF + - CONFIG_RW_STORAGE_OFF; + flash_offset = + CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF; flash_used = CONFIG_RW_SIZE; break; #ifdef CONFIG_RW_B case EC_IMAGE_RW_B: flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF + - CONFIG_RW_B_STORAGE_OFF; + CONFIG_RW_B_STORAGE_OFF; flash_used = CONFIG_RW_SIZE; break; #endif case EC_IMAGE_RO: default: /* Jump to RO by default */ - flash_offset = CONFIG_EC_PROTECTED_STORAGE_OFF + - CONFIG_RO_STORAGE_OFF; + flash_offset = + CONFIG_EC_PROTECTED_STORAGE_OFF + CONFIG_RO_STORAGE_OFF; flash_used = CONFIG_RO_SIZE; break; } /* Make sure the reset vector is inside the destination image */ - addr_entry = *(uintptr_t *)(flash_offset + - CONFIG_MAPPED_STORAGE_BASE + 4); + addr_entry = + *(uintptr_t *)(flash_offset + CONFIG_MAPPED_STORAGE_BASE + 4); /* * Speed up FW download time by increasing clock freq of EC. It will @@ -1361,25 +1353,30 @@ void system_jump_to_booter(void) /* Bypass for GMDA issue of ROM api utilities */ #if defined(CHIP_FAMILY_NPCX5) - system_download_from_flash( - flash_offset, /* The offset of the data in spi flash */ - CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of downloaded data */ - flash_used, /* Number of bytes to download */ - addr_entry /* jump to this address after download */ + system_download_from_flash(flash_offset, /* The offset of the data in + spi flash */ + CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of + downloaded + data */ + flash_used, /* Number of bytes to download */ + addr_entry /* jump to this address after + download */ ); #else - download_from_flash( - flash_offset, /* The offset of the data in spi flash */ - CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of downloaded data */ - flash_used, /* Number of bytes to download */ - SIGN_NO_CHECK, /* Need CRC check or not */ - addr_entry, /* jump to this address after download */ - &status /* Status fo download */ + download_from_flash(flash_offset, /* The offset of the data in spi flash + */ + CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of + downloaded data */ + flash_used, /* Number of bytes to download */ + SIGN_NO_CHECK, /* Need CRC check or not */ + addr_entry, /* jump to this address after download + */ + &status /* Status fo download */ ); #endif } -uint32_t system_get_lfw_address() +uint32_t system_get_lfw_address(void) { /* * In A3 version, we don't use little FW anymore @@ -1410,7 +1407,8 @@ void system_set_image_copy(enum ec_image copy) #endif default: CPRINTS("Invalid copy (%d) is requested as a jump destination. " - "Change it to %d.", copy, EC_IMAGE_RO); + "Change it to %d.", + copy, EC_IMAGE_RO); /* Fall through to EC_IMAGE_RO */ case EC_IMAGE_RO: SET_BIT(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION); diff --git a/chip/npcx/system_chip.h b/chip/npcx/system_chip.h index 2314f1458a..2ee5f8aff0 100644 --- a/chip/npcx/system_chip.h +++ b/chip/npcx/system_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,34 +9,34 @@ #define __CROS_EC_SYSTEM_CHIP_H /* Flags for BBRM_DATA_INDEX_WAKE */ -#define HIBERNATE_WAKE_MTC BIT(0) /* MTC alarm */ -#define HIBERNATE_WAKE_PIN BIT(1) /* Wake pin */ -#define HIBERNATE_WAKE_LCT BIT(2) /* LCT alarm */ +#define HIBERNATE_WAKE_MTC BIT(0) /* MTC alarm */ +#define HIBERNATE_WAKE_PIN BIT(1) /* Wake pin */ +#define HIBERNATE_WAKE_LCT BIT(2) /* LCT alarm */ /* * Indicate that EC enters hibernation via PSL. When EC wakes up from * hibernation and this flag is set, it will check the related status bit to * know the actual wake up source. (From LCT or physical wakeup pins) */ -#define HIBERNATE_WAKE_PSL BIT(3) +#define HIBERNATE_WAKE_PSL BIT(3) /* Indices for battery-backed ram (BBRAM) data position */ enum bbram_data_index { - BBRM_DATA_INDEX_SCRATCHPAD = 0, /* General-purpose scratchpad */ + BBRM_DATA_INDEX_SCRATCHPAD = 0, /* General-purpose scratchpad */ BBRM_DATA_INDEX_SAVED_RESET_FLAGS = 4, /* Saved reset flags */ - BBRM_DATA_INDEX_WAKE = 8, /* Wake reasons for hibernate */ - BBRM_DATA_INDEX_PD0 = 12, /* USB-PD saved port0 state */ - BBRM_DATA_INDEX_PD1 = 13, /* USB-PD saved port1 state */ - BBRM_DATA_INDEX_TRY_SLOT = 14, /* Vboot EC try slot */ - BBRM_DATA_INDEX_PD2 = 15, /* USB-PD saved port2 state */ + BBRM_DATA_INDEX_WAKE = 8, /* Wake reasons for hibernate */ + BBRM_DATA_INDEX_PD0 = 12, /* USB-PD saved port0 state */ + BBRM_DATA_INDEX_PD1 = 13, /* USB-PD saved port1 state */ + BBRM_DATA_INDEX_TRY_SLOT = 14, /* Vboot EC try slot */ + BBRM_DATA_INDEX_PD2 = 15, /* USB-PD saved port2 state */ /* Index 16-31 available for future use */ - BBRM_DATA_INDEX_RAMLOG = 32, /* RAM log for Booter */ - BBRM_DATA_INDEX_PANIC_FLAGS = 35, /* Flag to indicate validity of - * panic data starting at index - * 36. - */ - BBRM_DATA_INDEX_PANIC_BKUP = 36, /* Panic data (index 35-63)*/ - BBRM_DATA_INDEX_LCT_TIME = 64, /* The start time of LCT(4 bytes) - */ + BBRM_DATA_INDEX_RAMLOG = 32, /* RAM log for Booter */ + BBRM_DATA_INDEX_PANIC_FLAGS = 35, /* Flag to indicate validity of + * panic data starting at index + * 36. + */ + BBRM_DATA_INDEX_PANIC_BKUP = 36, /* Panic data (index 35-63)*/ + BBRM_DATA_INDEX_LCT_TIME = 64, /* The start time of LCT(4 bytes) + */ }; enum psl_pin_t { @@ -69,7 +69,7 @@ void system_check_bbram_on_reset(void); #if defined(CHIP_FAMILY_NPCX5) /* Bypass for GMDA issue of ROM api utilities only on npcx5 series */ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, - uint32_t size, uint32_t exeAddr); + uint32_t size, uint32_t exeAddr); /* Begin address for hibernate utility; defined in linker script */ extern unsigned int __flash_lpfw_start; diff --git a/chip/npcx/uart.c b/chip/npcx/uart.c index c158049e6a..bc87b5921e 100644 --- a/chip/npcx/uart.c +++ b/chip/npcx/uart.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -21,12 +21,12 @@ #include "uartn.h" #include "util.h" -#define CONSOLE_UART CONFIG_CONSOLE_UART +#define CONSOLE_UART CONFIG_CONSOLE_UART #if CONSOLE_UART -#define CONSOLE_UART_IRQ NPCX_IRQ_UART2 +#define CONSOLE_UART_IRQ NPCX_IRQ_UART2 #else -#define CONSOLE_UART_IRQ NPCX_IRQ_UART +#define CONSOLE_UART_IRQ NPCX_IRQ_UART #endif static int init_done; @@ -54,7 +54,7 @@ static int altpad_tx_len; */ static timestamp_t last_default_pad_rx_time; -static const uint32_t block_alt_timeout_us = 500*MSEC; +static const uint32_t block_alt_timeout_us = 500 * MSEC; #else @@ -209,7 +209,8 @@ static void uart_ec_interrupt(void) } if (uartn_tx_ready(NPCX_UART_PORT0)) { if (altpad_tx_pos < altpad_tx_len) - uartn_write_char(NPCX_UART_PORT0, + uartn_write_char( + NPCX_UART_PORT0, altpad_tx_buf[altpad_tx_pos++]); else uart_tx_stop(); @@ -319,8 +320,8 @@ int uart_alt_pad_write_read(uint8_t *tx, int tx_len, uint8_t *rx, int rx_len, uint32_t start = __hw_clock_source_read(); int ret = 0; - if ((get_time().val - last_default_pad_rx_time.val) - < block_alt_timeout_us) + if ((get_time().val - last_default_pad_rx_time.val) < + block_alt_timeout_us) return -EC_ERROR_BUSY; cflush(); @@ -381,7 +382,6 @@ out: #endif void uart_init(void) { - uartn_init(CONSOLE_UART); init_done = 1; } diff --git a/chip/npcx/uartn.c b/chip/npcx/uartn.c index 2269e11e7c..9bcaccd94c 100644 --- a/chip/npcx/uartn.c +++ b/chip/npcx/uartn.c @@ -1,5 +1,5 @@ /* - * Copyright 2018 The Chromium OS Authors. All rights reserved. + * Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,60 +17,58 @@ #ifdef NPCX_UART_FIFO_SUPPORT /* Enable UART Tx FIFO empty interrupt */ -#define NPCX_UART_TX_EMPTY_INT_EN(n) \ - (SET_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN)) +#define NPCX_UART_TX_EMPTY_INT_EN(n) \ + (SET_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN)) /* True if UART Tx FIFO empty interrupt is enabled */ -#define NPCX_UART_TX_EMPTY_INT_IS_EN(n) \ - (IS_BIT_SET(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN)) +#define NPCX_UART_TX_EMPTY_INT_IS_EN(n) \ + (IS_BIT_SET(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN)) /* Disable UART Tx FIFO empty interrupt */ -#define NPCX_UART_TX_EMPTY_INT_DIS(n) \ - (CLEAR_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN)) +#define NPCX_UART_TX_EMPTY_INT_DIS(n) \ + (CLEAR_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN)) /* True if the Tx FIFO is not completely full */ -#define NPCX_UART_TX_IS_READY(n) \ - (!(GET_FIELD(NPCX_UFTSTS(n), NPCX_UFTSTS_TEMPTY_LVL) == 0)) +#define NPCX_UART_TX_IS_READY(n) \ + (!(GET_FIELD(NPCX_UFTSTS(n), NPCX_UFTSTS_TEMPTY_LVL) == 0)) /* Enable UART Tx "not" in transmission interrupt */ -#define NPCX_UART_TX_NXMIP_INT_EN(n) \ - (SET_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_NXMIPEN)) +#define NPCX_UART_TX_NXMIP_INT_EN(n) \ + (SET_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_NXMIPEN)) /* Disable UART Tx "not" in transmission interrupt */ -#define NPCX_UART_TX_NXMIP_INT_DIS(n) \ - (CLEAR_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_NXMIPEN)) +#define NPCX_UART_TX_NXMIP_INT_DIS(n) \ + (CLEAR_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_NXMIPEN)) /* * True if Tx is in progress * (i.e. FIFO is not empty or last byte in TSFT (Transmit Shift register) * is not sent) */ -#define NPCX_UART_TX_IN_XMIT(n) \ - (!IS_BIT_SET(NPCX_UFTSTS(n), NPCX_UFTSTS_NXMIP)) +#define NPCX_UART_TX_IN_XMIT(n) (!IS_BIT_SET(NPCX_UFTSTS(n), NPCX_UFTSTS_NXMIP)) /* * Enable to generate interrupt when there is at least one byte * in the receive FIFO */ -#define NPCX_UART_RX_INT_EN(n) \ - (SET_BIT(NPCX_UFRCTL(n), NPCX_UFRCTL_RNEMPTY_EN)) +#define NPCX_UART_RX_INT_EN(n) (SET_BIT(NPCX_UFRCTL(n), NPCX_UFRCTL_RNEMPTY_EN)) /* True if at least one byte is in the receive FIFO */ -#define NPCX_UART_RX_IS_AVAILABLE(n) \ - (IS_BIT_SET(NPCX_UFRSTS(n), NPCX_UFRSTS_RFIFO_NEMPTY_STS)) +#define NPCX_UART_RX_IS_AVAILABLE(n) \ + (IS_BIT_SET(NPCX_UFRSTS(n), NPCX_UFRSTS_RFIFO_NEMPTY_STS)) #else /* Enable UART Tx buffer empty interrupt */ -#define NPCX_UART_TX_EMPTY_INT_EN(n) (NPCX_UICTRL(n) |= 0x20) +#define NPCX_UART_TX_EMPTY_INT_EN(n) (NPCX_UICTRL(n) |= 0x20) /* True if UART Tx buffer empty interrupt is enabled */ -#define NPCX_UART_TX_EMPTY_INT_IS_EN(n) (NPCX_UICTRL(n) & 0x20) +#define NPCX_UART_TX_EMPTY_INT_IS_EN(n) (NPCX_UICTRL(n) & 0x20) /* Disable UART Tx buffer empty interrupt */ -#define NPCX_UART_TX_EMPTY_INT_DIS(n) (NPCX_UICTRL(n) &= ~0x20) +#define NPCX_UART_TX_EMPTY_INT_DIS(n) (NPCX_UICTRL(n) &= ~0x20) /* True if 1-byte Tx buffer is empty */ -#define NPCX_UART_TX_IS_READY(n) (NPCX_UICTRL(n) & 0x01) +#define NPCX_UART_TX_IS_READY(n) (NPCX_UICTRL(n) & 0x01) /* * True if Tx is in progress * (i.e. Tx buffer is not empty or last byte in TSFT (Transmit Shift register) * is not sent) */ -#define NPCX_UART_TX_IN_XMIT(n) (NPCX_USTAT(n) & 0x40) - /* Enable to generate interrupt when there is data in the receive buffer */ -#define NPCX_UART_RX_INT_EN(n) (NPCX_UICTRL(n) = 0x40) +#define NPCX_UART_TX_IN_XMIT(n) (NPCX_USTAT(n) & 0x40) +/* Enable to generate interrupt when there is data in the receive buffer */ +#define NPCX_UART_RX_INT_EN(n) (NPCX_UICTRL(n) = 0x40) /* True if there is data in the 1-byte Receive buffer */ -#define NPCX_UART_RX_IS_AVAILABLE(n) (NPCX_UICTRL(n) & 0x02) +#define NPCX_UART_RX_IS_AVAILABLE(n) (NPCX_UICTRL(n) & 0x02) #endif struct uart_configs { @@ -79,9 +77,9 @@ struct uart_configs { uint32_t clk_en_msk; }; static const struct uart_configs uart_cfg[] = { - {NPCX_IRQ_UART, CGC_OFFSET_UART, CGC_UART_MASK}, + { NPCX_IRQ_UART, CGC_OFFSET_UART, CGC_UART_MASK }, #ifdef NPCX_SECOND_UART - {NPCX_IRQ_UART2, CGC_OFFSET_UART2, CGC_UART2_MASK}, + { NPCX_IRQ_UART2, CGC_OFFSET_UART2, CGC_UART2_MASK }, #endif }; BUILD_ASSERT(ARRAY_SIZE(uart_cfg) == UART_MODULE_COUNT); @@ -144,7 +142,7 @@ void uartn_tx_start(uint8_t uart_num) void uartn_enable_tx_complete_int(uint8_t uart_num, uint8_t enable) { enable ? NPCX_UART_TX_NXMIP_INT_EN(uart_num) : - NPCX_UART_TX_NXMIP_INT_DIS(uart_num); + NPCX_UART_TX_NXMIP_INT_DIS(uart_num); } #endif @@ -198,7 +196,7 @@ int uartn_read_char(uint8_t uart_num) void uartn_clear_rx_fifo(int channel) { - int scratch __attribute__ ((unused)); + int scratch __attribute__((unused)); /* If '1', that means there is RX data on the FIFO register */ while (NPCX_UART_RX_IS_AVAILABLE(channel)) @@ -211,9 +209,9 @@ static void uartn_set_fifo_mode(uint8_t uart_num) /* Enable the UART FIFO mode */ SET_BIT(NPCX_UMDSL(uart_num), NPCX_UMDSL_FIFO_MD); /* Disable all Tx interrupts */ - NPCX_UFTCTL(uart_num) &= ~(BIT(NPCX_UFTCTL_TEMPTY_LVL_EN) | - BIT(NPCX_UFTCTL_TEMPTY_EN) | - BIT(NPCX_UFTCTL_NXMIPEN)); + NPCX_UFTCTL(uart_num) &= + ~(BIT(NPCX_UFTCTL_TEMPTY_LVL_EN) | BIT(NPCX_UFTCTL_TEMPTY_EN) | + BIT(NPCX_UFTCTL_NXMIPEN)); } #endif diff --git a/chip/npcx/uartn.h b/chip/npcx/uartn.h index e5326f72b8..ce111f11d9 100644 --- a/chip/npcx/uartn.h +++ b/chip/npcx/uartn.h @@ -1,5 +1,5 @@ /* - * Copyright 2018 The Chromium OS Authors. All rights reserved. + * Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -22,7 +22,7 @@ void uartn_init(uint8_t uart_num); */ void uartn_tx_start(uint8_t uart_num); - /* Disable the UART transmit interrupt. */ +/* Disable the UART transmit interrupt. */ void uartn_tx_stop(uint8_t uart_num, uint8_t sleep_ena); /* Flush the transmit FIFO. */ @@ -62,4 +62,4 @@ void uartn_rx_int_en(uint8_t uart_num); void uartn_wui_en(uint8_t uart_num); /* Enable/disable Tx NXMIP (No Transmit In Progress) interrupt */ void uartn_enable_tx_complete_int(uint8_t uart_num, uint8_t enable); -#endif /* __CROS_EC_UARTN_H */ +#endif /* __CROS_EC_UARTN_H */ diff --git a/chip/npcx/watchdog.c b/chip/npcx/watchdog.c index 55b8df8c1c..8ae9ee0474 100644 --- a/chip/npcx/watchdog.c +++ b/chip/npcx/watchdog.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -108,18 +108,18 @@ void IRQ_HANDLER(ITIM_INT(ITIM_WDG_NO))(void) { /* Naked call so we can extract raw LR and SP */ asm volatile("mov r0, lr\n" - "mov r1, sp\n" - /* Must push registers in pairs to keep 64-bit aligned - * stack for ARM EABI. This also conveninently saves - * R0=LR so we can pass it to task_resched_if_needed. */ - "push {r0, lr}\n" - "bl watchdog_check\n" - "pop {r0, lr}\n" - "b task_resched_if_needed\n"); + "mov r1, sp\n" + /* Must push registers in pairs to keep 64-bit aligned + * stack for ARM EABI. This also conveninently saves + * R0=LR so we can pass it to task_resched_if_needed. */ + "push {r0, lr}\n" + "bl watchdog_check\n" + "pop {r0, lr}\n" + "b task_resched_if_needed\n"); } const struct irq_priority __keep IRQ_PRIORITY(ITIM_INT(ITIM_WDG_NO)) -__attribute__((section(".rodata.irqprio"))) -= {ITIM_INT(ITIM_WDG_NO), 0}; + __attribute__((section(".rodata.irqprio"))) = { ITIM_INT(ITIM_WDG_NO), + 0 }; /* put the watchdog at the highest priority */ void watchdog_reload(void) diff --git a/chip/npcx/wov.c b/chip/npcx/wov.c index 5c3e915200..1ae1afe71d 100644 --- a/chip/npcx/wov.c +++ b/chip/npcx/wov.c @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -26,7 +26,7 @@ #define CPRINTS(...) #else #define CPUTS(outstr) cputs(CC_AUDIO_CODEC, outstr) -#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ##args) #endif /* WOV FIFO status. */ @@ -64,106 +64,106 @@ #define WOV_FMUL2_CLK_TUNING_DELAY_TIME (4 * 1000) /* The size of RAM buffer to store the voice data */ -#define VOICE_BUF_SIZE 16000 +#define VOICE_BUF_SIZE 16000 /* PLL setting options. */ struct wov_pll_set_options_val { - uint8_t pll_indv; /* Input Divider */ - uint16_t pll_fbdv; /* Feedback Divider */ - uint8_t pll_otdv1; /* Output devide 1. */ - uint8_t pll_otdv2; /* Output devide 2. */ + uint8_t pll_indv; /* Input Divider */ + uint16_t pll_fbdv; /* Feedback Divider */ + uint8_t pll_otdv1; /* Output devide 1. */ + uint8_t pll_otdv2; /* Output devide 2. */ uint32_t pll_ext_div; /* Index for the table pll_ext_div */ }; /* PLL External Divider Load Values. */ struct wov_pll_ext_div_val { - uint8_t pll_ediv; /* Required PLL external divider */ + uint8_t pll_ediv; /* Required PLL external divider */ uint8_t pll_ediv_dc; /* Required PLL external divider DC */ }; static const struct wov_pll_ext_div_val pll_ext_div[] = { - {0x2F, 0x78}, /* 12 */ - {0x57, 0x7C}, /* 13 */ - {0x2B, 0x7C}, /* 14 */ - {0x55, 0x7E}, /* 15 */ - {0x2A, 0x7E}, /* 16 */ - {0x15, 0x7F}, /* 17 */ - {0x4A, 0x7F}, /* 18 */ - {0x65, 0x3F}, /* 19 */ - {0x32, 0x3F}, /* 20 */ - {0x19, 0x5F}, /* 21 */ - {0x4C, 0x5F}, /* 22 */ - {0x66, 0x2F}, /* 23 */ - {0x73, 0x2F}, /* 24 */ - {0x39, 0x57}, /* 25 */ - {0x5C, 0x57}, /* 26 */ - {0x6E, 0x2B}, /* 27 */ - {0x77, 0x2B}, /* 28 */ - {0x3B, 0x55}, /* 29 */ - {0x5D, 0x55}, /* 30 */ - {0x2E, 0x2A}, /* 31 */ - {0x17, 0x2A}, /* 32 */ - {0x4B, 0x15}, /* 33 */ - {0x25, 0x15}, /* 34 */ - {0x52, 0x4A}, /* 35 */ - {0x69, 0x4A}, /* 36 */ - {0x34, 0x65}, /* 37 */ - {0x1A, 0x65}, /* 38 */ - {0x0D, 0x32}, /* 39 */ - {0x46, 0x32}, /* 40 */ - {0x63, 0x19}, /* 41 */ - {0x31, 0x19}, /* 42 */ - {0x58, 0x4C}, /* 43 */ - {0x6C, 0x4C}, /* 44 */ - {0x76, 0x66}, /* 45 */ - {0x7B, 0x66}, /* 46 */ - {0x3D, 0x73}, /* 47 */ - {0x5E, 0x73}, /* 48 */ - {0x6F, 0x39}, /* 49 */ - {0x37, 0x39}, /* 50 */ - {0x5B, 0x5C}, /* 51 */ - {0x2D, 0x5C}, /* 52 */ - {0x56, 0x6E}, /* 53 */ - {0x6B, 0x6E}, /* 54 */ - {0x35, 0x77}, /* 55 */ - {0x5A, 0x77}, /* 56 */ - {0x6D, 0x3B}, /* 57 */ - {0x36, 0x3B}, /* 58 */ - {0x1B, 0x5D}, /* 59 */ - {0x4D, 0x5D}, /* 60 */ - {0x26, 0x2E}, /* 61 */ - {0x13, 0x2E}, /* 62 */ - {0x49, 0x17}, /* 63 */ - {0x24, 0x17}, /* 64 */ - {0x12, 0x4B}, /* 65 */ - {0x09, 0x4B}, /* 66 */ - {0x44, 0x25} /* 67 */ + { 0x2F, 0x78 }, /* 12 */ + { 0x57, 0x7C }, /* 13 */ + { 0x2B, 0x7C }, /* 14 */ + { 0x55, 0x7E }, /* 15 */ + { 0x2A, 0x7E }, /* 16 */ + { 0x15, 0x7F }, /* 17 */ + { 0x4A, 0x7F }, /* 18 */ + { 0x65, 0x3F }, /* 19 */ + { 0x32, 0x3F }, /* 20 */ + { 0x19, 0x5F }, /* 21 */ + { 0x4C, 0x5F }, /* 22 */ + { 0x66, 0x2F }, /* 23 */ + { 0x73, 0x2F }, /* 24 */ + { 0x39, 0x57 }, /* 25 */ + { 0x5C, 0x57 }, /* 26 */ + { 0x6E, 0x2B }, /* 27 */ + { 0x77, 0x2B }, /* 28 */ + { 0x3B, 0x55 }, /* 29 */ + { 0x5D, 0x55 }, /* 30 */ + { 0x2E, 0x2A }, /* 31 */ + { 0x17, 0x2A }, /* 32 */ + { 0x4B, 0x15 }, /* 33 */ + { 0x25, 0x15 }, /* 34 */ + { 0x52, 0x4A }, /* 35 */ + { 0x69, 0x4A }, /* 36 */ + { 0x34, 0x65 }, /* 37 */ + { 0x1A, 0x65 }, /* 38 */ + { 0x0D, 0x32 }, /* 39 */ + { 0x46, 0x32 }, /* 40 */ + { 0x63, 0x19 }, /* 41 */ + { 0x31, 0x19 }, /* 42 */ + { 0x58, 0x4C }, /* 43 */ + { 0x6C, 0x4C }, /* 44 */ + { 0x76, 0x66 }, /* 45 */ + { 0x7B, 0x66 }, /* 46 */ + { 0x3D, 0x73 }, /* 47 */ + { 0x5E, 0x73 }, /* 48 */ + { 0x6F, 0x39 }, /* 49 */ + { 0x37, 0x39 }, /* 50 */ + { 0x5B, 0x5C }, /* 51 */ + { 0x2D, 0x5C }, /* 52 */ + { 0x56, 0x6E }, /* 53 */ + { 0x6B, 0x6E }, /* 54 */ + { 0x35, 0x77 }, /* 55 */ + { 0x5A, 0x77 }, /* 56 */ + { 0x6D, 0x3B }, /* 57 */ + { 0x36, 0x3B }, /* 58 */ + { 0x1B, 0x5D }, /* 59 */ + { 0x4D, 0x5D }, /* 60 */ + { 0x26, 0x2E }, /* 61 */ + { 0x13, 0x2E }, /* 62 */ + { 0x49, 0x17 }, /* 63 */ + { 0x24, 0x17 }, /* 64 */ + { 0x12, 0x4B }, /* 65 */ + { 0x09, 0x4B }, /* 66 */ + { 0x44, 0x25 } /* 67 */ }; /* WOV interrupts */ static const uint8_t wov_interupts[] = { - 0, /* VAD_INTEN */ - 1, /* VAD_WKEN */ - 8, /* CFIFO_NE_IE */ - 9, /* CFIFO_OIT_IE */ + 0, /* VAD_INTEN */ + 1, /* VAD_WKEN */ + 8, /* CFIFO_NE_IE */ + 9, /* CFIFO_OIT_IE */ 10, /* CFIFO_OWT_WE */ 11, /* CFIFO_OVRN_IE */ 12, /* I2S_FIFO_OVRN_IE */ - 13 /* I2S_FIFO_UNDRN_IE */ + 13 /* I2S_FIFO_UNDRN_IE */ }; struct wov_ppl_divider { uint16_t pll_frame_len; /* PLL frame length. */ - uint16_t pll_fbdv; /* PLL feedback divider. */ - uint8_t pll_indv; /* PLL Input Divider. */ - uint8_t pll_otdv1; /* PLL Output Divider 1. */ - uint8_t pll_otdv2; /* PLL Output Divider 2. */ - uint8_t pll_ediv; /* PLL External Divide Factor. */ + uint16_t pll_fbdv; /* PLL feedback divider. */ + uint8_t pll_indv; /* PLL Input Divider. */ + uint8_t pll_otdv1; /* PLL Output Divider 1. */ + uint8_t pll_otdv2; /* PLL Output Divider 2. */ + uint8_t pll_ediv; /* PLL External Divide Factor. */ }; struct wov_cfifo_buf { uint32_t *buf; /* Pointer to a buffer. */ - int size; /* Buffer size in words. */ + int size; /* Buffer size in words. */ }; struct wov_config wov_conf; @@ -205,11 +205,11 @@ void wov_cfifo_read_handler_l(uint32_t num_elements) cfifo_buf.size -= num_elements; } -static enum ec_error_list wov_calc_pll_div_s(int32_t d_in, - int32_t total_div, int32_t vco_freq, - struct wov_ppl_divider *pll_div) +static enum ec_error_list wov_calc_pll_div_s(int32_t d_in, int32_t total_div, + int32_t vco_freq, + struct wov_ppl_divider *pll_div) { - int32_t d_1, d_2, d_e; + int32_t d_1, d_2, d_e; /* * Please see comments in wov_calc_pll_div_l function below. @@ -221,10 +221,10 @@ static enum ec_error_list wov_calc_pll_div_s(int32_t d_in, continue; if (total_div == (d_in * d_e * d_1 * d_2)) { - pll_div->pll_indv = d_in; + pll_div->pll_indv = d_in; pll_div->pll_otdv1 = d_1; pll_div->pll_otdv2 = d_2; - pll_div->pll_ediv = d_e; + pll_div->pll_ediv = d_e; return EC_SUCCESS; } } @@ -243,7 +243,8 @@ static enum ec_error_list wov_calc_pll_div_s(int32_t d_in, * @return None */ static enum ec_error_list wov_calc_pll_div_l(uint32_t i2s_clk_freq, - uint32_t sample_rate, struct wov_ppl_divider *pll_div) + uint32_t sample_rate, + struct wov_ppl_divider *pll_div) { int32_t d_f; int32_t total_div; @@ -292,12 +293,11 @@ static enum ec_error_list wov_calc_pll_div_l(uint32_t i2s_clk_freq, if ((vco_freq < 500) || (vco_freq > 1600)) continue; if (wov_calc_pll_div_s(d_in, total_div, - vco_freq, pll_div) == - EC_SUCCESS) { - pll_div->pll_fbdv = d_f; + vco_freq, + pll_div) == EC_SUCCESS) { + pll_div->pll_fbdv = d_f; return EC_SUCCESS; } - } } } @@ -340,12 +340,13 @@ static enum ec_error_list wov_set_i2s_config_l(void) int32_t start_delay_0, start_delay_1; ret_code = wov_calc_pll_div_l(wov_conf.i2s_clock, - wov_conf.sample_per_sec, &pll_div); + wov_conf.sample_per_sec, &pll_div); if (ret_code == EC_SUCCESS) { /* Configure the PLL. */ - ret_code = wov_pll_clk_div_config( - pll_div.pll_otdv1, pll_div.pll_otdv2, pll_div.pll_fbdv, - pll_div.pll_indv); + ret_code = wov_pll_clk_div_config(pll_div.pll_otdv1, + pll_div.pll_otdv2, + pll_div.pll_fbdv, + pll_div.pll_indv); if (ret_code != EC_SUCCESS) return ret_code; @@ -414,10 +415,10 @@ static enum ec_error_list wov_set_i2s_config_l(void) udelay(100); ret_code = wov_i2s_channel_config(0, wov_conf.bit_depth, - trigger_0, start_delay_0); + trigger_0, start_delay_0); ret_code = wov_i2s_channel_config(1, wov_conf.bit_depth, - trigger_1, start_delay_1); + trigger_1, start_delay_1); } return EC_SUCCESS; @@ -471,14 +472,14 @@ static enum ec_error_list wov_set_mic_source_l(void) case WOV_SRC_LEFT: if (wov_conf.bit_depth == 16) SET_FIELD(NPCX_WOV_FIFO_CNT, - NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x00); + NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x00); else SET_FIELD(NPCX_WOV_FIFO_CNT, - NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x02); + NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x02); SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT, - 0x01); + 0x01); SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT, - 0x01); + 0x01); apm_digital_mixer_config(APM_OUT_MIX_NORMAL_INPUT, APM_OUT_MIX_NO_INPUT); apm_set_vad_input_channel(APM_IN_LEFT); @@ -493,11 +494,11 @@ static enum ec_error_list wov_set_mic_source_l(void) SET_FIELD(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x02); SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT, - 0x01); + 0x01); SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT, - 0x01); + 0x01); apm_digital_mixer_config(APM_OUT_MIX_CROSS_INPUT, - APM_OUT_MIX_NO_INPUT); + APM_OUT_MIX_NO_INPUT); apm_set_vad_input_channel(APM_IN_RIGHT); wov_i2s_channel1_disable(1); break; @@ -505,16 +506,16 @@ static enum ec_error_list wov_set_mic_source_l(void) case WOV_SRC_MONO: if (wov_conf.bit_depth == 16) SET_FIELD(NPCX_WOV_FIFO_CNT, - NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x01); + NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x01); else SET_FIELD(NPCX_WOV_FIFO_CNT, - NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x03); + NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x03); SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT, - 0x02); + 0x02); SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT, - 0x02); + 0x02); apm_digital_mixer_config(APM_OUT_MIX_NORMAL_INPUT, - APM_OUT_MIX_NORMAL_INPUT); + APM_OUT_MIX_NORMAL_INPUT); apm_set_vad_input_channel(APM_IN_AVERAGE_LEFT_RIGHT); wov_i2s_channel1_disable(0); break; @@ -522,14 +523,14 @@ static enum ec_error_list wov_set_mic_source_l(void) case WOV_SRC_STEREO: if (wov_conf.bit_depth == 16) SET_FIELD(NPCX_WOV_FIFO_CNT, - NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x01); + NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x01); else SET_FIELD(NPCX_WOV_FIFO_CNT, - NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x03); + NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x03); SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT, - 0x01); + 0x01); SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT, - 0x01); + 0x01); apm_digital_mixer_config(APM_OUT_MIX_NORMAL_INPUT, APM_OUT_MIX_NORMAL_INPUT); wov_i2s_channel1_disable(0); @@ -586,7 +587,7 @@ static void wov_interrupt_handler(void) wov_inten = GET_FIELD(NPCX_WOV_WOV_INTEN, NPCX_WOV_STATUS_BITS); wov_status = wov_inten & - GET_FIELD(NPCX_WOV_STATUS, NPCX_WOV_STATUS_BITS); + GET_FIELD(NPCX_WOV_STATUS, NPCX_WOV_STATUS_BITS); /* * Voice activity detected. @@ -602,7 +603,7 @@ static void wov_interrupt_handler(void) WOV_CALLBACK(WOV_EVENT_ERROR_CORE_FIFO_OVERRUN); wov_core_fifo_reset(); } else if (WOV_IS_CFIFO_INT_THRESHOLD(wov_status) && - (cfifo_buf.buf != NULL)) { + (cfifo_buf.buf != NULL)) { /* * Core FIFO threshold or FIFO not empty event occurred. * - Read data from core FIFO to the buffer. @@ -635,7 +636,6 @@ static void wov_interrupt_handler(void) wov_i2s_fifo_reset(); } - /* Clear the WoV status register. */ SET_FIELD(NPCX_WOV_STATUS, NPCX_WOV_STATUS_BITS, wov_status); } @@ -651,19 +651,17 @@ DECLARE_IRQ(NPCX_IRQ_WOV, wov_interrupt_handler, 4); static void wov_fmul2_enable(int enable) { if (enable) { - /* If clock disabled, then enable it. */ if (IS_BIT_SET(NPCX_FMUL2_FM2CTRL, - NPCX_FMUL2_FM2CTRL_FMUL2_DIS)) { + NPCX_FMUL2_FM2CTRL_FMUL2_DIS)) { /* Enable clock tuning. */ CLEAR_BIT(NPCX_FMUL2_FM2CTRL, - NPCX_FMUL2_FM2CTRL_TUNE_DIS); + NPCX_FMUL2_FM2CTRL_TUNE_DIS); /* Enable clock. */ CLEAR_BIT(NPCX_FMUL2_FM2CTRL, - NPCX_FMUL2_FM2CTRL_FMUL2_DIS); + NPCX_FMUL2_FM2CTRL_FMUL2_DIS); udelay(WOV_FMUL2_CLK_TUNING_DELAY_TIME); - } } else SET_BIT(NPCX_FMUL2_FM2CTRL, NPCX_FMUL2_FM2CTRL_FMUL2_DIS); @@ -688,7 +686,7 @@ void wov_fmul2_conf_tuning(void) { /* Check if FMUL2 is enabled, then do nothing. */ if (IS_BIT_SET(NPCX_FMUL2_FM2CTRL, NPCX_FMUL2_FM2CTRL_FMUL2_DIS) == - 0x00) + 0x00) return; /* Enable clock tuning. */ @@ -968,7 +966,6 @@ void wov_set_clk_selection(enum wov_clk_src_sel clk_src) wov_fmul2_enable(0); else wov_pll_enable(0); - } /** @@ -981,9 +978,9 @@ void wov_set_clk_selection(enum wov_clk_src_sel clk_src) * PLL External Divider Load Values table. * @return EC_ERROR_INVAL or EC_SUCCESS */ -enum ec_error_list wov_pll_clk_ext_div_config( - enum wov_pll_ext_div_sel ext_div_sel, - uint32_t div_factor) +enum ec_error_list +wov_pll_clk_ext_div_config(enum wov_pll_ext_div_sel ext_div_sel, + uint32_t div_factor) { /* Sets the clock division factor for the PLL external divider. * The divide factor should be in the range of 2 to 67. @@ -1045,13 +1042,13 @@ void wov_pll_enable(int enable) * @return EC_ERROR_INVAL or EC_SUCCESS */ enum ec_error_list wov_pll_clk_div_config(uint32_t out_div_1, - uint32_t out_div_2, - uint32_t feedback_div, - uint32_t in_div) + uint32_t out_div_2, + uint32_t feedback_div, + uint32_t in_div) { /* Parameter check. */ - if ((out_div_1 < 1) || (out_div_1 > 7) || - (out_div_2 < 1) || (out_div_2 > 7)) + if ((out_div_1 < 1) || (out_div_1 > 7) || (out_div_2 < 1) || + (out_div_2 > 7)) return EC_ERROR_INVAL; /* @@ -1255,7 +1252,7 @@ int wov_set_buffer(uint32_t *buf, int size_in_words) cfifo_threshold = wov_get_cfifo_threshold_l(); if (size_in_words != - ((size_in_words / cfifo_threshold) * cfifo_threshold)) + ((size_in_words / cfifo_threshold) * cfifo_threshold)) return EC_ERROR_INVAL; cfifo_buf.buf = buf; @@ -1298,21 +1295,17 @@ void wov_apm_active(int enable) * @return EC_ERROR_INVAL or EC_SUCCESS */ enum ec_error_list wov_i2s_global_config( - enum wov_floating_mode i2s_hiz_data, - enum wov_floating_mode i2s_hiz, - enum wov_clk_inverted_mode clk_invert, - int out_pull_en, - enum wov_pull_upd_down_sel out_pull_mode, - int in_pull_en, - enum wov_pull_upd_down_sel in_pull_mode, - enum wov_test_mode test_mode) + enum wov_floating_mode i2s_hiz_data, enum wov_floating_mode i2s_hiz, + enum wov_clk_inverted_mode clk_invert, int out_pull_en, + enum wov_pull_upd_down_sel out_pull_mode, int in_pull_en, + enum wov_pull_upd_down_sel in_pull_mode, enum wov_test_mode test_mode) { /* Check the parameters correctness. */ if ((i2s_hiz_data == WOV_FLOATING) && - ((GET_FIELD(NPCX_WOV_I2S_CNTL(0), - NPCX_WOV_I2S_CNTL_I2S_ST_DEL) == 0) || - (GET_FIELD(NPCX_WOV_I2S_CNTL(1), - NPCX_WOV_I2S_CNTL_I2S_ST_DEL) == 0))) + ((GET_FIELD(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL_I2S_ST_DEL) == + 0) || + (GET_FIELD(NPCX_WOV_I2S_CNTL(1), NPCX_WOV_I2S_CNTL_I2S_ST_DEL) == + 0))) return EC_ERROR_INVAL; /* Set the parameters. */ @@ -1375,9 +1368,9 @@ enum ec_error_list wov_i2s_global_config( * @return EC_ERROR_INVAL or EC_SUCCESS */ enum ec_error_list wov_i2s_channel_config(uint32_t channel_num, - uint32_t bit_count, - enum wov_i2s_chan_trigger trigger, - int32_t start_delay) + uint32_t bit_count, + enum wov_i2s_chan_trigger trigger, + int32_t start_delay) { /* Check the parameters correctnes. */ if ((channel_num != 0) && (channel_num != 1)) @@ -1392,7 +1385,7 @@ enum ec_error_list wov_i2s_channel_config(uint32_t channel_num, /* Set the parameters. */ SET_FIELD(NPCX_WOV_I2S_CNTL(channel_num), NPCX_WOV_I2S_CNTL_I2S_BCNT, - (bit_count - 1)); + (bit_count - 1)); if (trigger == WOV_I2S_SAMPLED_1_AFTER_0) CLEAR_BIT(NPCX_WOV_I2S_CNTL(channel_num), @@ -1459,8 +1452,8 @@ int wov_set_sample_depth(int bits_num) if (wov_conf.mode != WOV_MODE_OFF) return EC_ERROR_INVALID_CONFIG; - if ((bits_num != 16) && (bits_num != 18) && - (bits_num != 20) && (bits_num != 24)) + if ((bits_num != 16) && (bits_num != 18) && (bits_num != 20) && + (bits_num != 24)) return EC_ERROR_INVAL; wov_conf.bit_depth = bits_num; @@ -1529,8 +1522,8 @@ void wov_set_gain(int left_chan_gain, int right_chan_gain) wov_conf.left_chan_gain = left_chan_gain; wov_conf.right_chan_gain = right_chan_gain; - (void) apm_adc_gain_config(APM_ADC_CHAN_GAINS_INDEPENDENT, - left_chan_gain, right_chan_gain); + (void)apm_adc_gain_config(APM_ADC_CHAN_GAINS_INDEPENDENT, + left_chan_gain, right_chan_gain); } /** @@ -1571,10 +1564,10 @@ void wov_enable_agc(int enable) * @param min_applied_gain - Minimum Gain Value to apply to the ADC path. * @return EC_ERROR_INVAL or EC_SUCCESS */ -enum ec_error_list wov_set_agc_config(int stereo, float target, - int noise_gate_threshold, uint8_t hold_time, - uint16_t attack_time, uint16_t decay_time, - float max_applied_gain, float min_applied_gain) +enum ec_error_list +wov_set_agc_config(int stereo, float target, int noise_gate_threshold, + uint8_t hold_time, uint16_t attack_time, uint16_t decay_time, + float max_applied_gain, float min_applied_gain) { int target_code; int ngth_code; @@ -1607,7 +1600,7 @@ enum ec_error_list wov_set_agc_config(int stereo, float target, return EC_ERROR_INVAL; for (attack_time_code = 0; attack_time_code <= 0x0F; - attack_time_code++) { + attack_time_code++) { if (((attack_time_code + 1) * 32) == attack_time) break; } @@ -1622,15 +1615,15 @@ enum ec_error_list wov_set_agc_config(int stereo, float target, return EC_ERROR_INVAL; for (max_applied_gain_code = 0; max_applied_gain_code < 16; - max_applied_gain_code++) { + max_applied_gain_code++) { if ((max_applied_gain_code * 1.5) == max_applied_gain) break; } if (max_applied_gain_code == 16) { for (max_applied_gain_code = 18; max_applied_gain_code < 32; - max_applied_gain_code++) { + max_applied_gain_code++) { if (((max_applied_gain_code * 1.5) - 4) == - max_applied_gain) + max_applied_gain) break; } } @@ -1638,15 +1631,15 @@ enum ec_error_list wov_set_agc_config(int stereo, float target, return EC_ERROR_INVAL; for (min_applied_gain_code = 0; min_applied_gain_code < 16; - min_applied_gain_code++) { + min_applied_gain_code++) { if ((min_applied_gain_code * 1.5) == min_applied_gain) break; } if (min_applied_gain_code == 16) { for (min_applied_gain_code = 18; min_applied_gain_code < 32; - min_applied_gain_code++) { + min_applied_gain_code++) { if (((min_applied_gain_code * 1.5) - 4) == - min_applied_gain) + min_applied_gain) break; } } @@ -1654,14 +1647,14 @@ enum ec_error_list wov_set_agc_config(int stereo, float target, return EC_ERROR_INVAL; gain_cfg.stereo_enable = stereo, - gain_cfg.agc_target = (enum apm_adc_target_out_level) target_code; + gain_cfg.agc_target = (enum apm_adc_target_out_level)target_code; gain_cfg.nois_gate_en = (noise_gate_threshold != 0); - gain_cfg.nois_gate_thold = (enum apm_noise_gate_threshold) ngth_code; - gain_cfg.hold_time = (enum apm_agc_adj_hold_time) hold_time; - gain_cfg.attack_time = (enum apm_gain_ramp_time) attack_time_code; - gain_cfg.decay_time = (enum apm_gain_ramp_time) decay_time_code; - gain_cfg.gain_max = (enum apm_gain_values) max_applied_gain_code; - gain_cfg.gain_min = (enum apm_gain_values) min_applied_gain_code; + gain_cfg.nois_gate_thold = (enum apm_noise_gate_threshold)ngth_code; + gain_cfg.hold_time = (enum apm_agc_adj_hold_time)hold_time; + gain_cfg.attack_time = (enum apm_gain_ramp_time)attack_time_code; + gain_cfg.decay_time = (enum apm_gain_ramp_time)decay_time_code; + gain_cfg.gain_max = (enum apm_gain_values)max_applied_gain_code; + gain_cfg.gain_min = (enum apm_gain_values)min_applied_gain_code; ret_code = apm_adc_auto_gain_config(&gain_cfg); @@ -1676,7 +1669,6 @@ enum ec_error_list wov_set_agc_config(int stereo, float target, */ int wov_set_vad_sensitivity(int sensitivity_db) { - if ((sensitivity_db < 0) || (sensitivity_db > 31)) return EC_ERROR_INVAL; @@ -1752,27 +1744,27 @@ void wov_set_i2s_bclk(uint32_t i2s_clock) * @return EC error code. */ enum ec_error_list wov_set_i2s_tdm_config(int ch0_delay, int ch1_delay, - uint32_t flags) + uint32_t flags) { if (wov_conf.mode != WOV_MODE_OFF) return EC_ERROR_INVALID_CONFIG; - if ((ch0_delay < 0) || (ch0_delay > 496) || - (ch1_delay < -1) || (ch1_delay > 496)) + if ((ch0_delay < 0) || (ch0_delay > 496) || (ch1_delay < -1) || + (ch1_delay > 496)) return EC_ERROR_INVAL; wov_conf.i2s_start_delay_0 = ch0_delay; wov_conf.i2s_start_delay_1 = ch1_delay; SET_FIELD(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL_I2S_ST_DEL, - ch0_delay); + ch0_delay); if (ch1_delay == -1) wov_i2s_channel1_disable(1); else { wov_i2s_channel1_disable(0); SET_FIELD(NPCX_WOV_I2S_CNTL(1), NPCX_WOV_I2S_CNTL_I2S_ST_DEL, - ch1_delay); + ch1_delay); } if (flags & 0x0001) @@ -1820,10 +1812,10 @@ void wov_handle_event(enum wov_events event) } #ifdef DEBUG_AUDIO_CODEC -static uint32_t voice_buffer[VOICE_BUF_SIZE] = {0}; +static uint32_t voice_buffer[VOICE_BUF_SIZE] = { 0 }; /* voice data 16Khz 2ch 16bit 1s */ -static int command_wov(int argc, char **argv) +static int command_wov(int argc, const char **argv) { static int bit_clk; static enum wov_dai_format i2s_fmt; @@ -1845,8 +1837,9 @@ static int command_wov(int argc, char **argv) /* Start to capature voice data and store in RAM buffer */ if (strcasecmp(argv[1], "capram") == 0) { if (wov_set_buffer((uint32_t *)voice_buffer, - sizeof(voice_buffer) / sizeof(uint32_t)) - == EC_SUCCESS) { + sizeof(voice_buffer) / + sizeof(uint32_t)) == + EC_SUCCESS) { CPRINTS("Start RAM Catpure..."); wov_start_ram_capture(); return EC_SUCCESS; @@ -1980,8 +1973,9 @@ static int command_wov(int argc, char **argv) wov_set_mode(WOV_MODE_VAD); } else if (strcasecmp(argv[2], "ram") == 0) { if (wov_set_buffer((uint32_t *)voice_buffer, - sizeof(voice_buffer) / sizeof(uint32_t)) - == EC_SUCCESS) + sizeof(voice_buffer) / + sizeof(uint32_t)) == + EC_SUCCESS) wov_set_mode(WOV_MODE_RAM); else return EC_ERROR_INVAL; @@ -1989,8 +1983,9 @@ static int command_wov(int argc, char **argv) wov_set_mode(WOV_MODE_I2S); } else if (strcasecmp(argv[2], "rami2s") == 0) { if (wov_set_buffer((uint32_t *)voice_buffer, - sizeof(voice_buffer) / sizeof(uint32_t)) - == EC_SUCCESS) + sizeof(voice_buffer) / + sizeof(uint32_t)) == + EC_SUCCESS) wov_set_mode(WOV_MODE_RAM_AND_I2S); else return EC_ERROR_INVAL; @@ -2013,7 +2008,7 @@ static int command_wov(int argc, char **argv) if (strcasecmp(argv[1], "fmul2") == 0) { if (strcasecmp(argv[2], "enable") == 0) { CLEAR_BIT(NPCX_FMUL2_FM2CTRL, - NPCX_FMUL2_FM2CTRL_TUNE_DIS); + NPCX_FMUL2_FM2CTRL_TUNE_DIS); return EC_SUCCESS; } if (strcasecmp(argv[2], "disable") == 0) { @@ -2050,22 +2045,22 @@ static int command_wov(int argc, char **argv) } DECLARE_CONSOLE_COMMAND(wov, command_wov, - "init\n" - "mute <enable|disable>\n" - "capram\n" - "cfgsrc <mono|stereo|left|right>\n" - "cfgbit <16|18|20|24>\n" - "cfgsfs <8000|12000|16000|24000|32000|48000>\n" - "cfgbck <32fs|48fs|64fs|128fs|256fs>\n" - "cfgfmt <i2s|right|left|pcma|pcmb|tdm>\n" - "cfgmod <off|vad|ram|i2s|rami2s>\n" - "cfgtdm [0~496 0~496 0~3]>\n" - "cfgdckV <0.75|1.0|1.2|2.4|3.0>\n" - "cfgdckR <0.75|1.0|1.2|2.4|3.0>\n" - "cfgdckI <0.75|1.0|1.2|2.4|3.0>\n" - "cfgget\n" - "fmul2 <enable|disable>\n" - "vadsens <0~31>\n" - "gain <0~31>", - "wov configuration"); + "init\n" + "mute <enable|disable>\n" + "capram\n" + "cfgsrc <mono|stereo|left|right>\n" + "cfgbit <16|18|20|24>\n" + "cfgsfs <8000|12000|16000|24000|32000|48000>\n" + "cfgbck <32fs|48fs|64fs|128fs|256fs>\n" + "cfgfmt <i2s|right|left|pcma|pcmb|tdm>\n" + "cfgmod <off|vad|ram|i2s|rami2s>\n" + "cfgtdm [0~496 0~496 0~3]>\n" + "cfgdckV <0.75|1.0|1.2|2.4|3.0>\n" + "cfgdckR <0.75|1.0|1.2|2.4|3.0>\n" + "cfgdckI <0.75|1.0|1.2|2.4|3.0>\n" + "cfgget\n" + "fmul2 <enable|disable>\n" + "vadsens <0~31>\n" + "gain <0~31>", + "wov configuration"); #endif diff --git a/chip/npcx/wov_chip.h b/chip/npcx/wov_chip.h index dce534c501..b0da9128e1 100644 --- a/chip/npcx/wov_chip.h +++ b/chip/npcx/wov_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -34,10 +34,7 @@ enum wov_mic_source { }; /* Clock source for APM. */ -enum wov_clk_src_sel { - WOV_FMUL2_CLK_SRC = 0, - WOV_PLL_CLK_SRC = 1 -}; +enum wov_clk_src_sel { WOV_FMUL2_CLK_SRC = 0, WOV_PLL_CLK_SRC = 1 }; /* FMUL clock division factore. */ enum wov_fmul_div { @@ -48,10 +45,7 @@ enum wov_fmul_div { }; /* Lock state. */ -enum wov_lock_state { - WOV_UNLOCK = 0, - WOV_LOCK = 1 -}; +enum wov_lock_state { WOV_UNLOCK = 0, WOV_LOCK = 1 }; /* Reference clock source select. */ enum wov_ref_clk_src_sel { @@ -60,10 +54,7 @@ enum wov_ref_clk_src_sel { }; /* PLL external divider select. */ -enum wov_ext_div_sel { - WOV_EXT_DIV_BINARY_CNT = 0, - WOV_EXT_DIV_LFSR_DIV = 1 -}; +enum wov_ext_div_sel { WOV_EXT_DIV_BINARY_CNT = 0, WOV_EXT_DIV_LFSR_DIV = 1 }; /* FMUL output frequency. */ enum wov_fmul_out_freq { @@ -117,10 +108,7 @@ enum wov_interrupt_index { }; /* FIFO DMA request selection. */ -enum wov_dma_req_sel { - WOV_DFLT_ESPI_DMA_REQ = 0, - WOV_FROM_FIFO_DMA_REQUEST -}; +enum wov_dma_req_sel { WOV_DFLT_ESPI_DMA_REQ = 0, WOV_FROM_FIFO_DMA_REQUEST }; /* Core FIFO input select. */ enum wov_core_fifo_in_sel { @@ -131,10 +119,7 @@ enum wov_core_fifo_in_sel { }; /* PLL external divider selector. */ -enum wov_pll_ext_div_sel { - WOV_PLL_EXT_DIV_BIN_CNT = 0, - WOV_PLL_EXT_DIV_LFSR -}; +enum wov_pll_ext_div_sel { WOV_PLL_EXT_DIV_BIN_CNT = 0, WOV_PLL_EXT_DIV_LFSR }; /* Code for events for call back function. */ enum wov_events { @@ -144,7 +129,7 @@ enum wov_events { * need to call to wov_set_buffer to update the buffer * pointer */ WOV_EVENT_DATA_READY = 1, - WOV_EVENT_VAD, /* Voice activity detected */ + WOV_EVENT_VAD, /* Voice activity detected */ WOV_EVENT_ERROR_FIRST = 128, WOV_EVENT_ERROR_CORE_FIFO_OVERRUN = 128, @@ -158,8 +143,8 @@ enum wov_events { enum wov_fifo_errors { WOV_FIFO_NO_ERROR = 0, WOV_CORE_FIFO_OVERRUN = 1, /* 2 : I2S FIFO is underrun. */ - WOV_I2S_FIFO_OVERRUN = 2, /* 3 : I2S FIFO is overrun. */ - WOV_I2S_FIFO_UNDERRUN = 3 /* 4 : I2S FIFO is underrun. */ + WOV_I2S_FIFO_OVERRUN = 2, /* 3 : I2S FIFO is overrun. */ + WOV_I2S_FIFO_UNDERRUN = 3 /* 4 : I2S FIFO is underrun. */ }; @@ -191,12 +176,12 @@ enum wov_modes { /* DAI format. */ enum wov_dai_format { - WOV_DAI_FMT_I2S, /* I2S mode */ + WOV_DAI_FMT_I2S, /* I2S mode */ WOV_DAI_FMT_RIGHT_J, /* Right Justified mode */ - WOV_DAI_FMT_LEFT_J, /* Left Justified mode */ - WOV_DAI_FMT_PCM_A, /* PCM A Audio */ - WOV_DAI_FMT_PCM_B, /* PCM B Audio */ - WOV_DAI_FMT_PCM_TDM /* Time Division Multiplexing */ + WOV_DAI_FMT_LEFT_J, /* Left Justified mode */ + WOV_DAI_FMT_PCM_A, /* PCM A Audio */ + WOV_DAI_FMT_PCM_B, /* PCM B Audio */ + WOV_DAI_FMT_PCM_TDM /* Time Division Multiplexing */ }; struct wov_config { @@ -375,10 +360,10 @@ void wov_enable_agc(int enable); * @param min_applied_gain - Minimum Gain Value to apply to the ADC path. * @return EC_ERROR_INVAL or EC_SUCCESS */ -enum ec_error_list wov_set_agc_config(int stereo, float target, - int noise_gate_threshold, uint8_t hold_time, - uint16_t attack_time, uint16_t decay_time, - float max_applied_gain, float min_applied_gain); +enum ec_error_list +wov_set_agc_config(int stereo, float target, int noise_gate_threshold, + uint8_t hold_time, uint16_t attack_time, uint16_t decay_time, + float max_applied_gain, float min_applied_gain); /** * Sets VAD sensitivity. @@ -438,7 +423,7 @@ void wov_set_i2s_bclk(uint32_t i2s_clock); * @return EC error code. */ enum ec_error_list wov_set_i2s_tdm_config(int ch0_delay, int ch1_delay, - uint32_t flags); + uint32_t flags); /** * Configure FMUL2 clock tunning. @@ -477,8 +462,9 @@ extern void wov_set_clk_selection(enum wov_clk_src_sel clk_src); * PLL External Divider Load Values table. * @return EC_ERROR_INVAL or EC_SUCCESS */ -enum ec_error_list wov_pll_clk_ext_div_config( - enum wov_pll_ext_div_sel ext_div_sel, uint32_t div_factor); +enum ec_error_list +wov_pll_clk_ext_div_config(enum wov_pll_ext_div_sel ext_div_sel, + uint32_t div_factor); /** * PLL power down. @@ -498,9 +484,9 @@ void wov_pll_enable(int enable); * @return EC_ERROR_INVAL or EC_SUCCESS */ enum ec_error_list wov_pll_clk_div_config(uint32_t out_div_1, - uint32_t out_div_2, - uint32_t feedback_div, - uint32_t in_div); + uint32_t out_div_2, + uint32_t feedback_div, + uint32_t in_div); /** * Enables/Disables WoV interrupt. @@ -521,7 +507,7 @@ void wov_interrupt_enable(enum wov_interrupt_index int_index, int enable); * @return None */ void wov_cfifo_config(enum wov_core_fifo_in_sel in_sel, - enum wov_fifo_threshold threshold); + enum wov_fifo_threshold threshold); /** * Start the actual capturing of the Voice data to the RAM. @@ -632,13 +618,10 @@ void wov_handle_event(enum wov_events event); * @return EC_ERROR_INVAL or EC_SUCCESS */ enum ec_error_list wov_i2s_global_config( - enum wov_floating_mode i2s_hiz_data, - enum wov_floating_mode i2s_hiz, - enum wov_clk_inverted_mode clk_invert, - int out_pull_en, enum wov_pull_upd_down_sel out_pull_mode, - int in_pull_en, - enum wov_pull_upd_down_sel in_pull_mode, - enum wov_test_mode test_mode); + enum wov_floating_mode i2s_hiz_data, enum wov_floating_mode i2s_hiz, + enum wov_clk_inverted_mode clk_invert, int out_pull_en, + enum wov_pull_upd_down_sel out_pull_mode, int in_pull_en, + enum wov_pull_upd_down_sel in_pull_mode, enum wov_test_mode test_mode); /** * I2S channel configuration @@ -652,7 +635,8 @@ enum ec_error_list wov_i2s_global_config( * @return EC_ERROR_INVAL or EC_SUCCESS */ enum ec_error_list wov_i2s_channel_config(uint32_t channel_num, - uint32_t bit_count, enum wov_i2s_chan_trigger trigger, - int32_t start_delay); + uint32_t bit_count, + enum wov_i2s_chan_trigger trigger, + int32_t start_delay); #endif /* __CROS_EC_WOV_CHIP_H */ |