diff options
Diffstat (limited to 'chip/npcx/i2c.c')
| -rw-r--r-- | chip/npcx/i2c.c | 310 |
1 files changed, 168 insertions, 142 deletions
diff --git a/chip/npcx/i2c.c b/chip/npcx/i2c.c index a7c389f1b3..ebfba26c58 100644 --- a/chip/npcx/i2c.c +++ b/chip/npcx/i2c.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -24,8 +24,8 @@ #define CPRINTF(...) #else #define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args) #endif /* Timeout for device should be available after reset (SMBus spec. unit:ms) */ @@ -41,54 +41,54 @@ * I2C module that supports FIFO mode has 32 bytes Tx FIFO and * 32 bytes Rx FIFO. */ -#define NPCX_I2C_FIFO_MAX_SIZE 32 +#define NPCX_I2C_FIFO_MAX_SIZE 32 /* Macro functions of I2C */ #define I2C_START(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_START) -#define I2C_STOP(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_STOP) -#define I2C_NACK(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_ACK) +#define I2C_STOP(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_STOP) +#define I2C_NACK(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_ACK) /* I2C module automatically stall bus after sending peripheral address */ #define I2C_STALL(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_STASTRE) #define I2C_WRITE_BYTE(ctrl, data) (NPCX_SMBSDA(ctrl) = data) -#define I2C_READ_BYTE(ctrl, data) (data = NPCX_SMBSDA(ctrl)) +#define I2C_READ_BYTE(ctrl, data) (data = NPCX_SMBSDA(ctrl)) #define I2C_TX_FIFO_OCCUPIED(ctrl) (NPCX_SMBTXF_STS(ctrl) & 0x3F) #define I2C_TX_FIFO_AVAILABLE(ctrl) \ - (NPCX_I2C_FIFO_MAX_SIZE - I2C_TX_FIFO_OCCUPIED(ctrl)) + (NPCX_I2C_FIFO_MAX_SIZE - I2C_TX_FIFO_OCCUPIED(ctrl)) #define I2C_RX_FIFO_OCCUPIED(ctrl) (NPCX_SMBRXF_STS(ctrl) & 0x3F) #define I2C_RX_FIFO_AVAILABLE(ctrl) \ - (NPCX_I2C_FIFO_MAX_SIZE - I2C_RX_FIFO_OCCUPIED(ctrl)) + (NPCX_I2C_FIFO_MAX_SIZE - I2C_RX_FIFO_OCCUPIED(ctrl)) /* Drive the SCL signal to low */ -#define I2C_SCL_STALL(ctrl) \ - (NPCX_SMBCTL3(ctrl) = \ - (NPCX_SMBCTL3(ctrl) & ~BIT(NPCX_SMBCTL3_SCL_LVL)) | \ - BIT(NPCX_SMBCTL3_SDA_LVL)) +#define I2C_SCL_STALL(ctrl) \ + (NPCX_SMBCTL3(ctrl) = \ + (NPCX_SMBCTL3(ctrl) & ~BIT(NPCX_SMBCTL3_SCL_LVL)) | \ + BIT(NPCX_SMBCTL3_SDA_LVL)) /* * Release the SCL signal to be pulled up to high level. * Note: The SCL might be still driven low either by I2C module or external * devices connected to ths bus. */ -#define I2C_SCL_FREE(ctrl) \ - (NPCX_SMBCTL3(ctrl) |= BIT(NPCX_SMBCTL3_SCL_LVL) | \ - BIT(NPCX_SMBCTL3_SDA_LVL)) +#define I2C_SCL_FREE(ctrl) \ + (NPCX_SMBCTL3(ctrl) |= BIT(NPCX_SMBCTL3_SCL_LVL) | \ + BIT(NPCX_SMBCTL3_SDA_LVL)) /* Error values that functions can return */ enum smb_error { - SMB_OK = 0, /* No error */ - SMB_CH_OCCUPIED, /* Channel is already occupied */ - SMB_MEM_POOL_INIT_ERROR, /* Memory pool initialization error */ - SMB_BUS_FREQ_ERROR, /* SMbus freq was not valid */ - SMB_INVLAID_REGVALUE, /* Invalid SMbus register value */ - SMB_UNEXIST_CH_ERROR, /* Channel does not exist */ - SMB_NO_SUPPORT_PTL, /* Not support SMBus Protocol */ - SMB_BUS_ERROR, /* Encounter bus error */ - SMB_NO_ADDRESS_MATCH, /* No peripheral address match */ - /* (Controller Mode) */ - SMB_READ_DATA_ERROR, /* Read data for SDA error */ - SMB_READ_OVERFLOW_ERROR, /* Read data over than we predict */ - SMB_TIMEOUT_ERROR, /* Timeout expired */ - SMB_MODULE_ISBUSY, /* Module is occupied by other device */ - SMB_BUS_BUSY, /* SMBus is occupied by other device */ + SMB_OK = 0, /* No error */ + SMB_CH_OCCUPIED, /* Channel is already occupied */ + SMB_MEM_POOL_INIT_ERROR, /* Memory pool initialization error */ + SMB_BUS_FREQ_ERROR, /* SMbus freq was not valid */ + SMB_INVLAID_REGVALUE, /* Invalid SMbus register value */ + SMB_UNEXIST_CH_ERROR, /* Channel does not exist */ + SMB_NO_SUPPORT_PTL, /* Not support SMBus Protocol */ + SMB_BUS_ERROR, /* Encounter bus error */ + SMB_NO_ADDRESS_MATCH, /* No peripheral address match */ + /* (Controller Mode) */ + SMB_READ_DATA_ERROR, /* Read data for SDA error */ + SMB_READ_OVERFLOW_ERROR, /* Read data over than we predict */ + SMB_TIMEOUT_ERROR, /* Timeout expired */ + SMB_MODULE_ISBUSY, /* Module is occupied by other device */ + SMB_BUS_BUSY, /* SMBus is occupied by other device */ }; /* @@ -108,18 +108,18 @@ enum smb_oper_state_t { /* I2C controller state data */ struct i2c_status { - int flags; /* Flags (I2C_XFER_*) */ - const uint8_t *tx_buf; /* Entry pointer of transmit buffer */ - uint8_t *rx_buf; /* Entry pointer of receive buffer */ - uint16_t sz_txbuf; /* Size of Tx buffer in bytes */ - uint16_t sz_rxbuf; /* Size of rx buffer in bytes */ - uint16_t idx_buf; /* Current index of Tx/Rx buffer */ - uint16_t addr_flags;/* Target address */ - enum smb_oper_state_t oper_state;/* Smbus operation state */ - enum smb_error err_code; /* Error code */ - int task_waiting; /* Task waiting on controller */ - uint32_t timeout_us;/* Transaction timeout */ - uint16_t kbps; /* Speed */ + int flags; /* Flags (I2C_XFER_*) */ + const uint8_t *tx_buf; /* Entry pointer of transmit buffer */ + uint8_t *rx_buf; /* Entry pointer of receive buffer */ + uint16_t sz_txbuf; /* Size of Tx buffer in bytes */ + uint16_t sz_rxbuf; /* Size of rx buffer in bytes */ + uint16_t idx_buf; /* Current index of Tx/Rx buffer */ + uint16_t addr_flags; /* Target address */ + enum smb_oper_state_t oper_state; /* Smbus operation state */ + enum smb_error err_code; /* Error code */ + int task_waiting; /* Task waiting on controller */ + uint32_t timeout_us; /* Transaction timeout */ + uint16_t kbps; /* Speed */ }; /* I2C controller state data array */ static struct i2c_status i2c_stsobjs[I2C_CONTROLLER_COUNT]; @@ -127,27 +127,29 @@ static struct i2c_status i2c_stsobjs[I2C_CONTROLLER_COUNT]; /* I2C timing setting */ struct i2c_timing { uint8_t clock; /* I2C source clock. (Unit: MHz)*/ - uint8_t HLDT; /* I2C hold-time. (Unit: clocks) */ - uint8_t k1; /* k1 = SCL low-time (Unit: clocks) */ - uint8_t k2; /* k2 = SCL high-time (Unit: clocks) */ + uint8_t HLDT; /* I2C hold-time. (Unit: clocks) */ + uint8_t k1; /* k1 = SCL low-time (Unit: clocks) */ + uint8_t k2; /* k2 = SCL high-time (Unit: clocks) */ }; /* I2C timing setting array of 400K & 1M Hz */ static const struct i2c_timing i2c_400k_timings[] = { - {20, 7, 32, 22}, - {15, 7, 24, 18},}; + { 20, 7, 32, 22 }, + { 15, 7, 24, 18 }, +}; const unsigned int i2c_400k_timing_used = ARRAY_SIZE(i2c_400k_timings); static const struct i2c_timing i2c_1m_timings[] = { - {20, 7, 16, 10}, - {15, 7, 14, 10},}; + { 20, 7, 16, 10 }, + { 15, 7, 14, 10 }, +}; const unsigned int i2c_1m_timing_used = ARRAY_SIZE(i2c_1m_timings); /* IRQ for each port */ const uint32_t i2c_irqs[I2C_CONTROLLER_COUNT] = { - NPCX_IRQ_SMB1, NPCX_IRQ_SMB2, NPCX_IRQ_SMB3, NPCX_IRQ_SMB4, + NPCX_IRQ_SMB1, NPCX_IRQ_SMB2, NPCX_IRQ_SMB3, NPCX_IRQ_SMB4, #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7 - NPCX_IRQ_SMB5, NPCX_IRQ_SMB6, NPCX_IRQ_SMB7, NPCX_IRQ_SMB8, + NPCX_IRQ_SMB5, NPCX_IRQ_SMB6, NPCX_IRQ_SMB7, NPCX_IRQ_SMB8, #endif }; BUILD_ASSERT(ARRAY_SIZE(i2c_irqs) == I2C_CONTROLLER_COUNT); @@ -198,8 +200,8 @@ static void i2c_abort_data(int controller) SET_BIT(NPCX_SMBST(controller), NPCX_SMBST_NEGACK); /* Wait till STOP condition is generated */ - if (i2c_wait_stop_completed(controller, I2C_MAX_TIMEOUT) - != EC_SUCCESS) { + if (i2c_wait_stop_completed(controller, I2C_MAX_TIMEOUT) != + EC_SUCCESS) { cprintf(CC_I2C, "Abort i2c %02x fail!\n", controller); /* Clear BB (BUS BUSY) bit */ SET_BIT(NPCX_SMBCST(controller), NPCX_SMBCST_BB); @@ -219,8 +221,9 @@ static int i2c_reset(int controller) while (--timeout) { /* WAIT FOR SCL & SDA IS HIGH */ - if (IS_BIT_SET(NPCX_SMBCTL3(controller), NPCX_SMBCTL3_SCL_LVL) - && IS_BIT_SET(NPCX_SMBCTL3(controller), NPCX_SMBCTL3_SDA_LVL)) + if (IS_BIT_SET(NPCX_SMBCTL3(controller), + NPCX_SMBCTL3_SCL_LVL) && + IS_BIT_SET(NPCX_SMBCTL3(controller), NPCX_SMBCTL3_SDA_LVL)) break; msleep(1); } @@ -306,9 +309,8 @@ static void i2c_fifo_write_data(int controller) } for (i = 0; i < len; i++) { I2C_WRITE_BYTE(controller, - p_status->tx_buf[p_status->idx_buf++]); - CPRINTF("%02x ", - p_status->tx_buf[p_status->idx_buf - 1]); + p_status->tx_buf[p_status->idx_buf++]); + CPRINTF("%02x ", p_status->tx_buf[p_status->idx_buf - 1]); } CPRINTF("\n"); } @@ -355,7 +357,7 @@ enum smb_error i2c_controller_transaction(int controller) * is set simultaneously. */ if (p_status->sz_rxbuf == 1 && - (p_status->flags & I2C_XFER_STOP)) { + (p_status->flags & I2C_XFER_STOP)) { /* * Since SCL is released after reading last * byte from previous transaction, adding a @@ -375,30 +377,30 @@ enum smb_error i2c_controller_transaction(int controller) } } else cprintf(CC_I2C, "Unexpected i2c state machine! %d\n", - p_status->oper_state); + p_status->oper_state); if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) { if (p_status->sz_rxbuf > 0) { if (p_status->sz_rxbuf > NPCX_I2C_FIFO_MAX_SIZE) { /* Set RX threshold = FIFO_MAX_SIZE */ SET_FIELD(NPCX_SMBRXF_CTL(controller), - NPCX_SMBRXF_CTL_RX_THR, - NPCX_I2C_FIFO_MAX_SIZE); + NPCX_SMBRXF_CTL_RX_THR, + NPCX_I2C_FIFO_MAX_SIZE); } else { /* * set RX threshold = remaining data bytes * (it should be <= FIFO_MAX_SIZE) */ SET_FIELD(NPCX_SMBRXF_CTL(controller), - NPCX_SMBRXF_CTL_RX_THR, - p_status->sz_rxbuf); + NPCX_SMBRXF_CTL_RX_THR, + p_status->sz_rxbuf); /* * Set LAST bit generate the NACK at the * last byte of the data group in FIFO */ if (p_status->flags & I2C_XFER_STOP) { SET_BIT(NPCX_SMBRXF_CTL(controller), - NPCX_SMBRXF_CTL_LAST); + NPCX_SMBRXF_CTL_LAST); } } @@ -412,7 +414,7 @@ enum smb_error i2c_controller_transaction(int controller) /* Generate a START condition */ if (p_status->oper_state == SMB_CONTROLLER_START || - p_status->oper_state == SMB_REPEAT_START) { + p_status->oper_state == SMB_REPEAT_START) { I2C_START(controller); CPUTS("ST"); } @@ -421,8 +423,8 @@ enum smb_error i2c_controller_transaction(int controller) task_enable_irq(i2c_irqs[controller]); /* Wait for transfer complete or timeout */ - events = task_wait_event_mask(TASK_EVENT_I2C_IDLE, - p_status->timeout_us); + events = + task_wait_event_mask(TASK_EVENT_I2C_IDLE, p_status->timeout_us); /* Disable event and error interrupts */ task_disable_irq(i2c_irqs[controller]); @@ -452,8 +454,9 @@ enum smb_error i2c_controller_transaction(int controller) i2c_recovery(controller, p_status); /* Wait till STOP condition is generated for normal transaction */ - if (p_status->err_code == SMB_OK && i2c_wait_stop_completed(controller, - I2C_MIN_TIMEOUT) != EC_SUCCESS) { + if (p_status->err_code == SMB_OK && + i2c_wait_stop_completed(controller, I2C_MIN_TIMEOUT) != + EC_SUCCESS) { cprintf(CC_I2C, "STOP fail! scl %02x is held by slave device!\n", controller); @@ -476,7 +479,7 @@ void i2c_done(int controller) /* Clear RXF_TXE bit (RX FIFO full/TX FIFO empty) */ if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) NPCX_SMBFIF_CTS(controller) = - BIT(NPCX_SMBFIF_CTS_RXF_TXE); + BIT(NPCX_SMBFIF_CTS_RXF_TXE); /* Clear SDAST by writing mock byte */ I2C_WRITE_BYTE(controller, 0xFF); @@ -485,8 +488,9 @@ void i2c_done(int controller) /* Set error code */ p_status->err_code = SMB_OK; /* Set SMB status if we need stall bus */ - p_status->oper_state = (p_status->flags & I2C_XFER_STOP) - ? SMB_IDLE : SMB_WRITE_SUSPEND; + p_status->oper_state = (p_status->flags & I2C_XFER_STOP) ? + SMB_IDLE : + SMB_WRITE_SUSPEND; /* * Disable interrupt for i2c controller stall SCL * and forbid SDAST generate interrupt @@ -540,7 +544,7 @@ static void i2c_handle_receive(int controller) /* Read to buf. Skip last byte if meet SMB_FAKE_READ_OPER */ if (p_status->oper_state == SMB_FAKE_READ_OPER && - p_status->idx_buf == (p_status->sz_rxbuf - 1)) + p_status->idx_buf == (p_status->sz_rxbuf - 1)) p_status->idx_buf++; else p_status->rx_buf[p_status->idx_buf++] = data; @@ -548,8 +552,9 @@ static void i2c_handle_receive(int controller) /* last byte is read - end of transaction */ if (p_status->idx_buf == p_status->sz_rxbuf) { /* Set current status */ - p_status->oper_state = (p_status->flags & I2C_XFER_STOP) - ? SMB_IDLE : SMB_READ_SUSPEND; + p_status->oper_state = (p_status->flags & I2C_XFER_STOP) ? + SMB_IDLE : + SMB_READ_SUSPEND; /* Set error code */ p_status->err_code = SMB_OK; /* Notify upper layer of missing data */ @@ -623,35 +628,33 @@ static void i2c_fifo_handle_receive(int controller) if (remaining_bytes > 0) { if (remaining_bytes > NPCX_I2C_FIFO_MAX_SIZE) { SET_FIELD(NPCX_SMBRXF_CTL(controller), - NPCX_SMBRXF_CTL_RX_THR, - NPCX_I2C_FIFO_MAX_SIZE); + NPCX_SMBRXF_CTL_RX_THR, + NPCX_I2C_FIFO_MAX_SIZE); } else { SET_FIELD(NPCX_SMBRXF_CTL(controller), - NPCX_SMBRXF_CTL_RX_THR, - remaining_bytes); + NPCX_SMBRXF_CTL_RX_THR, + remaining_bytes); if (p_status->flags & I2C_XFER_STOP) { SET_BIT(NPCX_SMBRXF_CTL(controller), - NPCX_SMBRXF_CTL_LAST); + NPCX_SMBRXF_CTL_LAST); CPRINTS("-FGNA"); } } - } i2c_stall_bus(controller, 0); - } /* last byte is read - end of transaction */ if (p_status->idx_buf == p_status->sz_rxbuf) { /* Set current status */ - p_status->oper_state = (p_status->flags & I2C_XFER_STOP) - ? SMB_IDLE : SMB_READ_SUSPEND; + p_status->oper_state = (p_status->flags & I2C_XFER_STOP) ? + SMB_IDLE : + SMB_READ_SUSPEND; /* Set error code */ p_status->err_code = SMB_OK; /* Notify upper layer of missing data */ task_set_event(p_status->task_waiting, TASK_EVENT_I2C_IDLE); CPUTS("-END"); } - } static void i2c_handle_sda_irq(int controller) @@ -660,10 +663,10 @@ static void i2c_handle_sda_irq(int controller) uint8_t addr_8bit = I2C_STRIP_FLAGS(p_status->addr_flags) << 1; /* 1 Issue Start is successful ie. write address byte */ - if (p_status->oper_state == SMB_CONTROLLER_START - || p_status->oper_state == SMB_REPEAT_START) { + if (p_status->oper_state == SMB_CONTROLLER_START || + p_status->oper_state == SMB_REPEAT_START) { /* Prepare address byte */ - if (p_status->sz_txbuf == 0) {/* Receive mode */ + if (p_status->sz_txbuf == 0) { /* Receive mode */ p_status->oper_state = SMB_READ_OPER; /* * Receiving one or zero bytes - stall bus after @@ -676,7 +679,7 @@ static void i2c_handle_sda_irq(int controller) /* Write the address to the bus R bit*/ I2C_WRITE_BYTE(controller, (addr_8bit | 0x1)); CPRINTS("-ARR-0x%02x", addr_8bit); - } else {/* Transmit mode */ + } else { /* Transmit mode */ p_status->oper_state = SMB_WRITE_OPER; /* Write the address to the bus W bit*/ I2C_WRITE_BYTE(controller, addr_8bit); @@ -720,14 +723,13 @@ static void i2c_handle_sda_irq(int controller) * in the SMBnTXF_CTL register. */ if (p_status->sz_rxbuf == 1 && - (p_status->flags & I2C_XFER_STOP) && - !IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) { + (p_status->flags & I2C_XFER_STOP) && + !IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) { I2C_NACK(controller); CPUTS("-GNA"); } /* Write the address to the bus R bit*/ - I2C_WRITE_BYTE(controller, - (addr_8bit | 0x1)); + I2C_WRITE_BYTE(controller, (addr_8bit | 0x1)); CPUTS("-ARR"); } } @@ -749,7 +751,7 @@ static void i2c_handle_sda_irq(int controller) * operation) */ else if (p_status->oper_state == SMB_READ_OPER || - p_status->oper_state == SMB_FAKE_READ_OPER) { + p_status->oper_state == SMB_FAKE_READ_OPER) { if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) i2c_fifo_handle_receive(controller); else @@ -826,7 +828,7 @@ static void i2c_controller_int_handler(int controller) * register. */ else if ((p_status->flags & I2C_XFER_STOP) && - !IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) { + !IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) { I2C_NACK(controller); } @@ -840,9 +842,10 @@ static void i2c_controller_int_handler(int controller) #if DEBUG_I2C /* SDAST still issued with unexpected state machine */ if (IS_BIT_SET(NPCX_SMBST(controller), NPCX_SMBST_SDAST) && - p_status->oper_state != SMB_WRITE_SUSPEND) { + p_status->oper_state != SMB_WRITE_SUSPEND) { cprints(CC_I2C, "i2c %d unknown state %d, error %d\n", - controller, p_status->oper_state, p_status->err_code); + controller, p_status->oper_state, + p_status->err_code); } #endif } @@ -858,15 +861,39 @@ void handle_interrupt(int controller) i2c_controller_int_handler(controller); } -static void i2c0_interrupt(void) { handle_interrupt(0); } -static void i2c1_interrupt(void) { handle_interrupt(1); } -static void i2c2_interrupt(void) { handle_interrupt(2); } -static void i2c3_interrupt(void) { handle_interrupt(3); } +static void i2c0_interrupt(void) +{ + handle_interrupt(0); +} +static void i2c1_interrupt(void) +{ + handle_interrupt(1); +} +static void i2c2_interrupt(void) +{ + handle_interrupt(2); +} +static void i2c3_interrupt(void) +{ + handle_interrupt(3); +} #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7 -static void i2c4_interrupt(void) { handle_interrupt(4); } -static void i2c5_interrupt(void) { handle_interrupt(5); } -static void i2c6_interrupt(void) { handle_interrupt(6); } -static void i2c7_interrupt(void) { handle_interrupt(7); } +static void i2c4_interrupt(void) +{ + handle_interrupt(4); +} +static void i2c5_interrupt(void) +{ + handle_interrupt(5); +} +static void i2c6_interrupt(void) +{ + handle_interrupt(6); +} +static void i2c7_interrupt(void) +{ + handle_interrupt(7); +} #endif DECLARE_IRQ(NPCX_IRQ_SMB1, i2c0_interrupt, 4); @@ -892,14 +919,12 @@ void i2c_set_timeout(int port, uint32_t timeout) return; /* Param is port, but timeout is stored by-controller. */ - i2c_stsobjs[ctrl].timeout_us = - timeout ? timeout : I2C_TIMEOUT_DEFAULT_US; + i2c_stsobjs[ctrl].timeout_us = timeout ? timeout : + I2C_TIMEOUT_DEFAULT_US; } -int chip_i2c_xfer(const int port, - const uint16_t addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags) +int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out, + int out_size, uint8_t *in, int in_size, int flags) { volatile struct i2c_status *p_status; int ctrl = i2c_port_to_controller(port); @@ -921,23 +946,23 @@ int chip_i2c_xfer(const int port, i2c_select_port(port); /* Copy data to controller struct */ - p_status->flags = flags; - p_status->tx_buf = out; - p_status->sz_txbuf = out_size; - p_status->rx_buf = in; - p_status->sz_rxbuf = in_size; + p_status->flags = flags; + p_status->tx_buf = out; + p_status->sz_txbuf = out_size; + p_status->rx_buf = in; + p_status->sz_rxbuf = in_size; p_status->addr_flags = addr_flags; /* Reset index & error */ - p_status->idx_buf = 0; - p_status->err_code = SMB_OK; + p_status->idx_buf = 0; + p_status->err_code = SMB_OK; /* Make sure we're in a good state to start */ if ((flags & I2C_XFER_START) && - /* Ignore busy bus for repeated start */ - p_status->oper_state != SMB_WRITE_SUSPEND && - (i2c_bus_busy(ctrl) - || (i2c_get_line_levels(port) != I2C_LINE_IDLE))) { + /* Ignore busy bus for repeated start */ + p_status->oper_state != SMB_WRITE_SUSPEND && + (i2c_bus_busy(ctrl) || + (i2c_get_line_levels(port) != I2C_LINE_IDLE))) { int ret; /* Attempt to unwedge the i2c port */ @@ -974,7 +999,7 @@ int chip_i2c_xfer(const int port, int i2c_get_line_levels(int port) { return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) | - (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); + (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); } int i2c_raw_get_scl(int port) @@ -989,8 +1014,9 @@ int i2c_raw_get_scl(int port) if (i2c_is_raw_mode(port)) return gpio_get_level(g); else - return IS_BIT_SET(NPCX_SMBCTL3( - i2c_port_to_controller(port)), NPCX_SMBCTL3_SCL_LVL); + return IS_BIT_SET( + NPCX_SMBCTL3(i2c_port_to_controller(port)), + NPCX_SMBCTL3_SCL_LVL); } /* If no SCL pin defined for this port, then return 1 to appear idle */ @@ -1009,11 +1035,11 @@ int i2c_raw_get_sda(int port) if (i2c_is_raw_mode(port)) return gpio_get_level(g); else - return IS_BIT_SET(NPCX_SMBCTL3( - i2c_port_to_controller(port)), NPCX_SMBCTL3_SDA_LVL); + return IS_BIT_SET( + NPCX_SMBCTL3(i2c_port_to_controller(port)), + NPCX_SMBCTL3_SDA_LVL); } - /* If no SDA pin defined for this port, then return 1 to appear idle */ return 1; } @@ -1032,8 +1058,8 @@ static void i2c_port_set_freq(const int ctrl, const int bus_freq_kbps) * SMB0/1/4/5/6/7 use APB3 clock * SMB2/3 use APB2 clock */ - freq = (ctrl < 2 || ctrl > 3) ? - clock_get_apb3_freq() : clock_get_apb2_freq(); + freq = (ctrl < 2 || ctrl > 3) ? clock_get_apb3_freq() : + clock_get_apb2_freq(); #else /* CHIP_FAMILY_NPCX5 */ /* * SMB0/1 use core clock @@ -1051,7 +1077,7 @@ static void i2c_port_set_freq(const int ctrl, const int bus_freq_kbps) * fSCL = fCLK / (4*SCLFRQ) * SCLFRQ = ceil(fCLK/(4*fSCL)) */ - scl_freq = DIV_ROUND_UP(freq, bus_freq_kbps*4000); /* Unit in bps */ + scl_freq = DIV_ROUND_UP(freq, bus_freq_kbps * 4000); /* Unit in bps */ /* Normal mode if I2C freq is under 100kHz */ if (bus_freq_kbps <= 100) { @@ -1089,19 +1115,19 @@ static void i2c_port_set_freq(const int ctrl, const int bus_freq_kbps) } for (j = 0; j < i2c_timing_used; j++, pTiming++) { - if (pTiming->clock == (freq/SECOND)) { + if (pTiming->clock == (freq / SECOND)) { i2c_stsobjs[ctrl].kbps = bus_freq_kbps; /* Set SCLH(L)T and hold-time */ - NPCX_SMBSCLLT(ctrl) = pTiming->k1/2; - NPCX_SMBSCLHT(ctrl) = pTiming->k2/2; - SET_FIELD(NPCX_SMBCTL4(ctrl), - NPCX_SMBCTL4_HLDT_FIELD, pTiming->HLDT); + NPCX_SMBSCLLT(ctrl) = pTiming->k1 / 2; + NPCX_SMBSCLHT(ctrl) = pTiming->k2 / 2; + SET_FIELD(NPCX_SMBCTL4(ctrl), NPCX_SMBCTL4_HLDT_FIELD, + pTiming->HLDT); break; } } if (j == i2c_timing_used) - cprints(CC_I2C, "Error: I2C %d: src clk %d not supported", - ctrl, freq / SECOND); + cprints(CC_I2C, "Error: I2C %d: src clk %d not supported", ctrl, + freq / SECOND); } /* Hooks */ @@ -1187,10 +1213,10 @@ void i2c_init(void) /* Enable clock for I2C peripheral */ clock_enable_peripheral(CGC_OFFSET_I2C, CGC_I2C_MASK, - CGC_MODE_RUN | CGC_MODE_SLEEP); + CGC_MODE_RUN | CGC_MODE_SLEEP); #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7 clock_enable_peripheral(CGC_OFFSET_I2C2, CGC_I2C_MASK2, - CGC_MODE_RUN | CGC_MODE_SLEEP); + CGC_MODE_RUN | CGC_MODE_SLEEP); #endif /* Set I2C freq */ |