diff options
Diffstat (limited to 'chip/npcx/system-npcx7.c')
| -rw-r--r-- | chip/npcx/system-npcx7.c | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/chip/npcx/system-npcx7.c b/chip/npcx/system-npcx7.c index abbb6755c3..5cacbec749 100644 --- a/chip/npcx/system-npcx7.c +++ b/chip/npcx/system-npcx7.c @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -6,6 +6,7 @@ #include <stdnoreturn.h> /* System module driver depends on chip series for Chrome EC */ +#include "builtin/assert.h" #include "common.h" #include "console.h" #include "cpu.h" @@ -21,13 +22,13 @@ #include "system_chip.h" #include "rom_chip.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) /* Macros for last 32K ram block */ #define LAST_RAM_BLK ((NPCX_RAM_SIZE / (32 * 1024)) - 1) /* Higher bits are reserved and need to be masked */ -#define RAM_PD_MASK (~BIT(LAST_RAM_BLK)) +#define RAM_PD_MASK (~BIT(LAST_RAM_BLK)) /*****************************************************************************/ /* IC specific low-level driver depends on chip series */ @@ -83,11 +84,11 @@ void system_enter_psl_mode(void) NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_PSL; #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9 - /* - * If pulse mode is enabled, the VCC power is turned off by the - * external component (Ex: PMIC) but PSL_OUT. So we can just return - * here. - */ + /* + * If pulse mode is enabled, the VCC power is turned off by the + * external component (Ex: PMIC) but PSL_OUT. So we can just return + * here. + */ if (IS_BIT_SET(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_PLS_EN)) return; #endif @@ -113,8 +114,7 @@ static void system_psl_type_sel(enum psl_pin_t psl_pin, uint32_t flags) /* Set PSL input events' type as level or edge trigger */ if ((flags & GPIO_INT_F_HIGH) || (flags & GPIO_INT_F_LOW)) CLEAR_BIT(NPCX_GLUE_PSL_CTS, psl_pin + 4); - else if ((flags & GPIO_INT_F_RISING) || - (flags & GPIO_INT_F_FALLING)) + else if ((flags & GPIO_INT_F_RISING) || (flags & GPIO_INT_F_FALLING)) SET_BIT(NPCX_GLUE_PSL_CTS, psl_pin + 4); /* @@ -145,7 +145,7 @@ int system_config_psl_mode(enum gpio_signal signal) * Hibernate function in last 32K ram block for npcx7 series. * Do not use global variable since we also turn off data ram. */ -noreturn void __keep __attribute__ ((section(".after_init"))) +noreturn void __keep __attribute__((section(".after_init"))) __enter_hibernate_in_last_block(void) { /* @@ -164,7 +164,7 @@ __enter_hibernate_in_last_block(void) NPCX_PMCSR = 0x6; /* Enter deep idle, wake-up by GPIOs or RTC */ - asm volatile ("wfi"); + asm volatile("wfi"); /* RTC wake-up */ if (IS_BIT_SET(NPCX_WTC, NPCX_WTC_PTO)) @@ -208,8 +208,8 @@ void __hibernate_npcx_series(void) __enter_hibernate_in_psl(); #else /* Make sure this is located in the last 32K code RAM block */ - ASSERT((uint32_t)(&__after_init_end) - CONFIG_PROGRAM_MEMORY_BASE - < (32*1024)); + ASSERT((uint32_t)(&__after_init_end) - CONFIG_PROGRAM_MEMORY_BASE < + (32 * 1024)); /* Execute hibernate func in last 32K block */ __enter_hibernate_in_last_block(); |