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Diffstat (limited to 'chip/stm32/i2c-stm32l4.c')
-rw-r--r--chip/stm32/i2c-stm32l4.c72
1 files changed, 36 insertions, 36 deletions
diff --git a/chip/stm32/i2c-stm32l4.c b/chip/stm32/i2c-stm32l4.c
index f7d311ba87..eeb87ec4e0 100644
--- a/chip/stm32/i2c-stm32l4.c
+++ b/chip/stm32/i2c-stm32l4.c
@@ -1,8 +1,9 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
+#include "builtin/assert.h"
#include "printf.h"
#include "chipset.h"
#include "clock.h"
@@ -21,13 +22,13 @@
/* Console output macros */
#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
/* Transmit timeout in microseconds */
-#define I2C_TX_TIMEOUT_MASTER (10 * MSEC)
+#define I2C_TX_TIMEOUT_MASTER (10 * MSEC)
#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-#define I2C_SLAVE_ERROR_CODE 0xec
+#define I2C_SLAVE_ERROR_CODE 0xec
#if (I2C_PORT_EC == STM32_I2C1_PORT)
#define IRQ_SLAVE STM32_IRQ_I2C1
#else
@@ -37,8 +38,8 @@
/* I2C port state data */
struct i2c_port_data {
- uint32_t timeout_us; /* Transaction timeout, or 0 to use default */
- enum i2c_freq freq; /* Port clock speed */
+ uint32_t timeout_us; /* Transaction timeout, or 0 to use default */
+ enum i2c_freq freq; /* Port clock speed */
};
static struct i2c_port_data pdata[I2C_PORT_COUNT];
@@ -50,8 +51,8 @@ void i2c_set_timeout(int port, uint32_t timeout)
/* timing register values for supported input clks / i2c clk rates */
static const uint32_t busyloop_us[I2C_FREQ_COUNT] = {
[I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */
- [I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */
- [I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */
+ [I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */
+ [I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */
};
/**
@@ -70,7 +71,7 @@ static int wait_isr(int port, int mask)
/* Check for errors */
if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR |
- STM32_I2C_ISR_NACK))
+ STM32_I2C_ISR_NACK))
return EC_ERROR_UNKNOWN;
/* Check for desired mask */
@@ -115,8 +116,7 @@ static const uint32_t timingr_regs[I2C_CLK_SRC_COUNT][I2C_FREQ_COUNT] = {
};
static void i2c_set_freq_port(const struct i2c_port_t *p,
- enum stm32_i2c_clk_src src,
- enum i2c_freq freq)
+ enum stm32_i2c_clk_src src, enum i2c_freq freq)
{
int port = p->port;
@@ -209,8 +209,8 @@ static void i2c_event_handler(int port)
STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
/* Clear error status bits */
- STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF
- | STM32_I2C_ICR_ARLOCF;
+ STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF |
+ STM32_I2C_ICR_ARLOCF;
}
/* Transfer matched our slave address */
@@ -286,8 +286,8 @@ static void i2c_event_handler(int port)
STM32_I2C_TXDR(port) =
slave_buffer[tx_idx++];
} else {
- STM32_I2C_TXDR(port)
- = I2C_SLAVE_ERROR_CODE;
+ STM32_I2C_TXDR(port) =
+ I2C_SLAVE_ERROR_CODE;
tx_idx = 0;
tx_end = 0;
tx_pending = 0;
@@ -309,9 +309,8 @@ DECLARE_IRQ(IRQ_SLAVE, i2c_event_interrupt, 2);
/*****************************************************************************/
/* Interface */
-int chip_i2c_xfer(const int port, const uint16_t addr_flags,
- const uint8_t *out, int out_bytes,
- uint8_t *in, int in_bytes, int flags)
+int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+ int out_bytes, uint8_t *in, int in_bytes, int flags)
{
int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
int rv = EC_SUCCESS;
@@ -335,13 +334,13 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags,
* if we are not stopping, set RELOAD bit so that we can load
* NBYTES again. if we are starting, then set START bit.
*/
- STM32_I2C_CR2(port) = ((out_bytes & 0xFF) << 16)
- | addr_8bit
- | ((in_bytes == 0 && xfer_stop) ?
- STM32_I2C_CR2_AUTOEND : 0)
- | ((in_bytes == 0 && !xfer_stop) ?
- STM32_I2C_CR2_RELOAD : 0)
- | (xfer_start ? STM32_I2C_CR2_START : 0);
+ STM32_I2C_CR2(port) =
+ ((out_bytes & 0xFF) << 16) | addr_8bit |
+ ((in_bytes == 0 && xfer_stop) ? STM32_I2C_CR2_AUTOEND :
+ 0) |
+ ((in_bytes == 0 && !xfer_stop) ? STM32_I2C_CR2_RELOAD :
+ 0) |
+ (xfer_start ? STM32_I2C_CR2_START : 0);
for (i = 0; i < out_bytes; i++) {
rv = wait_isr(port, STM32_I2C_ISR_TXIS);
@@ -364,11 +363,11 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags,
* NBYTES again. if we were just transmitting, we need to
* set START bit to send (re)start and begin read transaction.
*/
- STM32_I2C_CR2(port) = ((in_bytes & 0xFF) << 16)
- | STM32_I2C_CR2_RD_WRN | addr_8bit
- | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0)
- | (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0)
- | (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0);
+ STM32_I2C_CR2(port) =
+ ((in_bytes & 0xFF) << 16) | STM32_I2C_CR2_RD_WRN |
+ addr_8bit | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) |
+ (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) |
+ (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0);
for (i = 0; i < in_bytes; i++) {
/* Wait for receive buffer not empty */
@@ -448,7 +447,7 @@ int i2c_raw_get_sda(int port)
int i2c_get_line_levels(int port)
{
return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
- (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
+ (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
}
void i2c_init(void)
@@ -460,11 +459,12 @@ void i2c_init(void)
i2c_init_port(p);
#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
- STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE
- | STM32_I2C_CR1_ADDRIE | STM32_I2C_CR1_STOPIE
- | STM32_I2C_CR1_NACKIE;
- STM32_I2C_OAR1(I2C_PORT_EC) = 0x8000
- | (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1);
+ STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE |
+ STM32_I2C_CR1_ADDRIE |
+ STM32_I2C_CR1_STOPIE |
+ STM32_I2C_CR1_NACKIE;
+ STM32_I2C_OAR1(I2C_PORT_EC) =
+ 0x8000 | (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1);
task_enable_irq(IRQ_SLAVE);
#endif
}
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