diff options
Diffstat (limited to 'chip/stm32')
166 files changed, 20071 insertions, 18880 deletions
diff --git a/chip/stm32/adc-stm32f0.c b/chip/stm32/adc-stm32f0.c index b0654132cd..d1b1cc0e02 100644 --- a/chip/stm32/adc-stm32f0.c +++ b/chip/stm32/adc-stm32f0.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -21,7 +21,7 @@ struct adc_profile_t { /* Register values. */ uint32_t cfgr1_reg; uint32_t cfgr2_reg; - uint32_t smpr_reg; /* Default Sampling Rate */ + uint32_t smpr_reg; /* Default Sampling Rate */ uint32_t ier_reg; /* DMA config. */ const struct dma_option *dma_option; @@ -31,7 +31,8 @@ struct adc_profile_t { #ifdef CONFIG_ADC_PROFILE_SINGLE static const struct dma_option dma_single = { - STM32_DMAC_ADC, (void *)&STM32_ADC_DR, + STM32_DMAC_ADC, + (void *)&STM32_ADC_DR, STM32_DMA_CCR_MSIZE_32_BIT | STM32_DMA_CCR_PSIZE_32_BIT, }; @@ -41,12 +42,9 @@ static const struct dma_option dma_single = { static const struct adc_profile_t profile = { /* Sample all channels once using DMA */ - .cfgr1_reg = STM32_ADC_CFGR1_OVRMOD, - .cfgr2_reg = 0, - .smpr_reg = CONFIG_ADC_SAMPLE_TIME, - .ier_reg = 0, - .dma_option = &dma_single, - .dma_buffer_size = 1, + .cfgr1_reg = STM32_ADC_CFGR1_OVRMOD, .cfgr2_reg = 0, + .smpr_reg = CONFIG_ADC_SAMPLE_TIME, .ier_reg = 0, + .dma_option = &dma_single, .dma_buffer_size = 1, }; #endif @@ -57,15 +55,15 @@ static const struct adc_profile_t profile = { #endif static const struct dma_option dma_continuous = { - STM32_DMAC_ADC, (void *)&STM32_ADC_DR, + STM32_DMAC_ADC, + (void *)&STM32_ADC_DR, STM32_DMA_CCR_MSIZE_32_BIT | STM32_DMA_CCR_PSIZE_32_BIT | - STM32_DMA_CCR_CIRC, + STM32_DMA_CCR_CIRC, }; static const struct adc_profile_t profile = { /* Sample all channels continuously using DMA */ - .cfgr1_reg = STM32_ADC_CFGR1_OVRMOD | - STM32_ADC_CFGR1_CONT | + .cfgr1_reg = STM32_ADC_CFGR1_OVRMOD | STM32_ADC_CFGR1_CONT | STM32_ADC_CFGR1_DMACFG, .cfgr2_reg = 0, .smpr_reg = CONFIG_ADC_SAMPLE_TIME, @@ -114,7 +112,7 @@ static void adc_configure(int ain_id, enum stm32_adc_smpr sample_rate) { /* Sampling time */ if (sample_rate == STM32_ADC_SMPR_DEFAULT || - sample_rate >= STM32_ADC_SMPR_COUNT) + sample_rate >= STM32_ADC_SMPR_COUNT) STM32_ADC_SMPR = profile.smpr_reg; else STM32_ADC_SMPR = STM32_ADC_SMPR_SMP(sample_rate); @@ -160,12 +158,12 @@ static void adc_interval_read(int ain_id, int interval_ms) adc_configure(ain_id, STM32_ADC_SMPR_DEFAULT); /* EXTEN=01 -> hardware trigger detection on rising edge */ - STM32_ADC_CFGR1 = (STM32_ADC_CFGR1 & ~STM32_ADC_CFGR1_EXTEN_MASK) - | STM32_ADC_CFGR1_EXTEN_RISE; + STM32_ADC_CFGR1 = (STM32_ADC_CFGR1 & ~STM32_ADC_CFGR1_EXTEN_MASK) | + STM32_ADC_CFGR1_EXTEN_RISE; /* EXTSEL=TRG3 -> Trigger on TIM3_TRGO */ STM32_ADC_CFGR1 = (STM32_ADC_CFGR1 & ~STM32_ADC_CFGR1_TRG_MASK) | - STM32_ADC_CFGR1_TRG3; + STM32_ADC_CFGR1_TRG3; __hw_timer_enable_clock(TIM_ADC, 1); @@ -293,9 +291,18 @@ int adc_set_watchdog_delay(int delay_ms) #else /* CONFIG_ADC_WATCHDOG */ -static int adc_watchdog_enabled(void) { return 0; } -static int adc_enable_watchdog_no_lock(void) { return 0; } -static int adc_disable_watchdog_no_lock(void) { return 0; } +static int adc_watchdog_enabled(void) +{ + return 0; +} +static int adc_enable_watchdog_no_lock(void) +{ + return 0; +} +static int adc_disable_watchdog_no_lock(void) +{ + return 0; +} #endif /* CONFIG_ADC_WATCHDOG */ diff --git a/chip/stm32/adc-stm32f3.c b/chip/stm32/adc-stm32f3.c index 543a44ab1a..605bb14b69 100644 --- a/chip/stm32/adc-stm32f3.c +++ b/chip/stm32/adc-stm32f3.c @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -16,9 +16,9 @@ #define ADC_SINGLE_READ_TIMEOUT 3000 /* 3 ms */ -#define SMPR1_EXPAND(v) ((v) | ((v) << 3) | ((v) << 6) | ((v) << 9) | \ - ((v) << 12) | ((v) << 15) | ((v) << 18) | \ - ((v) << 21)) +#define SMPR1_EXPAND(v) \ + ((v) | ((v) << 3) | ((v) << 6) | ((v) << 9) | ((v) << 12) | \ + ((v) << 15) | ((v) << 18) | ((v) << 21)) #define SMPR2_EXPAND(v) (SMPR1_EXPAND(v) | ((v) << 24) | ((v) << 27)) /* Default ADC sample time = 13.5 cycles */ @@ -215,8 +215,9 @@ int adc_read_channel(enum adc_channel ch) adc_enable_watchdog_no_lock(); mutex_unlock(&adc_lock); - return (value == ADC_READ_ERROR) ? ADC_READ_ERROR : - value * adc->factor_mul / adc->factor_div + adc->shift; + return (value == ADC_READ_ERROR) ? + ADC_READ_ERROR : + value * adc->factor_mul / adc->factor_div + adc->shift; } static void adc_init(void) diff --git a/chip/stm32/adc-stm32f4.c b/chip/stm32/adc-stm32f4.c index 5e375b9dbf..605bb14b69 120000..100644 --- a/chip/stm32/adc-stm32f4.c +++ b/chip/stm32/adc-stm32f4.c @@ -1 +1,260 @@ -adc-stm32f3.c
\ No newline at end of file +/* Copyright 2012 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "adc.h" +#include "clock.h" +#include "common.h" +#include "console.h" +#include "dma.h" +#include "hooks.h" +#include "registers.h" +#include "task.h" +#include "timer.h" +#include "util.h" + +#define ADC_SINGLE_READ_TIMEOUT 3000 /* 3 ms */ + +#define SMPR1_EXPAND(v) \ + ((v) | ((v) << 3) | ((v) << 6) | ((v) << 9) | ((v) << 12) | \ + ((v) << 15) | ((v) << 18) | ((v) << 21)) +#define SMPR2_EXPAND(v) (SMPR1_EXPAND(v) | ((v) << 24) | ((v) << 27)) + +/* Default ADC sample time = 13.5 cycles */ +#ifndef CONFIG_ADC_SAMPLE_TIME +#define CONFIG_ADC_SAMPLE_TIME 2 +#endif + +struct mutex adc_lock; + +static int watchdog_ain_id; + +static inline void adc_set_channel(int sample_id, int channel) +{ + uint32_t mask, val; + volatile uint32_t *sqr_reg; + + if (sample_id < 6) { + mask = 0x1f << (sample_id * 5); + val = channel << (sample_id * 5); + sqr_reg = &STM32_ADC_SQR3; + } else if (sample_id < 12) { + mask = 0x1f << ((sample_id - 6) * 5); + val = channel << ((sample_id - 6) * 5); + sqr_reg = &STM32_ADC_SQR2; + } else { + mask = 0x1f << ((sample_id - 12) * 5); + val = channel << ((sample_id - 12) * 5); + sqr_reg = &STM32_ADC_SQR1; + } + + *sqr_reg = (*sqr_reg & ~mask) | val; +} + +static void adc_configure(int ain_id) +{ + /* Set ADC channel */ + adc_set_channel(0, ain_id); + + /* Disable DMA */ + STM32_ADC_CR2 &= ~BIT(8); + + /* Disable scan mode */ + STM32_ADC_CR1 &= ~BIT(8); +} + +static void __attribute__((unused)) adc_configure_all(void) +{ + int i; + + /* Set ADC channels */ + STM32_ADC_SQR1 = (ADC_CH_COUNT - 1) << 20; + for (i = 0; i < ADC_CH_COUNT; ++i) + adc_set_channel(i, adc_channels[i].channel); + + /* Enable DMA */ + STM32_ADC_CR2 |= BIT(8); + + /* Enable scan mode */ + STM32_ADC_CR1 |= BIT(8); +} + +static inline int adc_powered(void) +{ + return STM32_ADC_CR2 & BIT(0); +} + +static inline int adc_conversion_ended(void) +{ + return STM32_ADC_SR & BIT(1); +} + +static int adc_watchdog_enabled(void) +{ + return STM32_ADC_CR1 & BIT(23); +} + +static int adc_enable_watchdog_no_lock(void) +{ + /* Fail if watchdog already enabled */ + if (adc_watchdog_enabled()) + return EC_ERROR_UNKNOWN; + + /* Set channel */ + STM32_ADC_SQR3 = watchdog_ain_id; + STM32_ADC_SQR1 = 0; + STM32_ADC_CR1 = (STM32_ADC_CR1 & ~0x1f) | watchdog_ain_id; + + /* Clear interrupt bit */ + STM32_ADC_SR &= ~0x1; + + /* AWDSGL=1, SCAN=1, AWDIE=1, AWDEN=1 */ + STM32_ADC_CR1 |= BIT(9) | BIT(8) | BIT(6) | BIT(23); + + /* Disable DMA */ + STM32_ADC_CR2 &= ~BIT(8); + + /* CONT=1 */ + STM32_ADC_CR2 |= BIT(1); + + /* Start conversion */ + STM32_ADC_CR2 |= BIT(0); + + return EC_SUCCESS; +} + +int adc_enable_watchdog(int ain_id, int high, int low) +{ + int ret; + + if (!adc_powered()) + return EC_ERROR_UNKNOWN; + + mutex_lock(&adc_lock); + + watchdog_ain_id = ain_id; + + /* Set thresholds */ + STM32_ADC_HTR = high & 0xfff; + STM32_ADC_LTR = low & 0xfff; + + ret = adc_enable_watchdog_no_lock(); + mutex_unlock(&adc_lock); + return ret; +} + +static int adc_disable_watchdog_no_lock(void) +{ + /* Fail if watchdog not running */ + if (!adc_watchdog_enabled()) + return EC_ERROR_UNKNOWN; + + /* AWDEN=0, AWDIE=0 */ + STM32_ADC_CR1 &= ~BIT(23) & ~BIT(6); + + /* CONT=0 */ + STM32_ADC_CR2 &= ~BIT(1); + + return EC_SUCCESS; +} + +int adc_disable_watchdog(void) +{ + int ret; + + if (!adc_powered()) + return EC_ERROR_UNKNOWN; + + mutex_lock(&adc_lock); + ret = adc_disable_watchdog_no_lock(); + mutex_unlock(&adc_lock); + return ret; +} + +int adc_read_channel(enum adc_channel ch) +{ + const struct adc_t *adc = adc_channels + ch; + int value; + int restore_watchdog = 0; + timestamp_t deadline; + + if (!adc_powered()) + return EC_ERROR_UNKNOWN; + + mutex_lock(&adc_lock); + + if (adc_watchdog_enabled()) { + restore_watchdog = 1; + adc_disable_watchdog_no_lock(); + } + + adc_configure(adc->channel); + + /* Clear EOC bit */ + STM32_ADC_SR &= ~BIT(1); + + /* Start conversion (Note: For now only confirmed on F4) */ +#if defined(CHIP_FAMILY_STM32F4) + STM32_ADC_CR2 |= STM32_ADC_CR2_ADON | STM32_ADC_CR2_SWSTART; +#else + STM32_ADC_CR2 |= STM32_ADC_CR2_ADON; +#endif + + /* Wait for EOC bit set */ + deadline.val = get_time().val + ADC_SINGLE_READ_TIMEOUT; + value = ADC_READ_ERROR; + do { + if (adc_conversion_ended()) { + value = STM32_ADC_DR & ADC_READ_MAX; + break; + } + } while (!timestamp_expired(deadline, NULL)); + + if (restore_watchdog) + adc_enable_watchdog_no_lock(); + + mutex_unlock(&adc_lock); + return (value == ADC_READ_ERROR) ? + ADC_READ_ERROR : + value * adc->factor_mul / adc->factor_div + adc->shift; +} + +static void adc_init(void) +{ + /* + * Enable ADC clock. + * APB2 clock is 16MHz. ADC clock prescaler is /2. + * So the ADC clock is 8MHz. + */ + clock_enable_module(MODULE_ADC, 1); + + /* + * ADC clock is divided with respect to AHB, so no delay needed + * here. If ADC clock is the same as AHB, a read on ADC + * register is needed here. + */ + + if (!adc_powered()) { + /* Power on ADC module */ + STM32_ADC_CR2 |= STM32_ADC_CR2_ADON; + + /* Reset calibration */ + STM32_ADC_CR2 |= STM32_ADC_CR2_RSTCAL; + while (STM32_ADC_CR2 & STM32_ADC_CR2_RSTCAL) + ; + + /* A/D Calibrate */ + STM32_ADC_CR2 |= STM32_ADC_CR2_CAL; + while (STM32_ADC_CR2 & STM32_ADC_CR2_CAL) + ; + } + + /* Set right alignment */ + STM32_ADC_CR2 &= ~STM32_ADC_CR2_ALIGN; + + /* Set sample time of all channels */ + STM32_ADC_SMPR1 = SMPR1_EXPAND(CONFIG_ADC_SAMPLE_TIME); + STM32_ADC_SMPR2 = SMPR2_EXPAND(CONFIG_ADC_SAMPLE_TIME); +} +DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC); diff --git a/chip/stm32/adc-stm32l.c b/chip/stm32/adc-stm32l.c index c1f1cfae4a..636710f071 100644 --- a/chip/stm32/adc-stm32l.c +++ b/chip/stm32/adc-stm32l.c @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -91,7 +91,7 @@ static void adc_init(void) if (!adc_powered()) /* Power on ADC module */ - STM32_ADC_CR2 |= BIT(0); /* ADON */ + STM32_ADC_CR2 |= BIT(0); /* ADON */ /* Set right alignment */ STM32_ADC_CR2 &= ~BIT(11); @@ -165,6 +165,7 @@ int adc_read_channel(enum adc_channel ch) adc_release(); mutex_unlock(&adc_lock); - return (value == ADC_READ_ERROR) ? ADC_READ_ERROR : - value * adc->factor_mul / adc->factor_div + adc->shift; + return (value == ADC_READ_ERROR) ? + ADC_READ_ERROR : + value * adc->factor_mul / adc->factor_div + adc->shift; } diff --git a/chip/stm32/adc-stm32l4.c b/chip/stm32/adc-stm32l4.c index 8609d44f5d..e67ae4a8fd 100644 --- a/chip/stm32/adc-stm32l4.c +++ b/chip/stm32/adc-stm32l4.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -21,7 +21,7 @@ struct adc_profile_t { /* Register values. */ uint32_t cfgr1_reg; uint32_t cfgr2_reg; - uint32_t smpr_reg; /* Default Sampling Rate */ + uint32_t smpr_reg; /* Default Sampling Rate */ uint32_t ier_reg; /* DMA config. */ const struct dma_option *dma_option; @@ -36,11 +36,11 @@ struct adc_profile_t { #endif #if defined(CHIP_FAMILY_STM32L4) -#define ADC_CALIBRATION_TIMEOUT_US 100000U -#define ADC_ENABLE_TIMEOUT_US 200000U -#define ADC_CONVERSION_TIMEOUT_US 200000U +#define ADC_CALIBRATION_TIMEOUT_US 100000U +#define ADC_ENABLE_TIMEOUT_US 200000U +#define ADC_CONVERSION_TIMEOUT_US 200000U -#define NUMBER_OF_ADC_CHANNEL 2 +#define NUMBER_OF_ADC_CHANNEL 2 uint8_t adc1_initialized; #endif @@ -51,15 +51,15 @@ uint8_t adc1_initialized; #endif static const struct dma_option dma_continuous = { - STM32_DMAC_ADC, (void *)&STM32_ADC_DR, + STM32_DMAC_ADC, + (void *)&STM32_ADC_DR, STM32_DMA_CCR_MSIZE_32_BIT | STM32_DMA_CCR_PSIZE_32_BIT | - STM32_DMA_CCR_CIRC, + STM32_DMA_CCR_CIRC, }; static const struct adc_profile_t profile = { /* Sample all channels continuously using DMA */ - .cfgr1_reg = STM32_ADC_CFGR1_OVRMOD | - STM32_ADC_CFGR1_CONT | + .cfgr1_reg = STM32_ADC_CFGR1_OVRMOD | STM32_ADC_CFGR1_CONT | STM32_ADC_CFGR1_DMACFG, .cfgr2_reg = 0, .smpr_reg = CONFIG_ADC_SAMPLE_TIME, @@ -87,7 +87,7 @@ static void adc_init(const struct adc_t *adc) /* set ADC clock to 20MHz */ STM32_ADC1_CCR &= ~0x003C0000; - STM32_ADC1_CCR |= 0x00080000; + STM32_ADC1_CCR |= 0x00080000; STM32_RCC_AHB2ENR |= STM32_RCC_HB2_GPIOA; STM32_RCC_AHB2ENR |= STM32_RCC_HB2_GPIOB; @@ -101,13 +101,13 @@ static void adc_init(const struct adc_t *adc) } static void adc_configure(int ain_id, int ain_rank, - enum stm32_adc_smpr sample_rate) + enum stm32_adc_smpr sample_rate) { /* Select Sampling time and channel to convert */ - if (ain_id <= 10) { + if (ain_id <= 10) { STM32_ADC1_SMPR1 &= ~(7 << ((ain_id - 1) * 3)); STM32_ADC1_SMPR1 |= (sample_rate << ((ain_id - 1) * 3)); - } else { + } else { STM32_ADC1_SMPR2 &= ~(7 << ((ain_id - 11) * 3)); STM32_ADC1_SMPR2 |= (sample_rate << ((ain_id - 11) * 3)); } @@ -172,7 +172,8 @@ int adc_read_channel(enum adc_channel ch) /* wait for the end of calibration */ wait_loop_index = ((ADC_CALIBRATION_TIMEOUT_US * - (CPU_CLOCK / (100000 * 2))) / 10); + (CPU_CLOCK / (100000 * 2))) / + 10); while (STM32_ADC1_CR & STM32_ADC1_CR_ADCAL) { if (wait_loop_index-- == 0) break; @@ -181,8 +182,9 @@ int adc_read_channel(enum adc_channel ch) /* Enable ADC */ STM32_ADC1_ISR |= STM32_ADC1_ISR_ADRDY; STM32_ADC1_CR |= STM32_ADC1_CR_ADEN; - wait_loop_index = ((ADC_ENABLE_TIMEOUT_US * - (CPU_CLOCK / (100000 * 2))) / 10); + wait_loop_index = + ((ADC_ENABLE_TIMEOUT_US * (CPU_CLOCK / (100000 * 2))) / + 10); while (!(STM32_ADC1_ISR & STM32_ADC1_ISR_ADRDY)) { wait_loop_index--; if (wait_loop_index == 0) @@ -196,8 +198,8 @@ int adc_read_channel(enum adc_channel ch) STM32_ADC1_CR |= BIT(3); /* JADSTART */ /* Wait for end of injected conversion */ - wait_loop_index = ((ADC_CONVERSION_TIMEOUT_US * - (CPU_CLOCK / (100000 * 2))) / 10); + wait_loop_index = + ((ADC_CONVERSION_TIMEOUT_US * (CPU_CLOCK / (100000 * 2))) / 10); while (!(STM32_ADC1_ISR & BIT(6))) { if (wait_loop_index-- == 0) break; diff --git a/chip/stm32/adc_chip.h b/chip/stm32/adc_chip.h index 7e3c688c14..2c4e726ea5 100644 --- a/chip/stm32/adc_chip.h +++ b/chip/stm32/adc_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -48,7 +48,7 @@ struct adc_t { #endif #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4) - enum stm32_adc_smpr sample_rate; /* Sampling Rate of the channel */ + enum stm32_adc_smpr sample_rate; /* Sampling Rate of the channel */ #endif }; diff --git a/chip/stm32/bkpdata.c b/chip/stm32/bkpdata.c index ded77401d6..bde026facd 100644 --- a/chip/stm32/bkpdata.c +++ b/chip/stm32/bkpdata.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -65,7 +65,7 @@ int bkpdata_index_lookup(enum system_bbram_idx idx, int *msb) return -1; } -uint32_t bkpdata_read_reset_flags() +uint32_t bkpdata_read_reset_flags(void) { uint32_t flags = bkpdata_read(BKPDATA_INDEX_SAVED_RESET_FLAGS); @@ -76,8 +76,7 @@ uint32_t bkpdata_read_reset_flags() return flags; } -__overridable -void bkpdata_write_reset_flags(uint32_t save_flags) +__overridable void bkpdata_write_reset_flags(uint32_t save_flags) { bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS, save_flags & 0xffff); #ifdef CONFIG_STM32_EXTENDED_RESET_FLAGS diff --git a/chip/stm32/bkpdata.h b/chip/stm32/bkpdata.h index 199ed213a9..14ef33483e 100644 --- a/chip/stm32/bkpdata.h +++ b/chip/stm32/bkpdata.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -20,27 +20,27 @@ * compatibility. */ enum bkpdata_index { - BKPDATA_INDEX_SCRATCHPAD, /* General-purpose scratchpad */ - BKPDATA_INDEX_SAVED_RESET_FLAGS, /* Saved reset flags */ + BKPDATA_INDEX_SCRATCHPAD, /* General-purpose scratchpad */ + BKPDATA_INDEX_SAVED_RESET_FLAGS, /* Saved reset flags */ #ifdef CONFIG_STM32_EXTENDED_RESET_FLAGS - BKPDATA_INDEX_SAVED_RESET_FLAGS_2, /* Saved reset flags (cont) */ + BKPDATA_INDEX_SAVED_RESET_FLAGS_2, /* Saved reset flags (cont) */ #endif #ifdef CONFIG_SOFTWARE_PANIC - BKPDATA_INDEX_SAVED_PANIC_REASON, /* Saved panic reason */ - BKPDATA_INDEX_SAVED_PANIC_INFO, /* Saved panic data */ + BKPDATA_INDEX_SAVED_PANIC_REASON, /* Saved panic reason */ + BKPDATA_INDEX_SAVED_PANIC_INFO, /* Saved panic data */ BKPDATA_INDEX_SAVED_PANIC_EXCEPTION, /* Saved panic exception code */ #endif #ifdef CONFIG_USB_PD_DUAL_ROLE - BKPDATA_INDEX_PD0, /* USB-PD saved port0 state */ - BKPDATA_INDEX_PD1, /* USB-PD saved port1 state */ - BKPDATA_INDEX_PD2, /* USB-PD saved port2 state */ + BKPDATA_INDEX_PD0, /* USB-PD saved port0 state */ + BKPDATA_INDEX_PD1, /* USB-PD saved port1 state */ + BKPDATA_INDEX_PD2, /* USB-PD saved port2 state */ #endif #ifdef CONFIG_SOFTWARE_PANIC /** * Saving the panic flags in case that AP thinks the panic is new * after a hard reset. */ - BKPDATA_INDEX_SAVED_PANIC_FLAGS, /* Saved panic flags */ + BKPDATA_INDEX_SAVED_PANIC_FLAGS, /* Saved panic flags */ #endif BKPDATA_COUNT }; diff --git a/chip/stm32/build.mk b/chip/stm32/build.mk index 0d47a0131a..1fc14a15fa 100644 --- a/chip/stm32/build.mk +++ b/chip/stm32/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2013 The Chromium OS Authors. All rights reserved. +# Copyright 2013 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/chip/stm32/charger_detect.c b/chip/stm32/charger_detect.c index b32b9f3ac0..c404fc827a 100644 --- a/chip/stm32/charger_detect.c +++ b/chip/stm32/charger_detect.c @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -33,7 +33,6 @@ static uint16_t detect_type(uint16_t det_type) return STM32_USB_BCDR; } - int charger_detect_get_device_type(void) { uint16_t pdet_result; diff --git a/chip/stm32/clock-f.c b/chip/stm32/clock-f.c index 0ae4440d78..d181397d86 100644 --- a/chip/stm32/clock-f.c +++ b/chip/stm32/clock-f.c @@ -1,10 +1,11 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Clocks and power management settings */ +#include "builtin/assert.h" #include "chipset.h" #include "clock.h" #include "clock-f.h" @@ -23,7 +24,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) /* Convert decimal to BCD */ static uint8_t u8_to_bcd(uint8_t val) @@ -41,8 +42,8 @@ static uint32_t rtc_tr_to_sec(uint32_t rtc_tr) uint32_t sec; /* convert the hours field */ - sec = (((rtc_tr & 0x300000) >> 20) * 10 + - ((rtc_tr & 0xf0000) >> 16)) * 3600; + sec = (((rtc_tr & 0x300000) >> 20) * 10 + ((rtc_tr & 0xf0000) >> 16)) * + 3600; /* convert the minutes field */ sec += (((rtc_tr & 0x7000) >> 12) * 10 + ((rtc_tr & 0xf00) >> 8)) * 60; /* convert the seconds field */ @@ -122,10 +123,9 @@ static uint32_t rtc_dr_to_sec(uint32_t rtc_dr) struct calendar_date time; uint32_t sec; - time.year = (((rtc_dr & 0xf00000) >> 20) * 10 + - ((rtc_dr & 0xf0000) >> 16)); - time.month = (((rtc_dr & 0x1000) >> 12) * 10 + - ((rtc_dr & 0xf00) >> 8)); + time.year = + (((rtc_dr & 0xf00000) >> 20) * 10 + ((rtc_dr & 0xf0000) >> 16)); + time.month = (((rtc_dr & 0x1000) >> 12) * 10 + ((rtc_dr & 0xf00) >> 8)); time.day = ((rtc_dr & 0x30) >> 4) * 10 + (rtc_dr & 0xf); sec = date_to_sec(time); @@ -258,8 +258,8 @@ void set_rtc_alarm(uint32_t delay_s, uint32_t delay_us, * If the caller doesn't specify subsecond delay (e.g. host command), * just align the alarm time to second. */ - STM32_RTC_ALRMASSR = delay_us ? - (us_to_rtcss(alarm_us) | 0x0f000000) : 0; + STM32_RTC_ALRMASSR = delay_us ? (us_to_rtcss(alarm_us) | 0x0f000000) : + 0; #ifdef CONFIG_HOSTCMD_RTC /* @@ -321,8 +321,7 @@ static void set_rtc_host_event(void) DECLARE_DEFERRED(set_rtc_host_event); #endif -test_mockable -void rtc_alarm_irq(void) +test_mockable void rtc_alarm_irq(void) { struct rtc_time_reg rtc; reset_rtc_alarm(&rtc); @@ -342,8 +341,7 @@ static void __rtc_alarm_irq(void) } DECLARE_IRQ(STM32_IRQ_RTC_ALARM, __rtc_alarm_irq, 1); -__attribute__((weak)) -int clock_get_timer_freq(void) +__attribute__((weak)) int clock_get_timer_freq(void) { return clock_get_freq(); } @@ -399,7 +397,7 @@ void print_system_rtc(enum console_channel ch) } #ifdef CONFIG_CMD_RTC -static int command_system_rtc(int argc, char **argv) +static int command_system_rtc(int argc, const char **argv) { char *e; uint32_t t; @@ -416,12 +414,11 @@ static int command_system_rtc(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc, - "[set <seconds>]", - "Get/set real-time clock"); +DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc, "[set <seconds>]", + "Get/set real-time clock"); #ifdef CONFIG_CMD_RTC_ALARM -static int command_rtc_alarm_test(int argc, char **argv) +static int command_rtc_alarm_test(int argc, const char **argv) { int s = 1, us = 0; struct rtc_time_reg rtc; @@ -433,7 +430,6 @@ static int command_rtc_alarm_test(int argc, char **argv) s = strtoi(argv[1], &e, 10); if (*e) return EC_ERROR_PARAM1; - } if (argc > 2) { us = strtoi(argv[2], &e, 10); @@ -445,8 +441,7 @@ static int command_rtc_alarm_test(int argc, char **argv) return EC_SUCCESS; } DECLARE_CONSOLE_COMMAND(rtc_alarm, command_rtc_alarm_test, - "[seconds [microseconds]]", - "Test alarm"); + "[seconds [microseconds]]", "Test alarm"); #endif /* CONFIG_CMD_RTC_ALARM */ #endif /* CONFIG_CMD_RTC */ @@ -465,9 +460,8 @@ static enum ec_status system_rtc_get_value(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE, - system_rtc_get_value, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE, system_rtc_get_value, + EC_VER_MASK(0)); static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args) { @@ -476,9 +470,8 @@ static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args) rtc_set(p->time); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE, - system_rtc_set_value, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE, system_rtc_set_value, + EC_VER_MASK(0)); static enum ec_status system_rtc_set_alarm(struct host_cmd_handler_args *args) { @@ -492,9 +485,8 @@ static enum ec_status system_rtc_set_alarm(struct host_cmd_handler_args *args) set_rtc_alarm(p->time, 0, &rtc, 1); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_ALARM, - system_rtc_set_alarm, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_ALARM, system_rtc_set_alarm, + EC_VER_MASK(0)); static enum ec_status system_rtc_get_alarm(struct host_cmd_handler_args *args) { @@ -505,8 +497,7 @@ static enum ec_status system_rtc_get_alarm(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_ALARM, - system_rtc_get_alarm, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_ALARM, system_rtc_get_alarm, + EC_VER_MASK(0)); #endif /* CONFIG_HOSTCMD_RTC */ diff --git a/chip/stm32/clock-f.h b/chip/stm32/clock-f.h index 4662b043cb..5ed302bf78 100644 --- a/chip/stm32/clock-f.h +++ b/chip/stm32/clock-f.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -100,4 +100,4 @@ int is_host_wake_alarm_expired(timestamp_t ts); /* Set RTC wakeup based on the value saved in host_wake_time */ void restore_host_wake_alarm(void); -#endif /* __CROS_EC_CLOCK_F_H */ +#endif /* __CROS_EC_CLOCK_F_H */ diff --git a/chip/stm32/clock-l4.h b/chip/stm32/clock-l4.h index d237b84580..975d952b9f 100644 --- a/chip/stm32/clock-l4.h +++ b/chip/stm32/clock-l4.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -107,4 +107,4 @@ void restore_host_wake_alarm(void); void low_power_init(void); #endif -#endif /* __CROS_EC_CLOCK_L4_H */ +#endif /* __CROS_EC_CLOCK_L4_H */ diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c index d791d63df3..3b56382fdb 100644 --- a/chip/stm32/clock-stm32f0.c +++ b/chip/stm32/clock-stm32f0.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -22,7 +22,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) /* use 48Mhz USB-synchronized High-speed oscillator */ #define HSI48_CLOCK 48000000 @@ -54,13 +54,13 @@ static int dsleep_recovery_margin_us = 1000000; * we won't miss the host alarm. */ #ifdef CHIP_VARIANT_STM32F373 -#define STOP_MODE_LATENCY 500 /* us */ +#define STOP_MODE_LATENCY 500 /* us */ #elif defined(CHIP_VARIANT_STM32F05X) -#define STOP_MODE_LATENCY 300 /* us */ +#define STOP_MODE_LATENCY 300 /* us */ #elif (CPU_CLOCK == PLL_CLOCK) -#define STOP_MODE_LATENCY 300 /* us */ +#define STOP_MODE_LATENCY 300 /* us */ #else -#define STOP_MODE_LATENCY 50 /* us */ +#define STOP_MODE_LATENCY 50 /* us */ #endif #define SET_RTC_MATCH_DELAY 200 /* us */ @@ -137,9 +137,8 @@ void config_hispeed_clock(void) while ((STM32_RCC_CFGR & 0xc) != 0x8) ; /* F03X and F05X and F070 don't have HSI48 */ -#elif defined(CHIP_VARIANT_STM32F03X) || \ -defined(CHIP_VARIANT_STM32F05X) || \ -defined(CHIP_VARIANT_STM32F070) +#elif defined(CHIP_VARIANT_STM32F03X) || defined(CHIP_VARIANT_STM32F05X) || \ + defined(CHIP_VARIANT_STM32F070) /* If PLL is the clock source, PLL has already been set up. */ if ((STM32_RCC_CFGR & 0xc) == 0x8) return; @@ -268,7 +267,7 @@ void __enter_hibernate(uint32_t seconds, uint32_t microseconds) STM32_PWR_CR |= 0xe; CPU_SCB_SYSCTRL |= 0x4; /* go to Standby mode */ - asm("wfi"); + cpu_enter_suspend_mode(); /* we should never reach that point */ while (1) @@ -319,8 +318,8 @@ void __idle(void) * EC exits deep sleep mode. */ !is_host_wake_alarm_expired( - (timestamp_t)(next_delay + t0.val + SECOND + - RESTORE_HOST_ALARM_LATENCY)) && + (timestamp_t)(next_delay + t0.val + SECOND + + RESTORE_HOST_ALARM_LATENCY)) && #endif (next_delay > (STOP_MODE_LATENCY + SET_RTC_MATCH_DELAY))) { /* Deep-sleep in STOP mode */ @@ -331,9 +330,9 @@ void __idle(void) /* Set deep sleep bit */ CPU_SCB_SYSCTRL |= 0x4; - set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY, - &rtc0, 0); - asm("wfi"); + set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY, &rtc0, + 0); + cpu_enter_suspend_mode(); CPU_SCB_SYSCTRL &= ~0x4; @@ -371,10 +370,10 @@ void __idle(void) idle_sleep_cnt++; /* Normal idle : only CPU clock stopped */ - asm("wfi"); + cpu_enter_suspend_mode(); } #ifdef CONFIG_LOW_POWER_IDLE_LIMITED -en_int: + en_int: #endif interrupt_enable(); } @@ -482,22 +481,21 @@ void rtc_set(uint32_t sec) /** * Print low power idle statistics */ -static int command_idle_stats(int argc, char **argv) +static int command_idle_stats(int argc, const char **argv) { timestamp_t ts = get_time(); ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt); ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt); ccprintf("Time spent in deep-sleep: %.6llds\n", - idle_dsleep_time_us); + idle_dsleep_time_us); ccprintf("Total time on: %.6llds\n", ts.val); ccprintf("Deep-sleep closest to wake deadline: %dus\n", - dsleep_recovery_margin_us); + dsleep_recovery_margin_us); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, - "", +DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "", "Print last idle stats"); #endif /* CONFIG_CMD_IDLE_STATS */ #endif diff --git a/chip/stm32/clock-stm32f3.c b/chip/stm32/clock-stm32f3.c index be91154e52..7d2b3de7f2 120000..100644 --- a/chip/stm32/clock-stm32f3.c +++ b/chip/stm32/clock-stm32f3.c @@ -1 +1,501 @@ -clock-stm32f0.c
\ No newline at end of file +/* Copyright 2014 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Clocks and power management settings */ + +#include "chipset.h" +#include "clock.h" +#include "clock-f.h" +#include "common.h" +#include "console.h" +#include "cpu.h" +#include "hooks.h" +#include "hwtimer.h" +#include "registers.h" +#include "system.h" +#include "task.h" +#include "timer.h" +#include "uart.h" +#include "util.h" + +/* Console output macros */ +#define CPUTS(outstr) cputs(CC_CLOCK, outstr) +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) + +/* use 48Mhz USB-synchronized High-speed oscillator */ +#define HSI48_CLOCK 48000000 + +/* use PLL at 38.4MHz as system clock. */ +#define PLL_CLOCK 38400000 + +/* Low power idle statistics */ +#ifdef CONFIG_LOW_POWER_IDLE +static int idle_sleep_cnt; +static int idle_dsleep_cnt; +static uint64_t idle_dsleep_time_us; +static int dsleep_recovery_margin_us = 1000000; + +/* + * minimum delay to enter stop mode + * + * STOP_MODE_LATENCY: max time to wake up from STOP mode with regulator in low + * power mode is 5 us + PLL locking time is 200us. + * + * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. If we set the alarm + * in the past, it will never wake up and cause a watchdog. + * For STM32F3, we are using HSE, which requires additional time to start up. + * Therefore, the latency for STM32F3 is set longer. + * + * RESTORE_HOST_ALARM_LATENCY: max latency between the deferred routine is + * called and the host alarm is actually restored. In practice, the max latency + * is measured as ~600us. 1000us should be conservative enough to guarantee + * we won't miss the host alarm. + */ +#ifdef CHIP_VARIANT_STM32F373 +#define STOP_MODE_LATENCY 500 /* us */ +#elif defined(CHIP_VARIANT_STM32F05X) +#define STOP_MODE_LATENCY 300 /* us */ +#elif (CPU_CLOCK == PLL_CLOCK) +#define STOP_MODE_LATENCY 300 /* us */ +#else +#define STOP_MODE_LATENCY 50 /* us */ +#endif +#define SET_RTC_MATCH_DELAY 200 /* us */ + +#ifdef CONFIG_HOSTCMD_RTC +#define RESTORE_HOST_ALARM_LATENCY 1000 /* us */ +#endif + +#endif /* CONFIG_LOW_POWER_IDLE */ + +/* + * RTC clock frequency (By default connected to LSI clock) + * + * The LSI on any given chip can be between 30 kHz to 60 kHz. + * Without calibration, LSI frequency may be off by as much as 50%. + * + * Set synchronous clock freq to (RTC clock source / 2) to maximize + * subsecond resolution. Set asynchronous clock to 1 Hz. + */ + +#define RTC_PREDIV_A 1 +#ifdef CONFIG_STM32_CLOCK_LSE +#define RTC_FREQ (32768 / (RTC_PREDIV_A + 1)) /* Hz */ +/* GCD(RTC_FREQ, 1000000) */ +#define RTC_GCD 64 +#else /* LSI clock, 40kHz-ish */ +#define RTC_FREQ (40000 / (RTC_PREDIV_A + 1)) /* Hz */ +/* GCD(RTC_FREQ, 1000000) */ +#define RTC_GCD 20000 +#endif +#define RTC_PREDIV_S (RTC_FREQ - 1) + +/* + * There are (1000000 / RTC_FREQ) us per RTC tick, take GCD of both terms + * for conversion calculations to fit in 32 bits. + */ +#define US_GCD (1000000 / RTC_GCD) +#define RTC_FREQ_GCD (RTC_FREQ / RTC_GCD) + +int32_t rtcss_to_us(uint32_t rtcss) +{ + return ((RTC_PREDIV_S - (rtcss & 0x7fff)) * US_GCD) / RTC_FREQ_GCD; +} + +uint32_t us_to_rtcss(int32_t us) +{ + return RTC_PREDIV_S - us * RTC_FREQ_GCD / US_GCD; +} + +void config_hispeed_clock(void) +{ +#ifdef CHIP_FAMILY_STM32F3 + /* Ensure that HSE is ON */ + wait_for_ready(&STM32_RCC_CR, BIT(16), BIT(17)); + + /* + * HSE = 24MHz, no prescalar, no MCO, with PLL *2 => 48MHz SYSCLK + * HCLK = SYSCLK, PCLK = HCLK / 2 = 24MHz + * ADCCLK = PCLK / 6 = 4MHz + * USB uses SYSCLK = 48MHz + */ + STM32_RCC_CFGR = 0x0041a400; + + /* Enable the PLL */ + STM32_RCC_CR |= 0x01000000; + + /* Wait until the PLL is ready */ + while (!(STM32_RCC_CR & 0x02000000)) + ; + + /* Switch SYSCLK to PLL */ + STM32_RCC_CFGR |= 0x2; + + /* Wait until the PLL is the clock source */ + while ((STM32_RCC_CFGR & 0xc) != 0x8) + ; +/* F03X and F05X and F070 don't have HSI48 */ +#elif defined(CHIP_VARIANT_STM32F03X) || defined(CHIP_VARIANT_STM32F05X) || \ + defined(CHIP_VARIANT_STM32F070) + /* If PLL is the clock source, PLL has already been set up. */ + if ((STM32_RCC_CFGR & 0xc) == 0x8) + return; + + /* Ensure that HSI is ON */ + wait_for_ready(&STM32_RCC_CR, BIT(0), BIT(1)); + + /* + * HSI = 8MHz, HSI/2 with PLL *12 = ~48 MHz + * therefore PCLK = FCLK = SYSCLK = 48MHz + */ + /* Switch the PLL source to HSI/2 */ + STM32_RCC_CFGR &= ~(0x00018000); + + /* + * Specify HSI/2 clock as input clock to PLL and set PLL (*12). + */ + STM32_RCC_CFGR |= 0x00280000; + + /* Enable the PLL. */ + STM32_RCC_CR |= 0x01000000; + + /* Wait until PLL is ready. */ + while (!(STM32_RCC_CR & 0x02000000)) + ; + + /* Switch SYSCLK to PLL. */ + STM32_RCC_CFGR |= 0x2; + + /* wait until the PLL is the clock source */ + while ((STM32_RCC_CFGR & 0xc) != 0x8) + ; +#else + /* Ensure that HSI48 is ON */ + wait_for_ready(&STM32_RCC_CR2, BIT(16), BIT(17)); + +#if (CPU_CLOCK == HSI48_CLOCK) + /* + * HSI48 = 48MHz, no prescaler, no MCO, no PLL + * therefore PCLK = FCLK = SYSCLK = 48MHz + * USB uses HSI48 = 48MHz + */ + +#ifdef CONFIG_USB + /* + * Configure and enable Clock Recovery System + * + * Since we are running from the internal RC HSI48 clock, the CSR + * is needed to guarantee an accurate 48MHz clock for USB. + * + * The default values configure the CRS to use the periodic USB SOF + * as the SYNC signal for calibrating the HSI48. + * + */ + + /* Enable Clock Recovery System */ + STM32_RCC_APB1ENR |= STM32_RCC_PB1_CRS; + + /* Enable automatic trimming */ + STM32_CRS_CR |= STM32_CRS_CR_AUTOTRIMEN; + + /* Enable oscillator clock for the frequency error counter */ + STM32_CRS_CR |= STM32_CRS_CR_CEN; +#endif + + /* switch SYSCLK to HSI48 */ + STM32_RCC_CFGR = 0x00000003; + + /* wait until the HSI48 is the clock source */ + while ((STM32_RCC_CFGR & 0xc) != 0xc) + ; + +#elif (CPU_CLOCK == PLL_CLOCK) + /* + * HSI48 = 48MHz, no prescalar, no MCO, with PLL *4/5 => 38.4MHz SYSCLK + * therefore PCLK = FCLK = SYSCLK = 38.4MHz + * USB uses HSI48 = 48MHz + */ + + /* If PLL is the clock source, PLL has already been set up. */ + if ((STM32_RCC_CFGR & 0xc) == 0x8) + return; + + /* + * Specify HSI48 clock as input clock to PLL and set PLL multiplier + * and divider. + */ + STM32_RCC_CFGR = 0x00098000; + STM32_RCC_CFGR2 = 0x4; + + /* Enable the PLL. */ + STM32_RCC_CR |= 0x01000000; + + /* Wait until PLL is ready. */ + while (!(STM32_RCC_CR & 0x02000000)) + ; + + /* Switch SYSCLK to PLL. */ + STM32_RCC_CFGR |= 0x2; + + /* wait until the PLL is the clock source */ + while ((STM32_RCC_CFGR & 0xc) != 0x8) + ; + +#else +#error "CPU_CLOCK must be either 48MHz or 38.4MHz" +#endif +#endif +} + +#ifdef CONFIG_HIBERNATE +void __enter_hibernate(uint32_t seconds, uint32_t microseconds) +{ + struct rtc_time_reg rtc; + + if (seconds || microseconds) + set_rtc_alarm(seconds, microseconds, &rtc, 0); + + /* interrupts off now */ + interrupt_disable(); + +#ifdef CONFIG_HIBERNATE_WAKEUP_PINS + /* enable the wake up pins */ + STM32_PWR_CSR |= CONFIG_HIBERNATE_WAKEUP_PINS; +#endif + STM32_PWR_CR |= 0xe; + CPU_SCB_SYSCTRL |= 0x4; + /* go to Standby mode */ + asm("wfi"); + + /* we should never reach that point */ + while (1) + ; +} +#endif + +#ifdef CONFIG_HOSTCMD_RTC +static void restore_host_wake_alarm_deferred(void) +{ + restore_host_wake_alarm(); +} +DECLARE_DEFERRED(restore_host_wake_alarm_deferred); +#endif + +#ifdef CONFIG_LOW_POWER_IDLE + +void clock_refresh_console_in_use(void) +{ +} + +void __idle(void) +{ + timestamp_t t0; + uint32_t rtc_diff; + int next_delay, margin_us; + struct rtc_time_reg rtc0, rtc1; + + while (1) { + interrupt_disable(); + + t0 = get_time(); + next_delay = __hw_clock_event_get() - t0.le.lo; + +#ifdef CONFIG_LOW_POWER_IDLE_LIMITED + if (idle_is_disabled()) + goto en_int; +#endif + + if (DEEP_SLEEP_ALLOWED && +#ifdef CONFIG_HOSTCMD_RTC + /* + * Don't go to deep sleep mode if we might miss the + * wake alarm that the host requested. Note that the + * host alarm always aligns to second. Considering the + * worst case, we have to ensure alarm won't go off + * within RESTORE_HOST_ALARM_LATENCY + 1 second after + * EC exits deep sleep mode. + */ + !is_host_wake_alarm_expired( + (timestamp_t)(next_delay + t0.val + SECOND + + RESTORE_HOST_ALARM_LATENCY)) && +#endif + (next_delay > (STOP_MODE_LATENCY + SET_RTC_MATCH_DELAY))) { + /* Deep-sleep in STOP mode */ + idle_dsleep_cnt++; + + uart_enable_wakeup(1); + + /* Set deep sleep bit */ + CPU_SCB_SYSCTRL |= 0x4; + + set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY, &rtc0, + 0); + asm("wfi"); + + CPU_SCB_SYSCTRL &= ~0x4; + + uart_enable_wakeup(0); + + /* + * By default only HSI 8MHz is enabled here. Re-enable + * high-speed clock if in use. + */ + config_hispeed_clock(); + + /* Fast forward timer according to RTC counter */ + reset_rtc_alarm(&rtc1); + rtc_diff = get_rtc_diff(&rtc0, &rtc1); + t0.val = t0.val + rtc_diff; + force_time(t0); + +#ifdef CONFIG_HOSTCMD_RTC + hook_call_deferred( + &restore_host_wake_alarm_deferred_data, 0); +#endif + /* Record time spent in deep sleep. */ + idle_dsleep_time_us += rtc_diff; + + /* Calculate how close we were to missing deadline */ + margin_us = next_delay - rtc_diff; + if (margin_us < 0) + /* Use CPUTS to save stack space */ + CPUTS("Idle overslept!\n"); + + /* Record the closest to missing a deadline. */ + if (margin_us < dsleep_recovery_margin_us) + dsleep_recovery_margin_us = margin_us; + } else { + idle_sleep_cnt++; + + /* Normal idle : only CPU clock stopped */ + asm("wfi"); + } +#ifdef CONFIG_LOW_POWER_IDLE_LIMITED + en_int: +#endif + interrupt_enable(); + } +} +#endif /* CONFIG_LOW_POWER_IDLE */ + +int clock_get_freq(void) +{ + return CPU_CLOCK; +} + +void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles) +{ + volatile uint32_t unused __attribute__((unused)); + + if (bus == BUS_AHB) { + while (cycles--) + unused = STM32_DMA1_REGS->isr; + } else { /* APB */ + while (cycles--) + unused = STM32_USART_BRR(STM32_USART1_BASE); + } +} + +void clock_enable_module(enum module_id module, int enable) +{ + if (module == MODULE_ADC) { + if (enable) + STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_ADCEN; + else + STM32_RCC_APB2ENR &= ~STM32_RCC_APB2ENR_ADCEN; + return; + } else if (module == MODULE_USB) { + if (enable) + STM32_RCC_APB1ENR |= STM32_RCC_PB1_USB; + else + STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_USB; + } +} + +int clock_is_module_enabled(enum module_id module) +{ + if (module == MODULE_ADC) + return !!(STM32_RCC_APB2ENR & STM32_RCC_APB2ENR_ADCEN); + else if (module == MODULE_USB) + return !!(STM32_RCC_APB1ENR & STM32_RCC_PB1_USB); + return 0; +} + +void rtc_init(void) +{ + rtc_unlock_regs(); + + /* Enter RTC initialize mode */ + STM32_RTC_ISR |= STM32_RTC_ISR_INIT; + while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF)) + ; + + /* Set clock prescalars */ + STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S; + + /* Start RTC timer */ + STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT; + while (STM32_RTC_ISR & STM32_RTC_ISR_INITF) + ; + + /* Enable RTC alarm interrupt */ + STM32_RTC_CR |= STM32_RTC_CR_ALRAIE | STM32_RTC_CR_BYPSHAD; + STM32_EXTI_RTSR |= EXTI_RTC_ALR_EVENT; + task_enable_irq(STM32_IRQ_RTC_ALARM); + + rtc_lock_regs(); +} + +#if defined(CONFIG_CMD_RTC) || defined(CONFIG_HOSTCMD_RTC) +void rtc_set(uint32_t sec) +{ + struct rtc_time_reg rtc; + + sec_to_rtc(sec, &rtc); + rtc_unlock_regs(); + + /* Disable alarm */ + STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE; + + /* Enter RTC initialize mode */ + STM32_RTC_ISR |= STM32_RTC_ISR_INIT; + while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF)) + ; + + /* Set clock prescalars */ + STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S; + + STM32_RTC_TR = rtc.rtc_tr; + STM32_RTC_DR = rtc.rtc_dr; + /* Start RTC timer */ + STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT; + + rtc_lock_regs(); +} +#endif + +#if defined(CONFIG_LOW_POWER_IDLE) && defined(CONFIG_COMMON_RUNTIME) +#ifdef CONFIG_CMD_IDLE_STATS +/** + * Print low power idle statistics + */ +static int command_idle_stats(int argc, const char **argv) +{ + timestamp_t ts = get_time(); + + ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt); + ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt); + ccprintf("Time spent in deep-sleep: %.6llds\n", + idle_dsleep_time_us); + ccprintf("Total time on: %.6llds\n", ts.val); + ccprintf("Deep-sleep closest to wake deadline: %dus\n", + dsleep_recovery_margin_us); + + return EC_SUCCESS; +} +DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "", + "Print last idle stats"); +#endif /* CONFIG_CMD_IDLE_STATS */ +#endif diff --git a/chip/stm32/clock-stm32f4.c b/chip/stm32/clock-stm32f4.c index b30edc1fa2..479faac7da 100644 --- a/chip/stm32/clock-stm32f4.c +++ b/chip/stm32/clock-stm32f4.c @@ -1,10 +1,11 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Clocks and power management settings */ +#include "builtin/assert.h" #include "chipset.h" #include "clock.h" #include "clock-f.h" @@ -21,12 +22,12 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) enum clock_osc { - OSC_HSI = 0, /* High-speed internal oscillator */ - OSC_HSE, /* High-speed external oscillator */ - OSC_PLL, /* PLL */ + OSC_HSI = 0, /* High-speed internal oscillator */ + OSC_HSE, /* High-speed external oscillator */ + OSC_PLL, /* PLL */ }; /* @@ -35,10 +36,11 @@ enum clock_osc { * A CONFIG may be needed if other boards have different MCO * requirements. */ -#define RCC_CFGR_MCO_CONFIG ((2 << 30) | /* MCO2 <- HSE */ \ - (0 << 27) | /* MCO2 div / 4 */ \ - (6 << 24) | /* MCO1 div / 4 */ \ - (3 << 21)) /* MCO1 <- PLL */ +#define RCC_CFGR_MCO_CONFIG \ + ((2 << 30) | /* MCO2 <- HSE */ \ + (0 << 27) | /* MCO2 div / 4 */ \ + (6 << 24) | /* MCO1 div / 4 */ \ + (3 << 21)) /* MCO1 <- PLL */ #ifdef CONFIG_STM32_CLOCK_HSE_HZ /* RTC clock must 1 Mhz when derived from HSE */ @@ -48,7 +50,6 @@ enum clock_osc { #define RTC_DIV 0 #endif /* CONFIG_STM32_CLOCK_HSE_HZ */ - /* Bus clocks dividers depending on the configuration */ /* * max speed configuration with the PLL ON @@ -56,18 +57,18 @@ enum clock_osc { * For STM32F446: max 45 MHz * For STM32F412: max AHB 100 MHz / APB2 100 Mhz / APB1 50 Mhz */ -#define RCC_CFGR_DIVIDERS_WITH_PLL (RCC_CFGR_MCO_CONFIG | \ - CFGR_RTCPRE(RTC_DIV) | \ - CFGR_PPRE2(STM32F4_APB2_PRE) | \ - CFGR_PPRE1(STM32F4_APB1_PRE) | \ - CFGR_HPRE(STM32F4_AHB_PRE)) +#define RCC_CFGR_DIVIDERS_WITH_PLL \ + (RCC_CFGR_MCO_CONFIG | CFGR_RTCPRE(RTC_DIV) | \ + CFGR_PPRE2(STM32F4_APB2_PRE) | CFGR_PPRE1(STM32F4_APB1_PRE) | \ + CFGR_HPRE(STM32F4_AHB_PRE)) /* * lower power configuration without the PLL * the frequency will be low (8-24Mhz), we don't want dividers to the * peripheral clocks, put /1 everywhere. */ -#define RCC_CFGR_DIVIDERS_NO_PLL (RCC_CFGR_MCO_CONFIG | CFGR_RTCPRE(0) | \ - CFGR_PPRE2(0) | CFGR_PPRE1(0) | CFGR_HPRE(0)) +#define RCC_CFGR_DIVIDERS_NO_PLL \ + (RCC_CFGR_MCO_CONFIG | CFGR_RTCPRE(0) | CFGR_PPRE2(0) | \ + CFGR_PPRE1(0) | CFGR_HPRE(0)) /* PLL output frequency */ #define STM32F4_PLL_CLOCK (STM32F4_VCO_CLOCK / STM32F4_PLLP_DIV) @@ -166,8 +167,9 @@ void clock_set_osc(enum clock_osc osc) /* Switch to HSI */ clock_switch_osc(OSC_HSI); /* optimized flash latency settings for <30Mhz clock (0-WS) */ - STM32_FLASH_ACR = (STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK) - | STM32_FLASH_ACR_LATENCY_SLOW; + STM32_FLASH_ACR = + (STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK) | + STM32_FLASH_ACR_LATENCY_SLOW; /* read-back the latency as advised by the Reference Manual */ unused = STM32_FLASH_ACR; /* Turn off the PLL1 to save power */ @@ -182,8 +184,9 @@ void clock_set_osc(enum clock_osc osc) /* Switch to HSE */ clock_switch_osc(OSC_HSE); /* optimized flash latency settings for <30Mhz clock (0-WS) */ - STM32_FLASH_ACR = (STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK) - | STM32_FLASH_ACR_LATENCY_SLOW; + STM32_FLASH_ACR = + (STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK) | + STM32_FLASH_ACR_LATENCY_SLOW; /* read-back the latency as advised by the Reference Manual */ unused = STM32_FLASH_ACR; /* Turn off the PLL1 to save power */ @@ -201,8 +204,9 @@ void clock_set_osc(enum clock_osc osc) * Increase flash latency before transition the clock * Use the minimum Wait States value optimized for the platform. */ - STM32_FLASH_ACR = (STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK) - | STM32_FLASH_ACR_LATENCY; + STM32_FLASH_ACR = + (STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK) | + STM32_FLASH_ACR_LATENCY; /* read-back the latency as advised by the Reference Manual */ unused = STM32_FLASH_ACR; /* Switch to PLL */ @@ -247,17 +251,14 @@ static void clock_pll_configure(void) i2sdiv = (vcoclock + (systemclock / 2)) / systemclock; /* Set up PLL */ - STM32_RCC_PLLCFGR = - PLLCFGR_PLLM(plldiv) | - PLLCFGR_PLLN(pllmult) | - PLLCFGR_PLLP(STM32F4_PLLP_DIV / 2 - 1) | + STM32_RCC_PLLCFGR = PLLCFGR_PLLM(plldiv) | PLLCFGR_PLLN(pllmult) | + PLLCFGR_PLLP(STM32F4_PLLP_DIV / 2 - 1) | #if defined(CONFIG_STM32_CLOCK_HSE_HZ) - PLLCFGR_PLLSRC_HSE | + PLLCFGR_PLLSRC_HSE | #else - PLLCFGR_PLLSRC_HSI | + PLLCFGR_PLLSRC_HSI | #endif - PLLCFGR_PLLQ(usbdiv) | - PLLCFGR_PLLR(i2sdiv); + PLLCFGR_PLLQ(usbdiv) | PLLCFGR_PLLR(i2sdiv); } void low_power_init(void); @@ -300,22 +301,23 @@ void clock_enable_module(enum module_id module, int enable) if (enable) { STM32_RCC_AHB2ENR |= STM32_RCC_AHB2ENR_OTGFSEN; STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_OTGHSEN | - STM32_RCC_AHB1ENR_OTGHSULPIEN; + STM32_RCC_AHB1ENR_OTGHSULPIEN; } else { STM32_RCC_AHB2ENR &= ~STM32_RCC_AHB2ENR_OTGFSEN; STM32_RCC_AHB1ENR &= ~STM32_RCC_AHB1ENR_OTGHSEN & - ~STM32_RCC_AHB1ENR_OTGHSULPIEN; + ~STM32_RCC_AHB1ENR_OTGHSULPIEN; } return; } else if (module == MODULE_I2C) { if (enable) { /* Enable clocks to I2C modules if necessary */ STM32_RCC_APB1ENR |= - STM32_RCC_I2C1EN | STM32_RCC_I2C2EN - | STM32_RCC_I2C3EN | STM32_RCC_FMPI2C4EN; + STM32_RCC_I2C1EN | STM32_RCC_I2C2EN | + STM32_RCC_I2C3EN | STM32_RCC_FMPI2C4EN; STM32_RCC_DCKCFGR2 = - (STM32_RCC_DCKCFGR2 & ~DCKCFGR2_FMPI2C1SEL_MASK) - | DCKCFGR2_FMPI2C1SEL(FMPI2C1SEL_APB); + (STM32_RCC_DCKCFGR2 & + ~DCKCFGR2_FMPI2C1SEL_MASK) | + DCKCFGR2_FMPI2C1SEL(FMPI2C1SEL_APB); } else { STM32_RCC_APB1ENR &= ~(STM32_RCC_I2C1EN | STM32_RCC_I2C2EN | @@ -349,12 +351,14 @@ void clock_enable_module(enum module_id module, int enable) int32_t rtcss_to_us(uint32_t rtcss) { - return ((RTC_PREDIV_S - rtcss) * (SECOND/SCALING) / (RTC_FREQ/SCALING)); + return ((RTC_PREDIV_S - rtcss) * (SECOND / SCALING) / + (RTC_FREQ / SCALING)); } uint32_t us_to_rtcss(int32_t us) { - return (RTC_PREDIV_S - (us * (RTC_FREQ/SCALING) / (SECOND/SCALING))); + return (RTC_PREDIV_S - + (us * (RTC_FREQ / SCALING) / (SECOND / SCALING))); } void rtc_init(void) @@ -365,8 +369,8 @@ void rtc_init(void) STM32_RCC_BDCR = STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC_HSE); #else /* RTC clocked from the LSI, ensure first it is ON */ - wait_for_ready(&(STM32_RCC_CSR), - STM32_RCC_CSR_LSION, STM32_RCC_CSR_LSIRDY); + wait_for_ready(&(STM32_RCC_CSR), STM32_RCC_CSR_LSION, + STM32_RCC_CSR_LSIRDY); STM32_RCC_BDCR = STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC_LSI); #endif @@ -379,11 +383,10 @@ void rtc_init(void) ; /* Set clock prescalars: Needs two separate writes. */ - STM32_RTC_PRER = - (STM32_RTC_PRER & ~STM32_RTC_PRER_S_MASK) | RTC_PREDIV_S; - STM32_RTC_PRER = - (STM32_RTC_PRER & ~STM32_RTC_PRER_A_MASK) - | (RTC_PREDIV_A << 16); + STM32_RTC_PRER = (STM32_RTC_PRER & ~STM32_RTC_PRER_S_MASK) | + RTC_PREDIV_S; + STM32_RTC_PRER = (STM32_RTC_PRER & ~STM32_RTC_PRER_A_MASK) | + (RTC_PREDIV_A << 16); /* Start RTC timer */ STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT; @@ -528,8 +531,9 @@ void __idle(void) /* Set deep sleep bit */ CPU_SCB_SYSCTRL |= 0x4; - set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY - - PLL_LOCK_LATENCY, + set_rtc_alarm(0, + next_delay - STOP_MODE_LATENCY - + PLL_LOCK_LATENCY, &rtc_sleep, 0); /* Switch to HSI */ @@ -540,7 +544,7 @@ void __idle(void) /* ensure outstanding memory transactions complete */ asm volatile("dsb"); - asm("wfi"); + cpu_enter_suspend_mode(); CPU_SCB_SYSCTRL &= ~0x4; @@ -573,30 +577,29 @@ void __idle(void) idle_sleep_cnt++; /* Normal idle : only CPU clock stopped */ - asm("wfi"); + cpu_enter_suspend_mode(); } interrupt_enable(); } } /* Print low power idle statistics. */ -static int command_idle_stats(int argc, char **argv) +static int command_idle_stats(int argc, const char **argv) { timestamp_t ts = get_time(); ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt); ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt); ccprintf("Time spent in deep-sleep: %.6llds\n", - idle_dsleep_time_us); + idle_dsleep_time_us); ccprintf("Num of prevented sleep: %d\n", - idle_sleep_prevented_cnt); + idle_sleep_prevented_cnt); ccprintf("Total time on: %.6llds\n", ts.val); ccprintf("Deep-sleep closest to wake deadline: %dus\n", - dsleep_recovery_margin_us); + dsleep_recovery_margin_us); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, - "", +DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "", "Print last idle stats"); #endif /* CONFIG_LOW_POWER_IDLE */ diff --git a/chip/stm32/clock-stm32g4.c b/chip/stm32/clock-stm32g4.c index b0bf56d85f..dbb8fd88cb 100644 --- a/chip/stm32/clock-stm32g4.c +++ b/chip/stm32/clock-stm32g4.c @@ -1,10 +1,11 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Clocks configuration routines */ +#include "builtin/assert.h" #include "chipset.h" #include "clock.h" #include "clock-f.h" @@ -21,14 +22,14 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) -#define MHZ(x) ((x) * 1000000) -#define WAIT_STATE_FREQ_STEP_HZ MHZ(20) +#define MHZ(x) ((x)*1000000) +#define WAIT_STATE_FREQ_STEP_HZ MHZ(20) /* PLL configuration constants */ -#define STM32G4_SYSCLK_MAX_HZ MHZ(170) -#define STM32G4_HSI_CLK_HZ MHZ(16) -#define STM32G4_PLL_IN_FREQ_HZ MHZ(4) +#define STM32G4_SYSCLK_MAX_HZ MHZ(170) +#define STM32G4_HSI_CLK_HZ MHZ(16) +#define STM32G4_PLL_IN_FREQ_HZ MHZ(4) #define STM32G4_PLL_R 2 #define STM32G4_AHB_PRE 1 #define STM32G4_APB1_PRE 1 @@ -42,7 +43,7 @@ enum rcc_clksrc { }; static void stm32g4_config_pll(uint32_t hclk_hz, uint32_t pll_src, - uint32_t pll_clk_in_hz) + uint32_t pll_clk_in_hz) { /* * The pll output frequency (Fhclkc) is determined by: @@ -81,20 +82,16 @@ static void stm32g4_config_pll(uint32_t hclk_hz, uint32_t pll_src, ASSERT(pll_m && (pll_m <= 16)); ASSERT((pll_n >= 8) && (pll_n <= 127)); - hclk_freq = pll_clk_in_hz * pll_n / (pll_m * - STM32G4_PLL_R * STM32G4_AHB_PRE); + hclk_freq = pll_clk_in_hz * pll_n / + (pll_m * STM32G4_PLL_R * STM32G4_AHB_PRE); /* Ensure that there aren't any integer rounding errors */ ASSERT(hclk_freq == hclk_hz); /* Program PLL config register */ - STM32_RCC_PLLCFGR = PLLCFGR_PLLP(0) | - PLLCFGR_PLLR(STM32G4_PLL_R / 2 - 1) | - PLLCFGR_PLLR_EN | - PLLCFGR_PLLQ(0) | - PLLCFGR_PLLQ_EN | - PLLCFGR_PLLN(pll_n) | - PLLCFGR_PLLM(pll_m - 1) | - pll_src; + STM32_RCC_PLLCFGR = + PLLCFGR_PLLP(0) | PLLCFGR_PLLR(STM32G4_PLL_R / 2 - 1) | + PLLCFGR_PLLR_EN | PLLCFGR_PLLQ(0) | PLLCFGR_PLLQ_EN | + PLLCFGR_PLLN(pll_n) | PLLCFGR_PLLM(pll_m - 1) | pll_src; /* Wait until PLL is locked */ wait_for_ready(&(STM32_RCC_CR), STM32_RCC_CR_PLLON, @@ -116,8 +113,8 @@ static void stm32g4_config_pll(uint32_t hclk_hz, uint32_t pll_src, static void stm32g4_config_low_speed_clock(void) { /* Ensure that LSI is ON */ - wait_for_ready(&(STM32_RCC_CSR), - STM32_RCC_CSR_LSION, STM32_RCC_CSR_LSIRDY); + wait_for_ready(&(STM32_RCC_CSR), STM32_RCC_CSR_LSION, + STM32_RCC_CSR_LSIRDY); /* Setup RTC Clock input */ STM32_RCC_BDCR |= STM32_RCC_BDCR_BDRST; @@ -163,10 +160,10 @@ void stm32g4_set_flash_ws(uint32_t freq_hz) * found in Table 9 of RM0440 - STM32G4 technical reference manual. A * table lookup is not required though as WS = HCLK (MHz) / 20 */ - ws = freq_hz / WAIT_STATE_FREQ_STEP_HZ; + ws = freq_hz / WAIT_STATE_FREQ_STEP_HZ; /* Enable data and instruction cache */ STM32_FLASH_ACR |= STM32_FLASH_ACR_DCEN | STM32_FLASH_ACR_ICEN | - STM32_FLASH_ACR_PRFTEN | ws; + STM32_FLASH_ACR_PRFTEN | ws; } void clock_init(void) @@ -255,16 +252,14 @@ void clock_enable_module(enum module_id module, int enable) } else if (module == MODULE_I2C) { if (enable) { /* Enable clocks to I2C modules if necessary */ - STM32_RCC_APB1ENR1 |= - STM32_RCC_APB1ENR1_I2C1EN | - STM32_RCC_APB1ENR1_I2C2EN | - STM32_RCC_APB1ENR1_I2C3EN; + STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_I2C1EN | + STM32_RCC_APB1ENR1_I2C2EN | + STM32_RCC_APB1ENR1_I2C3EN; STM32_RCC_APB1ENR2 |= STM32_RCC_APB1ENR2_I2C4EN; } else { - STM32_RCC_APB1ENR1 &= - ~(STM32_RCC_APB1ENR1_I2C1EN | - STM32_RCC_APB1ENR1_I2C2EN | - STM32_RCC_APB1ENR1_I2C3EN); + STM32_RCC_APB1ENR1 &= ~(STM32_RCC_APB1ENR1_I2C1EN | + STM32_RCC_APB1ENR1_I2C2EN | + STM32_RCC_APB1ENR1_I2C3EN); STM32_RCC_APB1ENR2 &= ~STM32_RCC_APB1ENR2_I2C4EN; } } else if (module == MODULE_ADC) { @@ -274,7 +269,7 @@ void clock_enable_module(enum module_id module, int enable) STM32_RCC_APB2ENR_ADC345EN); else STM32_RCC_AHB2ENR &= ~(STM32_RCC_AHB2ENR_ADC12EN | - STM32_RCC_APB2ENR_ADC345EN); + STM32_RCC_APB2ENR_ADC345EN); } else { CPRINTS("stm32g4: enable clock module %d not supported", module); diff --git a/chip/stm32/clock-stm32h7.c b/chip/stm32/clock-stm32h7.c index 57dc170dd9..67e17f4174 100644 --- a/chip/stm32/clock-stm32h7.c +++ b/chip/stm32/clock-stm32h7.c @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -13,9 +13,9 @@ * but at least yields predictable behavior. */ - #include <stdbool.h> +#include "builtin/assert.h" #include "chipset.h" #include "clock.h" #include "common.h" @@ -31,7 +31,7 @@ /* Check chip family and variant for compatibility */ #ifndef CHIP_FAMILY_STM32H7 -#error Source clock-stm32h7.c does not support this chip family. +#error Source clock-stm32h7.c does not support this chip family. #endif #ifndef CHIP_VARIANT_STM32H7X3 #error Unsupported chip variant. @@ -39,13 +39,13 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args) enum clock_osc { - OSC_HSI = 0, /* High-speed internal oscillator */ - OSC_CSI, /* Multi-speed internal oscillator: NOT IMPLEMENTED */ - OSC_HSE, /* High-speed external oscillator: NOT IMPLEMENTED */ - OSC_PLL, /* PLL */ + OSC_HSI = 0, /* High-speed internal oscillator */ + OSC_CSI, /* Multi-speed internal oscillator: NOT IMPLEMENTED */ + OSC_HSE, /* High-speed external oscillator: NOT IMPLEMENTED */ + OSC_PLL, /* PLL */ }; enum voltage_scale { @@ -57,12 +57,12 @@ enum voltage_scale { }; enum freq { - FREQ_1KHZ = 1000, - FREQ_32KHZ = 32 * FREQ_1KHZ, - FREQ_1MHZ = 1000000, - FREQ_2MHZ = 2 * FREQ_1MHZ, - FREQ_16MHZ = 16 * FREQ_1MHZ, - FREQ_64MHZ = 64 * FREQ_1MHZ, + FREQ_1KHZ = 1000, + FREQ_32KHZ = 32 * FREQ_1KHZ, + FREQ_1MHZ = 1000000, + FREQ_2MHZ = 2 * FREQ_1MHZ, + FREQ_16MHZ = 16 * FREQ_1MHZ, + FREQ_64MHZ = 64 * FREQ_1MHZ, FREQ_140MHZ = 140 * FREQ_1MHZ, FREQ_200MHZ = 200 * FREQ_1MHZ, FREQ_280MHZ = 280 * FREQ_1MHZ, @@ -144,13 +144,13 @@ static void clock_flash_latency(enum freq axi_freq, enum voltage_scale vos) * * @param output_freq The target output frequency. */ -static void clock_pll1_configure(enum freq output_freq) { +static void clock_pll1_configure(enum freq output_freq) +{ uint32_t divm = 4; // Input prescaler (16MHz max for PLL -- 64/4 ==> 16) - uint32_t divn; // Pll multiplier - uint32_t divp; // Output 1 prescaler + uint32_t divn; // Pll multiplier + uint32_t divp; // Output 1 prescaler - switch (output_freq) - { + switch (output_freq) { case FREQ_400MHZ: /* * PLL1 configuration: @@ -190,8 +190,8 @@ static void clock_pll1_configure(enum freq output_freq) { * Using VCO wide-range setting, STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE, * requires input frequency to be between 2MHz and 16MHz. */ - ASSERT(FREQ_2MHZ <= (STM32_HSI_CLOCK/divm)); - ASSERT((STM32_HSI_CLOCK/divm) <= FREQ_16MHZ); + ASSERT(FREQ_2MHZ <= (STM32_HSI_CLOCK / divm)); + ASSERT((STM32_HSI_CLOCK / divm) <= FREQ_16MHZ); /* * Ensure that we actually reach the target frequency. @@ -199,14 +199,14 @@ static void clock_pll1_configure(enum freq output_freq) { ASSERT((STM32_HSI_CLOCK / divm * divn / divp) == output_freq); /* Configure PLL1 using 64 Mhz HSI as input */ - STM32_RCC_PLLCKSELR = STM32_RCC_PLLCKSEL_PLLSRC_HSI - | STM32_RCC_PLLCKSEL_DIVM1(divm); + STM32_RCC_PLLCKSELR = STM32_RCC_PLLCKSEL_PLLSRC_HSI | + STM32_RCC_PLLCKSEL_DIVM1(divm); /* in integer mode, wide range VCO with 16Mhz input, use divP */ - STM32_RCC_PLLCFGR = STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE - | STM32_RCC_PLLCFG_PLL1RGE_8M_16M - | STM32_RCC_PLLCFG_DIVP1EN; - STM32_RCC_PLL1DIVR = STM32_RCC_PLLDIV_DIVP(divp) - | STM32_RCC_PLLDIV_DIVN(divn); + STM32_RCC_PLLCFGR = STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE | + STM32_RCC_PLLCFG_PLL1RGE_8M_16M | + STM32_RCC_PLLCFG_DIVP1EN; + STM32_RCC_PLL1DIVR = STM32_RCC_PLLDIV_DIVP(divp) | + STM32_RCC_PLLDIV_DIVN(divn); } /** @@ -215,22 +215,22 @@ static void clock_pll1_configure(enum freq output_freq) { * @param sysclk The input system clock, after the system clock prescaler. * @return The bus clock speed selected and configured */ -static enum freq clock_peripheral_configure(enum freq sysclk) { - switch (sysclk) - { +static enum freq clock_peripheral_configure(enum freq sysclk) +{ + switch (sysclk) { case FREQ_64MHZ: /* Restore /1 HPRE (AHB prescaler) */ /* Disable downstream prescalers */ - STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV1 - | STM32_RCC_D1CFGR_D1PPRE_DIV1 - | STM32_RCC_D1CFGR_D1CPRE_DIV1; + STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV1 | + STM32_RCC_D1CFGR_D1PPRE_DIV1 | + STM32_RCC_D1CFGR_D1CPRE_DIV1; /* TODO(b/149512910): Adjust more peripheral prescalers */ return FREQ_64MHZ; case FREQ_400MHZ: /* Put /2 on HPRE (AHB prescaler) to keep at the 200MHz max */ - STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV2 - | STM32_RCC_D1CFGR_D1PPRE_DIV1 - | STM32_RCC_D1CFGR_D1CPRE_DIV1; + STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV2 | + STM32_RCC_D1CFGR_D1PPRE_DIV1 | + STM32_RCC_D1CFGR_D1CPRE_DIV1; /* TODO(b/149512910): Adjust more peripheral prescalers */ return FREQ_200MHZ; default: @@ -293,16 +293,16 @@ static void clock_switch_osc(enum clock_osc osc) static void switch_voltage_scale(enum voltage_scale vos) { - volatile uint32_t *const vos_reg = &STM32_PWR_D3CR; - const uint32_t vos_ready = STM32_PWR_D3CR_VOSRDY; - const uint32_t vos_mask = STM32_PWR_D3CR_VOSMASK; - const uint32_t vos_values[] = { - /* See note below about VOS0. */ - STM32_PWR_D3CR_VOS1, - STM32_PWR_D3CR_VOS1, - STM32_PWR_D3CR_VOS2, - STM32_PWR_D3CR_VOS3, - }; + volatile uint32_t *const vos_reg = &STM32_PWR_D3CR; + const uint32_t vos_ready = STM32_PWR_D3CR_VOSRDY; + const uint32_t vos_mask = STM32_PWR_D3CR_VOSMASK; + const uint32_t vos_values[] = { + /* See note below about VOS0. */ + STM32_PWR_D3CR_VOS1, + STM32_PWR_D3CR_VOS1, + STM32_PWR_D3CR_VOS2, + STM32_PWR_D3CR_VOS3, + }; BUILD_ASSERT(ARRAY_SIZE(vos_values) == VOLTAGE_SCALE_COUNT); /* @@ -344,7 +344,8 @@ static void clock_set_osc(enum clock_osc osc) case OSC_HSI: /* Switch to HSI */ clock_switch_osc(osc); - current_bus_freq = clock_peripheral_configure(target_sysclk_freq); + current_bus_freq = + clock_peripheral_configure(target_sysclk_freq); /* Use more optimized flash latency settings for 64-MHz ACLK */ clock_flash_latency(current_bus_freq, target_voltage_scale); /* Turn off the PLL1 to save power */ @@ -368,7 +369,8 @@ static void clock_set_osc(enum clock_osc osc) clock_pll1_configure(target_sysclk_freq); /* turn on PLL1 and wait until it's ready */ clock_enable_osc(OSC_PLL, true); - current_bus_freq = clock_peripheral_configure(target_sysclk_freq); + current_bus_freq = + clock_peripheral_configure(target_sysclk_freq); /* Increase flash latency before transition the clock */ clock_flash_latency(current_bus_freq, target_voltage_scale); @@ -408,9 +410,9 @@ static int dsleep_recovery_margin_us = 1000000; static void low_power_init(void) { /* Clock LPTIM1 on the 32-kHz LSI for STOP mode time keeping */ - STM32_RCC_D2CCIP2R = (STM32_RCC_D2CCIP2R & - ~STM32_RCC_D2CCIP2_LPTIM1SEL_MASK) - | STM32_RCC_D2CCIP2_LPTIM1SEL_LSI; + STM32_RCC_D2CCIP2R = + (STM32_RCC_D2CCIP2R & ~STM32_RCC_D2CCIP2_LPTIM1SEL_MASK) | + STM32_RCC_D2CCIP2_LPTIM1SEL_LSI; /* configure LPTIM1 as our 1-Khz low power timer in STOP mode */ STM32_RCC_APB1LENR |= STM32_RCC_PB1_LPTIM1; @@ -428,9 +430,8 @@ static void low_power_init(void) STM32_EXTI_CPUIMR2 |= BIT(15); /* [15] wkup47: LPTIM1 wake-up */ /* optimize power vs latency in STOP mode */ - STM32_PWR_CR = (STM32_PWR_CR & ~STM32_PWR_CR_SVOS_MASK) - | STM32_PWR_CR_SVOS5 - | STM32_PWR_CR_FLPS; + STM32_PWR_CR = (STM32_PWR_CR & ~STM32_PWR_CR_SVOS_MASK) | + STM32_PWR_CR_SVOS5 | STM32_PWR_CR_FLPS; } void clock_refresh_console_in_use(void) @@ -544,7 +545,7 @@ void __idle(void) /* ensure outstanding memory transactions complete */ asm volatile("dsb"); - asm("wfi"); + cpu_enter_suspend_mode(); CPU_SCB_SYSCTRL &= ~0x4; @@ -579,7 +580,7 @@ void __idle(void) idle_sleep_cnt++; /* normal idle : only CPU clock stopped */ - asm("wfi"); + cpu_enter_suspend_mode(); } interrupt_enable(); } @@ -589,24 +590,23 @@ void __idle(void) /** * Print low power idle statistics */ -static int command_idle_stats(int argc, char **argv) +static int command_idle_stats(int argc, const char **argv) { timestamp_t ts = get_time(); ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt); ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt); ccprintf("Time spent in deep-sleep: %.6llds\n", - idle_dsleep_time_us); + idle_dsleep_time_us); ccprintf("Num of prevented sleep: %d\n", - idle_sleep_prevented_cnt); + idle_sleep_prevented_cnt); ccprintf("Total time on: %.6llds\n", ts.val); ccprintf("Deep-sleep closest to wake deadline: %dus\n", - dsleep_recovery_margin_us); + dsleep_recovery_margin_us); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, - "", +DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "", "Print last idle stats"); #endif /* CONFIG_CMD_IDLE_STATS */ #endif /* CONFIG_LOW_POWER_IDLE */ @@ -638,11 +638,11 @@ void clock_init(void) * by putting it on the fixed 64-Mhz HSI clock. * per_ck is clocked directly by the HSI (as per the default settings). */ - STM32_RCC_D2CCIP1R = (STM32_RCC_D2CCIP1R & - ~(STM32_RCC_D2CCIP1R_SPI123SEL_MASK | - STM32_RCC_D2CCIP1R_SPI45SEL_MASK)) - | STM32_RCC_D2CCIP1R_SPI123SEL_PERCK - | STM32_RCC_D2CCIP1R_SPI45SEL_HSI; + STM32_RCC_D2CCIP1R = + (STM32_RCC_D2CCIP1R & ~(STM32_RCC_D2CCIP1R_SPI123SEL_MASK | + STM32_RCC_D2CCIP1R_SPI45SEL_MASK)) | + STM32_RCC_D2CCIP1R_SPI123SEL_PERCK | + STM32_RCC_D2CCIP1R_SPI45SEL_HSI; /* Use more optimized flash latency settings for ACLK = HSI = 64 Mhz */ clock_flash_latency(FREQ_64MHZ, VOLTAGE_SCALE3); @@ -657,7 +657,7 @@ void clock_init(void) #endif } -static int command_clock(int argc, char **argv) +static int command_clock(int argc, const char **argv) { if (argc >= 2) { if (!strcasecmp(argv[1], "hsi")) @@ -670,5 +670,5 @@ static int command_clock(int argc, char **argv) ccprintf("Clock frequency is now %d Hz\n", clock_get_freq()); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(clock, command_clock, - "hsi | pll", "Set clock frequency"); +DECLARE_CONSOLE_COMMAND(clock, command_clock, "hsi | pll", + "Set clock frequency"); diff --git a/chip/stm32/clock-stm32l.c b/chip/stm32/clock-stm32l.c index bb0da42d14..1d0252302a 100644 --- a/chip/stm32/clock-stm32l.c +++ b/chip/stm32/clock-stm32l.c @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -37,9 +37,9 @@ static int fake_hibernate; #define MSI_1MHZ_CLOCK BIT(20) enum clock_osc { - OSC_INIT = 0, /* Uninitialized */ - OSC_HSI, /* High-speed oscillator */ - OSC_MSI, /* Med-speed oscillator @ 1 MHz */ + OSC_INIT = 0, /* Uninitialized */ + OSC_HSI, /* High-speed oscillator */ + OSC_MSI, /* Med-speed oscillator @ 1 MHz */ }; static int freq; @@ -86,8 +86,8 @@ static void clock_set_osc(enum clock_osc osc) switch (osc) { case OSC_HSI: /* Ensure that HSI is ON */ - wait_for_ready(&STM32_RCC_CR, - STM32_RCC_CR_HSION, STM32_RCC_CR_HSIRDY); + wait_for_ready(&STM32_RCC_CR, STM32_RCC_CR_HSION, + STM32_RCC_CR_HSIRDY); /* Disable LPSDSR */ STM32_PWR_CR &= ~STM32_PWR_CR_LPSDSR; @@ -122,7 +122,7 @@ static void clock_set_osc(enum clock_osc osc) STM32_RCC_CFGR = STM32_RCC_CFGR_SW_HSI; /* RM says to check SWS bits to make sure HSI is the sysclock */ while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) != - STM32_RCC_CFGR_SWS_HSI) + STM32_RCC_CFGR_SWS_HSI) ; /* Disable MSI */ @@ -137,14 +137,14 @@ static void clock_set_osc(enum clock_osc osc) (STM32_RCC_ICSCR & ~STM32_RCC_ICSCR_MSIRANGE_MASK) | STM32_RCC_ICSCR_MSIRANGE_1MHZ; /* Ensure that MSI is ON */ - wait_for_ready(&STM32_RCC_CR, - STM32_RCC_CR_MSION, STM32_RCC_CR_MSIRDY); + wait_for_ready(&STM32_RCC_CR, STM32_RCC_CR_MSION, + STM32_RCC_CR_MSIRDY); /* Switch to MSI */ STM32_RCC_CFGR = STM32_RCC_CFGR_SW_MSI; /* RM says to check SWS bits to make sure MSI is the sysclock */ while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) != - STM32_RCC_CFGR_SWS_MSI) + STM32_RCC_CFGR_SWS_MSI) ; /* @@ -208,7 +208,6 @@ void clock_enable_module(enum module_id module, int enable) /* Only change clock if needed */ if ((!!new_mask) != (!!clock_mask)) { - /* Flush UART before switching clock speed */ cflush(); @@ -314,7 +313,7 @@ static void fake_hibernate_power_button_hook(void) } } DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, fake_hibernate_power_button_hook, - HOOK_PRIO_DEFAULT); + HOOK_PRIO_DEFAULT); static void fake_hibernate_lid_hook(void) { @@ -365,7 +364,7 @@ static void clock_chipset_shutdown(void) DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, clock_chipset_shutdown, HOOK_PRIO_DEFAULT); DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, clock_chipset_shutdown, HOOK_PRIO_DEFAULT); -static int command_clock(int argc, char **argv) +static int command_clock(int argc, const char **argv) { if (argc >= 2) { if (!strcasecmp(argv[1], "hsi")) @@ -379,6 +378,5 @@ static int command_clock(int argc, char **argv) ccprintf("Clock frequency is now %d Hz\n", freq); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(clock, command_clock, - "hsi | msi", +DECLARE_CONSOLE_COMMAND(clock, command_clock, "hsi | msi", "Set clock frequency"); diff --git a/chip/stm32/clock-stm32l4.c b/chip/stm32/clock-stm32l4.c index 730f5d6bb9..1c460c10fc 100644 --- a/chip/stm32/clock-stm32l4.c +++ b/chip/stm32/clock-stm32l4.c @@ -1,10 +1,11 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Clocks and power management settings for STM32L4xx as well as STM32L5xx. */ +#include "builtin/assert.h" #include "chipset.h" #include "clock.h" #include "clock-l4.h" @@ -21,7 +22,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) /* High-speed oscillator is 16 MHz */ #define STM32_HSI_CLOCK 16000000 @@ -45,13 +46,13 @@ #define SCALING 1000 enum clock_osc { - OSC_INIT = 0, /* Uninitialized */ - OSC_HSI, /* High-speed internal oscillator */ - OSC_MSI, /* Multi-speed internal oscillator */ -#ifdef STM32_HSE_CLOCK /* Allows us to catch absence of HSE at comiple time */ - OSC_HSE, /* High-speed external oscillator */ + OSC_INIT = 0, /* Uninitialized */ + OSC_HSI, /* High-speed internal oscillator */ + OSC_MSI, /* Multi-speed internal oscillator */ +#ifdef STM32_HSE_CLOCK /* Allows us to catch absence of HSE at comiple time */ + OSC_HSE, /* High-speed external oscillator */ #endif - OSC_PLL, /* PLL */ + OSC_PLL, /* PLL */ }; static int freq = STM32_MSI_CLOCK; @@ -162,8 +163,8 @@ static void clock_switch_osc(enum clock_osc osc) * 5. Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, PLLREN * in RCC_PLLCFGR. */ -static int stm32_configure_pll(enum clock_osc osc, - uint8_t m, uint8_t n, uint8_t r) +static int stm32_configure_pll(enum clock_osc osc, uint8_t m, uint8_t n, + uint8_t r) { uint32_t val; bool pll_unchanged; @@ -323,9 +324,8 @@ static void clock_set_osc(enum clock_osc osc, enum clock_osc pll_osc) case OSC_MSI: /* Switch to MSI @ 1MHz */ - STM32_RCC_CR = - (STM32_RCC_CR & ~STM32_RCC_ICSCR_MSIRANGE_MASK) | - STM32_RCC_ICSCR_MSIRANGE_1MHZ; + STM32_RCC_CR = (STM32_RCC_CR & ~STM32_RCC_ICSCR_MSIRANGE_MASK) | + STM32_RCC_ICSCR_MSIRANGE_1MHZ; /* Ensure that MSI is ON */ clock_enable_osc(osc); @@ -353,7 +353,7 @@ static void clock_set_osc(enum clock_osc osc, enum clock_osc pll_osc) /* Disable other clock sources */ STM32_RCC_CR &= ~(STM32_RCC_CR_MSION | STM32_RCC_CR_HSION | - STM32_RCC_CR_PLLON); + STM32_RCC_CR_PLLON); freq = STM32_HSE_CLOCK; @@ -396,22 +396,22 @@ static void clock_set_osc(enum clock_osc osc, enum clock_osc pll_osc) */ val = STM32_FLASH_ACR; val &= ~STM32_FLASH_ACR_LATENCY_MASK; - if (freq <= 16000000U) { + if (freq <= 16000000U) { val = val; - } else if (freq <= 32000000U) { + } else if (freq <= 32000000U) { val |= 1; - } else if (freq <= 48000000U) { + } else if (freq <= 48000000U) { val |= 2; - } else if (freq <= 64000000U) { + } else if (freq <= 64000000U) { val |= 3; - } else if (freq <= 80000000U) { + } else if (freq <= 80000000U) { val |= 4; - } else { + } else { val |= 4; CPUTS("Incorrect Frequency setting in VOS1!\n"); } STM32_FLASH_ACR = val; - } else { + } else { val = STM32_FLASH_ACR; val &= ~STM32_FLASH_ACR_LATENCY_MASK; @@ -423,7 +423,7 @@ static void clock_set_osc(enum clock_osc osc, enum clock_osc pll_osc) val |= 2; } else if (freq <= 26000000U) { val |= 3; - } else { + } else { val |= 4; CPUTS("Incorrect Frequency setting in VOS2!\n"); } @@ -472,8 +472,8 @@ void clock_enable_module(enum module_id module, int enable) /* ADC select bit 28/29 */ STM32_RCC_CCIPR &= ~STM32_RCC_CCIPR_ADCSEL_MSK; - STM32_RCC_CCIPR |= (STM32_RCC_CCIPR_ADCSEL_0 | - STM32_RCC_CCIPR_ADCSEL_1); + STM32_RCC_CCIPR |= + (STM32_RCC_CCIPR_ADCSEL_0 | STM32_RCC_CCIPR_ADCSEL_1); /* ADC clock enable */ if (enable) STM32_RCC_AHB2ENR |= STM32_RCC_HB2_ADC1; @@ -484,12 +484,11 @@ void clock_enable_module(enum module_id module, int enable) STM32_RCC_APB1ENR1 |= STM32_RCC_PB1_SPI2; else STM32_RCC_APB1ENR1 &= ~STM32_RCC_PB1_SPI2; - } else if (module == MODULE_SPI || - module == MODULE_SPI_CONTROLLER) { + } else if (module == MODULE_SPI || module == MODULE_SPI_CONTROLLER) { if (enable) STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_SPI1EN; - else if ((new_mask & (BIT(MODULE_SPI) | - BIT(MODULE_SPI_CONTROLLER))) == 0) + else if ((new_mask & + (BIT(MODULE_SPI) | BIT(MODULE_SPI_CONTROLLER))) == 0) STM32_RCC_APB2ENR &= ~STM32_RCC_APB2ENR_SPI1EN; } else if (module == MODULE_USB) { #ifdef CHIP_FAMILY_STM32L5 @@ -588,7 +587,6 @@ void rtc_set(uint32_t sec) } #endif - void clock_init(void) { #ifdef STM32_HSE_CLOCK @@ -623,7 +621,7 @@ static void clock_chipset_shutdown(void) DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, clock_chipset_shutdown, HOOK_PRIO_DEFAULT); DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, clock_chipset_shutdown, HOOK_PRIO_DEFAULT); -static int command_clock(int argc, char **argv) +static int command_clock(int argc, const char **argv) { if (argc >= 2) { if (!strcasecmp(argv[1], "hsi")) @@ -666,7 +664,6 @@ uint32_t us_to_rtcss(uint32_t us) (us * (RTC_FREQ / SCALING) / (SECOND / SCALING))); } - /* Convert decimal to BCD */ static uint8_t u8_to_bcd(uint8_t val) { @@ -684,12 +681,14 @@ static uint32_t rtc_tr_to_sec(uint32_t rtc_tr) /* convert the hours field */ sec = (((rtc_tr & RTC_TR_HT) >> RTC_TR_HT_POS) * 10 + - ((rtc_tr & RTC_TR_HU) >> RTC_TR_HU_POS)) * 3600; + ((rtc_tr & RTC_TR_HU) >> RTC_TR_HU_POS)) * + 3600; /* convert the minutes field */ sec += (((rtc_tr & RTC_TR_MNT) >> RTC_TR_MNT_POS) * 10 + - ((rtc_tr & RTC_TR_MNU) >> RTC_TR_MNU_POS)) * 60; + ((rtc_tr & RTC_TR_MNU) >> RTC_TR_MNU_POS)) * + 60; /* convert the seconds field */ - sec += ((rtc_tr & RTC_TR_ST) >> RTC_TR_ST_POS) * 10 + + sec += ((rtc_tr & RTC_TR_ST) >> RTC_TR_ST_POS) * 10 + (rtc_tr & RTC_TR_SU); return sec; } @@ -766,10 +765,9 @@ static uint32_t rtc_dr_to_sec(uint32_t rtc_dr) struct calendar_date time; uint32_t sec; - time.year = (((rtc_dr & 0xf00000) >> 20) * 10 + - ((rtc_dr & 0xf0000) >> 16)); - time.month = (((rtc_dr & 0x1000) >> 12) * 10 + - ((rtc_dr & 0xf00) >> 8)); + time.year = + (((rtc_dr & 0xf00000) >> 20) * 10 + ((rtc_dr & 0xf0000) >> 16)); + time.month = (((rtc_dr & 0x1000) >> 12) * 10 + ((rtc_dr & 0xf00) >> 8)); time.day = ((rtc_dr & 0x30) >> 4) * 10 + (rtc_dr & 0xf); sec = date_to_sec(time); @@ -905,8 +903,8 @@ void set_rtc_alarm(uint32_t delay_s, uint32_t delay_us, * If the caller doesn't specify subsecond delay (e.g. host command), * just align the alarm time to second. */ - STM32_RTC_ALRMASSR = delay_us ? - (us_to_rtcss(alarm_us) | 0x0f000000) : 0; + STM32_RTC_ALRMASSR = delay_us ? (us_to_rtcss(alarm_us) | 0x0f000000) : + 0; #ifdef CONFIG_HOSTCMD_RTC /* @@ -968,8 +966,7 @@ static void set_rtc_host_event(void) DECLARE_DEFERRED(set_rtc_host_event); #endif -test_mockable_static -void __rtc_alarm_irq(void) +test_mockable_static void __rtc_alarm_irq(void) { struct rtc_time_reg rtc; @@ -985,7 +982,6 @@ void __rtc_alarm_irq(void) } DECLARE_IRQ(STM32_IRQ_RTC_ALARM, __rtc_alarm_irq, 1); - void print_system_rtc(enum console_channel ch) { uint32_t sec; @@ -997,7 +993,6 @@ void print_system_rtc(enum console_channel ch) cprintf(ch, "RTC: 0x%08x (%d.00 s)\n", sec, sec); } - #ifdef CONFIG_LOW_POWER_IDLE /* Low power idle statistics */ static int idle_sleep_cnt; @@ -1015,7 +1010,6 @@ static int dsleep_recovery_margin_us = 1000000; */ #define SET_RTC_MATCH_DELAY 120 /* us */ - void low_power_init(void) { /* Enter stop1 mode */ @@ -1055,15 +1049,15 @@ void __idle(void) /* Set deep sleep bit */ CPU_SCB_SYSCTRL |= 0x4; - set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY - - PLL_LOCK_LATENCY, + set_rtc_alarm(0, + next_delay - STOP_MODE_LATENCY - + PLL_LOCK_LATENCY, &rtc0, 0); - /* ensure outstanding memory transactions complete */ asm volatile("dsb"); - asm("wfi"); + cpu_enter_suspend_mode(); CPU_SCB_SYSCTRL &= ~0x4; @@ -1071,8 +1065,8 @@ void __idle(void) STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_PWREN; clock_wait_bus_cycles(BUS_APB, 2); - stm32_configure_pll(OSC_HSI, STM32_PLLM, - STM32_PLLN, STM32_PLLR); + stm32_configure_pll(OSC_HSI, STM32_PLLM, STM32_PLLN, + STM32_PLLR); /* Switch to PLL */ clock_switch_osc(OSC_PLL); @@ -1101,7 +1095,7 @@ void __idle(void) idle_sleep_cnt++; /* Normal idle : only CPU clock stopped */ - asm("wfi"); + cpu_enter_suspend_mode(); } interrupt_enable(); } @@ -1110,21 +1104,20 @@ void __idle(void) /*****************************************************************************/ /* Console commands */ /* Print low power idle statistics. */ -static int command_idle_stats(int argc, char **argv) +static int command_idle_stats(int argc, const char **argv) { timestamp_t ts = get_time(); ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt); ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt); ccprintf("Time spent in deep-sleep: %.6llus\n", - idle_dsleep_time_us); + idle_dsleep_time_us); ccprintf("Total time on: %.6llus\n", ts.val); ccprintf("Deep-sleep closest to wake deadline: %dus\n", - dsleep_recovery_margin_us); + dsleep_recovery_margin_us); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, - "", +DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "", "Print last idle stats"); #endif /* CONFIG_LOW_POWER_IDLE */ diff --git a/chip/stm32/clock-stm32l5.c b/chip/stm32/clock-stm32l5.c index 63f5b874bc..a4cf34f7b8 100644 --- a/chip/stm32/clock-stm32l5.c +++ b/chip/stm32/clock-stm32l5.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/stm32/config-stm32f03x.h b/chip/stm32/config-stm32f03x.h index 3c51086c26..695b16f0b3 100644 --- a/chip/stm32/config-stm32f03x.h +++ b/chip/stm32/config-stm32f03x.h @@ -1,25 +1,25 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ #ifdef CHIP_VARIANT_STM32F03X8 #define CONFIG_FLASH_SIZE_BYTES 0x00010000 -#define CONFIG_RAM_SIZE 0x00002000 +#define CONFIG_RAM_SIZE 0x00002000 #else #define CONFIG_FLASH_SIZE_BYTES 0x00008000 -#define CONFIG_RAM_SIZE 0x00001000 +#define CONFIG_RAM_SIZE 0x00001000 #endif /* Memory mapping */ -#define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */ -#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ +#define CONFIG_FLASH_BANK_SIZE 0x1000 +#define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */ +#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ /* No page mode on STM32F, so no benefit to larger write sizes */ #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002 -#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_BASE 0x20000000 /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 32 diff --git a/chip/stm32/config-stm32f05x.h b/chip/stm32/config-stm32f05x.h index 00bf45fde5..7f083b0eb2 100644 --- a/chip/stm32/config-stm32f05x.h +++ b/chip/stm32/config-stm32f05x.h @@ -1,19 +1,19 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Memory mapping */ #define CONFIG_FLASH_SIZE_BYTES (64 * 1024) -#define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */ -#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ +#define CONFIG_FLASH_BANK_SIZE 0x1000 +#define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */ +#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ /* No page mode on STM32F, so no benefit to larger write sizes */ #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002 -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00002000 +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00002000 /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 32 diff --git a/chip/stm32/config-stm32f07x.h b/chip/stm32/config-stm32f07x.h index 2aa8f6d37d..31468f656e 100644 --- a/chip/stm32/config-stm32f07x.h +++ b/chip/stm32/config-stm32f07x.h @@ -1,19 +1,19 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Memory mapping */ #define CONFIG_FLASH_SIZE_BYTES (128 * 1024) -#define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ -#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ +#define CONFIG_FLASH_BANK_SIZE 0x1000 +#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ +#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ /* No page mode on STM32F, so no benefit to larger write sizes */ #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002 -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00004000 +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00004000 /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 32 @@ -23,10 +23,10 @@ #define CONFIG_CONSOLE_HISTORY 3 /* USB packet ram config */ -#define CONFIG_USB_RAM_BASE 0x40006000 -#define CONFIG_USB_RAM_SIZE 1024 +#define CONFIG_USB_RAM_BASE 0x40006000 +#define CONFIG_USB_RAM_SIZE 1024 #define CONFIG_USB_RAM_ACCESS_TYPE uint16_t #define CONFIG_USB_RAM_ACCESS_SIZE 2 /* DFU Address */ -#define STM32_DFU_BASE 0x1fffC800 +#define STM32_DFU_BASE 0x1fffC800 diff --git a/chip/stm32/config-stm32f09x.h b/chip/stm32/config-stm32f09x.h index 527e84db1b..405c63f3ec 100644 --- a/chip/stm32/config-stm32f09x.h +++ b/chip/stm32/config-stm32f09x.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,15 +9,15 @@ * Write protect sectors: 31 4KB sectors, one 132KB sector */ #define CONFIG_FLASH_SIZE_BYTES 0x00040000 -#define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ -#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ +#define CONFIG_FLASH_BANK_SIZE 0x1000 +#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ +#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ /* No page mode on STM32F, so no benefit to larger write sizes */ #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002 -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00008000 +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00008000 /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 32 @@ -43,33 +43,33 @@ * */ -#define _SECTOR_4KB (4 * 1024) -#define _SECTOR_132KB (132 * 1024) +#define _SECTOR_4KB (4 * 1024) +#define _SECTOR_132KB (132 * 1024) /* The EC uses one sector to emulate persistent state */ #define CONFIG_FLASH_PSTATE -#define CONFIG_FW_PSTATE_SIZE _SECTOR_4KB -#define CONFIG_FW_PSTATE_OFF (30 * _SECTOR_4KB) +#define CONFIG_FW_PSTATE_SIZE _SECTOR_4KB +#define CONFIG_FW_PSTATE_OFF (30 * _SECTOR_4KB) -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RO_SIZE (30 * _SECTOR_4KB) -#define CONFIG_RW_MEM_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + \ - CONFIG_FW_PSTATE_SIZE) -#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE _SECTOR_132KB +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RO_SIZE (30 * _SECTOR_4KB) +#define CONFIG_RW_MEM_OFF \ + (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + CONFIG_FW_PSTATE_SIZE) +#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RW_SIZE _SECTOR_132KB -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 #define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE (CONFIG_FLASH_SIZE_BYTES - \ - CONFIG_EC_WRITABLE_STORAGE_OFF) +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ + (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE /* We map each write protect sector to a bank */ -#define PHYSICAL_BANKS 32 -#define WP_BANK_COUNT 31 -#define PSTATE_BANK 30 -#define PSTATE_BANK_COUNT 1 +#define PHYSICAL_BANKS 32 +#define WP_BANK_COUNT 31 +#define PSTATE_BANK 30 +#define PSTATE_BANK_COUNT 1 diff --git a/chip/stm32/config-stm32f373.h b/chip/stm32/config-stm32f373.h index 7694db4421..f57350a17c 100644 --- a/chip/stm32/config-stm32f373.h +++ b/chip/stm32/config-stm32f373.h @@ -1,28 +1,28 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Memory mapping */ #define CONFIG_FLASH_SIZE_BYTES 0x00040000 -#define CONFIG_FLASH_BANK_SIZE 0x2000 -#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ -#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ +#define CONFIG_FLASH_BANK_SIZE 0x2000 +#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ +#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ /* No page mode on STM32F, so no benefit to larger write sizes */ #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002 -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00008000 +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00008000 /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 81 /* STM32F3 uses the older 4 byte aligned access mechanism */ -#define CONFIG_USB_RAM_BASE 0x40006000 -#define CONFIG_USB_RAM_SIZE 512 +#define CONFIG_USB_RAM_BASE 0x40006000 +#define CONFIG_USB_RAM_SIZE 512 #define CONFIG_USB_RAM_ACCESS_TYPE uint32_t #define CONFIG_USB_RAM_ACCESS_SIZE 4 /* DFU Address */ -#define STM32_DFU_BASE 0x1fffd800 +#define STM32_DFU_BASE 0x1fffd800 diff --git a/chip/stm32/config-stm32f4.h b/chip/stm32/config-stm32f4.h index ee1d594116..d7ef668886 100644 --- a/chip/stm32/config-stm32f4.h +++ b/chip/stm32/config-stm32f4.h @@ -1,13 +1,13 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Memory mapping */ #ifdef CHIP_VARIANT_STM32F412 -# define CONFIG_FLASH_SIZE_BYTES (1 * 1024 * 1024) +#define CONFIG_FLASH_SIZE_BYTES (1 * 1024 * 1024) #else -# define CONFIG_FLASH_SIZE_BYTES (512 * 1024) +#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) #endif /* 3 regions type: 16K, 64K and 128K */ @@ -31,33 +31,32 @@ #define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_WRITE_SIZE #ifdef CHIP_VARIANT_STM32F412 -# define CONFIG_RAM_BASE 0x20000000 -# define CONFIG_RAM_SIZE 0x00040000 /* 256 KB */ +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00040000 /* 256 KB */ #else -# define CONFIG_RAM_BASE 0x20000000 -# define CONFIG_RAM_SIZE 0x00020000 /* 128 KB */ +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00020000 /* 128 KB */ #endif -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (256 * 1024) -#define CONFIG_RW_MEM_OFF (256 * 1024) -#define CONFIG_RW_SIZE (256 * 1024) +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_SIZE (256 * 1024) +#define CONFIG_RW_MEM_OFF (256 * 1024) +#define CONFIG_RW_SIZE (256 * 1024) -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ - (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) - -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ + (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE #undef I2C_PORT_COUNT -#define I2C_PORT_COUNT 4 +#define I2C_PORT_COUNT 4 /* Use PSTATE embedded in the RO image, not in its own erase block */ #define CONFIG_FLASH_PSTATE @@ -67,12 +66,12 @@ #define CONFIG_OTP /* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 97 +#define CONFIG_IRQ_COUNT 97 #undef CONFIG_CMD_CHARGEN /* DFU Address */ -#define STM32_DFU_BASE 0x1fff0000 +#define STM32_DFU_BASE 0x1fff0000 /* * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. If we set the alarm diff --git a/chip/stm32/config-stm32f76x.h b/chip/stm32/config-stm32f76x.h index aa7f7ac5c0..e7380118f0 100644 --- a/chip/stm32/config-stm32f76x.h +++ b/chip/stm32/config-stm32f76x.h @@ -1,10 +1,10 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES (2048 * 1024) +#define CONFIG_FLASH_SIZE_BYTES (2048 * 1024) /* 3 regions type: 32K, 128K and 256K */ #define SIZE_32KB (32 * 1024) @@ -29,35 +29,35 @@ /* DTCM-RAM: 128kB 0x20000000 - 0x2001FFFF*/ /* SRAM1: 368kB 0x20020000 - 0x2007BFFF */ /* SRAM2: 16kB 0x2007C000 - 0x2007FFFF */ -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00080000 +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00080000 -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (1024 * 1024) -#define CONFIG_RW_MEM_OFF (1024 * 1024) -#define CONFIG_RW_SIZE (1024 * 1024) +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_SIZE (1024 * 1024) +#define CONFIG_RW_MEM_OFF (1024 * 1024) +#define CONFIG_RW_SIZE (1024 * 1024) -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ - (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ + (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE #undef I2C_PORT_COUNT -#define I2C_PORT_COUNT 4 +#define I2C_PORT_COUNT 4 /* Use PSTATE embedded in the RO image, not in its own erase block */ #define CONFIG_FLASH_PSTATE #undef CONFIG_FLASH_PSTATE_BANK /* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 109 +#define CONFIG_IRQ_COUNT 109 /* DFU Address */ -#define STM32_DFU_BASE 0x1ff00000 +#define STM32_DFU_BASE 0x1ff00000 diff --git a/chip/stm32/config-stm32g41xb.h b/chip/stm32/config-stm32g41xb.h index d6ec8696fb..97e9d21d25 100644 --- a/chip/stm32/config-stm32g41xb.h +++ b/chip/stm32/config-stm32g41xb.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,12 +17,11 @@ * PSTATE in single bank memories with a write size > 4 bytes. */ -#define CONFIG_FLASH_SIZE_BYTES (128 * 1024) +#define CONFIG_FLASH_SIZE_BYTES (128 * 1024) #define CONFIG_FLASH_WRITE_SIZE 0x0004 #define CONFIG_FLASH_BANK_SIZE (2 * 1024) #define CONFIG_FLASH_ERASE_SIZE CONFIG_FLASH_BANK_SIZE - /* Erasing 128K can take up to 2s, need to defer erase. */ #define CONFIG_FLASH_DEFERRED_ERASE @@ -37,11 +36,11 @@ * • 10 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is also aliased * at 0x2000 5800 address to be accessed by all bus controllers. */ -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00008000 +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00008000 #undef I2C_PORT_COUNT -#define I2C_PORT_COUNT 3 +#define I2C_PORT_COUNT 3 /* Number of DMA channels supported (6 channels each for DMA1 and DMA2) */ #define DMAC_COUNT 12 @@ -51,13 +50,13 @@ #undef CONFIG_FLASH_PSTATE_BANK /* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 101 +#define CONFIG_IRQ_COUNT 101 /* USB packet ram config */ -#define CONFIG_USB_RAM_BASE 0x40006000 -#define CONFIG_USB_RAM_SIZE 1024 +#define CONFIG_USB_RAM_BASE 0x40006000 +#define CONFIG_USB_RAM_SIZE 1024 #define CONFIG_USB_RAM_ACCESS_TYPE uint16_t #define CONFIG_USB_RAM_ACCESS_SIZE 2 /* DFU Address */ -#define STM32_DFU_BASE 0x1fff0000 +#define STM32_DFU_BASE 0x1fff0000 diff --git a/chip/stm32/config-stm32g473xc.h b/chip/stm32/config-stm32g473xc.h index 0317b69491..63f4c73ea0 100644 --- a/chip/stm32/config-stm32g473xc.h +++ b/chip/stm32/config-stm32g473xc.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -42,11 +42,11 @@ * • 32 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is also aliased * at 0x2001 8000 address to be accessed by all bus controllers. */ -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00020000 +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00020000 #undef I2C_PORT_COUNT -#define I2C_PORT_COUNT 4 +#define I2C_PORT_COUNT 4 /* Number of DMA channels supported (6 channels each for DMA1 and DMA2) */ #define DMAC_COUNT 12 @@ -56,13 +56,13 @@ #undef CONFIG_FLASH_PSTATE_BANK /* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 101 +#define CONFIG_IRQ_COUNT 101 /* USB packet ram config */ -#define CONFIG_USB_RAM_BASE 0x40006000 -#define CONFIG_USB_RAM_SIZE 1024 +#define CONFIG_USB_RAM_BASE 0x40006000 +#define CONFIG_USB_RAM_SIZE 1024 #define CONFIG_USB_RAM_ACCESS_TYPE uint16_t #define CONFIG_USB_RAM_ACCESS_SIZE 2 /* DFU Address */ -#define STM32_DFU_BASE 0x1fff0000 +#define STM32_DFU_BASE 0x1fff0000 diff --git a/chip/stm32/config-stm32h7x3.h b/chip/stm32/config-stm32h7x3.h index 11da24b849..31f1d3c720 100644 --- a/chip/stm32/config-stm32h7x3.h +++ b/chip/stm32/config-stm32h7x3.h @@ -1,20 +1,20 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES (2048 * 1024) -#define CONFIG_FLASH_ERASE_SIZE (128 * 1024) /* erase bank size */ +#define CONFIG_FLASH_SIZE_BYTES (2048 * 1024) +#define CONFIG_FLASH_ERASE_SIZE (128 * 1024) /* erase bank size */ /* always use 256-bit writes due to ECC */ -#define CONFIG_FLASH_WRITE_SIZE 32 /* minimum write size */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 32 +#define CONFIG_FLASH_WRITE_SIZE 32 /* minimum write size */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 32 /* * What the code is calling 'bank' is really the size of the block used for * write-protected, here it's 128KB sector (same as erase size). */ -#define CONFIG_FLASH_BANK_SIZE (128 * 1024) +#define CONFIG_FLASH_BANK_SIZE (128 * 1024) /* Erasing 128K can take up to 2s, need to defer erase. */ #define CONFIG_FLASH_DEFERRED_ERASE @@ -27,28 +27,28 @@ /* (D2) AHB-SRAM3: 32kB 0x30040000 - 0x30047FFF */ /* (D3) AHB-SRAM4: 64kB 0x38000000 - 0x3800FFFF */ /* (D3) backup RAM: 4kB 0x38800000 - 0x38800FFF */ -#define CONFIG_RAM_BASE 0x24000000 -#define CONFIG_RAM_SIZE 0x00080000 +#define CONFIG_RAM_BASE 0x24000000 +#define CONFIG_RAM_SIZE 0x00080000 -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (128 * 1024) -#define CONFIG_RW_MEM_OFF (CONFIG_FLASH_SIZE_BYTES / 2) -#define CONFIG_RW_SIZE (512 * 1024) +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_SIZE (128 * 1024) +#define CONFIG_RW_MEM_OFF (CONFIG_FLASH_SIZE_BYTES / 2) +#define CONFIG_RW_SIZE (512 * 1024) -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ - (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ + (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE #undef I2C_PORT_COUNT -#define I2C_PORT_COUNT 4 +#define I2C_PORT_COUNT 4 /* * Cannot use PSTATE: @@ -58,7 +58,7 @@ #undef CONFIG_FLASH_PSTATE_BANK /* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 150 +#define CONFIG_IRQ_COUNT 150 /* the Cortex-M7 core has 'standard' ARMv7-M caches */ #define CONFIG_ARMV7M_CACHE @@ -68,9 +68,9 @@ #define CONFIG_CHIP_UNCACHED_REGION ahb4 /* Override MPU attribute settings to match the chip requirements */ /* Code is Normal memory type / non-shareable / write-through */ -#define MPU_ATTR_FLASH_MEMORY 0x02 +#define MPU_ATTR_FLASH_MEMORY 0x02 /* SRAM Data is Normal memory type / non-shareable / write-back, write-alloc */ #define MPU_ATTR_INTERNAL_SRAM 0x0B /* DFU Address */ -#define STM32_DFU_BASE 0x1ff00000 +#define STM32_DFU_BASE 0x1ff00000 diff --git a/chip/stm32/config-stm32l100.h b/chip/stm32/config-stm32l100.h index 2132fab4dd..ec28815525 100644 --- a/chip/stm32/config-stm32l100.h +++ b/chip/stm32/config-stm32l100.h @@ -1,12 +1,12 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Memory mapping */ #define CONFIG_FLASH_SIZE_BYTES 0x00020000 -#define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0100 /* erase bank size */ +#define CONFIG_FLASH_BANK_SIZE 0x1000 +#define CONFIG_FLASH_ERASE_SIZE 0x0100 /* erase bank size */ /* * TODO(crosbug.com/p/23805): Technically we can write in word-mode (4 bytes at @@ -21,8 +21,8 @@ /* Ideal write size in page-mode */ #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080 -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00002800 +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00002800 /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 45 @@ -37,10 +37,10 @@ #define CONFIG_STM32L_FAKE_HIBERNATE /* USB packet ram config */ -#define CONFIG_USB_RAM_BASE 0x40006000 -#define CONFIG_USB_RAM_SIZE 512 +#define CONFIG_USB_RAM_BASE 0x40006000 +#define CONFIG_USB_RAM_SIZE 512 #define CONFIG_USB_RAM_ACCESS_TYPE uint32_t #define CONFIG_USB_RAM_ACCESS_SIZE 4 /* DFU Address */ -#define STM32_DFU_BASE 0x1ff00000 +#define STM32_DFU_BASE 0x1ff00000 diff --git a/chip/stm32/config-stm32l15x.h b/chip/stm32/config-stm32l15x.h index 9f957d8981..ae069ed005 100644 --- a/chip/stm32/config-stm32l15x.h +++ b/chip/stm32/config-stm32l15x.h @@ -1,12 +1,12 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Memory mapping */ #define CONFIG_FLASH_SIZE_BYTES 0x00020000 -#define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0100 /* erase bank size */ +#define CONFIG_FLASH_BANK_SIZE 0x1000 +#define CONFIG_FLASH_ERASE_SIZE 0x0100 /* erase bank size */ /* * TODO(crosbug.com/p/23805): Technically we can write in word-mode (4 bytes at @@ -21,8 +21,8 @@ /* Ideal write size in page-mode */ #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080 -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00004000 +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00004000 /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 45 @@ -38,10 +38,10 @@ #define CONFIG_FLASH_ERASED_VALUE32 0 /* USB packet ram config */ -#define CONFIG_USB_RAM_BASE 0x40006000 -#define CONFIG_USB_RAM_SIZE 512 +#define CONFIG_USB_RAM_BASE 0x40006000 +#define CONFIG_USB_RAM_SIZE 512 #define CONFIG_USB_RAM_ACCESS_TYPE uint32_t #define CONFIG_USB_RAM_ACCESS_SIZE 4 /* DFU Address */ -#define STM32_DFU_BASE 0x1ff00000 +#define STM32_DFU_BASE 0x1ff00000 diff --git a/chip/stm32/config-stm32l431.h b/chip/stm32/config-stm32l431.h index 64d8d39327..de3204945a 100644 --- a/chip/stm32/config-stm32l431.h +++ b/chip/stm32/config-stm32l431.h @@ -1,25 +1,25 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256 kB */ +#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256 kB */ #define CONFIG_FLASH_BANK_SIZE \ 0x800 /* 2 kB. NOTE: BANK in chrome-ec means page */ -#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ -#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */ +#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ +#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */ /* Ideal write size in page-mode */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ /* * SRAM1 (48kB) at 0x20000000 * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000) * so they are contiguous. */ -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */ +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */ /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 82 @@ -45,36 +45,34 @@ * */ - - /* The EC uses one sector to emulate persistent state */ #define CONFIG_FLASH_PSTATE -#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE -#define CONFIG_FW_PSTATE_OFF (62 * CONFIG_FLASH_BANK_SIZE) +#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE +#define CONFIG_FW_PSTATE_OFF (62 * CONFIG_FLASH_BANK_SIZE) -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RO_SIZE (62 * CONFIG_FLASH_BANK_SIZE) -#define CONFIG_RW_MEM_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + \ - CONFIG_FW_PSTATE_SIZE) -#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - CONFIG_RW_MEM_OFF - \ - CONFIG_RW_STORAGE_OFF) +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RO_SIZE (62 * CONFIG_FLASH_BANK_SIZE) +#define CONFIG_RW_MEM_OFF \ + (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + CONFIG_FW_PSTATE_SIZE) +#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RW_SIZE \ + (CONFIG_FLASH_SIZE_BYTES - CONFIG_RW_MEM_OFF - CONFIG_RW_STORAGE_OFF) -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 #define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE (CONFIG_FLASH_SIZE_BYTES - \ - CONFIG_EC_WRITABLE_STORAGE_OFF) +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ + (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE /* We map each write protect sector to a bank */ -#define PHYSICAL_BANKS 128 -#define WP_BANK_COUNT 63 -#define PSTATE_BANK 62 -#define PSTATE_BANK_COUNT 1 +#define PHYSICAL_BANKS 128 +#define WP_BANK_COUNT 63 +#define PSTATE_BANK 62 +#define PSTATE_BANK_COUNT 1 /* DFU Address */ -#define STM32_DFU_BASE 0x1fff0000 +#define STM32_DFU_BASE 0x1fff0000 diff --git a/chip/stm32/config-stm32l442.h b/chip/stm32/config-stm32l442.h index 8a2a284d69..b85e9b1454 100644 --- a/chip/stm32/config-stm32l442.h +++ b/chip/stm32/config-stm32l442.h @@ -1,27 +1,27 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256 kB */ -#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */ -#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ -#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */ +#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256 kB */ +#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */ +#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ +#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */ /* Ideal write size in page-mode */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ /* * SRAM1 (48kB) at 0x20000000 * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000) * so they are contiguous. */ -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */ +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */ /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 82 /* DFU Address */ -#define STM32_DFU_BASE 0x1fff0000 +#define STM32_DFU_BASE 0x1fff0000 diff --git a/chip/stm32/config-stm32l476.h b/chip/stm32/config-stm32l476.h index 7f6fbb0f84..00a02e0ff9 100644 --- a/chip/stm32/config-stm32l476.h +++ b/chip/stm32/config-stm32l476.h @@ -1,23 +1,23 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES 0x00100000 /* 1 MB */ -#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */ -#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ -#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits (without 8 bits ECC) */ +#define CONFIG_FLASH_SIZE_BYTES 0x00100000 /* 1 MB */ +#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */ +#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ +#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits (without 8 bits ECC) */ /* Ideal write size in page-mode */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ -#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_BASE 0x20000000 /* Only using SRAM1. SRAM2 (32 KB) is ignored. */ -#define CONFIG_RAM_SIZE 0x00018000 /* 96 kB */ +#define CONFIG_RAM_SIZE 0x00018000 /* 96 kB */ /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 82 /* DFU Address */ -#define STM32_DFU_BASE 0x1fff0000 +#define STM32_DFU_BASE 0x1fff0000 diff --git a/chip/stm32/config-stm32l552xe.h b/chip/stm32/config-stm32l552xe.h index 1b9c34c4aa..ba11b7f098 100644 --- a/chip/stm32/config-stm32l552xe.h +++ b/chip/stm32/config-stm32l552xe.h @@ -1,39 +1,39 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES 0x00080000 /* 512 kB */ -#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */ -#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ -#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */ +#define CONFIG_FLASH_SIZE_BYTES 0x00080000 /* 512 kB */ +#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */ +#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ +#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */ /* Ideal write size in page-mode */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ /* * SRAM1 (48kB) at 0x20000000 * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000) * so they are contiguous. */ -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */ +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */ /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 109 /* USB packet ram config */ -#define CONFIG_USB_RAM_BASE 0x4000D800 -#define CONFIG_USB_RAM_SIZE 1024 +#define CONFIG_USB_RAM_BASE 0x4000D800 +#define CONFIG_USB_RAM_SIZE 1024 #define CONFIG_USB_RAM_ACCESS_TYPE uint16_t #define CONFIG_USB_RAM_ACCESS_SIZE 2 #undef I2C_PORT_COUNT -#define I2C_PORT_COUNT 4 +#define I2C_PORT_COUNT 4 /* Number of DMA channels supported (8 channels each for DMA1 and DMA2) */ #define DMAC_COUNT 16 /* DFU Address */ -#define STM32_DFU_BASE 0x0bf90000 +#define STM32_DFU_BASE 0x0bf90000 diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h index 4d630909e1..f85eef5c46 100644 --- a/chip/stm32/config_chip.h +++ b/chip/stm32/config_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,19 +10,19 @@ /* CPU core BFD configuration */ #include "core/cortex-m0/config_core.h" /* IRQ priorities */ -#define STM32_IRQ_EXT0_1_PRIORITY 1 -#define STM32_IRQ_EXT2_3_PRIORITY 1 -#define STM32_IRQ_EXTI4_15_PRIORITY 1 +#define STM32_IRQ_EXT0_1_PRIORITY 1 +#define STM32_IRQ_EXT2_3_PRIORITY 1 +#define STM32_IRQ_EXTI4_15_PRIORITY 1 #else /* CPU core BFD configuration */ #include "core/cortex-m/config_core.h" -#define STM32_IRQ_EXTI0_PRIORITY 1 -#define STM32_IRQ_EXTI1_PRIORITY 1 -#define STM32_IRQ_EXTI2_PRIORITY 1 -#define STM32_IRQ_EXTI3_PRIORITY 1 -#define STM32_IRQ_EXTI4_PRIORITY 1 -#define STM32_IRQ_EXTI9_5_PRIORITY 1 -#define STM32_IRQ_EXTI15_10_PRIORITY 1 +#define STM32_IRQ_EXTI0_PRIORITY 1 +#define STM32_IRQ_EXTI1_PRIORITY 1 +#define STM32_IRQ_EXTI2_PRIORITY 1 +#define STM32_IRQ_EXTI3_PRIORITY 1 +#define STM32_IRQ_EXTI4_PRIORITY 1 +#define STM32_IRQ_EXTI9_5_PRIORITY 1 +#define STM32_IRQ_EXTI15_10_PRIORITY 1 #endif /* Default to UART 1 for EC console */ @@ -87,10 +87,8 @@ /* Program is run directly from storage */ #define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE -#if !defined(CHIP_FAMILY_STM32F4) && \ - !defined(CHIP_FAMILY_STM32F7) && \ - !defined(CHIP_FAMILY_STM32H7) && \ - !defined(CHIP_VARIANT_STM32F09X) && \ +#if !defined(CHIP_FAMILY_STM32F4) && !defined(CHIP_FAMILY_STM32F7) && \ + !defined(CHIP_FAMILY_STM32H7) && !defined(CHIP_VARIANT_STM32F09X) && \ !defined(CHIP_VARIANT_STM32L431X) /* Compute the rest of the flash params from these */ #include "config_std_internal_flash.h" @@ -132,7 +130,7 @@ /* Interval between HOOK_TICK notifications */ #define HOOK_TICK_INTERVAL_MS 500 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) +#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) /* * Use a timer to print a watchdog warning event before the actual watchdog @@ -148,7 +146,7 @@ #define CONFIG_RTC /* Number of peripheral request signals per DMA channel */ -#define STM32_DMA_PERIPHERALS_PER_CHANNEL 4 +#define STM32_DMA_PERIPHERALS_PER_CHANNEL 4 /* * Use DMA for UART transmit for all platforms. DMA for UART receive is @@ -165,13 +163,13 @@ /* Chip needs to do custom pre-init */ #define CONFIG_CHIP_PRE_INIT -#define GPIO_NAME_BY_PIN(port, index) #port#index +#define GPIO_NAME_BY_PIN(port, index) #port #index #define GPIO_PIN(port, index) GPIO_##port, BIT(index) #define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m) /* Prescaler values for PLL. Currently used only by STM32L476 and STM32L431. */ -#define STM32_PLLM 1 -#define STM32_PLLN 1 -#define STM32_PLLR 1 +#define STM32_PLLM 1 +#define STM32_PLLN 1 +#define STM32_PLLR 1 #endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/stm32/crc_hw.h b/chip/stm32/crc_hw.h index 2a50d5760e..495af2fb98 100644 --- a/chip/stm32/crc_hw.h +++ b/chip/stm32/crc_hw.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,8 +17,8 @@ static inline void crc32_init(void) /* Delay 1 AHB clock cycle after the clock is enabled */ clock_wait_bus_cycles(BUS_AHB, 1); /* reset CRC state */ - STM32_CRC_CR = STM32_CRC_CR_RESET | STM32_CRC_CR_REV_OUT - | STM32_CRC_CR_REV_IN_WORD; + STM32_CRC_CR = STM32_CRC_CR_RESET | STM32_CRC_CR_REV_OUT | + STM32_CRC_CR_REV_IN_WORD; while (STM32_CRC_CR & 1) ; } diff --git a/chip/stm32/debug_printf.c b/chip/stm32/debug_printf.c index c4e151692c..3713d28d26 100644 --- a/chip/stm32/debug_printf.c +++ b/chip/stm32/debug_printf.c @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -27,8 +27,6 @@ static int debug_txchar(void *context, int c) return 0; } - - void debug_printf(const char *format, ...) { va_list args; @@ -102,8 +100,8 @@ void uart_init(void) STM32_USART_BRR(UARTN_BASE) = DIV_ROUND_NEAREST(CPU_CLOCK, CONFIG_UART_BAUD_RATE); /* UART enabled, 8 Data bits, oversampling x16, no parity */ - STM32_USART_CR1(UARTN_BASE) = - STM32_USART_CR1_UE | STM32_USART_CR1_TE | STM32_USART_CR1_RE; + STM32_USART_CR1(UARTN_BASE) = STM32_USART_CR1_UE | STM32_USART_CR1_TE | + STM32_USART_CR1_RE; /* 1 stop bit, no fancy stuff */ STM32_USART_CR2(UARTN_BASE) = 0x0000; /* DMA disabled, special modes disabled, error interrupt disabled */ diff --git a/chip/stm32/debug_printf.h b/chip/stm32/debug_printf.h index 6091cfc7fc..efd74d40b9 100644 --- a/chip/stm32/debug_printf.h +++ b/chip/stm32/debug_printf.h @@ -1,17 +1,17 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Synchronous UART debug printf */ -#ifndef __CROS_EC_DEBUG_H -#define __CROS_EC_DEBUG_H +#ifndef __CROS_EC_DEBUG_PRINTF_H +#define __CROS_EC_DEBUG_PRINTF_H #ifdef CONFIG_DEBUG_PRINTF -__attribute__((__format__(__printf__, 1, 2))) -void debug_printf(const char *format, ...); +__attribute__((__format__(__printf__, 1, 2))) void +debug_printf(const char *format, ...); #else #define debug_printf(...) #endif -#endif /* __CROS_EC_DEBUG_H */ +#endif /* __CROS_EC_DEBUG_PRINTF_H */ diff --git a/chip/stm32/dfu_bootmanager_main.c b/chip/stm32/dfu_bootmanager_main.c index 462dd08b60..452a7a6443 100644 --- a/chip/stm32/dfu_bootmanager_main.c +++ b/chip/stm32/dfu_bootmanager_main.c @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -93,7 +93,7 @@ static void dfu_bootmanager_init(void) { /* enable clock on Power module */ #ifndef CHIP_FAMILY_STM32H7 -#ifdef CHIP_FAMILY_STM32L4 +#ifdef CHIP_FAMILY_STM32L4 STM32_RCC_APB1ENR1 |= STM32_RCC_PWREN; #else STM32_RCC_APB1ENR |= STM32_RCC_PWREN; @@ -122,8 +122,8 @@ static void jump_to_rw(void) { void (*addr)(void); - addr = (void (*)(void)) (*((uint32_t *) (CONFIG_PROGRAM_MEMORY_BASE + - CONFIG_RW_MEM_OFF + 4))); + addr = (void (*)(void))(*((uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + + CONFIG_RW_MEM_OFF + 4))); addr(); } @@ -132,7 +132,7 @@ static void jump_to_dfu(void) { void (*addr)(void); - addr = (void (*)(void)) (*((uint32_t *) (STM32_DFU_BASE + 4))); + addr = (void (*)(void))(*((uint32_t *)(STM32_DFU_BASE + 4))); /* Clear the scratchpad. */ dfu_bootmanager_backup_write(DFU_BOOTMANAGER_VALUE_CLEAR); @@ -170,10 +170,18 @@ void exception_panic(void) * need to worry about concurrent access. */ -void task_clear_pending_irq(int irq) {} -void interrupt_disable(void) {} -void mutex_lock(mutex_t *mtx) {} -void mutex_unlock(mutex_t *mtx) {} +void task_clear_pending_irq(int irq) +{ +} +void interrupt_disable(void) +{ +} +void mutex_lock(mutex_t *mtx) +{ +} +void mutex_unlock(mutex_t *mtx) +{ +} bool in_interrupt_context(void) { diff --git a/chip/stm32/dfu_bootmanager_shared.c b/chip/stm32/dfu_bootmanager_shared.c index 212ee0a9e9..de8edcff5d 100644 --- a/chip/stm32/dfu_bootmanager_shared.c +++ b/chip/stm32/dfu_bootmanager_shared.c @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/chip/stm32/dfu_bootmanager_shared.h b/chip/stm32/dfu_bootmanager_shared.h index 4003583ee2..df920f16a5 100644 --- a/chip/stm32/dfu_bootmanager_shared.h +++ b/chip/stm32/dfu_bootmanager_shared.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -15,12 +15,12 @@ #include "common.h" /* Registers to validate the backup memory region. */ -#define DFU_BOOTMANAGER_VALUE_MASK 0x00FF -#define DFU_BOOTMANAGER_VALID_MASK 0xFF00 -#define DFU_BOOTMANAGER_VALID_CHECK 0xAA00 +#define DFU_BOOTMANAGER_VALUE_MASK 0x00FF +#define DFU_BOOTMANAGER_VALID_MASK 0xFF00 +#define DFU_BOOTMANAGER_VALID_CHECK 0xAA00 -#define DFU_BOOTMANAGER_VALUE_CLEAR 0 -#define DFU_BOOTMANAGER_VALUE_DFU UINT8_MAX +#define DFU_BOOTMANAGER_VALUE_CLEAR 0 +#define DFU_BOOTMANAGER_VALUE_DFU UINT8_MAX /* * Reset and enter the DFU mode. diff --git a/chip/stm32/dma-stm32f4.c b/chip/stm32/dma-stm32f4.c index 3374cff7fc..3121089437 100644 --- a/chip/stm32/dma-stm32f4.c +++ b/chip/stm32/dma-stm32f4.c @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,15 +14,15 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_DMA, outstr) -#define CPRINTF(format, args...) cprintf(CC_DMA, format, ## args) -#define CPRINTS(format, args...) cprints(CC_DMA, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_DMA, format, ##args) +#define CPRINTS(format, args...) cprints(CC_DMA, format, ##args) stm32_dma_regs_t *STM32_DMA_REGS[] = { STM32_DMA1_REGS, STM32_DMA2_REGS }; /* Callback data to use when IRQ fires */ static struct { - void (*cb)(void *); /* Callback function to call */ - void *cb_data; /* Callback data for callback function */ + void (*cb)(void *); /* Callback function to call */ + void *cb_data; /* Callback data for callback function */ } dma_irq[STM32_DMAS_TOTAL_COUNT]; /** @@ -91,7 +91,7 @@ void dma_disable_all(void) * @param flags DMA flags for the control register. */ static void prepare_stream(enum dma_channel stream, unsigned count, - void *periph, void *memory, unsigned flags) + void *periph, void *memory, unsigned flags) { stm32_dma_stream_t *dma_stream = dma_get_channel(stream); uint32_t ccr = STM32_DMA_CCR_PL_VERY_HIGH; @@ -128,18 +128,17 @@ void dma_prepare_tx(const struct dma_option *option, unsigned count, * we're preparing the stream for transmit. */ prepare_stream(option->channel, count, option->periph, (void *)memory, - STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_M2P | - option->flags); + STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_M2P | + option->flags); } -void dma_start_rx(const struct dma_option *option, unsigned count, - void *memory) +void dma_start_rx(const struct dma_option *option, unsigned count, void *memory) { stm32_dma_stream_t *stream = dma_get_channel(option->channel); prepare_stream(option->channel, count, option->periph, memory, - STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_P2M | - option->flags); + STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_P2M | + option->flags); dma_go(stream); } @@ -176,10 +175,8 @@ void dma_dump(enum dma_channel stream) CPRINTF("scr=%x, sndtr=%x, spar=%x, sm0ar=%x, sfcr=%x\n", dma_stream->scr, dma_stream->sndtr, dma_stream->spar, dma_stream->sm0ar, dma_stream->sfcr); - CPRINTF("stream %d, isr=%x, ifcr=%x\n", - stream, - STM32_DMA_GET_ISR(stream), - STM32_DMA_GET_IFCR(stream)); + CPRINTF("stream %d, isr=%x, ifcr=%x\n", stream, + STM32_DMA_GET_ISR(stream), STM32_DMA_GET_IFCR(stream)); } void dma_check(enum dma_channel stream, char *buf) @@ -218,7 +215,7 @@ void dma_test(enum dma_channel stream) dma_stream->spar = (uint32_t)periph; dma_stream->sm0ar = (uint32_t)memory; dma_stream->sndtr = count; - dma_stream->sfcr &= ~STM32_DMA_SFCR_DMDIS; + dma_stream->sfcr &= ~STM32_DMA_SFCR_DMDIS; ctrl = STM32_DMA_CCR_PL_MEDIUM; dma_stream->scr = ctrl; @@ -300,17 +297,17 @@ void dma_clear_isr(enum dma_channel stream) } #ifdef CONFIG_DMA_DEFAULT_HANDLERS -#define STM32_DMA_IDX(dma, x) CONCAT4(STM32_DMA, dma, _STREAM, x) -#define STM32_DMA_FCT(dma, x) CONCAT4(dma_, dma, _event_interrupt_stream_, x) -#define DECLARE_DMA_IRQ(dma, x) \ - static void STM32_DMA_FCT(dma, x)(void) \ - { \ - dma_clear_isr(STM32_DMA_IDX(dma, x)); \ - if (dma_irq[STM32_DMA_IDX(dma, x)].cb != NULL) \ - (*dma_irq[STM32_DMA_IDX(dma, x)].cb) \ - (dma_irq[STM32_DMA_IDX(dma, x)].cb_data); \ - } \ - DECLARE_IRQ(CONCAT4(STM32_IRQ_DMA, dma, _STREAM, x), \ +#define STM32_DMA_IDX(dma, x) CONCAT4(STM32_DMA, dma, _STREAM, x) +#define STM32_DMA_FCT(dma, x) CONCAT4(dma_, dma, _event_interrupt_stream_, x) +#define DECLARE_DMA_IRQ(dma, x) \ + static void STM32_DMA_FCT(dma, x)(void) \ + { \ + dma_clear_isr(STM32_DMA_IDX(dma, x)); \ + if (dma_irq[STM32_DMA_IDX(dma, x)].cb != NULL) \ + (*dma_irq[STM32_DMA_IDX(dma, x)].cb)( \ + dma_irq[STM32_DMA_IDX(dma, x)].cb_data); \ + } \ + DECLARE_IRQ(CONCAT4(STM32_IRQ_DMA, dma, _STREAM, x), \ STM32_DMA_FCT(dma, x), 1); DECLARE_DMA_IRQ(1, 0); diff --git a/chip/stm32/dma.c b/chip/stm32/dma.c index ae5a83789d..fbf0d59627 100644 --- a/chip/stm32/dma.c +++ b/chip/stm32/dma.c @@ -1,8 +1,9 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ +#include "builtin/assert.h" #include "clock.h" #include "common.h" #include "console.h" @@ -15,15 +16,14 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_DMA, outstr) -#define CPRINTF(format, args...) cprintf(CC_DMA, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_DMA, format, ##args) /* Callback data to use when IRQ fires */ static struct { - void (*cb)(void *); /* Callback function to call */ - void *cb_data; /* Callback data for callback function */ + void (*cb)(void *); /* Callback function to call */ + void *cb_data; /* Callback data for callback function */ } dma_irq[STM32_DMAC_COUNT]; - /** * Return the IRQ for the DMA channel * @@ -36,9 +36,8 @@ static int dma_get_irq(enum dma_channel channel) if (channel == STM32_DMAC_CH1) return STM32_IRQ_DMA_CHANNEL_1; - return channel > STM32_DMAC_CH3 ? - STM32_IRQ_DMA_CHANNEL_4_7 : - STM32_IRQ_DMA_CHANNEL_2_3; + return channel > STM32_DMAC_CH3 ? STM32_IRQ_DMA_CHANNEL_4_7 : + STM32_IRQ_DMA_CHANNEL_2_3; #elif defined(CHIP_FAMILY_STM32L4) if (channel < STM32_DMAC_PER_CTLR) return STM32_IRQ_DMA_CHANNEL_1 + channel; @@ -55,7 +54,7 @@ static int dma_get_irq(enum dma_channel channel) return STM32_IRQ_DMA_CHANNEL_1 + channel; else return STM32_IRQ_DMA2_CHANNEL1 + - (channel - STM32_DMAC_PER_CTLR); + (channel - STM32_DMAC_PER_CTLR); #endif } @@ -127,7 +126,7 @@ void dma_disable_all(void) * 0 for rx */ static void prepare_channel(enum dma_channel channel, unsigned int count, - void *periph, void *memory, unsigned int flags) + void *periph, void *memory, unsigned int flags) { stm32_dma_chan_t *chan = dma_get_channel(channel); uint32_t ccr = STM32_DMA_CCR_PL_VERY_HIGH; @@ -161,8 +160,7 @@ void dma_prepare_tx(const struct dma_option *option, unsigned int count, * we're preparing the channel for transmit. */ prepare_channel(option->channel, count, option->periph, (void *)memory, - STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR | - option->flags); + STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR | option->flags); } void dma_start_rx(const struct dma_option *option, unsigned int count, @@ -191,10 +189,9 @@ void dma_dump(enum dma_channel channel) stm32_dma_regs_t *dma = STM32_DMA_REGS(channel); stm32_dma_chan_t *chan = dma_get_channel(channel); - CPRINTF("ccr=%x, cndtr=%x, cpar=%x, cmar=%x\n", chan->ccr, - chan->cndtr, chan->cpar, chan->cmar); - CPRINTF("chan %d, isr=%x, ifcr=%x\n", - channel, + CPRINTF("ccr=%x, cndtr=%x, cpar=%x, cmar=%x\n", chan->ccr, chan->cndtr, + chan->cpar, chan->cmar); + CPRINTF("chan %d, isr=%x, ifcr=%x\n", channel, (dma->isr >> ((channel % STM32_DMAC_PER_CTLR) * 4)) & 0xf, (dma->ifcr >> ((channel % STM32_DMAC_PER_CTLR) * 4)) & 0xf); } @@ -238,11 +235,12 @@ void dma_test(enum dma_channel channel) ctrl = STM32_DMA_CCR_PL_MEDIUM; chan->ccr = ctrl; - ctrl |= STM32_DMA_CCR_MINC; /* | STM32_DMA_CCR_DIR */; + ctrl |= STM32_DMA_CCR_MINC; /* | STM32_DMA_CCR_DIR */ + ; ctrl |= STM32_DMA_CCR_MEM2MEM; ctrl |= STM32_DMA_CCR_PINC; -/* ctrl |= STM32_DMA_CCR_MSIZE_32_BIT; */ -/* ctrl |= STM32_DMA_CCR_PSIZE_32_BIT; */ + /* ctrl |= STM32_DMA_CCR_MSIZE_32_BIT; */ + /* ctrl |= STM32_DMA_CCR_PSIZE_32_BIT; */ chan->ccr = ctrl; chan->ccr = ctrl | STM32_DMA_CCR_EN; @@ -254,11 +252,13 @@ void dma_test(enum dma_channel channel) void dma_init(void) { -#if defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5) - STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN|STM32_RCC_AHB1ENR_DMA2EN; -#elif defined(CHIP_FAMILY_STM32G4) - STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN|STM32_RCC_AHB1ENR_DMA2EN | - STM32_RCC_AHB1ENR_DMAMUXEN; +#if defined(CHIP_FAMILY_STM32L4) + STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN | + STM32_RCC_AHB1ENR_DMA2EN; +#elif defined(CHIP_FAMILY_STM32G4) || defined(CHIP_FAMILY_STM32L5) + STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN | + STM32_RCC_AHB1ENR_DMA2EN | + STM32_RCC_AHB1ENR_DMAMUXEN; #else STM32_RCC_AHBENR |= STM32_RCC_HB_DMA1; #endif @@ -337,8 +337,8 @@ static void dma_event_interrupt_channel_1(void) if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(STM32_DMAC_CH1)) { dma_clear_isr(STM32_DMAC_CH1); if (dma_irq[STM32_DMAC_CH1].cb != NULL) - (*dma_irq[STM32_DMAC_CH1].cb) - (dma_irq[STM32_DMAC_CH1].cb_data); + (*dma_irq[STM32_DMAC_CH1].cb)( + dma_irq[STM32_DMAC_CH1].cb_data); } } DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_1, dma_event_interrupt_channel_1, 1); @@ -360,9 +360,7 @@ DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_2_3, dma_event_interrupt_channel_2_3, 1); static void dma_event_interrupt_channel_4_7(void) { int i; - const unsigned int max_chan = MIN(STM32_DMAC_CH7, STM32_DMAC_COUNT); - - for (i = STM32_DMAC_CH4; i <= max_chan; i++) { + for (i = STM32_DMAC_CH4; i < STM32_DMAC_COUNT; i++) { if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(i)) { dma_clear_isr(i); if (dma_irq[i].cb != NULL) @@ -374,15 +372,15 @@ DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_4_7, dma_event_interrupt_channel_4_7, 1); #else /* !CHIP_FAMILY_STM32F0 */ -#define DECLARE_DMA_IRQ(x) \ - static void CONCAT2(dma_event_interrupt_channel_, x)(void) \ - { \ - dma_clear_isr(CONCAT2(STM32_DMAC_CH, x)); \ - if (dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb != NULL) \ - (*dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb) \ - (dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb_data); \ - } \ - DECLARE_IRQ(CONCAT2(STM32_IRQ_DMA_CHANNEL_, x), \ +#define DECLARE_DMA_IRQ(x) \ + static void CONCAT2(dma_event_interrupt_channel_, x)(void) \ + { \ + dma_clear_isr(CONCAT2(STM32_DMAC_CH, x)); \ + if (dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb != NULL) \ + (*dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb)( \ + dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb_data); \ + } \ + DECLARE_IRQ(CONCAT2(STM32_IRQ_DMA_CHANNEL_, x), \ CONCAT2(dma_event_interrupt_channel_, x), 1) DECLARE_DMA_IRQ(1); @@ -396,7 +394,7 @@ DECLARE_DMA_IRQ(7); DECLARE_DMA_IRQ(9); DECLARE_DMA_IRQ(10); #endif -#ifdef CHIP_FAMILY_STM32L4 +#if defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5) DECLARE_DMA_IRQ(9); DECLARE_DMA_IRQ(10); DECLARE_DMA_IRQ(11); diff --git a/chip/stm32/flash-f.c b/chip/stm32/flash-f.c index 9e35a2c689..9bfdb1b6b7 100644 --- a/chip/stm32/flash-f.c +++ b/chip/stm32/flash-f.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -7,6 +7,7 @@ #include <stdbool.h> #include "battery.h" +#include "builtin/assert.h" #include "console.h" #include "clock.h" #include "flash.h" @@ -20,8 +21,8 @@ #include "util.h" #include "watchdog.h" -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) /* * Approximate number of CPU cycles per iteration of the loop when polling @@ -49,14 +50,15 @@ /* Forward declarations */ #if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE) -static enum flash_rdp_level flash_physical_get_rdp_level(void); + static enum flash_rdp_level + flash_physical_get_rdp_level(void); static int flash_physical_set_rdp_level(enum flash_rdp_level level); #endif /* CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE */ static inline int calculate_flash_timeout(void) { - return (FLASH_WRITE_TIMEOUT_US * - (clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP); + return (FLASH_WRITE_TIMEOUT_US * (clock_get_freq() / SECOND) / + CYCLE_PER_FLASH_LOOP); } static int wait_busy(void) @@ -67,7 +69,6 @@ static int wait_busy(void) return (timeout > 0) ? EC_SUCCESS : EC_ERROR_TIMEOUT; } - void unlock_flash_control_register(void) { STM32_FLASH_KEYR = FLASH_KEYR_KEY1; @@ -134,7 +135,7 @@ bool flash_control_register_locked(void) * We at least unlock the control register lock. * We may also unlock other locks. */ -enum extra_lock_type { +enum extra_lock_type { NO_EXTRA_LOCK = 0, OPT_LOCK = 1, }; @@ -382,9 +383,7 @@ int crec_flash_physical_write(int offset, int size, const char *data) watchdog_reload(); /* wait to be ready */ - for (i = 0; - (STM32_FLASH_SR & FLASH_SR_BUSY) && - (i < timeout); + for (i = 0; (STM32_FLASH_SR & FLASH_SR_BUSY) && (i < timeout); i++) ; @@ -392,9 +391,7 @@ int crec_flash_physical_write(int offset, int size, const char *data) *address++ = quantum; /* Wait for writes to complete */ - for (i = 0; - (STM32_FLASH_SR & FLASH_SR_BUSY) && - (i < timeout); + for (i = 0; (STM32_FLASH_SR & FLASH_SR_BUSY) && (i < timeout); i++) ; @@ -429,7 +426,7 @@ int crec_flash_physical_erase(int offset, int size) int sector = crec_flash_bank_index(offset); /* we take advantage of sector_size == erase_size */ if ((sector < 0) || (crec_flash_bank_index(offset + size) < 0)) - return EC_ERROR_INVAL; /* Invalid range */ + return EC_ERROR_INVAL; /* Invalid range */ #endif if (unlock(NO_EXTRA_LOCK) != EC_SUCCESS) @@ -459,7 +456,7 @@ int crec_flash_physical_erase(int offset, int size) #ifdef CHIP_FAMILY_STM32F4 /* select page to erase */ STM32_FLASH_CR = (STM32_FLASH_CR & ~STM32_FLASH_CR_SNB_MASK) | - (sector << STM32_FLASH_CR_SNB_OFFSET); + (sector << STM32_FLASH_CR_SNB_OFFSET); #else /* select page to erase */ STM32_FLASH_AR = CONFIG_PROGRAM_MEMORY_BASE + offset; @@ -472,7 +469,7 @@ int crec_flash_physical_erase(int offset, int size) watchdog_reload(); while ((STM32_FLASH_SR & FLASH_SR_BUSY) && (get_time().val < deadline.val)) { - usleep(timeout_us/100); + usleep(timeout_us / 100); } if (STM32_FLASH_SR & FLASH_SR_BUSY) { res = EC_ERROR_TIMEOUT; @@ -487,7 +484,7 @@ int crec_flash_physical_erase(int offset, int size) res = EC_ERROR_UNKNOWN; goto exit_er; } -next_sector: + next_sector: size -= sector_size; offset += sector_size; #ifdef CHIP_FAMILY_STM32F4 @@ -540,8 +537,7 @@ int crec_flash_physical_protect_at_boot(uint32_t new_flags) original_val = val = STM32_OPTB_WP & STM32_OPTB_nWRP_ALL; - for (block = WP_BANK_OFFSET; - block < WP_BANK_OFFSET + PHYSICAL_BANKS; + for (block = WP_BANK_OFFSET; block < WP_BANK_OFFSET + PHYSICAL_BANKS; block++) { int protect = new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT; @@ -573,10 +569,10 @@ static void unprotect_all_blocks(void) write_optb(STM32_FLASH_nWRP_ALL, STM32_FLASH_nWRP_ALL); } -#else /* CHIP_FAMILY_STM32F4 */ +#else /* CHIP_FAMILY_STM32F4 */ static int flash_physical_get_protect_at_boot(int block) { - uint8_t val = read_optb(STM32_OPTB_WRP_OFF(block/8)); + uint8_t val = read_optb(STM32_OPTB_WRP_OFF(block / 8)); return (!(val & (1 << (block % 8)))) ? 1 : 0; } @@ -589,11 +585,10 @@ int crec_flash_physical_protect_at_boot(uint32_t new_flags) for (i = 0; i < 4; ++i) original_val[i] = val[i] = read_optb(i * 2 + 8); - for (block = WP_BANK_OFFSET; - block < WP_BANK_OFFSET + PHYSICAL_BANKS; + for (block = WP_BANK_OFFSET; block < WP_BANK_OFFSET + PHYSICAL_BANKS; block++) { int protect = new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT; - int byte_off = STM32_OPTB_WRP_OFF(block/8) / 2 - 4; + int byte_off = STM32_OPTB_WRP_OFF(block / 8) / 2 - 4; if (block >= WP_BANK_OFFSET && block < WP_BANK_OFFSET + WP_BANK_COUNT) @@ -601,7 +596,8 @@ int crec_flash_physical_protect_at_boot(uint32_t new_flags) #ifdef CONFIG_ROLLBACK else if (block >= ROLLBACK_BANK_OFFSET && block < ROLLBACK_BANK_OFFSET + ROLLBACK_BANK_COUNT) - protect |= new_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT; + protect |= new_flags & + EC_FLASH_PROTECT_ROLLBACK_AT_BOOT; #endif #ifdef CONFIG_FLASH_PROTECT_RW else @@ -729,13 +725,12 @@ int crec_flash_pre_init(void) uint32_t prot_flags = crec_flash_get_protect(); int need_reset = 0; - #ifdef CHIP_FAMILY_STM32F4 unlock(NO_EXTRA_LOCK); /* Set the proper write size */ STM32_FLASH_CR = (STM32_FLASH_CR & ~STM32_FLASH_CR_PSIZE_MASK) | - (31 - __builtin_clz(CONFIG_FLASH_WRITE_SIZE)) << - STM32_FLASH_CR_PSIZE_OFFSET; + (31 - __builtin_clz(CONFIG_FLASH_WRITE_SIZE)) + << STM32_FLASH_CR_PSIZE_OFFSET; lock(); #endif if (crec_flash_physical_restore_state()) @@ -776,8 +771,8 @@ int crec_flash_pre_init(void) * to the check above. One of them should be able to * go away. */ - crec_flash_protect_at_boot( - prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT); + crec_flash_protect_at_boot(prot_flags & + EC_FLASH_PROTECT_RO_AT_BOOT); need_reset = 1; } } else { @@ -792,7 +787,7 @@ int crec_flash_pre_init(void) } if ((crec_flash_physical_get_valid_flags() & - EC_FLASH_PROTECT_ALL_AT_BOOT) && + EC_FLASH_PROTECT_ALL_AT_BOOT) && (!!(prot_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) != !!(prot_flags & EC_FLASH_PROTECT_ALL_NOW))) { /* @@ -808,7 +803,7 @@ int crec_flash_pre_init(void) #ifdef CONFIG_FLASH_PROTECT_RW if ((crec_flash_physical_get_valid_flags() & - EC_FLASH_PROTECT_RW_AT_BOOT) && + EC_FLASH_PROTECT_RW_AT_BOOT) && (!!(prot_flags & EC_FLASH_PROTECT_RW_AT_BOOT) != !!(prot_flags & EC_FLASH_PROTECT_RW_NOW))) { /* RW_AT_BOOT and RW_NOW do not match. */ @@ -818,7 +813,7 @@ int crec_flash_pre_init(void) #ifdef CONFIG_ROLLBACK if ((crec_flash_physical_get_valid_flags() & - EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) && + EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) && (!!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) != !!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_NOW))) { /* ROLLBACK_AT_BOOT and ROLLBACK_NOW do not match. */ diff --git a/chip/stm32/flash-f.h b/chip/stm32/flash-f.h index cbbe6ec86f..507ded32f1 100644 --- a/chip/stm32/flash-f.h +++ b/chip/stm32/flash-f.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,16 +9,16 @@ #include <stdbool.h> enum flash_rdp_level { - FLASH_RDP_LEVEL_INVALID = -1, /**< Error occurred. */ - FLASH_RDP_LEVEL_0, /**< No read protection. */ - FLASH_RDP_LEVEL_1, /**< Reading flash is disabled while in - * bootloader mode or JTAG attached. - * Changing to Level 0 from this level - * triggers mass erase. - */ - FLASH_RDP_LEVEL_2, /**< Same as Level 1, but is permanent - * and can never be disabled. - */ + FLASH_RDP_LEVEL_INVALID = -1, /**< Error occurred. */ + FLASH_RDP_LEVEL_0, /**< No read protection. */ + FLASH_RDP_LEVEL_1, /**< Reading flash is disabled while in + * bootloader mode or JTAG attached. + * Changing to Level 0 from this level + * triggers mass erase. + */ + FLASH_RDP_LEVEL_2, /**< Same as Level 1, but is permanent + * and can never be disabled. + */ }; bool is_flash_rdp_enabled(void); diff --git a/chip/stm32/flash-regs.h b/chip/stm32/flash-regs.h index b0a46667a1..9456c03963 100644 --- a/chip/stm32/flash-regs.h +++ b/chip/stm32/flash-regs.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/stm32/flash-stm32f0.c b/chip/stm32/flash-stm32f0.c index f790a657c8..058a8afc46 100644 --- a/chip/stm32/flash-stm32f0.c +++ b/chip/stm32/flash-stm32f0.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -65,8 +65,7 @@ uint32_t crec_flash_physical_get_protect_flags(void) /* Default: RW. */ int region = FLASH_REGION_RW; - if (i >= WP_BANK_OFFSET && - i < WP_BANK_OFFSET + WP_BANK_COUNT) + if (i >= WP_BANK_OFFSET && i < WP_BANK_OFFSET + WP_BANK_COUNT) region = FLASH_REGION_RO; #ifdef CONFIG_ROLLBACK if (i >= ROLLBACK_BANK_OFFSET && @@ -95,11 +94,11 @@ uint32_t crec_flash_physical_get_protect_flags(void) for (i = 0; i < FLASH_REGION_COUNT; i++) { if (!(wrp01 & wrp_mask[i][0]) && - (wrp01 & wrp_mask[i][0] << 8) == (wrp_mask[i][0] << 8)) + (wrp01 & wrp_mask[i][0] << 8) == (wrp_mask[i][0] << 8)) #if CONFIG_FLASH_SIZE_BYTES > 64 * 1024 if (!(wrp23 & wrp_mask[i][1]) && - (wrp23 & wrp_mask[i][1] << 8) == - (wrp_mask[i][1] << 8)) + (wrp23 & wrp_mask[i][1] << 8) == + (wrp_mask[i][1] << 8)) #endif flags |= mask_flags[i]; } @@ -127,18 +126,15 @@ int crec_flash_physical_restore_state(void) uint32_t crec_flash_physical_get_valid_flags(void) { - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | + return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW | #ifdef CONFIG_FLASH_PROTECT_RW - EC_FLASH_PROTECT_RW_AT_BOOT | - EC_FLASH_PROTECT_RW_NOW | + EC_FLASH_PROTECT_RW_AT_BOOT | EC_FLASH_PROTECT_RW_NOW | #endif #ifdef CONFIG_ROLLBACK EC_FLASH_PROTECT_ROLLBACK_AT_BOOT | EC_FLASH_PROTECT_ROLLBACK_NOW | #endif - EC_FLASH_PROTECT_ALL_AT_BOOT | - EC_FLASH_PROTECT_ALL_NOW; + EC_FLASH_PROTECT_ALL_AT_BOOT | EC_FLASH_PROTECT_ALL_NOW; } uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags) @@ -153,13 +149,13 @@ uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags) * ALL/RW at-boot state can be set if WP GPIO is asserted and can always * be cleared. */ - if (cur_flags & (EC_FLASH_PROTECT_ALL_AT_BOOT | - EC_FLASH_PROTECT_GPIO_ASSERTED)) + if (cur_flags & + (EC_FLASH_PROTECT_ALL_AT_BOOT | EC_FLASH_PROTECT_GPIO_ASSERTED)) ret |= EC_FLASH_PROTECT_ALL_AT_BOOT; #ifdef CONFIG_FLASH_PROTECT_RW - if (cur_flags & (EC_FLASH_PROTECT_RW_AT_BOOT | - EC_FLASH_PROTECT_GPIO_ASSERTED)) + if (cur_flags & + (EC_FLASH_PROTECT_RW_AT_BOOT | EC_FLASH_PROTECT_GPIO_ASSERTED)) ret |= EC_FLASH_PROTECT_RW_AT_BOOT; #endif diff --git a/chip/stm32/flash-stm32f3.c b/chip/stm32/flash-stm32f3.c index 138e690fcc..8705e4d657 100644 --- a/chip/stm32/flash-stm32f3.c +++ b/chip/stm32/flash-stm32f3.c @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -102,7 +102,7 @@ int crec_flash_physical_get_protect(int block) #elif defined(CHIP_FAMILY_STM32F4) !(STM32_OPTB_WP & STM32_OPTB_nWRP(block)) #endif - ); + ); } uint32_t crec_flash_physical_get_protect_flags(void) @@ -137,8 +137,7 @@ int crec_flash_physical_protect_now(int all) uint32_t crec_flash_physical_get_valid_flags(void) { - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | + return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW | EC_FLASH_PROTECT_ALL_NOW; } @@ -173,7 +172,7 @@ int crec_flash_physical_restore_state(void) */ if (reset_flags & EC_RESET_FLAG_SYSJUMP) { prev = (const struct flash_wp_state *)system_get_jump_tag( - FLASH_SYSJUMP_TAG, &version, &size); + FLASH_SYSJUMP_TAG, &version, &size); if (prev && version == FLASH_HOOK_VERSION && size == sizeof(*prev)) entire_flash_locked = prev->entire_flash_locked; diff --git a/chip/stm32/flash-stm32f4.c b/chip/stm32/flash-stm32f4.c index 6ff8130e17..8705e4d657 120000..100644 --- a/chip/stm32/flash-stm32f4.c +++ b/chip/stm32/flash-stm32f4.c @@ -1 +1,197 @@ -flash-stm32f3.c
\ No newline at end of file +/* Copyright 2017 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Flash memory module for stm32f3 and stm32f4 */ + +#include <stdbool.h> +#include "common.h" +#include "flash.h" +#include "flash-f.h" +#include "flash-regs.h" +#include "hooks.h" +#include "registers.h" +#include "system.h" +#include "panic.h" + +/*****************************************************************************/ +/* Physical layer APIs */ +#ifdef CHIP_VARIANT_STM32F76X +/* + * 8 "erase" sectors : 32KB/32KB/32KB/32KB/128KB/256KB/256KB/256KB + */ +struct ec_flash_bank const flash_bank_array[] = { + { + .count = 4, + .size_exp = __fls(SIZE_32KB), + .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), + .erase_size_exp = __fls(SIZE_32KB), + .protect_size_exp = __fls(SIZE_32KB), + }, + { + .count = 1, + .size_exp = __fls(SIZE_128KB), + .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), + .erase_size_exp = __fls(SIZE_128KB), + .protect_size_exp = __fls(SIZE_128KB), + }, + { + .count = (CONFIG_FLASH_SIZE_BYTES - SIZE_256KB) / SIZE_256KB, + .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), + .size_exp = __fls(SIZE_256KB), + .erase_size_exp = __fls(SIZE_256KB), + .protect_size_exp = __fls(SIZE_256KB), + }, +}; +#elif defined(CHIP_FAMILY_STM32F4) +/* + * STM32F412xE has 512 KB flash + * 8 "erase" sectors (512 KB) : 16KB/16KB/16KB/16KB/64KB/128KB/128KB/128KB + * + * STM32F412xG has 1 MB flash + * 12 "erase" sectors (1024 KB) : + * 16KB/16KB/16KB/16KB/64KB/128KB/128KB/128KB/128KB/128KB/128KB/128KB + * + * https://www.st.com/resource/en/datasheet/stm32f412cg.pdf + */ +struct ec_flash_bank const flash_bank_array[] = { + { + .count = 4, + .size_exp = __fls(SIZE_16KB), + .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), + .erase_size_exp = __fls(SIZE_16KB), + .protect_size_exp = __fls(SIZE_16KB), + }, + { + .count = 1, + .size_exp = __fls(SIZE_64KB), + .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), + .erase_size_exp = __fls(SIZE_64KB), + .protect_size_exp = __fls(SIZE_64KB), + }, + { + .count = (CONFIG_FLASH_SIZE_BYTES - SIZE_128KB) / SIZE_128KB, + .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), + .size_exp = __fls(SIZE_128KB), + .erase_size_exp = __fls(SIZE_128KB), + .protect_size_exp = __fls(SIZE_128KB), + }, +}; +#endif + +/* Flag indicating whether we have locked down entire flash */ +static int entire_flash_locked; + +#define FLASH_SYSJUMP_TAG 0x5750 /* "WP" - Write Protect */ +#define FLASH_HOOK_VERSION 1 + +/* The previous write protect state before sys jump */ +struct flash_wp_state { + int entire_flash_locked; +}; + +/*****************************************************************************/ +/* Physical layer APIs */ + +int crec_flash_physical_get_protect(int block) +{ + return (entire_flash_locked || +#if defined(CHIP_FAMILY_STM32F3) + !(STM32_FLASH_WRPR & BIT(block)) +#elif defined(CHIP_FAMILY_STM32F4) + !(STM32_OPTB_WP & STM32_OPTB_nWRP(block)) +#endif + ); +} + +uint32_t crec_flash_physical_get_protect_flags(void) +{ + uint32_t flags = 0; + + /* Read all-protected state from our shadow copy */ + if (entire_flash_locked) + flags |= EC_FLASH_PROTECT_ALL_NOW; + +#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE) + if (is_flash_rdp_enabled()) + flags |= EC_FLASH_PROTECT_RO_AT_BOOT; +#endif + + return flags; +} + +int crec_flash_physical_protect_now(int all) +{ + if (all) { + disable_flash_control_register(); + entire_flash_locked = 1; + + return EC_SUCCESS; + } + + disable_flash_option_bytes(); + + return EC_SUCCESS; +} + +uint32_t crec_flash_physical_get_valid_flags(void) +{ + return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW | + EC_FLASH_PROTECT_ALL_NOW; +} + +uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags) +{ + uint32_t ret = 0; + + /* If RO protection isn't enabled, its at-boot state can be changed. */ + if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW)) + ret |= EC_FLASH_PROTECT_RO_AT_BOOT; + + /* + * If entire flash isn't protected at this boot, it can be enabled if + * the WP GPIO is asserted. + */ + if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) && + (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED)) + ret |= EC_FLASH_PROTECT_ALL_NOW; + + return ret; +} + +int crec_flash_physical_restore_state(void) +{ + uint32_t reset_flags = system_get_reset_flags(); + int version, size; + const struct flash_wp_state *prev; + + /* + * If we have already jumped between images, an earlier image could + * have applied write protection. Nothing additional needs to be done. + */ + if (reset_flags & EC_RESET_FLAG_SYSJUMP) { + prev = (const struct flash_wp_state *)system_get_jump_tag( + FLASH_SYSJUMP_TAG, &version, &size); + if (prev && version == FLASH_HOOK_VERSION && + size == sizeof(*prev)) + entire_flash_locked = prev->entire_flash_locked; + return 1; + } + + return 0; +} + +/*****************************************************************************/ +/* Hooks */ + +static void flash_preserve_state(void) +{ + struct flash_wp_state state; + + state.entire_flash_locked = entire_flash_locked; + + system_add_jump_tag(FLASH_SYSJUMP_TAG, FLASH_HOOK_VERSION, + sizeof(state), &state); +} +DECLARE_HOOK(HOOK_SYSJUMP, flash_preserve_state, HOOK_PRIO_DEFAULT); diff --git a/chip/stm32/flash-stm32g4-l4.c b/chip/stm32/flash-stm32g4-l4.c index f792da6e3c..31dba5c887 100644 --- a/chip/stm32/flash-stm32g4-l4.c +++ b/chip/stm32/flash-stm32g4-l4.c @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -37,31 +37,31 @@ #define FLASH_PAGE_SIZE CONFIG_FLASH_BANK_SIZE #define FLASH_PAGE_MAX_COUNT (CONFIG_FLASH_SIZE_BYTES / FLASH_PAGE_SIZE) #define FLASH_RO_FIRST_PAGE_IDX WP_BANK_OFFSET -#define FLASH_RO_LAST_PAGE_IDX ((CONFIG_WP_STORAGE_SIZE / FLASH_PAGE_SIZE) \ - + FLASH_RO_FIRST_PAGE_IDX - 1) +#define FLASH_RO_LAST_PAGE_IDX \ + ((CONFIG_WP_STORAGE_SIZE / FLASH_PAGE_SIZE) + \ + FLASH_RO_FIRST_PAGE_IDX - 1) #define FLASH_RW_FIRST_PAGE_IDX (FLASH_RO_LAST_PAGE_IDX + 1) #define FLASH_RW_LAST_PAGE_IDX (FLASH_PAGE_MAX_COUNT - 1) - #define FLASH_PAGE_ROLLBACK_COUNT ROLLBACK_BANK_COUNT #define FLASH_PAGE_ROLLBACK_FIRST_IDX ROLLBACK_BANK_OFFSET -#define FLASH_PAGE_ROLLBACK_LAST_IDX (FLASH_PAGE_ROLLBACK_FIRST_IDX +\ - FLASH_PAGE_ROLLBACK_COUNT -1) +#define FLASH_PAGE_ROLLBACK_LAST_IDX \ + (FLASH_PAGE_ROLLBACK_FIRST_IDX + FLASH_PAGE_ROLLBACK_COUNT - 1) #ifdef STM32_FLASH_DBANK_MODE -#define FLASH_WRP_MASK (FLASH_PAGE_MAX_COUNT - 1) +#define FLASH_WRP_MASK (FLASH_PAGE_MAX_COUNT - 1) #else #ifdef CHIP_FAMILY_STM32L4 -#define FLASH_WRP_MASK 0xFF +#define FLASH_WRP_MASK 0xFF #else -#define FLASH_WRP_MASK ((FLASH_PAGE_MAX_COUNT) / 2 - 1) +#define FLASH_WRP_MASK ((FLASH_PAGE_MAX_COUNT) / 2 - 1) #endif #endif /* CONFIG_FLASH_DBANK_MODE */ -#define FLASH_WRP_START(val) ((val) & FLASH_WRP_MASK) -#define FLASH_WRP_END(val) (((val) >> 16) & FLASH_WRP_MASK) -#define FLASH_WRP_RANGE(start, end) (((start) & FLASH_WRP_MASK) | \ - (((end) & FLASH_WRP_MASK) << 16)) -#define FLASH_WRP_RANGE_DISABLED FLASH_WRP_RANGE(FLASH_WRP_MASK, 0x00) +#define FLASH_WRP_START(val) ((val)&FLASH_WRP_MASK) +#define FLASH_WRP_END(val) (((val) >> 16) & FLASH_WRP_MASK) +#define FLASH_WRP_RANGE(start, end) \ + (((start)&FLASH_WRP_MASK) | (((end)&FLASH_WRP_MASK) << 16)) +#define FLASH_WRP_RANGE_DISABLED FLASH_WRP_RANGE(FLASH_WRP_MASK, 0x00) #define FLASH_WRP1X_MASK FLASH_WRP_RANGE(FLASH_WRP_MASK, FLASH_WRP_MASK) enum wrp_region { @@ -77,8 +77,8 @@ struct wrp_info { static inline int calculate_flash_timeout(void) { - return (FLASH_TIMEOUT_US * - (clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP); + return (FLASH_TIMEOUT_US * (clock_get_freq() / SECOND) / + CYCLE_PER_FLASH_LOOP); } static int wait_while_busy(void) @@ -104,8 +104,7 @@ static int unlock(int locks) STM32_FLASH_KEYR = FLASH_KEYR_KEY2; } /* unlock option memory if required */ - if ((locks & FLASH_CR_OPTLOCK) && - (STM32_FLASH_CR & FLASH_CR_OPTLOCK)) { + if ((locks & FLASH_CR_OPTLOCK) && (STM32_FLASH_CR & FLASH_CR_OPTLOCK)) { STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1; STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2; } @@ -113,8 +112,8 @@ static int unlock(int locks) /* Re-enable bus fault handler */ ignore_bus_fault(0); - return (STM32_FLASH_CR & (locks | FLASH_CR_LOCK)) ? EC_ERROR_UNKNOWN - : EC_SUCCESS; + return (STM32_FLASH_CR & (locks | FLASH_CR_LOCK)) ? EC_ERROR_UNKNOWN : + EC_SUCCESS; } static void lock(void) @@ -299,10 +298,10 @@ static void optb_set_wrp(enum wrp_region region, struct wrp_info *wrp) * value. Otherwise, can use end passed in directly. */ if (start <= FLASH_WRP_MASK) { - rw_end = end > FLASH_WRP_MASK ? - FLASH_WRP_MASK : end; - STM32_FLASH_WRP1BR = FLASH_WRP_RANGE(start, - rw_end); + rw_end = end > FLASH_WRP_MASK ? FLASH_WRP_MASK : + end; + STM32_FLASH_WRP1BR = + FLASH_WRP_RANGE(start, rw_end); } /* * If the last RW flash page is in the 2nd half of @@ -366,8 +365,8 @@ int crec_flash_physical_protect_at_boot(uint32_t new_flags) * write protection in the option bytes. Based on new_flags either RO or * RW or both regions write protect may be set. */ - if (new_flags & (EC_FLASH_PROTECT_ALL_AT_BOOT | - EC_FLASH_PROTECT_RO_AT_BOOT)) { + if (new_flags & + (EC_FLASH_PROTECT_ALL_AT_BOOT | EC_FLASH_PROTECT_RO_AT_BOOT)) { wrp_ro.start = FLASH_RO_FIRST_PAGE_IDX; wrp_ro.end = FLASH_RO_LAST_PAGE_IDX; wrp_ro.enable = 1; @@ -434,9 +433,9 @@ static int registers_need_reset(void) /* The RO region is write-protected by the WRP1AR range. */ uint32_t wrp1ar = STM32_OPTB_WRP1AR; uint32_t ro_range = ro_at_boot ? - FLASH_WRP_RANGE(FLASH_RO_FIRST_PAGE_IDX, - FLASH_RO_LAST_PAGE_IDX) - : FLASH_WRP_RANGE_DISABLED; + FLASH_WRP_RANGE(FLASH_RO_FIRST_PAGE_IDX, + FLASH_RO_LAST_PAGE_IDX) : + FLASH_WRP_RANGE_DISABLED; return ro_range != (wrp1ar & FLASH_WRP1X_MASK); } @@ -484,10 +483,10 @@ int crec_flash_physical_write(int offset, int size, const char *data) /* write the 2 words */ if (unaligned) { - *address++ = (uint32_t)data[0] | (data[1] << 8) - | (data[2] << 16) | (data[3] << 24); - *address++ = (uint32_t)data[4] | (data[5] << 8) - | (data[6] << 16) | (data[7] << 24); + *address++ = (uint32_t)data[0] | (data[1] << 8) | + (data[2] << 16) | (data[3] << 24); + *address++ = (uint32_t)data[4] | (data[5] << 8) | + (data[6] << 16) | (data[7] << 24); data += STM32_FLASH_MIN_WRITE_SIZE; } else { *address++ = *data32++; @@ -540,8 +539,8 @@ int crec_flash_physical_erase(int offset, int size) timestamp_t deadline; /* select page to erase and PER bit */ - STM32_FLASH_CR = (STM32_FLASH_CR & ~FLASH_CR_PNB_MASK) - | FLASH_CR_PER | FLASH_CR_PNB(pg); + STM32_FLASH_CR = (STM32_FLASH_CR & ~FLASH_CR_PNB_MASK) | + FLASH_CR_PER | FLASH_CR_PNB(pg); /* set STRT bit : start erase */ STM32_FLASH_CR |= FLASH_CR_STRT; @@ -591,7 +590,7 @@ int crec_flash_physical_get_protect(int block) optb_get_wrp(WRP_RW, &wrp_rw); return ((block >= wrp_ro.start) && (block <= wrp_ro.end)) || - ((block >= wrp_rw.start) && (block <= wrp_rw.end)); + ((block >= wrp_rw.start) && (block <= wrp_rw.end)); } /* @@ -613,7 +612,6 @@ uint32_t crec_flash_physical_get_protect_flags(void) flags |= EC_FLASH_PROTECT_RO_AT_BOOT; if (wrp_rw.enable) { - #ifdef CONFIG_ROLLBACK if (wrp_rw.start <= FLASH_PAGE_ROLLBACK_FIRST_IDX && wrp_rw.end >= FLASH_PAGE_ROLLBACK_LAST_IDX) @@ -639,18 +637,15 @@ int crec_flash_physical_protect_now(int all) uint32_t crec_flash_physical_get_valid_flags(void) { - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | + return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW | #ifdef CONFIG_FLASH_PROTECT_RW - EC_FLASH_PROTECT_RW_AT_BOOT | - EC_FLASH_PROTECT_RW_NOW | + EC_FLASH_PROTECT_RW_AT_BOOT | EC_FLASH_PROTECT_RW_NOW | #endif #ifdef CONFIG_ROLLBACK EC_FLASH_PROTECT_ROLLBACK_AT_BOOT | EC_FLASH_PROTECT_ROLLBACK_NOW | #endif - EC_FLASH_PROTECT_ALL_AT_BOOT | - EC_FLASH_PROTECT_ALL_NOW; + EC_FLASH_PROTECT_ALL_AT_BOOT | EC_FLASH_PROTECT_ALL_NOW; } uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags) @@ -665,13 +660,13 @@ uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags) * ALL/RW at-boot state can be set if WP GPIO is asserted and can always * be cleared. */ - if (cur_flags & (EC_FLASH_PROTECT_ALL_AT_BOOT | - EC_FLASH_PROTECT_GPIO_ASSERTED)) + if (cur_flags & + (EC_FLASH_PROTECT_ALL_AT_BOOT | EC_FLASH_PROTECT_GPIO_ASSERTED)) ret |= EC_FLASH_PROTECT_ALL_AT_BOOT; #ifdef CONFIG_FLASH_PROTECT_RW - if (cur_flags & (EC_FLASH_PROTECT_RW_AT_BOOT | - EC_FLASH_PROTECT_GPIO_ASSERTED)) + if (cur_flags & + (EC_FLASH_PROTECT_RW_AT_BOOT | EC_FLASH_PROTECT_GPIO_ASSERTED)) ret |= EC_FLASH_PROTECT_RW_AT_BOOT; #endif @@ -735,8 +730,8 @@ int crec_flash_pre_init(void) * to the check above. One of them should be able to * go away. */ - crec_flash_protect_at_boot( - prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT); + crec_flash_protect_at_boot(prot_flags & + EC_FLASH_PROTECT_RO_AT_BOOT); need_reset = 1; } } else { @@ -751,7 +746,7 @@ int crec_flash_pre_init(void) } if ((crec_flash_physical_get_valid_flags() & - EC_FLASH_PROTECT_ALL_AT_BOOT) && + EC_FLASH_PROTECT_ALL_AT_BOOT) && (!!(prot_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) != !!(prot_flags & EC_FLASH_PROTECT_ALL_NOW))) { /* @@ -767,7 +762,7 @@ int crec_flash_pre_init(void) #ifdef CONFIG_FLASH_PROTECT_RW if ((crec_flash_physical_get_valid_flags() & - EC_FLASH_PROTECT_RW_AT_BOOT) && + EC_FLASH_PROTECT_RW_AT_BOOT) && (!!(prot_flags & EC_FLASH_PROTECT_RW_AT_BOOT) != !!(prot_flags & EC_FLASH_PROTECT_RW_NOW))) { /* RW_AT_BOOT and RW_NOW do not match. */ diff --git a/chip/stm32/flash-stm32h7.c b/chip/stm32/flash-stm32h7.c index 087ddbf062..445b354e57 100644 --- a/chip/stm32/flash-stm32h7.c +++ b/chip/stm32/flash-stm32h7.c @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -45,7 +45,7 @@ * not what is called 'bank' in the common code (ie Write-Protect sectors) * both have the same number of 128KB blocks. */ -#define HWBANK_SIZE (CONFIG_FLASH_SIZE_BYTES / 2) +#define HWBANK_SIZE (CONFIG_FLASH_SIZE_BYTES / 2) #define BLOCKS_PER_HWBANK (HWBANK_SIZE / CONFIG_FLASH_ERASE_SIZE) #define BLOCKS_HWBANK_MASK (BIT(BLOCKS_PER_HWBANK) - 1) @@ -74,8 +74,8 @@ struct flash_wp_state { static inline int calculate_flash_timeout(void) { - return (FLASH_TIMEOUT_US * - (clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP); + return (FLASH_TIMEOUT_US * (clock_get_freq() / SECOND) / + CYCLE_PER_FLASH_LOOP); } static int unlock(int bank) @@ -94,8 +94,8 @@ static int unlock(int bank) ignore_bus_fault(0); } - return (STM32_FLASH_CR(bank) & FLASH_CR_LOCK) ? EC_ERROR_UNKNOWN - : EC_SUCCESS; + return (STM32_FLASH_CR(bank) & FLASH_CR_LOCK) ? EC_ERROR_UNKNOWN : + EC_SUCCESS; } static void lock(int bank) @@ -123,15 +123,14 @@ static int unlock_optb(void) ignore_bus_fault(0); } - return flash_option_bytes_locked() ? EC_ERROR_UNKNOWN - : EC_SUCCESS; + return flash_option_bytes_locked() ? EC_ERROR_UNKNOWN : EC_SUCCESS; } static int commit_optb(void) { /* might use this before timer_init, cannot use get_time/usleep */ - int timeout = (FLASH_OPT_PRG_TIMEOUT_US * - (clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP); + int timeout = (FLASH_OPT_PRG_TIMEOUT_US * (clock_get_freq() / SECOND) / + CYCLE_PER_FLASH_LOOP); STM32_FLASH_OPTCR(0) |= FLASH_OPTCR_OPTSTART; @@ -149,12 +148,11 @@ static void protect_blocks(uint32_t blocks) if (unlock_optb()) return; STM32_FLASH_WPSN_PRG(0) &= ~(blocks & BLOCKS_HWBANK_MASK); - STM32_FLASH_WPSN_PRG(1) &= ~((blocks >> BLOCKS_PER_HWBANK) - & BLOCKS_HWBANK_MASK); + STM32_FLASH_WPSN_PRG(1) &= + ~((blocks >> BLOCKS_PER_HWBANK) & BLOCKS_HWBANK_MASK); commit_optb(); } - /* * Helper function definitions for consistency with F4 to enable flash * physical unitesting @@ -226,7 +224,7 @@ bool flash_option_bytes_locked(void) * Always use bank 0 flash controller as there is only one option bytes * set for both banks. See http://b/181130245 */ - return !!(STM32_FLASH_OPTCR(0) & FLASH_OPTCR_OPTLOCK); + return !!(STM32_FLASH_OPTCR(0) & FLASH_OPTCR_OPTLOCK); } bool flash_control_register_locked(void) @@ -252,8 +250,8 @@ bool flash_control_register_locked(void) static int is_wp_enabled(void) { #ifdef CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE - return (STM32_FLASH_OPTSR_CUR(0) & FLASH_OPTSR_RDP_MASK) - != FLASH_OPTSR_RDP_LEVEL_0; + return (STM32_FLASH_OPTSR_CUR(0) & FLASH_OPTSR_RDP_MASK) != + FLASH_OPTSR_RDP_LEVEL_0; #else return !!(STM32_FLASH_OPTSR_CUR(0) & FLASH_OPTSR_RSS1); #endif @@ -311,8 +309,8 @@ int crec_flash_physical_write(int offset, int size, const char *data) STM32_FLASH_CCR(bank) = FLASH_CCR_ERR_MASK; /* select write parallelism */ - STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) & ~FLASH_CR_PSIZE_MASK) - | DEFAULT_PSIZE; + STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) & ~FLASH_CR_PSIZE_MASK) | + DEFAULT_PSIZE; /* set PG bit */ STM32_FLASH_CR(bank) |= FLASH_CR_PG; @@ -326,18 +324,21 @@ int crec_flash_physical_write(int offset, int size, const char *data) /* write a 256-bit flash word */ if (unaligned) { - for (i = 0; i < CONFIG_FLASH_WRITE_SIZE / 4; i++, - data += 4) - *address++ = (uint32_t)data[0] | (data[1] << 8) - | (data[2] << 16) | (data[3] << 24); + for (i = 0; i < CONFIG_FLASH_WRITE_SIZE / 4; + i++, data += 4) + *address++ = (uint32_t)data[0] | + (data[1] << 8) | (data[2] << 16) | + (data[3] << 24); } else { for (i = 0; i < CONFIG_FLASH_WRITE_SIZE / 4; i++) *address++ = *data32++; } /* Wait for writes to complete */ - for (i = 0; (STM32_FLASH_SR(bank) & - (FLASH_SR_WBNE | FLASH_SR_QW)) && (i < timeout); i++) + for (i = 0; + (STM32_FLASH_SR(bank) & (FLASH_SR_WBNE | FLASH_SR_QW)) && + (i < timeout); + i++) ; if (STM32_FLASH_SR(bank) & (FLASH_SR_WBNE | FLASH_SR_QW)) { @@ -386,16 +387,16 @@ int crec_flash_physical_erase(int offset, int size) STM32_FLASH_CCR(bank) = FLASH_CCR_ERR_MASK; /* select erase parallelism */ - STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) & ~FLASH_CR_PSIZE_MASK) - | DEFAULT_PSIZE; + STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) & ~FLASH_CR_PSIZE_MASK) | + DEFAULT_PSIZE; for (sect = offset / CONFIG_FLASH_ERASE_SIZE; sect < last; sect++) { timestamp_t deadline; /* select page to erase and PER bit */ - STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) - & ~FLASH_CR_SNB_MASK) - | FLASH_CR_SER | FLASH_CR_SNB(sect); + STM32_FLASH_CR(bank) = + (STM32_FLASH_CR(bank) & ~FLASH_CR_SNB_MASK) | + FLASH_CR_SER | FLASH_CR_SNB(sect); /* set STRT bit : start erase */ STM32_FLASH_CR(bank) |= FLASH_CR_STRT; @@ -516,8 +517,7 @@ int crec_flash_physical_protect_at_boot(uint32_t new_flags) uint32_t crec_flash_physical_get_valid_flags(void) { - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | + return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW | EC_FLASH_PROTECT_ALL_NOW; } @@ -549,11 +549,11 @@ int crec_flash_physical_restore_state(void) /* * If we have already jumped between images, an earlier image could * have applied write protection. We simply need to represent these - * irreversible flags to other components. + * irreversible flags to other components. */ if (reset_flags & EC_RESET_FLAG_SYSJUMP) { prev = (const struct flash_wp_state *)system_get_jump_tag( - FLASH_SYSJUMP_TAG, &version, &size); + FLASH_SYSJUMP_TAG, &version, &size); if (prev && version == FLASH_HOOK_VERSION && size == sizeof(*prev)) { access_disabled = prev->access_disabled; @@ -571,7 +571,7 @@ int crec_flash_pre_init(void) uint32_t reset_flags = system_get_reset_flags(); uint32_t prot_flags = crec_flash_get_protect(); uint32_t unwanted_prot_flags = EC_FLASH_PROTECT_ALL_NOW | - EC_FLASH_PROTECT_ERROR_INCONSISTENT; + EC_FLASH_PROTECT_ERROR_INCONSISTENT; if (crec_flash_physical_restore_state()) return EC_SUCCESS; diff --git a/chip/stm32/flash-stm32l.c b/chip/stm32/flash-stm32l.c index f34200219a..b83f8961af 100644 --- a/chip/stm32/flash-stm32l.c +++ b/chip/stm32/flash-stm32l.c @@ -1,13 +1,15 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Flash memory module for Chrome EC */ +#include "builtin/assert.h" #include "clock.h" #include "console.h" #include "flash.h" +#include "panic.h" #include "registers.h" #include "system.h" #include "task.h" @@ -34,7 +36,8 @@ static void lock(void) ignore_bus_fault(1); STM32_FLASH_PECR = STM32_FLASH_PECR_PE_LOCK | - STM32_FLASH_PECR_PRG_LOCK | STM32_FLASH_PECR_OPT_LOCK; + STM32_FLASH_PECR_PRG_LOCK | + STM32_FLASH_PECR_OPT_LOCK; ignore_bus_fault(0); } @@ -105,8 +108,8 @@ static uint16_t read_optb(int offset) */ static void write_optb(int offset, uint16_t value) { - REG32(STM32_OPTB_BASE + offset) = - (uint32_t)value | ((uint32_t)(~value) << 16); + REG32(STM32_OPTB_BASE + offset) = (uint32_t)value | + ((uint32_t)(~value) << 16); } /** @@ -115,7 +118,7 @@ static void write_optb(int offset, uint16_t value) static uint32_t read_optb_wrp(void) { return read_optb(STM32_OPTB_WRP1L) | - ((uint32_t)read_optb(STM32_OPTB_WRP1H) << 16); + ((uint32_t)read_optb(STM32_OPTB_WRP1H) << 16); } /** @@ -133,8 +136,8 @@ static void write_optb_wrp(uint32_t value) * This function lives in internal RAM, as we cannot read flash during writing. * You must not call other functions from this one or declare it static. */ -void __attribute__((section(".iram.text"))) - iram_flash_write(uint32_t *addr, uint32_t *data) +void __attribute__((section(".iram.text"))) +iram_flash_write(uint32_t *addr, uint32_t *data) { int i; @@ -189,7 +192,7 @@ int crec_flash_physical_write(int offset, int size, const char *data) /* Update flash timeout based on current clock speed */ flash_timeout_loop = FLASH_TIMEOUT_MS * (clock_get_freq() / MSEC) / - CYCLE_PER_FLASH_LOOP; + CYCLE_PER_FLASH_LOOP; while (size > 0) { /* @@ -204,7 +207,8 @@ int crec_flash_physical_write(int offset, int size, const char *data) /* Wait for writes to complete */ for (i = 0; ((STM32_FLASH_SR & 9) != 8) && - (i < flash_timeout_loop); i++) + (i < flash_timeout_loop); + i++) ; size -= sizeof(uint32_t); @@ -257,13 +261,13 @@ int crec_flash_physical_erase(int offset, int size) for (address = (uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset); size > 0; size -= CONFIG_FLASH_ERASE_SIZE, - address += CONFIG_FLASH_ERASE_SIZE / sizeof(uint32_t)) { + address += CONFIG_FLASH_ERASE_SIZE / sizeof(uint32_t)) { timestamp_t deadline; /* Do nothing if already erased */ if (crec_flash_is_erased((uint32_t)address - - CONFIG_PROGRAM_MEMORY_BASE, - CONFIG_FLASH_ERASE_SIZE)) + CONFIG_PROGRAM_MEMORY_BASE, + CONFIG_FLASH_ERASE_SIZE)) continue; /* Start erase */ @@ -336,7 +340,7 @@ int crec_flash_physical_protect_at_boot(uint32_t new_flags) prot &= ~mask; if (prot == read_optb_wrp()) - return EC_SUCCESS; /* No bits changed */ + return EC_SUCCESS; /* No bits changed */ /* Unlock option bytes */ rv = unlock(STM32_FLASH_PECR_OPT_LOCK); @@ -402,8 +406,7 @@ int crec_flash_physical_protect_now(int all) uint32_t crec_flash_physical_get_valid_flags(void) { - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | + return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW | EC_FLASH_PROTECT_ALL_NOW; } @@ -458,7 +461,7 @@ int crec_flash_pre_init(void) * Set it back to a good state and reboot. */ crec_flash_protect_at_boot(prot_flags & - EC_FLASH_PROTECT_RO_AT_BOOT); + EC_FLASH_PROTECT_RO_AT_BOOT); need_reset = 1; } } else if (prot_flags & (EC_FLASH_PROTECT_RO_NOW | diff --git a/chip/stm32/fpu.c b/chip/stm32/fpu.c index b61d0354f7..2bf0a0b803 100644 --- a/chip/stm32/fpu.c +++ b/chip/stm32/fpu.c @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -38,5 +38,6 @@ __attribute__((naked)) void IRQ_HANDLER(STM32_IRQ_FPU)(void) "pop {r0, pc}\n"); } const struct irq_priority __keep IRQ_PRIORITY(STM32_IRQ_FPU) - __attribute__((section(".rodata.irqprio"))) - = {STM32_IRQ_FPU, 0}; /* highest priority */ + __attribute__((section(".rodata.irqprio"))) = { STM32_IRQ_FPU, + 0 }; /* highest priority + */ diff --git a/chip/stm32/gpio-f0-l.c b/chip/stm32/gpio-f0-l.c index 55628cb6d4..87ba4baa9f 100644 --- a/chip/stm32/gpio-f0-l.c +++ b/chip/stm32/gpio-f0-l.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,6 +9,7 @@ * These functions are shared by the STM32F0 and STM32L variants. */ +#include "builtin/assert.h" #include "common.h" #include "gpio_chip.h" #include "registers.h" @@ -62,7 +63,6 @@ int gpio_get_flags_by_mask(uint32_t port, uint32_t mask) flags |= GPIO_LOW; } - if (STM32_EXTI_RTSR & mask) flags |= GPIO_INT_F_RISING; if (STM32_EXTI_RTSR & mask) @@ -80,9 +80,9 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) /* Set up pullup / pulldown */ val = STM32_GPIO_PUPDR(port) & ~mask2; if (flags & GPIO_PULL_UP) - val |= 0x55555555 & mask2; /* Pull Up = 01 */ + val |= 0x55555555 & mask2; /* Pull Up = 01 */ else if (flags & GPIO_PULL_DOWN) - val |= 0xaaaaaaaa & mask2; /* Pull Down = 10 */ + val |= 0xaaaaaaaa & mask2; /* Pull Down = 10 */ STM32_GPIO_PUPDR(port) = val; /* @@ -133,10 +133,10 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) } void gpio_set_alternate_function(uint32_t port, uint32_t mask, - enum gpio_alternate_func func) + enum gpio_alternate_func func) { /* Ensure that the func parameter isn't overflowed */ - BUILD_ASSERT((int) MODULE_COUNT <= (int) GPIO_ALT_FUNC_MAX); + BUILD_ASSERT((int)MODULE_COUNT <= (int)GPIO_ALT_FUNC_MAX); int bit; uint32_t half; diff --git a/chip/stm32/gpio-stm32f0.c b/chip/stm32/gpio-stm32f0.c index d7e7aa4391..8fbc77a85c 100644 --- a/chip/stm32/gpio-stm32f0.c +++ b/chip/stm32/gpio-stm32f0.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/stm32/gpio-stm32f3.c b/chip/stm32/gpio-stm32f3.c index f3a1b0068b..113aadc1e6 100644 --- a/chip/stm32/gpio-stm32f3.c +++ b/chip/stm32/gpio-stm32f3.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/stm32/gpio-stm32f4.c b/chip/stm32/gpio-stm32f4.c index 1ccdadd472..8e8658b7f9 100644 --- a/chip/stm32/gpio-stm32f4.c +++ b/chip/stm32/gpio-stm32f4.c @@ -1,10 +1,11 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* GPIO module for Chrome EC */ +#include "builtin/assert.h" #include "clock.h" #include "common.h" #include "gpio.h" @@ -17,12 +18,12 @@ int gpio_required_clocks(void) { const int gpio_ports_used = (0 -# define GPIO(name, pin, flags) pin -# define GPIO_INT(name, pin, flags, signal) pin -# define ALTERNATE(pinmask, function, module, flagz) pinmask -# define PIN(port, index) | STM32_RCC_AHB1ENR_GPIO_PORT ## port -# define PIN_MASK(port, mask) PIN(port, 0) -# include "gpio.wrap" +#define GPIO(name, pin, flags) pin +#define GPIO_INT(name, pin, flags, signal) pin +#define ALTERNATE(pinmask, function, module, flagz) pinmask +#define PIN(port, index) | STM32_RCC_AHB1ENR_GPIO_PORT##port +#define PIN_MASK(port, mask) PIN(port, 0) +#include "gpio.wrap" ); /* diff --git a/chip/stm32/gpio-stm32g4.c b/chip/stm32/gpio-stm32g4.c index e77adc0ba6..8d1529a7ad 100644 --- a/chip/stm32/gpio-stm32g4.c +++ b/chip/stm32/gpio-stm32g4.c @@ -1,10 +1,11 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* GPIO module for Chrome EC */ +#include "builtin/assert.h" #include "clock.h" #include "common.h" #include "gpio.h" @@ -17,12 +18,12 @@ int gpio_required_clocks(void) { const int gpio_ports_used = (0 -# define GPIO(name, pin, flags) pin -# define GPIO_INT(name, pin, flags, signal) pin -# define ALTERNATE(pinmask, function, module, flagz) pinmask -# define PIN(port, index) | STM32_RCC_AHB2ENR_GPIO_PORT ## port -# define PIN_MASK(port, mask) PIN(port, 0) -# include "gpio.wrap" +#define GPIO(name, pin, flags) pin +#define GPIO_INT(name, pin, flags, signal) pin +#define ALTERNATE(pinmask, function, module, flagz) pinmask +#define PIN(port, index) | STM32_RCC_AHB2ENR_GPIO_PORT##port +#define PIN_MASK(port, mask) PIN(port, 0) +#include "gpio.wrap" ); /* diff --git a/chip/stm32/gpio-stm32h7.c b/chip/stm32/gpio-stm32h7.c index 2cb723f076..66c696e836 100644 --- a/chip/stm32/gpio-stm32h7.c +++ b/chip/stm32/gpio-stm32h7.c @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -33,7 +33,6 @@ static void gpio_init(void) task_enable_irq(STM32_IRQ_EXTI4); task_enable_irq(STM32_IRQ_EXTI9_5); task_enable_irq(STM32_IRQ_EXTI15_10); - } DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); diff --git a/chip/stm32/gpio-stm32l.c b/chip/stm32/gpio-stm32l.c index 607a1a391f..920cb382b0 100644 --- a/chip/stm32/gpio-stm32l.c +++ b/chip/stm32/gpio-stm32l.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/stm32/gpio-stm32l4.c b/chip/stm32/gpio-stm32l4.c index f4ec6f4412..1ef83a188a 100644 --- a/chip/stm32/gpio-stm32l4.c +++ b/chip/stm32/gpio-stm32l4.c @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -38,7 +38,6 @@ static void gpio_init(void) task_enable_irq(STM32_IRQ_EXTI4); task_enable_irq(STM32_IRQ_EXTI9_5); task_enable_irq(STM32_IRQ_EXTI15_10); - } DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); diff --git a/chip/stm32/gpio-stm32l5.c b/chip/stm32/gpio-stm32l5.c index 9943edd55b..e714164650 100644 --- a/chip/stm32/gpio-stm32l5.c +++ b/chip/stm32/gpio-stm32l5.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -45,7 +45,6 @@ static void gpio_init(void) task_enable_irq(STM32_IRQ_EXTI13); task_enable_irq(STM32_IRQ_EXTI14); task_enable_irq(STM32_IRQ_EXTI15); - } DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); diff --git a/chip/stm32/gpio.c b/chip/stm32/gpio.c index 20d9223351..2ad9f99d79 100644 --- a/chip/stm32/gpio.c +++ b/chip/stm32/gpio.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -16,7 +16,7 @@ #include "util.h" /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) +#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args) /* For each EXTI bit, record which GPIO entry is using it */ static uint8_t exti_events[16]; @@ -83,8 +83,8 @@ test_mockable int gpio_get_level(enum gpio_signal signal) void gpio_set_level(enum gpio_signal signal, int value) { - STM32_GPIO_BSRR(gpio_list[signal].port) = - gpio_list[signal].mask << (value ? 0 : 16); + STM32_GPIO_BSRR(gpio_list[signal].port) = gpio_list[signal].mask + << (value ? 0 : 16); } int gpio_enable_interrupt(enum gpio_signal signal) @@ -103,8 +103,8 @@ int gpio_enable_interrupt(enum gpio_signal signal) g_old += exti_events[bit]; if ((exti_events[bit]) && (exti_events[bit] != signal)) { - CPRINTS("Overriding %s with %s on EXTI%d", - g_old->name, g->name, bit); + CPRINTS("Overriding %s with %s on EXTI%d", g_old->name, g->name, + bit); } exti_events[bit] = signal; @@ -112,8 +112,9 @@ int gpio_enable_interrupt(enum gpio_signal signal) shift = (bit % 4) * 4; bank = (g->port - STM32_GPIOA_BASE) / 0x400; - STM32_SYSCFG_EXTICR(group) = (STM32_SYSCFG_EXTICR(group) & - ~(0xF << shift)) | (bank << shift); + STM32_SYSCFG_EXTICR(group) = + (STM32_SYSCFG_EXTICR(group) & ~(0xF << shift)) | + (bank << shift); STM32_EXTI_IMR |= g->mask; return EC_SUCCESS; diff --git a/chip/stm32/gpio_chip.h b/chip/stm32/gpio_chip.h index b440cf5041..0a52fe9191 100644 --- a/chip/stm32/gpio_chip.h +++ b/chip/stm32/gpio_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -20,4 +20,4 @@ void gpio_enable_clocks(void); int gpio_required_clocks(void); void __keep gpio_interrupt(void); -#endif /* __CROS_EC_CHIP_STM32_GPIO_CHIP_H */ +#endif /* __CROS_EC_CHIP_STM32_GPIO_CHIP_H */ diff --git a/chip/stm32/host_command_common.c b/chip/stm32/host_command_common.c index b39a298c64..10653a0711 100644 --- a/chip/stm32/host_command_common.c +++ b/chip/stm32/host_command_common.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,8 +17,8 @@ static enum fp_transport_type curr_transport_type = FP_TRANSPORT_TYPE_UNKNOWN; /* * Get protocol information */ -static enum ec_status host_command_protocol_info(struct host_cmd_handler_args - *args) +static enum ec_status +host_command_protocol_info(struct host_cmd_handler_args *args) { enum ec_status ret_status = EC_RES_INVALID_COMMAND; @@ -39,8 +39,7 @@ static enum ec_status host_command_protocol_info(struct host_cmd_handler_args return ret_status; } -DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, - host_command_protocol_info, +DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, host_command_protocol_info, EC_VER_MASK(0)); #endif /* CONFIG_I2C_PERIPHERAL */ diff --git a/chip/stm32/hwtimer.c b/chip/stm32/hwtimer.c index 8748b7f870..3521347f3f 100644 --- a/chip/stm32/hwtimer.c +++ b/chip/stm32/hwtimer.c @@ -1,10 +1,11 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Hardware timers driver */ +#include "builtin/assert.h" #include "clock.h" #include "clock-f.h" #include "common.h" @@ -33,20 +34,20 @@ * -------------------- * ts = 0 1 2 3 */ -#define STM32_TIM_TS_SECONDARY_1_PRIMARY_15 0 -#define STM32_TIM_TS_SECONDARY_1_PRIMARY_2 1 -#define STM32_TIM_TS_SECONDARY_1_PRIMARY_3 2 -#define STM32_TIM_TS_SECONDARY_1_PRIMARY_17 3 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_1 0 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_15 1 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_3 2 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_14 3 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_1 0 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_2 1 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_15 2 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_14 3 -#define STM32_TIM_TS_SECONDARY_15_PRIMARY_2 0 -#define STM32_TIM_TS_SECONDARY_15_PRIMARY_3 1 +#define STM32_TIM_TS_SECONDARY_1_PRIMARY_15 0 +#define STM32_TIM_TS_SECONDARY_1_PRIMARY_2 1 +#define STM32_TIM_TS_SECONDARY_1_PRIMARY_3 2 +#define STM32_TIM_TS_SECONDARY_1_PRIMARY_17 3 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_1 0 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_15 1 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_3 2 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_14 3 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_1 0 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_2 1 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_15 2 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_14 3 +#define STM32_TIM_TS_SECONDARY_15_PRIMARY_2 0 +#define STM32_TIM_TS_SECONDARY_15_PRIMARY_3 1 #define STM32_TIM_TS_SECONDARY_15_PRIMARY_16 2 #define STM32_TIM_TS_SECONDARY_15_PRIMARY_17 3 #elif defined(CHIP_FAMILY_STM32F3) @@ -61,28 +62,28 @@ * --------------------- * ts = 0 1 2 3 */ -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_19 0 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_15 1 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_3 2 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_14 3 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_19 0 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_2 1 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_5 2 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_14 3 -#define STM32_TIM_TS_SECONDARY_4_PRIMARY_19 0 -#define STM32_TIM_TS_SECONDARY_4_PRIMARY_2 1 -#define STM32_TIM_TS_SECONDARY_4_PRIMARY_3 2 -#define STM32_TIM_TS_SECONDARY_4_PRIMARY_15 3 -#define STM32_TIM_TS_SECONDARY_5_PRIMARY_2 0 -#define STM32_TIM_TS_SECONDARY_5_PRIMARY_3 1 -#define STM32_TIM_TS_SECONDARY_5_PRIMARY_4 2 -#define STM32_TIM_TS_SECONDARY_5_PRIMARY_15 3 -#define STM32_TIM_TS_SECONDARY_12_PRIMARY_4 0 -#define STM32_TIM_TS_SECONDARY_12_PRIMARY_5 1 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_19 0 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_15 1 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_3 2 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_14 3 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_19 0 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_2 1 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_5 2 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_14 3 +#define STM32_TIM_TS_SECONDARY_4_PRIMARY_19 0 +#define STM32_TIM_TS_SECONDARY_4_PRIMARY_2 1 +#define STM32_TIM_TS_SECONDARY_4_PRIMARY_3 2 +#define STM32_TIM_TS_SECONDARY_4_PRIMARY_15 3 +#define STM32_TIM_TS_SECONDARY_5_PRIMARY_2 0 +#define STM32_TIM_TS_SECONDARY_5_PRIMARY_3 1 +#define STM32_TIM_TS_SECONDARY_5_PRIMARY_4 2 +#define STM32_TIM_TS_SECONDARY_5_PRIMARY_15 3 +#define STM32_TIM_TS_SECONDARY_12_PRIMARY_4 0 +#define STM32_TIM_TS_SECONDARY_12_PRIMARY_5 1 #define STM32_TIM_TS_SECONDARY_12_PRIMARY_13 2 #define STM32_TIM_TS_SECONDARY_12_PRIMARY_14 3 -#define STM32_TIM_TS_SECONDARY_19_PRIMARY_2 0 -#define STM32_TIM_TS_SECONDARY_19_PRIMARY_3 1 +#define STM32_TIM_TS_SECONDARY_19_PRIMARY_2 0 +#define STM32_TIM_TS_SECONDARY_19_PRIMARY_3 1 #define STM32_TIM_TS_SECONDARY_19_PRIMARY_15 2 #define STM32_TIM_TS_SECONDARY_19_PRIMARY_16 3 #else /* !CHIP_FAMILY_STM32F0 && !CHIP_FAMILY_STM32F3 */ @@ -97,23 +98,23 @@ * ts = 0 1 2 3 */ #define STM32_TIM_TS_SECONDARY_1_PRIMARY_15 0 -#define STM32_TIM_TS_SECONDARY_1_PRIMARY_2 1 -#define STM32_TIM_TS_SECONDARY_1_PRIMARY_3 2 -#define STM32_TIM_TS_SECONDARY_1_PRIMARY_4 3 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_9 0 +#define STM32_TIM_TS_SECONDARY_1_PRIMARY_2 1 +#define STM32_TIM_TS_SECONDARY_1_PRIMARY_3 2 +#define STM32_TIM_TS_SECONDARY_1_PRIMARY_4 3 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_9 0 #define STM32_TIM_TS_SECONDARY_2_PRIMARY_10 1 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_3 2 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_4 3 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_9 0 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_2 1 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_3 2 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_4 3 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_9 0 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_2 1 #define STM32_TIM_TS_SECONDARY_3_PRIMARY_11 2 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_4 3 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_4 3 #define STM32_TIM_TS_SECONDARY_4_PRIMARY_10 0 -#define STM32_TIM_TS_SECONDARY_4_PRIMARY_2 1 -#define STM32_TIM_TS_SECONDARY_4_PRIMARY_3 2 -#define STM32_TIM_TS_SECONDARY_4_PRIMARY_9 3 -#define STM32_TIM_TS_SECONDARY_9_PRIMARY_2 0 -#define STM32_TIM_TS_SECONDARY_9_PRIMARY_3 1 +#define STM32_TIM_TS_SECONDARY_4_PRIMARY_2 1 +#define STM32_TIM_TS_SECONDARY_4_PRIMARY_3 2 +#define STM32_TIM_TS_SECONDARY_4_PRIMARY_9 3 +#define STM32_TIM_TS_SECONDARY_9_PRIMARY_2 0 +#define STM32_TIM_TS_SECONDARY_9_PRIMARY_3 1 #define STM32_TIM_TS_SECONDARY_9_PRIMARY_10 2 #define STM32_TIM_TS_SECONDARY_9_PRIMARY_11 3 #endif /* !CHIP_FAMILY_STM32F0 */ @@ -126,7 +127,7 @@ */ #define IRQ_MSB IRQ_TIM(TIM_CLOCK_MSB) #define IRQ_LSB IRQ_TIM(TIM_CLOCK_LSB) -#define IRQ_WD IRQ_TIM(TIM_WATCHDOG) +#define IRQ_WD IRQ_TIM(TIM_WATCHDOG) /* TIM1 has fancy names for its IRQs; remap count-up IRQ for the macro above */ #if defined TIM_WATCHDOG && (TIM_WATCHDOG == 1) @@ -360,8 +361,8 @@ int __hw_clock_source_init(uint32_t start_t) STM32_TIM_CR2(TIM_CLOCK_MSB) = 0x0000; STM32_TIM_CR2(TIM_CLOCK_LSB) = 0x0020; - STM32_TIM_SMCR(TIM_CLOCK_MSB) = 0x0007 | - (TSMAP(TIM_CLOCK_MSB, TIM_CLOCK_LSB) << 4); + STM32_TIM_SMCR(TIM_CLOCK_MSB) = + 0x0007 | (TSMAP(TIM_CLOCK_MSB, TIM_CLOCK_LSB) << 4); STM32_TIM_SMCR(TIM_CLOCK_LSB) = 0x0000; /* Auto-reload value : 16-bit free-running counters */ @@ -419,9 +420,12 @@ void IRQ_HANDLER(IRQ_WD)(void) "pop {r0,pc}\n"); } const struct irq_priority __keep IRQ_PRIORITY(IRQ_WD) - __attribute__((section(".rodata.irqprio"))) - = {IRQ_WD, 0}; /* put the watchdog at the highest - priority */ + __attribute__((section(".rodata.irqprio"))) = { + IRQ_WD, 0 + }; /* put the watchdog + at the highest + priority + */ void hwtimer_setup_watchdog(void) { @@ -474,4 +478,4 @@ void hwtimer_reset_watchdog(void) timer->cnt = timer->arr; } -#endif /* defined(CONFIG_WATCHDOG_HELP) */ +#endif /* defined(CONFIG_WATCHDOG_HELP) */ diff --git a/chip/stm32/hwtimer32.c b/chip/stm32/hwtimer32.c index f64eab989a..0448d34e4b 100644 --- a/chip/stm32/hwtimer32.c +++ b/chip/stm32/hwtimer32.c @@ -1,10 +1,11 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Hardware 32-bit timer driver */ +#include "builtin/assert.h" #include "clock.h" #include "clock-f.h" #include "common.h" @@ -115,7 +116,7 @@ void __hw_timer_enable_clock(int n, int enable) #endif #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \ -defined(CHIP_FAMILY_STM32H7) + defined(CHIP_FAMILY_STM32H7) if (n == 14) { reg = &STM32_RCC_APB1ENR; mask = STM32_RCC_PB1_TIM14; @@ -157,7 +158,7 @@ defined(CHIP_FAMILY_STM32H7) reg = &STM32_RCC_APB2ENR; mask = (n == 1) ? STM32_RCC_APB2ENR_TIM1EN : (n == 15) ? STM32_RCC_APB2ENR_TIM15EN : - STM32_RCC_APB2ENR_TIM16EN; + STM32_RCC_APB2ENR_TIM16EN; } #else if (n >= 2 && n <= 7) { @@ -213,12 +214,12 @@ static void update_prescaler(void) #ifdef CONFIG_WATCHDOG_HELP /* Watchdog timer runs at 1KHz */ STM32_TIM_PSC(TIM_WATCHDOG) = - (clock_get_timer_freq() / SECOND * MSEC)- 1; -#endif /* CONFIG_WATCHDOG_HELP */ + (clock_get_timer_freq() / SECOND * MSEC) - 1; +#endif /* CONFIG_WATCHDOG_HELP */ } DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT); #endif /* CHIP_FAMILY_STM32L || CHIP_FAMILY_STM32L4 || */ - /* CHIP_FAMILY_STM32F4 || CHIP_FAMILY_STM32H7 */ +/* CHIP_FAMILY_STM32F4 || CHIP_FAMILY_STM32H7 */ int __hw_clock_source_init(uint32_t start_t) { @@ -285,9 +286,12 @@ void IRQ_HANDLER(IRQ_WD)(void) "pop {r0,pc}\n"); } const struct irq_priority __keep IRQ_PRIORITY(IRQ_WD) - __attribute__((section(".rodata.irqprio"))) - = {IRQ_WD, 0}; /* put the watchdog at the highest - priority */ + __attribute__((section(".rodata.irqprio"))) = { + IRQ_WD, 0 + }; /* put the watchdog + at the highest + priority + */ void hwtimer_setup_watchdog(void) { @@ -320,8 +324,7 @@ void hwtimer_setup_watchdog(void) STM32_TIM_ARR(TIM_WATCHDOG) = CONFIG_AUX_TIMER_PERIOD_MS; /* Update prescaler: watchdog timer runs at 1KHz */ - STM32_TIM_PSC(TIM_WATCHDOG) = - (freq / SECOND * MSEC) - 1; + STM32_TIM_PSC(TIM_WATCHDOG) = (freq / SECOND * MSEC) - 1; } #ifdef CHIP_FAMILY_STM32L4 else { @@ -351,4 +354,4 @@ void hwtimer_reset_watchdog(void) STM32_TIM_CNT(TIM_WATCHDOG) = 0x0000; } -#endif /* CONFIG_WATCHDOG_HELP */ +#endif /* CONFIG_WATCHDOG_HELP */ diff --git a/chip/stm32/i2c-stm32f0.c b/chip/stm32/i2c-stm32f0.c index f78a450a4e..acd4d3aca6 100644 --- a/chip/stm32/i2c-stm32f0.c +++ b/chip/stm32/i2c-stm32f0.c @@ -1,8 +1,9 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ +#include "builtin/assert.h" #include "chipset.h" #include "clock.h" #include "common.h" @@ -23,10 +24,10 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) /* Transmit timeout in microseconds */ -#define I2C_TX_TIMEOUT_CONTROLLER (10 * MSEC) +#define I2C_TX_TIMEOUT_CONTROLLER (10 * MSEC) #ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS #if (I2C_PORT_EC == STM32_I2C1_PORT) @@ -36,11 +37,10 @@ #endif #endif - /* I2C port state data */ struct i2c_port_data { - uint32_t timeout_us; /* Transaction timeout, or 0 to use default */ - enum i2c_freq freq; /* Port clock speed */ + uint32_t timeout_us; /* Transaction timeout, or 0 to use default */ + enum i2c_freq freq; /* Port clock speed */ }; static struct i2c_port_data pdata[I2C_PORT_COUNT]; @@ -52,8 +52,8 @@ void i2c_set_timeout(int port, uint32_t timeout) /* timingr register values for supported input clks / i2c clk rates */ static const uint32_t busyloop_us[I2C_FREQ_COUNT] = { [I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */ - [I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */ - [I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */ + [I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */ + [I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */ }; /** @@ -72,7 +72,7 @@ static int wait_isr(int port, int mask) /* Check for errors */ if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR | - STM32_I2C_ISR_NACK)) + STM32_I2C_ISR_NACK)) return EC_ERROR_UNKNOWN; /* Check for desired mask */ @@ -118,8 +118,7 @@ int chip_i2c_set_freq(int port, enum i2c_freq freq) enum stm32_i2c_clk_src src = I2C_CLK_SRC_48MHZ; #if defined(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) && \ - defined(CONFIG_LOW_POWER_IDLE) && \ - (I2C_PORT_EC == STM32_I2C1_PORT) + defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT) if (port == STM32_I2C1_PORT) { /* * Use HSI (8MHz) for i2c clock. This allows smooth wakeup @@ -165,8 +164,7 @@ static int i2c_init_port(const struct i2c_port_t *p) if (port == STM32_I2C1_PORT) { #if defined(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) && \ - defined(CONFIG_LOW_POWER_IDLE) && \ - (I2C_PORT_EC == STM32_I2C1_PORT) + defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT) /* * Use HSI (8MHz) for i2c clock. This allows smooth wakeup * from STOP mode since HSI is only clock running immediately @@ -218,7 +216,7 @@ static int i2c_init_port(const struct i2c_port_t *p) */ static uint8_t host_buffer_padded[I2C_MAX_HOST_PACKET_SIZE + 4 + CONFIG_I2C_EXTRA_PACKET_SIZE] __aligned(4); -static uint8_t * const host_buffer = host_buffer_padded + 2; +static uint8_t *const host_buffer = host_buffer_padded + 2; static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4); static int host_i2c_resp_port; static int tx_pending; @@ -330,7 +328,7 @@ static void i2c_event_handler(int port) /* Clear error status bits */ STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF | - STM32_I2C_ICR_ARLOCF; + STM32_I2C_ICR_ARLOCF; } /* Transfer matched our peripheral address */ @@ -439,16 +437,18 @@ static void i2c_event_handler(int port) } } } -static void i2c2_event_interrupt(void) { i2c_event_handler(I2C_PORT_EC); } +static void i2c2_event_interrupt(void) +{ + i2c_event_handler(I2C_PORT_EC); +} DECLARE_IRQ(IRQ_PERIPHERAL, i2c2_event_interrupt, 2); #endif /*****************************************************************************/ /* Interface */ -int chip_i2c_xfer(const int port, const uint16_t addr_flags, - const uint8_t *out, int out_bytes, - uint8_t *in, int in_bytes, int flags) +int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out, + int out_bytes, uint8_t *in, int in_bytes, int flags) { int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1; int rv = EC_SUCCESS; @@ -495,13 +495,13 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, * if we are not stopping, set RELOAD bit so that we can load * NBYTES again. if we are starting, then set START bit. */ - STM32_I2C_CR2(port) = ((out_bytes & 0xFF) << 16) - | addr_8bit - | ((in_bytes == 0 && xfer_stop) ? - STM32_I2C_CR2_AUTOEND : 0) - | ((in_bytes == 0 && !xfer_stop) ? - STM32_I2C_CR2_RELOAD : 0) - | (xfer_start ? STM32_I2C_CR2_START : 0); + STM32_I2C_CR2(port) = + ((out_bytes & 0xFF) << 16) | addr_8bit | + ((in_bytes == 0 && xfer_stop) ? STM32_I2C_CR2_AUTOEND : + 0) | + ((in_bytes == 0 && !xfer_stop) ? STM32_I2C_CR2_RELOAD : + 0) | + (xfer_start ? STM32_I2C_CR2_START : 0); for (i = 0; i < out_bytes; i++) { rv = wait_isr(port, STM32_I2C_ISR_TXIS); @@ -524,11 +524,11 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, * NBYTES again. if we were just transmitting, we need to * set START bit to send (re)start and begin read transaction. */ - STM32_I2C_CR2(port) = ((in_bytes & 0xFF) << 16) - | STM32_I2C_CR2_RD_WRN | addr_8bit - | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) - | (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) - | (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0); + STM32_I2C_CR2(port) = + ((in_bytes & 0xFF) << 16) | STM32_I2C_CR2_RD_WRN | + addr_8bit | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) | + (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) | + (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0); for (i = 0; i < in_bytes; i++) { /* Wait for receive buffer not empty */ @@ -614,7 +614,7 @@ int i2c_raw_get_sda(int port) int i2c_get_line_levels(int port) { return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) | - (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); + (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); } void i2c_init(void) @@ -626,9 +626,10 @@ void i2c_init(void) i2c_init_port(p); #ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS - STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE - | STM32_I2C_CR1_ADDRIE | STM32_I2C_CR1_STOPIE - | STM32_I2C_CR1_NACKIE; + STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE | + STM32_I2C_CR1_ADDRIE | + STM32_I2C_CR1_STOPIE | + STM32_I2C_CR1_NACKIE; #if defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT) /* * If using low power idle and EC port is I2C1, then set I2C1 to wake @@ -637,15 +638,16 @@ void i2c_init(void) */ STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_WUPEN; #endif - STM32_I2C_OAR1(I2C_PORT_EC) = 0x8000 - | (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1); + STM32_I2C_OAR1(I2C_PORT_EC) = + 0x8000 | (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1); #ifdef TCPCI_I2C_PERIPHERAL /* * Configure TCPC address with OA2[1] masked so that we respond * to CONFIG_TCPC_I2C_BASE_ADDR and CONFIG_TCPC_I2C_BASE_ADDR + 2. */ - STM32_I2C_OAR2(I2C_PORT_EC) = 0x8100 - | (I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS) << 1); + STM32_I2C_OAR2(I2C_PORT_EC) = + 0x8100 | + (I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS) << 1); #endif task_enable_irq(IRQ_PERIPHERAL); #endif diff --git a/chip/stm32/i2c-stm32f3.c b/chip/stm32/i2c-stm32f3.c index ce8523ea90..acd4d3aca6 120000..100644 --- a/chip/stm32/i2c-stm32f3.c +++ b/chip/stm32/i2c-stm32f3.c @@ -1 +1,654 @@ -i2c-stm32f0.c
\ No newline at end of file +/* Copyright 2013 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "builtin/assert.h" +#include "chipset.h" +#include "clock.h" +#include "common.h" +#include "console.h" +#include "gpio.h" +#include "hooks.h" +#include "host_command.h" +#include "hwtimer.h" +#include "i2c.h" +#include "i2c_private.h" +#include "registers.h" +#include "system.h" +#include "task.h" +#include "timer.h" +#include "usb_pd_tcpc.h" +#include "usb_pd_tcpm.h" +#include "util.h" + +/* Console output macros */ +#define CPUTS(outstr) cputs(CC_I2C, outstr) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) + +/* Transmit timeout in microseconds */ +#define I2C_TX_TIMEOUT_CONTROLLER (10 * MSEC) + +#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS +#if (I2C_PORT_EC == STM32_I2C1_PORT) +#define IRQ_PERIPHERAL STM32_IRQ_I2C1 +#else +#define IRQ_PERIPHERAL STM32_IRQ_I2C2 +#endif +#endif + +/* I2C port state data */ +struct i2c_port_data { + uint32_t timeout_us; /* Transaction timeout, or 0 to use default */ + enum i2c_freq freq; /* Port clock speed */ +}; +static struct i2c_port_data pdata[I2C_PORT_COUNT]; + +void i2c_set_timeout(int port, uint32_t timeout) +{ + pdata[port].timeout_us = timeout ? timeout : I2C_TX_TIMEOUT_CONTROLLER; +} + +/* timingr register values for supported input clks / i2c clk rates */ +static const uint32_t busyloop_us[I2C_FREQ_COUNT] = { + [I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */ + [I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */ + [I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */ +}; + +/** + * Wait for ISR register to contain the specified mask. + * + * Returns EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or + * EC_ERROR_UNKNOWN if an error bit appeared in the status register. + */ +static int wait_isr(int port, int mask) +{ + uint32_t start = __hw_clock_source_read(); + uint32_t delta = 0; + + do { + int isr = STM32_I2C_ISR(port); + + /* Check for errors */ + if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR | + STM32_I2C_ISR_NACK)) + return EC_ERROR_UNKNOWN; + + /* Check for desired mask */ + if ((isr & mask) == mask) + return EC_SUCCESS; + + delta = __hw_clock_source_read() - start; + + /** + * Depending on the bus speed, busy loop for a while before + * sleeping and letting other things run. + */ + if (delta >= busyloop_us[pdata[port].freq]) + usleep(100); + } while (delta < pdata[port].timeout_us); + + return EC_ERROR_TIMEOUT; +} + +/* Supported i2c input clocks */ +enum stm32_i2c_clk_src { + I2C_CLK_SRC_48MHZ = 0, + I2C_CLK_SRC_8MHZ = 1, + I2C_CLK_SRC_COUNT, +}; + +/* timingr register values for supported input clks / i2c clk rates */ +static const uint32_t timingr_regs[I2C_CLK_SRC_COUNT][I2C_FREQ_COUNT] = { + [I2C_CLK_SRC_48MHZ] = { + [I2C_FREQ_1000KHZ] = 0x50100103, + [I2C_FREQ_400KHZ] = 0x50330609, + [I2C_FREQ_100KHZ] = 0xB0421214, + }, + [I2C_CLK_SRC_8MHZ] = { + [I2C_FREQ_1000KHZ] = 0x00100306, + [I2C_FREQ_400KHZ] = 0x00310309, + [I2C_FREQ_100KHZ] = 0x10420f13, + }, +}; + +int chip_i2c_set_freq(int port, enum i2c_freq freq) +{ + enum stm32_i2c_clk_src src = I2C_CLK_SRC_48MHZ; + +#if defined(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) && \ + defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT) + if (port == STM32_I2C1_PORT) { + /* + * Use HSI (8MHz) for i2c clock. This allows smooth wakeup + * from STOP mode since HSI is only clock running immediately + * upon exit from STOP mode. + */ + src = I2C_CLK_SRC_8MHZ; + } +#endif + + /* Disable port */ + STM32_I2C_CR1(port) = 0; + STM32_I2C_CR2(port) = 0; + /* Set clock frequency */ + STM32_I2C_TIMINGR(port) = timingr_regs[src][freq]; + /* Enable port */ + STM32_I2C_CR1(port) = STM32_I2C_CR1_PE; + + pdata[port].freq = freq; + + return EC_SUCCESS; +} + +enum i2c_freq chip_i2c_get_freq(int port) +{ + return pdata[port].freq; +} + +/** + * Initialize on the specified I2C port. + * + * @param p the I2c port + */ +static int i2c_init_port(const struct i2c_port_t *p) +{ + int port = p->port; + int ret = EC_SUCCESS; + enum i2c_freq freq; + + /* Enable clocks to I2C modules if necessary */ + if (!(STM32_RCC_APB1ENR & (1 << (21 + port)))) + STM32_RCC_APB1ENR |= 1 << (21 + port); + + if (port == STM32_I2C1_PORT) { +#if defined(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) && \ + defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT) + /* + * Use HSI (8MHz) for i2c clock. This allows smooth wakeup + * from STOP mode since HSI is only clock running immediately + * upon exit from STOP mode. + */ + STM32_RCC_CFGR3 &= ~0x10; +#else + /* Use SYSCLK for i2c clock. */ + STM32_RCC_CFGR3 |= 0x10; +#endif + } + + /* Configure GPIOs */ + gpio_config_module(MODULE_I2C, 1); + + /* Set clock frequency */ + switch (p->kbps) { + case 1000: + freq = I2C_FREQ_1000KHZ; + break; + case 400: + freq = I2C_FREQ_400KHZ; + break; + case 100: + freq = I2C_FREQ_100KHZ; + break; + default: /* unknown speed, defaults to 100kBps */ + CPRINTS("I2C bad speed %d kBps", p->kbps); + freq = I2C_FREQ_100KHZ; + ret = EC_ERROR_INVAL; + } + + /* Set up initial bus frequencies */ + chip_i2c_set_freq(p->port, freq); + + /* Set up default timeout */ + i2c_set_timeout(port, 0); + + return ret; +} + +/*****************************************************************************/ +#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS +/* Host command peripheral */ +/* + * Buffer for received host command packets (including prefix byte on request, + * and result/size on response). After any protocol-specific headers, the + * buffers must be 32-bit aligned. + */ +static uint8_t host_buffer_padded[I2C_MAX_HOST_PACKET_SIZE + 4 + + CONFIG_I2C_EXTRA_PACKET_SIZE] __aligned(4); +static uint8_t *const host_buffer = host_buffer_padded + 2; +static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4); +static int host_i2c_resp_port; +static int tx_pending; +static int tx_index, tx_end; +static struct host_packet i2c_packet; + +static void i2c_send_response_packet(struct host_packet *pkt) +{ + int size = pkt->response_size; + uint8_t *out = host_buffer; + + /* Ignore host command in-progress */ + if (pkt->driver_result == EC_RES_IN_PROGRESS) + return; + + /* Write result and size to first two bytes. */ + *out++ = pkt->driver_result; + *out++ = size; + + /* host_buffer data range */ + tx_index = 0; + tx_end = size + 2; + + /* + * Set the transmitter to be in 'not full' state to keep sending + * '0xec' in the event loop. Because of this, the controller i2c + * doesn't need to snoop the response stream to abort transaction. + */ + STM32_I2C_CR1(host_i2c_resp_port) |= STM32_I2C_CR1_TXIE; +} + +/* Process the command in the i2c host buffer */ +static void i2c_process_command(void) +{ + char *buff = host_buffer; + + /* + * TODO(crosbug.com/p/29241): Combine this functionality with the + * i2c_process_command function in chip/stm32/i2c-stm32f.c to make one + * host command i2c process function which handles all protocol + * versions. + */ + i2c_packet.send_response = i2c_send_response_packet; + + i2c_packet.request = (const void *)(&buff[1]); + i2c_packet.request_temp = params_copy; + i2c_packet.request_max = sizeof(params_copy); + /* Don't know the request size so pass in the entire buffer */ + i2c_packet.request_size = I2C_MAX_HOST_PACKET_SIZE; + + /* + * Stuff response at buff[2] to leave the first two bytes of + * buffer available for the result and size to send over i2c. Note + * that this 2-byte offset and the 2-byte offset from host_buffer + * add up to make the response buffer 32-bit aligned. + */ + i2c_packet.response = (void *)(&buff[2]); + i2c_packet.response_max = I2C_MAX_HOST_PACKET_SIZE; + i2c_packet.response_size = 0; + + if (*buff >= EC_COMMAND_PROTOCOL_3) { + i2c_packet.driver_result = EC_RES_SUCCESS; + } else { + /* Only host command protocol 3 is supported. */ + i2c_packet.driver_result = EC_RES_INVALID_HEADER; + } + host_packet_receive(&i2c_packet); +} + +#ifdef TCPCI_I2C_PERIPHERAL +static void i2c_send_tcpc_response(int len) +{ + /* host_buffer data range, beyond this length, will return 0xec */ + tx_index = 0; + tx_end = len; + + /* enable transmit interrupt and use irq to send data back */ + STM32_I2C_CR1(host_i2c_resp_port) |= STM32_I2C_CR1_TXIE; +} + +static void i2c_process_tcpc_command(int read, int addr, int len) +{ + tcpc_i2c_process(read, TCPC_ADDR_TO_PORT(addr), len, &host_buffer[0], + i2c_send_tcpc_response); +} +#endif + +static void i2c_event_handler(int port) +{ + int i2c_isr; + static int rx_pending, buf_idx; +#ifdef TCPCI_I2C_PERIPHERAL + int addr; +#endif + + i2c_isr = STM32_I2C_ISR(port); + + /* + * Check for error conditions. Note, arbitration loss and bus error + * are the only two errors we can get as a peripheral allowing clock + * stretching and in non-SMBus mode. + */ + if (i2c_isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR)) { + rx_pending = 0; + tx_pending = 0; + + /* Make sure TXIS interrupt is disabled */ + STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE; + + /* Clear error status bits */ + STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF | + STM32_I2C_ICR_ARLOCF; + } + + /* Transfer matched our peripheral address */ + if (i2c_isr & STM32_I2C_ISR_ADDR) { + if (i2c_isr & STM32_I2C_ISR_DIR) { + /* Transmitter peripheral */ + /* Clear transmit buffer */ + STM32_I2C_ISR(port) |= STM32_I2C_ISR_TXE; + + /* Enable txis interrupt to start response */ + STM32_I2C_CR1(port) |= STM32_I2C_CR1_TXIE; + } else { + /* Receiver peripheral */ + buf_idx = 0; + rx_pending = 1; + } + + /* Clear ADDR bit by writing to ADDRCF bit */ + STM32_I2C_ICR(port) |= STM32_I2C_ICR_ADDRCF; + /* Inhibit sleep mode when addressed until STOPF flag is set */ + disable_sleep(SLEEP_MASK_I2C_PERIPHERAL); + } + + /* Receiver full event */ + if (i2c_isr & STM32_I2C_ISR_RXNE) + host_buffer[buf_idx++] = STM32_I2C_RXDR(port); + + /* Stop condition on bus */ + if (i2c_isr & STM32_I2C_ISR_STOP) { +#ifdef TCPCI_I2C_PERIPHERAL + /* + * if tcpc is being addressed, and we received a stop + * while rx is pending, then this is a write only to + * the tcpc. + */ + addr = STM32_I2C_ISR_ADDCODE(STM32_I2C_ISR(port)); + if (rx_pending && ADDR_IS_TCPC(addr)) + i2c_process_tcpc_command(0, addr, buf_idx); +#endif + rx_pending = 0; + tx_pending = 0; + + /* Make sure TXIS interrupt is disabled */ + STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE; + + /* Clear STOPF bit by writing to STOPCF bit */ + STM32_I2C_ICR(port) |= STM32_I2C_ICR_STOPCF; + + /* No longer inhibit deep sleep after stop condition */ + enable_sleep(SLEEP_MASK_I2C_PERIPHERAL); + } + + /* Controller requested STOP or RESTART */ + if (i2c_isr & STM32_I2C_ISR_NACK) { + /* Make sure TXIS interrupt is disabled */ + STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE; + /* Clear NACK */ + STM32_I2C_ICR(port) |= STM32_I2C_ICR_NACKCF; + /* Resend last byte on RESTART */ + if (port == I2C_PORT_EC && tx_index) + tx_index--; + } + + /* Transmitter empty event */ + if (i2c_isr & STM32_I2C_ISR_TXIS) { + if (port == I2C_PORT_EC) { /* host is waiting for PD response */ + if (tx_pending) { + if (tx_index < tx_end) { + STM32_I2C_TXDR(port) = + host_buffer[tx_index++]; + } else { + STM32_I2C_TXDR(port) = 0xec; + /* + * Set tx_index = 0 to prevent NACK + * handler resending last buffer byte. + */ + tx_index = 0; + tx_end = 0; + /* No pending data */ + tx_pending = 0; + } + } else if (rx_pending) { + host_i2c_resp_port = port; + /* + * Disable TXIS interrupt, transmission will + * be prepared by host command task. + */ + STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE; + +#ifdef TCPCI_I2C_PERIPHERAL + addr = STM32_I2C_ISR_ADDCODE( + STM32_I2C_ISR(port)); + if (ADDR_IS_TCPC(addr)) + i2c_process_tcpc_command(1, addr, + buf_idx); + else +#endif + i2c_process_command(); + + /* Reset host buffer after end of transfer */ + rx_pending = 0; + tx_pending = 1; + } else { + STM32_I2C_TXDR(port) = 0xec; + } + } + } +} +static void i2c2_event_interrupt(void) +{ + i2c_event_handler(I2C_PORT_EC); +} +DECLARE_IRQ(IRQ_PERIPHERAL, i2c2_event_interrupt, 2); +#endif + +/*****************************************************************************/ +/* Interface */ + +int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out, + int out_bytes, uint8_t *in, int in_bytes, int flags) +{ + int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1; + int rv = EC_SUCCESS; + int i; + int xfer_start = flags & I2C_XFER_START; + int xfer_stop = flags & I2C_XFER_STOP; + +#if defined(CONFIG_I2C_SCL_GATE_ADDR) && defined(CONFIG_I2C_SCL_GATE_PORT) + if (port == CONFIG_I2C_SCL_GATE_PORT && + addr_flags == CONFIG_I2C_SCL_GATE_ADDR_FLAGS) + gpio_set_level(CONFIG_I2C_SCL_GATE_GPIO, 1); +#endif + + ASSERT(out || !out_bytes); + ASSERT(in || !in_bytes); + + /* Clear status */ + if (xfer_start) { + uint32_t cr2 = STM32_I2C_CR2(port); + + STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL; + STM32_I2C_CR2(port) = 0; + if (cr2 & STM32_I2C_CR2_RELOAD) { + /* + * If I2C_XFER_START flag is on and we've set RELOAD=1 + * in previous chip_i2c_xfer() call. Then we are + * probably in the middle of an i2c transaction. + * + * In this case, we need to clear the RELOAD bit and + * wait for Transfer Complete (TC) flag, to make sure + * the chip is not expecting another NBYTES data, And + * send repeated-start correctly. + */ + rv = wait_isr(port, STM32_I2C_ISR_TC); + if (rv) + goto xfer_exit; + } + } + + if (out_bytes || !in_bytes) { + /* + * Configure the write transfer: if we are stopping then set + * AUTOEND bit to automatically set STOP bit after NBYTES. + * if we are not stopping, set RELOAD bit so that we can load + * NBYTES again. if we are starting, then set START bit. + */ + STM32_I2C_CR2(port) = + ((out_bytes & 0xFF) << 16) | addr_8bit | + ((in_bytes == 0 && xfer_stop) ? STM32_I2C_CR2_AUTOEND : + 0) | + ((in_bytes == 0 && !xfer_stop) ? STM32_I2C_CR2_RELOAD : + 0) | + (xfer_start ? STM32_I2C_CR2_START : 0); + + for (i = 0; i < out_bytes; i++) { + rv = wait_isr(port, STM32_I2C_ISR_TXIS); + if (rv) + goto xfer_exit; + /* Write next data byte */ + STM32_I2C_TXDR(port) = out[i]; + } + } + if (in_bytes) { + if (out_bytes) { /* wait for completion of the write */ + rv = wait_isr(port, STM32_I2C_ISR_TC); + if (rv) + goto xfer_exit; + } + /* + * Configure the read transfer: if we are stopping then set + * AUTOEND bit to automatically set STOP bit after NBYTES. + * if we are not stopping, set RELOAD bit so that we can load + * NBYTES again. if we were just transmitting, we need to + * set START bit to send (re)start and begin read transaction. + */ + STM32_I2C_CR2(port) = + ((in_bytes & 0xFF) << 16) | STM32_I2C_CR2_RD_WRN | + addr_8bit | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) | + (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) | + (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0); + + for (i = 0; i < in_bytes; i++) { + /* Wait for receive buffer not empty */ + rv = wait_isr(port, STM32_I2C_ISR_RXNE); + if (rv) + goto xfer_exit; + + in[i] = STM32_I2C_RXDR(port); + } + } + + /* + * If we are stopping, then we already set AUTOEND and we should + * wait for the stop bit to be transmitted. Otherwise, we set + * the RELOAD bit and we should wait for transfer complete + * reload (TCR). + */ + rv = wait_isr(port, xfer_stop ? STM32_I2C_ISR_STOP : STM32_I2C_ISR_TCR); + if (rv) + goto xfer_exit; + +xfer_exit: + /* clear status */ + if (xfer_stop) + STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL; + + /* On error, queue a stop condition */ + if (rv) { + /* queue a STOP condition */ + STM32_I2C_CR2(port) |= STM32_I2C_CR2_STOP; + /* wait for it to take effect */ + /* Wait up to 100 us for bus idle */ + for (i = 0; i < 10; i++) { + if (!(STM32_I2C_ISR(port) & STM32_I2C_ISR_BUSY)) + break; + udelay(10); + } + + /* + * Allow bus to idle for at least one 100KHz clock = 10 us. + * This allows peripherals on the bus to detect bus-idle before + * the next start condition. + */ + udelay(10); + /* re-initialize the controller */ + STM32_I2C_CR2(port) = 0; + STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_PE; + udelay(10); + STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE; + } + +#ifdef CONFIG_I2C_SCL_GATE_ADDR + if (port == CONFIG_I2C_SCL_GATE_PORT && + addr_flags == CONFIG_I2C_SCL_GATE_ADDR_FLAGS) + gpio_set_level(CONFIG_I2C_SCL_GATE_GPIO, 0); +#endif + + return rv; +} + +int i2c_raw_get_scl(int port) +{ + enum gpio_signal g; + + if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS) + return gpio_get_level(g); + + /* If no SCL pin defined for this port, then return 1 to appear idle. */ + return 1; +} + +int i2c_raw_get_sda(int port) +{ + enum gpio_signal g; + + if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS) + return gpio_get_level(g); + + /* If no SCL pin defined for this port, then return 1 to appear idle. */ + return 1; +} + +int i2c_get_line_levels(int port) +{ + return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) | + (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); +} + +void i2c_init(void) +{ + const struct i2c_port_t *p = i2c_ports; + int i; + + for (i = 0; i < i2c_ports_used; i++, p++) + i2c_init_port(p); + +#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS + STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE | + STM32_I2C_CR1_ADDRIE | + STM32_I2C_CR1_STOPIE | + STM32_I2C_CR1_NACKIE; +#if defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT) + /* + * If using low power idle and EC port is I2C1, then set I2C1 to wake + * from STOP mode on address match. Note, this only works on I2C1 and + * only if the clock to I2C1 is HSI 8MHz. + */ + STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_WUPEN; +#endif + STM32_I2C_OAR1(I2C_PORT_EC) = + 0x8000 | (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1); +#ifdef TCPCI_I2C_PERIPHERAL + /* + * Configure TCPC address with OA2[1] masked so that we respond + * to CONFIG_TCPC_I2C_BASE_ADDR and CONFIG_TCPC_I2C_BASE_ADDR + 2. + */ + STM32_I2C_OAR2(I2C_PORT_EC) = + 0x8100 | + (I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS) << 1); +#endif + task_enable_irq(IRQ_PERIPHERAL); +#endif +} diff --git a/chip/stm32/i2c-stm32f4.c b/chip/stm32/i2c-stm32f4.c index bce81b14c9..9f4d799912 100644 --- a/chip/stm32/i2c-stm32f4.c +++ b/chip/stm32/i2c-stm32f4.c @@ -1,9 +1,10 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ +#include "builtin/assert.h" #include "chipset.h" #include "clock.h" #include "common.h" @@ -20,12 +21,12 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) #define I2C_ERROR_FAILED_START EC_ERROR_INTERNAL_FIRST /* Transmit timeout in microseconds */ -#define I2C_TX_TIMEOUT_CONTROLLER (10 * MSEC) +#define I2C_TX_TIMEOUT_CONTROLLER (10 * MSEC) #ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS #if (I2C_PORT_EC == STM32_I2C1_PORT) @@ -43,36 +44,36 @@ * two sets of functions to handle this for stm32f4. In stm32f446, we * only have one FMP block so we'll hardcode its port number. */ -#define STM32F4_FMPI2C_PORT 3 +#define STM32F4_FMPI2C_PORT 3 static const __unused struct dma_option dma_tx_option[I2C_PORT_COUNT] = { - {STM32_DMAC_I2C1_TX, (void *)&STM32_I2C_DR(STM32_I2C1_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_I2C1_TX_REQ_CH)}, - {STM32_DMAC_I2C2_TX, (void *)&STM32_I2C_DR(STM32_I2C2_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_I2C2_TX_REQ_CH)}, - {STM32_DMAC_I2C3_TX, (void *)&STM32_I2C_DR(STM32_I2C3_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_I2C3_TX_REQ_CH)}, - {STM32_DMAC_FMPI2C4_TX, (void *)&STM32_FMPI2C_TXDR(STM32_FMPI2C4_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_FMPI2C4_TX_REQ_CH)}, + { STM32_DMAC_I2C1_TX, (void *)&STM32_I2C_DR(STM32_I2C1_PORT), + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + STM32_DMA_CCR_CHANNEL(STM32_I2C1_TX_REQ_CH) }, + { STM32_DMAC_I2C2_TX, (void *)&STM32_I2C_DR(STM32_I2C2_PORT), + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + STM32_DMA_CCR_CHANNEL(STM32_I2C2_TX_REQ_CH) }, + { STM32_DMAC_I2C3_TX, (void *)&STM32_I2C_DR(STM32_I2C3_PORT), + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + STM32_DMA_CCR_CHANNEL(STM32_I2C3_TX_REQ_CH) }, + { STM32_DMAC_FMPI2C4_TX, (void *)&STM32_FMPI2C_TXDR(STM32_FMPI2C4_PORT), + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + STM32_DMA_CCR_CHANNEL(STM32_FMPI2C4_TX_REQ_CH) }, }; static const struct dma_option dma_rx_option[I2C_PORT_COUNT] = { - {STM32_DMAC_I2C1_RX, (void *)&STM32_I2C_DR(STM32_I2C1_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_I2C1_RX_REQ_CH)}, - {STM32_DMAC_I2C2_RX, (void *)&STM32_I2C_DR(STM32_I2C2_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_I2C2_RX_REQ_CH)}, - {STM32_DMAC_I2C3_RX, (void *)&STM32_I2C_DR(STM32_I2C3_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_I2C3_RX_REQ_CH)}, - {STM32_DMAC_FMPI2C4_RX, (void *)&STM32_FMPI2C_RXDR(STM32_FMPI2C4_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_FMPI2C4_RX_REQ_CH)}, + { STM32_DMAC_I2C1_RX, (void *)&STM32_I2C_DR(STM32_I2C1_PORT), + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + STM32_DMA_CCR_CHANNEL(STM32_I2C1_RX_REQ_CH) }, + { STM32_DMAC_I2C2_RX, (void *)&STM32_I2C_DR(STM32_I2C2_PORT), + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + STM32_DMA_CCR_CHANNEL(STM32_I2C2_RX_REQ_CH) }, + { STM32_DMAC_I2C3_RX, (void *)&STM32_I2C_DR(STM32_I2C3_PORT), + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + STM32_DMA_CCR_CHANNEL(STM32_I2C3_RX_REQ_CH) }, + { STM32_DMAC_FMPI2C4_RX, (void *)&STM32_FMPI2C_RXDR(STM32_FMPI2C4_PORT), + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + STM32_DMA_CCR_CHANNEL(STM32_FMPI2C4_RX_REQ_CH) }, }; /* Callback for ISR to wake task on DMA complete. */ @@ -164,7 +165,6 @@ static int wait_sr1(int port, int mask) return wait_sr1_poll(port, mask, SET, 100); } - /** * Send a start condition and peripheral address on the specified port. * @@ -232,8 +232,8 @@ static int wait_fmpi2c_isr_poll(int port, int mask, int val, int poll) int isr = STM32_FMPI2C_ISR(port); /* Check for errors */ - if (isr & (FMPI2C_ISR_ARLO | FMPI2C_ISR_BERR | - FMPI2C_ISR_NACKF)) { + if (isr & + (FMPI2C_ISR_ARLO | FMPI2C_ISR_BERR | FMPI2C_ISR_NACKF)) { return EC_ERROR_UNKNOWN; } @@ -265,19 +265,18 @@ static int wait_fmpi2c_isr(int port, int mask) * * @return Non-zero if error. */ -static int send_fmpi2c_start(const int port, const uint16_t addr_8bit, - int size, int is_read) +static int send_fmpi2c_start(const int port, const uint16_t addr_8bit, int size, + int is_read) { uint32_t reg; /* Send start bit */ reg = STM32_FMPI2C_CR2(port); reg &= ~(FMPI2C_CR2_SADD_MASK | FMPI2C_CR2_SIZE_MASK | - FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | - FMPI2C_CR2_RD_WRN | FMPI2C_CR2_START | FMPI2C_CR2_STOP); - reg |= FMPI2C_CR2_START | FMPI2C_CR2_AUTOEND | - addr_8bit | FMPI2C_CR2_SIZE(size) | - (is_read ? FMPI2C_CR2_RD_WRN : 0); + FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | FMPI2C_CR2_RD_WRN | + FMPI2C_CR2_START | FMPI2C_CR2_STOP); + reg |= FMPI2C_CR2_START | FMPI2C_CR2_AUTOEND | addr_8bit | + FMPI2C_CR2_SIZE(size) | (is_read ? FMPI2C_CR2_RD_WRN : 0); STM32_FMPI2C_CR2(port) = reg; return EC_SUCCESS; @@ -300,17 +299,17 @@ static void i2c_set_freq_port(const struct i2c_port_t *p) /* FMP I2C clock set. */ STM32_FMPI2C_CR1(port) &= ~FMPI2C_CR1_PE; - prescalar = (freq / (p->kbps * 1000 * - (0x12 + 1 + 0xe + 1 + 1))) - 1; + prescalar = + (freq / (p->kbps * 1000 * (0x12 + 1 + 0xe + 1 + 1))) - + 1; actual = freq / ((prescalar + 1) * (0x12 + 1 + 0xe + 1 + 1)); - reg = FMPI2C_TIMINGR_SCLL(0x12) | - FMPI2C_TIMINGR_SCLH(0xe) | - FMPI2C_TIMINGR_PRESC(prescalar); + reg = FMPI2C_TIMINGR_SCLL(0x12) | FMPI2C_TIMINGR_SCLH(0xe) | + FMPI2C_TIMINGR_PRESC(prescalar); STM32_FMPI2C_TIMINGR(port) = reg; - CPRINTS("port %d target %d, pre %d, act %d, reg 0x%08x", - port, p->kbps, prescalar, actual, reg); + CPRINTS("port %d target %d, pre %d, act %d, reg 0x%08x", port, + p->kbps, prescalar, actual, reg); STM32_FMPI2C_CR1(port) |= FMPI2C_CR1_PE; udelay(10); @@ -323,9 +322,9 @@ static void i2c_set_freq_port(const struct i2c_port_t *p) if (p->kbps > 100) { STM32_I2C_CCR(port) = freq / (2 * MSEC * p->kbps); } else { - STM32_I2C_CCR(port) = STM32_I2C_CCR_FM - | STM32_I2C_CCR_DUTY - | (freq / (16 + 9 * MSEC * p->kbps)); + STM32_I2C_CCR(port) = + STM32_I2C_CCR_FM | STM32_I2C_CCR_DUTY | + (freq / (16 + 9 * MSEC * p->kbps)); } STM32_I2C_CR2(port) = freq / SECOND; STM32_I2C_TRISE(port) = freq / SECOND + 1; @@ -384,10 +383,10 @@ static void fmpi2c_clear_regs(int port) STM32_FMPI2C_ICR(port) = 0xffffffff; /* Clear start, stop, NACK, etc. bits to get us in a known state */ - STM32_FMPI2C_CR2(port) &= ~(FMPI2C_CR2_START | FMPI2C_CR2_STOP | - FMPI2C_CR2_RD_WRN | FMPI2C_CR2_NACK | - FMPI2C_CR2_AUTOEND | - FMPI2C_CR2_SADD_MASK | FMPI2C_CR2_SIZE_MASK); + STM32_FMPI2C_CR2(port) &= + ~(FMPI2C_CR2_START | FMPI2C_CR2_STOP | FMPI2C_CR2_RD_WRN | + FMPI2C_CR2_NACK | FMPI2C_CR2_AUTOEND | FMPI2C_CR2_SADD_MASK | + FMPI2C_CR2_SIZE_MASK); } /** @@ -404,8 +403,8 @@ static void fmpi2c_clear_regs(int port) * @return EC_SUCCESS on success. */ static int chip_fmpi2c_xfer(const int port, const uint16_t addr_8bit, - const uint8_t *out, int out_bytes, - uint8_t *in, int in_bytes, int flags) + const uint8_t *out, int out_bytes, uint8_t *in, + int in_bytes, int flags) { int started = (flags & I2C_XFER_START) ? 0 : 1; int rv = EC_SUCCESS; @@ -424,8 +423,8 @@ static int chip_fmpi2c_xfer(const int port, const uint16_t addr_8bit, /* No out bytes and no in bytes means just check for active */ if (out_bytes || !in_bytes) { - rv = send_fmpi2c_start( - port, addr_8bit, out_bytes, FMPI2C_WRITE); + rv = send_fmpi2c_start(port, addr_8bit, out_bytes, + FMPI2C_WRITE); if (rv) goto xfer_exit; @@ -450,8 +449,8 @@ static int chip_fmpi2c_xfer(const int port, const uint16_t addr_8bit, dma_start_rx(dma, in_bytes, in); i2c_dma_enable_tc_interrupt(dma->channel, port); - rv_start = send_fmpi2c_start( - port, addr_8bit, in_bytes, FMPI2C_READ); + rv_start = send_fmpi2c_start(port, addr_8bit, in_bytes, + FMPI2C_READ); if (rv_start) goto xfer_exit; @@ -460,9 +459,8 @@ static int chip_fmpi2c_xfer(const int port, const uint16_t addr_8bit, goto xfer_exit; STM32_FMPI2C_CR1(port) |= FMPI2C_CR1_RXDMAEN; - rv = task_wait_event_mask( - TASK_EVENT_I2C_COMPLETION(port), - DMA_TRANSFER_TIMEOUT_US); + rv = task_wait_event_mask(TASK_EVENT_I2C_COMPLETION(port), + DMA_TRANSFER_TIMEOUT_US); if (rv & TASK_EVENT_I2C_COMPLETION(port)) rv = EC_SUCCESS; else @@ -478,7 +476,7 @@ static int chip_fmpi2c_xfer(const int port, const uint16_t addr_8bit, STM32_FMPI2C_CR1(port) &= ~FMPI2C_CR1_RXDMAEN; } - xfer_exit: +xfer_exit: /* On error, queue a stop condition */ if (rv) { flags |= I2C_XFER_STOP; @@ -492,7 +490,8 @@ static int chip_fmpi2c_xfer(const int port, const uint16_t addr_8bit, const struct i2c_port_t *p; CPRINTS("chip_fmpi2c_xfer start error; " - "unwedging and resetting i2c %d", port); + "unwedging and resetting i2c %d", + port); p = find_port(port); i2c_unwedge(port); @@ -522,7 +521,6 @@ static int chip_fmpi2c_xfer(const int port, const uint16_t addr_8bit, return rv; } - /** * Clear status regs on the specified I2C port. * @@ -539,10 +537,8 @@ static void i2c_clear_regs(int port) STM32_I2C_SR1(port) = 0; /* Clear start, stop, POS, ACK bits to get us in a known state */ - STM32_I2C_CR1(port) &= ~(STM32_I2C_CR1_START | - STM32_I2C_CR1_STOP | - STM32_I2C_CR1_POS | - STM32_I2C_CR1_ACK); + STM32_I2C_CR1(port) &= ~(STM32_I2C_CR1_START | STM32_I2C_CR1_STOP | + STM32_I2C_CR1_POS | STM32_I2C_CR1_ACK); } /***************************************************************************** @@ -550,9 +546,8 @@ static void i2c_clear_regs(int port) */ /* Perform an i2c transaction. */ -int chip_i2c_xfer(const int port, const uint16_t addr_flags, - const uint8_t *out, int out_bytes, - uint8_t *in, int in_bytes, int flags) +int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out, + int out_bytes, uint8_t *in, int in_bytes, int flags) { int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1; int started = (flags & I2C_XFER_START) ? 0 : 1; @@ -565,9 +560,8 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, ASSERT(!started); if (p->port == STM32F4_FMPI2C_PORT) { - return chip_fmpi2c_xfer(port, addr_8bit, - out, out_bytes, - in, in_bytes, flags); + return chip_fmpi2c_xfer(port, addr_8bit, out, out_bytes, in, + in_bytes, flags); } i2c_clear_regs(port); @@ -644,7 +638,7 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_DMAEN; } - xfer_exit: +xfer_exit: /* On error, queue a stop condition */ if (rv) { flags |= I2C_XFER_STOP; @@ -658,7 +652,8 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, const struct i2c_port_t *p; CPRINTS("chip_i2c_xfer start error; " - "unwedging and resetting i2c %d", port); + "unwedging and resetting i2c %d", + port); p = find_port(port); i2c_unwedge(port); @@ -711,7 +706,7 @@ int i2c_raw_get_sda(int port) int i2c_get_line_levels(int port) { return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) | - (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); + (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); } /*****************************************************************************/ @@ -766,7 +761,7 @@ DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_change_hook, HOOK_PRIO_DEFAULT); */ static uint8_t host_buffer_padded[I2C_MAX_HOST_PACKET_SIZE + 4 + CONFIG_I2C_EXTRA_PACKET_SIZE] __aligned(4); -static uint8_t * const host_buffer = host_buffer_padded + 2; +static uint8_t *const host_buffer = host_buffer_padded + 2; static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4); static int host_i2c_resp_port; static int tx_pending; @@ -879,14 +874,16 @@ static void i2c_event_handler(int port) /* Disable buffer interrupt */ STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_ITBUFEN; /* Clear error status bits */ - STM32_I2C_SR1(port) &= ~(STM32_I2C_SR1_ARLO | - STM32_I2C_SR1_BERR); + STM32_I2C_SR1(port) &= + ~(STM32_I2C_SR1_ARLO | STM32_I2C_SR1_BERR); } /* Transfer matched our peripheral address */ if (i2c_sr1 & STM32_I2C_SR1_ADDR) { addr_8bit = ((i2c_sr2 & STM32_I2C_SR2_DUALF) ? - STM32_I2C_OAR2(port) : STM32_I2C_OAR1(port)) & 0xfe; + STM32_I2C_OAR2(port) : + STM32_I2C_OAR1(port)) & + 0xfe; if (i2c_sr2 & STM32_I2C_SR2_TRA) { /* Transmitter peripheral */ i2c_sr1 |= STM32_I2C_SR1_TXE; @@ -957,7 +954,7 @@ static void i2c_event_handler(int port) #ifdef CONFIG_BOARD_I2C_ADDR_FLAGS if (rx_pending && (addr_8b >> 1) == - I2C_STRIP_FLAGS(CONFIG_BOARD_I2C_ADDR_FLAGS)) + I2C_STRIP_FLAGS(CONFIG_BOARD_I2C_ADDR_FLAGS)) i2c_process_board_command(0, addr_8bit, buf_idx); #endif rx_pending = 0; @@ -977,12 +974,14 @@ static void i2c_event_handler(int port) if (!(i2c_cr1 & STM32_I2C_CR1_PE)) STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE; } -static void i2c_event_interrupt(void) { i2c_event_handler(I2C_PORT_EC); } +static void i2c_event_interrupt(void) +{ + i2c_event_handler(I2C_PORT_EC); +} DECLARE_IRQ(IRQ_PERIPHERAL_EV, i2c_event_interrupt, 2); DECLARE_IRQ(IRQ_PERIPHERAL_ER, i2c_event_interrupt, 2); #endif - /* Init all available i2c ports */ void i2c_init(void) { @@ -992,19 +991,20 @@ void i2c_init(void) for (i = 0; i < i2c_ports_used; i++, p++) i2c_init_port(p); - #ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS /* Enable ACK */ STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_ACK; /* Enable interrupts */ - STM32_I2C_CR2(I2C_PORT_EC) |= STM32_I2C_CR2_ITEVTEN - | STM32_I2C_CR2_ITERREN; + STM32_I2C_CR2(I2C_PORT_EC) |= STM32_I2C_CR2_ITEVTEN | + STM32_I2C_CR2_ITERREN; /* Setup host command peripheral */ - STM32_I2C_OAR1(I2C_PORT_EC) = STM32_I2C_OAR1_B14 - | (I2C_STRIP_ADDR(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1); + STM32_I2C_OAR1(I2C_PORT_EC) = + STM32_I2C_OAR1_B14 | + (I2C_STRIP_ADDR(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1); #ifdef CONFIG_BOARD_I2C_ADDR_FLAGS - STM32_I2C_OAR2(I2C_PORT_EC) = STM32_I2C_OAR2_ENDUAL - | (I2C_STRIP_FLAGS(CONFIG_BOARD_I2C_ADDR_FLAGS) << 1); + STM32_I2C_OAR2(I2C_PORT_EC) = + STM32_I2C_OAR2_ENDUAL | + (I2C_STRIP_FLAGS(CONFIG_BOARD_I2C_ADDR_FLAGS) << 1); #endif task_enable_irq(IRQ_PERIPHERAL_EV); task_enable_irq(IRQ_PERIPHERAL_ER); diff --git a/chip/stm32/i2c-stm32g4.c b/chip/stm32/i2c-stm32g4.c index fbb13e3453..66ec8173d8 100644 --- a/chip/stm32/i2c-stm32g4.c +++ b/chip/stm32/i2c-stm32g4.c @@ -1,8 +1,9 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ +#include "builtin/assert.h" #include "chipset.h" #include "clock.h" #include "common.h" @@ -20,12 +21,12 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) #define I2C_ERROR_FAILED_START EC_ERROR_INTERNAL_FIRST /* Transmit timeout in microseconds */ -#define I2C_TX_TIMEOUT_MASTER (10 * MSEC) +#define I2C_TX_TIMEOUT_MASTER (10 * MSEC) enum i2c_freq_khz { freq_100 = 100, @@ -44,8 +45,8 @@ struct i2c_timing { /* timing register values for supported input clks / i2c clk rates */ static const uint32_t busyloop_us[I2C_FREQ_COUNT] = { [I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */ - [I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */ - [I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */ + [I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */ + [I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */ }; /* @@ -94,8 +95,8 @@ static const uint32_t i2c_regs_base[] = { /* I2C port state data */ struct i2c_port_data { - uint32_t timeout_us; /* Transaction timeout, or 0 to use default */ - enum i2c_freq freq; /* Port clock speed */ + uint32_t timeout_us; /* Transaction timeout, or 0 to use default */ + enum i2c_freq freq; /* Port clock speed */ }; static struct i2c_port_data pdata[I2C_PORT_COUNT]; @@ -145,10 +146,10 @@ static void i2c_set_timingr_port(const struct i2c_port_t *p) } /* Assemble write value for timingr register */ timingr = (i2c_timingr[index].scll << STM32_I2C_TIMINGR_SCLL_OFF) | - (i2c_timingr[index].sclh << STM32_I2C_TIMINGR_SCLH_OFF) | - (i2c_timingr[index].sdadel << STM32_I2C_TIMINGR_SDADEL_OFF) | - (i2c_timingr[index].scldel << STM32_I2C_TIMINGR_SCLDEL_OFF) | - (i2c_timingr[index].presc << STM32_I2C_TIMINGR_PRESC_OFF); + (i2c_timingr[index].sclh << STM32_I2C_TIMINGR_SCLH_OFF) | + (i2c_timingr[index].sdadel << STM32_I2C_TIMINGR_SDADEL_OFF) | + (i2c_timingr[index].scldel << STM32_I2C_TIMINGR_SCLDEL_OFF) | + (i2c_timingr[index].presc << STM32_I2C_TIMINGR_PRESC_OFF); /* Write timingr value */ STM32_I2C_TIMINGR(base) = timingr; @@ -189,8 +190,8 @@ static void i2c_init_port(const struct i2c_port_t *p) mask = STM32_RCC_CCIPR_I2CNSEL_MASK << shift; clksel = STM32_RCC_CCIPR; clksel &= ~mask; - STM32_RCC_CCIPR = clksel | (STM32_RCC_CCIPR_I2CNSEL_HSI - << shift); + STM32_RCC_CCIPR = clksel | + (STM32_RCC_CCIPR_I2CNSEL_HSI << shift); } else if (port == 3) { /* i2c4sel is bits 1:0, no shift required */ STM32_RCC_CCIPR2 &= ~STM32_RCC_CCIPR2_I2C4SEL_MASK; @@ -260,9 +261,8 @@ static int wait_isr(int port, int mask) * Exported functions declared in i2c.h */ /* Perform an i2c transaction. */ -int chip_i2c_xfer(const int port, const uint16_t addr_flags, - const uint8_t *out, int out_bytes, - uint8_t *in, int in_bytes, int flags) +int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out, + int out_bytes, uint8_t *in, int in_bytes, int flags) { int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1; int rv = EC_SUCCESS; @@ -290,13 +290,13 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, * if we are not stopping, set RELOAD bit so that we can load * NBYTES again. if we are starting, then set START bit. */ - STM32_I2C_CR2(base) = ((out_bytes & 0xFF) << 16) - | addr_8bit - | ((in_bytes == 0 && xfer_stop) ? - STM32_I2C_CR2_AUTOEND : 0) - | ((in_bytes == 0 && !xfer_stop) ? - STM32_I2C_CR2_RELOAD : 0) - | (xfer_start ? STM32_I2C_CR2_START : 0); + STM32_I2C_CR2(base) = + ((out_bytes & 0xFF) << 16) | addr_8bit | + ((in_bytes == 0 && xfer_stop) ? STM32_I2C_CR2_AUTOEND : + 0) | + ((in_bytes == 0 && !xfer_stop) ? STM32_I2C_CR2_RELOAD : + 0) | + (xfer_start ? STM32_I2C_CR2_START : 0); for (i = 0; i < out_bytes; i++) { rv = wait_isr(port, STM32_I2C_ISR_TXIS); @@ -319,11 +319,11 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, * NBYTES again. if we were just transmitting, we need to * set START bit to send (re)start and begin read transaction. */ - STM32_I2C_CR2(base) = ((in_bytes & 0xFF) << 16) - | STM32_I2C_CR2_RD_WRN | addr_8bit - | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) - | (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) - | (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0); + STM32_I2C_CR2(base) = + ((in_bytes & 0xFF) << 16) | STM32_I2C_CR2_RD_WRN | + addr_8bit | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) | + (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) | + (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0); for (i = 0; i < in_bytes; i++) { /* Wait for receive buffer not empty */ @@ -402,7 +402,7 @@ int i2c_raw_get_sda(int port) int i2c_get_line_levels(int port) { return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) | - (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); + (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); } /*****************************************************************************/ diff --git a/chip/stm32/i2c-stm32l.c b/chip/stm32/i2c-stm32l.c index 74ecff192d..f18374281a 100644 --- a/chip/stm32/i2c-stm32l.c +++ b/chip/stm32/i2c-stm32l.c @@ -1,8 +1,9 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ +#include "builtin/assert.h" #include "chipset.h" #include "clock.h" #include "common.h" @@ -19,7 +20,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) #define I2C_ERROR_FAILED_START EC_ERROR_INTERNAL_FIRST @@ -35,23 +36,20 @@ * flips out. The battery may flip out and hold lines low for up to * 25ms. If we just wait it will eventually let them go. */ -#define I2C_TX_TIMEOUT_MASTER (30 * MSEC) +#define I2C_TX_TIMEOUT_MASTER (30 * MSEC) /* * Delay 5us in bitbang mode. That gives us roughly 5us low and 5us high or * a frequency of 100kHz. */ -#define I2C_BITBANG_HALF_CYCLE_US 5 +#define I2C_BITBANG_HALF_CYCLE_US 5 #ifdef CONFIG_I2C_DEBUG static void dump_i2c_reg(int port, const char *what) { CPRINTS("i2c CR1=%04x CR2=%04x SR1=%04x SR2=%04x %s", - STM32_I2C_CR1(port), - STM32_I2C_CR2(port), - STM32_I2C_SR1(port), - STM32_I2C_SR2(port), - what); + STM32_I2C_CR1(port), STM32_I2C_CR2(port), STM32_I2C_SR1(port), + STM32_I2C_SR2(port), what); } #else static inline void dump_i2c_reg(int port, const char *what) @@ -164,10 +162,8 @@ static void i2c_init_port(const struct i2c_port_t *p) /*****************************************************************************/ /* Interface */ -int chip_i2c_xfer(const int port, - const uint16_t addr_flags, - const uint8_t *out, int out_bytes, - uint8_t *in, int in_bytes, int flags) +int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out, + int out_bytes, uint8_t *in, int in_bytes, int flags) { int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1; int started = (flags & I2C_XFER_START) ? 0 : 1; @@ -188,10 +184,8 @@ int chip_i2c_xfer(const int port, STM32_I2C_SR1(port) = 0; /* Clear start, stop, POS, ACK bits to get us in a known state */ - STM32_I2C_CR1(port) &= ~(STM32_I2C_CR1_START | - STM32_I2C_CR1_STOP | - STM32_I2C_CR1_POS | - STM32_I2C_CR1_ACK); + STM32_I2C_CR1(port) &= ~(STM32_I2C_CR1_START | STM32_I2C_CR1_STOP | + STM32_I2C_CR1_POS | STM32_I2C_CR1_ACK); /* No out bytes and no in bytes means just check for active */ if (out_bytes || !in_bytes) { @@ -291,7 +285,7 @@ int chip_i2c_xfer(const int port, } } - xfer_exit: +xfer_exit: /* On error, queue a stop condition */ if (rv) { flags |= I2C_XFER_STOP; @@ -305,7 +299,8 @@ int chip_i2c_xfer(const int port, if (rv == I2C_ERROR_FAILED_START) { const struct i2c_port_t *p = i2c_ports; CPRINTS("chip_i2c_xfer start error; " - "unwedging and resetting i2c %d", port); + "unwedging and resetting i2c %d", + port); i2c_unwedge(port); @@ -363,7 +358,7 @@ int i2c_raw_get_sda(int port) int i2c_get_line_levels(int port) { return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) | - (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); + (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); } /*****************************************************************************/ @@ -414,11 +409,9 @@ void i2c_init(void) /*****************************************************************************/ /* Console commands */ -static int command_i2cdump(int argc, char **argv) +static int command_i2cdump(int argc, const char **argv) { dump_i2c_reg(I2C_PORT_MASTER, "dump"); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(i2cdump, command_i2cdump, - NULL, - "Dump I2C regs"); +DECLARE_CONSOLE_COMMAND(i2cdump, command_i2cdump, NULL, "Dump I2C regs"); diff --git a/chip/stm32/i2c-stm32l4.c b/chip/stm32/i2c-stm32l4.c index f7d311ba87..eeb87ec4e0 100644 --- a/chip/stm32/i2c-stm32l4.c +++ b/chip/stm32/i2c-stm32l4.c @@ -1,8 +1,9 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ +#include "builtin/assert.h" #include "printf.h" #include "chipset.h" #include "clock.h" @@ -21,13 +22,13 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) /* Transmit timeout in microseconds */ -#define I2C_TX_TIMEOUT_MASTER (10 * MSEC) +#define I2C_TX_TIMEOUT_MASTER (10 * MSEC) #ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS -#define I2C_SLAVE_ERROR_CODE 0xec +#define I2C_SLAVE_ERROR_CODE 0xec #if (I2C_PORT_EC == STM32_I2C1_PORT) #define IRQ_SLAVE STM32_IRQ_I2C1 #else @@ -37,8 +38,8 @@ /* I2C port state data */ struct i2c_port_data { - uint32_t timeout_us; /* Transaction timeout, or 0 to use default */ - enum i2c_freq freq; /* Port clock speed */ + uint32_t timeout_us; /* Transaction timeout, or 0 to use default */ + enum i2c_freq freq; /* Port clock speed */ }; static struct i2c_port_data pdata[I2C_PORT_COUNT]; @@ -50,8 +51,8 @@ void i2c_set_timeout(int port, uint32_t timeout) /* timing register values for supported input clks / i2c clk rates */ static const uint32_t busyloop_us[I2C_FREQ_COUNT] = { [I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */ - [I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */ - [I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */ + [I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */ + [I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */ }; /** @@ -70,7 +71,7 @@ static int wait_isr(int port, int mask) /* Check for errors */ if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR | - STM32_I2C_ISR_NACK)) + STM32_I2C_ISR_NACK)) return EC_ERROR_UNKNOWN; /* Check for desired mask */ @@ -115,8 +116,7 @@ static const uint32_t timingr_regs[I2C_CLK_SRC_COUNT][I2C_FREQ_COUNT] = { }; static void i2c_set_freq_port(const struct i2c_port_t *p, - enum stm32_i2c_clk_src src, - enum i2c_freq freq) + enum stm32_i2c_clk_src src, enum i2c_freq freq) { int port = p->port; @@ -209,8 +209,8 @@ static void i2c_event_handler(int port) STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE; /* Clear error status bits */ - STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF - | STM32_I2C_ICR_ARLOCF; + STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF | + STM32_I2C_ICR_ARLOCF; } /* Transfer matched our slave address */ @@ -286,8 +286,8 @@ static void i2c_event_handler(int port) STM32_I2C_TXDR(port) = slave_buffer[tx_idx++]; } else { - STM32_I2C_TXDR(port) - = I2C_SLAVE_ERROR_CODE; + STM32_I2C_TXDR(port) = + I2C_SLAVE_ERROR_CODE; tx_idx = 0; tx_end = 0; tx_pending = 0; @@ -309,9 +309,8 @@ DECLARE_IRQ(IRQ_SLAVE, i2c_event_interrupt, 2); /*****************************************************************************/ /* Interface */ -int chip_i2c_xfer(const int port, const uint16_t addr_flags, - const uint8_t *out, int out_bytes, - uint8_t *in, int in_bytes, int flags) +int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out, + int out_bytes, uint8_t *in, int in_bytes, int flags) { int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1; int rv = EC_SUCCESS; @@ -335,13 +334,13 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, * if we are not stopping, set RELOAD bit so that we can load * NBYTES again. if we are starting, then set START bit. */ - STM32_I2C_CR2(port) = ((out_bytes & 0xFF) << 16) - | addr_8bit - | ((in_bytes == 0 && xfer_stop) ? - STM32_I2C_CR2_AUTOEND : 0) - | ((in_bytes == 0 && !xfer_stop) ? - STM32_I2C_CR2_RELOAD : 0) - | (xfer_start ? STM32_I2C_CR2_START : 0); + STM32_I2C_CR2(port) = + ((out_bytes & 0xFF) << 16) | addr_8bit | + ((in_bytes == 0 && xfer_stop) ? STM32_I2C_CR2_AUTOEND : + 0) | + ((in_bytes == 0 && !xfer_stop) ? STM32_I2C_CR2_RELOAD : + 0) | + (xfer_start ? STM32_I2C_CR2_START : 0); for (i = 0; i < out_bytes; i++) { rv = wait_isr(port, STM32_I2C_ISR_TXIS); @@ -364,11 +363,11 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, * NBYTES again. if we were just transmitting, we need to * set START bit to send (re)start and begin read transaction. */ - STM32_I2C_CR2(port) = ((in_bytes & 0xFF) << 16) - | STM32_I2C_CR2_RD_WRN | addr_8bit - | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) - | (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) - | (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0); + STM32_I2C_CR2(port) = + ((in_bytes & 0xFF) << 16) | STM32_I2C_CR2_RD_WRN | + addr_8bit | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) | + (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) | + (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0); for (i = 0; i < in_bytes; i++) { /* Wait for receive buffer not empty */ @@ -448,7 +447,7 @@ int i2c_raw_get_sda(int port) int i2c_get_line_levels(int port) { return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) | - (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); + (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); } void i2c_init(void) @@ -460,11 +459,12 @@ void i2c_init(void) i2c_init_port(p); #ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS - STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE - | STM32_I2C_CR1_ADDRIE | STM32_I2C_CR1_STOPIE - | STM32_I2C_CR1_NACKIE; - STM32_I2C_OAR1(I2C_PORT_EC) = 0x8000 - | (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1); + STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE | + STM32_I2C_CR1_ADDRIE | + STM32_I2C_CR1_STOPIE | + STM32_I2C_CR1_NACKIE; + STM32_I2C_OAR1(I2C_PORT_EC) = + 0x8000 | (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1); task_enable_irq(IRQ_SLAVE); #endif } diff --git a/chip/stm32/i2c-stm32l5.c b/chip/stm32/i2c-stm32l5.c index 86cc1c6df2..3c7cb170bc 100644 --- a/chip/stm32/i2c-stm32l5.c +++ b/chip/stm32/i2c-stm32l5.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/stm32/i2c_ite_flash_support.c b/chip/stm32/i2c_ite_flash_support.c index 916a8c364c..8482065086 100644 --- a/chip/stm32/i2c_ite_flash_support.c +++ b/chip/stm32/i2c_ite_flash_support.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -33,10 +33,10 @@ * (1<<9)-6 reads, leaving 6012 bytes of RAM available, down from 7356 bytes of * RAM available with the default 60 byte limits. */ -#if CONFIG_USB_I2C_MAX_WRITE_COUNT != ((1<<9) - 4) +#if CONFIG_USB_I2C_MAX_WRITE_COUNT != ((1 << 9) - 4) #error Must set CONFIG_USB_I2C_MAX_WRITE_COUNT to ((1<<9) - 4) #endif -#if CONFIG_USB_I2C_MAX_READ_COUNT != ((1<<9) - 6) +#if CONFIG_USB_I2C_MAX_READ_COUNT != ((1 << 9) - 6) #error Must set CONFIG_USB_I2C_MAX_WRITE_COUNT to ((1<<9) - 6) #endif @@ -97,16 +97,15 @@ static int ite_i2c_read_register(uint8_t register_offset, uint8_t *output) int ret; /* Tell the ITE EC which register we want to read. */ ret = i2c_xfer_unlocked(ite_dfu_config.i2c_port, - ITE_DFU_I2C_CMD_ADDR_FLAGS, - ®ister_offset, sizeof(register_offset), - NULL, 0, I2C_XFER_SINGLE); + ITE_DFU_I2C_CMD_ADDR_FLAGS, ®ister_offset, + sizeof(register_offset), NULL, 0, + I2C_XFER_SINGLE); if (ret != EC_SUCCESS) return ret; /* Read in the 1 byte register value. */ ret = i2c_xfer_unlocked(ite_dfu_config.i2c_port, - ITE_DFU_I2C_DATA_ADDR_FLAGS, - NULL, 0, - output, sizeof(*output), I2C_XFER_SINGLE); + ITE_DFU_I2C_DATA_ADDR_FLAGS, NULL, 0, output, + sizeof(*output), I2C_XFER_SINGLE); return ret; } @@ -212,7 +211,7 @@ unlock: } ccprintf("ITE EC info: CHIPID1=0x%02X CHIPID2=0x%02X CHIPVER=0x%02X ", - chipid1[0], chipid2[0], chipver[0]); + chipid1[0], chipid2[0], chipver[0]); ccprintf("version=%d flash_bytes=%d\n", chip_version, flash_kb << 10); /* @@ -226,7 +225,7 @@ unlock: } /* Enable ITE direct firmware update (DFU) mode. */ -static int command_enable_ite_dfu(int argc, char **argv) +static int command_enable_ite_dfu(int argc, const char **argv) { if (argc > 1) return EC_ERROR_PARAM_COUNT; @@ -236,8 +235,8 @@ static int command_enable_ite_dfu(int argc, char **argv) return EC_ERROR_ACCESS_DENIED; /* Enable peripheral clocks. */ - STM32_RCC_APB2ENR |= - STM32_RCC_APB2ENR_TIM16EN | STM32_RCC_APB2ENR_TIM17EN; + STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_TIM16EN | + STM32_RCC_APB2ENR_TIM17EN; /* Reset timer registers which are not otherwise set below. */ STM32_TIM_CR2(16) = 0x0000; @@ -265,10 +264,10 @@ static int command_enable_ite_dfu(int argc, char **argv) STM32_TIM_ARR(17) = (MHz / SMDAT_WAVEFORM_PERIOD_HZ) - 1; /* Set output compare 1 mode to PWM mode 1 and enable preload. */ - STM32_TIM_CCMR1(16) = - STM32_TIM_CCMR1_OC1M_PWM_MODE_1 | STM32_TIM_CCMR1_OC1PE; - STM32_TIM_CCMR1(17) = - STM32_TIM_CCMR1_OC1M_PWM_MODE_1 | STM32_TIM_CCMR1_OC1PE; + STM32_TIM_CCMR1(16) = STM32_TIM_CCMR1_OC1M_PWM_MODE_1 | + STM32_TIM_CCMR1_OC1PE; + STM32_TIM_CCMR1(17) = STM32_TIM_CCMR1_OC1M_PWM_MODE_1 | + STM32_TIM_CCMR1_OC1PE; /* * Enable output compare 1 (or its N counterpart). Note that if only @@ -335,12 +334,11 @@ static int command_enable_ite_dfu(int argc, char **argv) return cprint_ite_chip_id(); } -DECLARE_CONSOLE_COMMAND( - enable_ite_dfu, command_enable_ite_dfu, "", - "Enable ITE Direct Firmware Update (DFU) mode"); +DECLARE_CONSOLE_COMMAND(enable_ite_dfu, command_enable_ite_dfu, "", + "Enable ITE Direct Firmware Update (DFU) mode"); /* Read ITE chip ID. Can be used to verify ITE DFU mode. */ -static int command_get_ite_chipid(int argc, char **argv) +static int command_get_ite_chipid(int argc, const char **argv) { if (argc > 1) return EC_ERROR_PARAM_COUNT; diff --git a/chip/stm32/keyboard_raw.c b/chip/stm32/keyboard_raw.c index 219676968a..c3244c19f7 100644 --- a/chip/stm32/keyboard_raw.c +++ b/chip/stm32/keyboard_raw.c @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -86,12 +86,12 @@ test_mockable void keyboard_raw_drive_column(int out) } } - #ifdef CONFIG_KEYBOARD_COL2_INVERTED +#ifdef CONFIG_KEYBOARD_COL2_INVERTED if (bsrr & (gpio_list[GPIO_KB_OUT02].mask << 16 | - gpio_list[GPIO_KB_OUT02].mask)) + gpio_list[GPIO_KB_OUT02].mask)) bsrr ^= (gpio_list[GPIO_KB_OUT02].mask << 16 | gpio_list[GPIO_KB_OUT02].mask); - #endif +#endif if (bsrr) STM32_GPIO_BSRR(kb_out_ports[i]) = bsrr; @@ -131,9 +131,9 @@ void keyboard_raw_enable_interrupt(int enable) * Clear them before enable interrupt. */ STM32_EXTI_PR |= irq_mask; - STM32_EXTI_IMR |= irq_mask; /* 1: unmask interrupt */ + STM32_EXTI_IMR |= irq_mask; /* 1: unmask interrupt */ } else { - STM32_EXTI_IMR &= ~irq_mask; /* 0: mask interrupts */ + STM32_EXTI_IMR &= ~irq_mask; /* 0: mask interrupts */ } } diff --git a/chip/stm32/memory_regions.inc b/chip/stm32/memory_regions.inc index 2381c511f2..8c8e666f71 100644 --- a/chip/stm32/memory_regions.inc +++ b/chip/stm32/memory_regions.inc @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/stm32/otp-stm32f4.c b/chip/stm32/otp-stm32f4.c index 45ce38d159..ff6280ed20 100644 --- a/chip/stm32/otp-stm32f4.c +++ b/chip/stm32/otp-stm32f4.c @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -18,8 +18,7 @@ #ifdef CONFIG_SERIALNO_LEN /* Which block to use */ #define OTP_SERIAL_BLOCK 0 -#define OTP_SERIAL_ADDR \ - REG32_ADDR(STM32_OTP_BLOCK_DATA(OTP_SERIAL_BLOCK, 0)) +#define OTP_SERIAL_ADDR REG32_ADDR(STM32_OTP_BLOCK_DATA(OTP_SERIAL_BLOCK, 0)) /* Number of word used in the block */ #define OTP_SERIAL_BLOCK_SIZE (CONFIG_SERIALNO_LEN / sizeof(uint32_t)) @@ -40,7 +39,7 @@ static int otp_write(uint8_t block, int size, const char *data) if (size >= STM32_OTP_BLOCK_SIZE) return EC_ERROR_PARAM2; return crec_flash_physical_write(STM32_OTP_BLOCK_DATA(block, 0) - - CONFIG_PROGRAM_MEMORY_BASE, + CONFIG_PROGRAM_MEMORY_BASE, size * sizeof(uint32_t), data); } @@ -74,7 +73,7 @@ static int otp_set_protect(uint8_t block) lock = REG32(STM32_OTP_LOCK(block)); lock &= ~STM32_OPT_LOCK_MASK(block); rv = crec_flash_physical_write(STM32_OTP_LOCK(block) - - CONFIG_PROGRAM_MEMORY_BASE, + CONFIG_PROGRAM_MEMORY_BASE, sizeof(uint32_t), (char *)&lock); if (rv) return rv; diff --git a/chip/stm32/power_led.c b/chip/stm32/power_led.c index 508745199f..579925fff9 100644 --- a/chip/stm32/power_led.c +++ b/chip/stm32/power_led.c @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -15,6 +15,7 @@ * results in a breathing effect. It takes about 2sec for a full cycle. */ +#include "builtin/assert.h" #include "clock.h" #include "console.h" #include "gpio.h" @@ -28,9 +29,9 @@ #include "timer.h" #include "util.h" -#define LED_STATE_TIMEOUT_MIN (15 * MSEC) /* Minimum of 15ms per step */ -#define LED_HOLD_TIME (330 * MSEC) /* Hold for 330ms at min/max */ -#define LED_STEP_PERCENT 4 /* Incremental value of each step */ +#define LED_STATE_TIMEOUT_MIN (15 * MSEC) /* Minimum of 15ms per step */ +#define LED_HOLD_TIME (330 * MSEC) /* Hold for 330ms at min/max */ +#define LED_STEP_PERCENT 4 /* Incremental value of each step */ static enum powerled_state led_state = POWERLED_STATE_ON; static int power_led_percent = 100; @@ -86,7 +87,8 @@ static int power_led_step(void) * Decreases timeout as duty cycle percentage approaches * 0%, increase as it approaches 100%. */ - state_timeout = LED_STATE_TIMEOUT_MIN + + state_timeout = + LED_STATE_TIMEOUT_MIN + LED_STATE_TIMEOUT_MIN * (power_led_percent / 33); } @@ -137,7 +139,7 @@ void power_led_task(void) #define CONFIG_CMD_POWERLED #ifdef CONFIG_CMD_POWERLED -static int command_powerled(int argc, char **argv) +static int command_powerled(int argc, const char **argv) { enum powerled_state state; @@ -156,7 +158,6 @@ static int command_powerled(int argc, char **argv) powerled_set_state(state); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(powerled, command_powerled, - "[off | on | suspend]", - "Change power LED state"); +DECLARE_CONSOLE_COMMAND(powerled, command_powerled, "[off | on | suspend]", + "Change power LED state"); #endif diff --git a/chip/stm32/pwm.c b/chip/stm32/pwm.c index aadbde08c2..0f2e50c999 100644 --- a/chip/stm32/pwm.c +++ b/chip/stm32/pwm.c @@ -1,10 +1,11 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* PWM control module for STM32 */ +#include "builtin/assert.h" #include "clock.h" #include "clock-f.h" #include "gpio.h" diff --git a/chip/stm32/pwm_chip.h b/chip/stm32/pwm_chip.h index baa793090a..7269072ac2 100644 --- a/chip/stm32/pwm_chip.h +++ b/chip/stm32/pwm_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -29,7 +29,10 @@ struct pwm_t { extern const struct pwm_t pwm_channels[]; /* Macro to fill in both timer ID and register base */ -#define STM32_TIM(x) {x, STM32_TIM_BASE(x)} +#define STM32_TIM(x) \ + { \ + x, STM32_TIM_BASE(x) \ + } /* Plain ID mapping for readability */ #define STM32_TIM_CH(x) (x) diff --git a/chip/stm32/registers-stm32f0.h b/chip/stm32/registers-stm32f0.h index ee4963777b..645ed5048e 100644 --- a/chip/stm32/registers-stm32f0.h +++ b/chip/stm32/registers-stm32f0.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -23,407 +23,402 @@ #endif /* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_RTC_WAKEUP 2 -#define STM32_IRQ_RTC_ALARM 2 -#define STM32_IRQ_FLASH 3 -#define STM32_IRQ_RCC 4 -#define STM32_IRQ_EXTI0_1 5 -#define STM32_IRQ_EXTI2_3 6 -#define STM32_IRQ_EXTI4_15 7 -#define STM32_IRQ_TSC 8 -#define STM32_IRQ_DMA_CHANNEL_1 9 +#define STM32_IRQ_WWDG 0 +#define STM32_IRQ_PVD 1 +#define STM32_IRQ_RTC_WAKEUP 2 +#define STM32_IRQ_RTC_ALARM 2 +#define STM32_IRQ_FLASH 3 +#define STM32_IRQ_RCC 4 +#define STM32_IRQ_EXTI0_1 5 +#define STM32_IRQ_EXTI2_3 6 +#define STM32_IRQ_EXTI4_15 7 +#define STM32_IRQ_TSC 8 +#define STM32_IRQ_DMA_CHANNEL_1 9 #define STM32_IRQ_DMA_CHANNEL_2_3 10 #define STM32_IRQ_DMA_CHANNEL_4_7 11 -#define STM32_IRQ_ADC_COMP 12 +#define STM32_IRQ_ADC_COMP 12 #define STM32_IRQ_TIM1_BRK_UP_TRG 13 -#define STM32_IRQ_TIM1_CC 14 -#define STM32_IRQ_TIM2 15 -#define STM32_IRQ_TIM3 16 -#define STM32_IRQ_TIM6_DAC 17 -#define STM32_IRQ_TIM7 18 -#define STM32_IRQ_TIM14 19 -#define STM32_IRQ_TIM15 20 -#define STM32_IRQ_TIM16 21 -#define STM32_IRQ_TIM17 22 -#define STM32_IRQ_I2C1 23 -#define STM32_IRQ_I2C2 24 -#define STM32_IRQ_SPI1 25 -#define STM32_IRQ_SPI2 26 -#define STM32_IRQ_USART1 27 -#define STM32_IRQ_USART2 28 -#define STM32_IRQ_USART3_4 29 -#define STM32_IRQ_CEC_CAN 30 -#define STM32_IRQ_USB 31 +#define STM32_IRQ_TIM1_CC 14 +#define STM32_IRQ_TIM2 15 +#define STM32_IRQ_TIM3 16 +#define STM32_IRQ_TIM6_DAC 17 +#define STM32_IRQ_TIM7 18 +#define STM32_IRQ_TIM14 19 +#define STM32_IRQ_TIM15 20 +#define STM32_IRQ_TIM16 21 +#define STM32_IRQ_TIM17 22 +#define STM32_IRQ_I2C1 23 +#define STM32_IRQ_I2C2 24 +#define STM32_IRQ_SPI1 25 +#define STM32_IRQ_SPI2 26 +#define STM32_IRQ_USART1 27 +#define STM32_IRQ_USART2 28 +#define STM32_IRQ_USART3_4 29 +#define STM32_IRQ_CEC_CAN 30 +#define STM32_IRQ_USB 31 /* aliases for easier code sharing */ #define STM32_IRQ_COMP STM32_IRQ_ADC_COMP #define STM32_IRQ_USB_LP STM32_IRQ_USB - - /* Peripheral base addresses */ -#define STM32_ADC1_BASE 0x40012400 -#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */ +#define STM32_ADC1_BASE 0x40012400 +#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */ -#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ -#define STM32_CRC_BASE 0x40023000 -#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ -#define STM32_DAC_BASE 0x40007400 +#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ +#define STM32_CRC_BASE 0x40023000 +#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ +#define STM32_DAC_BASE 0x40007400 -#define STM32_COMP_BASE 0x40010000 +#define STM32_COMP_BASE 0x40010000 -#define STM32_DBGMCU_BASE 0x40015800 +#define STM32_DBGMCU_BASE 0x40015800 -#define STM32_DMA1_BASE 0x40020000 -#define STM32_DMA2_BASE 0x40020400 +#define STM32_DMA1_BASE 0x40020000 +#define STM32_DMA2_BASE 0x40020400 -#define STM32_EXTI_BASE 0x40010400 +#define STM32_EXTI_BASE 0x40010400 -#define STM32_FLASH_REGS_BASE 0x40022000 +#define STM32_FLASH_REGS_BASE 0x40022000 -#define STM32_GPIOA_BASE 0x48000000 -#define STM32_GPIOB_BASE 0x48000400 -#define STM32_GPIOC_BASE 0x48000800 -#define STM32_GPIOD_BASE 0x48000C00 -#define STM32_GPIOE_BASE 0x48001000 -#define STM32_GPIOF_BASE 0x48001400 -#define STM32_GPIOG_BASE 0x48001800 /* only for stm32l4x6 */ -#define STM32_GPIOH_BASE 0x48001C00 /* only for stm32l4 */ +#define STM32_GPIOA_BASE 0x48000000 +#define STM32_GPIOB_BASE 0x48000400 +#define STM32_GPIOC_BASE 0x48000800 +#define STM32_GPIOD_BASE 0x48000C00 +#define STM32_GPIOE_BASE 0x48001000 +#define STM32_GPIOF_BASE 0x48001400 +#define STM32_GPIOG_BASE 0x48001800 /* only for stm32l4x6 */ +#define STM32_GPIOH_BASE 0x48001C00 /* only for stm32l4 */ -#define STM32_I2C1_BASE 0x40005400 -#define STM32_I2C2_BASE 0x40005800 -#define STM32_I2C3_BASE 0x40005C00 -#define STM32_I2C4_BASE 0x40006000 +#define STM32_I2C1_BASE 0x40005400 +#define STM32_I2C2_BASE 0x40005800 +#define STM32_I2C3_BASE 0x40005C00 +#define STM32_I2C4_BASE 0x40006000 -#define STM32_IWDG_BASE 0x40003000 -#define STM32_LCD_BASE 0x40002400 +#define STM32_IWDG_BASE 0x40003000 +#define STM32_LCD_BASE 0x40002400 -#define STM32_OPTB_BASE 0x1FFFF800 +#define STM32_OPTB_BASE 0x1FFFF800 -#define STM32_PMSE_BASE 0x40013400 -#define STM32_PWR_BASE 0x40007000 +#define STM32_PMSE_BASE 0x40013400 +#define STM32_PWR_BASE 0x40007000 -#define STM32_RCC_BASE 0x40021000 +#define STM32_RCC_BASE 0x40021000 -#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ -#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ -#define STM32_RTC_BASE 0x40002800 +#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ +#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ +#define STM32_RTC_BASE 0x40002800 -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ +#define STM32_SPI1_BASE 0x40013000 +#define STM32_SPI2_BASE 0x40003800 +#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ -#define STM32_SYSCFG_BASE 0x40010000 +#define STM32_SYSCFG_BASE 0x40010000 -#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ -#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ -#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 -#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ -#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ +#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ +#define STM32_TIM2_BASE 0x40000000 +#define STM32_TIM3_BASE 0x40000400 +#define STM32_TIM4_BASE 0x40000800 +#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ +#define STM32_TIM6_BASE 0x40001000 +#define STM32_TIM7_BASE 0x40001400 +#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ +#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ +#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ +#define STM32_TIM15_BASE 0x40014000 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ +#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ -#define STM32_UNIQUE_ID_BASE 0x1ffff7ac +#define STM32_UNIQUE_ID_BASE 0x1ffff7ac -#define STM32_USART1_BASE 0x40013800 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART9_BASE 0x40008000 /* LPUART */ +#define STM32_USART1_BASE 0x40013800 +#define STM32_USART2_BASE 0x40004400 +#define STM32_USART3_BASE 0x40004800 +#define STM32_USART4_BASE 0x40004c00 +#define STM32_USART9_BASE 0x40008000 /* LPUART */ -#define STM32_USB_CAN_SRAM_BASE 0x40006000 -#define STM32_USB_FS_BASE 0x40005C00 - -#define STM32_WWDG_BASE 0x40002C00 +#define STM32_USB_CAN_SRAM_BASE 0x40006000 +#define STM32_USB_FS_BASE 0x40005C00 +#define STM32_WWDG_BASE 0x40002C00 #ifndef __ASSEMBLER__ /* Register definitions */ /* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_UESM BIT(1) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR2_SWAP BIT(15) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) -#define STM32_USART_CR3_OVRDIS BIT(12) -#define STM32_USART_CR3_WUS_START_BIT (2 << 20) -#define STM32_USART_CR3_WUFIE BIT(22) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) -#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) -#define STM32_USART_ICR_ORECF BIT(3) -#define STM32_USART_ICR_TCCF BIT(6) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) -#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) +#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) +#define STM32_USART_CR1_UE BIT(0) +#define STM32_USART_CR1_UESM BIT(1) +#define STM32_USART_CR1_RE BIT(2) +#define STM32_USART_CR1_TE BIT(3) +#define STM32_USART_CR1_RXNEIE BIT(5) +#define STM32_USART_CR1_TCIE BIT(6) +#define STM32_USART_CR1_TXEIE BIT(7) +#define STM32_USART_CR1_PS BIT(9) +#define STM32_USART_CR1_PCE BIT(10) +#define STM32_USART_CR1_M BIT(12) +#define STM32_USART_CR1_OVER8 BIT(15) +#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) +#define STM32_USART_CR2_SWAP BIT(15) +#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) +#define STM32_USART_CR3_EIE BIT(0) +#define STM32_USART_CR3_DMAR BIT(6) +#define STM32_USART_CR3_DMAT BIT(7) +#define STM32_USART_CR3_ONEBIT BIT(11) +#define STM32_USART_CR3_OVRDIS BIT(12) +#define STM32_USART_CR3_WUS_START_BIT (2 << 20) +#define STM32_USART_CR3_WUFIE BIT(22) +#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) +#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) +#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) +#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) +#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) +#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) +#define STM32_USART_ICR_ORECF BIT(3) +#define STM32_USART_ICR_TCCF BIT(6) +#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) +#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) +#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) /* register alias */ -#define STM32_USART_SR(base) STM32_USART_ISR(base) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) +#define STM32_USART_SR(base) STM32_USART_ISR(base) +#define STM32_USART_SR_ORE BIT(3) +#define STM32_USART_SR_RXNE BIT(5) +#define STM32_USART_SR_TC BIT(6) +#define STM32_USART_SR_TXE BIT(7) /* --- GPIO --- */ -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) -#define STM32_GPIO_BRR(b) REG32((b) + 0x28) -#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4 */ - -#define GPIO_ALT_F0 0x0 -#define GPIO_ALT_F1 0x1 -#define GPIO_ALT_F2 0x2 -#define GPIO_ALT_F3 0x3 -#define GPIO_ALT_F4 0x4 -#define GPIO_ALT_F5 0x5 -#define GPIO_ALT_F6 0x6 -#define GPIO_ALT_F7 0x7 -#define GPIO_ALT_F8 0x8 -#define GPIO_ALT_F9 0x9 -#define GPIO_ALT_FA 0xA -#define GPIO_ALT_FB 0xB -#define GPIO_ALT_FC 0xC -#define GPIO_ALT_FD 0xD -#define GPIO_ALT_FE 0xE -#define GPIO_ALT_FF 0xF +#define STM32_GPIO_MODER(b) REG32((b) + 0x00) +#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) +#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) +#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) +#define STM32_GPIO_IDR(b) REG16((b) + 0x10) +#define STM32_GPIO_ODR(b) REG16((b) + 0x14) +#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) +#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) +#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) +#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) +#define STM32_GPIO_BRR(b) REG32((b) + 0x28) +#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4 */ + +#define GPIO_ALT_F0 0x0 +#define GPIO_ALT_F1 0x1 +#define GPIO_ALT_F2 0x2 +#define GPIO_ALT_F3 0x3 +#define GPIO_ALT_F4 0x4 +#define GPIO_ALT_F5 0x5 +#define GPIO_ALT_F6 0x6 +#define GPIO_ALT_F7 0x7 +#define GPIO_ALT_F8 0x8 +#define GPIO_ALT_F9 0x9 +#define GPIO_ALT_FA 0xA +#define GPIO_ALT_FB 0xB +#define GPIO_ALT_FC 0xC +#define GPIO_ALT_FD 0xD +#define GPIO_ALT_FE 0xE +#define GPIO_ALT_FF 0xF /* --- I2C --- */ -#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_TXIE BIT(1) -#define STM32_I2C_CR1_RXIE BIT(2) -#define STM32_I2C_CR1_ADDRIE BIT(3) -#define STM32_I2C_CR1_NACKIE BIT(4) -#define STM32_I2C_CR1_STOPIE BIT(5) -#define STM32_I2C_CR1_ERRIE BIT(7) -#define STM32_I2C_CR1_WUPEN BIT(18) -#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_RD_WRN BIT(10) -#define STM32_I2C_CR2_START BIT(13) -#define STM32_I2C_CR2_STOP BIT(14) -#define STM32_I2C_CR2_NACK BIT(15) -#define STM32_I2C_CR2_RELOAD BIT(24) -#define STM32_I2C_CR2_AUTOEND BIT(25) -#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_ISR_TXE BIT(0) -#define STM32_I2C_ISR_TXIS BIT(1) -#define STM32_I2C_ISR_RXNE BIT(2) -#define STM32_I2C_ISR_ADDR BIT(3) -#define STM32_I2C_ISR_NACK BIT(4) -#define STM32_I2C_ISR_STOP BIT(5) -#define STM32_I2C_ISR_TC BIT(6) -#define STM32_I2C_ISR_TCR BIT(7) -#define STM32_I2C_ISR_BERR BIT(8) -#define STM32_I2C_ISR_ARLO BIT(9) -#define STM32_I2C_ISR_OVR BIT(10) -#define STM32_I2C_ISR_PECERR BIT(11) -#define STM32_I2C_ISR_TIMEOUT BIT(12) -#define STM32_I2C_ISR_ALERT BIT(13) -#define STM32_I2C_ISR_BUSY BIT(15) -#define STM32_I2C_ISR_DIR BIT(16) -#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe) -#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_ICR_ADDRCF BIT(3) -#define STM32_I2C_ICR_NACKCF BIT(4) -#define STM32_I2C_ICR_STOPCF BIT(5) -#define STM32_I2C_ICR_BERRCF BIT(8) -#define STM32_I2C_ICR_ARLOCF BIT(9) -#define STM32_I2C_ICR_OVRCF BIT(10) -#define STM32_I2C_ICR_TIMEOUTCF BIT(12) -#define STM32_I2C_ICR_ALL 0x3F38 -#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) -#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) -#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) - +#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) +#define STM32_I2C_CR1_PE BIT(0) +#define STM32_I2C_CR1_TXIE BIT(1) +#define STM32_I2C_CR1_RXIE BIT(2) +#define STM32_I2C_CR1_ADDRIE BIT(3) +#define STM32_I2C_CR1_NACKIE BIT(4) +#define STM32_I2C_CR1_STOPIE BIT(5) +#define STM32_I2C_CR1_ERRIE BIT(7) +#define STM32_I2C_CR1_WUPEN BIT(18) +#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) +#define STM32_I2C_CR2_RD_WRN BIT(10) +#define STM32_I2C_CR2_START BIT(13) +#define STM32_I2C_CR2_STOP BIT(14) +#define STM32_I2C_CR2_NACK BIT(15) +#define STM32_I2C_CR2_RELOAD BIT(24) +#define STM32_I2C_CR2_AUTOEND BIT(25) +#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) +#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) +#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) +#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) +#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) +#define STM32_I2C_ISR_TXE BIT(0) +#define STM32_I2C_ISR_TXIS BIT(1) +#define STM32_I2C_ISR_RXNE BIT(2) +#define STM32_I2C_ISR_ADDR BIT(3) +#define STM32_I2C_ISR_NACK BIT(4) +#define STM32_I2C_ISR_STOP BIT(5) +#define STM32_I2C_ISR_TC BIT(6) +#define STM32_I2C_ISR_TCR BIT(7) +#define STM32_I2C_ISR_BERR BIT(8) +#define STM32_I2C_ISR_ARLO BIT(9) +#define STM32_I2C_ISR_OVR BIT(10) +#define STM32_I2C_ISR_PECERR BIT(11) +#define STM32_I2C_ISR_TIMEOUT BIT(12) +#define STM32_I2C_ISR_ALERT BIT(13) +#define STM32_I2C_ISR_BUSY BIT(15) +#define STM32_I2C_ISR_DIR BIT(16) +#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe) +#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) +#define STM32_I2C_ICR_ADDRCF BIT(3) +#define STM32_I2C_ICR_NACKCF BIT(4) +#define STM32_I2C_ICR_STOPCF BIT(5) +#define STM32_I2C_ICR_BERRCF BIT(8) +#define STM32_I2C_ICR_ARLOCF BIT(9) +#define STM32_I2C_ICR_OVRCF BIT(10) +#define STM32_I2C_ICR_TIMEOUTCF BIT(12) +#define STM32_I2C_ICR_ALL 0x3F38 +#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) +#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) +#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) /* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CR REG32(STM32_PWR_BASE + 0x00) -#define STM32_PWD_PVD_LS_MASK (0x07 << 5) -#define STM32_PWD_PVD_LS(n) ((n & 0x07) << 5) -#define STM32_PWR_PVDE BIT(4) - -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) - -#define STM32_PWR_CSR_EWUP1 BIT(8) -#define STM32_PWR_CSR_EWUP2 BIT(9) -#define STM32_PWR_CSR_EWUP3 BIT(10) -#define STM32_PWR_CSR_EWUP4 BIT(11) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP5 BIT(12) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP6 BIT(13) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP7 BIT(14) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP8 BIT(15) /* STM32F0xx only */ - -#define STM32_CRS_CR REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */ -#define STM32_CRS_CR_SYNCOKIE BIT(0) -#define STM32_CRS_CR_SYNCWARNIE BIT(1) -#define STM32_CRS_CR_ERRIE BIT(2) -#define STM32_CRS_CR_ESYNCIE BIT(3) -#define STM32_CRS_CR_CEN BIT(5) -#define STM32_CRS_CR_AUTOTRIMEN BIT(6) -#define STM32_CRS_CR_SWSYNC BIT(7) -#define STM32_CRS_CR_TRIM(n) (((n) & 0x3f) << 8) - -#define STM32_CRS_CFGR REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */ -#define STM32_CRS_CFGR_RELOAD(n) (((n) & 0xffff) << 0) -#define STM32_CRS_CFGR_FELIM(n) (((n) & 0xff) << 16) -#define STM32_CRS_CFGR_SYNCDIV(n) (((n) & 7) << 24) -#define STM32_CRS_CFGR_SYNCSRC(n) (((n) & 3) << 28) -#define STM32_CRS_CFGR_SYNCPOL BIT(31) - -#define STM32_CRS_ISR REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */ -#define STM32_CRS_ISR_SYNCOKF BIT(0) -#define STM32_CRS_ISR_SYNCWARNF BIT(1) -#define STM32_CRS_ISR_ERRF BIT(2) -#define STM32_CRS_ISR_ESYNCF BIT(3) -#define STM32_CRS_ISR_SYNCERR BIT(8) -#define STM32_CRS_ISR_SYNCMISS BIT(9) -#define STM32_CRS_ISR_TRIMOVF BIT(10) -#define STM32_CRS_ISR_FEDIR BIT(15) -#define STM32_CRS_ISR_FECAP (0xffff << 16) - -#define STM32_CRS_ICR REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */ -#define STM32_CRS_ICR_SYNCOKC BIT(0) -#define STM32_CRS_ICR_SYNCWARINC BIT(1) -#define STM32_CRS_ICR_ERRC BIT(2) -#define STM32_CRS_ICR_ESYNCC BIT(3) - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x04) -#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x0c) -#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x10) -#define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x18) -#define STM32_RCC_APB2ENR_ADCEN BIT(9) /* STM32F3/F0 */ -#define STM32_RCC_APB2ENR_TIM16EN BIT(17) -#define STM32_RCC_APB2ENR_TIM17EN BIT(18) -#define STM32_RCC_DBGMCUEN BIT(22) -#define STM32_RCC_SYSCFGEN BIT(0) - -#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x1c) -#define STM32_RCC_DACEN BIT(29) -#define STM32_RCC_PWREN BIT(28) - -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x24) +#define STM32_PWR_CR REG32(STM32_PWR_BASE + 0x00) +#define STM32_PWD_PVD_LS_MASK (0x07 << 5) +#define STM32_PWD_PVD_LS(n) ((n & 0x07) << 5) +#define STM32_PWR_PVDE BIT(4) + +#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) + +#define STM32_PWR_CSR_EWUP1 BIT(8) +#define STM32_PWR_CSR_EWUP2 BIT(9) +#define STM32_PWR_CSR_EWUP3 BIT(10) +#define STM32_PWR_CSR_EWUP4 BIT(11) /* STM32F0xx only */ +#define STM32_PWR_CSR_EWUP5 BIT(12) /* STM32F0xx only */ +#define STM32_PWR_CSR_EWUP6 BIT(13) /* STM32F0xx only */ +#define STM32_PWR_CSR_EWUP7 BIT(14) /* STM32F0xx only */ +#define STM32_PWR_CSR_EWUP8 BIT(15) /* STM32F0xx only */ + +#define STM32_CRS_CR REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */ +#define STM32_CRS_CR_SYNCOKIE BIT(0) +#define STM32_CRS_CR_SYNCWARNIE BIT(1) +#define STM32_CRS_CR_ERRIE BIT(2) +#define STM32_CRS_CR_ESYNCIE BIT(3) +#define STM32_CRS_CR_CEN BIT(5) +#define STM32_CRS_CR_AUTOTRIMEN BIT(6) +#define STM32_CRS_CR_SWSYNC BIT(7) +#define STM32_CRS_CR_TRIM(n) (((n)&0x3f) << 8) + +#define STM32_CRS_CFGR REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */ +#define STM32_CRS_CFGR_RELOAD(n) (((n)&0xffff) << 0) +#define STM32_CRS_CFGR_FELIM(n) (((n)&0xff) << 16) +#define STM32_CRS_CFGR_SYNCDIV(n) (((n)&7) << 24) +#define STM32_CRS_CFGR_SYNCSRC(n) (((n)&3) << 28) +#define STM32_CRS_CFGR_SYNCPOL BIT(31) + +#define STM32_CRS_ISR REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */ +#define STM32_CRS_ISR_SYNCOKF BIT(0) +#define STM32_CRS_ISR_SYNCWARNF BIT(1) +#define STM32_CRS_ISR_ERRF BIT(2) +#define STM32_CRS_ISR_ESYNCF BIT(3) +#define STM32_CRS_ISR_SYNCERR BIT(8) +#define STM32_CRS_ISR_SYNCMISS BIT(9) +#define STM32_CRS_ISR_TRIMOVF BIT(10) +#define STM32_CRS_ISR_FEDIR BIT(15) +#define STM32_CRS_ISR_FECAP (0xffff << 16) + +#define STM32_CRS_ICR REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */ +#define STM32_CRS_ICR_SYNCOKC BIT(0) +#define STM32_CRS_ICR_SYNCWARINC BIT(1) +#define STM32_CRS_ICR_ERRC BIT(2) +#define STM32_CRS_ICR_ESYNCC BIT(3) + +#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) +#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x04) +#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x08) +#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x0c) +#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x10) +#define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x14) +#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x18) +#define STM32_RCC_APB2ENR_ADCEN BIT(9) /* STM32F3/F0 */ +#define STM32_RCC_APB2ENR_TIM16EN BIT(17) +#define STM32_RCC_APB2ENR_TIM17EN BIT(18) +#define STM32_RCC_DBGMCUEN BIT(22) +#define STM32_RCC_SYSCFGEN BIT(0) + +#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x1c) +#define STM32_RCC_DACEN BIT(29) +#define STM32_RCC_PWREN BIT(28) + +#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x20) +#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x24) /* STM32F373 */ -#define STM32_RCC_CFGR2 REG32(STM32_RCC_BASE + 0x2c) +#define STM32_RCC_CFGR2 REG32(STM32_RCC_BASE + 0x2c) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_CFGR3 REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_CR2 REG32(STM32_RCC_BASE + 0x34) /* STM32F0XX */ +#define STM32_RCC_CFGR3 REG32(STM32_RCC_BASE + 0x30) +#define STM32_RCC_CR2 REG32(STM32_RCC_BASE + 0x34) /* STM32F0XX */ -#define STM32_RCC_HB_DMA1 BIT(0) +#define STM32_RCC_HB_DMA1 BIT(0) /* STM32F373 */ -#define STM32_RCC_HB_DMA2 BIT(1) -#define STM32_RCC_PB2_TIM1 BIT(11) /* Except STM32F373 */ -#define STM32_RCC_PB2_TIM15 BIT(16) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM16 BIT(17) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM17 BIT(18) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM19 BIT(19) /* STM32F373 */ -#define STM32_RCC_PB2_PMAD BIT(11) /* STM32TS */ -#define STM32_RCC_PB2_PMSE BIT(13) /* STM32TS */ -#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32F373 */ -#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32F373 */ -#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB1_TIM18 BIT(9) /* STM32F373 */ -#define STM32_RCC_PB1_USB BIT(23) -#define STM32_RCC_PB1_CRS BIT(27) - -#define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x00) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) -#define STM32_SYSCFG_CFGR2 REG32(STM32_SYSCFG_BASE + 0x18) - +#define STM32_RCC_HB_DMA2 BIT(1) +#define STM32_RCC_PB2_TIM1 BIT(11) /* Except STM32F373 */ +#define STM32_RCC_PB2_TIM15 BIT(16) /* STM32F0XX and STM32F373 */ +#define STM32_RCC_PB2_TIM16 BIT(17) /* STM32F0XX and STM32F373 */ +#define STM32_RCC_PB2_TIM17 BIT(18) /* STM32F0XX and STM32F373 */ +#define STM32_RCC_PB2_TIM19 BIT(19) /* STM32F373 */ +#define STM32_RCC_PB2_PMAD BIT(11) /* STM32TS */ +#define STM32_RCC_PB2_PMSE BIT(13) /* STM32TS */ +#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32F373 */ +#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32F373 */ +#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32F0XX and STM32F373 */ +#define STM32_RCC_PB1_TIM18 BIT(9) /* STM32F373 */ +#define STM32_RCC_PB1_USB BIT(23) +#define STM32_RCC_PB1_CRS BIT(27) + +#define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x00) +#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) +#define STM32_SYSCFG_CFGR2 REG32(STM32_SYSCFG_BASE + 0x18) /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB2_USART1 BIT(14) +#define STM32_RCC_PB2_USART1 BIT(14) /* Reset causes definitions */ /* Reset causes in RCC CSR register */ #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG 0x60000000 -#define RESET_CAUSE_SFT 0x10000000 -#define RESET_CAUSE_POR 0x08000000 -#define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xfe000000 -#define RESET_CAUSE_RMVF 0x01000000 +#define RESET_CAUSE_WDG 0x60000000 +#define RESET_CAUSE_SFT 0x10000000 +#define RESET_CAUSE_POR 0x08000000 +#define RESET_CAUSE_PIN 0x04000000 +#define RESET_CAUSE_OTHER 0xfe000000 +#define RESET_CAUSE_RMVF 0x01000000 /* Power cause in PWR CSR register */ -#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR -#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR -#define RESET_CAUSE_SBF 0x00000002 -#define RESET_CAUSE_SBF_CLR 0x00000004 +#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR +#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR +#define RESET_CAUSE_SBF 0x00000002 +#define RESET_CAUSE_SBF_CLR 0x00000004 /* --- Watchdogs --- */ /* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 20 +#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) +#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) +#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) +#define STM32_RTC_CR_BYPSHAD BIT(5) +#define STM32_RTC_CR_ALRAE BIT(8) +#define STM32_RTC_CR_ALRAIE BIT(12) +#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) +#define STM32_RTC_ISR_ALRAWF BIT(0) +#define STM32_RTC_ISR_RSF BIT(5) +#define STM32_RTC_ISR_INITF BIT(6) +#define STM32_RTC_ISR_INIT BIT(7) +#define STM32_RTC_ISR_ALRAF BIT(8) +#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) +#define STM32_RTC_PRER_A_MASK (0x7f << 16) +#define STM32_RTC_PRER_S_MASK (0x7fff << 0) +#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) +#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) +#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) +#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) +#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) +#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) +#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) +#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) +#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) +#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) +#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) + +#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) +#define STM32_BKP_BYTES 20 /* --- SPI --- */ @@ -440,8 +435,8 @@ struct stm32_spi_regs { unsigned crcpr; unsigned rxcrcr; unsigned txcrcr; - unsigned i2scfgr; /* STM32L only */ - unsigned i2spr; /* STM32L only */ + unsigned i2scfgr; /* STM32L only */ + unsigned i2spr; /* STM32L only */ }; /* Must be volatile, or compiler optimizes out repeated accesses */ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; @@ -451,155 +446,154 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) +#define STM32_SPI_CR1_BIDIMODE BIT(15) +#define STM32_SPI_CR1_BIDIOE BIT(14) +#define STM32_SPI_CR1_CRCEN BIT(13) +#define STM32_SPI_CR1_SSM BIT(9) +#define STM32_SPI_CR1_SSI BIT(8) +#define STM32_SPI_CR1_LSBFIRST BIT(7) +#define STM32_SPI_CR1_SPE BIT(6) +#define STM32_SPI_CR1_BR_DIV64R (5 << 3) +#define STM32_SPI_CR1_BR_DIV4R BIT(3) +#define STM32_SPI_CR1_MSTR BIT(2) +#define STM32_SPI_CR1_CPOL BIT(1) +#define STM32_SPI_CR1_CPHA BIT(0) +#define STM32_SPI_CR2_FRXTH BIT(12) +#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8) +#define STM32_SPI_CR2_TXEIE BIT(7) +#define STM32_SPI_CR2_RXNEIE BIT(6) +#define STM32_SPI_CR2_NSSP BIT(3) +#define STM32_SPI_CR2_SSOE BIT(2) +#define STM32_SPI_CR2_TXDMAEN BIT(1) +#define STM32_SPI_CR2_RXDMAEN BIT(0) + +#define STM32_SPI_SR_RXNE BIT(0) +#define STM32_SPI_SR_TXE BIT(1) +#define STM32_SPI_SR_CRCERR BIT(4) +#define STM32_SPI_SR_BSY BIT(7) +#define STM32_SPI_SR_FRLVL (3 << 9) +#define STM32_SPI_SR_FTLVL (3 << 11) /* --- Debug --- */ -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) +#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) +#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) /* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) +#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) #define STM32_FLASH_ACR_LATENCY_SHIFT (0) -#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) -#define STM32_FLASH_ACR_LATENCY BIT(0) -#define STM32_FLASH_ACR_PRFTEN BIT(4) -#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB - -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define FLASH_OPTKEYR_KEY1 FLASH_KEYR_KEY1 -#define FLASH_OPTKEYR_KEY2 FLASH_KEYR_KEY2 -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define FLASH_SR_BUSY BIT(0) -#define FLASH_SR_PGERR BIT(2) -#define FLASH_SR_WRPRTERR BIT(4) -#define FLASH_SR_ALL_ERR \ - (FLASH_SR_PGERR | FLASH_SR_WRPRTERR) -#define FLASH_SR_EOP BIT(5) -#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_OPTPG BIT(4) -#define FLASH_CR_OPTER BIT(5) -#define FLASH_CR_STRT BIT(6) -#define FLASH_CR_LOCK BIT(7) -#define FLASH_CR_OPTWRE BIT(9) -#define FLASH_CR_OBL_LAUNCH BIT(13) -#define STM32_FLASH_OPT_LOCKED (!(STM32_FLASH_CR & FLASH_CR_OPTWRE)) -#define STM32_FLASH_AR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c) -#define STM32_FLASH_OBR_RDP_MASK (3 << 1) -#define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20) - -#define STM32_OPTB_RDP_OFF 0x00 -#define STM32_OPTB_USER_OFF 0x02 -#define STM32_OPTB_WRP_OFF(n) (0x08 + (n&3) * 2) -#define STM32_OPTB_WRP01 0x08 -#define STM32_OPTB_WRP23 0x0c - -#define STM32_OPTB_COMPL_SHIFT 8 +#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) +#define STM32_FLASH_ACR_LATENCY BIT(0) +#define STM32_FLASH_ACR_PRFTEN BIT(4) +#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) +#define FLASH_KEYR_KEY1 0x45670123 +#define FLASH_KEYR_KEY2 0xCDEF89AB + +#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) +#define FLASH_OPTKEYR_KEY1 FLASH_KEYR_KEY1 +#define FLASH_OPTKEYR_KEY2 FLASH_KEYR_KEY2 +#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) +#define FLASH_SR_BUSY BIT(0) +#define FLASH_SR_PGERR BIT(2) +#define FLASH_SR_WRPRTERR BIT(4) +#define FLASH_SR_ALL_ERR (FLASH_SR_PGERR | FLASH_SR_WRPRTERR) +#define FLASH_SR_EOP BIT(5) +#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) +#define FLASH_CR_PG BIT(0) +#define FLASH_CR_PER BIT(1) +#define FLASH_CR_OPTPG BIT(4) +#define FLASH_CR_OPTER BIT(5) +#define FLASH_CR_STRT BIT(6) +#define FLASH_CR_LOCK BIT(7) +#define FLASH_CR_OPTWRE BIT(9) +#define FLASH_CR_OBL_LAUNCH BIT(13) +#define STM32_FLASH_OPT_LOCKED (!(STM32_FLASH_CR & FLASH_CR_OPTWRE)) +#define STM32_FLASH_AR REG32(STM32_FLASH_REGS_BASE + 0x14) +#define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c) +#define STM32_FLASH_OBR_RDP_MASK (3 << 1) +#define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20) + +#define STM32_OPTB_RDP_OFF 0x00 +#define STM32_OPTB_USER_OFF 0x02 +#define STM32_OPTB_WRP_OFF(n) (0x08 + (n & 3) * 2) +#define STM32_OPTB_WRP01 0x08 +#define STM32_OPTB_WRP23 0x0c + +#define STM32_OPTB_COMPL_SHIFT 8 /* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) +#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) +#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) +#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) +#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) +#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) +#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) -#define EXTI_PVD_EVENT BIT(16) -#define EXTI_RTC_ALR_EVENT BIT(17) -#define EXTI_COMP2_EVENT BIT(22) +#define EXTI_PVD_EVENT BIT(16) +#define EXTI_RTC_ALR_EVENT BIT(17) +#define EXTI_COMP2_EVENT BIT(22) /* --- ADC --- */ -#define STM32_ADC_ISR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC_ISR_ADRDY BIT(0) -#define STM32_ADC_IER REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC_IER_AWDIE BIT(7) -#define STM32_ADC_IER_OVRIE BIT(4) -#define STM32_ADC_IER_EOSEQIE BIT(3) -#define STM32_ADC_IER_EOCIE BIT(2) -#define STM32_ADC_IER_EOSMPIE BIT(1) -#define STM32_ADC_IER_ADRDYIE BIT(0) - -#define STM32_ADC_CR REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC_CR_ADEN BIT(0) -#define STM32_ADC_CR_ADDIS BIT(1) -#define STM32_ADC_CR_ADCAL BIT(31) -#define STM32_ADC_CFGR1 REG32(STM32_ADC1_BASE + 0x0C) +#define STM32_ADC_ISR REG32(STM32_ADC1_BASE + 0x00) +#define STM32_ADC_ISR_ADRDY BIT(0) +#define STM32_ADC_IER REG32(STM32_ADC1_BASE + 0x04) +#define STM32_ADC_IER_AWDIE BIT(7) +#define STM32_ADC_IER_OVRIE BIT(4) +#define STM32_ADC_IER_EOSEQIE BIT(3) +#define STM32_ADC_IER_EOCIE BIT(2) +#define STM32_ADC_IER_EOSMPIE BIT(1) +#define STM32_ADC_IER_ADRDYIE BIT(0) + +#define STM32_ADC_CR REG32(STM32_ADC1_BASE + 0x08) +#define STM32_ADC_CR_ADEN BIT(0) +#define STM32_ADC_CR_ADDIS BIT(1) +#define STM32_ADC_CR_ADCAL BIT(31) +#define STM32_ADC_CFGR1 REG32(STM32_ADC1_BASE + 0x0C) /* Analog watchdog channel selection */ #define STM32_ADC_CFGR1_AWDCH_MASK (0x1f << 26) -#define STM32_ADC_CFGR1_AWDEN BIT(23) -#define STM32_ADC_CFGR1_AWDSGL BIT(22) +#define STM32_ADC_CFGR1_AWDEN BIT(23) +#define STM32_ADC_CFGR1_AWDSGL BIT(22) /* Selects single vs continuous */ -#define STM32_ADC_CFGR1_CONT BIT(13) +#define STM32_ADC_CFGR1_CONT BIT(13) /* Selects ADC_DR overwrite vs preserve */ -#define STM32_ADC_CFGR1_OVRMOD BIT(12) +#define STM32_ADC_CFGR1_OVRMOD BIT(12) /* External trigger polarity selection */ -#define STM32_ADC_CFGR1_EXTEN_DIS (0 << 10) +#define STM32_ADC_CFGR1_EXTEN_DIS (0 << 10) #define STM32_ADC_CFGR1_EXTEN_RISE (1 << 10) #define STM32_ADC_CFGR1_EXTEN_FALL (2 << 10) #define STM32_ADC_CFGR1_EXTEN_BOTH (3 << 10) #define STM32_ADC_CFGR1_EXTEN_MASK (3 << 10) /* External trigger selection */ -#define STM32_ADC_CFGR1_TRG0 (0 << 6) -#define STM32_ADC_CFGR1_TRG1 (1 << 6) -#define STM32_ADC_CFGR1_TRG2 (2 << 6) -#define STM32_ADC_CFGR1_TRG3 (3 << 6) -#define STM32_ADC_CFGR1_TRG4 (4 << 6) -#define STM32_ADC_CFGR1_TRG5 (5 << 6) -#define STM32_ADC_CFGR1_TRG6 (6 << 6) -#define STM32_ADC_CFGR1_TRG7 (7 << 6) -#define STM32_ADC_CFGR1_TRG_MASK (7 << 6) +#define STM32_ADC_CFGR1_TRG0 (0 << 6) +#define STM32_ADC_CFGR1_TRG1 (1 << 6) +#define STM32_ADC_CFGR1_TRG2 (2 << 6) +#define STM32_ADC_CFGR1_TRG3 (3 << 6) +#define STM32_ADC_CFGR1_TRG4 (4 << 6) +#define STM32_ADC_CFGR1_TRG5 (5 << 6) +#define STM32_ADC_CFGR1_TRG6 (6 << 6) +#define STM32_ADC_CFGR1_TRG7 (7 << 6) +#define STM32_ADC_CFGR1_TRG_MASK (7 << 6) /* Selects circular vs one-shot */ -#define STM32_ADC_CFGR1_DMACFG BIT(1) -#define STM32_ADC_CFGR1_DMAEN BIT(0) -#define STM32_ADC_CFGR2 REG32(STM32_ADC1_BASE + 0x10) +#define STM32_ADC_CFGR1_DMACFG BIT(1) +#define STM32_ADC_CFGR1_DMAEN BIT(0) +#define STM32_ADC_CFGR2 REG32(STM32_ADC1_BASE + 0x10) /* Sampling time selection - 1.5 ADC cycles min, 239.5 cycles max */ -#define STM32_ADC_SMPR REG32(STM32_ADC1_BASE + 0x14) +#define STM32_ADC_SMPR REG32(STM32_ADC1_BASE + 0x14) /* Macro to convert enum stm32_adc_smpr to SMP bits of the ADC_SMPR register */ -#define STM32_ADC_SMPR_SMP(s) ((s) - 1) -#define STM32_ADC_TR REG32(STM32_ADC1_BASE + 0x20) -#define STM32_ADC_CHSELR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x40) -#define STM32_ADC_CCR REG32(STM32_ADC1_BASE + 0x308) +#define STM32_ADC_SMPR_SMP(s) ((s)-1) +#define STM32_ADC_TR REG32(STM32_ADC1_BASE + 0x20) +#define STM32_ADC_CHSELR REG32(STM32_ADC1_BASE + 0x28) +#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x40) +#define STM32_ADC_CCR REG32(STM32_ADC1_BASE + 0x308) /* --- Comparators --- */ -#define STM32_COMP_CSR REG32(STM32_COMP_BASE + 0x1C) +#define STM32_COMP_CSR REG32(STM32_COMP_BASE + 0x1C) -#define STM32_COMP_CMP2LOCK BIT(31) -#define STM32_COMP_CMP2OUT BIT(30) -#define STM32_COMP_CMP2HYST_HI (3 << 28) -#define STM32_COMP_CMP2HYST_MED (2 << 28) -#define STM32_COMP_CMP2HYST_LOW (1 << 28) -#define STM32_COMP_CMP2HYST_NO (0 << 28) -#define STM32_COMP_CMP2POL BIT(27) +#define STM32_COMP_CMP2LOCK BIT(31) +#define STM32_COMP_CMP2OUT BIT(30) +#define STM32_COMP_CMP2HYST_HI (3 << 28) +#define STM32_COMP_CMP2HYST_MED (2 << 28) +#define STM32_COMP_CMP2HYST_LOW (1 << 28) +#define STM32_COMP_CMP2HYST_NO (0 << 28) +#define STM32_COMP_CMP2POL BIT(27) #define STM32_COMP_CMP2OUTSEL_TIM3_OCR (7 << 24) #define STM32_COMP_CMP2OUTSEL_TIM3_IC1 (6 << 24) @@ -608,32 +602,32 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_COMP_CMP2OUTSEL_TIM1_OCR (3 << 24) #define STM32_COMP_CMP2OUTSEL_TIM1_IC1 (2 << 24) #define STM32_COMP_CMP2OUTSEL_TIM1_BRK (1 << 24) -#define STM32_COMP_CMP2OUTSEL_NONE (0 << 24) -#define STM32_COMP_WNDWEN BIT(23) - -#define STM32_COMP_CMP2INSEL_MASK (7 << 20) -#define STM32_COMP_CMP2INSEL_INM7 (6 << 20) /* STM32F373 only */ -#define STM32_COMP_CMP2INSEL_INM6 (6 << 20) -#define STM32_COMP_CMP2INSEL_INM5 (5 << 20) -#define STM32_COMP_CMP2INSEL_INM4 (4 << 20) -#define STM32_COMP_CMP2INSEL_VREF (3 << 20) -#define STM32_COMP_CMP2INSEL_VREF34 (2 << 20) -#define STM32_COMP_CMP2INSEL_VREF12 (1 << 20) -#define STM32_COMP_CMP2INSEL_VREF14 (0 << 20) - -#define STM32_COMP_CMP2MODE_VLSPEED (3 << 18) -#define STM32_COMP_CMP2MODE_LSPEED (2 << 18) -#define STM32_COMP_CMP2MODE_MSPEED (1 << 18) -#define STM32_COMP_CMP2MODE_HSPEED (0 << 18) -#define STM32_COMP_CMP2EN BIT(16) - -#define STM32_COMP_CMP1LOCK BIT(15) -#define STM32_COMP_CMP1OUT BIT(14) -#define STM32_COMP_CMP1HYST_HI (3 << 12) -#define STM32_COMP_CMP1HYST_MED (2 << 12) -#define STM32_COMP_CMP1HYST_LOW (1 << 12) -#define STM32_COMP_CMP1HYST_NO (0 << 12) -#define STM32_COMP_CMP1POL BIT(11) +#define STM32_COMP_CMP2OUTSEL_NONE (0 << 24) +#define STM32_COMP_WNDWEN BIT(23) + +#define STM32_COMP_CMP2INSEL_MASK (7 << 20) +#define STM32_COMP_CMP2INSEL_INM7 (6 << 20) /* STM32F373 only */ +#define STM32_COMP_CMP2INSEL_INM6 (6 << 20) +#define STM32_COMP_CMP2INSEL_INM5 (5 << 20) +#define STM32_COMP_CMP2INSEL_INM4 (4 << 20) +#define STM32_COMP_CMP2INSEL_VREF (3 << 20) +#define STM32_COMP_CMP2INSEL_VREF34 (2 << 20) +#define STM32_COMP_CMP2INSEL_VREF12 (1 << 20) +#define STM32_COMP_CMP2INSEL_VREF14 (0 << 20) + +#define STM32_COMP_CMP2MODE_VLSPEED (3 << 18) +#define STM32_COMP_CMP2MODE_LSPEED (2 << 18) +#define STM32_COMP_CMP2MODE_MSPEED (1 << 18) +#define STM32_COMP_CMP2MODE_HSPEED (0 << 18) +#define STM32_COMP_CMP2EN BIT(16) + +#define STM32_COMP_CMP1LOCK BIT(15) +#define STM32_COMP_CMP1OUT BIT(14) +#define STM32_COMP_CMP1HYST_HI (3 << 12) +#define STM32_COMP_CMP1HYST_MED (2 << 12) +#define STM32_COMP_CMP1HYST_LOW (1 << 12) +#define STM32_COMP_CMP1HYST_NO (0 << 12) +#define STM32_COMP_CMP1POL BIT(11) #define STM32_COMP_CMP1OUTSEL_TIM3_OCR (7 << 8) #define STM32_COMP_CMP1OUTSEL_TIM3_IC1 (6 << 8) @@ -642,25 +636,24 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_COMP_CMP1OUTSEL_TIM1_OCR (3 << 8) #define STM32_COMP_CMP1OUTSEL_TIM1_IC1 (2 << 8) #define STM32_COMP_CMP1OUTSEL_TIM1_BRK (1 << 8) -#define STM32_COMP_CMP1OUTSEL_NONE (0 << 8) - -#define STM32_COMP_CMP1INSEL_MASK (7 << 4) -#define STM32_COMP_CMP1INSEL_INM7 (7 << 4) /* STM32F373 only */ -#define STM32_COMP_CMP1INSEL_INM6 (6 << 4) -#define STM32_COMP_CMP1INSEL_INM5 (5 << 4) -#define STM32_COMP_CMP1INSEL_INM4 (4 << 4) -#define STM32_COMP_CMP1INSEL_VREF (3 << 4) -#define STM32_COMP_CMP1INSEL_VREF34 (2 << 4) -#define STM32_COMP_CMP1INSEL_VREF12 (1 << 4) -#define STM32_COMP_CMP1INSEL_VREF14 (0 << 4) - -#define STM32_COMP_CMP1MODE_VLSPEED (3 << 2) -#define STM32_COMP_CMP1MODE_LSPEED (2 << 2) -#define STM32_COMP_CMP1MODE_MSPEED (1 << 2) -#define STM32_COMP_CMP1MODE_HSPEED (0 << 2) -#define STM32_COMP_CMP1SW1 BIT(1) -#define STM32_COMP_CMP1EN BIT(0) - +#define STM32_COMP_CMP1OUTSEL_NONE (0 << 8) + +#define STM32_COMP_CMP1INSEL_MASK (7 << 4) +#define STM32_COMP_CMP1INSEL_INM7 (7 << 4) /* STM32F373 only */ +#define STM32_COMP_CMP1INSEL_INM6 (6 << 4) +#define STM32_COMP_CMP1INSEL_INM5 (5 << 4) +#define STM32_COMP_CMP1INSEL_INM4 (4 << 4) +#define STM32_COMP_CMP1INSEL_VREF (3 << 4) +#define STM32_COMP_CMP1INSEL_VREF34 (2 << 4) +#define STM32_COMP_CMP1INSEL_VREF12 (1 << 4) +#define STM32_COMP_CMP1INSEL_VREF14 (0 << 4) + +#define STM32_COMP_CMP1MODE_VLSPEED (3 << 2) +#define STM32_COMP_CMP1MODE_LSPEED (2 << 2) +#define STM32_COMP_CMP1MODE_MSPEED (1 << 2) +#define STM32_COMP_CMP1MODE_HSPEED (0 << 2) +#define STM32_COMP_CMP1SW1 BIT(1) +#define STM32_COMP_CMP1EN BIT(0) /* --- DMA --- */ @@ -682,19 +675,19 @@ enum dma_channel { STM32_DMAC_CH3 = 2, STM32_DMAC_CH4 = 3, STM32_DMAC_CH5 = 4, +#if defined(CHIP_VARIANT_STM32F07X) || defined(CHIP_VARIANT_STM32F09X) STM32_DMAC_CH6 = 5, STM32_DMAC_CH7 = 6, - /* - * Skip CH8, it should belong to DMA engine 1. - * Sharing code with STM32s that have 16 engines will be easier. - */ +#endif +/* STM32F09 has two DMAs with 7 & 5 channels, respectively */ +#ifdef CHIP_VARIANT_STM32F09X STM32_DMAC_CH9 = 8, STM32_DMAC_CH10 = 9, STM32_DMAC_CH11 = 10, STM32_DMAC_CH12 = 11, STM32_DMAC_CH13 = 12, STM32_DMAC_CH14 = 13, - +#endif /* Channel functions */ STM32_DMAC_ADC = STM32_DMAC_CH1, STM32_DMAC_SPI1_RX = STM32_DMAC_CH2, @@ -722,16 +715,19 @@ enum dma_channel { STM32_DMAC_COUNT = 5, #endif }; - +/* + * TODO(b/233369173): This file was originally shared by many MCUs, + * 8 is assumed to be the max number of channels for all chips. + */ #define STM32_DMAC_PER_CTLR 8 /* Registers for a single channel of the DMA controller */ struct stm32_dma_chan { - uint32_t ccr; /* Control */ - uint32_t cndtr; /* Number of data to transfer */ - uint32_t cpar; /* Peripheral address */ - uint32_t cmar; /* Memory address */ - uint32_t reserved; + uint32_t ccr; /* Control */ + uint32_t cndtr; /* Number of data to transfer */ + uint32_t cpar; /* Peripheral address */ + uint32_t cmar; /* Memory address */ + uint32_t reserved; }; /* Always use stm32_dma_chan_t so volatile keyword is included! */ @@ -742,8 +738,8 @@ typedef stm32_dma_chan_t dma_chan_t; /* Registers for the DMA controller */ struct stm32_dma_regs { - uint32_t isr; - uint32_t ifcr; + uint32_t isr; + uint32_t ifcr; stm32_dma_chan_t chan[STM32_DMAC_COUNT]; }; @@ -752,108 +748,106 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - -#define STM32_DMA_CCR_CHANNEL(channel) (0) +#define STM32_DMA_CCR_CHANNEL(channel) (0) #ifdef CHIP_VARIANT_STM32F09X #define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE) #define STM32_DMA_REGS(channel) \ ((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS) -#define STM32_DMA_CSELR(channel) \ - REG32(((channel) < STM32_DMAC_PER_CTLR ? \ - STM32_DMA1_BASE : STM32_DMA2_BASE) + 0xA8) +#define STM32_DMA_CSELR(channel) \ + REG32(((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_BASE : \ + STM32_DMA2_BASE) + \ + 0xA8) #else #define STM32_DMA_REGS(channel) STM32_DMA1_REGS #endif /* Bits for DMA controller regs (isr and ifcr) */ -#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) +#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) #define STM32_DMA_ISR_MASK(channel, mask) \ ((mask) << STM32_DMA_CH_OFFSET(channel)) -#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) -#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) -#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) -#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) -#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) - -#define STM32_DMA_GIF BIT(0) -#define STM32_DMA_TCIF BIT(1) -#define STM32_DMA_HTIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_ALL 0xf - -#define STM32_DMA_GET_ISR(channel) \ - ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr = \ - ((STM32_DMA_REGS(channel)->isr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) -#define STM32_DMA_GET_IFCR(channel) \ - ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr = \ - ((STM32_DMA_REGS(channel)->ifcr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) - +#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) +#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) +#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) +#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) +#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) + +#define STM32_DMA_GIF BIT(0) +#define STM32_DMA_TCIF BIT(1) +#define STM32_DMA_HTIF BIT(2) +#define STM32_DMA_TEIF BIT(3) +#define STM32_DMA_ALL 0xf + +#define STM32_DMA_GET_ISR(channel) \ + ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) & \ + STM32_DMA_ALL) +#define STM32_DMA_SET_ISR(channel, val) \ + (STM32_DMA_REGS(channel)->isr = \ + ((STM32_DMA_REGS(channel)->isr & \ + ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) +#define STM32_DMA_GET_IFCR(channel) \ + ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) & \ + STM32_DMA_ALL) +#define STM32_DMA_SET_IFCR(channel, val) \ + (STM32_DMA_REGS(channel)->ifcr = \ + ((STM32_DMA_REGS(channel)->ifcr & \ + ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) /* Bits for DMA channel regs */ -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_TCIE BIT(1) -#define STM32_DMA_CCR_HTIE BIT(2) -#define STM32_DMA_CCR_TEIE BIT(3) -#define STM32_DMA_CCR_DIR BIT(4) -#define STM32_DMA_CCR_CIRC BIT(5) -#define STM32_DMA_CCR_PINC BIT(6) -#define STM32_DMA_CCR_MINC BIT(7) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) -#define STM32_DMA_CCR_PL_LOW (0 << 12) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) -#define STM32_DMA_CCR_PL_HIGH (2 << 12) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) -#define STM32_DMA_CCR_MEM2MEM BIT(14) - +#define STM32_DMA_CCR_EN BIT(0) +#define STM32_DMA_CCR_TCIE BIT(1) +#define STM32_DMA_CCR_HTIE BIT(2) +#define STM32_DMA_CCR_TEIE BIT(3) +#define STM32_DMA_CCR_DIR BIT(4) +#define STM32_DMA_CCR_CIRC BIT(5) +#define STM32_DMA_CCR_PINC BIT(6) +#define STM32_DMA_CCR_MINC BIT(7) +#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) +#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) +#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) +#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) +#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) +#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) +#define STM32_DMA_CCR_PL_LOW (0 << 12) +#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) +#define STM32_DMA_CCR_PL_HIGH (2 << 12) +#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) +#define STM32_DMA_CCR_MEM2MEM BIT(14) /* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 +#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) + +#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) +#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) +#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) +#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) + +#define STM32_CRC_CR_RESET BIT(0) +#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) +#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) +#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) +#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) +#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) +#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) +#define STM32_CRC_CR_REV_IN_WORD (3 << 5) +#define STM32_CRC_CR_REV_OUT BIT(7) + +#define EP_MASK 0x0F0F +#define EP_TX_DTOG 0x0040 +#define EP_TX_MASK 0x0030 #define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 +#define EP_TX_NAK 0x0020 #define EP_TX_STALL 0x0010 #define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 +#define EP_RX_DTOG 0x4000 +#define EP_RX_MASK 0x3000 #define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 +#define EP_RX_NAK 0x2000 #define EP_RX_STALL 0x1000 #define EP_RX_DISAB 0x0000 @@ -863,28 +857,27 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) #define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) + STM32_USB_EP(n) = \ + (((STM32_USB_EP(n) & (EP_MASK | (mask))) ^ (val)) | (flags)) /* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) +#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) +#define STM32_RNG_CR_RNGEN BIT(2) +#define STM32_RNG_CR_IE BIT(3) +#define STM32_RNG_CR_CED BIT(5) +#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) +#define STM32_RNG_SR_DRDY BIT(0) +#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) /* --- AXI interconnect --- */ /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) +#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x)) +#define WRITE_ISS_OVERRIDE BIT(1) +#define READ_ISS_OVERRIDE BIT(0) /* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) +#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) +#define STM32_UNIQUE_ID_LENGTH (3 * 4) #endif /* !__ASSEMBLER__ */ diff --git a/chip/stm32/registers-stm32f3.h b/chip/stm32/registers-stm32f3.h index b7e3cfc8af..e88f5f7d52 100644 --- a/chip/stm32/registers-stm32f3.h +++ b/chip/stm32/registers-stm32f3.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,473 +19,467 @@ #endif /* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_TAMPER_STAMP 2 -#define STM32_IRQ_RTC_WAKEUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 +#define STM32_IRQ_WWDG 0 +#define STM32_IRQ_PVD 1 +#define STM32_IRQ_TAMPER_STAMP 2 +#define STM32_IRQ_RTC_WAKEUP 3 +#define STM32_IRQ_FLASH 4 +#define STM32_IRQ_RCC 5 +#define STM32_IRQ_EXTI0 6 +#define STM32_IRQ_EXTI1 7 +#define STM32_IRQ_EXTI2 8 +#define STM32_IRQ_EXTI3 9 +#define STM32_IRQ_EXTI4 10 +#define STM32_IRQ_DMA_CHANNEL_1 11 +#define STM32_IRQ_DMA_CHANNEL_2 12 +#define STM32_IRQ_DMA_CHANNEL_3 13 +#define STM32_IRQ_DMA_CHANNEL_4 14 +#define STM32_IRQ_DMA_CHANNEL_5 15 +#define STM32_IRQ_DMA_CHANNEL_6 16 +#define STM32_IRQ_DMA_CHANNEL_7 17 #ifdef CHIP_VARIANT_STM32F373 -#define STM32_IRQ_USB_HP 74 -#define STM32_IRQ_USB_LP 75 +#define STM32_IRQ_USB_HP 74 +#define STM32_IRQ_USB_LP 75 #else -#define STM32_IRQ_USB_HP 19 -#define STM32_IRQ_USB_LP 20 +#define STM32_IRQ_USB_HP 19 +#define STM32_IRQ_USB_LP 20 #endif -#define STM32_IRQ_ADC1 18 /* STM32L4 only */ -#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ -#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ -#define STM32_IRQ_DAC 21 -#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ +#define STM32_IRQ_ADC1 18 /* STM32L4 only */ +#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ +#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ +#define STM32_IRQ_DAC 21 +#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ #ifdef CHIP_VARIANT_STM32F373 -#define STM32_IRQ_COMP 64 +#define STM32_IRQ_COMP 64 #else -#define STM32_IRQ_COMP 22 +#define STM32_IRQ_COMP 22 #endif -#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_LCD 24 /* STM32L15X only */ -#define STM32_IRQ_TIM15 24 /* STM32F373 only */ -#define STM32_IRQ_TIM9 25 /* STM32L15X only */ -#define STM32_IRQ_TIM16 25 /* STM32F373 only */ -#define STM32_IRQ_TIM10 26 /* STM32L15X only */ -#define STM32_IRQ_TIM17 26 /* STM32F373 only */ -#define STM32_IRQ_TIM11 27 /* STM32L15X only */ -#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_TIM3 29 -#define STM32_IRQ_TIM4 30 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ -#define STM32_IRQ_CEC 42 /* STM32F373 only */ -#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ -#define STM32_IRQ_TIM12 43 /* STM32F373 only */ -#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ -#define STM32_IRQ_TIM13 44 /* STM32F373 only */ -#define STM32_IRQ_TIM14 45 /* STM32F373 only */ -#define STM32_IRQ_TIM5 50 /* STM32F373 */ -#define STM32_IRQ_SPI3 51 /* STM32F373 */ -#define STM32_IRQ_USART4 52 /* STM32F446 only */ -#define STM32_IRQ_USART5 53 /* STM32F446 only */ -#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ -#define STM32_IRQ_TIM7 55 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ +#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ +#define STM32_IRQ_EXTI9_5 23 +#define STM32_IRQ_LCD 24 /* STM32L15X only */ +#define STM32_IRQ_TIM15 24 /* STM32F373 only */ +#define STM32_IRQ_TIM9 25 /* STM32L15X only */ +#define STM32_IRQ_TIM16 25 /* STM32F373 only */ +#define STM32_IRQ_TIM10 26 /* STM32L15X only */ +#define STM32_IRQ_TIM17 26 /* STM32F373 only */ +#define STM32_IRQ_TIM11 27 /* STM32L15X only */ +#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ +#define STM32_IRQ_TIM2 28 +#define STM32_IRQ_TIM3 29 +#define STM32_IRQ_TIM4 30 +#define STM32_IRQ_I2C1_EV 31 +#define STM32_IRQ_I2C1_ER 32 +#define STM32_IRQ_I2C2_EV 33 +#define STM32_IRQ_I2C2_ER 34 +#define STM32_IRQ_SPI1 35 +#define STM32_IRQ_SPI2 36 +#define STM32_IRQ_USART1 37 +#define STM32_IRQ_USART2 38 +#define STM32_IRQ_USART3 39 +#define STM32_IRQ_EXTI15_10 40 +#define STM32_IRQ_RTC_ALARM 41 +#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ +#define STM32_IRQ_CEC 42 /* STM32F373 only */ +#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ +#define STM32_IRQ_TIM12 43 /* STM32F373 only */ +#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ +#define STM32_IRQ_TIM13 44 /* STM32F373 only */ +#define STM32_IRQ_TIM14 45 /* STM32F373 only */ +#define STM32_IRQ_TIM5 50 /* STM32F373 */ +#define STM32_IRQ_SPI3 51 /* STM32F373 */ +#define STM32_IRQ_USART4 52 /* STM32F446 only */ +#define STM32_IRQ_USART5 53 /* STM32F446 only */ +#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ +#define STM32_IRQ_TIM7 55 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ /* if MISC_REMAP bits are set */ -#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ -#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ -#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ -#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ -#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ -#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ -#define STM32_IRQ_LPUART 70 /* STM32L4 only */ -#define STM32_IRQ_USART9 70 /* STM32L4 only */ -#define STM32_IRQ_USART6 71 /* STM32F446 only */ -#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ -#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ -#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ -#define STM32_IRQ_TIM19 78 /* STM32F373 only */ -#define STM32_IRQ_AES 79 /* STM32L4 only */ -#define STM32_IRQ_RNG 80 /* STM32L4 only */ -#define STM32_IRQ_FPU 81 /* STM32F373 only */ - +#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ +#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ +#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ +#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ +#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ +#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ +#define STM32_IRQ_LPUART 70 /* STM32L4 only */ +#define STM32_IRQ_USART9 70 /* STM32L4 only */ +#define STM32_IRQ_USART6 71 /* STM32F446 only */ +#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ +#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ +#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ +#define STM32_IRQ_TIM19 78 /* STM32F373 only */ +#define STM32_IRQ_AES 79 /* STM32L4 only */ +#define STM32_IRQ_RNG 80 /* STM32L4 only */ +#define STM32_IRQ_FPU 81 /* STM32F373 only */ /* To simplify code generation, define DMA channel 9..10 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 +#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 +#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 +#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 +#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 /* aliases for easier code sharing */ #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV #define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV #define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV - - /* Peripheral base addresses */ -#define STM32_ADC1_BASE 0x40012400 -#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */ +#define STM32_ADC1_BASE 0x40012400 +#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */ -#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ -#define STM32_CRC_BASE 0x40023000 -#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ -#define STM32_DAC_BASE 0x40007400 +#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ +#define STM32_CRC_BASE 0x40023000 +#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ +#define STM32_DAC_BASE 0x40007400 -#define STM32_COMP_BASE 0x40010000 +#define STM32_COMP_BASE 0x40010000 -#define STM32_DBGMCU_BASE 0xE0042000 +#define STM32_DBGMCU_BASE 0xE0042000 -#define STM32_DMA1_BASE 0x40020000 -#define STM32_DMA2_BASE 0x40020400 +#define STM32_DMA1_BASE 0x40020000 +#define STM32_DMA2_BASE 0x40020400 -#define STM32_EXTI_BASE 0x40010400 +#define STM32_EXTI_BASE 0x40010400 -#define STM32_FLASH_REGS_BASE 0x40022000 +#define STM32_FLASH_REGS_BASE 0x40022000 -#define STM32_GPIOA_BASE 0x48000000 -#define STM32_GPIOB_BASE 0x48000400 -#define STM32_GPIOC_BASE 0x48000800 -#define STM32_GPIOD_BASE 0x48000C00 -#define STM32_GPIOE_BASE 0x48001000 -#define STM32_GPIOF_BASE 0x48001400 -#define STM32_GPIOG_BASE 0x48001800 /* only for stm32l4x6 */ -#define STM32_GPIOH_BASE 0x48001C00 /* only for stm32l4 */ +#define STM32_GPIOA_BASE 0x48000000 +#define STM32_GPIOB_BASE 0x48000400 +#define STM32_GPIOC_BASE 0x48000800 +#define STM32_GPIOD_BASE 0x48000C00 +#define STM32_GPIOE_BASE 0x48001000 +#define STM32_GPIOF_BASE 0x48001400 +#define STM32_GPIOG_BASE 0x48001800 /* only for stm32l4x6 */ +#define STM32_GPIOH_BASE 0x48001C00 /* only for stm32l4 */ -#define STM32_I2C1_BASE 0x40005400 -#define STM32_I2C2_BASE 0x40005800 -#define STM32_I2C3_BASE 0x40005C00 -#define STM32_I2C4_BASE 0x40006000 +#define STM32_I2C1_BASE 0x40005400 +#define STM32_I2C2_BASE 0x40005800 +#define STM32_I2C3_BASE 0x40005C00 +#define STM32_I2C4_BASE 0x40006000 -#define STM32_IWDG_BASE 0x40003000 -#define STM32_LCD_BASE 0x40002400 +#define STM32_IWDG_BASE 0x40003000 +#define STM32_LCD_BASE 0x40002400 -#define STM32_OPTB_BASE 0x1FFFF800 +#define STM32_OPTB_BASE 0x1FFFF800 -#define STM32_PMSE_BASE 0x40013400 -#define STM32_PWR_BASE 0x40007000 +#define STM32_PMSE_BASE 0x40013400 +#define STM32_PWR_BASE 0x40007000 -#define STM32_RCC_BASE 0x40021000 +#define STM32_RCC_BASE 0x40021000 -#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ -#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ -#define STM32_RTC_BASE 0x40002800 +#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ +#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ +#define STM32_RTC_BASE 0x40002800 -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ +#define STM32_SPI1_BASE 0x40013000 +#define STM32_SPI2_BASE 0x40003800 +#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ -#define STM32_SYSCFG_BASE 0x40010000 +#define STM32_SYSCFG_BASE 0x40010000 -#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ -#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ -#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 -#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ -#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ +#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ +#define STM32_TIM2_BASE 0x40000000 +#define STM32_TIM3_BASE 0x40000400 +#define STM32_TIM4_BASE 0x40000800 +#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ +#define STM32_TIM6_BASE 0x40001000 +#define STM32_TIM7_BASE 0x40001400 +#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ +#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ +#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ +#define STM32_TIM15_BASE 0x40014000 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ +#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ -#define STM32_UNIQUE_ID_BASE 0x1ffff7ac +#define STM32_UNIQUE_ID_BASE 0x1ffff7ac -#define STM32_USART1_BASE 0x40013800 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART9_BASE 0x40008000 /* LPUART */ +#define STM32_USART1_BASE 0x40013800 +#define STM32_USART2_BASE 0x40004400 +#define STM32_USART3_BASE 0x40004800 +#define STM32_USART4_BASE 0x40004c00 +#define STM32_USART9_BASE 0x40008000 /* LPUART */ -#define STM32_USB_CAN_SRAM_BASE 0x40006000 -#define STM32_USB_FS_BASE 0x40005C00 - -#define STM32_WWDG_BASE 0x40002C00 +#define STM32_USB_CAN_SRAM_BASE 0x40006000 +#define STM32_USB_FS_BASE 0x40005C00 +#define STM32_WWDG_BASE 0x40002C00 #ifndef __ASSEMBLER__ /* Register definitions */ /* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_UESM BIT(1) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR2_SWAP BIT(15) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) -#define STM32_USART_CR3_OVRDIS BIT(12) -#define STM32_USART_CR3_WUS_START_BIT (2 << 20) -#define STM32_USART_CR3_WUFIE BIT(22) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) -#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) -#define STM32_USART_ICR_ORECF BIT(3) -#define STM32_USART_ICR_TCCF BIT(6) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) -#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) +#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) +#define STM32_USART_CR1_UE BIT(0) +#define STM32_USART_CR1_UESM BIT(1) +#define STM32_USART_CR1_RE BIT(2) +#define STM32_USART_CR1_TE BIT(3) +#define STM32_USART_CR1_RXNEIE BIT(5) +#define STM32_USART_CR1_TCIE BIT(6) +#define STM32_USART_CR1_TXEIE BIT(7) +#define STM32_USART_CR1_PS BIT(9) +#define STM32_USART_CR1_PCE BIT(10) +#define STM32_USART_CR1_M BIT(12) +#define STM32_USART_CR1_OVER8 BIT(15) +#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) +#define STM32_USART_CR2_SWAP BIT(15) +#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) +#define STM32_USART_CR3_EIE BIT(0) +#define STM32_USART_CR3_DMAR BIT(6) +#define STM32_USART_CR3_DMAT BIT(7) +#define STM32_USART_CR3_ONEBIT BIT(11) +#define STM32_USART_CR3_OVRDIS BIT(12) +#define STM32_USART_CR3_WUS_START_BIT (2 << 20) +#define STM32_USART_CR3_WUFIE BIT(22) +#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) +#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) +#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) +#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) +#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) +#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) +#define STM32_USART_ICR_ORECF BIT(3) +#define STM32_USART_ICR_TCCF BIT(6) +#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) +#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) +#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) /* register alias */ -#define STM32_USART_SR(base) STM32_USART_ISR(base) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) +#define STM32_USART_SR(base) STM32_USART_ISR(base) +#define STM32_USART_SR_ORE BIT(3) +#define STM32_USART_SR_RXNE BIT(5) +#define STM32_USART_SR_TC BIT(6) +#define STM32_USART_SR_TXE BIT(7) /* --- GPIO --- */ -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) -#define STM32_GPIO_BRR(b) REG32((b) + 0x28) -#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4 */ - -#define GPIO_ALT_F0 0x0 -#define GPIO_ALT_F1 0x1 -#define GPIO_ALT_F2 0x2 -#define GPIO_ALT_F3 0x3 -#define GPIO_ALT_F4 0x4 -#define GPIO_ALT_F5 0x5 -#define GPIO_ALT_F6 0x6 -#define GPIO_ALT_F7 0x7 -#define GPIO_ALT_F8 0x8 -#define GPIO_ALT_F9 0x9 -#define GPIO_ALT_FA 0xA -#define GPIO_ALT_FB 0xB -#define GPIO_ALT_FC 0xC -#define GPIO_ALT_FD 0xD -#define GPIO_ALT_FE 0xE -#define GPIO_ALT_FF 0xF +#define STM32_GPIO_MODER(b) REG32((b) + 0x00) +#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) +#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) +#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) +#define STM32_GPIO_IDR(b) REG16((b) + 0x10) +#define STM32_GPIO_ODR(b) REG16((b) + 0x14) +#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) +#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) +#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) +#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) +#define STM32_GPIO_BRR(b) REG32((b) + 0x28) +#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4 */ + +#define GPIO_ALT_F0 0x0 +#define GPIO_ALT_F1 0x1 +#define GPIO_ALT_F2 0x2 +#define GPIO_ALT_F3 0x3 +#define GPIO_ALT_F4 0x4 +#define GPIO_ALT_F5 0x5 +#define GPIO_ALT_F6 0x6 +#define GPIO_ALT_F7 0x7 +#define GPIO_ALT_F8 0x8 +#define GPIO_ALT_F9 0x9 +#define GPIO_ALT_FA 0xA +#define GPIO_ALT_FB 0xB +#define GPIO_ALT_FC 0xC +#define GPIO_ALT_FD 0xD +#define GPIO_ALT_FE 0xE +#define GPIO_ALT_FF 0xF /* --- I2C --- */ -#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_TXIE BIT(1) -#define STM32_I2C_CR1_RXIE BIT(2) -#define STM32_I2C_CR1_ADDRIE BIT(3) -#define STM32_I2C_CR1_NACKIE BIT(4) -#define STM32_I2C_CR1_STOPIE BIT(5) -#define STM32_I2C_CR1_ERRIE BIT(7) -#define STM32_I2C_CR1_WUPEN BIT(18) -#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_RD_WRN BIT(10) -#define STM32_I2C_CR2_START BIT(13) -#define STM32_I2C_CR2_STOP BIT(14) -#define STM32_I2C_CR2_NACK BIT(15) -#define STM32_I2C_CR2_RELOAD BIT(24) -#define STM32_I2C_CR2_AUTOEND BIT(25) -#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_ISR_TXE BIT(0) -#define STM32_I2C_ISR_TXIS BIT(1) -#define STM32_I2C_ISR_RXNE BIT(2) -#define STM32_I2C_ISR_ADDR BIT(3) -#define STM32_I2C_ISR_NACK BIT(4) -#define STM32_I2C_ISR_STOP BIT(5) -#define STM32_I2C_ISR_TC BIT(6) -#define STM32_I2C_ISR_TCR BIT(7) -#define STM32_I2C_ISR_BERR BIT(8) -#define STM32_I2C_ISR_ARLO BIT(9) -#define STM32_I2C_ISR_OVR BIT(10) -#define STM32_I2C_ISR_PECERR BIT(11) -#define STM32_I2C_ISR_TIMEOUT BIT(12) -#define STM32_I2C_ISR_ALERT BIT(13) -#define STM32_I2C_ISR_BUSY BIT(15) -#define STM32_I2C_ISR_DIR BIT(16) -#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe) -#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_ICR_ADDRCF BIT(3) -#define STM32_I2C_ICR_NACKCF BIT(4) -#define STM32_I2C_ICR_STOPCF BIT(5) -#define STM32_I2C_ICR_BERRCF BIT(8) -#define STM32_I2C_ICR_ARLOCF BIT(9) -#define STM32_I2C_ICR_OVRCF BIT(10) -#define STM32_I2C_ICR_TIMEOUTCF BIT(12) -#define STM32_I2C_ICR_ALL 0x3F38 -#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) -#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) -#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) - +#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) +#define STM32_I2C_CR1_PE BIT(0) +#define STM32_I2C_CR1_TXIE BIT(1) +#define STM32_I2C_CR1_RXIE BIT(2) +#define STM32_I2C_CR1_ADDRIE BIT(3) +#define STM32_I2C_CR1_NACKIE BIT(4) +#define STM32_I2C_CR1_STOPIE BIT(5) +#define STM32_I2C_CR1_ERRIE BIT(7) +#define STM32_I2C_CR1_WUPEN BIT(18) +#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) +#define STM32_I2C_CR2_RD_WRN BIT(10) +#define STM32_I2C_CR2_START BIT(13) +#define STM32_I2C_CR2_STOP BIT(14) +#define STM32_I2C_CR2_NACK BIT(15) +#define STM32_I2C_CR2_RELOAD BIT(24) +#define STM32_I2C_CR2_AUTOEND BIT(25) +#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) +#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) +#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) +#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) +#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) +#define STM32_I2C_ISR_TXE BIT(0) +#define STM32_I2C_ISR_TXIS BIT(1) +#define STM32_I2C_ISR_RXNE BIT(2) +#define STM32_I2C_ISR_ADDR BIT(3) +#define STM32_I2C_ISR_NACK BIT(4) +#define STM32_I2C_ISR_STOP BIT(5) +#define STM32_I2C_ISR_TC BIT(6) +#define STM32_I2C_ISR_TCR BIT(7) +#define STM32_I2C_ISR_BERR BIT(8) +#define STM32_I2C_ISR_ARLO BIT(9) +#define STM32_I2C_ISR_OVR BIT(10) +#define STM32_I2C_ISR_PECERR BIT(11) +#define STM32_I2C_ISR_TIMEOUT BIT(12) +#define STM32_I2C_ISR_ALERT BIT(13) +#define STM32_I2C_ISR_BUSY BIT(15) +#define STM32_I2C_ISR_DIR BIT(16) +#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe) +#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) +#define STM32_I2C_ICR_ADDRCF BIT(3) +#define STM32_I2C_ICR_NACKCF BIT(4) +#define STM32_I2C_ICR_STOPCF BIT(5) +#define STM32_I2C_ICR_BERRCF BIT(8) +#define STM32_I2C_ICR_ARLOCF BIT(9) +#define STM32_I2C_ICR_OVRCF BIT(10) +#define STM32_I2C_ICR_TIMEOUTCF BIT(12) +#define STM32_I2C_ICR_ALL 0x3F38 +#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) +#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) +#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) /* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) - -#define STM32_PWR_CSR_EWUP1 BIT(8) -#define STM32_PWR_CSR_EWUP2 BIT(9) -#define STM32_PWR_CSR_EWUP3 BIT(10) -#define STM32_PWR_CSR_EWUP4 BIT(11) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP5 BIT(12) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP6 BIT(13) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP7 BIT(14) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP8 BIT(15) /* STM32F0xx only */ - -#define STM32_CRS_CR REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */ -#define STM32_CRS_CR_SYNCOKIE BIT(0) -#define STM32_CRS_CR_SYNCWARNIE BIT(1) -#define STM32_CRS_CR_ERRIE BIT(2) -#define STM32_CRS_CR_ESYNCIE BIT(3) -#define STM32_CRS_CR_CEN BIT(5) -#define STM32_CRS_CR_AUTOTRIMEN BIT(6) -#define STM32_CRS_CR_SWSYNC BIT(7) -#define STM32_CRS_CR_TRIM(n) (((n) & 0x3f) << 8) - -#define STM32_CRS_CFGR REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */ -#define STM32_CRS_CFGR_RELOAD(n) (((n) & 0xffff) << 0) -#define STM32_CRS_CFGR_FELIM(n) (((n) & 0xff) << 16) -#define STM32_CRS_CFGR_SYNCDIV(n) (((n) & 7) << 24) -#define STM32_CRS_CFGR_SYNCSRC(n) (((n) & 3) << 28) -#define STM32_CRS_CFGR_SYNCPOL BIT(31) - -#define STM32_CRS_ISR REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */ -#define STM32_CRS_ISR_SYNCOKF BIT(0) -#define STM32_CRS_ISR_SYNCWARNF BIT(1) -#define STM32_CRS_ISR_ERRF BIT(2) -#define STM32_CRS_ISR_ESYNCF BIT(3) -#define STM32_CRS_ISR_SYNCERR BIT(8) -#define STM32_CRS_ISR_SYNCMISS BIT(9) -#define STM32_CRS_ISR_TRIMOVF BIT(10) -#define STM32_CRS_ISR_FEDIR BIT(15) -#define STM32_CRS_ISR_FECAP (0xffff << 16) - -#define STM32_CRS_ICR REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */ -#define STM32_CRS_ICR_SYNCOKC BIT(0) -#define STM32_CRS_ICR_SYNCWARINC BIT(1) -#define STM32_CRS_ICR_ERRC BIT(2) -#define STM32_CRS_ICR_ESYNCC BIT(3) - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x04) -#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x0c) -#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x10) -#define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x18) -#define STM32_RCC_APB2ENR_ADCEN BIT(9) /* STM32F3/F0 */ -#define STM32_RCC_APB2ENR_TIM16EN BIT(17) -#define STM32_RCC_APB2ENR_TIM17EN BIT(18) -#define STM32_RCC_DBGMCUEN BIT(22) -#define STM32_RCC_SYSCFGEN BIT(0) - -#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x1c) -#define STM32_RCC_PWREN BIT(28) - -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x24) +#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) + +#define STM32_PWR_CSR_EWUP1 BIT(8) +#define STM32_PWR_CSR_EWUP2 BIT(9) +#define STM32_PWR_CSR_EWUP3 BIT(10) +#define STM32_PWR_CSR_EWUP4 BIT(11) /* STM32F0xx only */ +#define STM32_PWR_CSR_EWUP5 BIT(12) /* STM32F0xx only */ +#define STM32_PWR_CSR_EWUP6 BIT(13) /* STM32F0xx only */ +#define STM32_PWR_CSR_EWUP7 BIT(14) /* STM32F0xx only */ +#define STM32_PWR_CSR_EWUP8 BIT(15) /* STM32F0xx only */ + +#define STM32_CRS_CR REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */ +#define STM32_CRS_CR_SYNCOKIE BIT(0) +#define STM32_CRS_CR_SYNCWARNIE BIT(1) +#define STM32_CRS_CR_ERRIE BIT(2) +#define STM32_CRS_CR_ESYNCIE BIT(3) +#define STM32_CRS_CR_CEN BIT(5) +#define STM32_CRS_CR_AUTOTRIMEN BIT(6) +#define STM32_CRS_CR_SWSYNC BIT(7) +#define STM32_CRS_CR_TRIM(n) (((n)&0x3f) << 8) + +#define STM32_CRS_CFGR REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */ +#define STM32_CRS_CFGR_RELOAD(n) (((n)&0xffff) << 0) +#define STM32_CRS_CFGR_FELIM(n) (((n)&0xff) << 16) +#define STM32_CRS_CFGR_SYNCDIV(n) (((n)&7) << 24) +#define STM32_CRS_CFGR_SYNCSRC(n) (((n)&3) << 28) +#define STM32_CRS_CFGR_SYNCPOL BIT(31) + +#define STM32_CRS_ISR REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */ +#define STM32_CRS_ISR_SYNCOKF BIT(0) +#define STM32_CRS_ISR_SYNCWARNF BIT(1) +#define STM32_CRS_ISR_ERRF BIT(2) +#define STM32_CRS_ISR_ESYNCF BIT(3) +#define STM32_CRS_ISR_SYNCERR BIT(8) +#define STM32_CRS_ISR_SYNCMISS BIT(9) +#define STM32_CRS_ISR_TRIMOVF BIT(10) +#define STM32_CRS_ISR_FEDIR BIT(15) +#define STM32_CRS_ISR_FECAP (0xffff << 16) + +#define STM32_CRS_ICR REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */ +#define STM32_CRS_ICR_SYNCOKC BIT(0) +#define STM32_CRS_ICR_SYNCWARINC BIT(1) +#define STM32_CRS_ICR_ERRC BIT(2) +#define STM32_CRS_ICR_ESYNCC BIT(3) + +#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) +#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x04) +#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x08) +#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x0c) +#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x10) +#define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x14) +#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x18) +#define STM32_RCC_APB2ENR_ADCEN BIT(9) /* STM32F3/F0 */ +#define STM32_RCC_APB2ENR_TIM16EN BIT(17) +#define STM32_RCC_APB2ENR_TIM17EN BIT(18) +#define STM32_RCC_DBGMCUEN BIT(22) +#define STM32_RCC_SYSCFGEN BIT(0) + +#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x1c) +#define STM32_RCC_PWREN BIT(28) + +#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x20) +#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x24) /* STM32F373 */ -#define STM32_RCC_CFGR2 REG32(STM32_RCC_BASE + 0x2c) +#define STM32_RCC_CFGR2 REG32(STM32_RCC_BASE + 0x2c) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_CFGR3 REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_CR2 REG32(STM32_RCC_BASE + 0x34) /* STM32F0XX */ +#define STM32_RCC_CFGR3 REG32(STM32_RCC_BASE + 0x30) +#define STM32_RCC_CR2 REG32(STM32_RCC_BASE + 0x34) /* STM32F0XX */ -#define STM32_RCC_HB_DMA1 BIT(0) +#define STM32_RCC_HB_DMA1 BIT(0) /* STM32F373 */ -#define STM32_RCC_HB_DMA2 BIT(1) -#define STM32_RCC_PB2_TIM1 BIT(11) /* Except STM32F373 */ -#define STM32_RCC_PB2_TIM15 BIT(16) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM16 BIT(17) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM17 BIT(18) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM19 BIT(19) /* STM32F373 */ -#define STM32_RCC_PB2_PMAD BIT(11) /* STM32TS */ -#define STM32_RCC_PB2_PMSE BIT(13) /* STM32TS */ -#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32F373 */ -#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32F373 */ -#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB1_TIM18 BIT(9) /* STM32F373 */ -#define STM32_RCC_PB1_USB BIT(23) -#define STM32_RCC_PB1_CRS BIT(27) - -#define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x00) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) -#define STM32_SYSCFG_CFGR2 REG32(STM32_SYSCFG_BASE + 0x18) - +#define STM32_RCC_HB_DMA2 BIT(1) +#define STM32_RCC_PB2_TIM1 BIT(11) /* Except STM32F373 */ +#define STM32_RCC_PB2_TIM15 BIT(16) /* STM32F0XX and STM32F373 */ +#define STM32_RCC_PB2_TIM16 BIT(17) /* STM32F0XX and STM32F373 */ +#define STM32_RCC_PB2_TIM17 BIT(18) /* STM32F0XX and STM32F373 */ +#define STM32_RCC_PB2_TIM19 BIT(19) /* STM32F373 */ +#define STM32_RCC_PB2_PMAD BIT(11) /* STM32TS */ +#define STM32_RCC_PB2_PMSE BIT(13) /* STM32TS */ +#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32F373 */ +#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32F373 */ +#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32F0XX and STM32F373 */ +#define STM32_RCC_PB1_TIM18 BIT(9) /* STM32F373 */ +#define STM32_RCC_PB1_USB BIT(23) +#define STM32_RCC_PB1_CRS BIT(27) + +#define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x00) +#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) +#define STM32_SYSCFG_CFGR2 REG32(STM32_SYSCFG_BASE + 0x18) /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB2_USART1 BIT(14) +#define STM32_RCC_PB2_USART1 BIT(14) /* Reset causes definitions */ /* Reset causes in RCC CSR register */ #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG 0x60000000 -#define RESET_CAUSE_SFT 0x10000000 -#define RESET_CAUSE_POR 0x08000000 -#define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xfe000000 -#define RESET_CAUSE_RMVF 0x01000000 +#define RESET_CAUSE_WDG 0x60000000 +#define RESET_CAUSE_SFT 0x10000000 +#define RESET_CAUSE_POR 0x08000000 +#define RESET_CAUSE_PIN 0x04000000 +#define RESET_CAUSE_OTHER 0xfe000000 +#define RESET_CAUSE_RMVF 0x01000000 /* Power cause in PWR CSR register */ #define STM32_PWR_RESET_CAUSE STM32_PWR_CSR #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR -#define RESET_CAUSE_SBF 0x00000002 -#define RESET_CAUSE_SBF_CLR 0x00000004 +#define RESET_CAUSE_SBF 0x00000002 +#define RESET_CAUSE_SBF_CLR 0x00000004 /* --- Watchdogs --- */ /* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 64 +#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) +#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) +#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) +#define STM32_RTC_CR_BYPSHAD BIT(5) +#define STM32_RTC_CR_ALRAE BIT(8) +#define STM32_RTC_CR_ALRAIE BIT(12) +#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) +#define STM32_RTC_ISR_ALRAWF BIT(0) +#define STM32_RTC_ISR_RSF BIT(5) +#define STM32_RTC_ISR_INITF BIT(6) +#define STM32_RTC_ISR_INIT BIT(7) +#define STM32_RTC_ISR_ALRAF BIT(8) +#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) +#define STM32_RTC_PRER_A_MASK (0x7f << 16) +#define STM32_RTC_PRER_S_MASK (0x7fff << 0) +#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) +#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) +#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) +#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) +#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) +#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) +#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) +#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) +#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) +#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) +#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) + +#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) +#define STM32_BKP_BYTES 64 /* --- SPI --- */ @@ -502,8 +496,8 @@ struct stm32_spi_regs { unsigned crcpr; unsigned rxcrcr; unsigned txcrcr; - unsigned i2scfgr; /* STM32L only */ - unsigned i2spr; /* STM32L only */ + unsigned i2scfgr; /* STM32L only */ + unsigned i2spr; /* STM32L only */ }; /* Must be volatile, or compiler optimizes out repeated accesses */ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; @@ -513,125 +507,124 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) +#define STM32_SPI_CR1_BIDIMODE BIT(15) +#define STM32_SPI_CR1_BIDIOE BIT(14) +#define STM32_SPI_CR1_CRCEN BIT(13) +#define STM32_SPI_CR1_SSM BIT(9) +#define STM32_SPI_CR1_SSI BIT(8) +#define STM32_SPI_CR1_LSBFIRST BIT(7) +#define STM32_SPI_CR1_SPE BIT(6) +#define STM32_SPI_CR1_BR_DIV64R (5 << 3) +#define STM32_SPI_CR1_BR_DIV4R BIT(3) +#define STM32_SPI_CR1_MSTR BIT(2) +#define STM32_SPI_CR1_CPOL BIT(1) +#define STM32_SPI_CR1_CPHA BIT(0) +#define STM32_SPI_CR2_FRXTH BIT(12) +#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8) +#define STM32_SPI_CR2_TXEIE BIT(7) +#define STM32_SPI_CR2_RXNEIE BIT(6) +#define STM32_SPI_CR2_NSSP BIT(3) +#define STM32_SPI_CR2_SSOE BIT(2) +#define STM32_SPI_CR2_TXDMAEN BIT(1) +#define STM32_SPI_CR2_RXDMAEN BIT(0) + +#define STM32_SPI_SR_RXNE BIT(0) +#define STM32_SPI_SR_TXE BIT(1) +#define STM32_SPI_SR_CRCERR BIT(4) +#define STM32_SPI_SR_BSY BIT(7) +#define STM32_SPI_SR_FRLVL (3 << 9) +#define STM32_SPI_SR_FTLVL (3 << 11) /* --- Debug --- */ -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) +#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) +#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) /* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) +#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) #define STM32_FLASH_ACR_LATENCY_SHIFT (0) -#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) -#define STM32_FLASH_ACR_LATENCY BIT(0) -#define STM32_FLASH_ACR_PRFTEN BIT(4) -#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB - -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define FLASH_OPTKEYR_KEY1 FLASH_KEYR_KEY1 -#define FLASH_OPTKEYR_KEY2 FLASH_KEYR_KEY2 -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define FLASH_SR_BUSY BIT(0) -#define FLASH_SR_PGERR BIT(2) -#define FLASH_SR_WRPRTERR BIT(4) -#define FLASH_SR_ALL_ERR \ - (FLASH_SR_PGERR | FLASH_SR_WRPRTERR) -#define FLASH_SR_EOP BIT(5) -#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_OPTPG BIT(4) -#define FLASH_CR_OPTER BIT(5) -#define FLASH_CR_STRT BIT(6) -#define FLASH_CR_LOCK BIT(7) -#define FLASH_CR_OPTWRE BIT(9) -#define FLASH_CR_OBL_LAUNCH BIT(13) -#define STM32_FLASH_OPT_LOCKED (!(STM32_FLASH_CR & FLASH_CR_OPTWRE)) -#define STM32_FLASH_AR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c) -#define STM32_FLASH_OBR_RDP_MASK (3 << 1) -#define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20) - -#define STM32_OPTB_RDP_OFF 0x00 -#define STM32_OPTB_USER_OFF 0x02 -#define STM32_OPTB_WRP_OFF(n) (0x08 + (n&3) * 2) -#define STM32_OPTB_WRP01 0x08 -#define STM32_OPTB_WRP23 0x0c - -#define STM32_OPTB_COMPL_SHIFT 8 +#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) +#define STM32_FLASH_ACR_LATENCY BIT(0) +#define STM32_FLASH_ACR_PRFTEN BIT(4) +#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) +#define FLASH_KEYR_KEY1 0x45670123 +#define FLASH_KEYR_KEY2 0xCDEF89AB + +#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) +#define FLASH_OPTKEYR_KEY1 FLASH_KEYR_KEY1 +#define FLASH_OPTKEYR_KEY2 FLASH_KEYR_KEY2 +#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) +#define FLASH_SR_BUSY BIT(0) +#define FLASH_SR_PGERR BIT(2) +#define FLASH_SR_WRPRTERR BIT(4) +#define FLASH_SR_ALL_ERR (FLASH_SR_PGERR | FLASH_SR_WRPRTERR) +#define FLASH_SR_EOP BIT(5) +#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) +#define FLASH_CR_PG BIT(0) +#define FLASH_CR_PER BIT(1) +#define FLASH_CR_OPTPG BIT(4) +#define FLASH_CR_OPTER BIT(5) +#define FLASH_CR_STRT BIT(6) +#define FLASH_CR_LOCK BIT(7) +#define FLASH_CR_OPTWRE BIT(9) +#define FLASH_CR_OBL_LAUNCH BIT(13) +#define STM32_FLASH_OPT_LOCKED (!(STM32_FLASH_CR & FLASH_CR_OPTWRE)) +#define STM32_FLASH_AR REG32(STM32_FLASH_REGS_BASE + 0x14) +#define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c) +#define STM32_FLASH_OBR_RDP_MASK (3 << 1) +#define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20) + +#define STM32_OPTB_RDP_OFF 0x00 +#define STM32_OPTB_USER_OFF 0x02 +#define STM32_OPTB_WRP_OFF(n) (0x08 + (n & 3) * 2) +#define STM32_OPTB_WRP01 0x08 +#define STM32_OPTB_WRP23 0x0c + +#define STM32_OPTB_COMPL_SHIFT 8 /* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) +#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) +#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) +#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) +#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) +#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) +#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) #define EXTI_RTC_ALR_EVENT BIT(17) /* --- ADC --- */ #ifdef CHIP_VARIANT_STM32F373 -#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC_CR2_ADON BIT(0) -#define STM32_ADC_CR2_CONT BIT(1) -#define STM32_ADC_CR2_CAL BIT(2) -#define STM32_ADC_CR2_RSTCAL BIT(3) -#define STM32_ADC_CR2_ALIGN BIT(11) -#define STM32_ADC_CR2_SWSTART BIT(30) -#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) -#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) -#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) -#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24) -#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4) -#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x2C) -#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x30) -#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x34) -#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38) -#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4) -#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C) +#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) +#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) +#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) +#define STM32_ADC_CR2_ADON BIT(0) +#define STM32_ADC_CR2_CONT BIT(1) +#define STM32_ADC_CR2_CAL BIT(2) +#define STM32_ADC_CR2_RSTCAL BIT(3) +#define STM32_ADC_CR2_ALIGN BIT(11) +#define STM32_ADC_CR2_SWSTART BIT(30) +#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) +#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) +#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) +#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24) +#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28) +#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4) +#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x2C) +#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x30) +#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x34) +#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38) +#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4) +#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C) #endif /* --- Comparators --- */ -#define STM32_COMP_CSR REG32(STM32_COMP_BASE + 0x1C) +#define STM32_COMP_CSR REG32(STM32_COMP_BASE + 0x1C) -#define STM32_COMP_CMP2LOCK BIT(31) -#define STM32_COMP_CMP2OUT BIT(30) -#define STM32_COMP_CMP2HYST_HI (3 << 28) -#define STM32_COMP_CMP2HYST_MED (2 << 28) -#define STM32_COMP_CMP2HYST_LOW (1 << 28) -#define STM32_COMP_CMP2HYST_NO (0 << 28) -#define STM32_COMP_CMP2POL BIT(27) +#define STM32_COMP_CMP2LOCK BIT(31) +#define STM32_COMP_CMP2OUT BIT(30) +#define STM32_COMP_CMP2HYST_HI (3 << 28) +#define STM32_COMP_CMP2HYST_MED (2 << 28) +#define STM32_COMP_CMP2HYST_LOW (1 << 28) +#define STM32_COMP_CMP2HYST_NO (0 << 28) +#define STM32_COMP_CMP2POL BIT(27) #define STM32_COMP_CMP2OUTSEL_TIM3_OCR (7 << 24) #define STM32_COMP_CMP2OUTSEL_TIM3_IC1 (6 << 24) @@ -646,32 +639,32 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_COMP_CMP2OUTSEL_TIM1_IC1 (2 << 24) #define STM32_COMP_CMP2OUTSEL_TIM1_BRK (1 << 24) #endif -#define STM32_COMP_CMP2OUTSEL_NONE (0 << 24) -#define STM32_COMP_WNDWEN BIT(23) - -#define STM32_COMP_CMP2INSEL_MASK (7 << 20) -#define STM32_COMP_CMP2INSEL_INM7 (6 << 20) /* STM32F373 only */ -#define STM32_COMP_CMP2INSEL_INM6 (6 << 20) -#define STM32_COMP_CMP2INSEL_INM5 (5 << 20) -#define STM32_COMP_CMP2INSEL_INM4 (4 << 20) -#define STM32_COMP_CMP2INSEL_VREF (3 << 20) -#define STM32_COMP_CMP2INSEL_VREF34 (2 << 20) -#define STM32_COMP_CMP2INSEL_VREF12 (1 << 20) -#define STM32_COMP_CMP2INSEL_VREF14 (0 << 20) - -#define STM32_COMP_CMP2MODE_VLSPEED (3 << 18) -#define STM32_COMP_CMP2MODE_LSPEED (2 << 18) -#define STM32_COMP_CMP2MODE_MSPEED (1 << 18) -#define STM32_COMP_CMP2MODE_HSPEED (0 << 18) -#define STM32_COMP_CMP2EN BIT(16) - -#define STM32_COMP_CMP1LOCK BIT(15) -#define STM32_COMP_CMP1OUT BIT(14) -#define STM32_COMP_CMP1HYST_HI (3 << 12) -#define STM32_COMP_CMP1HYST_MED (2 << 12) -#define STM32_COMP_CMP1HYST_LOW (1 << 12) -#define STM32_COMP_CMP1HYST_NO (0 << 12) -#define STM32_COMP_CMP1POL BIT(11) +#define STM32_COMP_CMP2OUTSEL_NONE (0 << 24) +#define STM32_COMP_WNDWEN BIT(23) + +#define STM32_COMP_CMP2INSEL_MASK (7 << 20) +#define STM32_COMP_CMP2INSEL_INM7 (6 << 20) /* STM32F373 only */ +#define STM32_COMP_CMP2INSEL_INM6 (6 << 20) +#define STM32_COMP_CMP2INSEL_INM5 (5 << 20) +#define STM32_COMP_CMP2INSEL_INM4 (4 << 20) +#define STM32_COMP_CMP2INSEL_VREF (3 << 20) +#define STM32_COMP_CMP2INSEL_VREF34 (2 << 20) +#define STM32_COMP_CMP2INSEL_VREF12 (1 << 20) +#define STM32_COMP_CMP2INSEL_VREF14 (0 << 20) + +#define STM32_COMP_CMP2MODE_VLSPEED (3 << 18) +#define STM32_COMP_CMP2MODE_LSPEED (2 << 18) +#define STM32_COMP_CMP2MODE_MSPEED (1 << 18) +#define STM32_COMP_CMP2MODE_HSPEED (0 << 18) +#define STM32_COMP_CMP2EN BIT(16) + +#define STM32_COMP_CMP1LOCK BIT(15) +#define STM32_COMP_CMP1OUT BIT(14) +#define STM32_COMP_CMP1HYST_HI (3 << 12) +#define STM32_COMP_CMP1HYST_MED (2 << 12) +#define STM32_COMP_CMP1HYST_LOW (1 << 12) +#define STM32_COMP_CMP1HYST_NO (0 << 12) +#define STM32_COMP_CMP1POL BIT(11) #ifdef CHIP_VARIANT_STM32F373 #define STM32_COMP_CMP1OUTSEL_TIM5_OCR (7 << 8) @@ -690,25 +683,24 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_COMP_CMP1OUTSEL_TIM1_IC1 (2 << 8) #define STM32_COMP_CMP1OUTSEL_TIM1_BRK (1 << 8) #endif -#define STM32_COMP_CMP1OUTSEL_NONE (0 << 8) - -#define STM32_COMP_CMP1INSEL_MASK (7 << 4) -#define STM32_COMP_CMP1INSEL_INM7 (7 << 4) /* STM32F373 only */ -#define STM32_COMP_CMP1INSEL_INM6 (6 << 4) -#define STM32_COMP_CMP1INSEL_INM5 (5 << 4) -#define STM32_COMP_CMP1INSEL_INM4 (4 << 4) -#define STM32_COMP_CMP1INSEL_VREF (3 << 4) -#define STM32_COMP_CMP1INSEL_VREF34 (2 << 4) -#define STM32_COMP_CMP1INSEL_VREF12 (1 << 4) -#define STM32_COMP_CMP1INSEL_VREF14 (0 << 4) - -#define STM32_COMP_CMP1MODE_VLSPEED (3 << 2) -#define STM32_COMP_CMP1MODE_LSPEED (2 << 2) -#define STM32_COMP_CMP1MODE_MSPEED (1 << 2) -#define STM32_COMP_CMP1MODE_HSPEED (0 << 2) -#define STM32_COMP_CMP1SW1 BIT(1) -#define STM32_COMP_CMP1EN BIT(0) - +#define STM32_COMP_CMP1OUTSEL_NONE (0 << 8) + +#define STM32_COMP_CMP1INSEL_MASK (7 << 4) +#define STM32_COMP_CMP1INSEL_INM7 (7 << 4) /* STM32F373 only */ +#define STM32_COMP_CMP1INSEL_INM6 (6 << 4) +#define STM32_COMP_CMP1INSEL_INM5 (5 << 4) +#define STM32_COMP_CMP1INSEL_INM4 (4 << 4) +#define STM32_COMP_CMP1INSEL_VREF (3 << 4) +#define STM32_COMP_CMP1INSEL_VREF34 (2 << 4) +#define STM32_COMP_CMP1INSEL_VREF12 (1 << 4) +#define STM32_COMP_CMP1INSEL_VREF14 (0 << 4) + +#define STM32_COMP_CMP1MODE_VLSPEED (3 << 2) +#define STM32_COMP_CMP1MODE_LSPEED (2 << 2) +#define STM32_COMP_CMP1MODE_MSPEED (1 << 2) +#define STM32_COMP_CMP1MODE_HSPEED (0 << 2) +#define STM32_COMP_CMP1SW1 BIT(1) +#define STM32_COMP_CMP1EN BIT(0) /* --- DMA --- */ @@ -779,11 +771,11 @@ enum dma_channel { /* Registers for a single channel of the DMA controller */ struct stm32_dma_chan { - uint32_t ccr; /* Control */ - uint32_t cndtr; /* Number of data to transfer */ - uint32_t cpar; /* Peripheral address */ - uint32_t cmar; /* Memory address */ - uint32_t reserved; + uint32_t ccr; /* Control */ + uint32_t cndtr; /* Number of data to transfer */ + uint32_t cpar; /* Peripheral address */ + uint32_t cmar; /* Memory address */ + uint32_t reserved; }; /* Always use stm32_dma_chan_t so volatile keyword is included! */ @@ -794,8 +786,8 @@ typedef stm32_dma_chan_t dma_chan_t; /* Registers for the DMA controller */ struct stm32_dma_regs { - uint32_t isr; - uint32_t ifcr; + uint32_t isr; + uint32_t ifcr; stm32_dma_chan_t chan[STM32_DMAC_COUNT]; }; @@ -804,210 +796,130 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - -#define STM32_DMA_CCR_CHANNEL(channel) (0) +#define STM32_DMA_CCR_CHANNEL(channel) (0) #define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE) #define STM32_DMA_REGS(channel) \ ((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS) -#define STM32_DMA_CSELR(channel) \ - REG32(((channel) < STM32_DMAC_PER_CTLR ? \ - STM32_DMA1_BASE : STM32_DMA2_BASE) + 0xA8) +#define STM32_DMA_CSELR(channel) \ + REG32(((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_BASE : \ + STM32_DMA2_BASE) + \ + 0xA8) /* Bits for DMA controller regs (isr and ifcr) */ -#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) +#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) #define STM32_DMA_ISR_MASK(channel, mask) \ ((mask) << STM32_DMA_CH_OFFSET(channel)) -#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) -#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) -#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) -#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) -#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) - -#define STM32_DMA_GIF BIT(0) -#define STM32_DMA_TCIF BIT(1) -#define STM32_DMA_HTIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_ALL 0xf - -#define STM32_DMA_GET_ISR(channel) \ - ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr = \ - ((STM32_DMA_REGS(channel)->isr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) -#define STM32_DMA_GET_IFCR(channel) \ - ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr = \ - ((STM32_DMA_REGS(channel)->ifcr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) - +#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) +#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) +#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) +#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) +#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) + +#define STM32_DMA_GIF BIT(0) +#define STM32_DMA_TCIF BIT(1) +#define STM32_DMA_HTIF BIT(2) +#define STM32_DMA_TEIF BIT(3) +#define STM32_DMA_ALL 0xf + +#define STM32_DMA_GET_ISR(channel) \ + ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) & \ + STM32_DMA_ALL) +#define STM32_DMA_SET_ISR(channel, val) \ + (STM32_DMA_REGS(channel)->isr = \ + ((STM32_DMA_REGS(channel)->isr & \ + ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) +#define STM32_DMA_GET_IFCR(channel) \ + ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) & \ + STM32_DMA_ALL) +#define STM32_DMA_SET_IFCR(channel, val) \ + (STM32_DMA_REGS(channel)->ifcr = \ + ((STM32_DMA_REGS(channel)->ifcr & \ + ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) /* Bits for DMA channel regs */ -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_TCIE BIT(1) -#define STM32_DMA_CCR_HTIE BIT(2) -#define STM32_DMA_CCR_TEIE BIT(3) -#define STM32_DMA_CCR_DIR BIT(4) -#define STM32_DMA_CCR_CIRC BIT(5) -#define STM32_DMA_CCR_PINC BIT(6) -#define STM32_DMA_CCR_MINC BIT(7) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) -#define STM32_DMA_CCR_PL_LOW (0 << 12) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) -#define STM32_DMA_CCR_PL_HIGH (2 << 12) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) -#define STM32_DMA_CCR_MEM2MEM BIT(14) - +#define STM32_DMA_CCR_EN BIT(0) +#define STM32_DMA_CCR_TCIE BIT(1) +#define STM32_DMA_CCR_HTIE BIT(2) +#define STM32_DMA_CCR_TEIE BIT(3) +#define STM32_DMA_CCR_DIR BIT(4) +#define STM32_DMA_CCR_CIRC BIT(5) +#define STM32_DMA_CCR_PINC BIT(6) +#define STM32_DMA_CCR_MINC BIT(7) +#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) +#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) +#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) +#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) +#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) +#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) +#define STM32_DMA_CCR_PL_LOW (0 << 12) +#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) +#define STM32_DMA_CCR_PL_HIGH (2 << 12) +#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) +#define STM32_DMA_CCR_MEM2MEM BIT(14) /* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) +#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) + +#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) +#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) +#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) +#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) + +#define STM32_CRC_CR_RESET BIT(0) +#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) +#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) +#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) +#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) +#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) +#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) +#define STM32_CRC_CR_REV_IN_WORD (3 << 5) +#define STM32_CRC_CR_REV_OUT BIT(7) /* --- PMSE --- */ -#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) -#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) -#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) -#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) -#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) -#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) -#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) -#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x) * 4) -#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) -#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) -#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) -#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) -#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) -#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) -#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) -#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) -#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) -#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) -#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) - -/* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) +#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) +#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) +#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) +#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) +#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) +#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) +#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) +#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x)*4) +#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) +#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) +#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) +#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) +#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) +#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) +#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) +#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) +#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) +#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) +#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) /* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) +#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) +#define STM32_RNG_CR_RNGEN BIT(2) +#define STM32_RNG_CR_IE BIT(3) +#define STM32_RNG_CR_CED BIT(5) +#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) +#define STM32_RNG_SR_DRDY BIT(0) +#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) /* --- AXI interconnect --- */ /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) +#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x)) +#define WRITE_ISS_OVERRIDE BIT(1) +#define READ_ISS_OVERRIDE BIT(0) /* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) +#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) +#define STM32_UNIQUE_ID_LENGTH (3 * 4) #endif /* !__ASSEMBLER__ */ diff --git a/chip/stm32/registers-stm32f4.h b/chip/stm32/registers-stm32f4.h index 12bfe31063..a415b80d5c 100644 --- a/chip/stm32/registers-stm32f4.h +++ b/chip/stm32/registers-stm32f4.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -22,104 +22,103 @@ #endif /* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_TAMPER_STAMP 2 -#define STM32_IRQ_RTC_WAKEUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#define STM32_IRQ_USB_HP 19 -#define STM32_IRQ_USB_LP 20 - -#define STM32_IRQ_ADC1 18 /* STM32L4 only */ -#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ -#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ -#define STM32_IRQ_DAC 21 -#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ - -#define STM32_IRQ_COMP 22 - -#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_LCD 24 /* STM32L15X only */ -#define STM32_IRQ_TIM15 24 /* STM32F373 only */ +#define STM32_IRQ_WWDG 0 +#define STM32_IRQ_PVD 1 +#define STM32_IRQ_TAMPER_STAMP 2 +#define STM32_IRQ_RTC_WAKEUP 3 +#define STM32_IRQ_FLASH 4 +#define STM32_IRQ_RCC 5 +#define STM32_IRQ_EXTI0 6 +#define STM32_IRQ_EXTI1 7 +#define STM32_IRQ_EXTI2 8 +#define STM32_IRQ_EXTI3 9 +#define STM32_IRQ_EXTI4 10 +#define STM32_IRQ_DMA_CHANNEL_1 11 +#define STM32_IRQ_DMA_CHANNEL_2 12 +#define STM32_IRQ_DMA_CHANNEL_3 13 +#define STM32_IRQ_DMA_CHANNEL_4 14 +#define STM32_IRQ_DMA_CHANNEL_5 15 +#define STM32_IRQ_DMA_CHANNEL_6 16 +#define STM32_IRQ_DMA_CHANNEL_7 17 +#define STM32_IRQ_USB_HP 19 +#define STM32_IRQ_USB_LP 20 + +#define STM32_IRQ_ADC1 18 /* STM32L4 only */ +#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ +#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ +#define STM32_IRQ_DAC 21 +#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ + +#define STM32_IRQ_COMP 22 + +#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ +#define STM32_IRQ_EXTI9_5 23 +#define STM32_IRQ_LCD 24 /* STM32L15X only */ +#define STM32_IRQ_TIM15 24 /* STM32F373 only */ #if defined(CHIP_VARIANT_STM32F412) -#define STM32_IRQ_TIM9 24 /* STM32F412 only */ +#define STM32_IRQ_TIM9 24 /* STM32F412 only */ #else -#define STM32_IRQ_TIM9 25 /* STM32L15X only */ +#define STM32_IRQ_TIM9 25 /* STM32L15X only */ #endif -#define STM32_IRQ_TIM16 25 /* STM32F373 only */ -#define STM32_IRQ_TIM10 26 /* STM32L15X only */ -#define STM32_IRQ_TIM17 26 /* STM32F373 only */ -#define STM32_IRQ_TIM11 27 /* STM32L15X only */ -#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_TIM3 29 -#define STM32_IRQ_TIM4 30 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ -#define STM32_IRQ_CEC 42 /* STM32F373 only */ -#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ -#define STM32_IRQ_TIM12 43 /* STM32F373 only */ -#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ -#define STM32_IRQ_TIM13 44 /* STM32F373 only */ -#define STM32_IRQ_TIM14 45 /* STM32F373 only */ -#define STM32_IRQ_TIM5 50 /* STM32F373 */ -#define STM32_IRQ_SPI3 51 /* STM32F373 */ -#define STM32_IRQ_USART4 52 /* STM32F446 only */ -#define STM32_IRQ_USART5 53 /* STM32F446 only */ -#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ -#define STM32_IRQ_TIM7 55 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ +#define STM32_IRQ_TIM16 25 /* STM32F373 only */ +#define STM32_IRQ_TIM10 26 /* STM32L15X only */ +#define STM32_IRQ_TIM17 26 /* STM32F373 only */ +#define STM32_IRQ_TIM11 27 /* STM32L15X only */ +#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ +#define STM32_IRQ_TIM2 28 +#define STM32_IRQ_TIM3 29 +#define STM32_IRQ_TIM4 30 +#define STM32_IRQ_I2C1_EV 31 +#define STM32_IRQ_I2C1_ER 32 +#define STM32_IRQ_I2C2_EV 33 +#define STM32_IRQ_I2C2_ER 34 +#define STM32_IRQ_SPI1 35 +#define STM32_IRQ_SPI2 36 +#define STM32_IRQ_USART1 37 +#define STM32_IRQ_USART2 38 +#define STM32_IRQ_USART3 39 +#define STM32_IRQ_EXTI15_10 40 +#define STM32_IRQ_RTC_ALARM 41 +#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ +#define STM32_IRQ_CEC 42 /* STM32F373 only */ +#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ +#define STM32_IRQ_TIM12 43 /* STM32F373 only */ +#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ +#define STM32_IRQ_TIM13 44 /* STM32F373 only */ +#define STM32_IRQ_TIM14 45 /* STM32F373 only */ +#define STM32_IRQ_TIM5 50 /* STM32F373 */ +#define STM32_IRQ_SPI3 51 /* STM32F373 */ +#define STM32_IRQ_USART4 52 /* STM32F446 only */ +#define STM32_IRQ_USART5 53 /* STM32F446 only */ +#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ +#define STM32_IRQ_TIM7 55 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ /* if MISC_REMAP bits are set */ -#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ -#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ -#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ -#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ -#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ -#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ -#define STM32_IRQ_LPUART 70 /* STM32L4 only */ -#define STM32_IRQ_USART9 70 /* STM32L4 only */ -#define STM32_IRQ_USART6 71 /* STM32F446 only */ -#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ -#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ -#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ -#define STM32_IRQ_TIM19 78 /* STM32F373 only */ -#define STM32_IRQ_AES 79 /* STM32L4 only */ -#define STM32_IRQ_RNG 80 /* STM32L4 only */ -#define STM32_IRQ_FPU 81 /* STM32F373 only */ - +#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ +#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ +#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ +#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ +#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ +#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ +#define STM32_IRQ_LPUART 70 /* STM32L4 only */ +#define STM32_IRQ_USART9 70 /* STM32L4 only */ +#define STM32_IRQ_USART6 71 /* STM32F446 only */ +#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ +#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ +#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ +#define STM32_IRQ_TIM19 78 /* STM32F373 only */ +#define STM32_IRQ_AES 79 /* STM32L4 only */ +#define STM32_IRQ_RNG 80 /* STM32L4 only */ +#define STM32_IRQ_FPU 81 /* STM32F373 only */ /* To simplify code generation, define DMA channel 9..10 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 +#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 +#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 +#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 +#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 /* aliases for easier code sharing */ #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV @@ -134,279 +133,276 @@ * STM32F4 introduces a concept of DMA stream to allow * fine allocation of a stream to a channel. */ -#define STM32_IRQ_DMA1_STREAM0 11 -#define STM32_IRQ_DMA1_STREAM1 12 -#define STM32_IRQ_DMA1_STREAM2 13 -#define STM32_IRQ_DMA1_STREAM3 14 -#define STM32_IRQ_DMA1_STREAM4 15 -#define STM32_IRQ_DMA1_STREAM5 16 -#define STM32_IRQ_DMA1_STREAM6 17 -#define STM32_IRQ_DMA1_STREAM7 47 -#define STM32_IRQ_DMA2_STREAM0 56 -#define STM32_IRQ_DMA2_STREAM1 57 -#define STM32_IRQ_DMA2_STREAM2 58 -#define STM32_IRQ_DMA2_STREAM3 59 -#define STM32_IRQ_DMA2_STREAM4 60 -#define STM32_IRQ_DMA2_STREAM5 68 -#define STM32_IRQ_DMA2_STREAM6 69 -#define STM32_IRQ_DMA2_STREAM7 70 - -#define STM32_IRQ_OTG_HS_WKUP 76 -#define STM32_IRQ_OTG_HS_EP1_IN 75 -#define STM32_IRQ_OTG_HS_EP1_OUT 74 -#define STM32_IRQ_OTG_HS 77 -#define STM32_IRQ_OTG_FS 67 -#define STM32_IRQ_OTG_FS_WKUP 42 +#define STM32_IRQ_DMA1_STREAM0 11 +#define STM32_IRQ_DMA1_STREAM1 12 +#define STM32_IRQ_DMA1_STREAM2 13 +#define STM32_IRQ_DMA1_STREAM3 14 +#define STM32_IRQ_DMA1_STREAM4 15 +#define STM32_IRQ_DMA1_STREAM5 16 +#define STM32_IRQ_DMA1_STREAM6 17 +#define STM32_IRQ_DMA1_STREAM7 47 +#define STM32_IRQ_DMA2_STREAM0 56 +#define STM32_IRQ_DMA2_STREAM1 57 +#define STM32_IRQ_DMA2_STREAM2 58 +#define STM32_IRQ_DMA2_STREAM3 59 +#define STM32_IRQ_DMA2_STREAM4 60 +#define STM32_IRQ_DMA2_STREAM5 68 +#define STM32_IRQ_DMA2_STREAM6 69 +#define STM32_IRQ_DMA2_STREAM7 70 + +#define STM32_IRQ_OTG_HS_WKUP 76 +#define STM32_IRQ_OTG_HS_EP1_IN 75 +#define STM32_IRQ_OTG_HS_EP1_OUT 74 +#define STM32_IRQ_OTG_HS 77 +#define STM32_IRQ_OTG_FS 67 +#define STM32_IRQ_OTG_FS_WKUP 42 /* Peripheral base addresses */ -#define STM32_ADC1_BASE 0x40012000 -#define STM32_ADC_BASE 0x40012300 - -#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ -#define STM32_CRC_BASE 0x40023000 -#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ -#define STM32_DAC_BASE 0x40007400 - - -#define STM32_DBGMCU_BASE 0xE0042000 - -#define STM32_DMA1_BASE 0x40026000 -#define STM32_DMA2_BASE 0x40026400 - -#define STM32_EXTI_BASE 0x40013C00 - -#define STM32_FLASH_REGS_BASE 0x40023c00 - -#define STM32_GPIOA_BASE 0x40020000 -#define STM32_GPIOB_BASE 0x40020400 -#define STM32_GPIOC_BASE 0x40020800 -#define STM32_GPIOD_BASE 0x40020C00 -#define STM32_GPIOE_BASE 0x40021000 -#define STM32_GPIOF_BASE 0x40021400 /* see RM0402/0390 table 1 */ -#define STM32_GPIOG_BASE 0x40021800 -#define STM32_GPIOH_BASE 0x40021C00 - -#define STM32_I2C1_BASE 0x40005400 -#define STM32_I2C2_BASE 0x40005800 -#define STM32_I2C3_BASE 0x40005C00 -#define STM32_I2C4_BASE 0x40006000 - -#define STM32_IWDG_BASE 0x40003000 -#define STM32_LCD_BASE 0x40002400 - -#define STM32_OPTB_BASE 0x1FFFC000 -#define STM32_OTP_BASE 0x1FFF7800 - -#define STM32_PMSE_BASE 0x40013400 -#define STM32_PWR_BASE 0x40007000 - -#define STM32_RCC_BASE 0x40023800 - -#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ -#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ -#define STM32_RTC_BASE 0x40002800 - -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ - -#define STM32_SYSCFG_BASE 0x40013800 - -#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM9_BASE 0x40014000 /* STM32F41x only */ -#define STM32_TIM10_BASE 0x40014400 /* STM32F41x only */ -#define STM32_TIM11_BASE 0x40014800 /* STM32F41x only */ -#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ -#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ -#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 -#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ -#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ - -#define STM32_UNIQUE_ID_BASE 0x1fff7a10 - -#define STM32_USART1_BASE 0x40011000 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART5_BASE 0x40005000 -#define STM32_USART6_BASE 0x40011400 - -#define STM32_USB_CAN_SRAM_BASE 0x40006000 -#define STM32_USB_FS_BASE 0x40005C00 - -#define STM32_WWDG_BASE 0x40002C00 - +#define STM32_ADC1_BASE 0x40012000 +#define STM32_ADC_BASE 0x40012300 + +#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ +#define STM32_CRC_BASE 0x40023000 +#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ +#define STM32_DAC_BASE 0x40007400 + +#define STM32_DBGMCU_BASE 0xE0042000 + +#define STM32_DMA1_BASE 0x40026000 +#define STM32_DMA2_BASE 0x40026400 + +#define STM32_EXTI_BASE 0x40013C00 + +#define STM32_FLASH_REGS_BASE 0x40023c00 + +#define STM32_GPIOA_BASE 0x40020000 +#define STM32_GPIOB_BASE 0x40020400 +#define STM32_GPIOC_BASE 0x40020800 +#define STM32_GPIOD_BASE 0x40020C00 +#define STM32_GPIOE_BASE 0x40021000 +#define STM32_GPIOF_BASE 0x40021400 /* see RM0402/0390 table 1 */ +#define STM32_GPIOG_BASE 0x40021800 +#define STM32_GPIOH_BASE 0x40021C00 + +#define STM32_I2C1_BASE 0x40005400 +#define STM32_I2C2_BASE 0x40005800 +#define STM32_I2C3_BASE 0x40005C00 +#define STM32_I2C4_BASE 0x40006000 + +#define STM32_IWDG_BASE 0x40003000 +#define STM32_LCD_BASE 0x40002400 + +#define STM32_OPTB_BASE 0x1FFFC000 +#define STM32_OTP_BASE 0x1FFF7800 + +#define STM32_PMSE_BASE 0x40013400 +#define STM32_PWR_BASE 0x40007000 + +#define STM32_RCC_BASE 0x40023800 + +#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ +#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ +#define STM32_RTC_BASE 0x40002800 + +#define STM32_SPI1_BASE 0x40013000 +#define STM32_SPI2_BASE 0x40003800 +#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ + +#define STM32_SYSCFG_BASE 0x40013800 + +#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ +#define STM32_TIM2_BASE 0x40000000 +#define STM32_TIM3_BASE 0x40000400 +#define STM32_TIM4_BASE 0x40000800 +#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ +#define STM32_TIM6_BASE 0x40001000 +#define STM32_TIM7_BASE 0x40001400 +#define STM32_TIM9_BASE 0x40014000 /* STM32F41x only */ +#define STM32_TIM10_BASE 0x40014400 /* STM32F41x only */ +#define STM32_TIM11_BASE 0x40014800 /* STM32F41x only */ +#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ +#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ +#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ +#define STM32_TIM15_BASE 0x40014000 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ +#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ + +#define STM32_UNIQUE_ID_BASE 0x1fff7a10 + +#define STM32_USART1_BASE 0x40011000 +#define STM32_USART2_BASE 0x40004400 +#define STM32_USART3_BASE 0x40004800 +#define STM32_USART4_BASE 0x40004c00 +#define STM32_USART5_BASE 0x40005000 +#define STM32_USART6_BASE 0x40011400 + +#define STM32_USB_CAN_SRAM_BASE 0x40006000 +#define STM32_USB_FS_BASE 0x40005C00 + +#define STM32_WWDG_BASE 0x40002C00 #ifndef __ASSEMBLER__ /* Register definitions */ /* --- USART --- */ -#define STM32_USART_SR(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) -#define STM32_USART_DR(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_UE BIT(13) -#define STM32_USART_CR1_OVER8 BIT(15) /* STM32L only */ -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) /* STM32L only */ -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x18) +#define STM32_USART_SR(base) STM32_USART_REG(base, 0x00) +#define STM32_USART_SR_ORE BIT(3) +#define STM32_USART_SR_RXNE BIT(5) +#define STM32_USART_SR_TC BIT(6) +#define STM32_USART_SR_TXE BIT(7) +#define STM32_USART_DR(base) STM32_USART_REG(base, 0x04) +#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x08) +#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x0C) +#define STM32_USART_CR1_RE BIT(2) +#define STM32_USART_CR1_TE BIT(3) +#define STM32_USART_CR1_RXNEIE BIT(5) +#define STM32_USART_CR1_TCIE BIT(6) +#define STM32_USART_CR1_TXEIE BIT(7) +#define STM32_USART_CR1_PS BIT(9) +#define STM32_USART_CR1_PCE BIT(10) +#define STM32_USART_CR1_M BIT(12) +#define STM32_USART_CR1_UE BIT(13) +#define STM32_USART_CR1_OVER8 BIT(15) /* STM32L only */ +#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x10) +#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x14) +#define STM32_USART_CR3_EIE BIT(0) +#define STM32_USART_CR3_DMAR BIT(6) +#define STM32_USART_CR3_DMAT BIT(7) +#define STM32_USART_CR3_ONEBIT BIT(11) /* STM32L only */ +#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x18) /* register aliases */ -#define STM32_USART_TDR(base) STM32_USART_DR(base) -#define STM32_USART_RDR(base) STM32_USART_DR(base) +#define STM32_USART_TDR(base) STM32_USART_DR(base) +#define STM32_USART_RDR(base) STM32_USART_DR(base) /* --- GPIO --- */ -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) - -#define GPIO_ALT_SYS 0x0 -#define GPIO_ALT_TIM2 0x1 -#define GPIO_ALT_TIM3_4 0x2 -#define GPIO_ALT_TIM9_11 0x3 -#define GPIO_ALT_I2C 0x4 -#define GPIO_ALT_SPI 0x5 -#define GPIO_ALT_SPI3 0x6 -#define GPIO_ALT_USART 0x7 -#define GPIO_ALT_I2C_23 0x9 -#define GPIO_ALT_USB 0xA -#define GPIO_ALT_LCD 0xB -#define GPIO_ALT_RI 0xE -#define GPIO_ALT_EVENTOUT 0xF +#define STM32_GPIO_MODER(b) REG32((b) + 0x00) +#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) +#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) +#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) +#define STM32_GPIO_IDR(b) REG16((b) + 0x10) +#define STM32_GPIO_ODR(b) REG16((b) + 0x14) +#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) +#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) +#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) +#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) + +#define GPIO_ALT_SYS 0x0 +#define GPIO_ALT_TIM2 0x1 +#define GPIO_ALT_TIM3_4 0x2 +#define GPIO_ALT_TIM9_11 0x3 +#define GPIO_ALT_I2C 0x4 +#define GPIO_ALT_SPI 0x5 +#define GPIO_ALT_SPI3 0x6 +#define GPIO_ALT_USART 0x7 +#define GPIO_ALT_I2C_23 0x9 +#define GPIO_ALT_USB 0xA +#define GPIO_ALT_LCD 0xB +#define GPIO_ALT_RI 0xE +#define GPIO_ALT_EVENTOUT 0xF /* --- I2C --- */ -#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_START BIT(8) -#define STM32_I2C_CR1_STOP BIT(9) -#define STM32_I2C_CR1_ACK BIT(10) -#define STM32_I2C_CR1_POS BIT(11) -#define STM32_I2C_CR1_SWRST BIT(15) -#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_ITERREN BIT(8) -#define STM32_I2C_CR2_ITEVTEN BIT(9) -#define STM32_I2C_CR2_ITBUFEN BIT(10) -#define STM32_I2C_CR2_DMAEN BIT(11) -#define STM32_I2C_CR2_LAST BIT(12) -#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR1_B14 BIT(14) -#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_OAR2_ENDUAL BIT(0) -#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_SR1_SB BIT(0) -#define STM32_I2C_SR1_ADDR BIT(1) -#define STM32_I2C_SR1_BTF BIT(2) -#define STM32_I2C_SR1_STOPF BIT(4) -#define STM32_I2C_SR1_RXNE BIT(6) -#define STM32_I2C_SR1_TXE BIT(7) -#define STM32_I2C_SR1_BERR BIT(8) -#define STM32_I2C_SR1_ARLO BIT(9) -#define STM32_I2C_SR1_AF BIT(10) - -#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_SR2_BUSY BIT(1) -#define STM32_I2C_SR2_TRA BIT(2) -#define STM32_I2C_SR2_DUALF BIT(7) - -#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_CCR_DUTY BIT(14) -#define STM32_I2C_CCR_FM BIT(15) -#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) - -#define STM32_FMPI2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) -#define FMPI2C_CR1_PE BIT(0) -#define FMPI2C_CR1_TXDMAEN BIT(14) -#define FMPI2C_CR1_RXDMAEN BIT(15) -#define STM32_FMPI2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) -#define FMPI2C_CR2_RD_WRN BIT(10) -#define FMPI2C_READ 1 -#define FMPI2C_WRITE 0 -#define FMPI2C_CR2_START BIT(13) -#define FMPI2C_CR2_STOP BIT(14) -#define FMPI2C_CR2_NACK BIT(15) -#define FMPI2C_CR2_RELOAD BIT(24) -#define FMPI2C_CR2_AUTOEND BIT(25) -#define FMPI2C_CR2_SADD(addr) ((addr) & 0x3ff) -#define FMPI2C_CR2_SADD_MASK FMPI2C_CR2_SADD(0x3ff) -#define FMPI2C_CR2_SIZE(size) (((size) & 0xff) << 16) -#define FMPI2C_CR2_SIZE_MASK FMPI2C_CR2_SIZE(0xf) -#define STM32_FMPI2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) -#define STM32_FMPI2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) -#define STM32_FMPI2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) -#define TIMINGR_THE_RIGHT_VALUE 0xC0000E12 -#define FMPI2C_TIMINGR_PRESC(val) (((val) & 0xf) << 28) -#define FMPI2C_TIMINGR_SCLDEL(val) (((val) & 0xf) << 20) -#define FMPI2C_TIMINGR_SDADEL(val) (((val) & 0xf) << 16) -#define FMPI2C_TIMINGR_SCLH(val) (((val) & 0xff) << 8) -#define FMPI2C_TIMINGR_SCLL(val) (((val) & 0xff) << 0) -#define STM32_FMPI2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) - -#define STM32_FMPI2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) -#define FMPI2C_ISR_TXE BIT(0) -#define FMPI2C_ISR_TXIS BIT(1) -#define FMPI2C_ISR_RXNE BIT(2) -#define FMPI2C_ISR_ADDR BIT(3) -#define FMPI2C_ISR_NACKF BIT(4) -#define FMPI2C_ISR_STOPF BIT(5) -#define FMPI2C_ISR_BERR BIT(8) -#define FMPI2C_ISR_ARLO BIT(9) -#define FMPI2C_ISR_BUSY BIT(15) -#define STM32_FMPI2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) - -#define STM32_FMPI2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) -#define STM32_FMPI2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) -#define STM32_FMPI2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) +#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) +#define STM32_I2C_CR1_PE BIT(0) +#define STM32_I2C_CR1_START BIT(8) +#define STM32_I2C_CR1_STOP BIT(9) +#define STM32_I2C_CR1_ACK BIT(10) +#define STM32_I2C_CR1_POS BIT(11) +#define STM32_I2C_CR1_SWRST BIT(15) +#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04)) +#define STM32_I2C_CR2_ITERREN BIT(8) +#define STM32_I2C_CR2_ITEVTEN BIT(9) +#define STM32_I2C_CR2_ITBUFEN BIT(10) +#define STM32_I2C_CR2_DMAEN BIT(11) +#define STM32_I2C_CR2_LAST BIT(12) +#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08)) +#define STM32_I2C_OAR1_B14 BIT(14) +#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C)) +#define STM32_I2C_OAR2_ENDUAL BIT(0) +#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10)) +#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14)) +#define STM32_I2C_SR1_SB BIT(0) +#define STM32_I2C_SR1_ADDR BIT(1) +#define STM32_I2C_SR1_BTF BIT(2) +#define STM32_I2C_SR1_STOPF BIT(4) +#define STM32_I2C_SR1_RXNE BIT(6) +#define STM32_I2C_SR1_TXE BIT(7) +#define STM32_I2C_SR1_BERR BIT(8) +#define STM32_I2C_SR1_ARLO BIT(9) +#define STM32_I2C_SR1_AF BIT(10) + +#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18)) +#define STM32_I2C_SR2_BUSY BIT(1) +#define STM32_I2C_SR2_TRA BIT(2) +#define STM32_I2C_SR2_DUALF BIT(7) + +#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) +#define STM32_I2C_CCR_DUTY BIT(14) +#define STM32_I2C_CCR_FM BIT(15) +#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) + +#define STM32_FMPI2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) +#define FMPI2C_CR1_PE BIT(0) +#define FMPI2C_CR1_TXDMAEN BIT(14) +#define FMPI2C_CR1_RXDMAEN BIT(15) +#define STM32_FMPI2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) +#define FMPI2C_CR2_RD_WRN BIT(10) +#define FMPI2C_READ 1 +#define FMPI2C_WRITE 0 +#define FMPI2C_CR2_START BIT(13) +#define FMPI2C_CR2_STOP BIT(14) +#define FMPI2C_CR2_NACK BIT(15) +#define FMPI2C_CR2_RELOAD BIT(24) +#define FMPI2C_CR2_AUTOEND BIT(25) +#define FMPI2C_CR2_SADD(addr) ((addr)&0x3ff) +#define FMPI2C_CR2_SADD_MASK FMPI2C_CR2_SADD(0x3ff) +#define FMPI2C_CR2_SIZE(size) (((size)&0xff) << 16) +#define FMPI2C_CR2_SIZE_MASK FMPI2C_CR2_SIZE(0xf) +#define STM32_FMPI2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) +#define STM32_FMPI2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) +#define STM32_FMPI2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) +#define TIMINGR_THE_RIGHT_VALUE 0xC0000E12 +#define FMPI2C_TIMINGR_PRESC(val) (((val)&0xf) << 28) +#define FMPI2C_TIMINGR_SCLDEL(val) (((val)&0xf) << 20) +#define FMPI2C_TIMINGR_SDADEL(val) (((val)&0xf) << 16) +#define FMPI2C_TIMINGR_SCLH(val) (((val)&0xff) << 8) +#define FMPI2C_TIMINGR_SCLL(val) (((val)&0xff) << 0) +#define STM32_FMPI2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) + +#define STM32_FMPI2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) +#define FMPI2C_ISR_TXE BIT(0) +#define FMPI2C_ISR_TXIS BIT(1) +#define FMPI2C_ISR_RXNE BIT(2) +#define FMPI2C_ISR_ADDR BIT(3) +#define FMPI2C_ISR_NACKF BIT(4) +#define FMPI2C_ISR_STOPF BIT(5) +#define FMPI2C_ISR_BERR BIT(8) +#define FMPI2C_ISR_ARLO BIT(9) +#define FMPI2C_ISR_BUSY BIT(15) +#define STM32_FMPI2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) + +#define STM32_FMPI2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) +#define STM32_FMPI2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) +#define STM32_FMPI2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) /* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) - +#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_CR_HSION BIT(0) -#define STM32_RCC_CR_HSIRDY BIT(1) -#define STM32_RCC_CR_HSEON BIT(16) -#define STM32_RCC_CR_HSERDY BIT(17) -#define STM32_RCC_CR_PLLON BIT(24) -#define STM32_RCC_CR_PLLRDY BIT(25) +#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) +#define STM32_RCC_CR_HSION BIT(0) +#define STM32_RCC_CR_HSIRDY BIT(1) +#define STM32_RCC_CR_HSEON BIT(16) +#define STM32_RCC_CR_HSERDY BIT(17) +#define STM32_RCC_CR_PLLON BIT(24) +#define STM32_RCC_CR_PLLRDY BIT(25) #if defined(CHIP_VARIANT_STM32F446) /* Required or recommended clocks for stm32f446 */ #define STM32F4_PLL_REQ 2000000 #define STM32F4_RTC_REQ 1000000 -#define STM32F4_IO_CLOCK 42000000 +#define STM32F4_IO_CLOCK 42000000 #define STM32F4_USB_REQ 48000000 #define STM32F4_VCO_CLOCK 336000000 #define STM32F4_HSI_CLOCK 16000000 @@ -416,15 +412,15 @@ #define STM32F4_AHB_PRE 0x8 #define STM32F4_APB1_PRE 0x0 #define STM32F4_APB2_PRE 0x0 -#define STM32_FLASH_ACR_LATENCY BIT(0) +#define STM32_FLASH_ACR_LATENCY BIT(0) /* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */ -#define STM32_FLASH_ACR_LATENCY_SLOW 0 +#define STM32_FLASH_ACR_LATENCY_SLOW 0 #elif defined(CHIP_VARIANT_STM32F412) /* Required or recommended clocks for stm32f412 */ #define STM32F4_PLL_REQ 2000000 #define STM32F4_RTC_REQ 1000000 -#define STM32F4_IO_CLOCK 48000000 +#define STM32F4_IO_CLOCK 48000000 #define STM32F4_USB_REQ 48000000 #define STM32F4_VCO_CLOCK 384000000 #define STM32F4_HSI_CLOCK 16000000 @@ -434,15 +430,15 @@ #define STM32F4_AHB_PRE 0x0 #define STM32F4_APB1_PRE 0x4 #define STM32F4_APB2_PRE 0x4 -#define STM32_FLASH_ACR_LATENCY (3 << 0) +#define STM32_FLASH_ACR_LATENCY (3 << 0) /* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */ -#define STM32_FLASH_ACR_LATENCY_SLOW 0 +#define STM32_FLASH_ACR_LATENCY_SLOW 0 #elif defined(CHIP_VARIANT_STM32F411) /* Required or recommended clocks for stm32f411 */ #define STM32F4_PLL_REQ 2000000 #define STM32F4_RTC_REQ 1000000 -#define STM32F4_IO_CLOCK 48000000 +#define STM32F4_IO_CLOCK 48000000 #define STM32F4_USB_REQ 48000000 #define STM32F4_VCO_CLOCK 384000000 #define STM32F4_HSI_CLOCK 16000000 @@ -452,204 +448,205 @@ #define STM32F4_AHB_PRE 0x8 #define STM32F4_APB1_PRE 0x0 #define STM32F4_APB2_PRE 0x0 -#define STM32_FLASH_ACR_LATENCY BIT(0) +#define STM32_FLASH_ACR_LATENCY BIT(0) /* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */ -#define STM32_FLASH_ACR_LATENCY_SLOW 0 +#define STM32_FLASH_ACR_LATENCY_SLOW 0 #elif defined(CHIP_VARIANT_STM32F76X) /* Required or recommended clocks for stm32f767/769 */ #define STM32F4_PLL_REQ 2000000 #define STM32F4_RTC_REQ 1000000 #define STM32F4_IO_CLOCK 45000000 -#define STM32F4_USB_REQ 45000000 /* not compatible with USB, will use PLLSAI */ +#define STM32F4_USB_REQ \ + 45000000 /* not compatible with USB, will use PLLSAI \ + */ #define STM32F4_VCO_CLOCK 360000000 #define STM32F4_HSI_CLOCK 16000000 #define STM32F4_LSI_CLOCK 32000 #define STM32F4_TIMER_CLOCK (STM32F4_IO_CLOCK * 2) -#define STM32F4_PLLP_DIV 2 /* sys = VCO/2 = 180 Mhz */ -#define STM32F4_AHB_PRE 0x0 /* AHB = sysclk = 180 Mhz */ +#define STM32F4_PLLP_DIV 2 /* sys = VCO/2 = 180 Mhz */ +#define STM32F4_AHB_PRE 0x0 /* AHB = sysclk = 180 Mhz */ #define STM32F4_APB1_PRE 0x5 /* APB1 = AHB /4 = 45 Mhz */ #define STM32F4_APB2_PRE 0x5 /* APB2 = AHB /4 = 45 Mhz */ -#define STM32_FLASH_ACR_LATENCY (5 << 0) +#define STM32_FLASH_ACR_LATENCY (5 << 0) /* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */ -#define STM32_FLASH_ACR_LATENCY_SLOW 0 +#define STM32_FLASH_ACR_LATENCY_SLOW 0 #else #error "No valid clocks defined" #endif -#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x04) +#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x04) /* PLL Division factor */ -#define PLLCFGR_PLLM_OFF 0 -#define PLLCFGR_PLLM(val) (((val) & 0x1f) << PLLCFGR_PLLM_OFF) +#define PLLCFGR_PLLM_OFF 0 +#define PLLCFGR_PLLM(val) (((val)&0x1f) << PLLCFGR_PLLM_OFF) /* PLL Multiplication factor */ -#define PLLCFGR_PLLN_OFF 6 -#define PLLCFGR_PLLN(val) (((val) & 0x1ff) << PLLCFGR_PLLN_OFF) +#define PLLCFGR_PLLN_OFF 6 +#define PLLCFGR_PLLN(val) (((val)&0x1ff) << PLLCFGR_PLLN_OFF) /* Main CPU Clock */ -#define PLLCFGR_PLLP_OFF 16 -#define PLLCFGR_PLLP(val) (((val) & 0x3) << PLLCFGR_PLLP_OFF) +#define PLLCFGR_PLLP_OFF 16 +#define PLLCFGR_PLLP(val) (((val)&0x3) << PLLCFGR_PLLP_OFF) -#define PLLCFGR_PLLSRC_HSI (0 << 22) -#define PLLCFGR_PLLSRC_HSE BIT(22) +#define PLLCFGR_PLLSRC_HSI (0 << 22) +#define PLLCFGR_PLLSRC_HSE BIT(22) /* USB OTG FS: Must equal 48MHz */ -#define PLLCFGR_PLLQ_OFF 24 -#define PLLCFGR_PLLQ(val) (((val) & 0xf) << PLLCFGR_PLLQ_OFF) +#define PLLCFGR_PLLQ_OFF 24 +#define PLLCFGR_PLLQ(val) (((val)&0xf) << PLLCFGR_PLLQ_OFF) /* SYSTEM */ -#define PLLCFGR_PLLR_OFF 28 -#define PLLCFGR_PLLR(val) (((val) & 0x7) << PLLCFGR_PLLR_OFF) - -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_CFGR_SW_HSI (0 << 0) -#define STM32_RCC_CFGR_SW_HSE (1 << 0) -#define STM32_RCC_CFGR_SW_PLL (2 << 0) -#define STM32_RCC_CFGR_SW_PLL_R (3 << 0) -#define STM32_RCC_CFGR_SW_MASK (3 << 0) -#define STM32_RCC_CFGR_SWS_HSI (0 << 2) -#define STM32_RCC_CFGR_SWS_HSE (1 << 2) -#define STM32_RCC_CFGR_SWS_PLL (2 << 2) -#define STM32_RCC_CFGR_SWS_PLL_R (3 << 2) -#define STM32_RCC_CFGR_SWS_MASK (3 << 2) +#define PLLCFGR_PLLR_OFF 28 +#define PLLCFGR_PLLR(val) (((val)&0x7) << PLLCFGR_PLLR_OFF) + +#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) +#define STM32_RCC_CFGR_SW_HSI (0 << 0) +#define STM32_RCC_CFGR_SW_HSE (1 << 0) +#define STM32_RCC_CFGR_SW_PLL (2 << 0) +#define STM32_RCC_CFGR_SW_PLL_R (3 << 0) +#define STM32_RCC_CFGR_SW_MASK (3 << 0) +#define STM32_RCC_CFGR_SWS_HSI (0 << 2) +#define STM32_RCC_CFGR_SWS_HSE (1 << 2) +#define STM32_RCC_CFGR_SWS_PLL (2 << 2) +#define STM32_RCC_CFGR_SWS_PLL_R (3 << 2) +#define STM32_RCC_CFGR_SWS_MASK (3 << 2) /* AHB Prescalar: nonlinear values, look up in RM0390 */ -#define CFGR_HPRE_OFF 4 -#define CFGR_HPRE(val) (((val) & 0xf) << CFGR_HPRE_OFF) +#define CFGR_HPRE_OFF 4 +#define CFGR_HPRE(val) (((val)&0xf) << CFGR_HPRE_OFF) /* APB1 Low Speed Prescalar < 45MHz */ -#define CFGR_PPRE1_OFF 10 -#define CFGR_PPRE1(val) (((val) & 0x7) << CFGR_PPRE1_OFF) +#define CFGR_PPRE1_OFF 10 +#define CFGR_PPRE1(val) (((val)&0x7) << CFGR_PPRE1_OFF) /* APB2 High Speed Prescalar < 90MHz */ -#define CFGR_PPRE2_OFF 13 -#define CFGR_PPRE2(val) (((val) & 0x7) << CFGR_PPRE2_OFF) +#define CFGR_PPRE2_OFF 13 +#define CFGR_PPRE2(val) (((val)&0x7) << CFGR_PPRE2_OFF) /* RTC CLock: Must equal 1MHz */ -#define CFGR_RTCPRE_OFF 16 -#define CFGR_RTCPRE(val) (((val) & 0x1f) << CFGR_RTCPRE_OFF) - -#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C) -#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x10) -#define RCC_AHB1RSTR_OTGHSRST BIT(29) - -#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x18) - -#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x24) - -#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_AHB1ENR_GPIO_PORTA BIT(0) -#define STM32_RCC_AHB1ENR_GPIO_PORTB BIT(1) -#define STM32_RCC_AHB1ENR_GPIO_PORTC BIT(2) -#define STM32_RCC_AHB1ENR_GPIO_PORTD BIT(3) -#define STM32_RCC_AHB1ENR_GPIO_PORTE BIT(4) -#define STM32_RCC_AHB1ENR_GPIO_PORTF BIT(5) -#define STM32_RCC_AHB1ENR_GPIO_PORTG BIT(6) -#define STM32_RCC_AHB1ENR_GPIO_PORTH BIT(7) -#define STM32_RCC_AHB1ENR_GPIOMASK (0xff << 0) -#define STM32_RCC_AHB1ENR_BKPSRAMEN BIT(18) -#define STM32_RCC_AHB1ENR_DMA1EN BIT(21) -#define STM32_RCC_AHB1ENR_DMA2EN BIT(22) +#define CFGR_RTCPRE_OFF 16 +#define CFGR_RTCPRE(val) (((val)&0x1f) << CFGR_RTCPRE_OFF) + +#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C) +#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x10) +#define RCC_AHB1RSTR_OTGHSRST BIT(29) + +#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x14) +#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x18) + +#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x20) +#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x24) + +#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x30) +#define STM32_RCC_AHB1ENR_GPIO_PORTA BIT(0) +#define STM32_RCC_AHB1ENR_GPIO_PORTB BIT(1) +#define STM32_RCC_AHB1ENR_GPIO_PORTC BIT(2) +#define STM32_RCC_AHB1ENR_GPIO_PORTD BIT(3) +#define STM32_RCC_AHB1ENR_GPIO_PORTE BIT(4) +#define STM32_RCC_AHB1ENR_GPIO_PORTF BIT(5) +#define STM32_RCC_AHB1ENR_GPIO_PORTG BIT(6) +#define STM32_RCC_AHB1ENR_GPIO_PORTH BIT(7) +#define STM32_RCC_AHB1ENR_GPIOMASK (0xff << 0) +#define STM32_RCC_AHB1ENR_BKPSRAMEN BIT(18) +#define STM32_RCC_AHB1ENR_DMA1EN BIT(21) +#define STM32_RCC_AHB1ENR_DMA2EN BIT(22) /* TODO(nsanders): normalize naming.*/ -#define STM32_RCC_HB1_DMA1 BIT(21) -#define STM32_RCC_HB1_DMA2 BIT(22) -#define STM32_RCC_AHB1ENR_OTGHSEN BIT(29) -#define STM32_RCC_AHB1ENR_OTGHSULPIEN BIT(30) - -#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x34) -#define STM32_RCC_AHB2ENR_RNGEN BIT(6) -#define STM32_RCC_AHB2ENR_OTGFSEN BIT(7) -#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x38) - -#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x40) -#define STM32_RCC_PWREN BIT(28) -#define STM32_RCC_I2C1EN BIT(21) -#define STM32_RCC_I2C2EN BIT(22) -#define STM32_RCC_I2C3EN BIT(23) -#define STM32_RCC_FMPI2C4EN BIT(24) - -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x44) -#define STM32_RCC_APB2ENR_ADC1EN BIT(8) /* STM32F4 */ - -#define STM32_RCC_PB2_USART6 BIT(5) -#define STM32_RCC_SYSCFGEN BIT(14) - -#define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x50) -#define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x54) -#define STM32_RCC_AHB3LPENR REG32(STM32_RCC_BASE + 0x58) -#define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x60) -#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x64) - -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x70) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x74) -#define STM32_RCC_CSR_LSION BIT(0) -#define STM32_RCC_CSR_LSIRDY BIT(1) - -#define STM32_RCC_PB2_TIM1 BIT(0) -#define STM32_RCC_PB2_TIM8 BIT(1) -#define STM32_RCC_PB2_TIM9 BIT(16) -#define STM32_RCC_PB2_TIM10 BIT(17) -#define STM32_RCC_PB2_TIM11 BIT(18) - -#define STM32_RCC_DCKCFGR2 REG32(STM32_RCC_BASE + 0x94) -#define DCKCFGR2_FMPI2C1SEL(val) (((val) & 0x3) << 22) -#define DCKCFGR2_FMPI2C1SEL_MASK (0x3 << 22) -#define FMPI2C1SEL_APB 0x0 - -#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00) -#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) -#define STM32_SYSCFG_CMPCR REG32(STM32_SYSCFG_BASE + 0x20) -#define STM32_SYSCFG_CFGR REG32(STM32_SYSCFG_BASE + 0x2C) - +#define STM32_RCC_HB1_DMA1 BIT(21) +#define STM32_RCC_HB1_DMA2 BIT(22) +#define STM32_RCC_AHB1ENR_OTGHSEN BIT(29) +#define STM32_RCC_AHB1ENR_OTGHSULPIEN BIT(30) + +#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x34) +#define STM32_RCC_AHB2ENR_RNGEN BIT(6) +#define STM32_RCC_AHB2ENR_OTGFSEN BIT(7) +#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x38) + +#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x40) +#define STM32_RCC_PWREN BIT(28) +#define STM32_RCC_I2C1EN BIT(21) +#define STM32_RCC_I2C2EN BIT(22) +#define STM32_RCC_I2C3EN BIT(23) +#define STM32_RCC_FMPI2C4EN BIT(24) + +#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x44) +#define STM32_RCC_APB2ENR_ADC1EN BIT(8) /* STM32F4 */ + +#define STM32_RCC_PB2_USART6 BIT(5) +#define STM32_RCC_SYSCFGEN BIT(14) + +#define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x50) +#define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x54) +#define STM32_RCC_AHB3LPENR REG32(STM32_RCC_BASE + 0x58) +#define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x60) +#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x64) + +#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x70) +#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x74) +#define STM32_RCC_CSR_LSION BIT(0) +#define STM32_RCC_CSR_LSIRDY BIT(1) + +#define STM32_RCC_PB2_TIM1 BIT(0) +#define STM32_RCC_PB2_TIM8 BIT(1) +#define STM32_RCC_PB2_TIM9 BIT(16) +#define STM32_RCC_PB2_TIM10 BIT(17) +#define STM32_RCC_PB2_TIM11 BIT(18) + +#define STM32_RCC_DCKCFGR2 REG32(STM32_RCC_BASE + 0x94) +#define DCKCFGR2_FMPI2C1SEL(val) (((val)&0x3) << 22) +#define DCKCFGR2_FMPI2C1SEL_MASK (0x3 << 22) +#define FMPI2C1SEL_APB 0x0 + +#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00) +#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04) +#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) +#define STM32_SYSCFG_CMPCR REG32(STM32_SYSCFG_BASE + 0x20) +#define STM32_SYSCFG_CFGR REG32(STM32_SYSCFG_BASE + 0x2C) /* Peripheral bits for RCC_APB/AHB regs */ -#define STM32_RCC_PB2_USART1 BIT(4) +#define STM32_RCC_PB2_USART1 BIT(4) /* Reset causes definitions */ /* Reset causes in RCC CSR register */ #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG (BIT(30)|BIT(29)) -#define RESET_CAUSE_SFT BIT(28) -#define RESET_CAUSE_POR BIT(27) -#define RESET_CAUSE_PIN BIT(26) -#define RESET_CAUSE_OTHER (BIT(31)|BIT(30)|BIT(29)|BIT(28)| \ - BIT(27)|BIT(26)|BIT(25)) -#define RESET_CAUSE_RMVF BIT(24) +#define RESET_CAUSE_WDG (BIT(30) | BIT(29)) +#define RESET_CAUSE_SFT BIT(28) +#define RESET_CAUSE_POR BIT(27) +#define RESET_CAUSE_PIN BIT(26) +#define RESET_CAUSE_OTHER \ + (BIT(31) | BIT(30) | BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)) +#define RESET_CAUSE_RMVF BIT(24) /* Power cause in PWR CSR register */ #define STM32_PWR_RESET_CAUSE STM32_PWR_CSR -#define RESET_CAUSE_SBF BIT(1) +#define RESET_CAUSE_SBF BIT(1) #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR -#define RESET_CAUSE_SBF_CLR BIT(3) +#define RESET_CAUSE_SBF_CLR BIT(3) /* --- Watchdogs --- */ /* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 80 +#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) +#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) +#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) +#define STM32_RTC_CR_BYPSHAD BIT(5) +#define STM32_RTC_CR_ALRAE BIT(8) +#define STM32_RTC_CR_ALRAIE BIT(12) +#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) +#define STM32_RTC_ISR_ALRAWF BIT(0) +#define STM32_RTC_ISR_RSF BIT(5) +#define STM32_RTC_ISR_INITF BIT(6) +#define STM32_RTC_ISR_INIT BIT(7) +#define STM32_RTC_ISR_ALRAF BIT(8) +#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) +#define STM32_RTC_PRER_A_MASK (0x7f << 16) +#define STM32_RTC_PRER_S_MASK (0x7fff << 0) +#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) +#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) +#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) +#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) +#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) +#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) +#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) +#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) +#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) +#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) +#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) + +#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) +#define STM32_BKP_BYTES 80 /* --- SPI --- */ @@ -666,8 +663,8 @@ struct stm32_spi_regs { unsigned crcpr; unsigned rxcrcr; unsigned txcrcr; - unsigned i2scfgr; /* STM32L only */ - unsigned i2spr; /* STM32L only */ + unsigned i2scfgr; /* STM32L only */ + unsigned i2spr; /* STM32L only */ }; /* Must be volatile, or compiler optimizes out repeated accesses */ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; @@ -677,185 +674,181 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) +#define STM32_SPI_CR1_BIDIMODE BIT(15) +#define STM32_SPI_CR1_BIDIOE BIT(14) +#define STM32_SPI_CR1_CRCEN BIT(13) +#define STM32_SPI_CR1_SSM BIT(9) +#define STM32_SPI_CR1_SSI BIT(8) +#define STM32_SPI_CR1_LSBFIRST BIT(7) +#define STM32_SPI_CR1_SPE BIT(6) +#define STM32_SPI_CR1_BR_DIV64R (5 << 3) +#define STM32_SPI_CR1_BR_DIV4R BIT(3) +#define STM32_SPI_CR1_MSTR BIT(2) +#define STM32_SPI_CR1_CPOL BIT(1) +#define STM32_SPI_CR1_CPHA BIT(0) +#define STM32_SPI_CR2_FRXTH BIT(12) +#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8) +#define STM32_SPI_CR2_TXEIE BIT(7) +#define STM32_SPI_CR2_RXNEIE BIT(6) +#define STM32_SPI_CR2_NSSP BIT(3) +#define STM32_SPI_CR2_SSOE BIT(2) +#define STM32_SPI_CR2_TXDMAEN BIT(1) +#define STM32_SPI_CR2_RXDMAEN BIT(0) + +#define STM32_SPI_SR_RXNE BIT(0) +#define STM32_SPI_SR_TXE BIT(1) +#define STM32_SPI_SR_CRCERR BIT(4) +#define STM32_SPI_SR_BSY BIT(7) +#define STM32_SPI_SR_FRLVL (3 << 9) +#define STM32_SPI_SR_FTLVL (3 << 11) /* --- Debug --- */ -#define STM32_DBGMCU_CR_SLEEP BIT(0) -#define STM32_DBGMCU_CR_STOP BIT(1) -#define STM32_DBGMCU_CR_STBY BIT(2) -#define STM32_DBGMCU_CR_TRACE_MASK (BIT(5)|BIT(6)|BIT(7)) -#define STM32_DBGMCU_CR_TRACE_EN BIT(5) -#define STM32_DBGMCU_CR_TRACE_MODE_ASYNC 0 -#define STM32_DBGMCU_CR_TRACE_MODE_SYNC1 BIT(6) -#define STM32_DBGMCU_CR_TRACE_MODE_SYNC2 BIT(7) -#define STM32_DBGMCU_CR_TRACE_MODE_SYNC4 (BIT(6)|BIT(7)) -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB1FZ_TIM2 BIT(0) -#define STM32_DBGMCU_APB1FZ_TIM3 BIT(1) -#define STM32_DBGMCU_APB1FZ_TIM4 BIT(2) -#define STM32_DBGMCU_APB1FZ_TIM5 BIT(3) -#define STM32_DBGMCU_APB1FZ_TIM6 BIT(4) -#define STM32_DBGMCU_APB1FZ_TIM7 BIT(5) -#define STM32_DBGMCU_APB1FZ_TIM12 BIT(6) -#define STM32_DBGMCU_APB1FZ_TIM13 BIT(7) -#define STM32_DBGMCU_APB1FZ_TIM14 BIT(8) -#define STM32_DBGMCU_APB1FZ_RTC BIT(10) -#define STM32_DBGMCU_APB1FZ_WWDG BIT(11) -#define STM32_DBGMCU_APB1FZ_IWDG BIT(12) -#define STM32_DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT BIT(21) -#define STM32_DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT BIT(22) -#define STM32_DBGMCU_APB1FZ_I2C3_SMBUS_TIMEOUT BIT(23) -#define STM32_DBGMCU_APB1FZ_I2CFMP_SMBUS_TIMEOUT BIT(24) -#define STM32_DBGMCU_APB1FZ_CAN1 BIT(25) -#define STM32_DBGMCU_APB1FZ_CAN2 BIT(26) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) -#define STM32_DBGMCU_APB2FZ_TIM1 BIT(0) -#define STM32_DBGMCU_APB2FZ_TIM8 BIT(1) -#define STM32_DBGMCU_APB2FZ_TIM9 BIT(16) -#define STM32_DBGMCU_APB2FZ_TIM10 BIT(17) -#define STM32_DBGMCU_APB2FZ_TIM11 BIT(18) +#define STM32_DBGMCU_CR_SLEEP BIT(0) +#define STM32_DBGMCU_CR_STOP BIT(1) +#define STM32_DBGMCU_CR_STBY BIT(2) +#define STM32_DBGMCU_CR_TRACE_MASK (BIT(5) | BIT(6) | BIT(7)) +#define STM32_DBGMCU_CR_TRACE_EN BIT(5) +#define STM32_DBGMCU_CR_TRACE_MODE_ASYNC 0 +#define STM32_DBGMCU_CR_TRACE_MODE_SYNC1 BIT(6) +#define STM32_DBGMCU_CR_TRACE_MODE_SYNC2 BIT(7) +#define STM32_DBGMCU_CR_TRACE_MODE_SYNC4 (BIT(6) | BIT(7)) +#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) +#define STM32_DBGMCU_APB1FZ_TIM2 BIT(0) +#define STM32_DBGMCU_APB1FZ_TIM3 BIT(1) +#define STM32_DBGMCU_APB1FZ_TIM4 BIT(2) +#define STM32_DBGMCU_APB1FZ_TIM5 BIT(3) +#define STM32_DBGMCU_APB1FZ_TIM6 BIT(4) +#define STM32_DBGMCU_APB1FZ_TIM7 BIT(5) +#define STM32_DBGMCU_APB1FZ_TIM12 BIT(6) +#define STM32_DBGMCU_APB1FZ_TIM13 BIT(7) +#define STM32_DBGMCU_APB1FZ_TIM14 BIT(8) +#define STM32_DBGMCU_APB1FZ_RTC BIT(10) +#define STM32_DBGMCU_APB1FZ_WWDG BIT(11) +#define STM32_DBGMCU_APB1FZ_IWDG BIT(12) +#define STM32_DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT BIT(21) +#define STM32_DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT BIT(22) +#define STM32_DBGMCU_APB1FZ_I2C3_SMBUS_TIMEOUT BIT(23) +#define STM32_DBGMCU_APB1FZ_I2CFMP_SMBUS_TIMEOUT BIT(24) +#define STM32_DBGMCU_APB1FZ_CAN1 BIT(25) +#define STM32_DBGMCU_APB1FZ_CAN2 BIT(26) +#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) +#define STM32_DBGMCU_APB2FZ_TIM1 BIT(0) +#define STM32_DBGMCU_APB2FZ_TIM8 BIT(1) +#define STM32_DBGMCU_APB2FZ_TIM9 BIT(16) +#define STM32_DBGMCU_APB2FZ_TIM10 BIT(17) +#define STM32_DBGMCU_APB2FZ_TIM11 BIT(18) /* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) -#define STM32_FLASH_ACR_SHIFT 0 -#define STM32_FLASH_ACR_LAT_MASK 0xf -#define STM32_FLASH_ACR_PRFTEN BIT(8) -#define STM32_FLASH_ACR_ICEN BIT(9) -#define STM32_FLASH_ACR_DCEN BIT(10) -#define STM32_FLASH_ACR_ICRST BIT(11) -#define STM32_FLASH_ACR_DCRST BIT(12) -#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define FLASH_OPTKEYR_KEY1 0x08192A3B -#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define FLASH_SR_EOP BIT(0) -#define FLASH_SR_OPERR BIT(1) -#define FLASH_SR_WRPERR BIT(4) -#define FLASH_SR_PGAERR BIT(5) -#define FLASH_SR_PGPERR BIT(6) -#define FLASH_SR_PGSERR BIT(7) -#define FLASH_SR_RDERR BIT(8) -#define FLASH_SR_ALL_ERR \ +#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) +#define STM32_FLASH_ACR_SHIFT 0 +#define STM32_FLASH_ACR_LAT_MASK 0xf +#define STM32_FLASH_ACR_PRFTEN BIT(8) +#define STM32_FLASH_ACR_ICEN BIT(9) +#define STM32_FLASH_ACR_DCEN BIT(10) +#define STM32_FLASH_ACR_ICRST BIT(11) +#define STM32_FLASH_ACR_DCRST BIT(12) +#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) +#define FLASH_KEYR_KEY1 0x45670123 +#define FLASH_KEYR_KEY2 0xCDEF89AB +#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) +#define FLASH_OPTKEYR_KEY1 0x08192A3B +#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F +#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) +#define FLASH_SR_EOP BIT(0) +#define FLASH_SR_OPERR BIT(1) +#define FLASH_SR_WRPERR BIT(4) +#define FLASH_SR_PGAERR BIT(5) +#define FLASH_SR_PGPERR BIT(6) +#define FLASH_SR_PGSERR BIT(7) +#define FLASH_SR_RDERR BIT(8) +#define FLASH_SR_ALL_ERR \ (FLASH_SR_OPERR | FLASH_SR_WRPERR | FLASH_SR_PGAERR | \ FLASH_SR_PGPERR | FLASH_SR_PGSERR | FLASH_SR_RDERR) -#define FLASH_SR_BUSY BIT(16) -#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_MER BIT(2) -#define STM32_FLASH_CR_SNB_OFFSET (3) -#define STM32_FLASH_CR_SNB(sec) \ - (((sec) & 0xf) << STM32_FLASH_CR_SNB_OFFSET) -#define STM32_FLASH_CR_SNB_MASK (STM32_FLASH_CR_SNB(0xf)) -#define STM32_FLASH_CR_PSIZE_OFFSET (8) -#define STM32_FLASH_CR_PSIZE(size) \ - (((size) & 0x3) << STM32_FLASH_CR_PSIZE_OFFSET) -#define STM32_FLASH_CR_PSIZE_MASK (STM32_FLASH_CR_PSIZE(0x3)) -#define FLASH_CR_STRT BIT(16) -#define FLASH_CR_LOCK BIT(31) -#define STM32_FLASH_OPTCR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define FLASH_OPTLOCK BIT(0) -#define FLASH_OPTSTRT BIT(1) -#define STM32_FLASH_BOR_LEV_OFFSET (2) -#define FLASH_OPTCR_RDP_SHIFT (8) -#define FLASH_OPTCR_RDP_MASK (0xFF << FLASH_OPTCR_RDP_SHIFT) -#define FLASH_OPTCR_RDP_LEVEL_0 (0xAA << FLASH_OPTCR_RDP_SHIFT) +#define FLASH_SR_BUSY BIT(16) +#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) +#define FLASH_CR_PG BIT(0) +#define FLASH_CR_PER BIT(1) +#define FLASH_CR_MER BIT(2) +#define STM32_FLASH_CR_SNB_OFFSET (3) +#define STM32_FLASH_CR_SNB(sec) (((sec)&0xf) << STM32_FLASH_CR_SNB_OFFSET) +#define STM32_FLASH_CR_SNB_MASK (STM32_FLASH_CR_SNB(0xf)) +#define STM32_FLASH_CR_PSIZE_OFFSET (8) +#define STM32_FLASH_CR_PSIZE(size) (((size)&0x3) << STM32_FLASH_CR_PSIZE_OFFSET) +#define STM32_FLASH_CR_PSIZE_MASK (STM32_FLASH_CR_PSIZE(0x3)) +#define FLASH_CR_STRT BIT(16) +#define FLASH_CR_LOCK BIT(31) +#define STM32_FLASH_OPTCR REG32(STM32_FLASH_REGS_BASE + 0x14) +#define FLASH_OPTLOCK BIT(0) +#define FLASH_OPTSTRT BIT(1) +#define STM32_FLASH_BOR_LEV_OFFSET (2) +#define FLASH_OPTCR_RDP_SHIFT (8) +#define FLASH_OPTCR_RDP_MASK (0xFF << FLASH_OPTCR_RDP_SHIFT) +#define FLASH_OPTCR_RDP_LEVEL_0 (0xAA << FLASH_OPTCR_RDP_SHIFT) /* RDP Level 1: Anything but 0xAA/0xCC */ -#define FLASH_OPTCR_RDP_LEVEL_1 (0x00 << FLASH_OPTCR_RDP_SHIFT) -#define FLASH_OPTCR_RDP_LEVEL_2 (0xCC << FLASH_OPTCR_RDP_SHIFT) -#define STM32_FLASH_nWRP_OFFSET (16) -#define STM32_FLASH_nWRP(_bank) BIT(_bank + STM32_FLASH_nWRP_OFFSET) -#define STM32_FLASH_nWRP_ALL (0xFF << STM32_FLASH_nWRP_OFFSET) -#define STM32_FLASH_OPT_LOCKED (STM32_FLASH_OPTCR & FLASH_OPTLOCK) - -#define STM32_OPTB_RDP_USER REG32(STM32_OPTB_BASE + 0x00) -#define STM32_OPTB_RDP_OFF 0x00 -#define STM32_OPTB_USER_OFF 0x02 -#define STM32_OPTB_WRP_OFF(n) (0x08 + (n&3) * 2) -#define STM32_OPTB_WP REG32(STM32_OPTB_BASE + 0x08) -#define STM32_OPTB_nWRP(_bank) BIT(_bank) -#define STM32_OPTB_nWRP_ALL (0xFF) - -#define STM32_OPTB_COMPL_SHIFT 8 - -#define STM32_OTP_BLOCK_NB 16 -#define STM32_OTP_BLOCK_SIZE 32 +#define FLASH_OPTCR_RDP_LEVEL_1 (0x00 << FLASH_OPTCR_RDP_SHIFT) +#define FLASH_OPTCR_RDP_LEVEL_2 (0xCC << FLASH_OPTCR_RDP_SHIFT) +#define STM32_FLASH_nWRP_OFFSET (16) +#define STM32_FLASH_nWRP(_bank) BIT(_bank + STM32_FLASH_nWRP_OFFSET) +#define STM32_FLASH_nWRP_ALL (0xFF << STM32_FLASH_nWRP_OFFSET) +#define STM32_FLASH_OPT_LOCKED (STM32_FLASH_OPTCR & FLASH_OPTLOCK) + +#define STM32_OPTB_RDP_USER REG32(STM32_OPTB_BASE + 0x00) +#define STM32_OPTB_RDP_OFF 0x00 +#define STM32_OPTB_USER_OFF 0x02 +#define STM32_OPTB_WRP_OFF(n) (0x08 + (n & 3) * 2) +#define STM32_OPTB_WP REG32(STM32_OPTB_BASE + 0x08) +#define STM32_OPTB_nWRP(_bank) BIT(_bank) +#define STM32_OPTB_nWRP_ALL (0xFF) + +#define STM32_OPTB_COMPL_SHIFT 8 + +#define STM32_OTP_BLOCK_NB 16 +#define STM32_OTP_BLOCK_SIZE 32 #define STM32_OTP_BLOCK_DATA(_block, _offset) \ - (STM32_OTP_BASE + STM32_OTP_BLOCK_SIZE * (_block) + (_offset) * 4) -#define STM32_OTP_UNLOCK_BYTE 0x00 -#define STM32_OTP_LOCK_BYTE 0xFF -#define STM32_OTP_LOCK_BASE \ + (STM32_OTP_BASE + STM32_OTP_BLOCK_SIZE * (_block) + (_offset)*4) +#define STM32_OTP_UNLOCK_BYTE 0x00 +#define STM32_OTP_LOCK_BYTE 0xFF +#define STM32_OTP_LOCK_BASE \ (STM32_OTP_BASE + STM32_OTP_BLOCK_NB * STM32_OTP_BLOCK_SIZE) -#define STM32_OTP_LOCK(_block) \ - (STM32_OTP_LOCK_BASE + ((_block) / 4) * 4) -#define STM32_OPT_LOCK_MASK(_block) ((0xFF << ((_block) % 4) * 8)) +#define STM32_OTP_LOCK(_block) (STM32_OTP_LOCK_BASE + ((_block) / 4) * 4) +#define STM32_OPT_LOCK_MASK(_block) ((0xFF << ((_block) % 4) * 8)) /* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) +#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) +#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) +#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) +#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) +#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) +#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) #define EXTI_RTC_ALR_EVENT BIT(17) /* --- ADC --- */ -#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC_CR2_ADON BIT(0) -#define STM32_ADC_CR2_CONT BIT(1) -#define STM32_ADC_CR2_CAL BIT(2) -#define STM32_ADC_CR2_RSTCAL BIT(3) -#define STM32_ADC_CR2_ALIGN BIT(11) -#define STM32_ADC_CR2_SWSTART BIT(30) -#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) -#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) -#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) -#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24) -#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4) -#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x2C) -#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x30) -#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x34) -#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38) -#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4) -#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C) +#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) +#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) +#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) +#define STM32_ADC_CR2_ADON BIT(0) +#define STM32_ADC_CR2_CONT BIT(1) +#define STM32_ADC_CR2_CAL BIT(2) +#define STM32_ADC_CR2_RSTCAL BIT(3) +#define STM32_ADC_CR2_ALIGN BIT(11) +#define STM32_ADC_CR2_SWSTART BIT(30) +#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) +#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) +#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) +#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24) +#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28) +#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4) +#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x2C) +#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x30) +#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x34) +#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38) +#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4) +#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C) /* --- Comparators --- */ - /* --- DMA --- */ /* * Available DMA streams, numbered from 0. @@ -963,12 +956,12 @@ enum dma_channel { /* Registers for a single stream of a DMA controller */ struct stm32_dma_stream { - uint32_t scr; /* Control */ - uint32_t sndtr; /* Number of data to transfer */ - uint32_t spar; /* Peripheral address */ - uint32_t sm0ar; /* Memory address 0 */ - uint32_t sm1ar; /* address 1 for double buffer */ - uint32_t sfcr; /* FIFO control */ + uint32_t scr; /* Control */ + uint32_t sndtr; /* Number of data to transfer */ + uint32_t spar; /* Peripheral address */ + uint32_t sm0ar; /* Memory address 0 */ + uint32_t sm1ar; /* address 1 for double buffer */ + uint32_t sfcr; /* FIFO control */ }; /* Always use stm32_dma_stream_t so volatile keyword is included! */ @@ -977,12 +970,11 @@ typedef volatile struct stm32_dma_stream stm32_dma_stream_t; /* Common code and header file must use this */ typedef stm32_dma_stream_t dma_chan_t; struct stm32_dma_regs { - uint32_t isr[2]; - uint32_t ifcr[2]; + uint32_t isr[2]; + uint32_t ifcr[2]; stm32_dma_stream_t stream[STM32_DMAS_COUNT]; }; - /* Always use stm32_dma_regs_t so volatile keyword is included! */ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; @@ -993,109 +985,106 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_DMA_REGS(channel) \ ((channel) < STM32_DMAS_COUNT ? STM32_DMA1_REGS : STM32_DMA2_REGS) -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_DMEIE BIT(1) -#define STM32_DMA_CCR_TEIE BIT(2) -#define STM32_DMA_CCR_HTIE BIT(3) -#define STM32_DMA_CCR_TCIE BIT(4) -#define STM32_DMA_CCR_PFCTRL BIT(5) -#define STM32_DMA_CCR_DIR_P2M (0 << 6) -#define STM32_DMA_CCR_DIR_M2P (1 << 6) -#define STM32_DMA_CCR_DIR_M2M (2 << 6) -#define STM32_DMA_CCR_CIRC BIT(8) -#define STM32_DMA_CCR_PINC BIT(9) -#define STM32_DMA_CCR_MINC BIT(10) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 11) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 11) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 11) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 13) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 13) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 13) -#define STM32_DMA_CCR_PINCOS BIT(15) -#define STM32_DMA_CCR_PL_LOW (0 << 16) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 16) -#define STM32_DMA_CCR_PL_HIGH (2 << 16) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 16) -#define STM32_DMA_CCR_DBM BIT(18) -#define STM32_DMA_CCR_CT BIT(19) -#define STM32_DMA_CCR_PBURST(b_len) ((((b_len) - 4) / 4) << 21) -#define STM32_DMA_CCR_MBURST(b_len) ((((b_len) - 4) / 4) << 21) -#define STM32_DMA_CCR_CHANNEL_MASK (0x7 << 25) -#define STM32_DMA_CCR_CHANNEL(channel) ((channel) << 25) -#define STM32_DMA_CCR_RSVD_MASK (0xF0100000) - - -#define STM32_DMA_SFCR_DMDIS BIT(2) -#define STM32_DMA_SFCR_FTH(level) (((level) - 1) << 0) - - -#define STM32_DMA_CH_LOCAL(channel) ((channel) % STM32_DMAS_COUNT) -#define STM32_DMA_CH_LH(channel) \ - ((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1) -#define STM32_DMA_CH_OFFSET(channel) \ +#define STM32_DMA_CCR_EN BIT(0) +#define STM32_DMA_CCR_DMEIE BIT(1) +#define STM32_DMA_CCR_TEIE BIT(2) +#define STM32_DMA_CCR_HTIE BIT(3) +#define STM32_DMA_CCR_TCIE BIT(4) +#define STM32_DMA_CCR_PFCTRL BIT(5) +#define STM32_DMA_CCR_DIR_P2M (0 << 6) +#define STM32_DMA_CCR_DIR_M2P (1 << 6) +#define STM32_DMA_CCR_DIR_M2M (2 << 6) +#define STM32_DMA_CCR_CIRC BIT(8) +#define STM32_DMA_CCR_PINC BIT(9) +#define STM32_DMA_CCR_MINC BIT(10) +#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 11) +#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 11) +#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 11) +#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 13) +#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 13) +#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 13) +#define STM32_DMA_CCR_PINCOS BIT(15) +#define STM32_DMA_CCR_PL_LOW (0 << 16) +#define STM32_DMA_CCR_PL_MEDIUM (1 << 16) +#define STM32_DMA_CCR_PL_HIGH (2 << 16) +#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 16) +#define STM32_DMA_CCR_DBM BIT(18) +#define STM32_DMA_CCR_CT BIT(19) +#define STM32_DMA_CCR_PBURST(b_len) ((((b_len)-4) / 4) << 21) +#define STM32_DMA_CCR_MBURST(b_len) ((((b_len)-4) / 4) << 21) +#define STM32_DMA_CCR_CHANNEL_MASK (0x7 << 25) +#define STM32_DMA_CCR_CHANNEL(channel) ((channel) << 25) +#define STM32_DMA_CCR_RSVD_MASK (0xF0100000) + +#define STM32_DMA_SFCR_DMDIS BIT(2) +#define STM32_DMA_SFCR_FTH(level) (((level)-1) << 0) + +#define STM32_DMA_CH_LOCAL(channel) ((channel) % STM32_DMAS_COUNT) +#define STM32_DMA_CH_LH(channel) ((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1) +#define STM32_DMA_CH_OFFSET(channel) \ (((STM32_DMA_CH_LOCAL(channel) % 4) * 6) + \ - (((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0)) + (((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0)) #define STM32_DMA_CH_GETBITS(channel, val) \ (((val) >> STM32_DMA_CH_OFFSET(channel)) & 0x3f) -#define STM32_DMA_GET_IFCR(channel) \ - (STM32_DMA_CH_GETBITS(channel, \ - STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)])) -#define STM32_DMA_GET_ISR(channel) \ - (STM32_DMA_CH_GETBITS(channel, \ - STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)])) - -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \ - (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \ - ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel))) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \ - (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \ - ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel))) - -#define STM32_DMA_FEIF BIT(0) -#define STM32_DMA_DMEIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_HTIF BIT(4) -#define STM32_DMA_TCIF BIT(5) -#define STM32_DMA_ALL 0x3d - - +#define STM32_DMA_GET_IFCR(channel) \ + (STM32_DMA_CH_GETBITS( \ + channel, \ + STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)])) +#define STM32_DMA_GET_ISR(channel) \ + (STM32_DMA_CH_GETBITS( \ + channel, \ + STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)])) + +#define STM32_DMA_SET_IFCR(channel, val) \ + (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \ + (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \ + ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&0x3f) << STM32_DMA_CH_OFFSET(channel))) +#define STM32_DMA_SET_ISR(channel, val) \ + (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \ + (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \ + ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&0x3f) << STM32_DMA_CH_OFFSET(channel))) + +#define STM32_DMA_FEIF BIT(0) +#define STM32_DMA_DMEIF BIT(2) +#define STM32_DMA_TEIF BIT(3) +#define STM32_DMA_HTIF BIT(4) +#define STM32_DMA_TCIF BIT(5) +#define STM32_DMA_ALL 0x3d /* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 +#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) + +#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) +#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) +#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) +#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) + +#define STM32_CRC_CR_RESET BIT(0) +#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) +#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) +#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) +#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) +#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) +#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) +#define STM32_CRC_CR_REV_IN_WORD (3 << 5) +#define STM32_CRC_CR_REV_OUT BIT(7) + +#define EP_MASK 0x0F0F +#define EP_TX_DTOG 0x0040 +#define EP_TX_MASK 0x0030 #define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 +#define EP_TX_NAK 0x0020 #define EP_TX_STALL 0x0010 #define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 +#define EP_RX_DTOG 0x4000 +#define EP_RX_MASK 0x3000 #define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 +#define EP_RX_NAK 0x2000 #define EP_RX_STALL 0x1000 #define EP_RX_DISAB 0x0000 @@ -1105,28 +1094,27 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) #define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) + STM32_USB_EP(n) = \ + (((STM32_USB_EP(n) & (EP_MASK | (mask))) ^ (val)) | (flags)) /* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) +#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) +#define STM32_RNG_CR_RNGEN BIT(2) +#define STM32_RNG_CR_IE BIT(3) +#define STM32_RNG_CR_CED BIT(5) +#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) +#define STM32_RNG_SR_DRDY BIT(0) +#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) /* --- AXI interconnect --- */ /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) +#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x)) +#define WRITE_ISS_OVERRIDE BIT(1) +#define READ_ISS_OVERRIDE BIT(0) /* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) +#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) +#define STM32_UNIQUE_ID_LENGTH (3 * 4) #endif /* !__ASSEMBLER__ */ diff --git a/chip/stm32/registers-stm32f7.h b/chip/stm32/registers-stm32f7.h index 7c039c9d61..a597cbfe68 100644 --- a/chip/stm32/registers-stm32f7.h +++ b/chip/stm32/registers-stm32f7.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,100 +19,99 @@ #endif /* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_TAMPER_STAMP 2 -#define STM32_IRQ_RTC_WAKEUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#define STM32_IRQ_USB_HP 19 -#define STM32_IRQ_USB_LP 20 - -#define STM32_IRQ_ADC1 18 /* STM32L4 only */ -#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ -#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ -#define STM32_IRQ_DAC 21 -#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ - -#define STM32_IRQ_COMP 22 - -#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_LCD 24 /* STM32L15X only */ -#define STM32_IRQ_TIM15 24 /* STM32F373 only */ -#define STM32_IRQ_TIM9 25 /* STM32L15X only */ -#define STM32_IRQ_TIM16 25 /* STM32F373 only */ -#define STM32_IRQ_TIM10 26 /* STM32L15X only */ -#define STM32_IRQ_TIM17 26 /* STM32F373 only */ -#define STM32_IRQ_TIM11 27 /* STM32L15X only */ -#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_TIM3 29 -#define STM32_IRQ_TIM4 30 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ -#define STM32_IRQ_CEC 42 /* STM32F373 only */ -#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ -#define STM32_IRQ_TIM12 43 /* STM32F373 only */ -#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ -#define STM32_IRQ_TIM13 44 /* STM32F373 only */ -#define STM32_IRQ_TIM14 45 /* STM32F373 only */ -#define STM32_IRQ_TIM5 50 /* STM32F373 */ -#define STM32_IRQ_SPI3 51 /* STM32F373 */ -#define STM32_IRQ_USART4 52 /* STM32F446 only */ -#define STM32_IRQ_USART5 53 /* STM32F446 only */ -#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ -#define STM32_IRQ_TIM7 55 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ +#define STM32_IRQ_WWDG 0 +#define STM32_IRQ_PVD 1 +#define STM32_IRQ_TAMPER_STAMP 2 +#define STM32_IRQ_RTC_WAKEUP 3 +#define STM32_IRQ_FLASH 4 +#define STM32_IRQ_RCC 5 +#define STM32_IRQ_EXTI0 6 +#define STM32_IRQ_EXTI1 7 +#define STM32_IRQ_EXTI2 8 +#define STM32_IRQ_EXTI3 9 +#define STM32_IRQ_EXTI4 10 +#define STM32_IRQ_DMA_CHANNEL_1 11 +#define STM32_IRQ_DMA_CHANNEL_2 12 +#define STM32_IRQ_DMA_CHANNEL_3 13 +#define STM32_IRQ_DMA_CHANNEL_4 14 +#define STM32_IRQ_DMA_CHANNEL_5 15 +#define STM32_IRQ_DMA_CHANNEL_6 16 +#define STM32_IRQ_DMA_CHANNEL_7 17 +#define STM32_IRQ_USB_HP 19 +#define STM32_IRQ_USB_LP 20 + +#define STM32_IRQ_ADC1 18 /* STM32L4 only */ +#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ +#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ +#define STM32_IRQ_DAC 21 +#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ + +#define STM32_IRQ_COMP 22 + +#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ +#define STM32_IRQ_EXTI9_5 23 +#define STM32_IRQ_LCD 24 /* STM32L15X only */ +#define STM32_IRQ_TIM15 24 /* STM32F373 only */ +#define STM32_IRQ_TIM9 25 /* STM32L15X only */ +#define STM32_IRQ_TIM16 25 /* STM32F373 only */ +#define STM32_IRQ_TIM10 26 /* STM32L15X only */ +#define STM32_IRQ_TIM17 26 /* STM32F373 only */ +#define STM32_IRQ_TIM11 27 /* STM32L15X only */ +#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ +#define STM32_IRQ_TIM2 28 +#define STM32_IRQ_TIM3 29 +#define STM32_IRQ_TIM4 30 +#define STM32_IRQ_I2C1_EV 31 +#define STM32_IRQ_I2C1_ER 32 +#define STM32_IRQ_I2C2_EV 33 +#define STM32_IRQ_I2C2_ER 34 +#define STM32_IRQ_SPI1 35 +#define STM32_IRQ_SPI2 36 +#define STM32_IRQ_USART1 37 +#define STM32_IRQ_USART2 38 +#define STM32_IRQ_USART3 39 +#define STM32_IRQ_EXTI15_10 40 +#define STM32_IRQ_RTC_ALARM 41 +#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ +#define STM32_IRQ_CEC 42 /* STM32F373 only */ +#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ +#define STM32_IRQ_TIM12 43 /* STM32F373 only */ +#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ +#define STM32_IRQ_TIM13 44 /* STM32F373 only */ +#define STM32_IRQ_TIM14 45 /* STM32F373 only */ +#define STM32_IRQ_TIM5 50 /* STM32F373 */ +#define STM32_IRQ_SPI3 51 /* STM32F373 */ +#define STM32_IRQ_USART4 52 /* STM32F446 only */ +#define STM32_IRQ_USART5 53 /* STM32F446 only */ +#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ +#define STM32_IRQ_TIM7 55 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ /* if MISC_REMAP bits are set */ -#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ -#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ -#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ -#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ -#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ -#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ -#define STM32_IRQ_LPUART 70 /* STM32L4 only */ -#define STM32_IRQ_USART9 70 /* STM32L4 only */ -#define STM32_IRQ_USART6 71 /* STM32F446 only */ -#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ -#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ -#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ -#define STM32_IRQ_TIM19 78 /* STM32F373 only */ -#define STM32_IRQ_AES 79 /* STM32L4 only */ -#define STM32_IRQ_RNG 80 /* STM32L4 only */ -#define STM32_IRQ_FPU 81 /* STM32F373 only */ - +#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ +#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ +#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ +#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ +#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ +#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ +#define STM32_IRQ_LPUART 70 /* STM32L4 only */ +#define STM32_IRQ_USART9 70 /* STM32L4 only */ +#define STM32_IRQ_USART6 71 /* STM32F446 only */ +#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ +#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ +#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ +#define STM32_IRQ_TIM19 78 /* STM32F373 only */ +#define STM32_IRQ_AES 79 /* STM32L4 only */ +#define STM32_IRQ_RNG 80 /* STM32L4 only */ +#define STM32_IRQ_FPU 81 /* STM32F373 only */ /* To simplify code generation, define DMA channel 9..10 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 +#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 +#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 +#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 +#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 /* aliases for easier code sharing */ #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV @@ -123,464 +122,462 @@ * STM32F4 introduces a concept of DMA stream to allow * fine allocation of a stream to a channel. */ -#define STM32_IRQ_DMA1_STREAM0 11 -#define STM32_IRQ_DMA1_STREAM1 12 -#define STM32_IRQ_DMA1_STREAM2 13 -#define STM32_IRQ_DMA1_STREAM3 14 -#define STM32_IRQ_DMA1_STREAM4 15 -#define STM32_IRQ_DMA1_STREAM5 16 -#define STM32_IRQ_DMA1_STREAM6 17 -#define STM32_IRQ_DMA1_STREAM7 47 -#define STM32_IRQ_DMA2_STREAM0 56 -#define STM32_IRQ_DMA2_STREAM1 57 -#define STM32_IRQ_DMA2_STREAM2 58 -#define STM32_IRQ_DMA2_STREAM3 59 -#define STM32_IRQ_DMA2_STREAM4 60 -#define STM32_IRQ_DMA2_STREAM5 68 -#define STM32_IRQ_DMA2_STREAM6 69 -#define STM32_IRQ_DMA2_STREAM7 70 - -#define STM32_IRQ_OTG_HS_WKUP 76 -#define STM32_IRQ_OTG_HS_EP1_IN 75 -#define STM32_IRQ_OTG_HS_EP1_OUT 74 -#define STM32_IRQ_OTG_HS 77 -#define STM32_IRQ_OTG_FS 67 -#define STM32_IRQ_OTG_FS_WKUP 42 +#define STM32_IRQ_DMA1_STREAM0 11 +#define STM32_IRQ_DMA1_STREAM1 12 +#define STM32_IRQ_DMA1_STREAM2 13 +#define STM32_IRQ_DMA1_STREAM3 14 +#define STM32_IRQ_DMA1_STREAM4 15 +#define STM32_IRQ_DMA1_STREAM5 16 +#define STM32_IRQ_DMA1_STREAM6 17 +#define STM32_IRQ_DMA1_STREAM7 47 +#define STM32_IRQ_DMA2_STREAM0 56 +#define STM32_IRQ_DMA2_STREAM1 57 +#define STM32_IRQ_DMA2_STREAM2 58 +#define STM32_IRQ_DMA2_STREAM3 59 +#define STM32_IRQ_DMA2_STREAM4 60 +#define STM32_IRQ_DMA2_STREAM5 68 +#define STM32_IRQ_DMA2_STREAM6 69 +#define STM32_IRQ_DMA2_STREAM7 70 + +#define STM32_IRQ_OTG_HS_WKUP 76 +#define STM32_IRQ_OTG_HS_EP1_IN 75 +#define STM32_IRQ_OTG_HS_EP1_OUT 74 +#define STM32_IRQ_OTG_HS 77 +#define STM32_IRQ_OTG_FS 67 +#define STM32_IRQ_OTG_FS_WKUP 42 /* Peripheral base addresses */ -#define STM32_ADC1_BASE 0x40012000 -#define STM32_ADC_BASE 0x40012300 - -#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ -#define STM32_CRC_BASE 0x40023000 -#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ -#define STM32_DAC_BASE 0x40007400 - - -#define STM32_DBGMCU_BASE 0xE0042000 - -#define STM32_DMA1_BASE 0x40026000 -#define STM32_DMA2_BASE 0x40026400 - -#define STM32_EXTI_BASE 0x40013C00 - -#define STM32_FLASH_REGS_BASE 0x40023c00 - -#define STM32_GPIOA_BASE 0x40020000 -#define STM32_GPIOB_BASE 0x40020400 -#define STM32_GPIOC_BASE 0x40020800 -#define STM32_GPIOD_BASE 0x40020C00 -#define STM32_GPIOE_BASE 0x40021000 -#define STM32_GPIOF_BASE 0x40021400 /* see RM0402/0390 table 1 */ -#define STM32_GPIOG_BASE 0x40021800 -#define STM32_GPIOH_BASE 0x40021C00 - -#define STM32_I2C1_BASE 0x40005400 -#define STM32_I2C2_BASE 0x40005800 -#define STM32_I2C3_BASE 0x40005C00 -#define STM32_I2C4_BASE 0x40006000 - -#define STM32_IWDG_BASE 0x40003000 -#define STM32_LCD_BASE 0x40002400 - -#define STM32_OPTB_BASE 0x1FFFC000 -#define STM32_OTP_BASE 0x1FFF7800 - -#define STM32_PMSE_BASE 0x40013400 -#define STM32_PWR_BASE 0x40007000 - -#define STM32_RCC_BASE 0x40023800 - -#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ -#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ -#define STM32_RTC_BASE 0x40002800 - -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ - -#define STM32_SYSCFG_BASE 0x40013800 - -#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM9_BASE 0x40014000 /* STM32F41x only */ -#define STM32_TIM10_BASE 0x40014400 /* STM32F41x only */ -#define STM32_TIM11_BASE 0x40014800 /* STM32F41x only */ -#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ -#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ -#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 -#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ -#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ - -#define STM32_UNIQUE_ID_BASE 0x1fff7a10 - -#define STM32_USART1_BASE 0x40011000 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART5_BASE 0x40005000 -#define STM32_USART6_BASE 0x40011400 - -#define STM32_USB_CAN_SRAM_BASE 0x40006000 -#define STM32_USB_FS_BASE 0x40005C00 - -#define STM32_WWDG_BASE 0x40002C00 - +#define STM32_ADC1_BASE 0x40012000 +#define STM32_ADC_BASE 0x40012300 + +#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ +#define STM32_CRC_BASE 0x40023000 +#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ +#define STM32_DAC_BASE 0x40007400 + +#define STM32_DBGMCU_BASE 0xE0042000 + +#define STM32_DMA1_BASE 0x40026000 +#define STM32_DMA2_BASE 0x40026400 + +#define STM32_EXTI_BASE 0x40013C00 + +#define STM32_FLASH_REGS_BASE 0x40023c00 + +#define STM32_GPIOA_BASE 0x40020000 +#define STM32_GPIOB_BASE 0x40020400 +#define STM32_GPIOC_BASE 0x40020800 +#define STM32_GPIOD_BASE 0x40020C00 +#define STM32_GPIOE_BASE 0x40021000 +#define STM32_GPIOF_BASE 0x40021400 /* see RM0402/0390 table 1 */ +#define STM32_GPIOG_BASE 0x40021800 +#define STM32_GPIOH_BASE 0x40021C00 + +#define STM32_I2C1_BASE 0x40005400 +#define STM32_I2C2_BASE 0x40005800 +#define STM32_I2C3_BASE 0x40005C00 +#define STM32_I2C4_BASE 0x40006000 + +#define STM32_IWDG_BASE 0x40003000 +#define STM32_LCD_BASE 0x40002400 + +#define STM32_OPTB_BASE 0x1FFFC000 +#define STM32_OTP_BASE 0x1FFF7800 + +#define STM32_PMSE_BASE 0x40013400 +#define STM32_PWR_BASE 0x40007000 + +#define STM32_RCC_BASE 0x40023800 + +#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ +#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ +#define STM32_RTC_BASE 0x40002800 + +#define STM32_SPI1_BASE 0x40013000 +#define STM32_SPI2_BASE 0x40003800 +#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ + +#define STM32_SYSCFG_BASE 0x40013800 + +#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ +#define STM32_TIM2_BASE 0x40000000 +#define STM32_TIM3_BASE 0x40000400 +#define STM32_TIM4_BASE 0x40000800 +#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ +#define STM32_TIM6_BASE 0x40001000 +#define STM32_TIM7_BASE 0x40001400 +#define STM32_TIM9_BASE 0x40014000 /* STM32F41x only */ +#define STM32_TIM10_BASE 0x40014400 /* STM32F41x only */ +#define STM32_TIM11_BASE 0x40014800 /* STM32F41x only */ +#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ +#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ +#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ +#define STM32_TIM15_BASE 0x40014000 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ +#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ + +#define STM32_UNIQUE_ID_BASE 0x1fff7a10 + +#define STM32_USART1_BASE 0x40011000 +#define STM32_USART2_BASE 0x40004400 +#define STM32_USART3_BASE 0x40004800 +#define STM32_USART4_BASE 0x40004c00 +#define STM32_USART5_BASE 0x40005000 +#define STM32_USART6_BASE 0x40011400 + +#define STM32_USB_CAN_SRAM_BASE 0x40006000 +#define STM32_USB_FS_BASE 0x40005C00 + +#define STM32_WWDG_BASE 0x40002C00 #ifndef __ASSEMBLER__ /* Register definitions */ /* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_UESM BIT(1) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR2_SWAP BIT(15) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) -#define STM32_USART_CR3_OVRDIS BIT(12) -#define STM32_USART_CR3_WUS_START_BIT (2 << 20) -#define STM32_USART_CR3_WUFIE BIT(22) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) -#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) -#define STM32_USART_ICR_ORECF BIT(3) -#define STM32_USART_ICR_TCCF BIT(6) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) -#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) +#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) +#define STM32_USART_CR1_UE BIT(0) +#define STM32_USART_CR1_UESM BIT(1) +#define STM32_USART_CR1_RE BIT(2) +#define STM32_USART_CR1_TE BIT(3) +#define STM32_USART_CR1_RXNEIE BIT(5) +#define STM32_USART_CR1_TCIE BIT(6) +#define STM32_USART_CR1_TXEIE BIT(7) +#define STM32_USART_CR1_PS BIT(9) +#define STM32_USART_CR1_PCE BIT(10) +#define STM32_USART_CR1_M BIT(12) +#define STM32_USART_CR1_OVER8 BIT(15) +#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) +#define STM32_USART_CR2_SWAP BIT(15) +#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) +#define STM32_USART_CR3_EIE BIT(0) +#define STM32_USART_CR3_DMAR BIT(6) +#define STM32_USART_CR3_DMAT BIT(7) +#define STM32_USART_CR3_ONEBIT BIT(11) +#define STM32_USART_CR3_OVRDIS BIT(12) +#define STM32_USART_CR3_WUS_START_BIT (2 << 20) +#define STM32_USART_CR3_WUFIE BIT(22) +#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) +#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) +#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) +#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) +#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) +#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) +#define STM32_USART_ICR_ORECF BIT(3) +#define STM32_USART_ICR_TCCF BIT(6) +#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) +#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) +#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) /* register alias */ -#define STM32_USART_SR(base) STM32_USART_ISR(base) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) +#define STM32_USART_SR(base) STM32_USART_ISR(base) +#define STM32_USART_SR_ORE BIT(3) +#define STM32_USART_SR_RXNE BIT(5) +#define STM32_USART_SR_TC BIT(6) +#define STM32_USART_SR_TXE BIT(7) /* --- GPIO --- */ -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) - -#define GPIO_ALT_SYS 0x0 -#define GPIO_ALT_TIM2 0x1 -#define GPIO_ALT_TIM3_4 0x2 -#define GPIO_ALT_TIM9_11 0x3 -#define GPIO_ALT_I2C 0x4 -#define GPIO_ALT_SPI 0x5 -#define GPIO_ALT_SPI3 0x6 -#define GPIO_ALT_USART 0x7 -#define GPIO_ALT_I2C_23 0x9 -#define GPIO_ALT_USB 0xA -#define GPIO_ALT_LCD 0xB -#define GPIO_ALT_RI 0xE -#define GPIO_ALT_EVENTOUT 0xF +#define STM32_GPIO_MODER(b) REG32((b) + 0x00) +#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) +#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) +#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) +#define STM32_GPIO_IDR(b) REG16((b) + 0x10) +#define STM32_GPIO_ODR(b) REG16((b) + 0x14) +#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) +#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) +#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) +#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) + +#define GPIO_ALT_SYS 0x0 +#define GPIO_ALT_TIM2 0x1 +#define GPIO_ALT_TIM3_4 0x2 +#define GPIO_ALT_TIM9_11 0x3 +#define GPIO_ALT_I2C 0x4 +#define GPIO_ALT_SPI 0x5 +#define GPIO_ALT_SPI3 0x6 +#define GPIO_ALT_USART 0x7 +#define GPIO_ALT_I2C_23 0x9 +#define GPIO_ALT_USB 0xA +#define GPIO_ALT_LCD 0xB +#define GPIO_ALT_RI 0xE +#define GPIO_ALT_EVENTOUT 0xF /* --- I2C --- */ -#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_START BIT(8) -#define STM32_I2C_CR1_STOP BIT(9) -#define STM32_I2C_CR1_ACK BIT(10) -#define STM32_I2C_CR1_POS BIT(11) -#define STM32_I2C_CR1_SWRST BIT(15) -#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_ITERREN BIT(8) -#define STM32_I2C_CR2_ITEVTEN BIT(9) -#define STM32_I2C_CR2_ITBUFEN BIT(10) -#define STM32_I2C_CR2_DMAEN BIT(11) -#define STM32_I2C_CR2_LAST BIT(12) -#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR1_B14 BIT(14) -#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_OAR2_ENDUAL BIT(0) -#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_SR1_SB BIT(0) -#define STM32_I2C_SR1_ADDR BIT(1) -#define STM32_I2C_SR1_BTF BIT(2) -#define STM32_I2C_SR1_STOPF BIT(4) -#define STM32_I2C_SR1_RXNE BIT(6) -#define STM32_I2C_SR1_TXE BIT(7) -#define STM32_I2C_SR1_BERR BIT(8) -#define STM32_I2C_SR1_ARLO BIT(9) -#define STM32_I2C_SR1_AF BIT(10) - -#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_SR2_BUSY BIT(1) -#define STM32_I2C_SR2_TRA BIT(2) -#define STM32_I2C_SR2_DUALF BIT(7) - -#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_CCR_DUTY BIT(14) -#define STM32_I2C_CCR_FM BIT(15) -#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) - -#define STM32_FMPI2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) -#define FMPI2C_CR1_PE BIT(0) -#define FMPI2C_CR1_TXDMAEN BIT(14) -#define FMPI2C_CR1_RXDMAEN BIT(15) -#define STM32_FMPI2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) -#define FMPI2C_CR2_RD_WRN BIT(10) -#define FMPI2C_READ 1 -#define FMPI2C_WRITE 0 -#define FMPI2C_CR2_START BIT(13) -#define FMPI2C_CR2_STOP BIT(14) -#define FMPI2C_CR2_NACK BIT(15) -#define FMPI2C_CR2_RELOAD BIT(24) -#define FMPI2C_CR2_AUTOEND BIT(25) -#define FMPI2C_CR2_SADD(addr) ((addr) & 0x3ff) -#define FMPI2C_CR2_SADD_MASK FMPI2C_CR2_SADD(0x3ff) -#define FMPI2C_CR2_SIZE(size) (((size) & 0xff) << 16) -#define FMPI2C_CR2_SIZE_MASK FMPI2C_CR2_SIZE(0xf) -#define STM32_FMPI2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) -#define STM32_FMPI2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) -#define STM32_FMPI2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) -#define TIMINGR_THE_RIGHT_VALUE 0xC0000E12 -#define FMPI2C_TIMINGR_PRESC(val) (((val) & 0xf) << 28) -#define FMPI2C_TIMINGR_SCLDEL(val) (((val) & 0xf) << 20) -#define FMPI2C_TIMINGR_SDADEL(val) (((val) & 0xf) << 16) -#define FMPI2C_TIMINGR_SCLH(val) (((val) & 0xff) << 8) -#define FMPI2C_TIMINGR_SCLL(val) (((val) & 0xff) << 0) -#define STM32_FMPI2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) - -#define STM32_FMPI2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) -#define FMPI2C_ISR_TXE BIT(0) -#define FMPI2C_ISR_TXIS BIT(1) -#define FMPI2C_ISR_RXNE BIT(2) -#define FMPI2C_ISR_ADDR BIT(3) -#define FMPI2C_ISR_NACKF BIT(4) -#define FMPI2C_ISR_STOPF BIT(5) -#define FMPI2C_ISR_BERR BIT(8) -#define FMPI2C_ISR_ARLO BIT(9) -#define FMPI2C_ISR_BUSY BIT(15) -#define STM32_FMPI2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) - -#define STM32_FMPI2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) -#define STM32_FMPI2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) -#define STM32_FMPI2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) +#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) +#define STM32_I2C_CR1_PE BIT(0) +#define STM32_I2C_CR1_START BIT(8) +#define STM32_I2C_CR1_STOP BIT(9) +#define STM32_I2C_CR1_ACK BIT(10) +#define STM32_I2C_CR1_POS BIT(11) +#define STM32_I2C_CR1_SWRST BIT(15) +#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04)) +#define STM32_I2C_CR2_ITERREN BIT(8) +#define STM32_I2C_CR2_ITEVTEN BIT(9) +#define STM32_I2C_CR2_ITBUFEN BIT(10) +#define STM32_I2C_CR2_DMAEN BIT(11) +#define STM32_I2C_CR2_LAST BIT(12) +#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08)) +#define STM32_I2C_OAR1_B14 BIT(14) +#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C)) +#define STM32_I2C_OAR2_ENDUAL BIT(0) +#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10)) +#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14)) +#define STM32_I2C_SR1_SB BIT(0) +#define STM32_I2C_SR1_ADDR BIT(1) +#define STM32_I2C_SR1_BTF BIT(2) +#define STM32_I2C_SR1_STOPF BIT(4) +#define STM32_I2C_SR1_RXNE BIT(6) +#define STM32_I2C_SR1_TXE BIT(7) +#define STM32_I2C_SR1_BERR BIT(8) +#define STM32_I2C_SR1_ARLO BIT(9) +#define STM32_I2C_SR1_AF BIT(10) + +#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18)) +#define STM32_I2C_SR2_BUSY BIT(1) +#define STM32_I2C_SR2_TRA BIT(2) +#define STM32_I2C_SR2_DUALF BIT(7) + +#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) +#define STM32_I2C_CCR_DUTY BIT(14) +#define STM32_I2C_CCR_FM BIT(15) +#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) + +#define STM32_FMPI2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) +#define FMPI2C_CR1_PE BIT(0) +#define FMPI2C_CR1_TXDMAEN BIT(14) +#define FMPI2C_CR1_RXDMAEN BIT(15) +#define STM32_FMPI2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) +#define FMPI2C_CR2_RD_WRN BIT(10) +#define FMPI2C_READ 1 +#define FMPI2C_WRITE 0 +#define FMPI2C_CR2_START BIT(13) +#define FMPI2C_CR2_STOP BIT(14) +#define FMPI2C_CR2_NACK BIT(15) +#define FMPI2C_CR2_RELOAD BIT(24) +#define FMPI2C_CR2_AUTOEND BIT(25) +#define FMPI2C_CR2_SADD(addr) ((addr)&0x3ff) +#define FMPI2C_CR2_SADD_MASK FMPI2C_CR2_SADD(0x3ff) +#define FMPI2C_CR2_SIZE(size) (((size)&0xff) << 16) +#define FMPI2C_CR2_SIZE_MASK FMPI2C_CR2_SIZE(0xf) +#define STM32_FMPI2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) +#define STM32_FMPI2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) +#define STM32_FMPI2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) +#define TIMINGR_THE_RIGHT_VALUE 0xC0000E12 +#define FMPI2C_TIMINGR_PRESC(val) (((val)&0xf) << 28) +#define FMPI2C_TIMINGR_SCLDEL(val) (((val)&0xf) << 20) +#define FMPI2C_TIMINGR_SDADEL(val) (((val)&0xf) << 16) +#define FMPI2C_TIMINGR_SCLH(val) (((val)&0xff) << 8) +#define FMPI2C_TIMINGR_SCLL(val) (((val)&0xff) << 0) +#define STM32_FMPI2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) + +#define STM32_FMPI2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) +#define FMPI2C_ISR_TXE BIT(0) +#define FMPI2C_ISR_TXIS BIT(1) +#define FMPI2C_ISR_RXNE BIT(2) +#define FMPI2C_ISR_ADDR BIT(3) +#define FMPI2C_ISR_NACKF BIT(4) +#define FMPI2C_ISR_STOPF BIT(5) +#define FMPI2C_ISR_BERR BIT(8) +#define FMPI2C_ISR_ARLO BIT(9) +#define FMPI2C_ISR_BUSY BIT(15) +#define STM32_FMPI2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) + +#define STM32_FMPI2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) +#define STM32_FMPI2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) +#define STM32_FMPI2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) /* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) - +#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_CR_HSION BIT(0) -#define STM32_RCC_CR_HSIRDY BIT(1) -#define STM32_RCC_CR_HSEON BIT(16) -#define STM32_RCC_CR_HSERDY BIT(17) -#define STM32_RCC_CR_PLLON BIT(24) -#define STM32_RCC_CR_PLLRDY BIT(25) +#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) +#define STM32_RCC_CR_HSION BIT(0) +#define STM32_RCC_CR_HSIRDY BIT(1) +#define STM32_RCC_CR_HSEON BIT(16) +#define STM32_RCC_CR_HSERDY BIT(17) +#define STM32_RCC_CR_PLLON BIT(24) +#define STM32_RCC_CR_PLLRDY BIT(25) #ifdef CHIP_VARIANT_STM32F76X /* Required or recommended clocks for stm32f767/769 */ #define STM32F4_PLL_REQ 2000000 #define STM32F4_RTC_REQ 1000000 #define STM32F4_IO_CLOCK 45000000 -#define STM32F4_USB_REQ 45000000 /* not compatible with USB, will use PLLSAI */ +#define STM32F4_USB_REQ \ + 45000000 /* not compatible with USB, will use PLLSAI \ + */ #define STM32F4_VCO_CLOCK 360000000 #define STM32F4_HSI_CLOCK 16000000 #define STM32F4_LSI_CLOCK 32000 #define STM32F4_TIMER_CLOCK (STM32F4_IO_CLOCK * 2) -#define STM32F4_PLLP_DIV 2 /* sys = VCO/2 = 180 Mhz */ -#define STM32F4_AHB_PRE 0x0 /* AHB = sysclk = 180 Mhz */ +#define STM32F4_PLLP_DIV 2 /* sys = VCO/2 = 180 Mhz */ +#define STM32F4_AHB_PRE 0x0 /* AHB = sysclk = 180 Mhz */ #define STM32F4_APB1_PRE 0x5 /* APB1 = AHB /4 = 45 Mhz */ #define STM32F4_APB2_PRE 0x5 /* APB2 = AHB /4 = 45 Mhz */ -#define STM32_FLASH_ACR_LATENCY (5 << 0) +#define STM32_FLASH_ACR_LATENCY (5 << 0) #else #error "No valid clocks defined" #endif -#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x04) +#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x04) /* PLL Division factor */ -#define PLLCFGR_PLLM_OFF 0 -#define PLLCFGR_PLLM(val) (((val) & 0x1f) << PLLCFGR_PLLM_OFF) +#define PLLCFGR_PLLM_OFF 0 +#define PLLCFGR_PLLM(val) (((val)&0x1f) << PLLCFGR_PLLM_OFF) /* PLL Multiplication factor */ -#define PLLCFGR_PLLN_OFF 6 -#define PLLCFGR_PLLN(val) (((val) & 0x1ff) << PLLCFGR_PLLN_OFF) +#define PLLCFGR_PLLN_OFF 6 +#define PLLCFGR_PLLN(val) (((val)&0x1ff) << PLLCFGR_PLLN_OFF) /* Main CPU Clock */ -#define PLLCFGR_PLLP_OFF 16 -#define PLLCFGR_PLLP(val) (((val) & 0x3) << PLLCFGR_PLLP_OFF) +#define PLLCFGR_PLLP_OFF 16 +#define PLLCFGR_PLLP(val) (((val)&0x3) << PLLCFGR_PLLP_OFF) -#define PLLCFGR_PLLSRC_HSI (0 << 22) -#define PLLCFGR_PLLSRC_HSE BIT(22) +#define PLLCFGR_PLLSRC_HSI (0 << 22) +#define PLLCFGR_PLLSRC_HSE BIT(22) /* USB OTG FS: Must equal 48MHz */ -#define PLLCFGR_PLLQ_OFF 24 -#define PLLCFGR_PLLQ(val) (((val) & 0xf) << PLLCFGR_PLLQ_OFF) +#define PLLCFGR_PLLQ_OFF 24 +#define PLLCFGR_PLLQ(val) (((val)&0xf) << PLLCFGR_PLLQ_OFF) /* SYSTEM */ -#define PLLCFGR_PLLR_OFF 28 -#define PLLCFGR_PLLR(val) (((val) & 0x7) << PLLCFGR_PLLR_OFF) - -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_CFGR_SW_HSI (0 << 0) -#define STM32_RCC_CFGR_SW_HSE (1 << 0) -#define STM32_RCC_CFGR_SW_PLL (2 << 0) -#define STM32_RCC_CFGR_SW_PLL_R (3 << 0) -#define STM32_RCC_CFGR_SW_MASK (3 << 0) -#define STM32_RCC_CFGR_SWS_HSI (0 << 2) -#define STM32_RCC_CFGR_SWS_HSE (1 << 2) -#define STM32_RCC_CFGR_SWS_PLL (2 << 2) -#define STM32_RCC_CFGR_SWS_PLL_R (3 << 2) -#define STM32_RCC_CFGR_SWS_MASK (3 << 2) +#define PLLCFGR_PLLR_OFF 28 +#define PLLCFGR_PLLR(val) (((val)&0x7) << PLLCFGR_PLLR_OFF) + +#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) +#define STM32_RCC_CFGR_SW_HSI (0 << 0) +#define STM32_RCC_CFGR_SW_HSE (1 << 0) +#define STM32_RCC_CFGR_SW_PLL (2 << 0) +#define STM32_RCC_CFGR_SW_PLL_R (3 << 0) +#define STM32_RCC_CFGR_SW_MASK (3 << 0) +#define STM32_RCC_CFGR_SWS_HSI (0 << 2) +#define STM32_RCC_CFGR_SWS_HSE (1 << 2) +#define STM32_RCC_CFGR_SWS_PLL (2 << 2) +#define STM32_RCC_CFGR_SWS_PLL_R (3 << 2) +#define STM32_RCC_CFGR_SWS_MASK (3 << 2) /* AHB Prescalar: nonlinear values, look up in RM0390 */ -#define CFGR_HPRE_OFF 4 -#define CFGR_HPRE(val) (((val) & 0xf) << CFGR_HPRE_OFF) +#define CFGR_HPRE_OFF 4 +#define CFGR_HPRE(val) (((val)&0xf) << CFGR_HPRE_OFF) /* APB1 Low Speed Prescalar < 45MHz */ -#define CFGR_PPRE1_OFF 10 -#define CFGR_PPRE1(val) (((val) & 0x7) << CFGR_PPRE1_OFF) +#define CFGR_PPRE1_OFF 10 +#define CFGR_PPRE1(val) (((val)&0x7) << CFGR_PPRE1_OFF) /* APB2 High Speed Prescalar < 90MHz */ -#define CFGR_PPRE2_OFF 13 -#define CFGR_PPRE2(val) (((val) & 0x7) << CFGR_PPRE2_OFF) +#define CFGR_PPRE2_OFF 13 +#define CFGR_PPRE2(val) (((val)&0x7) << CFGR_PPRE2_OFF) /* RTC CLock: Must equal 1MHz */ -#define CFGR_RTCPRE_OFF 16 -#define CFGR_RTCPRE(val) (((val) & 0x1f) << CFGR_RTCPRE_OFF) +#define CFGR_RTCPRE_OFF 16 +#define CFGR_RTCPRE(val) (((val)&0x1f) << CFGR_RTCPRE_OFF) -#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C) -#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x10) -#define RCC_AHB1RSTR_OTGHSRST BIT(29) +#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C) +#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x10) +#define RCC_AHB1RSTR_OTGHSRST BIT(29) -#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x18) +#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x14) +#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x18) -#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x24) +#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x20) +#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x24) -#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_AHB1ENR_GPIOMASK (0xff << 0) -#define STM32_RCC_AHB1ENR_BKPSRAMEN BIT(18) -#define STM32_RCC_AHB1ENR_DMA1EN BIT(21) -#define STM32_RCC_AHB1ENR_DMA2EN BIT(22) +#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x30) +#define STM32_RCC_AHB1ENR_GPIOMASK (0xff << 0) +#define STM32_RCC_AHB1ENR_BKPSRAMEN BIT(18) +#define STM32_RCC_AHB1ENR_DMA1EN BIT(21) +#define STM32_RCC_AHB1ENR_DMA2EN BIT(22) /* TODO(nsanders): normalize naming.*/ -#define STM32_RCC_HB1_DMA1 BIT(21) -#define STM32_RCC_HB1_DMA2 BIT(22) -#define STM32_RCC_AHB1ENR_OTGHSEN BIT(29) -#define STM32_RCC_AHB1ENR_OTGHSULPIEN BIT(30) - -#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x34) -#define STM32_RCC_AHB2ENR_RNGEN BIT(6) -#define STM32_RCC_AHB2ENR_OTGFSEN BIT(7) -#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x38) - -#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x40) -#define STM32_RCC_PWREN BIT(28) -#define STM32_RCC_I2C1EN BIT(21) -#define STM32_RCC_I2C2EN BIT(22) -#define STM32_RCC_I2C3EN BIT(23) -#define STM32_RCC_FMPI2C4EN BIT(24) - -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x44) -#define STM32_RCC_APB2ENR_ADC1EN BIT(8) /* STM32F4 */ - -#define STM32_RCC_PB2_USART6 BIT(5) -#define STM32_RCC_SYSCFGEN BIT(14) - -#define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x50) -#define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x54) -#define STM32_RCC_AHB3LPENR REG32(STM32_RCC_BASE + 0x58) -#define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x60) -#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x64) - -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x70) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x74) -#define STM32_RCC_CSR_LSION BIT(0) -#define STM32_RCC_CSR_LSIRDY BIT(1) - -#define STM32_RCC_PB2_TIM9 BIT(16) -#define STM32_RCC_PB2_TIM10 BIT(17) -#define STM32_RCC_PB2_TIM11 BIT(18) - -#define STM32_RCC_DCKCFGR2 REG32(STM32_RCC_BASE + 0x94) -#define DCKCFGR2_FMPI2C1SEL(val) (((val) & 0x3) << 22) -#define DCKCFGR2_FMPI2C1SEL_MASK (0x3 << 22) -#define FMPI2C1SEL_APB 0x0 - -#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00) -#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) -#define STM32_SYSCFG_CMPCR REG32(STM32_SYSCFG_BASE + 0x20) -#define STM32_SYSCFG_CFGR REG32(STM32_SYSCFG_BASE + 0x2C) - +#define STM32_RCC_HB1_DMA1 BIT(21) +#define STM32_RCC_HB1_DMA2 BIT(22) +#define STM32_RCC_AHB1ENR_OTGHSEN BIT(29) +#define STM32_RCC_AHB1ENR_OTGHSULPIEN BIT(30) + +#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x34) +#define STM32_RCC_AHB2ENR_RNGEN BIT(6) +#define STM32_RCC_AHB2ENR_OTGFSEN BIT(7) +#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x38) + +#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x40) +#define STM32_RCC_PWREN BIT(28) +#define STM32_RCC_I2C1EN BIT(21) +#define STM32_RCC_I2C2EN BIT(22) +#define STM32_RCC_I2C3EN BIT(23) +#define STM32_RCC_FMPI2C4EN BIT(24) + +#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x44) +#define STM32_RCC_APB2ENR_ADC1EN BIT(8) /* STM32F4 */ + +#define STM32_RCC_PB2_USART6 BIT(5) +#define STM32_RCC_SYSCFGEN BIT(14) + +#define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x50) +#define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x54) +#define STM32_RCC_AHB3LPENR REG32(STM32_RCC_BASE + 0x58) +#define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x60) +#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x64) + +#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x70) +#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x74) +#define STM32_RCC_CSR_LSION BIT(0) +#define STM32_RCC_CSR_LSIRDY BIT(1) + +#define STM32_RCC_PB2_TIM9 BIT(16) +#define STM32_RCC_PB2_TIM10 BIT(17) +#define STM32_RCC_PB2_TIM11 BIT(18) + +#define STM32_RCC_DCKCFGR2 REG32(STM32_RCC_BASE + 0x94) +#define DCKCFGR2_FMPI2C1SEL(val) (((val)&0x3) << 22) +#define DCKCFGR2_FMPI2C1SEL_MASK (0x3 << 22) +#define FMPI2C1SEL_APB 0x0 + +#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00) +#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04) +#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) +#define STM32_SYSCFG_CMPCR REG32(STM32_SYSCFG_BASE + 0x20) +#define STM32_SYSCFG_CFGR REG32(STM32_SYSCFG_BASE + 0x2C) /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB2_USART1 BIT(4) +#define STM32_RCC_PB2_USART1 BIT(4) /* Reset causes definitions */ /* Reset causes in RCC CSR register */ #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG 0x60000000 -#define RESET_CAUSE_SFT 0x10000000 -#define RESET_CAUSE_POR 0x08000000 -#define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xfe000000 -#define RESET_CAUSE_RMVF 0x01000000 +#define RESET_CAUSE_WDG 0x60000000 +#define RESET_CAUSE_SFT 0x10000000 +#define RESET_CAUSE_POR 0x08000000 +#define RESET_CAUSE_PIN 0x04000000 +#define RESET_CAUSE_OTHER 0xfe000000 +#define RESET_CAUSE_RMVF 0x01000000 /* Power cause in PWR CSR register */ #define STM32_PWR_RESET_CAUSE STM32_PWR_CSR #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR -#define RESET_CAUSE_SBF 0x00000002 -#define RESET_CAUSE_SBF_CLR 0x00000004 +#define RESET_CAUSE_SBF 0x00000002 +#define RESET_CAUSE_SBF_CLR 0x00000004 /* --- Watchdogs --- */ /* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 80 +#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) +#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) +#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) +#define STM32_RTC_CR_BYPSHAD BIT(5) +#define STM32_RTC_CR_ALRAE BIT(8) +#define STM32_RTC_CR_ALRAIE BIT(12) +#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) +#define STM32_RTC_ISR_ALRAWF BIT(0) +#define STM32_RTC_ISR_RSF BIT(5) +#define STM32_RTC_ISR_INITF BIT(6) +#define STM32_RTC_ISR_INIT BIT(7) +#define STM32_RTC_ISR_ALRAF BIT(8) +#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) +#define STM32_RTC_PRER_A_MASK (0x7f << 16) +#define STM32_RTC_PRER_S_MASK (0x7fff << 0) +#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) +#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) +#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) +#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) +#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) +#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) +#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) +#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) +#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) +#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) +#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) + +#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) +#define STM32_BKP_BYTES 80 /* --- SPI --- */ @@ -597,8 +594,8 @@ struct stm32_spi_regs { unsigned crcpr; unsigned rxcrcr; unsigned txcrcr; - unsigned i2scfgr; /* STM32L only */ - unsigned i2spr; /* STM32L only */ + unsigned i2scfgr; /* STM32L only */ + unsigned i2spr; /* STM32L only */ }; /* Must be volatile, or compiler optimizes out repeated accesses */ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; @@ -608,146 +605,142 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) +#define STM32_SPI_CR1_BIDIMODE BIT(15) +#define STM32_SPI_CR1_BIDIOE BIT(14) +#define STM32_SPI_CR1_CRCEN BIT(13) +#define STM32_SPI_CR1_SSM BIT(9) +#define STM32_SPI_CR1_SSI BIT(8) +#define STM32_SPI_CR1_LSBFIRST BIT(7) +#define STM32_SPI_CR1_SPE BIT(6) +#define STM32_SPI_CR1_BR_DIV64R (5 << 3) +#define STM32_SPI_CR1_BR_DIV4R BIT(3) +#define STM32_SPI_CR1_MSTR BIT(2) +#define STM32_SPI_CR1_CPOL BIT(1) +#define STM32_SPI_CR1_CPHA BIT(0) +#define STM32_SPI_CR2_FRXTH BIT(12) +#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8) +#define STM32_SPI_CR2_TXEIE BIT(7) +#define STM32_SPI_CR2_RXNEIE BIT(6) +#define STM32_SPI_CR2_NSSP BIT(3) +#define STM32_SPI_CR2_SSOE BIT(2) +#define STM32_SPI_CR2_TXDMAEN BIT(1) +#define STM32_SPI_CR2_RXDMAEN BIT(0) + +#define STM32_SPI_SR_RXNE BIT(0) +#define STM32_SPI_SR_TXE BIT(1) +#define STM32_SPI_SR_CRCERR BIT(4) +#define STM32_SPI_SR_BSY BIT(7) +#define STM32_SPI_SR_FRLVL (3 << 9) +#define STM32_SPI_SR_FTLVL (3 << 11) /* --- Debug --- */ -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) +#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) +#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) /* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) -#define STM32_FLASH_ACR_SHIFT 0 -#define STM32_FLASH_ACR_LAT_MASK 0xf -#define STM32_FLASH_ACR_PRFTEN BIT(8) -#define STM32_FLASH_ACR_ICEN BIT(9) -#define STM32_FLASH_ACR_DCEN BIT(10) -#define STM32_FLASH_ACR_ICRST BIT(11) -#define STM32_FLASH_ACR_DCRST BIT(12) -#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define FLASH_OPTKEYR_KEY1 0x08192A3B -#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define FLASH_SR_EOP BIT(0) -#define FLASH_SR_OPERR BIT(1) -#define FLASH_SR_WRPERR BIT(4) -#define FLASH_SR_PGAERR BIT(5) -#define FLASH_SR_PGPERR BIT(6) -#define FLASH_SR_PGSERR BIT(7) -#define FLASH_SR_RDERR BIT(8) -#define FLASH_SR_ALL_ERR \ +#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) +#define STM32_FLASH_ACR_SHIFT 0 +#define STM32_FLASH_ACR_LAT_MASK 0xf +#define STM32_FLASH_ACR_PRFTEN BIT(8) +#define STM32_FLASH_ACR_ICEN BIT(9) +#define STM32_FLASH_ACR_DCEN BIT(10) +#define STM32_FLASH_ACR_ICRST BIT(11) +#define STM32_FLASH_ACR_DCRST BIT(12) +#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) +#define FLASH_KEYR_KEY1 0x45670123 +#define FLASH_KEYR_KEY2 0xCDEF89AB +#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) +#define FLASH_OPTKEYR_KEY1 0x08192A3B +#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F +#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) +#define FLASH_SR_EOP BIT(0) +#define FLASH_SR_OPERR BIT(1) +#define FLASH_SR_WRPERR BIT(4) +#define FLASH_SR_PGAERR BIT(5) +#define FLASH_SR_PGPERR BIT(6) +#define FLASH_SR_PGSERR BIT(7) +#define FLASH_SR_RDERR BIT(8) +#define FLASH_SR_ALL_ERR \ (FLASH_SR_OPERR | FLASH_SR_WRPERR | FLASH_SR_PGAERR | \ FLASH_SR_PGPERR | FLASH_SR_PGSERR | FLASH_SR_RDERR) -#define FLASH_SR_BUSY BIT(16) -#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_MER BIT(2) -#define STM32_FLASH_CR_SNB_OFFSET (3) -#define STM32_FLASH_CR_SNB(sec) \ - (((sec) & 0xf) << STM32_FLASH_CR_SNB_OFFSET) -#define STM32_FLASH_CR_SNB_MASK (STM32_FLASH_CR_SNB(0xf)) -#define STM32_FLASH_CR_PSIZE_OFFSET (8) -#define STM32_FLASH_CR_PSIZE(size) \ - (((size) & 0x3) << STM32_FLASH_CR_PSIZE_OFFSET) -#define STM32_FLASH_CR_PSIZE_MASK (STM32_FLASH_CR_PSIZE(0x3)) -#define FLASH_CR_STRT BIT(16) -#define FLASH_CR_LOCK BIT(31) -#define STM32_FLASH_OPTCR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define FLASH_OPTLOCK BIT(0) -#define FLASH_OPTSTRT BIT(1) -#define STM32_FLASH_BOR_LEV_OFFSET (2) -#define STM32_FLASH_RDP_MASK (0xFF << 8) -#define STM32_FLASH_nWRP_OFFSET (16) -#define STM32_FLASH_nWRP(_bank) BIT(_bank + STM32_FLASH_nWRP_OFFSET) -#define STM32_FLASH_nWRP_ALL (0xFF << STM32_FLASH_nWRP_OFFSET) -#define STM32_FLASH_OPT_LOCKED (STM32_FLASH_OPTCR & FLASH_OPTLOCK) - -#define STM32_OPTB_RDP_USER REG32(STM32_OPTB_BASE + 0x00) -#define STM32_OPTB_RDP_OFF 0x00 -#define STM32_OPTB_USER_OFF 0x02 -#define STM32_OPTB_WRP_OFF(n) (0x08 + (n&3) * 2) -#define STM32_OPTB_WP REG32(STM32_OPTB_BASE + 0x08) -#define STM32_OPTB_nWRP(_bank) BIT(_bank) -#define STM32_OPTB_nWRP_ALL (0xFF) - -#define STM32_OPTB_COMPL_SHIFT 8 - -#define STM32_OTP_BLOCK_NB 16 -#define STM32_OTP_BLOCK_SIZE 32 +#define FLASH_SR_BUSY BIT(16) +#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) +#define FLASH_CR_PG BIT(0) +#define FLASH_CR_PER BIT(1) +#define FLASH_CR_MER BIT(2) +#define STM32_FLASH_CR_SNB_OFFSET (3) +#define STM32_FLASH_CR_SNB(sec) (((sec)&0xf) << STM32_FLASH_CR_SNB_OFFSET) +#define STM32_FLASH_CR_SNB_MASK (STM32_FLASH_CR_SNB(0xf)) +#define STM32_FLASH_CR_PSIZE_OFFSET (8) +#define STM32_FLASH_CR_PSIZE(size) (((size)&0x3) << STM32_FLASH_CR_PSIZE_OFFSET) +#define STM32_FLASH_CR_PSIZE_MASK (STM32_FLASH_CR_PSIZE(0x3)) +#define FLASH_CR_STRT BIT(16) +#define FLASH_CR_LOCK BIT(31) +#define STM32_FLASH_OPTCR REG32(STM32_FLASH_REGS_BASE + 0x14) +#define FLASH_OPTLOCK BIT(0) +#define FLASH_OPTSTRT BIT(1) +#define STM32_FLASH_BOR_LEV_OFFSET (2) +#define STM32_FLASH_RDP_MASK (0xFF << 8) +#define STM32_FLASH_nWRP_OFFSET (16) +#define STM32_FLASH_nWRP(_bank) BIT(_bank + STM32_FLASH_nWRP_OFFSET) +#define STM32_FLASH_nWRP_ALL (0xFF << STM32_FLASH_nWRP_OFFSET) +#define STM32_FLASH_OPT_LOCKED (STM32_FLASH_OPTCR & FLASH_OPTLOCK) + +#define STM32_OPTB_RDP_USER REG32(STM32_OPTB_BASE + 0x00) +#define STM32_OPTB_RDP_OFF 0x00 +#define STM32_OPTB_USER_OFF 0x02 +#define STM32_OPTB_WRP_OFF(n) (0x08 + (n & 3) * 2) +#define STM32_OPTB_WP REG32(STM32_OPTB_BASE + 0x08) +#define STM32_OPTB_nWRP(_bank) BIT(_bank) +#define STM32_OPTB_nWRP_ALL (0xFF) + +#define STM32_OPTB_COMPL_SHIFT 8 + +#define STM32_OTP_BLOCK_NB 16 +#define STM32_OTP_BLOCK_SIZE 32 #define STM32_OTP_BLOCK_DATA(_block, _offset) \ - (STM32_OTP_BASE + STM32_OTP_BLOCK_SIZE * (_block) + (_offset) * 4) -#define STM32_OTP_UNLOCK_BYTE 0x00 -#define STM32_OTP_LOCK_BYTE 0xFF -#define STM32_OTP_LOCK_BASE \ + (STM32_OTP_BASE + STM32_OTP_BLOCK_SIZE * (_block) + (_offset)*4) +#define STM32_OTP_UNLOCK_BYTE 0x00 +#define STM32_OTP_LOCK_BYTE 0xFF +#define STM32_OTP_LOCK_BASE \ (STM32_OTP_BASE + STM32_OTP_BLOCK_NB * STM32_OTP_BLOCK_SIZE) -#define STM32_OTP_LOCK(_block) \ - (STM32_OTP_LOCK_BASE + ((_block) / 4) * 4) -#define STM32_OPT_LOCK_MASK(_block) ((0xFF << ((_block) % 4) * 8)) +#define STM32_OTP_LOCK(_block) (STM32_OTP_LOCK_BASE + ((_block) / 4) * 4) +#define STM32_OPT_LOCK_MASK(_block) ((0xFF << ((_block) % 4) * 8)) /* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) +#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) +#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) +#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) +#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) +#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) +#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) #define EXTI_RTC_ALR_EVENT BIT(17) /* --- ADC --- */ -#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC_CR2_ADON BIT(0) -#define STM32_ADC_CR2_CONT BIT(1) -#define STM32_ADC_CR2_CAL BIT(2) -#define STM32_ADC_CR2_RSTCAL BIT(3) -#define STM32_ADC_CR2_ALIGN BIT(11) -#define STM32_ADC_CR2_SWSTART BIT(30) -#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) -#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) -#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) -#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24) -#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4) -#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x2C) -#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x30) -#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x34) -#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38) -#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4) -#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C) +#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) +#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) +#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) +#define STM32_ADC_CR2_ADON BIT(0) +#define STM32_ADC_CR2_CONT BIT(1) +#define STM32_ADC_CR2_CAL BIT(2) +#define STM32_ADC_CR2_RSTCAL BIT(3) +#define STM32_ADC_CR2_ALIGN BIT(11) +#define STM32_ADC_CR2_SWSTART BIT(30) +#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) +#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) +#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) +#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24) +#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28) +#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4) +#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x2C) +#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x30) +#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x34) +#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38) +#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4) +#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C) /* --- Comparators --- */ - /* --- DMA --- */ /* * Available DMA streams, numbered from 0. @@ -838,12 +831,12 @@ enum dma_channel { /* Registers for a single stream of a DMA controller */ struct stm32_dma_stream { - uint32_t scr; /* Control */ - uint32_t sndtr; /* Number of data to transfer */ - uint32_t spar; /* Peripheral address */ - uint32_t sm0ar; /* Memory address 0 */ - uint32_t sm1ar; /* address 1 for double buffer */ - uint32_t sfcr; /* FIFO control */ + uint32_t scr; /* Control */ + uint32_t sndtr; /* Number of data to transfer */ + uint32_t spar; /* Peripheral address */ + uint32_t sm0ar; /* Memory address 0 */ + uint32_t sm1ar; /* address 1 for double buffer */ + uint32_t sfcr; /* FIFO control */ }; /* Always use stm32_dma_stream_t so volatile keyword is included! */ @@ -852,12 +845,11 @@ typedef volatile struct stm32_dma_stream stm32_dma_stream_t; /* Common code and header file must use this */ typedef stm32_dma_stream_t dma_chan_t; struct stm32_dma_regs { - uint32_t isr[2]; - uint32_t ifcr[2]; + uint32_t isr[2]; + uint32_t ifcr[2]; stm32_dma_stream_t stream[STM32_DMAS_COUNT]; }; - /* Always use stm32_dma_regs_t so volatile keyword is included! */ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; @@ -868,215 +860,134 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_DMA_REGS(channel) \ ((channel) < STM32_DMAS_COUNT ? STM32_DMA1_REGS : STM32_DMA2_REGS) -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_DMEIE BIT(1) -#define STM32_DMA_CCR_TEIE BIT(2) -#define STM32_DMA_CCR_HTIE BIT(3) -#define STM32_DMA_CCR_TCIE BIT(4) -#define STM32_DMA_CCR_PFCTRL BIT(5) -#define STM32_DMA_CCR_DIR_P2M (0 << 6) -#define STM32_DMA_CCR_DIR_M2P (1 << 6) -#define STM32_DMA_CCR_DIR_M2M (2 << 6) -#define STM32_DMA_CCR_CIRC BIT(8) -#define STM32_DMA_CCR_PINC BIT(9) -#define STM32_DMA_CCR_MINC BIT(10) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 11) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 11) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 11) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 13) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 13) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 13) -#define STM32_DMA_CCR_PINCOS BIT(15) -#define STM32_DMA_CCR_PL_LOW (0 << 16) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 16) -#define STM32_DMA_CCR_PL_HIGH (2 << 16) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 16) -#define STM32_DMA_CCR_DBM BIT(18) -#define STM32_DMA_CCR_CT BIT(19) -#define STM32_DMA_CCR_PBURST(b_len) ((((b_len) - 4) / 4) << 21) -#define STM32_DMA_CCR_MBURST(b_len) ((((b_len) - 4) / 4) << 21) -#define STM32_DMA_CCR_CHANNEL_MASK (0x7 << 25) -#define STM32_DMA_CCR_CHANNEL(channel) ((channel) << 25) -#define STM32_DMA_CCR_RSVD_MASK (0xF0100000) - - -#define STM32_DMA_SFCR_DMDIS BIT(2) -#define STM32_DMA_SFCR_FTH(level) (((level) - 1) << 0) - - -#define STM32_DMA_CH_LOCAL(channel) ((channel) % STM32_DMAS_COUNT) -#define STM32_DMA_CH_LH(channel) \ - ((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1) -#define STM32_DMA_CH_OFFSET(channel) \ +#define STM32_DMA_CCR_EN BIT(0) +#define STM32_DMA_CCR_DMEIE BIT(1) +#define STM32_DMA_CCR_TEIE BIT(2) +#define STM32_DMA_CCR_HTIE BIT(3) +#define STM32_DMA_CCR_TCIE BIT(4) +#define STM32_DMA_CCR_PFCTRL BIT(5) +#define STM32_DMA_CCR_DIR_P2M (0 << 6) +#define STM32_DMA_CCR_DIR_M2P (1 << 6) +#define STM32_DMA_CCR_DIR_M2M (2 << 6) +#define STM32_DMA_CCR_CIRC BIT(8) +#define STM32_DMA_CCR_PINC BIT(9) +#define STM32_DMA_CCR_MINC BIT(10) +#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 11) +#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 11) +#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 11) +#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 13) +#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 13) +#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 13) +#define STM32_DMA_CCR_PINCOS BIT(15) +#define STM32_DMA_CCR_PL_LOW (0 << 16) +#define STM32_DMA_CCR_PL_MEDIUM (1 << 16) +#define STM32_DMA_CCR_PL_HIGH (2 << 16) +#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 16) +#define STM32_DMA_CCR_DBM BIT(18) +#define STM32_DMA_CCR_CT BIT(19) +#define STM32_DMA_CCR_PBURST(b_len) ((((b_len)-4) / 4) << 21) +#define STM32_DMA_CCR_MBURST(b_len) ((((b_len)-4) / 4) << 21) +#define STM32_DMA_CCR_CHANNEL_MASK (0x7 << 25) +#define STM32_DMA_CCR_CHANNEL(channel) ((channel) << 25) +#define STM32_DMA_CCR_RSVD_MASK (0xF0100000) + +#define STM32_DMA_SFCR_DMDIS BIT(2) +#define STM32_DMA_SFCR_FTH(level) (((level)-1) << 0) + +#define STM32_DMA_CH_LOCAL(channel) ((channel) % STM32_DMAS_COUNT) +#define STM32_DMA_CH_LH(channel) ((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1) +#define STM32_DMA_CH_OFFSET(channel) \ (((STM32_DMA_CH_LOCAL(channel) % 4) * 6) + \ - (((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0)) + (((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0)) #define STM32_DMA_CH_GETBITS(channel, val) \ (((val) >> STM32_DMA_CH_OFFSET(channel)) & 0x3f) -#define STM32_DMA_GET_IFCR(channel) \ - (STM32_DMA_CH_GETBITS(channel, \ - STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)])) -#define STM32_DMA_GET_ISR(channel) \ - (STM32_DMA_CH_GETBITS(channel, \ - STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)])) - -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \ - (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \ - ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel))) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \ - (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \ - ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel))) - -#define STM32_DMA_FEIF BIT(0) -#define STM32_DMA_DMEIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_HTIF BIT(4) -#define STM32_DMA_TCIF BIT(5) -#define STM32_DMA_ALL 0x3d - - +#define STM32_DMA_GET_IFCR(channel) \ + (STM32_DMA_CH_GETBITS( \ + channel, \ + STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)])) +#define STM32_DMA_GET_ISR(channel) \ + (STM32_DMA_CH_GETBITS( \ + channel, \ + STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)])) + +#define STM32_DMA_SET_IFCR(channel, val) \ + (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \ + (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \ + ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&0x3f) << STM32_DMA_CH_OFFSET(channel))) +#define STM32_DMA_SET_ISR(channel, val) \ + (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \ + (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \ + ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&0x3f) << STM32_DMA_CH_OFFSET(channel))) + +#define STM32_DMA_FEIF BIT(0) +#define STM32_DMA_DMEIF BIT(2) +#define STM32_DMA_TEIF BIT(3) +#define STM32_DMA_HTIF BIT(4) +#define STM32_DMA_TCIF BIT(5) +#define STM32_DMA_ALL 0x3d /* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) +#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) + +#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) +#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) +#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) +#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) + +#define STM32_CRC_CR_RESET BIT(0) +#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) +#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) +#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) +#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) +#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) +#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) +#define STM32_CRC_CR_REV_IN_WORD (3 << 5) +#define STM32_CRC_CR_REV_OUT BIT(7) /* --- PMSE --- */ -#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) -#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) -#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) -#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) -#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) -#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) -#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) -#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x) * 4) -#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) -#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) -#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) -#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) -#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) -#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) -#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) -#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) -#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) -#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) -#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) - -/* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) +#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) +#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) +#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) +#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) +#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) +#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) +#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) +#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x)*4) +#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) +#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) +#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) +#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) +#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) +#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) +#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) +#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) +#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) +#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) +#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) /* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) +#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) +#define STM32_RNG_CR_RNGEN BIT(2) +#define STM32_RNG_CR_IE BIT(3) +#define STM32_RNG_CR_CED BIT(5) +#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) +#define STM32_RNG_SR_DRDY BIT(0) +#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) /* --- AXI interconnect --- */ /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) +#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x)) +#define WRITE_ISS_OVERRIDE BIT(1) +#define READ_ISS_OVERRIDE BIT(0) /* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) +#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) +#define STM32_UNIQUE_ID_LENGTH (3 * 4) #endif /* !__ASSEMBLER__ */ diff --git a/chip/stm32/registers-stm32g4.h b/chip/stm32/registers-stm32g4.h index 5ad6194795..4610bb1e98 100644 --- a/chip/stm32/registers-stm32g4.h +++ b/chip/stm32/registers-stm32g4.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,87 +19,87 @@ #endif /* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_TAMPER_STAMP 2 -#define STM32_IRQ_RTC_WAKEUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#define STM32_IRQ_ADC1 18 -#define STM32_IRQ_USB_HP 19 -#define STM32_IRQ_USB_LP 20 -#define STM32_IRQ_FDCAN_IT0 21 -#define STM32_IRQ_FDCAN_IT1 22 -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_TIM15 24 -#define STM32_IRQ_TIM16 25 -#define STM32_IRQ_TIM17 26 -#define STM32_IRQ_TIM1_CC 27 -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_TIM3 29 -#define STM32_IRQ_TIM4 30 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_USB_FS_WAKEUP 42 -#define STM32_IRQ_TIM8_BREAK 43 -#define STM32_IRQ_TIM8_UP 44 -#define STM32_IRQ_TIM8_TRG_COM 45 -#define STM32_IRQ_TIM8_CC 46 -#define STM32_IRQ_LPTIM1 49 -#define STM32_IRQ_SPI3 51 -#define STM32_IRQ_USART4 52 -#define STM32_IRQ_TIM6_DAC 54 -#define STM32_IRQ_TIM7 55 -#define STM32_IRQ_DMA2_CHANNEL1 56 -#define STM32_IRQ_DMA2_CHANNEL2 57 -#define STM32_IRQ_DMA2_CHANNEL3 58 -#define STM32_IRQ_DMA2_CHANNEL4 59 -#define STM32_IRQ_DMA2_CHANNEL5 60 -#define STM32_IRQ_UCPD1 63 -#define STM32_IRQ_COMP_1_2_3 64 -#define STM32_IRQ_COMP_4 65 -#define STM32_IRQ_CRS 75 -#define STM32_IRQ_SAI1 76 -#define STM32_IRQ_FPU 81 -#define STM32_IRQ_RNG 90 -#define STM32_IRQ_LPUART 91 -#define STM32_IRQ_I2C3_EV 92 -#define STM32_IRQ_I2C3_ER 93 -#define STM32_IRQ_DMAMUX_OVR 94 -#define STM32_IRQ_DMA1_CHANNEL8 96 -#define STM32_IRQ_DMA2_CHANNEL6 97 -#define STM32_IRQ_DMA2_CHANNEL7 98 -#define STM32_IRQ_DMA2_CHANNEL8 99 -#define STM32_IRQ_CORDIC 100 -#define STM32_IRQ_FMAC 101 +#define STM32_IRQ_WWDG 0 +#define STM32_IRQ_PVD 1 +#define STM32_IRQ_TAMPER_STAMP 2 +#define STM32_IRQ_RTC_WAKEUP 3 +#define STM32_IRQ_FLASH 4 +#define STM32_IRQ_RCC 5 +#define STM32_IRQ_EXTI0 6 +#define STM32_IRQ_EXTI1 7 +#define STM32_IRQ_EXTI2 8 +#define STM32_IRQ_EXTI3 9 +#define STM32_IRQ_EXTI4 10 +#define STM32_IRQ_DMA_CHANNEL_1 11 +#define STM32_IRQ_DMA_CHANNEL_2 12 +#define STM32_IRQ_DMA_CHANNEL_3 13 +#define STM32_IRQ_DMA_CHANNEL_4 14 +#define STM32_IRQ_DMA_CHANNEL_5 15 +#define STM32_IRQ_DMA_CHANNEL_6 16 +#define STM32_IRQ_DMA_CHANNEL_7 17 +#define STM32_IRQ_ADC1 18 +#define STM32_IRQ_USB_HP 19 +#define STM32_IRQ_USB_LP 20 +#define STM32_IRQ_FDCAN_IT0 21 +#define STM32_IRQ_FDCAN_IT1 22 +#define STM32_IRQ_EXTI9_5 23 +#define STM32_IRQ_TIM15 24 +#define STM32_IRQ_TIM16 25 +#define STM32_IRQ_TIM17 26 +#define STM32_IRQ_TIM1_CC 27 +#define STM32_IRQ_TIM2 28 +#define STM32_IRQ_TIM3 29 +#define STM32_IRQ_TIM4 30 +#define STM32_IRQ_I2C1_EV 31 +#define STM32_IRQ_I2C1_ER 32 +#define STM32_IRQ_I2C2_EV 33 +#define STM32_IRQ_I2C2_ER 34 +#define STM32_IRQ_SPI1 35 +#define STM32_IRQ_SPI2 36 +#define STM32_IRQ_USART1 37 +#define STM32_IRQ_USART2 38 +#define STM32_IRQ_USART3 39 +#define STM32_IRQ_EXTI15_10 40 +#define STM32_IRQ_RTC_ALARM 41 +#define STM32_IRQ_USB_FS_WAKEUP 42 +#define STM32_IRQ_TIM8_BREAK 43 +#define STM32_IRQ_TIM8_UP 44 +#define STM32_IRQ_TIM8_TRG_COM 45 +#define STM32_IRQ_TIM8_CC 46 +#define STM32_IRQ_LPTIM1 49 +#define STM32_IRQ_SPI3 51 +#define STM32_IRQ_USART4 52 +#define STM32_IRQ_TIM6_DAC 54 +#define STM32_IRQ_TIM7 55 +#define STM32_IRQ_DMA2_CHANNEL1 56 +#define STM32_IRQ_DMA2_CHANNEL2 57 +#define STM32_IRQ_DMA2_CHANNEL3 58 +#define STM32_IRQ_DMA2_CHANNEL4 59 +#define STM32_IRQ_DMA2_CHANNEL5 60 +#define STM32_IRQ_UCPD1 63 +#define STM32_IRQ_COMP_1_2_3 64 +#define STM32_IRQ_COMP_4 65 +#define STM32_IRQ_CRS 75 +#define STM32_IRQ_SAI1 76 +#define STM32_IRQ_FPU 81 +#define STM32_IRQ_RNG 90 +#define STM32_IRQ_LPUART 91 +#define STM32_IRQ_I2C3_EV 92 +#define STM32_IRQ_I2C3_ER 93 +#define STM32_IRQ_DMAMUX_OVR 94 +#define STM32_IRQ_DMA1_CHANNEL8 96 +#define STM32_IRQ_DMA2_CHANNEL6 97 +#define STM32_IRQ_DMA2_CHANNEL7 98 +#define STM32_IRQ_DMA2_CHANNEL8 99 +#define STM32_IRQ_CORDIC 100 +#define STM32_IRQ_FMAC 101 /* LPUART gets accessed as UART9 in STM32 uart driver */ #define STM32_IRQ_USART9 STM32_IRQ_LPUART /* To simplify code generation, define DMA channel 13 - 14 */ -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 +#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 +#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 /* aliases for easier code sharing */ #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV @@ -111,144 +111,144 @@ #endif /* Embedded flash option bytes base address */ -#define STM32_OPTB_BANK1_BASE 0x1FFF7800UL -#define STM32_OPTB_BANK2_BASE 0x1FFF8000UL +#define STM32_OPTB_BANK1_BASE 0x1FFF7800UL +#define STM32_OPTB_BANK2_BASE 0x1FFF8000UL /* Peripheral base addresses */ -#define STM32_PERIPH_BASE (0x40000000UL) +#define STM32_PERIPH_BASE (0x40000000UL) /* Peripheral memory map */ -#define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000UL) -#define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000UL) -#define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000UL) -#define STM32_AHB2PERIPH_BASE (STM32_PERIPH_BASE + 0x08000000UL) +#define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000UL) +#define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000UL) +#define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000UL) +#define STM32_AHB2PERIPH_BASE (STM32_PERIPH_BASE + 0x08000000UL) /* APB1 peripherals */ -#define STM32_APB1PERIPH(offset) (STM32_APB1PERIPH_BASE + offset) -#define STM32_TIM2_BASE STM32_APB1PERIPH(0x0000UL) -#define STM32_TIM3_BASE STM32_APB1PERIPH(0x0400UL) -#define STM32_TIM4_BASE STM32_APB1PERIPH(0x0800UL) -#define STM32_TIM6_BASE STM32_APB1PERIPH(0x1000UL) -#define STM32_TIM7_BASE STM32_APB1PERIPH(0x1400UL) -#define STM32_CRS_BASE STM32_APB1PERIPH(0x2000UL) -#define STM32_TAMP_BASE STM32_APB1PERIPH(0x2400UL) -#define STM32_RTC_BASE STM32_APB1PERIPH(0x2800UL) -#define STM32_WWDG_BASE STM32_APB1PERIPH(0x2C00UL) -#define STM32_IWDG_BASE STM32_APB1PERIPH(0x3000UL) -#define STM32_SPI2_BASE STM32_APB1PERIPH(0x3800UL) -#define STM32_SPI3_BASE STM32_APB1PERIPH(0x3C00UL) -#define STM32_USART2_BASE STM32_APB1PERIPH(0x4400UL) -#define STM32_USART3_BASE STM32_APB1PERIPH(0x4800UL) -#define STM32_UART4_BASE STM32_APB1PERIPH(0x4C00UL) -#define STM32_I2C1_BASE STM32_APB1PERIPH(0x5400UL) -#define STM32_I2C2_BASE STM32_APB1PERIPH(0x5800UL) +#define STM32_APB1PERIPH(offset) (STM32_APB1PERIPH_BASE + offset) +#define STM32_TIM2_BASE STM32_APB1PERIPH(0x0000UL) +#define STM32_TIM3_BASE STM32_APB1PERIPH(0x0400UL) +#define STM32_TIM4_BASE STM32_APB1PERIPH(0x0800UL) +#define STM32_TIM6_BASE STM32_APB1PERIPH(0x1000UL) +#define STM32_TIM7_BASE STM32_APB1PERIPH(0x1400UL) +#define STM32_CRS_BASE STM32_APB1PERIPH(0x2000UL) +#define STM32_TAMP_BASE STM32_APB1PERIPH(0x2400UL) +#define STM32_RTC_BASE STM32_APB1PERIPH(0x2800UL) +#define STM32_WWDG_BASE STM32_APB1PERIPH(0x2C00UL) +#define STM32_IWDG_BASE STM32_APB1PERIPH(0x3000UL) +#define STM32_SPI2_BASE STM32_APB1PERIPH(0x3800UL) +#define STM32_SPI3_BASE STM32_APB1PERIPH(0x3C00UL) +#define STM32_USART2_BASE STM32_APB1PERIPH(0x4400UL) +#define STM32_USART3_BASE STM32_APB1PERIPH(0x4800UL) +#define STM32_UART4_BASE STM32_APB1PERIPH(0x4C00UL) +#define STM32_I2C1_BASE STM32_APB1PERIPH(0x5400UL) +#define STM32_I2C2_BASE STM32_APB1PERIPH(0x5800UL) /* USB_IP Peripheral Registers base address */ -#define STM32_USB_FS_BASE STM32_APB1PERIPH(0x5C00UL) +#define STM32_USB_FS_BASE STM32_APB1PERIPH(0x5C00UL) /* USB_IP Packet Memory Area base address */ -#define STM32_USB_PMAADDR STM32_APB1PERIPH(0x6000UL) -#define STM32_FDCAN1_BASE STM32_APB1PERIPH(0x6400UL) +#define STM32_USB_PMAADDR STM32_APB1PERIPH(0x6000UL) +#define STM32_FDCAN1_BASE STM32_APB1PERIPH(0x6400UL) /* FDCAN configuration registers base address */ -#define STM32_FDCAN_CONFIG_BASE STM32_APB1PERIPH(0x6500UL) -#define STM32_PWR_BASE STM32_APB1PERIPH(0x7000UL) -#define STM32_I2C3_BASE STM32_APB1PERIPH(0x7800UL) -#define STM32_LPTIM1_BASE STM32_APB1PERIPH(0x7C00UL) -#define STM32_LPUART1_BASE STM32_APB1PERIPH(0x8000UL) -#define STM32_I2C4_BASE STM32_APB1PERIPH(0x8400UL) +#define STM32_FDCAN_CONFIG_BASE STM32_APB1PERIPH(0x6500UL) +#define STM32_PWR_BASE STM32_APB1PERIPH(0x7000UL) +#define STM32_I2C3_BASE STM32_APB1PERIPH(0x7800UL) +#define STM32_LPTIM1_BASE STM32_APB1PERIPH(0x7C00UL) +#define STM32_LPUART1_BASE STM32_APB1PERIPH(0x8000UL) +#define STM32_I2C4_BASE STM32_APB1PERIPH(0x8400UL) /* UART9 is used as link to LPUART in STM32 uart.c implementation */ -#define STM32_USART9_BASE STM32_APB1PERIPH(0x8000UL) -#define STM32_I2C4_BASE STM32_APB1PERIPH(0x8400UL) -#define STM32_UCPD1_BASE STM32_APB1PERIPH(0xA000UL) -#define STM32_SRAMCAN_BASE STM32_APB1PERIPH(0xA400UL) +#define STM32_USART9_BASE STM32_APB1PERIPH(0x8000UL) +#define STM32_I2C4_BASE STM32_APB1PERIPH(0x8400UL) +#define STM32_UCPD1_BASE STM32_APB1PERIPH(0xA000UL) +#define STM32_SRAMCAN_BASE STM32_APB1PERIPH(0xA400UL) /* APB2 peripherals */ -#define STM32_APB2PERIPH(offset) (STM32_APB2PERIPH_BASE + offset) -#define STM32_SYSCFG_BASE STM32_APB2PERIPH(0x0000UL) -#define STM32_VREFBUF_BASE STM32_APB2PERIPH(0x0030UL) -#define STM32_COMP1_BASE STM32_APB2PERIPH(0x0200UL) -#define STM32_COMP2_BASE STM32_APB2PERIPH(0x0204UL) -#define STM32_COMP3_BASE STM32_APB2PERIPH(0x0208UL) -#define STM32_COMP4_BASE STM32_APB2PERIPH(0x020CUL) -#define STM32_OPAMP_BASE STM32_APB2PERIPH(0x0300UL) -#define STM32_OPAMP1_BASE STM32_APB2PERIPH(0x0300UL) -#define STM32_OPAMP2_BASE STM32_APB2PERIPH(0x0304UL) -#define STM32_OPAMP3_BASE STM32_APB2PERIPH(0x0308UL) -#define STM32_EXTI_BASE STM32_APB2PERIPH(0x0400UL) -#define STM32_TIM1_BASE STM32_APB2PERIPH(0x2C00UL) -#define STM32_SPI1_BASE STM32_APB2PERIPH(0x3000UL) -#define STM32_TIM8_BASE STM32_APB2PERIPH(0x3400UL) -#define STM32_USART1_BASE STM32_APB2PERIPH(0x3800UL) -#define STM32_TIM15_BASE STM32_APB2PERIPH(0x4000UL) -#define STM32_TIM16_BASE STM32_APB2PERIPH(0x4400UL) -#define STM32_TIM17_BASE STM32_APB2PERIPH(0x4800UL) -#define STM32_SAI1_BASE STM32_APB2PERIPH(0x5400UL) -#define STM32_SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) -#define STM32_SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) +#define STM32_APB2PERIPH(offset) (STM32_APB2PERIPH_BASE + offset) +#define STM32_SYSCFG_BASE STM32_APB2PERIPH(0x0000UL) +#define STM32_VREFBUF_BASE STM32_APB2PERIPH(0x0030UL) +#define STM32_COMP1_BASE STM32_APB2PERIPH(0x0200UL) +#define STM32_COMP2_BASE STM32_APB2PERIPH(0x0204UL) +#define STM32_COMP3_BASE STM32_APB2PERIPH(0x0208UL) +#define STM32_COMP4_BASE STM32_APB2PERIPH(0x020CUL) +#define STM32_OPAMP_BASE STM32_APB2PERIPH(0x0300UL) +#define STM32_OPAMP1_BASE STM32_APB2PERIPH(0x0300UL) +#define STM32_OPAMP2_BASE STM32_APB2PERIPH(0x0304UL) +#define STM32_OPAMP3_BASE STM32_APB2PERIPH(0x0308UL) +#define STM32_EXTI_BASE STM32_APB2PERIPH(0x0400UL) +#define STM32_TIM1_BASE STM32_APB2PERIPH(0x2C00UL) +#define STM32_SPI1_BASE STM32_APB2PERIPH(0x3000UL) +#define STM32_TIM8_BASE STM32_APB2PERIPH(0x3400UL) +#define STM32_USART1_BASE STM32_APB2PERIPH(0x3800UL) +#define STM32_TIM15_BASE STM32_APB2PERIPH(0x4000UL) +#define STM32_TIM16_BASE STM32_APB2PERIPH(0x4400UL) +#define STM32_TIM17_BASE STM32_APB2PERIPH(0x4800UL) +#define STM32_SAI1_BASE STM32_APB2PERIPH(0x5400UL) +#define STM32_SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define STM32_SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) /* AHB1 peripherals */ -#define STM32_AHB1PERIPH(offset) (STM32_AHB1PERIPH_BASE + offset) -#define STM32_DMA1_BASE STM32_AHB1PERIPH(0x0000UL) -#define STM32_DMA2_BASE STM32_AHB1PERIPH(0x0400UL) -#define STM32_DMAMUX_BASE STM32_AHB1PERIPH(0x0800UL) -#define STM32_CORDIC_BASE STM32_AHB1PERIPH(0x0C00UL) -#define STM32_RCC_BASE STM32_AHB1PERIPH(0x1000UL) -#define STM32_FMAC_BASE STM32_AHB1PERIPH(0x1400UL) -#define STM32_FLASH_REGS_BASE STM32_AHB1PERIPH(0x2000UL) -#define STM32_CRC_BASE STM32_AHB1PERIPH(0x3000UL) - -#define STM32_DMA1_CHAN(offset) (STM32_DMA1_BASE + offset) -#define STM32_DMA1_Channel1_BASE STM32_DMA1_CHAN(0x0008UL) -#define STM32_DMA1_Channel2_BASE STM32_DMA1_CHAN(0x001CUL) -#define STM32_DMA1_Channel3_BASE STM32_DMA1_CHAN(0x0030UL) -#define STM32_DMA1_Channel4_BASE STM32_DMA1_CHAN(0x0044UL) -#define STM32_DMA1_Channel5_BASE STM32_DMA1_CHAN(0x0058UL) -#define STM32_DMA1_Channel6_BASE STM32_DMA1_CHAN(0x006CUL) - -#define STM32_DMA2_CHAN(offset) (STM32_DMA2_BASE + offset) -#define STM32_DMA2_Channel1_BASE STM32_DMA2_CHAN(0x0008UL) -#define STM32_DMA2_Channel2_BASE STM32_DMA2_CHAN(0x001CUL) -#define STM32_DMA2_Channel3_BASE STM32_DMA2_CHAN(0x0030UL) -#define STM32_DMA2_Channel4_BASE STM32_DMA2_CHAN(0x0044UL) -#define STM32_DMA2_Channel5_BASE STM32_DMA2_CHAN(0x0058UL) -#define STM32_DMA2_Channel6_BASE STM32_DMA2_CHAN(0x006CUL) - -#define STM32_DMAMUX(offset) (STM32_DMAMUX_BASE + offset) -#define STM32_DMAMUX_Channel0_BASE STM32_DMAMUX(0x0000UL) -#define STM32_DMAMUX_Channel1_BASE STM32_DMAMUX(0x0004UL) -#define STM32_DMAMUX_Channel2_BASE STM32_DMAMUX(0x0008UL) -#define STM32_DMAMUX_Channel3_BASE STM32_DMAMUX(0x000CUL) -#define STM32_DMAMUX_Channel4_BASE STM32_DMAMUX(0x0010UL) -#define STM32_DMAMUX_Channel5_BASE STM32_DMAMUX(0x0014UL) -#define STM32_DMAMUX_Channel6_BASE STM32_DMAMUX(0x0020UL) -#define STM32_DMAMUX_Channel7_BASE STM32_DMAMUX(0x0024UL) -#define STM32_DMAMUX_Channel8_BASE STM32_DMAMUX(0x0028UL) -#define STM32_DMAMUX_Channel9_BASE STM32_DMAMUX(0x002CUL) -#define STM32_DMAMUX_Channel10_BASE STM32_DMAMUX(0x0030UL) -#define STM32_DMAMUX_Channel11_BASE STM32_DMAMUX(0x0034UL) -#define STM32_DMAMUX_RequestGenerator0_BASE STM32_DMAMUX(0x0100UL) -#define STM32_DMAMUX_RequestGenerator1_BASE STM32_DMAMUX(0x0104UL) -#define STM32_DMAMUX_RequestGenerator2_BASE STM32_DMAMUX(0x0108UL) -#define STM32_DMAMUX_RequestGenerator3_BASE STM32_DMAMUX(0x010CUL) -#define STM32_DMAMUX_ChannelStatus_BASE STM32_DMAMUX(0x0080UL) -#define STM32_DMAMUX_RequestGenStatus_BASE STM32_DMAMUX(0x0140UL) +#define STM32_AHB1PERIPH(offset) (STM32_AHB1PERIPH_BASE + offset) +#define STM32_DMA1_BASE STM32_AHB1PERIPH(0x0000UL) +#define STM32_DMA2_BASE STM32_AHB1PERIPH(0x0400UL) +#define STM32_DMAMUX_BASE STM32_AHB1PERIPH(0x0800UL) +#define STM32_CORDIC_BASE STM32_AHB1PERIPH(0x0C00UL) +#define STM32_RCC_BASE STM32_AHB1PERIPH(0x1000UL) +#define STM32_FMAC_BASE STM32_AHB1PERIPH(0x1400UL) +#define STM32_FLASH_REGS_BASE STM32_AHB1PERIPH(0x2000UL) +#define STM32_CRC_BASE STM32_AHB1PERIPH(0x3000UL) + +#define STM32_DMA1_CHAN(offset) (STM32_DMA1_BASE + offset) +#define STM32_DMA1_Channel1_BASE STM32_DMA1_CHAN(0x0008UL) +#define STM32_DMA1_Channel2_BASE STM32_DMA1_CHAN(0x001CUL) +#define STM32_DMA1_Channel3_BASE STM32_DMA1_CHAN(0x0030UL) +#define STM32_DMA1_Channel4_BASE STM32_DMA1_CHAN(0x0044UL) +#define STM32_DMA1_Channel5_BASE STM32_DMA1_CHAN(0x0058UL) +#define STM32_DMA1_Channel6_BASE STM32_DMA1_CHAN(0x006CUL) + +#define STM32_DMA2_CHAN(offset) (STM32_DMA2_BASE + offset) +#define STM32_DMA2_Channel1_BASE STM32_DMA2_CHAN(0x0008UL) +#define STM32_DMA2_Channel2_BASE STM32_DMA2_CHAN(0x001CUL) +#define STM32_DMA2_Channel3_BASE STM32_DMA2_CHAN(0x0030UL) +#define STM32_DMA2_Channel4_BASE STM32_DMA2_CHAN(0x0044UL) +#define STM32_DMA2_Channel5_BASE STM32_DMA2_CHAN(0x0058UL) +#define STM32_DMA2_Channel6_BASE STM32_DMA2_CHAN(0x006CUL) + +#define STM32_DMAMUX(offset) (STM32_DMAMUX_BASE + offset) +#define STM32_DMAMUX_Channel0_BASE STM32_DMAMUX(0x0000UL) +#define STM32_DMAMUX_Channel1_BASE STM32_DMAMUX(0x0004UL) +#define STM32_DMAMUX_Channel2_BASE STM32_DMAMUX(0x0008UL) +#define STM32_DMAMUX_Channel3_BASE STM32_DMAMUX(0x000CUL) +#define STM32_DMAMUX_Channel4_BASE STM32_DMAMUX(0x0010UL) +#define STM32_DMAMUX_Channel5_BASE STM32_DMAMUX(0x0014UL) +#define STM32_DMAMUX_Channel6_BASE STM32_DMAMUX(0x0020UL) +#define STM32_DMAMUX_Channel7_BASE STM32_DMAMUX(0x0024UL) +#define STM32_DMAMUX_Channel8_BASE STM32_DMAMUX(0x0028UL) +#define STM32_DMAMUX_Channel9_BASE STM32_DMAMUX(0x002CUL) +#define STM32_DMAMUX_Channel10_BASE STM32_DMAMUX(0x0030UL) +#define STM32_DMAMUX_Channel11_BASE STM32_DMAMUX(0x0034UL) +#define STM32_DMAMUX_RequestGenerator0_BASE STM32_DMAMUX(0x0100UL) +#define STM32_DMAMUX_RequestGenerator1_BASE STM32_DMAMUX(0x0104UL) +#define STM32_DMAMUX_RequestGenerator2_BASE STM32_DMAMUX(0x0108UL) +#define STM32_DMAMUX_RequestGenerator3_BASE STM32_DMAMUX(0x010CUL) +#define STM32_DMAMUX_ChannelStatus_BASE STM32_DMAMUX(0x0080UL) +#define STM32_DMAMUX_RequestGenStatus_BASE STM32_DMAMUX(0x0140UL) /* AHB2 peripherals */ -#define STM32_AHB2PERIPH(offset) (STM32_AHB2PERIPH_BASE + offset) -#define STM32_GPIOA_BASE STM32_AHB2PERIPH(0x0000UL) -#define STM32_GPIOB_BASE STM32_AHB2PERIPH(0x0400UL) -#define STM32_GPIOC_BASE STM32_AHB2PERIPH(0x0800UL) -#define STM32_GPIOD_BASE STM32_AHB2PERIPH(0x0C00UL) -#define STM32_GPIOE_BASE STM32_AHB2PERIPH(0x1000UL) -#define STM32_GPIOF_BASE STM32_AHB2PERIPH(0x1400UL) -#define STM32_GPIOG_BASE STM32_AHB2PERIPH(0x1800UL) -#define STM32_ADC1_BASE STM32_AHB2PERIPH(0x08000000UL) -#define STM32_ADC2_BASE STM32_AHB2PERIPH(0x08000100UL) -#define STM32_ADC12_COMMON_BASE STM32_AHB2PERIPH(0x08000300UL) -#define STM32_DAC_BASE STM32_AHB2PERIPH(0x08000800UL) -#define STM32_DAC1_BASE STM32_AHB2PERIPH(0x08000800UL) -#define STM32_DAC3_BASE STM32_AHB2PERIPH(0x08001000UL) -#define STM32_RNG_BASE STM32_AHB2PERIPH(0x08060800UL) - -#define STM32_UNIQUE_ID_BASE 0x1FFF7590 -#define STM32_DBGMCU_BASE 0xE0042000 +#define STM32_AHB2PERIPH(offset) (STM32_AHB2PERIPH_BASE + offset) +#define STM32_GPIOA_BASE STM32_AHB2PERIPH(0x0000UL) +#define STM32_GPIOB_BASE STM32_AHB2PERIPH(0x0400UL) +#define STM32_GPIOC_BASE STM32_AHB2PERIPH(0x0800UL) +#define STM32_GPIOD_BASE STM32_AHB2PERIPH(0x0C00UL) +#define STM32_GPIOE_BASE STM32_AHB2PERIPH(0x1000UL) +#define STM32_GPIOF_BASE STM32_AHB2PERIPH(0x1400UL) +#define STM32_GPIOG_BASE STM32_AHB2PERIPH(0x1800UL) +#define STM32_ADC1_BASE STM32_AHB2PERIPH(0x08000000UL) +#define STM32_ADC2_BASE STM32_AHB2PERIPH(0x08000100UL) +#define STM32_ADC12_COMMON_BASE STM32_AHB2PERIPH(0x08000300UL) +#define STM32_DAC_BASE STM32_AHB2PERIPH(0x08000800UL) +#define STM32_DAC1_BASE STM32_AHB2PERIPH(0x08000800UL) +#define STM32_DAC3_BASE STM32_AHB2PERIPH(0x08001000UL) +#define STM32_RNG_BASE STM32_AHB2PERIPH(0x08060800UL) + +#define STM32_UNIQUE_ID_BASE 0x1FFF7590 +#define STM32_DBGMCU_BASE 0xE0042000 #ifndef __ASSEMBLER__ @@ -256,319 +256,299 @@ /* --- UCPD --- */ #define STM32_UCPD_REG(port, offset) \ - REG32(((STM32_UCPD1_BASE + ((port) * 0x400)) + (offset))) - -#define STM32_UCPD_CFGR1(port) STM32_UCPD_REG(port, 0x00) -#define STM32_UCPD_CFGR2(port) STM32_UCPD_REG(port, 0x04) -#define STM32_UCPD_CR(port) STM32_UCPD_REG(port, 0x0c) -#define STM32_UCPD_IMR(port) STM32_UCPD_REG(port, 0x10) -#define STM32_UCPD_SR(port) STM32_UCPD_REG(port, 0x14) -#define STM32_UCPD_ICR(port) STM32_UCPD_REG(port, 0x18) -#define STM32_UCPD_TX_ORDSETR(port) STM32_UCPD_REG(port, 0x1c) -#define STM32_UCPD_TX_PAYSZR(port) STM32_UCPD_REG(port, 0x20) -#define STM32_UCPD_TXDR(port) STM32_UCPD_REG(port, 0x24) -#define STM32_UCPD_RX_ORDSETR(port) STM32_UCPD_REG(port, 0x28) -#define STM32_UCPD_RX_PAYSZR(port) STM32_UCPD_REG(port, 0x2c) -#define STM32_UCPD_RXDR(port) STM32_UCPD_REG(port, 0x30) -#define STM32_UCPD_RX_ORDEXTR1(port) STM32_UCPD_REG(port, 0x34) -#define STM32_UCPD_RX_ORDEXTR2(port) STM32_UCPD_REG(port, 0x38) + REG32(((STM32_UCPD1_BASE + ((port)*0x400)) + (offset))) + +#define STM32_UCPD_CFGR1(port) STM32_UCPD_REG(port, 0x00) +#define STM32_UCPD_CFGR2(port) STM32_UCPD_REG(port, 0x04) +#define STM32_UCPD_CR(port) STM32_UCPD_REG(port, 0x0c) +#define STM32_UCPD_IMR(port) STM32_UCPD_REG(port, 0x10) +#define STM32_UCPD_SR(port) STM32_UCPD_REG(port, 0x14) +#define STM32_UCPD_ICR(port) STM32_UCPD_REG(port, 0x18) +#define STM32_UCPD_TX_ORDSETR(port) STM32_UCPD_REG(port, 0x1c) +#define STM32_UCPD_TX_PAYSZR(port) STM32_UCPD_REG(port, 0x20) +#define STM32_UCPD_TXDR(port) STM32_UCPD_REG(port, 0x24) +#define STM32_UCPD_RX_ORDSETR(port) STM32_UCPD_REG(port, 0x28) +#define STM32_UCPD_RX_PAYSZR(port) STM32_UCPD_REG(port, 0x2c) +#define STM32_UCPD_RXDR(port) STM32_UCPD_REG(port, 0x30) +#define STM32_UCPD_RX_ORDEXTR1(port) STM32_UCPD_REG(port, 0x34) +#define STM32_UCPD_RX_ORDEXTR2(port) STM32_UCPD_REG(port, 0x38) /* --- UCPD CFGR1 Bit Definitions --- */ -#define STM32_UCPD_CFGR1_HBITCLKD_SHIFT 0 -#define STM32_UCPD_CFGR1_HBITCLKD_MASK ((0x3f) << \ - (STM32_UCPD_CFGR1_HBITCLKD_SHIFT)) -#define STM32_UCPD_CFGR1_HBITCLKD_VAL(x) ((x) << \ - STM32_UCPD_CFGR1_HBITCLKD_SHIFT) -#define STM32_UCPD_CFGR1_IFRGAP_SHIFT 6 -#define STM32_UCPD_CFGR1_IFRGAP_MASK ((0x1f) << \ - (STM32_UCPD_CFGR1_IFRGAP_SHIFT)) -#define STM32_UCPD_CFGR1_IFRGAP_VAL(x) ((x) << \ - STM32_UCPD_CFGR1_IFRGAP_SHIFT) -#define STM32_UCPD_CFGR1_TRANSWIN_SHIFT 11 -#define STM32_UCPD_CFGR1_TRANSWIN_MASK ((0x1f) << \ - (STM32_UCPD_CFGR1_TRANSWIN_SHIFT)) -#define STM32_UCPD_CFGR1_TRANSWIN_VAL(x) ((x) << \ - STM32_UCPD_CFGR1_TRANSWIN_SHIFT) -#define STM32_UCPD_CFGR1_PSC_CLK_SHIFT 17 -#define STM32_UCPD_CFGR1_PSC_CLK_MASK ((0x7) << \ - STM32_UCPD_CFGR1_PSC_CLK_SHIFT) -#define STM32_UCPD_CFGR1_PSC_CLK_VAL(x) ((x) << \ - STM32_UCPD_CFGR1_PSC_CLK_SHIFT) -#define STM32_UCPD_CFGR1_RXORDSETEN_SHIFT 20 -#define STM32_UCPD_CFGR1_RXORDSETEN_MASK ((0x1ff) << \ - STM32_UCPD_CFGR1_RXORDSETEN_SHIFT) -#define STM32_UCPD_CFGR1_RXORDSETEN_VAL(x) ((x) << \ - STM32_UCPD_CFGR1_RXORDSETEN_SHIFT) -#define STM32_UCPD_CFGR1_TXDMAEN BIT(29) -#define STM32_UCPD_CFGR1_RXDMAEN BIT(30) -#define STM32_UCPD_CFGR1_UCPDEN BIT(31) +#define STM32_UCPD_CFGR1_HBITCLKD_SHIFT 0 +#define STM32_UCPD_CFGR1_HBITCLKD_MASK \ + ((0x3f) << (STM32_UCPD_CFGR1_HBITCLKD_SHIFT)) +#define STM32_UCPD_CFGR1_HBITCLKD_VAL(x) \ + ((x) << STM32_UCPD_CFGR1_HBITCLKD_SHIFT) +#define STM32_UCPD_CFGR1_IFRGAP_SHIFT 6 +#define STM32_UCPD_CFGR1_IFRGAP_MASK ((0x1f) << (STM32_UCPD_CFGR1_IFRGAP_SHIFT)) +#define STM32_UCPD_CFGR1_IFRGAP_VAL(x) ((x) << STM32_UCPD_CFGR1_IFRGAP_SHIFT) +#define STM32_UCPD_CFGR1_TRANSWIN_SHIFT 11 +#define STM32_UCPD_CFGR1_TRANSWIN_MASK \ + ((0x1f) << (STM32_UCPD_CFGR1_TRANSWIN_SHIFT)) +#define STM32_UCPD_CFGR1_TRANSWIN_VAL(x) \ + ((x) << STM32_UCPD_CFGR1_TRANSWIN_SHIFT) +#define STM32_UCPD_CFGR1_PSC_CLK_SHIFT 17 +#define STM32_UCPD_CFGR1_PSC_CLK_MASK ((0x7) << STM32_UCPD_CFGR1_PSC_CLK_SHIFT) +#define STM32_UCPD_CFGR1_PSC_CLK_VAL(x) ((x) << STM32_UCPD_CFGR1_PSC_CLK_SHIFT) +#define STM32_UCPD_CFGR1_RXORDSETEN_SHIFT 20 +#define STM32_UCPD_CFGR1_RXORDSETEN_MASK \ + ((0x1ff) << STM32_UCPD_CFGR1_RXORDSETEN_SHIFT) +#define STM32_UCPD_CFGR1_RXORDSETEN_VAL(x) \ + ((x) << STM32_UCPD_CFGR1_RXORDSETEN_SHIFT) +#define STM32_UCPD_CFGR1_TXDMAEN BIT(29) +#define STM32_UCPD_CFGR1_RXDMAEN BIT(30) +#define STM32_UCPD_CFGR1_UCPDEN BIT(31) /* --- UCPD CFGR2 Bit Definitions --- */ -#define STM32_UCPD_CFGR2_RXFILTDIS BIT(0) -#define STM32_UCPD_CFGR2_RXFILT2N3 BIT(1) -#define STM32_UCPD_CFGR2_FORCECLK BIT(2) -#define STM32_UCPD_CFGR2_WUPEN BIT(3) +#define STM32_UCPD_CFGR2_RXFILTDIS BIT(0) +#define STM32_UCPD_CFGR2_RXFILT2N3 BIT(1) +#define STM32_UCPD_CFGR2_FORCECLK BIT(2) +#define STM32_UCPD_CFGR2_WUPEN BIT(3) /* --- UCPD CR Bit Definitions --- */ -#define STM32_UCPD_CR_TXMODE_SHIFT 0 -#define STM32_UCPD_CR_TXMODE_MASK ((0x3) << \ - (STM32_UCPD_CR_TXMODE_SHIFT)) -#define STM32_UCPD_CR_TXMODE_VAL(x) ((x) << STM32_UCPD_CR_TXMODE_SHIFT) -#define STM32_UCPD_CR_TXSEND BIT(2) -#define STM32_UCPD_CR_TXHRST BIT(3) -#define STM32_UCPD_CR_RXMODE BIT(4) -#define STM32_UCPD_CR_PHYRXEN BIT(5) -#define STM32_UCPD_CR_PHYCCSEL BIT(6) -#define STM32_UCPD_CR_ANASUBMODE_SHIFT 7 -#define STM32_UCPD_CR_ANASUBMODE_MASK ((0x3) << \ - (STM32_UCPD_CR_ANASUBMODE_SHIFT)) -#define STM32_UCPD_CR_ANASUBMODE_VAL(x) ((x) << \ - STM32_UCPD_CR_ANASUBMODE_SHIFT) -#define STM32_UCPD_CR_ANAMODE BIT(9) -#define STM32_UCPD_CR_CCENABLE_SHIFT 10 -#define STM32_UCPD_CR_CCENABLE_MASK ((0x3) << \ - (STM32_UCPD_CR_CCENABLE_SHIFT)) -#define STM32_UCPD_CR_CCENABLE_VAL(x) ((x) << \ - STM32_UCPD_CR_CCENABLE_SHIFT) -#define STM32_UCPD_CR_FRSRXEN BIT(16) -#define STM32_UCPD_CR_FRSTX BIT(17) -#define STM32_UCPD_CR_RDCH BIT(18) -#define STM32_UCPD_CR_CC1TCDIS BIT(20) -#define STM32_UCPD_CR_CC2TCDIS BIT(21) +#define STM32_UCPD_CR_TXMODE_SHIFT 0 +#define STM32_UCPD_CR_TXMODE_MASK ((0x3) << (STM32_UCPD_CR_TXMODE_SHIFT)) +#define STM32_UCPD_CR_TXMODE_VAL(x) ((x) << STM32_UCPD_CR_TXMODE_SHIFT) +#define STM32_UCPD_CR_TXSEND BIT(2) +#define STM32_UCPD_CR_TXHRST BIT(3) +#define STM32_UCPD_CR_RXMODE BIT(4) +#define STM32_UCPD_CR_PHYRXEN BIT(5) +#define STM32_UCPD_CR_PHYCCSEL BIT(6) +#define STM32_UCPD_CR_ANASUBMODE_SHIFT 7 +#define STM32_UCPD_CR_ANASUBMODE_MASK \ + ((0x3) << (STM32_UCPD_CR_ANASUBMODE_SHIFT)) +#define STM32_UCPD_CR_ANASUBMODE_VAL(x) ((x) << STM32_UCPD_CR_ANASUBMODE_SHIFT) +#define STM32_UCPD_CR_ANAMODE BIT(9) +#define STM32_UCPD_CR_CCENABLE_SHIFT 10 +#define STM32_UCPD_CR_CCENABLE_MASK ((0x3) << (STM32_UCPD_CR_CCENABLE_SHIFT)) +#define STM32_UCPD_CR_CCENABLE_VAL(x) ((x) << STM32_UCPD_CR_CCENABLE_SHIFT) +#define STM32_UCPD_CR_FRSRXEN BIT(16) +#define STM32_UCPD_CR_FRSTX BIT(17) +#define STM32_UCPD_CR_RDCH BIT(18) +#define STM32_UCPD_CR_CC1TCDIS BIT(20) +#define STM32_UCPD_CR_CC2TCDIS BIT(21) /* TX mode message types */ -#define STM32_UCPD_CR_TXMODE_DEF 0 -#define STM32_UCPD_CR_TXMODE_CBL_RST 1 -#define STM32_UCPD_CR_TXMODE_BIST 2 +#define STM32_UCPD_CR_TXMODE_DEF 0 +#define STM32_UCPD_CR_TXMODE_CBL_RST 1 +#define STM32_UCPD_CR_TXMODE_BIST 2 /* --- UCPD IMR Bit Definitions --- */ -#define STM32_UCPD_IMR_TXISIE BIT(0) -#define STM32_UCPD_IMR_TXMSGDISCIE BIT(1) -#define STM32_UCPD_IMR_TXMSGSENTIE BIT(2) -#define STM32_UCPD_IMR_TXMSGABTIE BIT(3) -#define STM32_UCPD_IMR_HRSTDISCIE BIT(4) -#define STM32_UCPD_IMR_HRSTSENTIE BIT(5) -#define STM32_UCPD_IMR_TXUNDIE BIT(6) -#define STM32_UCPD_IMR_RXNEIE BIT(8) -#define STM32_UCPD_IMR_RXORDDETIE BIT(9) -#define STM32_UCPD_IMR_RXHRSTDETIE BIT(10) -#define STM32_UCPD_IMR_RXOVRIE BIT(11) -#define STM32_UCPD_IMR_RXMSGENDIE BIT(12) -#define STM32_UCPD_IMR_TYPECEVT1IE BIT(14) -#define STM32_UCPD_IMR_TYPECEVT2IE BIT(15) -#define STM32_UCPD_IMR_FRSEVTIE BIT(20) +#define STM32_UCPD_IMR_TXISIE BIT(0) +#define STM32_UCPD_IMR_TXMSGDISCIE BIT(1) +#define STM32_UCPD_IMR_TXMSGSENTIE BIT(2) +#define STM32_UCPD_IMR_TXMSGABTIE BIT(3) +#define STM32_UCPD_IMR_HRSTDISCIE BIT(4) +#define STM32_UCPD_IMR_HRSTSENTIE BIT(5) +#define STM32_UCPD_IMR_TXUNDIE BIT(6) +#define STM32_UCPD_IMR_RXNEIE BIT(8) +#define STM32_UCPD_IMR_RXORDDETIE BIT(9) +#define STM32_UCPD_IMR_RXHRSTDETIE BIT(10) +#define STM32_UCPD_IMR_RXOVRIE BIT(11) +#define STM32_UCPD_IMR_RXMSGENDIE BIT(12) +#define STM32_UCPD_IMR_TYPECEVT1IE BIT(14) +#define STM32_UCPD_IMR_TYPECEVT2IE BIT(15) +#define STM32_UCPD_IMR_FRSEVTIE BIT(20) /* --- UCPD SR Bit Definitions --- */ -#define STM32_UCPD_SR_TXIS BIT(0) -#define STM32_UCPD_SR_TXMSGDISC BIT(1) -#define STM32_UCPD_SR_TXMSGSENT BIT(2) -#define STM32_UCPD_SR_TXMSGABT BIT(3) -#define STM32_UCPD_SR_HRSTDISC BIT(4) -#define STM32_UCPD_SR_HRSTSENT BIT(5) -#define STM32_UCPD_SR_TXUND BIT(6) -#define STM32_UCPD_SR_RXNE BIT(8) -#define STM32_UCPD_SR_RXORDDET BIT(9) -#define STM32_UCPD_SR_RXHRSTDET BIT(10) -#define STM32_UCPD_SR_RXOVR BIT(11) -#define STM32_UCPD_SR_RXMSGEND BIT(12) -#define STM32_UCPD_SR_RXERR BIT(13) -#define STM32_UCPD_SR_TYPECEVT1 BIT(14) -#define STM32_UCPD_SR_TYPECEVT2 BIT(15) -#define STM32_UCPD_SR_VSTATE_CC1_SHIFT 16 -#define STM32_UCPD_SR_VSTATE_CC1_MASK ((0x3) << \ - (STM32_UCPD_SR_VSTATE_CC1_SHIFT)) -#define STM32_UCPD_SR_VSTATE_CC1_VAL(x) ((x) << \ - STM32_UCPD_SR_VSTATE_CC1_SHIFT) -#define STM32_UCPD_SR_VSTATE_CC2_SHIFT 18 -#define STM32_UCPD_SR_VSTATE_CC2_MASK ((0x3) << \ - (STM32_UCPD_SR_VSTATE_CC2_SHIFT)) -#define STM32_UCPD_SR_VSTATE_CC2_VAL(x) ((x) << \ - STM32_UCPD_SR_VSTATE_CC2_SHIFT) -#define STM32_UCPD_SR_FRSEVT BIT(20) - -#define STM32_UCPD_SR_VSTATE_OPEN 3 -#define STM32_UCPD_SR_VSTATE_RA 0 +#define STM32_UCPD_SR_TXIS BIT(0) +#define STM32_UCPD_SR_TXMSGDISC BIT(1) +#define STM32_UCPD_SR_TXMSGSENT BIT(2) +#define STM32_UCPD_SR_TXMSGABT BIT(3) +#define STM32_UCPD_SR_HRSTDISC BIT(4) +#define STM32_UCPD_SR_HRSTSENT BIT(5) +#define STM32_UCPD_SR_TXUND BIT(6) +#define STM32_UCPD_SR_RXNE BIT(8) +#define STM32_UCPD_SR_RXORDDET BIT(9) +#define STM32_UCPD_SR_RXHRSTDET BIT(10) +#define STM32_UCPD_SR_RXOVR BIT(11) +#define STM32_UCPD_SR_RXMSGEND BIT(12) +#define STM32_UCPD_SR_RXERR BIT(13) +#define STM32_UCPD_SR_TYPECEVT1 BIT(14) +#define STM32_UCPD_SR_TYPECEVT2 BIT(15) +#define STM32_UCPD_SR_VSTATE_CC1_SHIFT 16 +#define STM32_UCPD_SR_VSTATE_CC1_MASK \ + ((0x3) << (STM32_UCPD_SR_VSTATE_CC1_SHIFT)) +#define STM32_UCPD_SR_VSTATE_CC1_VAL(x) ((x) << STM32_UCPD_SR_VSTATE_CC1_SHIFT) +#define STM32_UCPD_SR_VSTATE_CC2_SHIFT 18 +#define STM32_UCPD_SR_VSTATE_CC2_MASK \ + ((0x3) << (STM32_UCPD_SR_VSTATE_CC2_SHIFT)) +#define STM32_UCPD_SR_VSTATE_CC2_VAL(x) ((x) << STM32_UCPD_SR_VSTATE_CC2_SHIFT) +#define STM32_UCPD_SR_FRSEVT BIT(20) + +#define STM32_UCPD_SR_VSTATE_OPEN 3 +#define STM32_UCPD_SR_VSTATE_RA 0 /* --- UCPD ICR Bit Definitions --- */ -#define STM32_UCPD_ICR_TXMSGDISCCF BIT(1) -#define STM32_UCPD_ICR_TXMSGSENTCF BIT(2) -#define STM32_UCPD_ICR_TXMSGABTCF BIT(3) -#define STM32_UCPD_ICR_HRSTDISCCF BIT(4) -#define STM32_UCPD_ICR_HRSTSENTCF BIT(5) -#define STM32_UCPD_ICR_TXUNDCF BIT(6) -#define STM32_UCPD_ICR_RXORDDETCF BIT(9) -#define STM32_UCPD_ICR_RXHRSTDETCF BIT(10) -#define STM32_UCPD_ICR_RXOVRCF BIT(11) -#define STM32_UCPD_ICR_RXMSGENDCF BIT(12) -#define STM32_UCPD_ICR_TYPECEVT1CF BIT(14) -#define STM32_UCPD_ICR_TYPECEVT2CF BIT(15) -#define STM32_UCPD_ICR_FRSEVTCF BIT(20) - +#define STM32_UCPD_ICR_TXMSGDISCCF BIT(1) +#define STM32_UCPD_ICR_TXMSGSENTCF BIT(2) +#define STM32_UCPD_ICR_TXMSGABTCF BIT(3) +#define STM32_UCPD_ICR_HRSTDISCCF BIT(4) +#define STM32_UCPD_ICR_HRSTSENTCF BIT(5) +#define STM32_UCPD_ICR_TXUNDCF BIT(6) +#define STM32_UCPD_ICR_RXORDDETCF BIT(9) +#define STM32_UCPD_ICR_RXHRSTDETCF BIT(10) +#define STM32_UCPD_ICR_RXOVRCF BIT(11) +#define STM32_UCPD_ICR_RXMSGENDCF BIT(12) +#define STM32_UCPD_ICR_TYPECEVT1CF BIT(14) +#define STM32_UCPD_ICR_TYPECEVT2CF BIT(15) +#define STM32_UCPD_ICR_FRSEVTCF BIT(20) /* --- UCPD TX_ORDSETR Bit Definitions --- */ -#define STM32_UCPD_TX_ORDSETR_SHIFT 0 -#define STM32_UCPD_TX_ORDSETR_MASK ((0xfffff) << \ - (STM32_UCPD_TX_ORDSETR_SHIFT)) -#define STM32_UCPD_TX_ORDSETR_VAL(x) ((x) << STM32_UCPD_TX_ORDSETR_SHIFT) +#define STM32_UCPD_TX_ORDSETR_SHIFT 0 +#define STM32_UCPD_TX_ORDSETR_MASK ((0xfffff) << (STM32_UCPD_TX_ORDSETR_SHIFT)) +#define STM32_UCPD_TX_ORDSETR_VAL(x) ((x) << STM32_UCPD_TX_ORDSETR_SHIFT) /* --- UCPD TX_PAYSZR Bit Definitions --- */ -#define STM32_UCPD_TX_PAYSZR_SHIFT 0 -#define STM32_UCPD_TX_PAYSZR_MASK ((0x3ff) << \ - (STM32_UCPD_TX_PAYSZR_SHIFT)) -#define STM32_UCPD_TX_PAYSZR_VAL(x) ((x) << STM32_UCPD_TX_PAYSZR_SHIFT) +#define STM32_UCPD_TX_PAYSZR_SHIFT 0 +#define STM32_UCPD_TX_PAYSZR_MASK ((0x3ff) << (STM32_UCPD_TX_PAYSZR_SHIFT)) +#define STM32_UCPD_TX_PAYSZR_VAL(x) ((x) << STM32_UCPD_TX_PAYSZR_SHIFT) /* --- UCPD TXDR Bit Definitions --- */ -#define STM32_UCPD_TXDR_SHIFT 0 -#define STM32_UCPD_TXDR_MASK ((0xff) << \ - (STM32_UCPD_TXDR_SHIFT)) -#define STM32_UCPD_TXDR_VAL(x) ((x) << STM32_UCPD_TXDR_SHIFT) +#define STM32_UCPD_TXDR_SHIFT 0 +#define STM32_UCPD_TXDR_MASK ((0xff) << (STM32_UCPD_TXDR_SHIFT)) +#define STM32_UCPD_TXDR_VAL(x) ((x) << STM32_UCPD_TXDR_SHIFT) /* --- UCPD RX_ORDSETR Bit Definitions --- */ -#define STM32_UCPD_RXORDSETR_SHIFT 0 -#define STM32_UCPD_RXORDSETR_MASK ((0x7) << \ - (STM32_UCPD_RXORDSETR_SHIFT)) -#define STM32_UCPD_RXORDSETR_VAL(x) ((x) << STM32_UCPD_RXORDSETR_SHIFT) -#define STM32_UCPD_RXSOP3OF4 BIT(3) -#define STM32_UCPD_RXSOPKINVALID_SHIFT 4 -#define STM32_UCPD_RXSOPKINVALID_MASK ((0x7) << \ - (STM32_UCPD_RXSOPKINVALID_SHIFT)) -#define STM32_UCPD_RXSOPKINVALID_VAL(x) ((x) << \ - STM32_UCPD_RXSOPKINVALID_SHIFT) +#define STM32_UCPD_RXORDSETR_SHIFT 0 +#define STM32_UCPD_RXORDSETR_MASK ((0x7) << (STM32_UCPD_RXORDSETR_SHIFT)) +#define STM32_UCPD_RXORDSETR_VAL(x) ((x) << STM32_UCPD_RXORDSETR_SHIFT) +#define STM32_UCPD_RXSOP3OF4 BIT(3) +#define STM32_UCPD_RXSOPKINVALID_SHIFT 4 +#define STM32_UCPD_RXSOPKINVALID_MASK \ + ((0x7) << (STM32_UCPD_RXSOPKINVALID_SHIFT)) +#define STM32_UCPD_RXSOPKINVALID_VAL(x) ((x) << STM32_UCPD_RXSOPKINVALID_SHIFT) /* --- UCPD RX_PAYSZR Bit Definitions --- */ -#define STM32_UCPD_RX_PAYSZR_SHIFT 0 -#define STM32_UCPD_RX_PAYSZR_MASK ((0x3ff) << \ - (STM32_UCPD_RX_PAYSZR_SHIFT)) -#define STM32_UCPD_RX_PAYSZR_VAL(x) ((x) << STM32_UCPD_RX_PAYSZR_SHIFT) +#define STM32_UCPD_RX_PAYSZR_SHIFT 0 +#define STM32_UCPD_RX_PAYSZR_MASK ((0x3ff) << (STM32_UCPD_RX_PAYSZR_SHIFT)) +#define STM32_UCPD_RX_PAYSZR_VAL(x) ((x) << STM32_UCPD_RX_PAYSZR_SHIFT) /* --- UCPD TXDR Bit Definitions --- */ -#define STM32_UCPD_RXDR_SHIFT 0 -#define STM32_UCPD_RXDR_MASK ((0xff) << \ - (STM32_UCPD_RXDR_SHIFT)) -#define STM32_UCPD_RXDR_VAL(x) ((x) << STM32_UCPD_RXDR_SHIFT) - +#define STM32_UCPD_RXDR_SHIFT 0 +#define STM32_UCPD_RXDR_MASK ((0xff) << (STM32_UCPD_RXDR_SHIFT)) +#define STM32_UCPD_RXDR_VAL(x) ((x) << STM32_UCPD_RXDR_SHIFT) /* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_SR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) +#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) +#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) +#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) +#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) +#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) +#define STM32_USART_SR(base) STM32_USART_REG(base, 0x1C) +#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) +#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) /* --- USART bit definitions -- */ -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) - -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) - -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) - +#define STM32_USART_SR_ORE BIT(3) +#define STM32_USART_SR_RXNE BIT(5) +#define STM32_USART_SR_TC BIT(6) +#define STM32_USART_SR_TXE BIT(7) + +#define STM32_USART_CR1_UE BIT(0) +#define STM32_USART_CR1_RE BIT(2) +#define STM32_USART_CR1_TE BIT(3) +#define STM32_USART_CR1_RXNEIE BIT(5) +#define STM32_USART_CR1_TCIE BIT(6) +#define STM32_USART_CR1_TXEIE BIT(7) +#define STM32_USART_CR1_PS BIT(9) +#define STM32_USART_CR1_PCE BIT(10) +#define STM32_USART_CR1_M BIT(12) +#define STM32_USART_CR1_OVER8 BIT(15) + +#define STM32_USART_CR3_EIE BIT(0) +#define STM32_USART_CR3_DMAR BIT(6) +#define STM32_USART_CR3_DMAT BIT(7) +#define STM32_USART_CR3_ONEBIT BIT(11) /* --- GPIO --- */ -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) - -#define GPIO_ALT_SYS 0x0 -#define GPIO_ALT_TIM2 0x1 -#define GPIO_ALT_I2C3 0x2 -#define GPIO_ALT_TIM9_11 0x3 -#define GPIO_ALT_I2C 0x4 -#define GPIO_ALT_SPI 0x5 -#define GPIO_ALT_SPI3 0x6 -#define GPIO_ALT_USART 0x7 -#define GPIO_ALT_I2C_23 0x9 -#define GPIO_ALT_USB 0xA -#define GPIO_ALT_LCD 0xB -#define GPIO_ALT_LPUART 0xC -#define GPIO_ALT_SAI1 0xD -#define GPIO_ALT_RI 0xE -#define GPIO_ALT_EVENTOUT 0xF +#define STM32_GPIO_MODER(b) REG32((b) + 0x00) +#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) +#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) +#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) +#define STM32_GPIO_IDR(b) REG16((b) + 0x10) +#define STM32_GPIO_ODR(b) REG16((b) + 0x14) +#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) +#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) +#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) +#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) + +#define GPIO_ALT_SYS 0x0 +#define GPIO_ALT_TIM2 0x1 +#define GPIO_ALT_I2C3 0x2 +#define GPIO_ALT_TIM9_11 0x3 +#define GPIO_ALT_I2C 0x4 +#define GPIO_ALT_SPI 0x5 +#define GPIO_ALT_SPI3 0x6 +#define GPIO_ALT_USART 0x7 +#define GPIO_ALT_I2C_23 0x9 +#define GPIO_ALT_USB 0xA +#define GPIO_ALT_LCD 0xB +#define GPIO_ALT_LPUART 0xC +#define GPIO_ALT_SAI1 0xD +#define GPIO_ALT_RI 0xE +#define GPIO_ALT_EVENTOUT 0xF /* --- I2C --- */ #define stm32g4_i2c_reg(base, offset) ((uint16_t *)((base) + (offset))) -#define STM32_I2C_CR1(base) REG32(stm32g4_i2c_reg(base, 0x00)) -#define STM32_I2C_CR2(base) REG32(stm32g4_i2c_reg(base, 0x04)) -#define STM32_I2C_OAR1(base) REG16(stm32g4_i2c_reg(base, 0x08)) -#define STM32_I2C_OAR2(base) REG16(stm32g4_i2c_reg(base, 0x0C)) -#define STM32_I2C_TIMINGR(base) REG32(stm32g4_i2c_reg(base, 0x10)) -#define STM32_I2C_TIMEOUTR(base) REG32(stm32g4_i2c_reg(base, 0x14)) -#define STM32_I2C_ISR(base) REG32(stm32g4_i2c_reg(base, 0x18)) -#define STM32_I2C_ICR(base) REG32(stm32g4_i2c_reg(base, 0x1C)) -#define STM32_I2C_PECR(base) REG32(stm32g4_i2c_reg(base, 0x20)) -#define STM32_I2C_RXDR(base) REG32(stm32g4_i2c_reg(base, 0x24)) -#define STM32_I2C_TXDR(base) REG32(stm32g4_i2c_reg(base, 0x28)) +#define STM32_I2C_CR1(base) REG32(stm32g4_i2c_reg(base, 0x00)) +#define STM32_I2C_CR2(base) REG32(stm32g4_i2c_reg(base, 0x04)) +#define STM32_I2C_OAR1(base) REG16(stm32g4_i2c_reg(base, 0x08)) +#define STM32_I2C_OAR2(base) REG16(stm32g4_i2c_reg(base, 0x0C)) +#define STM32_I2C_TIMINGR(base) REG32(stm32g4_i2c_reg(base, 0x10)) +#define STM32_I2C_TIMEOUTR(base) REG32(stm32g4_i2c_reg(base, 0x14)) +#define STM32_I2C_ISR(base) REG32(stm32g4_i2c_reg(base, 0x18)) +#define STM32_I2C_ICR(base) REG32(stm32g4_i2c_reg(base, 0x1C)) +#define STM32_I2C_PECR(base) REG32(stm32g4_i2c_reg(base, 0x20)) +#define STM32_I2C_RXDR(base) REG32(stm32g4_i2c_reg(base, 0x24)) +#define STM32_I2C_TXDR(base) REG32(stm32g4_i2c_reg(base, 0x28)) /* --- I2C CR1 Bit Definitions --- */ -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_TXIE BIT(1) -#define STM32_I2C_CR1_RXIE BIT(2) -#define STM32_I2C_CR1_ADDRIE BIT(3) -#define STM32_I2C_CR1_NACKIE BIT(4) -#define STM32_I2C_CR1_STOPIE BIT(5) -#define STM32_I2C_CR1_ERRIE BIT(7) -#define STM32_I2C_CR1_WUPEN BIT(18) +#define STM32_I2C_CR1_PE BIT(0) +#define STM32_I2C_CR1_TXIE BIT(1) +#define STM32_I2C_CR1_RXIE BIT(2) +#define STM32_I2C_CR1_ADDRIE BIT(3) +#define STM32_I2C_CR1_NACKIE BIT(4) +#define STM32_I2C_CR1_STOPIE BIT(5) +#define STM32_I2C_CR1_ERRIE BIT(7) +#define STM32_I2C_CR1_WUPEN BIT(18) /* --- I2C CR2 Bit Definitions --- */ -#define STM32_I2C_CR2_RD_WRN BIT(10) -#define STM32_I2C_CR2_START BIT(13) -#define STM32_I2C_CR2_STOP BIT(14) -#define STM32_I2C_CR2_NACK BIT(15) -#define STM32_I2C_CR2_RELOAD BIT(24) -#define STM32_I2C_CR2_AUTOEND BIT(25) +#define STM32_I2C_CR2_RD_WRN BIT(10) +#define STM32_I2C_CR2_START BIT(13) +#define STM32_I2C_CR2_STOP BIT(14) +#define STM32_I2C_CR2_NACK BIT(15) +#define STM32_I2C_CR2_RELOAD BIT(24) +#define STM32_I2C_CR2_AUTOEND BIT(25) /* --- I2C ISR Bit Definitions --- */ -#define STM32_I2C_ISR_TXE BIT(0) -#define STM32_I2C_ISR_TXIS BIT(1) -#define STM32_I2C_ISR_RXNE BIT(2) -#define STM32_I2C_ISR_ADDR BIT(3) -#define STM32_I2C_ISR_NACK BIT(4) -#define STM32_I2C_ISR_STOP BIT(5) -#define STM32_I2C_ISR_TC BIT(6) -#define STM32_I2C_ISR_TCR BIT(7) -#define STM32_I2C_ISR_BERR BIT(8) -#define STM32_I2C_ISR_ARLO BIT(9) -#define STM32_I2C_ISR_OVR BIT(10) -#define STM32_I2C_ISR_PECERR BIT(11) -#define STM32_I2C_ISR_TIMEOUT BIT(12) -#define STM32_I2C_ISR_ALERT BIT(13) -#define STM32_I2C_ISR_BUSY BIT(15) -#define STM32_I2C_ISR_DIR BIT(16) +#define STM32_I2C_ISR_TXE BIT(0) +#define STM32_I2C_ISR_TXIS BIT(1) +#define STM32_I2C_ISR_RXNE BIT(2) +#define STM32_I2C_ISR_ADDR BIT(3) +#define STM32_I2C_ISR_NACK BIT(4) +#define STM32_I2C_ISR_STOP BIT(5) +#define STM32_I2C_ISR_TC BIT(6) +#define STM32_I2C_ISR_TCR BIT(7) +#define STM32_I2C_ISR_BERR BIT(8) +#define STM32_I2C_ISR_ARLO BIT(9) +#define STM32_I2C_ISR_OVR BIT(10) +#define STM32_I2C_ISR_PECERR BIT(11) +#define STM32_I2C_ISR_TIMEOUT BIT(12) +#define STM32_I2C_ISR_ALERT BIT(13) +#define STM32_I2C_ISR_BUSY BIT(15) +#define STM32_I2C_ISR_DIR BIT(16) /* --- I2C ICR Bit Definitions --- */ -#define STM32_I2C_ICR_ADDRCF BIT(3) -#define STM32_I2C_ICR_NACKCF BIT(4) -#define STM32_I2C_ICR_STOPCF BIT(5) -#define STM32_I2C_ICR_BERRCF BIT(8) -#define STM32_I2C_ICR_ARLOCF BIT(9) -#define STM32_I2C_ICR_OVRCF BIT(10) -#define STM32_I2C_ICR_TIMEOUTCF BIT(12) -#define STM32_I2C_ICR_ALL 0x3F38 +#define STM32_I2C_ICR_ADDRCF BIT(3) +#define STM32_I2C_ICR_NACKCF BIT(4) +#define STM32_I2C_ICR_STOPCF BIT(5) +#define STM32_I2C_ICR_BERRCF BIT(8) +#define STM32_I2C_ICR_ARLOCF BIT(9) +#define STM32_I2C_ICR_OVRCF BIT(10) +#define STM32_I2C_ICR_TIMEOUTCF BIT(12) +#define STM32_I2C_ICR_ALL 0x3F38 /* --- I2C TIMINGR bit Definitions --- */ #define STM32_I2C_TIMINGR_SCLL_OFF 0 @@ -579,277 +559,271 @@ /* --- Power / Reset / Clocks --- */ -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x0C) -#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x18) -#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x1C) -#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x28) -#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x2C) -#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_APB1RSTR1 REG32(STM32_RCC_BASE + 0x38) -#define STM32_RCC_APB1RSTR2 REG32(STM32_RCC_BASE + 0x3C) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x40) -#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x48) -#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x4C) -#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x50) -#define STM32_RCC_APB1ENR1 REG32(STM32_RCC_BASE + 0x58) -#define STM32_RCC_APB1ENR2 REG32(STM32_RCC_BASE + 0x5C) -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60) -#define STM32_RCC_AHB1SMENR REG32(STM32_RCC_BASE + 0x68) -#define STM32_RCC_AHB2SMENR REG32(STM32_RCC_BASE + 0x6C) -#define STM32_RCC_AHB3SMENR REG32(STM32_RCC_BASE + 0x70) -#define STM32_RCC_APB1SMENR1 REG32(STM32_RCC_BASE + 0x78) -#define STM32_RCC_APB1SMENR2 REG32(STM32_RCC_BASE + 0x7C) -#define STM32_RCC_APB2SMENR REG32(STM32_RCC_BASE + 0x80) -#define STM32_RCC_CCIPR REG32(STM32_RCC_BASE + 0x88) -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x94) -#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98) -#define STM32_RCC_CCIPR2 REG32(STM32_RCC_BASE + 0x9C) +#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) +#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) +#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) +#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x0C) +#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x18) +#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x1C) +#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x20) +#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x28) +#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x2C) +#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x30) +#define STM32_RCC_APB1RSTR1 REG32(STM32_RCC_BASE + 0x38) +#define STM32_RCC_APB1RSTR2 REG32(STM32_RCC_BASE + 0x3C) +#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x40) +#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x48) +#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x4C) +#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x50) +#define STM32_RCC_APB1ENR1 REG32(STM32_RCC_BASE + 0x58) +#define STM32_RCC_APB1ENR2 REG32(STM32_RCC_BASE + 0x5C) +#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60) +#define STM32_RCC_AHB1SMENR REG32(STM32_RCC_BASE + 0x68) +#define STM32_RCC_AHB2SMENR REG32(STM32_RCC_BASE + 0x6C) +#define STM32_RCC_AHB3SMENR REG32(STM32_RCC_BASE + 0x70) +#define STM32_RCC_APB1SMENR1 REG32(STM32_RCC_BASE + 0x78) +#define STM32_RCC_APB1SMENR2 REG32(STM32_RCC_BASE + 0x7C) +#define STM32_RCC_APB2SMENR REG32(STM32_RCC_BASE + 0x80) +#define STM32_RCC_CCIPR REG32(STM32_RCC_BASE + 0x88) +#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90) +#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x94) +#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98) +#define STM32_RCC_CCIPR2 REG32(STM32_RCC_BASE + 0x9C) #define STM32_RCC_APB1ENR STM32_RCC_APB1ENR1 #define STM32_RCC_AHBENR STM32_RCC_APB1ENR /* --- RCC CR Bit Definitions --- */ -#define STM32_RCC_CR_HSION BIT(8) -#define STM32_RCC_CR_HSIRDY BIT(10) -#define STM32_RCC_CR_HSEON BIT(16) -#define STM32_RCC_CR_HSERDY BIT(17) -#define STM32_RCC_CR_PLLON BIT(24) -#define STM32_RCC_CR_PLLRDY BIT(25) +#define STM32_RCC_CR_HSION BIT(8) +#define STM32_RCC_CR_HSIRDY BIT(10) +#define STM32_RCC_CR_HSEON BIT(16) +#define STM32_RCC_CR_HSERDY BIT(17) +#define STM32_RCC_CR_PLLON BIT(24) +#define STM32_RCC_CR_PLLRDY BIT(25) /* --- RCC PLLCFGR Bit Definitions --- */ -#define PLLCFGR_PLLSRC_OFF 0 -#define PLLCFGR_PLLSRC(val) (((val) & 0x3) << PLLCFGR_PLLSRC_OFF) -#define PLLCFGR_PLLSRC_HSI 2 -#define PLLCFGR_PLLSRC_HSE 3 +#define PLLCFGR_PLLSRC_OFF 0 +#define PLLCFGR_PLLSRC(val) (((val)&0x3) << PLLCFGR_PLLSRC_OFF) +#define PLLCFGR_PLLSRC_HSI 2 +#define PLLCFGR_PLLSRC_HSE 3 /* PLL Division factor */ -#define PLLCFGR_PLLM_OFF 4 -#define PLLCFGR_PLLM(val) (((val) & 0x1f) << PLLCFGR_PLLM_OFF) +#define PLLCFGR_PLLM_OFF 4 +#define PLLCFGR_PLLM(val) (((val)&0x1f) << PLLCFGR_PLLM_OFF) /* PLL Multiplication factor */ -#define PLLCFGR_PLLN_OFF 8 -#define PLLCFGR_PLLN(val) (((val) & 0x7f) << PLLCFGR_PLLN_OFF) -#define PLLCFGR_PLLQ_EN BIT(20) -#define PLLCFGR_PLLQ_OFF 21 -#define PLLCFGR_PLLQ(val) (((val) & 0x3) << PLLCFGR_PLLQ_OFF) +#define PLLCFGR_PLLN_OFF 8 +#define PLLCFGR_PLLN(val) (((val)&0x7f) << PLLCFGR_PLLN_OFF) +#define PLLCFGR_PLLQ_EN BIT(20) +#define PLLCFGR_PLLQ_OFF 21 +#define PLLCFGR_PLLQ(val) (((val)&0x3) << PLLCFGR_PLLQ_OFF) /* System and main CPU clock */ -#define PLLCFGR_PLLR_EN BIT(24) -#define PLLCFGR_PLLR_OFF 25 -#define PLLCFGR_PLLR(val) (((val) & 0x3) << PLLCFGR_PLLR_OFF) -#define PLLCFGR_PLLP_OFF 27 -#define PLLCFGR_PLLP(val) (((val) & 0x1f) << PLLCFGR_PLLP_OFF) +#define PLLCFGR_PLLR_EN BIT(24) +#define PLLCFGR_PLLR_OFF 25 +#define PLLCFGR_PLLR(val) (((val)&0x3) << PLLCFGR_PLLR_OFF) +#define PLLCFGR_PLLP_OFF 27 +#define PLLCFGR_PLLP(val) (((val)&0x1f) << PLLCFGR_PLLP_OFF) /* --- RCC CFGR Bit Definitions --- */ -#define STM32_RCC_CFGR_SW_HSI (1 << 0) -#define STM32_RCC_CFGR_SW_HSE (2 << 0) -#define STM32_RCC_CFGR_SW_PLL (3 << 0) -#define STM32_RCC_CFGR_SW_MASK (3 << 0) -#define STM32_RCC_CFGR_SWS_HSI (1 << 2) -#define STM32_RCC_CFGR_SWS_HSE (2 << 2) -#define STM32_RCC_CFGR_SWS_PLL (3 << 2) -#define STM32_RCC_CFGR_SWS_MASK (3 << 2) +#define STM32_RCC_CFGR_SW_HSI (1 << 0) +#define STM32_RCC_CFGR_SW_HSE (2 << 0) +#define STM32_RCC_CFGR_SW_PLL (3 << 0) +#define STM32_RCC_CFGR_SW_MASK (3 << 0) +#define STM32_RCC_CFGR_SWS_HSI (1 << 2) +#define STM32_RCC_CFGR_SWS_HSE (2 << 2) +#define STM32_RCC_CFGR_SWS_PLL (3 << 2) +#define STM32_RCC_CFGR_SWS_MASK (3 << 2) /* AHB Prescalar: */ -#define CFGR_HPRE_OFF 4 -#define CFGR_HPRE(val) (((val) & 0xf) << CFGR_HPRE_OFF) +#define CFGR_HPRE_OFF 4 +#define CFGR_HPRE(val) (((val)&0xf) << CFGR_HPRE_OFF) /* APB1 Low Speed Prescalar < 45MHz */ -#define CFGR_PPRE1_OFF 8 -#define CFGR_PPRE1(val) (((val) & 0x7) << CFGR_PPRE1_OFF) +#define CFGR_PPRE1_OFF 8 +#define CFGR_PPRE1(val) (((val)&0x7) << CFGR_PPRE1_OFF) /* APB2 High Speed Prescalar < 90MHz */ -#define CFGR_PPRE2_OFF 11 -#define CFGR_PPRE2(val) (((val) & 0x7) << CFGR_PPRE2_OFF) +#define CFGR_PPRE2_OFF 11 +#define CFGR_PPRE2(val) (((val)&0x7) << CFGR_PPRE2_OFF) /* RTC CLock: Must equal 1MHz */ -#define CFGR_RTCPRE_OFF 16 -#define CFGR_RTCPRE(val) (((val) & 0x1f) << CFGR_RTCPRE_OFF) +#define CFGR_RTCPRE_OFF 16 +#define CFGR_RTCPRE(val) (((val)&0x1f) << CFGR_RTCPRE_OFF) /* --- RCC AHB1ENR Bit Definitions --- */ -#define STM32_RCC_AHB1ENR_DMA1EN BIT(0) -#define STM32_RCC_AHB1ENR_DMA2EN BIT(1) -#define STM32_RCC_AHB1ENR_DMAMUXEN BIT(2) +#define STM32_RCC_AHB1ENR_DMA1EN BIT(0) +#define STM32_RCC_AHB1ENR_DMA2EN BIT(1) +#define STM32_RCC_AHB1ENR_DMAMUXEN BIT(2) /* --- RCC AHB2ENR Bit Definitions --- */ -#define STM32_RCC_AHB2ENR_GPIO_PORTA BIT(0) -#define STM32_RCC_AHB2ENR_GPIO_PORTB BIT(1) -#define STM32_RCC_AHB2ENR_GPIO_PORTC BIT(2) -#define STM32_RCC_AHB2ENR_GPIO_PORTD BIT(3) -#define STM32_RCC_AHB2ENR_GPIO_PORTE BIT(4) -#define STM32_RCC_AHB2ENR_GPIO_PORTF BIT(5) -#define STM32_RCC_AHB2ENR_GPIO_PORTG BIT(6) -#define STM32_RCC_AHB2ENR_GPIOMASK (0x7f << 0) -#define STM32_RCC_AHB2ENR_ADC12EN BIT(13) -#define STM32_RCC_APB2ENR_ADC345EN BIT(14) -#define STM32_RCC_AHB2ENR_RNGEN BIT(26) +#define STM32_RCC_AHB2ENR_GPIO_PORTA BIT(0) +#define STM32_RCC_AHB2ENR_GPIO_PORTB BIT(1) +#define STM32_RCC_AHB2ENR_GPIO_PORTC BIT(2) +#define STM32_RCC_AHB2ENR_GPIO_PORTD BIT(3) +#define STM32_RCC_AHB2ENR_GPIO_PORTE BIT(4) +#define STM32_RCC_AHB2ENR_GPIO_PORTF BIT(5) +#define STM32_RCC_AHB2ENR_GPIO_PORTG BIT(6) +#define STM32_RCC_AHB2ENR_GPIOMASK (0x7f << 0) +#define STM32_RCC_AHB2ENR_ADC12EN BIT(13) +#define STM32_RCC_APB2ENR_ADC345EN BIT(14) +#define STM32_RCC_AHB2ENR_RNGEN BIT(26) /* --- RCC APB1ENR1 Bit Definitions --- */ -#define STM32_RCC_APB1ENR1_TIM2EN BIT(0) -#define STM32_RCC_APB1ENR1_TIM3EN BIT(1) -#define STM32_RCC_APB1ENR1_TIM4EN BIT(2) -#define STM32_RCC_APB1ENR1_TIM5EN BIT(3) -#define STM32_RCC_APB1ENR1_TIM6EN BIT(4) -#define STM32_RCC_APB1ENR1_TIM7EN BIT(5) -#define STM32_RCC_APB1ENR1_WWDGEN BIT(11) -#define STM32_RCC_APB1ENR1_USART2 BIT(17) -#define STM32_RCC_APB1ENR1_USART3 BIT(18) -#define STM32_RCC_APB1ENR1_UART4 BIT(19) -#define STM32_RCC_APB1ENR1_UART5 BIT(20) -#define STM32_RCC_APB1ENR1_I2C1EN BIT(21) -#define STM32_RCC_APB1ENR1_I2C2EN BIT(22) -#define STM32_RCC_APB1ENR1_USBEN BIT(23) -#define STM32_RCC_APB1ENR1_PWREN BIT(28) -#define STM32_RCC_APB1ENR1_I2C3EN BIT(30) +#define STM32_RCC_APB1ENR1_TIM2EN BIT(0) +#define STM32_RCC_APB1ENR1_TIM3EN BIT(1) +#define STM32_RCC_APB1ENR1_TIM4EN BIT(2) +#define STM32_RCC_APB1ENR1_TIM5EN BIT(3) +#define STM32_RCC_APB1ENR1_TIM6EN BIT(4) +#define STM32_RCC_APB1ENR1_TIM7EN BIT(5) +#define STM32_RCC_APB1ENR1_WWDGEN BIT(11) +#define STM32_RCC_APB1ENR1_USART2 BIT(17) +#define STM32_RCC_APB1ENR1_USART3 BIT(18) +#define STM32_RCC_APB1ENR1_UART4 BIT(19) +#define STM32_RCC_APB1ENR1_UART5 BIT(20) +#define STM32_RCC_APB1ENR1_I2C1EN BIT(21) +#define STM32_RCC_APB1ENR1_I2C2EN BIT(22) +#define STM32_RCC_APB1ENR1_USBEN BIT(23) +#define STM32_RCC_APB1ENR1_PWREN BIT(28) +#define STM32_RCC_APB1ENR1_I2C3EN BIT(30) #define STM32_RCC_PWREN STM32_RCC_APB1ENR1_PWREN /* --- RCC APB1ENR2 Bit Definitions --- */ -#define STM32_RCC_APB1ENR2_LPUART1EN BIT(0) -#define STM32_RCC_APB1ENR2_I2C4EN BIT(1) -#define STM32_RCC_APB1ENR2_UPCD1EN BIT(8) +#define STM32_RCC_APB1ENR2_LPUART1EN BIT(0) +#define STM32_RCC_APB1ENR2_I2C4EN BIT(1) +#define STM32_RCC_APB1ENR2_UPCD1EN BIT(8) /* --- RCC APB2ENR Bit Definitions --- */ -#define STM32_RCC_APB2ENR_SYSCFGEN BIT(0) -#define STM32_RCC_APB2ENR_TIM1 BIT(11) -#define STM32_RCC_APB2ENR_SPI1EN BIT(12) -#define STM32_RCC_APB2ENR_TIM8 BIT(13) -#define STM32_RCC_APB2ENR_USART1 BIT(14) -#define STM32_RCC_APB2ENR_SPI4EN BIT(15) -#define STM32_RCC_APB2ENR_TIM15 BIT(16) -#define STM32_RCC_APB2ENR_TIM16 BIT(17) -#define STM32_RCC_APB2ENR_TIM17 BIT(18) -#define STM32_RCC_APB2ENR_TIM20 BIT(20) - -#define STM32_RCC_PB2_USART1 STM32_RCC_APB2ENR_USART1 +#define STM32_RCC_APB2ENR_SYSCFGEN BIT(0) +#define STM32_RCC_APB2ENR_TIM1 BIT(11) +#define STM32_RCC_APB2ENR_SPI1EN BIT(12) +#define STM32_RCC_APB2ENR_TIM8 BIT(13) +#define STM32_RCC_APB2ENR_USART1 BIT(14) +#define STM32_RCC_APB2ENR_SPI4EN BIT(15) +#define STM32_RCC_APB2ENR_TIM15 BIT(16) +#define STM32_RCC_APB2ENR_TIM16 BIT(17) +#define STM32_RCC_APB2ENR_TIM17 BIT(18) +#define STM32_RCC_APB2ENR_TIM20 BIT(20) + +#define STM32_RCC_PB2_USART1 STM32_RCC_APB2ENR_USART1 /* gpio.c needs STM32_RCC_SYSCFGEN */ #define STM32_RCC_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN /* --- RCC APB1RSTR1 Bit Definitions --- */ -#define STM32_RCC_APB1RSTR1_USB_RST BIT(23) -#define STM32_RCC_APB1RSTR STM32_RCC_APB1RSTR1 -#define STM32_RCC_PB1_USB STM32_RCC_APB1RSTR1_USB_RST +#define STM32_RCC_APB1RSTR1_USB_RST BIT(23) +#define STM32_RCC_APB1RSTR STM32_RCC_APB1RSTR1 +#define STM32_RCC_PB1_USB STM32_RCC_APB1RSTR1_USB_RST /* --- RCC CSR Bit Definitions --- */ -#define STM32_RCC_CSR_LSION BIT(0) -#define STM32_RCC_CSR_LSIRDY BIT(1) +#define STM32_RCC_CSR_LSION BIT(0) +#define STM32_RCC_CSR_LSIRDY BIT(1) /* --- RCC CCIPR Bit Definitions --- */ -#define STM32_RCC_CCIPR_UART_SYSCLK 0x1 -#define STM32_RCC_CCIPR_USART1SEL_MASK 0x3 -#define STM32_RCC_CCIPR_USART1SEL_SHIFT 0 -#define STM32_RCC_CCIPR_LPUART1SEL_MASK 0x3 +#define STM32_RCC_CCIPR_UART_SYSCLK 0x1 +#define STM32_RCC_CCIPR_USART1SEL_MASK 0x3 +#define STM32_RCC_CCIPR_USART1SEL_SHIFT 0 +#define STM32_RCC_CCIPR_LPUART1SEL_MASK 0x3 #define STM32_RCC_CCIPR_LPUART1SEL_SHIFT 10 -#define STM32_RCC_CCIPR_I2C1SEL_MASK 0x3 -#define STM32_RCC_CCIPR_I2C1SEL_SHIFT 12 -#define STM32_RCC_CCIPR_I2C2SEL_MASK 0x3 -#define STM32_RCC_CCIPR_I2C2SEL_SHIFT 14 -#define STM32_RCC_CCIPR_I2C3SEL_MASK 0x3 -#define STM32_RCC_CCIPR_I2C3SEL_SHIFT 16 +#define STM32_RCC_CCIPR_I2C1SEL_MASK 0x3 +#define STM32_RCC_CCIPR_I2C1SEL_SHIFT 12 +#define STM32_RCC_CCIPR_I2C2SEL_MASK 0x3 +#define STM32_RCC_CCIPR_I2C2SEL_SHIFT 14 +#define STM32_RCC_CCIPR_I2C3SEL_MASK 0x3 +#define STM32_RCC_CCIPR_I2C3SEL_SHIFT 16 -#define STM32_RCC_CCIPR2_I2C4SEL_MASK 0x3 +#define STM32_RCC_CCIPR2_I2C4SEL_MASK 0x3 -#define STM32_RCC_CCIPR_I2CNSEL_MASK 0x3 +#define STM32_RCC_CCIPR_I2CNSEL_MASK 0x3 #define STM32_RCC_CCIPR_I2CNSEL_SHIFT(n) (STM32_RCC_CCIPR_I2C1SEL_SHIFT + n * 2) -#define STM32_RCC_CCIPR_I2CNSEL_HSI 0x2 +#define STM32_RCC_CCIPR_I2CNSEL_HSI 0x2 /* --- RCC CRRCR Bit Definitions */ -#define RCC_CRRCR_HSI48O BIT(0) -#define RCC_CRRCR_HSIRDY BIT(1) +#define RCC_CRRCR_HSI48O BIT(0) +#define RCC_CRRCR_HSIRDY BIT(1) /* Reset causes definitions */ /* * Reset causes in RCC CSR register. The generic names are required */ #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define STM32_RCC_CSR_RMVF BIT(24) -#define STM32_RCC_CSR_BORRS BIT(25) -#define STM32_RCC_CSR_PIN BIT(26) -#define STM32_RCC_CSR_POR BIT(27) -#define STM32_RCC_CSR_SFT BIT(28) -#define STM32_RCC_CSR_IWDG BIT(29) -#define STM32_RCC_CSR_WWDG BIT(30) -#define STM32_RCC_CSR_LPWR BIT(31) - - -#define RESET_CAUSE_WDG (STM32_RCC_CSR_WWDG | \ - STM32_RCC_CSR_IWDG) -#define RESET_CAUSE_SFT STM32_RCC_CSR_SFT -#define RESET_CAUSE_POR STM32_RCC_CSR_POR -#define RESET_CAUSE_PIN STM32_RCC_CSR_PIN -#define RESET_CAUSE_RMVF STM32_RCC_CSR_RMVF -#define RESET_CAUSE_OTHER (STM32_RCC_CSR_LPWR | \ - STM32_RCC_CSR_BORRS) +#define STM32_RCC_CSR_RMVF BIT(24) +#define STM32_RCC_CSR_BORRS BIT(25) +#define STM32_RCC_CSR_PIN BIT(26) +#define STM32_RCC_CSR_POR BIT(27) +#define STM32_RCC_CSR_SFT BIT(28) +#define STM32_RCC_CSR_IWDG BIT(29) +#define STM32_RCC_CSR_WWDG BIT(30) +#define STM32_RCC_CSR_LPWR BIT(31) + +#define RESET_CAUSE_WDG (STM32_RCC_CSR_WWDG | STM32_RCC_CSR_IWDG) +#define RESET_CAUSE_SFT STM32_RCC_CSR_SFT +#define RESET_CAUSE_POR STM32_RCC_CSR_POR +#define RESET_CAUSE_PIN STM32_RCC_CSR_PIN +#define RESET_CAUSE_RMVF STM32_RCC_CSR_RMVF +#define RESET_CAUSE_OTHER (STM32_RCC_CSR_LPWR | STM32_RCC_CSR_BORRS) /* Power cause in PWR CSR register */ -#define STM32_PWR_CR1 REG32(STM32_PWR_BASE + 0x00) -#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x04) -#define STM32_PWR_CR3 REG32(STM32_PWR_BASE + 0x08) -#define STM32_PWR_CR4 REG32(STM32_PWR_BASE + 0x0C) -#define STM32_PWR_SR1 REG32(STM32_PWR_BASE + 0x10) -#define STM32_PWR_SR2 REG32(STM32_PWR_BASE + 0x14) -#define STM32_PWR_SCR REG32(STM32_PWR_BASE + 0x18) -#define STM32_PWR_SCR_CSBF BIT(8) -#define STM32_PWR_SR1_SBF BIT(8) +#define STM32_PWR_CR1 REG32(STM32_PWR_BASE + 0x00) +#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x04) +#define STM32_PWR_CR3 REG32(STM32_PWR_BASE + 0x08) +#define STM32_PWR_CR4 REG32(STM32_PWR_BASE + 0x0C) +#define STM32_PWR_SR1 REG32(STM32_PWR_BASE + 0x10) +#define STM32_PWR_SR2 REG32(STM32_PWR_BASE + 0x14) +#define STM32_PWR_SCR REG32(STM32_PWR_BASE + 0x18) +#define STM32_PWR_SCR_CSBF BIT(8) +#define STM32_PWR_SR1_SBF BIT(8) #define STM32_PWR_RESET_CAUSE STM32_PWR_SR1 -#define RESET_CAUSE_SBF STM32_PWR_SR1_SBF +#define RESET_CAUSE_SBF STM32_PWR_SR1_SBF #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_SCR -#define RESET_CAUSE_SBF_CLR STM32_PWR_SCR_CSBF +#define RESET_CAUSE_SBF_CLR STM32_PWR_SCR_CSBF -#define STM32_PWR_CR1_DBP BIT(8) +#define STM32_PWR_CR1_DBP BIT(8) -#define STM32_PWR_CR3_UCPD1_STDBY BIT(13) -#define STM32_PWR_CR3_UCPD1_DBDIS BIT(14) +#define STM32_PWR_CR3_UCPD1_STDBY BIT(13) +#define STM32_PWR_CR3_UCPD1_DBDIS BIT(14) /* --- System Config Registers --- */ -#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00) -#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) -#define STM32_SYSCFG_CMPCR REG32(STM32_SYSCFG_BASE + 0x20) -#define STM32_SYSCFG_CFGR REG32(STM32_SYSCFG_BASE + 0x2C) +#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00) +#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04) +#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) +#define STM32_SYSCFG_CMPCR REG32(STM32_SYSCFG_BASE + 0x20) +#define STM32_SYSCFG_CFGR REG32(STM32_SYSCFG_BASE + 0x2C) /* --- Watchdogs --- */ /* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x18) - - -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_CALR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_SHIFTR REG32(STM32_RTC_BASE + 0x2C) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TSSSR REG32(STM32_RTC_BASE + 0x38) - -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x48) -#define STM32_RTC_ALRMBSSR REG32(STM32_RTC_BASE + 0x44) +#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) +#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) +#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x08) +#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) +#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) +#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) +#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x18) + +#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) +#define STM32_RTC_CALR REG32(STM32_RTC_BASE + 0x28) +#define STM32_RTC_SHIFTR REG32(STM32_RTC_BASE + 0x2C) +#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) +#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) +#define STM32_RTC_TSSSR REG32(STM32_RTC_BASE + 0x38) + +#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x40) +#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) +#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x48) +#define STM32_RTC_ALRMBSSR REG32(STM32_RTC_BASE + 0x44) /* --- RTC CR Bit Definitions --- */ -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) +#define STM32_RTC_CR_BYPSHAD BIT(5) +#define STM32_RTC_CR_ALRAE BIT(8) +#define STM32_RTC_CR_ALRAIE BIT(12) /* --- RTC ICSR Bit Definitions --- */ -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) +#define STM32_RTC_ISR_ALRAWF BIT(0) +#define STM32_RTC_ISR_RSF BIT(5) +#define STM32_RTC_ISR_INITF BIT(6) +#define STM32_RTC_ISR_INIT BIT(7) +#define STM32_RTC_ISR_ALRAF BIT(8) /* --- RTC PRER Bit Definitions --- */ -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) - +#define STM32_RTC_PRER_A_MASK (0x7f << 16) +#define STM32_RTC_PRER_S_MASK (0x7fff << 0) /* --- Tamper and Backup --- */ -#define STM32_TAMP_BKPxR(n) REG32(STM32_TAMP_BASE + 0x100 + 4 * (n)) -#define STM32_BKP_DATA(n) STM32_TAMP_BKPxR(n) -#define STM32_BKP_BYTES 64 - +#define STM32_TAMP_BKPxR(n) REG32(STM32_TAMP_BASE + 0x100 + 4 * (n)) +#define STM32_BKP_DATA(n) STM32_TAMP_BKPxR(n) +#define STM32_BKP_BYTES 64 /* --- SPI --- */ @@ -877,223 +851,222 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) +#define STM32_SPI_CR1_BIDIMODE BIT(15) +#define STM32_SPI_CR1_BIDIOE BIT(14) +#define STM32_SPI_CR1_CRCEN BIT(13) +#define STM32_SPI_CR1_SSM BIT(9) +#define STM32_SPI_CR1_SSI BIT(8) +#define STM32_SPI_CR1_LSBFIRST BIT(7) +#define STM32_SPI_CR1_SPE BIT(6) +#define STM32_SPI_CR1_BR_DIV64R (5 << 3) +#define STM32_SPI_CR1_BR_DIV4R BIT(3) +#define STM32_SPI_CR1_MSTR BIT(2) +#define STM32_SPI_CR1_CPOL BIT(1) +#define STM32_SPI_CR1_CPHA BIT(0) +#define STM32_SPI_CR2_FRXTH BIT(12) +#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8) +#define STM32_SPI_CR2_TXEIE BIT(7) +#define STM32_SPI_CR2_RXNEIE BIT(6) +#define STM32_SPI_CR2_NSSP BIT(3) +#define STM32_SPI_CR2_SSOE BIT(2) +#define STM32_SPI_CR2_TXDMAEN BIT(1) +#define STM32_SPI_CR2_RXDMAEN BIT(0) + +#define STM32_SPI_SR_RXNE BIT(0) +#define STM32_SPI_SR_TXE BIT(1) +#define STM32_SPI_SR_CRCERR BIT(4) +#define STM32_SPI_SR_BSY BIT(7) +#define STM32_SPI_SR_FRLVL (3 << 9) +#define STM32_SPI_SR_FTLVL (3 << 11) /* --- Debug --- */ -#define STM32_DBGMCU_IDCODE REG32(STM32_DBGMCU_BASE + 0x00) -#define STM32_DBGMCU_CR REG32(STM32_DBGMCU_BASE + 0x04) -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) +#define STM32_DBGMCU_IDCODE REG32(STM32_DBGMCU_BASE + 0x00) +#define STM32_DBGMCU_CR REG32(STM32_DBGMCU_BASE + 0x04) +#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) +#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) /* --- DBGMCU CR Bit Definitions --- */ -#define STM32_DBGMCU_CR_SLEEP BIT(0) -#define STM32_DBGMCU_CR_STOP BIT(1) -#define STM32_DBGMCU_CR_STBY BIT(2) -#define STM32_DBGMCU_CR_TRACE_MASK (BIT(5)|BIT(6)|BIT(7)) -#define STM32_DBGMCU_CR_TRACE_EN BIT(5) -#define STM32_DBGMCU_CR_TRACE_MODE_ASYNC 0 -#define STM32_DBGMCU_CR_TRACE_MODE_SYNC1 BIT(6) -#define STM32_DBGMCU_CR_TRACE_MODE_SYNC2 BIT(7) -#define STM32_DBGMCU_CR_TRACE_MODE_SYNC4 (BIT(6)|BIT(7)) +#define STM32_DBGMCU_CR_SLEEP BIT(0) +#define STM32_DBGMCU_CR_STOP BIT(1) +#define STM32_DBGMCU_CR_STBY BIT(2) +#define STM32_DBGMCU_CR_TRACE_MASK (BIT(5) | BIT(6) | BIT(7)) +#define STM32_DBGMCU_CR_TRACE_EN BIT(5) +#define STM32_DBGMCU_CR_TRACE_MODE_ASYNC 0 +#define STM32_DBGMCU_CR_TRACE_MODE_SYNC1 BIT(6) +#define STM32_DBGMCU_CR_TRACE_MODE_SYNC2 BIT(7) +#define STM32_DBGMCU_CR_TRACE_MODE_SYNC4 (BIT(6) | BIT(7)) /* --- DBGMCU APB1FZ Bit Definitions --- */ -#define STM32_DBGMCU_APB1FZ_TIM2 BIT(0) -#define STM32_DBGMCU_APB1FZ_TIM3 BIT(1) -#define STM32_DBGMCU_APB1FZ_TIM4 BIT(2) -#define STM32_DBGMCU_APB1FZ_TIM5 BIT(3) -#define STM32_DBGMCU_APB1FZ_TIM6 BIT(4) -#define STM32_DBGMCU_APB1FZ_TIM7 BIT(5) -#define STM32_DBGMCU_APB1FZ_RTC BIT(10) -#define STM32_DBGMCU_APB1FZ_WWDG BIT(11) -#define STM32_DBGMCU_APB1FZ_IWDG BIT(12) -#define STM32_DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT BIT(21) -#define STM32_DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT BIT(22) -#define STM32_DBGMCU_APB1FZ_I2C3_SMBUS_TIMEOUT BIT(30) +#define STM32_DBGMCU_APB1FZ_TIM2 BIT(0) +#define STM32_DBGMCU_APB1FZ_TIM3 BIT(1) +#define STM32_DBGMCU_APB1FZ_TIM4 BIT(2) +#define STM32_DBGMCU_APB1FZ_TIM5 BIT(3) +#define STM32_DBGMCU_APB1FZ_TIM6 BIT(4) +#define STM32_DBGMCU_APB1FZ_TIM7 BIT(5) +#define STM32_DBGMCU_APB1FZ_RTC BIT(10) +#define STM32_DBGMCU_APB1FZ_WWDG BIT(11) +#define STM32_DBGMCU_APB1FZ_IWDG BIT(12) +#define STM32_DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT BIT(21) +#define STM32_DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT BIT(22) +#define STM32_DBGMCU_APB1FZ_I2C3_SMBUS_TIMEOUT BIT(30) /* --- DBGMCU APB2FZ Bit Definitions --- */ -#define STM32_DBGMCU_APB2FZ_TIM1 BIT(11) -#define STM32_DBGMCU_APB2FZ_TIM8 BIT(13) -#define STM32_DBGMCU_APB2FZ_TIM15 BIT(16) -#define STM32_DBGMCU_APB2FZ_TIM16 BIT(17) -#define STM32_DBGMCU_APB2FZ_TIM17 BIT(18) -#define STM32_DBGMCU_APB2FZ_TIM20 BIT(20) +#define STM32_DBGMCU_APB2FZ_TIM1 BIT(11) +#define STM32_DBGMCU_APB2FZ_TIM8 BIT(13) +#define STM32_DBGMCU_APB2FZ_TIM15 BIT(16) +#define STM32_DBGMCU_APB2FZ_TIM16 BIT(17) +#define STM32_DBGMCU_APB2FZ_TIM17 BIT(18) +#define STM32_DBGMCU_APB2FZ_TIM20 BIT(20) /* --- Flash --- */ -#define STM32_FLASH_REG(off) REG32(STM32_FLASH_REGS_BASE + (off)) -#define STM32_FLASH_ACR STM32_FLASH_REG(0x00) -#define STM32_FLASH_PDKEYR STM32_FLASH_REG(0x04) -#define STM32_FLASH_KEYR STM32_FLASH_REG(0x08) -#define STM32_FLASH_OPTKEYR STM32_FLASH_REG(0x0c) -#define STM32_FLASH_SR STM32_FLASH_REG(0x10) -#define STM32_FLASH_CR STM32_FLASH_REG(0x14) -#define STM32_FLASH_ECCR STM32_FLASH_REG(0x18) +#define STM32_FLASH_REG(off) REG32(STM32_FLASH_REGS_BASE + (off)) +#define STM32_FLASH_ACR STM32_FLASH_REG(0x00) +#define STM32_FLASH_PDKEYR STM32_FLASH_REG(0x04) +#define STM32_FLASH_KEYR STM32_FLASH_REG(0x08) +#define STM32_FLASH_OPTKEYR STM32_FLASH_REG(0x0c) +#define STM32_FLASH_SR STM32_FLASH_REG(0x10) +#define STM32_FLASH_CR STM32_FLASH_REG(0x14) +#define STM32_FLASH_ECCR STM32_FLASH_REG(0x18) /* * Bank 1 Option Byte Copy Registers. These registers are loaded from the option * bytes location in flash at reset, assuming that option byte loading has not * been disabled. */ -#define STM32_FLASH_OPTR STM32_FLASH_REG(0x20) -#define STM32_FLASH_PCROP1SR STM32_FLASH_REG(0x24) -#define STM32_FLASH_PCROP1ER STM32_FLASH_REG(0x28) -#define STM32_FLASH_WRP1AR STM32_FLASH_REG(0x2C) -#define STM32_FLASH_WRP1BR STM32_FLASH_REG(0x30) +#define STM32_FLASH_OPTR STM32_FLASH_REG(0x20) +#define STM32_FLASH_PCROP1SR STM32_FLASH_REG(0x24) +#define STM32_FLASH_PCROP1ER STM32_FLASH_REG(0x28) +#define STM32_FLASH_WRP1AR STM32_FLASH_REG(0x2C) +#define STM32_FLASH_WRP1BR STM32_FLASH_REG(0x30) /* * Bank 2 Option Byte Copy Registers. These will only exist for category 3 * devices. */ -#define STM32_FLASH_PCROP2SR STM32_FLASH_REG(0x44) -#define STM32_FLASH_PCROP2ER STM32_FLASH_REG(0x48) -#define STM32_FLASH_WRP2AR STM32_FLASH_REG(0x4C) -#define STM32_FLASH_WRP2BR STM32_FLASH_REG(0x50) +#define STM32_FLASH_PCROP2SR STM32_FLASH_REG(0x44) +#define STM32_FLASH_PCROP2ER STM32_FLASH_REG(0x48) +#define STM32_FLASH_WRP2AR STM32_FLASH_REG(0x4C) +#define STM32_FLASH_WRP2BR STM32_FLASH_REG(0x50) -#define STM32_FLASH_SEC_SIZE1 STM32_FLASH_REG(0x70) -#define STM32_FLASH_SEC_SIZE2 STM32_FLASH_REG(0x74) +#define STM32_FLASH_SEC_SIZE1 STM32_FLASH_REG(0x70) +#define STM32_FLASH_SEC_SIZE2 STM32_FLASH_REG(0x74) /* --- FLASH CR Bit Definitions --- */ #define STM32_FLASH_ACR_LATENCY_SHIFT (0) -#define STM32_FLASH_ACR_LATENCY_MASK (0xf << STM32_FLASH_ACR_LATENCY_SHIFT) -#define STM32_FLASH_ACR_PRFTEN BIT(8) -#define STM32_FLASH_ACR_ICEN BIT(9) -#define STM32_FLASH_ACR_DCEN BIT(10) -#define STM32_FLASH_ACR_ICRST BIT(11) -#define STM32_FLASH_ACR_DCRST BIT(12) +#define STM32_FLASH_ACR_LATENCY_MASK (0xf << STM32_FLASH_ACR_LATENCY_SHIFT) +#define STM32_FLASH_ACR_PRFTEN BIT(8) +#define STM32_FLASH_ACR_ICEN BIT(9) +#define STM32_FLASH_ACR_DCEN BIT(10) +#define STM32_FLASH_ACR_ICRST BIT(11) +#define STM32_FLASH_ACR_DCRST BIT(12) /* --- FLASH KEYR Bit Definitions --- */ -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB +#define FLASH_KEYR_KEY1 0x45670123 +#define FLASH_KEYR_KEY2 0xCDEF89AB /* --- FLASH OPTKEYR Bit Definitions --- */ -#define FLASH_OPTKEYR_KEY1 0x08192A3B -#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F +#define FLASH_OPTKEYR_KEY1 0x08192A3B +#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F /* --- FLASH SR Bit Definitions --- */ -#define FLASH_SR_BUSY BIT(16) -#define FLASH_SR_OPTVERR BIT(15) -#define FLASH_SR_RDERR BIT(14) -#define FLASH_SR_FASTERR BIT(9) -#define FLASH_SR_MISERR BIT(8) -#define FLASH_SR_PGSERR BIT(7) -#define FLASH_SR_SIZERR BIT(6) -#define FLASH_SR_PGAERR BIT(5) -#define FLASH_SR_WRPERR BIT(4) -#define FLASH_SR_PROGERR BIT(3) -#define FLASH_SR_OPERR BIT(1) -#define FLASH_SR_ERR_MASK (FLASH_SR_OPTVERR | FLASH_SR_RDERR | \ - FLASH_SR_FASTERR | FLASH_SR_PGSERR | \ - FLASH_SR_SIZERR | FLASH_SR_PGAERR | \ - FLASH_SR_WRPERR | FLASH_SR_PROGERR | \ - FLASH_SR_OPERR) +#define FLASH_SR_BUSY BIT(16) +#define FLASH_SR_OPTVERR BIT(15) +#define FLASH_SR_RDERR BIT(14) +#define FLASH_SR_FASTERR BIT(9) +#define FLASH_SR_MISERR BIT(8) +#define FLASH_SR_PGSERR BIT(7) +#define FLASH_SR_SIZERR BIT(6) +#define FLASH_SR_PGAERR BIT(5) +#define FLASH_SR_WRPERR BIT(4) +#define FLASH_SR_PROGERR BIT(3) +#define FLASH_SR_OPERR BIT(1) +#define FLASH_SR_ERR_MASK \ + (FLASH_SR_OPTVERR | FLASH_SR_RDERR | FLASH_SR_FASTERR | \ + FLASH_SR_PGSERR | FLASH_SR_SIZERR | FLASH_SR_PGAERR | \ + FLASH_SR_WRPERR | FLASH_SR_PROGERR | FLASH_SR_OPERR) /* --- FLASH CR Bit Definitions --- */ -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_STRT BIT(16) -#define FLASH_CR_OPTSTRT BIT(17) -#define FLASH_CR_OBL_LAUNCH BIT(27) -#define FLASH_CR_OPTLOCK BIT(30) -#define FLASH_CR_LOCK BIT(31) -#define FLASH_CR_PNB(sec) (((sec) & 0x7f) << 3) -#define FLASH_CR_PNB_MASK FLASH_CR_PNB(0x7f) - -#define STM32_FLASH_MIN_WRITE_SIZE (CONFIG_FLASH_WRITE_SIZE * 2) +#define FLASH_CR_PG BIT(0) +#define FLASH_CR_PER BIT(1) +#define FLASH_CR_STRT BIT(16) +#define FLASH_CR_OPTSTRT BIT(17) +#define FLASH_CR_OBL_LAUNCH BIT(27) +#define FLASH_CR_OPTLOCK BIT(30) +#define FLASH_CR_LOCK BIT(31) +#define FLASH_CR_PNB(sec) (((sec)&0x7f) << 3) +#define FLASH_CR_PNB_MASK FLASH_CR_PNB(0x7f) + +#define STM32_FLASH_MIN_WRITE_SIZE (CONFIG_FLASH_WRITE_SIZE * 2) /* --- FLASH Option bytes --- */ -#define STM32_OPTB_USER_RDP REG32(STM32_OPTB_BANK1_BASE + 0x00) -#define STM32_OPTB_PCROP1_START REG32(STM32_OPTB_BANK1_BASE + 0x08) -#define STM32_OPTB_PCROP1_END REG32(STM32_OPTB_BANK1_BASE + 0x10) -#define STM32_OPTB_WRP1AR REG32(STM32_OPTB_BANK1_BASE + 0x18) -#define STM32_OPTB_WRP1BR REG32(STM32_OPTB_BANK1_BASE + 0x20) -#define STM32_OPTB_SECURE1_MEM REG32(STM32_OPTB_BANK1_BASE + 0x28) - -#define STM32_OPTB_UNUSED REG32(STM32_OPTB_BANK2_BASE + 0x00) -#define STM32_OPTB_PCROP2_START REG32(STM32_OPTB_BANK2_BASE + 0x08) -#define STM32_OPTB_PCROP2_END REG32(STM32_OPTB_BANK2_BASE + 0x10) -#define STM32_OPTB_WRP2AR REG32(STM32_OPTB_BANK2_BASE + 0x18) -#define STM32_OPTB_WRP2BR REG32(STM32_OPTB_BANK2_BASE + 0x20) -#define STM32_OPTB_SECURE2_MEM REG32(STM32_OPTB_BANK2_BASE + 0x28) +#define STM32_OPTB_USER_RDP REG32(STM32_OPTB_BANK1_BASE + 0x00) +#define STM32_OPTB_PCROP1_START REG32(STM32_OPTB_BANK1_BASE + 0x08) +#define STM32_OPTB_PCROP1_END REG32(STM32_OPTB_BANK1_BASE + 0x10) +#define STM32_OPTB_WRP1AR REG32(STM32_OPTB_BANK1_BASE + 0x18) +#define STM32_OPTB_WRP1BR REG32(STM32_OPTB_BANK1_BASE + 0x20) +#define STM32_OPTB_SECURE1_MEM REG32(STM32_OPTB_BANK1_BASE + 0x28) + +#define STM32_OPTB_UNUSED REG32(STM32_OPTB_BANK2_BASE + 0x00) +#define STM32_OPTB_PCROP2_START REG32(STM32_OPTB_BANK2_BASE + 0x08) +#define STM32_OPTB_PCROP2_END REG32(STM32_OPTB_BANK2_BASE + 0x10) +#define STM32_OPTB_WRP2AR REG32(STM32_OPTB_BANK2_BASE + 0x18) +#define STM32_OPTB_WRP2BR REG32(STM32_OPTB_BANK2_BASE + 0x20) +#define STM32_OPTB_SECURE2_MEM REG32(STM32_OPTB_BANK2_BASE + 0x28) /* Read option bytes from flash memory for Bank 1 */ -#define STM32_OPTB_BANK1_READ(n) REG32(STM32_OPTB_BANK1_BASE + ((n) * 8)) -#define STM32_OPTB_BANK1_COMP_READ(n) REG32(STM32_OPTB_BANK1_BASE + ((n) * 8) + 0x4) -#define STM32_OPTB_BANK2_READ(n) REG32(STM32_OPTB_BANK2_BASE + ((n) * 8)) -#define STM32_OPTB_BANK2_COMP_READ(n) REG32(STM32_OPTB_BANK2_BASE + ((n) * 8) + 0x4) - -#define STM32_OPTB_USER_DBANK BIT(22) -#define STM32_OPTB_USER_nBOOT1 BIT(23) -#define STM32_OPTB_USER_nSWBOOT0 BIT(26) -#define STM32_OPTB_USER_nBOOT0 BIT(27) +#define STM32_OPTB_BANK1_READ(n) REG32(STM32_OPTB_BANK1_BASE + ((n)*8)) +#define STM32_OPTB_BANK1_COMP_READ(n) \ + REG32(STM32_OPTB_BANK1_BASE + ((n)*8) + 0x4) +#define STM32_OPTB_BANK2_READ(n) REG32(STM32_OPTB_BANK2_BASE + ((n)*8)) +#define STM32_OPTB_BANK2_COMP_READ(n) \ + REG32(STM32_OPTB_BANK2_BASE + ((n)*8) + 0x4) + +#define STM32_OPTB_USER_DBANK BIT(22) +#define STM32_OPTB_USER_nBOOT1 BIT(23) +#define STM32_OPTB_USER_nSWBOOT0 BIT(26) +#define STM32_OPTB_USER_nBOOT0 BIT(27) #define STM32_OPTB_ENTRY_NUM 6 /* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) +#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) +#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) +#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) +#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) +#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) +#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) #define EXTI_RTC_ALR_EVENT BIT(17) /* --- ADC --- */ -#define STM32_ADC_ISR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC_IER REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC_CR REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC_CFGR REG32(STM32_ADC1_BASE + 0x0C) -#define STM32_ADC_CFGR2 REG32(STM32_ADC1_BASE + 0x10) -#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x14) -#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x18) -#define STM32_ADC_TR1 REG32(STM32_ADC1_BASE + 0x20) -#define STM32_ADC_TR2 REG32(STM32_ADC1_BASE + 0x24) -#define STM32_ADC_TR3 REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) -#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24) -#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x30 + ((n)&3) * 4) -#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x30) -#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x34) -#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x38) -#define STM32_ADC_SQR4 REG32(STM32_ADC1_BASE + 0x3C) -#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x40) -#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x4C) -#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x80 + ((n)&3) * 4) - +#define STM32_ADC_ISR REG32(STM32_ADC1_BASE + 0x00) +#define STM32_ADC_IER REG32(STM32_ADC1_BASE + 0x04) +#define STM32_ADC_CR REG32(STM32_ADC1_BASE + 0x08) +#define STM32_ADC_CFGR REG32(STM32_ADC1_BASE + 0x0C) +#define STM32_ADC_CFGR2 REG32(STM32_ADC1_BASE + 0x10) +#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x14) +#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x18) +#define STM32_ADC_TR1 REG32(STM32_ADC1_BASE + 0x20) +#define STM32_ADC_TR2 REG32(STM32_ADC1_BASE + 0x24) +#define STM32_ADC_TR3 REG32(STM32_ADC1_BASE + 0x28) +#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) +#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24) +#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28) +#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x30 + ((n)&3) * 4) +#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x30) +#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x34) +#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x38) +#define STM32_ADC_SQR4 REG32(STM32_ADC1_BASE + 0x3C) +#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x40) +#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x4C) +#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x80 + ((n)&3) * 4) /* --- ADC CR Bit Definitions --- */ -#define STM32_ADC_CR_ADEN BIT(0) -#define STM32_ADC_CR_ADSTART BIT(2) -#define STM32_ADC_CR_ADVREGEN BIT(28) -#define STM32_ADC_CR_CAL BIT(31) +#define STM32_ADC_CR_ADEN BIT(0) +#define STM32_ADC_CR_ADSTART BIT(2) +#define STM32_ADC_CR_ADVREGEN BIT(28) +#define STM32_ADC_CR_CAL BIT(31) -#define STM32_ADC_CFGR_CONT BIT(13) -#define STM32_ADC_CR2_ALIGN BIT(15) +#define STM32_ADC_CFGR_CONT BIT(13) +#define STM32_ADC_CR2_ALIGN BIT(15) /* --- Comparators --- */ - /* --- DMA --- */ /* * Available DMA streams, numbered from 0. @@ -1175,11 +1148,11 @@ enum dma_channel { /* Registers for a single channel of the DMA controller */ struct stm32_dma_chan { - uint32_t ccr; /* Control */ - uint32_t cndtr; /* Number of data to transfer */ - uint32_t cpar; /* Peripheral address */ - uint32_t cmar; /* Memory address */ - uint32_t reserved; + uint32_t ccr; /* Control */ + uint32_t cndtr; /* Number of data to transfer */ + uint32_t cpar; /* Peripheral address */ + uint32_t cmar; /* Memory address */ + uint32_t reserved; }; /* Always use stm32_dma_chan_t so volatile keyword is included! */ @@ -1190,8 +1163,8 @@ typedef stm32_dma_chan_t dma_chan_t; /* Registers for the DMA controller */ struct stm32_dma_regs { - uint32_t isr; - uint32_t ifcr; + uint32_t isr; + uint32_t ifcr; stm32_dma_chan_t chan[STM32_DMAC_COUNT]; }; @@ -1200,78 +1173,77 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - -#define STM32_DMA_CCR_CHANNEL(channel) (0) +#define STM32_DMA_CCR_CHANNEL(channel) (0) #define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE) #define STM32_DMA_REGS(channel) \ ((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS) -#define STM32_DMA_CSELR(channel) \ - REG32(((channel) < STM32_DMAC_PER_CTLR ? \ - STM32_DMA1_BASE : STM32_DMA2_BASE) + 0xA8) +#define STM32_DMA_CSELR(channel) \ + REG32(((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_BASE : \ + STM32_DMA2_BASE) + \ + 0xA8) /* Bits for DMA controller regs (isr and ifcr) */ -#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) +#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) #define STM32_DMA_ISR_MASK(channel, mask) \ ((mask) << STM32_DMA_CH_OFFSET(channel)) -#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) -#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) -#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) -#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) -#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) - -#define STM32_DMA_GIF BIT(0) -#define STM32_DMA_TCIF BIT(1) -#define STM32_DMA_HTIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_ALL 0xf - -#define STM32_DMA_GET_ISR(channel) \ - ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr = \ - ((STM32_DMA_REGS(channel)->isr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) -#define STM32_DMA_GET_IFCR(channel) \ - ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr = \ - ((STM32_DMA_REGS(channel)->ifcr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) - +#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) +#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) +#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) +#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) +#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) + +#define STM32_DMA_GIF BIT(0) +#define STM32_DMA_TCIF BIT(1) +#define STM32_DMA_HTIF BIT(2) +#define STM32_DMA_TEIF BIT(3) +#define STM32_DMA_ALL 0xf + +#define STM32_DMA_GET_ISR(channel) \ + ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) & \ + STM32_DMA_ALL) +#define STM32_DMA_SET_ISR(channel, val) \ + (STM32_DMA_REGS(channel)->isr = \ + ((STM32_DMA_REGS(channel)->isr & \ + ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) +#define STM32_DMA_GET_IFCR(channel) \ + ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) & \ + STM32_DMA_ALL) +#define STM32_DMA_SET_IFCR(channel, val) \ + (STM32_DMA_REGS(channel)->ifcr = \ + ((STM32_DMA_REGS(channel)->ifcr & \ + ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) /* Bits for DMA channel regs */ -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_TCIE BIT(1) -#define STM32_DMA_CCR_HTIE BIT(2) -#define STM32_DMA_CCR_TEIE BIT(3) -#define STM32_DMA_CCR_DIR BIT(4) -#define STM32_DMA_CCR_CIRC BIT(5) -#define STM32_DMA_CCR_PINC BIT(6) -#define STM32_DMA_CCR_MINC BIT(7) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) -#define STM32_DMA_CCR_PL_LOW (0 << 12) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) -#define STM32_DMA_CCR_PL_HIGH (2 << 12) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) -#define STM32_DMA_CCR_MEM2MEM BIT(14) +#define STM32_DMA_CCR_EN BIT(0) +#define STM32_DMA_CCR_TCIE BIT(1) +#define STM32_DMA_CCR_HTIE BIT(2) +#define STM32_DMA_CCR_TEIE BIT(3) +#define STM32_DMA_CCR_DIR BIT(4) +#define STM32_DMA_CCR_CIRC BIT(5) +#define STM32_DMA_CCR_PINC BIT(6) +#define STM32_DMA_CCR_MINC BIT(7) +#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) +#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) +#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) +#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) +#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) +#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) +#define STM32_DMA_CCR_PL_LOW (0 << 12) +#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) +#define STM32_DMA_CCR_PL_HIGH (2 << 12) +#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) +#define STM32_DMA_CCR_MEM2MEM BIT(14) /* The requests for the DMA1/DMA2 controllers are routed through DMAMUX. */ /* DMAMUX registers */ -#define STM32_DMAMUX_CxCR(x) REG32(STM32_DMAMUX_BASE + 4 * (x)) -#define STM32_DMAMUX_CSR REG32(STM32_DMAMUX_BASE + 0x80) -#define STM32_DMAMUX_CFR REG32(STM32_DMAMUX_BASE + 0x84) -#define STM32_DMAMUX_RGxCR(x) REG32(STM32_DMAMUX_BASE + 0x100 + 4 * (x)) -#define STM32_DMAMUX_RGSR REG32(STM32_DMAMUX_BASE + 0x140) -#define STM32_DMAMUX_RGCFR REG32(STM32_DMAMUX_BASE + 0x144) +#define STM32_DMAMUX_CxCR(x) REG32(STM32_DMAMUX_BASE + 4 * (x)) +#define STM32_DMAMUX_CSR REG32(STM32_DMAMUX_BASE + 0x80) +#define STM32_DMAMUX_CFR REG32(STM32_DMAMUX_BASE + 0x84) +#define STM32_DMAMUX_RGxCR(x) REG32(STM32_DMAMUX_BASE + 0x100 + 4 * (x)) +#define STM32_DMAMUX_RGSR REG32(STM32_DMAMUX_BASE + 0x140) +#define STM32_DMAMUX_RGCFR REG32(STM32_DMAMUX_BASE + 0x144) enum dmamux1_request { DMAMUX_REQ_ADC1 = 5, @@ -1378,94 +1350,41 @@ enum dmamux1_request { #define DMAMUX_REQ_UART9_TX DMAMUX_REQ_LPUART1_TX /* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) - +#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) + +#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) +#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) +#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) +#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) + +#define STM32_CRC_CR_RESET BIT(0) +#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) +#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) +#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) +#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) +#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) +#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) +#define STM32_CRC_CR_REV_IN_WORD (3 << 5) +#define STM32_CRC_CR_REV_OUT BIT(7) /* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) -#define STM32_USB_BCDR_DPPU BIT(15) +#define STM32_USB_BCDR_DPPU BIT(15) /* --- USB Endpoint bit definitions --- */ -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 +#define EP_MASK 0x0F0F +#define EP_TX_DTOG 0x0040 +#define EP_TX_MASK 0x0030 #define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 +#define EP_TX_NAK 0x0020 #define EP_TX_STALL 0x0010 #define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 +#define EP_RX_DTOG 0x4000 +#define EP_RX_MASK 0x3000 #define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 +#define EP_RX_NAK 0x2000 #define EP_RX_STALL 0x1000 #define EP_RX_DISAB 0x0000 @@ -1475,31 +1394,30 @@ enum dmamux1_request { #define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) #define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) + STM32_USB_EP(n) = \ + (((STM32_USB_EP(n) & (EP_MASK | (mask))) ^ (val)) | (flags)) /* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) +#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) +#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) +#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) /* --- RNG CR Bit Definitions --- */ -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) +#define STM32_RNG_CR_RNGEN BIT(2) +#define STM32_RNG_CR_IE BIT(3) +#define STM32_RNG_CR_CED BIT(5) /* --- RNG SR_DRDY Bit Definitions --- */ -#define STM32_RNG_SR_DRDY BIT(0) +#define STM32_RNG_SR_DRDY BIT(0) /* --- AXI interconnect --- */ /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) +#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x)) +#define WRITE_ISS_OVERRIDE BIT(1) +#define READ_ISS_OVERRIDE BIT(0) /* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) +#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) +#define STM32_UNIQUE_ID_LENGTH (3 * 4) #endif /* !__ASSEMBLER__ */ diff --git a/chip/stm32/registers-stm32h7.h b/chip/stm32/registers-stm32h7.h index 1ae8e3bdaa..f4178d17f0 100644 --- a/chip/stm32/registers-stm32h7.h +++ b/chip/stm32/registers-stm32h7.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,591 +19,586 @@ #endif /* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_TAMPER_STAMP 2 -#define STM32_IRQ_RTC_WAKEUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#define STM32_IRQ_USB_HP 19 -#define STM32_IRQ_USB_LP 20 - -#define STM32_IRQ_ADC1 18 /* STM32L4 only */ -#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ -#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ -#define STM32_IRQ_DAC 21 -#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ - -#define STM32_IRQ_COMP 22 - -#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_TIM3 29 -#define STM32_IRQ_TIM4 30 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ -#define STM32_IRQ_CEC 42 /* STM32F373 only */ -#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ -#define STM32_IRQ_TIM12 43 /* STM32F373 only */ -#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ -#define STM32_IRQ_TIM13 44 /* STM32F373 only */ -#define STM32_IRQ_TIM14 45 /* STM32F373 only */ -#define STM32_IRQ_TIM5 50 /* STM32F373 */ -#define STM32_IRQ_SPI3 51 /* STM32F373 */ -#define STM32_IRQ_USART4 52 /* STM32F446 only */ -#define STM32_IRQ_USART5 53 /* STM32F446 only */ -#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ -#define STM32_IRQ_TIM7 55 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ +#define STM32_IRQ_WWDG 0 +#define STM32_IRQ_PVD 1 +#define STM32_IRQ_TAMPER_STAMP 2 +#define STM32_IRQ_RTC_WAKEUP 3 +#define STM32_IRQ_FLASH 4 +#define STM32_IRQ_RCC 5 +#define STM32_IRQ_EXTI0 6 +#define STM32_IRQ_EXTI1 7 +#define STM32_IRQ_EXTI2 8 +#define STM32_IRQ_EXTI3 9 +#define STM32_IRQ_EXTI4 10 +#define STM32_IRQ_DMA_CHANNEL_1 11 +#define STM32_IRQ_DMA_CHANNEL_2 12 +#define STM32_IRQ_DMA_CHANNEL_3 13 +#define STM32_IRQ_DMA_CHANNEL_4 14 +#define STM32_IRQ_DMA_CHANNEL_5 15 +#define STM32_IRQ_DMA_CHANNEL_6 16 +#define STM32_IRQ_DMA_CHANNEL_7 17 +#define STM32_IRQ_USB_HP 19 +#define STM32_IRQ_USB_LP 20 + +#define STM32_IRQ_ADC1 18 /* STM32L4 only */ +#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ +#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ +#define STM32_IRQ_DAC 21 +#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ + +#define STM32_IRQ_COMP 22 + +#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ +#define STM32_IRQ_EXTI9_5 23 +#define STM32_IRQ_TIM2 28 +#define STM32_IRQ_TIM3 29 +#define STM32_IRQ_TIM4 30 +#define STM32_IRQ_I2C1_EV 31 +#define STM32_IRQ_I2C1_ER 32 +#define STM32_IRQ_I2C2_EV 33 +#define STM32_IRQ_I2C2_ER 34 +#define STM32_IRQ_SPI1 35 +#define STM32_IRQ_SPI2 36 +#define STM32_IRQ_USART1 37 +#define STM32_IRQ_USART2 38 +#define STM32_IRQ_USART3 39 +#define STM32_IRQ_EXTI15_10 40 +#define STM32_IRQ_RTC_ALARM 41 +#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ +#define STM32_IRQ_CEC 42 /* STM32F373 only */ +#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ +#define STM32_IRQ_TIM12 43 /* STM32F373 only */ +#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ +#define STM32_IRQ_TIM13 44 /* STM32F373 only */ +#define STM32_IRQ_TIM14 45 /* STM32F373 only */ +#define STM32_IRQ_TIM5 50 /* STM32F373 */ +#define STM32_IRQ_SPI3 51 /* STM32F373 */ +#define STM32_IRQ_USART4 52 /* STM32F446 only */ +#define STM32_IRQ_USART5 53 /* STM32F446 only */ +#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ +#define STM32_IRQ_TIM7 55 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ /* if MISC_REMAP bits are set */ -#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ -#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ -#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ -#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ -#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ -#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ -#define STM32_IRQ_LPUART 70 /* STM32L4 only */ -#define STM32_IRQ_USART9 70 /* STM32L4 only */ -#define STM32_IRQ_USART6 71 /* STM32F446 only */ -#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ -#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ -#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ -#define STM32_IRQ_TIM19 78 /* STM32F373 only */ -#define STM32_IRQ_AES 79 /* STM32L4 only */ -#define STM32_IRQ_RNG 80 /* STM32L4 only */ -#define STM32_IRQ_FPU 81 /* STM32F373 only */ - -#define STM32_IRQ_LPTIM1 93 -#define STM32_IRQ_TIM15 116 -#define STM32_IRQ_TIM16 117 -#define STM32_IRQ_TIM17 118 -#define STM32_IRQ_LPTIM2 138 -#define STM32_IRQ_LPTIM3 139 -#define STM32_IRQ_LPTIM4 140 -#define STM32_IRQ_LPTIM5 141 +#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ +#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ +#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ +#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ +#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ +#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ +#define STM32_IRQ_LPUART 70 /* STM32L4 only */ +#define STM32_IRQ_USART9 70 /* STM32L4 only */ +#define STM32_IRQ_USART6 71 /* STM32F446 only */ +#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ +#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ +#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ +#define STM32_IRQ_TIM19 78 /* STM32F373 only */ +#define STM32_IRQ_AES 79 /* STM32L4 only */ +#define STM32_IRQ_RNG 80 /* STM32L4 only */ +#define STM32_IRQ_FPU 81 /* STM32F373 only */ + +#define STM32_IRQ_LPTIM1 93 +#define STM32_IRQ_TIM15 116 +#define STM32_IRQ_TIM16 117 +#define STM32_IRQ_TIM17 118 +#define STM32_IRQ_LPTIM2 138 +#define STM32_IRQ_LPTIM3 139 +#define STM32_IRQ_LPTIM4 140 +#define STM32_IRQ_LPTIM5 141 /* To simplify code generation, define DMA channel 9..10 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 +#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 +#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 +#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 +#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 /* aliases for easier code sharing */ #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV #define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV #define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV - /* * STM32F4 introduces a concept of DMA stream to allow * fine allocation of a stream to a channel. */ -#define STM32_IRQ_DMA1_STREAM0 11 -#define STM32_IRQ_DMA1_STREAM1 12 -#define STM32_IRQ_DMA1_STREAM2 13 -#define STM32_IRQ_DMA1_STREAM3 14 -#define STM32_IRQ_DMA1_STREAM4 15 -#define STM32_IRQ_DMA1_STREAM5 16 -#define STM32_IRQ_DMA1_STREAM6 17 -#define STM32_IRQ_DMA1_STREAM7 47 -#define STM32_IRQ_DMA2_STREAM0 56 -#define STM32_IRQ_DMA2_STREAM1 57 -#define STM32_IRQ_DMA2_STREAM2 58 -#define STM32_IRQ_DMA2_STREAM3 59 -#define STM32_IRQ_DMA2_STREAM4 60 -#define STM32_IRQ_DMA2_STREAM5 68 -#define STM32_IRQ_DMA2_STREAM6 69 -#define STM32_IRQ_DMA2_STREAM7 70 - -#define STM32_IRQ_OTG_HS_WKUP 76 -#define STM32_IRQ_OTG_HS_EP1_IN 75 -#define STM32_IRQ_OTG_HS_EP1_OUT 74 -#define STM32_IRQ_OTG_HS 77 -#define STM32_IRQ_OTG_FS 67 -#define STM32_IRQ_OTG_FS_WKUP 42 +#define STM32_IRQ_DMA1_STREAM0 11 +#define STM32_IRQ_DMA1_STREAM1 12 +#define STM32_IRQ_DMA1_STREAM2 13 +#define STM32_IRQ_DMA1_STREAM3 14 +#define STM32_IRQ_DMA1_STREAM4 15 +#define STM32_IRQ_DMA1_STREAM5 16 +#define STM32_IRQ_DMA1_STREAM6 17 +#define STM32_IRQ_DMA1_STREAM7 47 +#define STM32_IRQ_DMA2_STREAM0 56 +#define STM32_IRQ_DMA2_STREAM1 57 +#define STM32_IRQ_DMA2_STREAM2 58 +#define STM32_IRQ_DMA2_STREAM3 59 +#define STM32_IRQ_DMA2_STREAM4 60 +#define STM32_IRQ_DMA2_STREAM5 68 +#define STM32_IRQ_DMA2_STREAM6 69 +#define STM32_IRQ_DMA2_STREAM7 70 + +#define STM32_IRQ_OTG_HS_WKUP 76 +#define STM32_IRQ_OTG_HS_EP1_IN 75 +#define STM32_IRQ_OTG_HS_EP1_OUT 74 +#define STM32_IRQ_OTG_HS 77 +#define STM32_IRQ_OTG_FS 67 +#define STM32_IRQ_OTG_FS_WKUP 42 /* Peripheral base addresses */ -#define STM32_GPV_BASE 0x51000000 - -#define STM32_DBGMCU_BASE 0x5C001000 - -#define STM32_BDMA_BASE 0x58025400 -#define STM32_DMA1_BASE 0x40020000 -#define STM32_DMA2_BASE 0x40020400 -#define STM32_DMA2D_BASE 0x52001000 -#define STM32_DMAMUX1_BASE 0x40020800 -#define STM32_DMAMUX2_BASE 0x58025800 -#define STM32_MDMA_BASE 0x52000000 - -#define STM32_EXTI_BASE 0x58000000 - -#define STM32_FLASH_REGS_BASE 0x52002000 - -#define STM32_GPIOA_BASE 0x58020000 -#define STM32_GPIOB_BASE 0x58020400 -#define STM32_GPIOC_BASE 0x58020800 -#define STM32_GPIOD_BASE 0x58020C00 -#define STM32_GPIOE_BASE 0x58021000 -#define STM32_GPIOF_BASE 0x58021400 -#define STM32_GPIOG_BASE 0x58021800 -#define STM32_GPIOH_BASE 0x58021C00 -#define STM32_GPIOI_BASE 0x58022000 -#define STM32_GPIOJ_BASE 0x58022400 -#define STM32_GPIOK_BASE 0x58022800 - -#define STM32_IWDG_BASE 0x58004800 - -#define STM32_LPTIM1_BASE 0x40002400 -#define STM32_LPTIM2_BASE 0x58002400 -#define STM32_LPTIM3_BASE 0x58002800 -#define STM32_LPTIM4_BASE 0x58002C00 -#define STM32_LPTIM5_BASE 0x58003000 - -#define STM32_PWR_BASE 0x58024800 -#define STM32_RCC_BASE 0x58024400 -#define STM32_RNG_BASE 0x48021800 -#define STM32_RTC_BASE 0x58004000 - -#define STM32_SYSCFG_BASE 0x58000400 - -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 -#define STM32_SPI4_BASE 0x40013400 -#define STM32_SPI5_BASE 0x40015000 - -#define STM32_TIM1_BASE 0x40010000 -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM8_BASE 0x40010400 -#define STM32_TIM12_BASE 0x40001800 -#define STM32_TIM13_BASE 0x40001c00 -#define STM32_TIM14_BASE 0x40002000 -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 - -#define STM32_UNIQUE_ID_BASE 0x1ff1e800 - -#define STM32_USART1_BASE 0x40011000 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART5_BASE 0x40005000 -#define STM32_USART6_BASE 0x40011400 -#define STM32_USART7_BASE 0x40007800 -#define STM32_USART8_BASE 0x40007C00 +#define STM32_GPV_BASE 0x51000000 + +#define STM32_DBGMCU_BASE 0x5C001000 + +#define STM32_BDMA_BASE 0x58025400 +#define STM32_DMA1_BASE 0x40020000 +#define STM32_DMA2_BASE 0x40020400 +#define STM32_DMA2D_BASE 0x52001000 +#define STM32_DMAMUX1_BASE 0x40020800 +#define STM32_DMAMUX2_BASE 0x58025800 +#define STM32_MDMA_BASE 0x52000000 + +#define STM32_EXTI_BASE 0x58000000 + +#define STM32_FLASH_REGS_BASE 0x52002000 + +#define STM32_GPIOA_BASE 0x58020000 +#define STM32_GPIOB_BASE 0x58020400 +#define STM32_GPIOC_BASE 0x58020800 +#define STM32_GPIOD_BASE 0x58020C00 +#define STM32_GPIOE_BASE 0x58021000 +#define STM32_GPIOF_BASE 0x58021400 +#define STM32_GPIOG_BASE 0x58021800 +#define STM32_GPIOH_BASE 0x58021C00 +#define STM32_GPIOI_BASE 0x58022000 +#define STM32_GPIOJ_BASE 0x58022400 +#define STM32_GPIOK_BASE 0x58022800 + +#define STM32_IWDG_BASE 0x58004800 + +#define STM32_LPTIM1_BASE 0x40002400 +#define STM32_LPTIM2_BASE 0x58002400 +#define STM32_LPTIM3_BASE 0x58002800 +#define STM32_LPTIM4_BASE 0x58002C00 +#define STM32_LPTIM5_BASE 0x58003000 + +#define STM32_PWR_BASE 0x58024800 +#define STM32_RCC_BASE 0x58024400 +#define STM32_RNG_BASE 0x48021800 +#define STM32_RTC_BASE 0x58004000 + +#define STM32_SYSCFG_BASE 0x58000400 + +#define STM32_SPI1_BASE 0x40013000 +#define STM32_SPI2_BASE 0x40003800 +#define STM32_SPI3_BASE 0x40003c00 +#define STM32_SPI4_BASE 0x40013400 +#define STM32_SPI5_BASE 0x40015000 + +#define STM32_TIM1_BASE 0x40010000 +#define STM32_TIM2_BASE 0x40000000 +#define STM32_TIM3_BASE 0x40000400 +#define STM32_TIM4_BASE 0x40000800 +#define STM32_TIM5_BASE 0x40000c00 +#define STM32_TIM6_BASE 0x40001000 +#define STM32_TIM7_BASE 0x40001400 +#define STM32_TIM8_BASE 0x40010400 +#define STM32_TIM12_BASE 0x40001800 +#define STM32_TIM13_BASE 0x40001c00 +#define STM32_TIM14_BASE 0x40002000 +#define STM32_TIM15_BASE 0x40014000 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_TIM17_BASE 0x40014800 + +#define STM32_UNIQUE_ID_BASE 0x1ff1e800 + +#define STM32_USART1_BASE 0x40011000 +#define STM32_USART2_BASE 0x40004400 +#define STM32_USART3_BASE 0x40004800 +#define STM32_USART4_BASE 0x40004c00 +#define STM32_USART5_BASE 0x40005000 +#define STM32_USART6_BASE 0x40011400 +#define STM32_USART7_BASE 0x40007800 +#define STM32_USART8_BASE 0x40007C00 #ifndef __ASSEMBLER__ /* Register definitions */ /* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_UESM BIT(1) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR2_SWAP BIT(15) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) -#define STM32_USART_CR3_OVRDIS BIT(12) -#define STM32_USART_CR3_WUS_START_BIT (2 << 20) -#define STM32_USART_CR3_WUFIE BIT(22) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) -#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) -#define STM32_USART_ICR_ORECF BIT(3) -#define STM32_USART_ICR_TCCF BIT(6) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) -#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) +#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) +#define STM32_USART_CR1_UE BIT(0) +#define STM32_USART_CR1_UESM BIT(1) +#define STM32_USART_CR1_RE BIT(2) +#define STM32_USART_CR1_TE BIT(3) +#define STM32_USART_CR1_RXNEIE BIT(5) +#define STM32_USART_CR1_TCIE BIT(6) +#define STM32_USART_CR1_TXEIE BIT(7) +#define STM32_USART_CR1_PS BIT(9) +#define STM32_USART_CR1_PCE BIT(10) +#define STM32_USART_CR1_M BIT(12) +#define STM32_USART_CR1_OVER8 BIT(15) +#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) +#define STM32_USART_CR2_SWAP BIT(15) +#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) +#define STM32_USART_CR3_EIE BIT(0) +#define STM32_USART_CR3_DMAR BIT(6) +#define STM32_USART_CR3_DMAT BIT(7) +#define STM32_USART_CR3_ONEBIT BIT(11) +#define STM32_USART_CR3_OVRDIS BIT(12) +#define STM32_USART_CR3_WUS_START_BIT (2 << 20) +#define STM32_USART_CR3_WUFIE BIT(22) +#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) +#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) +#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) +#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) +#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) +#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) +#define STM32_USART_ICR_ORECF BIT(3) +#define STM32_USART_ICR_TCCF BIT(6) +#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) +#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) +#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) /* register alias */ -#define STM32_USART_SR(base) STM32_USART_ISR(base) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) +#define STM32_USART_SR(base) STM32_USART_ISR(base) +#define STM32_USART_SR_ORE BIT(3) +#define STM32_USART_SR_RXNE BIT(5) +#define STM32_USART_SR_TC BIT(6) +#define STM32_USART_SR_TXE BIT(7) /* --- GPIO --- */ - -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) - -#define GPIO_ALT_SYS 0x0 -#define GPIO_ALT_TIM2 0x1 -#define GPIO_ALT_TIM3_4 0x2 -#define GPIO_ALT_TIM9_11 0x3 -#define GPIO_ALT_I2C 0x4 -#define GPIO_ALT_SPI 0x5 -#define GPIO_ALT_SPI3 0x6 -#define GPIO_ALT_USART 0x7 -#define GPIO_ALT_I2C_23 0x9 -#define GPIO_ALT_USB 0xA -#define GPIO_ALT_LCD 0xB -#define GPIO_ALT_RI 0xE -#define GPIO_ALT_EVENTOUT 0xF +#define STM32_GPIO_MODER(b) REG32((b) + 0x00) +#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) +#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) +#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) +#define STM32_GPIO_IDR(b) REG16((b) + 0x10) +#define STM32_GPIO_ODR(b) REG16((b) + 0x14) +#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) +#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) +#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) +#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) + +#define GPIO_ALT_SYS 0x0 +#define GPIO_ALT_TIM2 0x1 +#define GPIO_ALT_TIM3_4 0x2 +#define GPIO_ALT_TIM9_11 0x3 +#define GPIO_ALT_I2C 0x4 +#define GPIO_ALT_SPI 0x5 +#define GPIO_ALT_SPI3 0x6 +#define GPIO_ALT_USART 0x7 +#define GPIO_ALT_I2C_23 0x9 +#define GPIO_ALT_USB 0xA +#define GPIO_ALT_LCD 0xB +#define GPIO_ALT_RI 0xE +#define GPIO_ALT_EVENTOUT 0xF /* --- I2C --- */ -#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_START BIT(8) -#define STM32_I2C_CR1_STOP BIT(9) -#define STM32_I2C_CR1_ACK BIT(10) -#define STM32_I2C_CR1_POS BIT(11) -#define STM32_I2C_CR1_SWRST BIT(15) -#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_ITERREN BIT(8) -#define STM32_I2C_CR2_ITEVTEN BIT(9) -#define STM32_I2C_CR2_ITBUFEN BIT(10) -#define STM32_I2C_CR2_DMAEN BIT(11) -#define STM32_I2C_CR2_LAST BIT(12) -#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR1_B14 BIT(14) -#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_OAR2_ENDUAL BIT(0) -#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_SR1_SB BIT(0) -#define STM32_I2C_SR1_ADDR BIT(1) -#define STM32_I2C_SR1_BTF BIT(2) -#define STM32_I2C_SR1_STOPF BIT(4) -#define STM32_I2C_SR1_RXNE BIT(6) -#define STM32_I2C_SR1_TXE BIT(7) -#define STM32_I2C_SR1_BERR BIT(8) -#define STM32_I2C_SR1_ARLO BIT(9) -#define STM32_I2C_SR1_AF BIT(10) - -#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_SR2_BUSY BIT(1) -#define STM32_I2C_SR2_TRA BIT(2) -#define STM32_I2C_SR2_DUALF BIT(7) - -#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_CCR_DUTY BIT(14) -#define STM32_I2C_CCR_FM BIT(15) -#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) - +#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) +#define STM32_I2C_CR1_PE BIT(0) +#define STM32_I2C_CR1_START BIT(8) +#define STM32_I2C_CR1_STOP BIT(9) +#define STM32_I2C_CR1_ACK BIT(10) +#define STM32_I2C_CR1_POS BIT(11) +#define STM32_I2C_CR1_SWRST BIT(15) +#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04)) +#define STM32_I2C_CR2_ITERREN BIT(8) +#define STM32_I2C_CR2_ITEVTEN BIT(9) +#define STM32_I2C_CR2_ITBUFEN BIT(10) +#define STM32_I2C_CR2_DMAEN BIT(11) +#define STM32_I2C_CR2_LAST BIT(12) +#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08)) +#define STM32_I2C_OAR1_B14 BIT(14) +#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C)) +#define STM32_I2C_OAR2_ENDUAL BIT(0) +#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10)) +#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14)) +#define STM32_I2C_SR1_SB BIT(0) +#define STM32_I2C_SR1_ADDR BIT(1) +#define STM32_I2C_SR1_BTF BIT(2) +#define STM32_I2C_SR1_STOPF BIT(4) +#define STM32_I2C_SR1_RXNE BIT(6) +#define STM32_I2C_SR1_TXE BIT(7) +#define STM32_I2C_SR1_BERR BIT(8) +#define STM32_I2C_SR1_ARLO BIT(9) +#define STM32_I2C_SR1_AF BIT(10) + +#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18)) +#define STM32_I2C_SR2_BUSY BIT(1) +#define STM32_I2C_SR2_TRA BIT(2) +#define STM32_I2C_SR2_DUALF BIT(7) + +#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) +#define STM32_I2C_CCR_DUTY BIT(14) +#define STM32_I2C_CCR_FM BIT(15) +#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) /* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) -#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x08) -#define STM32_PWR_CR3 REG32(STM32_PWR_BASE + 0x0C) -#define STM32_PWR_CR3_BYPASS BIT(0) -#define STM32_PWR_CR3_LDOEN BIT(1) -#define STM32_PWR_CR3_SCUEN BIT(2) -#define STM32_PWR_CR3_VBE BIT(8) -#define STM32_PWR_CR3_VBRS BIT(9) -#define STM32_PWR_CR3_USB33DEN BIT(24) -#define STM32_PWR_CR3_USBREGEN BIT(25) -#define STM32_PWR_CR3_USB33RDY BIT(26) -#define STM32_PWR_CPUCR REG32(STM32_PWR_BASE + 0x10) -#define STM32_PWR_CPUCR_PDDS_D1 BIT(0) -#define STM32_PWR_CPUCR_PDDS_D2 BIT(1) -#define STM32_PWR_CPUCR_PDDS_D3 BIT(2) -#define STM32_PWR_CPUCR_STOPF BIT(5) -#define STM32_PWR_CPUCR_SBF BIT(6) -#define STM32_PWR_CPUCR_SBF_D1 BIT(7) -#define STM32_PWR_CPUCR_SBF_D2 BIT(8) -#define STM32_PWR_CPUCR_CSSF BIT(9) -#define STM32_PWR_CPUCR_RUN_D3 BIT(11) -#define STM32_PWR_D3CR REG32(STM32_PWR_BASE + 0x18) -#define STM32_PWR_D3CR_VOS1 (3 << 14) -#define STM32_PWR_D3CR_VOS2 (2 << 14) -#define STM32_PWR_D3CR_VOS3 (1 << 14) -#define STM32_PWR_D3CR_VOSMASK (3 << 14) -#define STM32_PWR_D3CR_VOSRDY (1 << 13) -#define STM32_PWR_WKUPCR REG32(STM32_PWR_BASE + 0x20) -#define STM32_PWR_WKUPFR REG32(STM32_PWR_BASE + 0x24) -#define STM32_PWR_WKUPEPR REG32(STM32_PWR_BASE + 0x28) - - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x000) -#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x004) -#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x008) -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x010) -#define STM32_RCC_D1CFGR REG32(STM32_RCC_BASE + 0x018) -#define STM32_RCC_D2CFGR REG32(STM32_RCC_BASE + 0x01C) -#define STM32_RCC_D3CFGR REG32(STM32_RCC_BASE + 0x020) -#define STM32_RCC_PLLCKSELR REG32(STM32_RCC_BASE + 0x028) -#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x02C) -#define STM32_RCC_PLL1DIVR REG32(STM32_RCC_BASE + 0x030) -#define STM32_RCC_PLL1FRACR REG32(STM32_RCC_BASE + 0x034) -#define STM32_RCC_PLL2DIVR REG32(STM32_RCC_BASE + 0x038) -#define STM32_RCC_PLL2FRACR REG32(STM32_RCC_BASE + 0x03C) -#define STM32_RCC_PLL3DIVR REG32(STM32_RCC_BASE + 0x040) -#define STM32_RCC_PLL3FRACR REG32(STM32_RCC_BASE + 0x044) -#define STM32_RCC_D1CCIPR REG32(STM32_RCC_BASE + 0x04C) -#define STM32_RCC_D2CCIP1R REG32(STM32_RCC_BASE + 0x050) -#define STM32_RCC_D2CCIP2R REG32(STM32_RCC_BASE + 0x054) -#define STM32_RCC_D3CCIPR REG32(STM32_RCC_BASE + 0x058) -#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x060) -#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x064) -#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x068) -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x070) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x074) - -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x098) - -#define STM32_RCC_RSR REG32(STM32_RCC_BASE + 0x0D0) -#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x0D4) -#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x0D8) -#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x0DC) -#define STM32_RCC_AHB2ENR_RNGEN BIT(6) -#define STM32_RCC_AHB2ENR_HASHEN BIT(5) -#define STM32_RCC_AHB2ENR_CRYPTEN BIT(4) -#define STM32_RCC_AHB4ENR REG32(STM32_RCC_BASE + 0x0E0) -#define STM32_RCC_AHB4ENR_GPIOMASK 0x3ff -#define STM32_RCC_APB3ENR REG32(STM32_RCC_BASE + 0x0E4) -#define STM32_RCC_APB1LENR REG32(STM32_RCC_BASE + 0x0E8) -#define STM32_RCC_APB1HENR REG32(STM32_RCC_BASE + 0x0EC) -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x0F0) -#define STM32_RCC_APB4ENR REG32(STM32_RCC_BASE + 0x0F4) -#define STM32_RCC_SYSCFGEN BIT(1) -#define STM32_RCC_AHB3LPENR REG32(STM32_RCC_BASE + 0x0FC) -#define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x100) -#define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x104) -#define STM32_RCC_AHB4LPENR REG32(STM32_RCC_BASE + 0x108) -#define STM32_RCC_APB3LPENR REG32(STM32_RCC_BASE + 0x10C) -#define STM32_RCC_APB1LLPENR REG32(STM32_RCC_BASE + 0x110) -#define STM32_RCC_APB1HLPENR REG32(STM32_RCC_BASE + 0x114) -#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x118) -#define STM32_RCC_APB4LPENR REG32(STM32_RCC_BASE + 0x11C) +#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) +#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x08) +#define STM32_PWR_CR3 REG32(STM32_PWR_BASE + 0x0C) +#define STM32_PWR_CR3_BYPASS BIT(0) +#define STM32_PWR_CR3_LDOEN BIT(1) +#define STM32_PWR_CR3_SCUEN BIT(2) +#define STM32_PWR_CR3_VBE BIT(8) +#define STM32_PWR_CR3_VBRS BIT(9) +#define STM32_PWR_CR3_USB33DEN BIT(24) +#define STM32_PWR_CR3_USBREGEN BIT(25) +#define STM32_PWR_CR3_USB33RDY BIT(26) +#define STM32_PWR_CPUCR REG32(STM32_PWR_BASE + 0x10) +#define STM32_PWR_CPUCR_PDDS_D1 BIT(0) +#define STM32_PWR_CPUCR_PDDS_D2 BIT(1) +#define STM32_PWR_CPUCR_PDDS_D3 BIT(2) +#define STM32_PWR_CPUCR_STOPF BIT(5) +#define STM32_PWR_CPUCR_SBF BIT(6) +#define STM32_PWR_CPUCR_SBF_D1 BIT(7) +#define STM32_PWR_CPUCR_SBF_D2 BIT(8) +#define STM32_PWR_CPUCR_CSSF BIT(9) +#define STM32_PWR_CPUCR_RUN_D3 BIT(11) +#define STM32_PWR_D3CR REG32(STM32_PWR_BASE + 0x18) +#define STM32_PWR_D3CR_VOS1 (3 << 14) +#define STM32_PWR_D3CR_VOS2 (2 << 14) +#define STM32_PWR_D3CR_VOS3 (1 << 14) +#define STM32_PWR_D3CR_VOSMASK (3 << 14) +#define STM32_PWR_D3CR_VOSRDY (1 << 13) +#define STM32_PWR_WKUPCR REG32(STM32_PWR_BASE + 0x20) +#define STM32_PWR_WKUPFR REG32(STM32_PWR_BASE + 0x24) +#define STM32_PWR_WKUPEPR REG32(STM32_PWR_BASE + 0x28) + +#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x000) +#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x004) +#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x008) +#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x010) +#define STM32_RCC_D1CFGR REG32(STM32_RCC_BASE + 0x018) +#define STM32_RCC_D2CFGR REG32(STM32_RCC_BASE + 0x01C) +#define STM32_RCC_D3CFGR REG32(STM32_RCC_BASE + 0x020) +#define STM32_RCC_PLLCKSELR REG32(STM32_RCC_BASE + 0x028) +#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x02C) +#define STM32_RCC_PLL1DIVR REG32(STM32_RCC_BASE + 0x030) +#define STM32_RCC_PLL1FRACR REG32(STM32_RCC_BASE + 0x034) +#define STM32_RCC_PLL2DIVR REG32(STM32_RCC_BASE + 0x038) +#define STM32_RCC_PLL2FRACR REG32(STM32_RCC_BASE + 0x03C) +#define STM32_RCC_PLL3DIVR REG32(STM32_RCC_BASE + 0x040) +#define STM32_RCC_PLL3FRACR REG32(STM32_RCC_BASE + 0x044) +#define STM32_RCC_D1CCIPR REG32(STM32_RCC_BASE + 0x04C) +#define STM32_RCC_D2CCIP1R REG32(STM32_RCC_BASE + 0x050) +#define STM32_RCC_D2CCIP2R REG32(STM32_RCC_BASE + 0x054) +#define STM32_RCC_D3CCIPR REG32(STM32_RCC_BASE + 0x058) +#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x060) +#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x064) +#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x068) +#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x070) +#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x074) + +#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x098) + +#define STM32_RCC_RSR REG32(STM32_RCC_BASE + 0x0D0) +#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x0D4) +#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x0D8) +#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x0DC) +#define STM32_RCC_AHB2ENR_RNGEN BIT(6) +#define STM32_RCC_AHB2ENR_HASHEN BIT(5) +#define STM32_RCC_AHB2ENR_CRYPTEN BIT(4) +#define STM32_RCC_AHB4ENR REG32(STM32_RCC_BASE + 0x0E0) +#define STM32_RCC_AHB4ENR_GPIOMASK 0x3ff +#define STM32_RCC_APB3ENR REG32(STM32_RCC_BASE + 0x0E4) +#define STM32_RCC_APB1LENR REG32(STM32_RCC_BASE + 0x0E8) +#define STM32_RCC_APB1HENR REG32(STM32_RCC_BASE + 0x0EC) +#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x0F0) +#define STM32_RCC_APB4ENR REG32(STM32_RCC_BASE + 0x0F4) +#define STM32_RCC_SYSCFGEN BIT(1) +#define STM32_RCC_AHB3LPENR REG32(STM32_RCC_BASE + 0x0FC) +#define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x100) +#define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x104) +#define STM32_RCC_AHB4LPENR REG32(STM32_RCC_BASE + 0x108) +#define STM32_RCC_APB3LPENR REG32(STM32_RCC_BASE + 0x10C) +#define STM32_RCC_APB1LLPENR REG32(STM32_RCC_BASE + 0x110) +#define STM32_RCC_APB1HLPENR REG32(STM32_RCC_BASE + 0x114) +#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x118) +#define STM32_RCC_APB4LPENR REG32(STM32_RCC_BASE + 0x11C) /* Aliases */ -#define STM32_RCC_APB1ENR STM32_RCC_APB1LENR - -#define STM32_RCC_CR_HSION BIT(0) -#define STM32_RCC_CR_HSIRDY BIT(2) -#define STM32_RCC_CR_CSION BIT(7) -#define STM32_RCC_CR_CSIRDY BIT(8) -#define STM32_RCC_CR_HSI48ON BIT(12) -#define STM32_RCC_CR_HSI48RDY BIT(13) -#define STM32_RCC_CR_PLL1ON BIT(24) -#define STM32_RCC_CR_PLL1RDY BIT(25) -#define STM32_RCC_CR_PLL2ON BIT(26) -#define STM32_RCC_CR_PLL2RDY BIT(27) -#define STM32_RCC_CR_PLL3ON BIT(28) -#define STM32_RCC_CR_PLL3RDY BIT(29) -#define STM32_RCC_CFGR_SW_HSI (0 << 0) -#define STM32_RCC_CFGR_SW_CSI (1 << 0) -#define STM32_RCC_CFGR_SW_HSE (2 << 0) -#define STM32_RCC_CFGR_SW_PLL1 (3 << 0) -#define STM32_RCC_CFGR_SW_MASK (3 << 0) -#define STM32_RCC_CFGR_SWS_HSI (0 << 3) -#define STM32_RCC_CFGR_SWS_CSI (1 << 3) -#define STM32_RCC_CFGR_SWS_HSE (2 << 3) -#define STM32_RCC_CFGR_SWS_PLL1 (3 << 3) -#define STM32_RCC_CFGR_SWS_MASK (3 << 3) -#define STM32_RCC_D1CFGR_HPRE_DIV1 (0 << 0) -#define STM32_RCC_D1CFGR_HPRE_DIV2 (8 << 0) -#define STM32_RCC_D1CFGR_HPRE_DIV4 (9 << 0) -#define STM32_RCC_D1CFGR_HPRE_DIV8 (10 << 0) -#define STM32_RCC_D1CFGR_HPRE_DIV16 (11 << 0) -#define STM32_RCC_D1CFGR_D1PPRE_DIV1 (0 << 4) -#define STM32_RCC_D1CFGR_D1PPRE_DIV2 (4 << 4) -#define STM32_RCC_D1CFGR_D1PPRE_DIV4 (5 << 4) -#define STM32_RCC_D1CFGR_D1PPRE_DIV8 (6 << 4) -#define STM32_RCC_D1CFGR_D1PPRE_DIV16 (7 << 4) -#define STM32_RCC_D1CFGR_D1CPRE_DIV1 (0 << 8) -#define STM32_RCC_D1CFGR_D1CPRE_DIV2 (8 << 8) -#define STM32_RCC_D1CFGR_D1CPRE_DIV4 (9 << 8) -#define STM32_RCC_D1CFGR_D1CPRE_DIV8 (10 << 8) -#define STM32_RCC_D1CFGR_D1CPRE_DIV16 (1BIT(8)) -#define STM32_RCC_PLLCKSEL_PLLSRC_HSI (0 << 0) -#define STM32_RCC_PLLCKSEL_PLLSRC_CSI (1 << 0) -#define STM32_RCC_PLLCKSEL_PLLSRC_HSE (2 << 0) -#define STM32_RCC_PLLCKSEL_PLLSRC_NONE (3 << 0) -#define STM32_RCC_PLLCKSEL_PLLSRC_MASK (3 << 0) -#define STM32_RCC_PLLCKSEL_DIVM1(m) ((m) << 4) -#define STM32_RCC_PLLCKSEL_DIVM2(m) ((m) << 12) -#define STM32_RCC_PLLCKSEL_DIVM3(m) ((m) << 20) -#define STM32_RCC_PLLCFG_PLL1VCOSEL_FRACEN BIT(0) -#define STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE (0 << 1) -#define STM32_RCC_PLLCFG_PLL1VCOSEL_MEDIUM BIT(1) -#define STM32_RCC_PLLCFG_PLL1RGE_1M_2M (0 << 2) -#define STM32_RCC_PLLCFG_PLL1RGE_2M_4M (1 << 2) -#define STM32_RCC_PLLCFG_PLL1RGE_4M_8M (2 << 2) -#define STM32_RCC_PLLCFG_PLL1RGE_8M_16M (3 << 2) -#define STM32_RCC_PLLCFG_DIVP1EN BIT(16) -#define STM32_RCC_PLLCFG_DIVQ1EN BIT(17) -#define STM32_RCC_PLLCFG_DIVR1EN BIT(18) -#define STM32_RCC_PLLDIV_DIVN(n) (((n) - 1) << 0) -#define STM32_RCC_PLLDIV_DIVP(p) (((p) - 1) << 9) -#define STM32_RCC_PLLDIV_DIVQ(q) (((q) - 1) << 16) -#define STM32_RCC_PLLDIV_DIVR(r) (((r) - 1) << 24) -#define STM32_RCC_PLLFRAC(n) ((n) << 3) -#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL1Q (0 << 12) -#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL2P (1 << 12) -#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL3P (2 << 12) -#define STM32_RCC_D2CCIP1R_SPI123SEL_I2SCKIN (3 << 12) -#define STM32_RCC_D2CCIP1R_SPI123SEL_PERCK (4 << 12) -#define STM32_RCC_D2CCIP1R_SPI123SEL_MASK (7 << 12) -#define STM32_RCC_D2CCIP1R_SPI45SEL_APB (0 << 16) -#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL2Q (1 << 16) -#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL3Q (2 << 16) -#define STM32_RCC_D2CCIP1R_SPI45SEL_HSI (3 << 16) -#define STM32_RCC_D2CCIP1R_SPI45SEL_CSI (4 << 16) -#define STM32_RCC_D2CCIP1R_SPI45SEL_HSE (5 << 16) -#define STM32_RCC_D2CCIP1R_SPI45SEL_MASK (7 << 16) -#define STM32_RCC_D2CCIP2_USART234578SEL_PCLK (0 << 0) +#define STM32_RCC_APB1ENR STM32_RCC_APB1LENR + +#define STM32_RCC_CR_HSION BIT(0) +#define STM32_RCC_CR_HSIRDY BIT(2) +#define STM32_RCC_CR_CSION BIT(7) +#define STM32_RCC_CR_CSIRDY BIT(8) +#define STM32_RCC_CR_HSI48ON BIT(12) +#define STM32_RCC_CR_HSI48RDY BIT(13) +#define STM32_RCC_CR_PLL1ON BIT(24) +#define STM32_RCC_CR_PLL1RDY BIT(25) +#define STM32_RCC_CR_PLL2ON BIT(26) +#define STM32_RCC_CR_PLL2RDY BIT(27) +#define STM32_RCC_CR_PLL3ON BIT(28) +#define STM32_RCC_CR_PLL3RDY BIT(29) +#define STM32_RCC_CFGR_SW_HSI (0 << 0) +#define STM32_RCC_CFGR_SW_CSI (1 << 0) +#define STM32_RCC_CFGR_SW_HSE (2 << 0) +#define STM32_RCC_CFGR_SW_PLL1 (3 << 0) +#define STM32_RCC_CFGR_SW_MASK (3 << 0) +#define STM32_RCC_CFGR_SWS_HSI (0 << 3) +#define STM32_RCC_CFGR_SWS_CSI (1 << 3) +#define STM32_RCC_CFGR_SWS_HSE (2 << 3) +#define STM32_RCC_CFGR_SWS_PLL1 (3 << 3) +#define STM32_RCC_CFGR_SWS_MASK (3 << 3) +#define STM32_RCC_D1CFGR_HPRE_DIV1 (0 << 0) +#define STM32_RCC_D1CFGR_HPRE_DIV2 (8 << 0) +#define STM32_RCC_D1CFGR_HPRE_DIV4 (9 << 0) +#define STM32_RCC_D1CFGR_HPRE_DIV8 (10 << 0) +#define STM32_RCC_D1CFGR_HPRE_DIV16 (11 << 0) +#define STM32_RCC_D1CFGR_D1PPRE_DIV1 (0 << 4) +#define STM32_RCC_D1CFGR_D1PPRE_DIV2 (4 << 4) +#define STM32_RCC_D1CFGR_D1PPRE_DIV4 (5 << 4) +#define STM32_RCC_D1CFGR_D1PPRE_DIV8 (6 << 4) +#define STM32_RCC_D1CFGR_D1PPRE_DIV16 (7 << 4) +#define STM32_RCC_D1CFGR_D1CPRE_DIV1 (0 << 8) +#define STM32_RCC_D1CFGR_D1CPRE_DIV2 (8 << 8) +#define STM32_RCC_D1CFGR_D1CPRE_DIV4 (9 << 8) +#define STM32_RCC_D1CFGR_D1CPRE_DIV8 (10 << 8) +#define STM32_RCC_D1CFGR_D1CPRE_DIV16 (1BIT(8)) +#define STM32_RCC_PLLCKSEL_PLLSRC_HSI (0 << 0) +#define STM32_RCC_PLLCKSEL_PLLSRC_CSI (1 << 0) +#define STM32_RCC_PLLCKSEL_PLLSRC_HSE (2 << 0) +#define STM32_RCC_PLLCKSEL_PLLSRC_NONE (3 << 0) +#define STM32_RCC_PLLCKSEL_PLLSRC_MASK (3 << 0) +#define STM32_RCC_PLLCKSEL_DIVM1(m) ((m) << 4) +#define STM32_RCC_PLLCKSEL_DIVM2(m) ((m) << 12) +#define STM32_RCC_PLLCKSEL_DIVM3(m) ((m) << 20) +#define STM32_RCC_PLLCFG_PLL1VCOSEL_FRACEN BIT(0) +#define STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE (0 << 1) +#define STM32_RCC_PLLCFG_PLL1VCOSEL_MEDIUM BIT(1) +#define STM32_RCC_PLLCFG_PLL1RGE_1M_2M (0 << 2) +#define STM32_RCC_PLLCFG_PLL1RGE_2M_4M (1 << 2) +#define STM32_RCC_PLLCFG_PLL1RGE_4M_8M (2 << 2) +#define STM32_RCC_PLLCFG_PLL1RGE_8M_16M (3 << 2) +#define STM32_RCC_PLLCFG_DIVP1EN BIT(16) +#define STM32_RCC_PLLCFG_DIVQ1EN BIT(17) +#define STM32_RCC_PLLCFG_DIVR1EN BIT(18) +#define STM32_RCC_PLLDIV_DIVN(n) (((n)-1) << 0) +#define STM32_RCC_PLLDIV_DIVP(p) (((p)-1) << 9) +#define STM32_RCC_PLLDIV_DIVQ(q) (((q)-1) << 16) +#define STM32_RCC_PLLDIV_DIVR(r) (((r)-1) << 24) +#define STM32_RCC_PLLFRAC(n) ((n) << 3) +#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL1Q (0 << 12) +#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL2P (1 << 12) +#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL3P (2 << 12) +#define STM32_RCC_D2CCIP1R_SPI123SEL_I2SCKIN (3 << 12) +#define STM32_RCC_D2CCIP1R_SPI123SEL_PERCK (4 << 12) +#define STM32_RCC_D2CCIP1R_SPI123SEL_MASK (7 << 12) +#define STM32_RCC_D2CCIP1R_SPI45SEL_APB (0 << 16) +#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL2Q (1 << 16) +#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL3Q (2 << 16) +#define STM32_RCC_D2CCIP1R_SPI45SEL_HSI (3 << 16) +#define STM32_RCC_D2CCIP1R_SPI45SEL_CSI (4 << 16) +#define STM32_RCC_D2CCIP1R_SPI45SEL_HSE (5 << 16) +#define STM32_RCC_D2CCIP1R_SPI45SEL_MASK (7 << 16) +#define STM32_RCC_D2CCIP2_USART234578SEL_PCLK (0 << 0) #define STM32_RCC_D2CCIP2_USART234578SEL_PLL2Q (1 << 0) #define STM32_RCC_D2CCIP2_USART234578SEL_PLL3Q (2 << 0) -#define STM32_RCC_D2CCIP2_USART234578SEL_HSI (3 << 0) -#define STM32_RCC_D2CCIP2_USART234578SEL_CSI (4 << 0) -#define STM32_RCC_D2CCIP2_USART234578SEL_LSE (5 << 0) -#define STM32_RCC_D2CCIP2_USART234578SEL_MASK (7 << 0) -#define STM32_RCC_D2CCIP2_USART16SEL_PCLK (0 << 3) -#define STM32_RCC_D2CCIP2_USART16SEL_PLL2Q (1 << 3) -#define STM32_RCC_D2CCIP2_USART16SEL_PLL3Q (2 << 3) -#define STM32_RCC_D2CCIP2_USART16SEL_HSI (3 << 3) -#define STM32_RCC_D2CCIP2_USART16SEL_CSI (4 << 3) -#define STM32_RCC_D2CCIP2_USART16SEL_LSE (5 << 3) -#define STM32_RCC_D2CCIP2_USART16SEL_MASK (7 << 3) -#define STM32_RCC_D2CCIP2_RNGSEL_HSI48 (0 << 8) -#define STM32_RCC_D2CCIP2_RNGSEL_PLL1Q (1 << 8) -#define STM32_RCC_D2CCIP2_RNGSEL_LSE (2 << 8) -#define STM32_RCC_D2CCIP2_RNGSEL_LSI (3 << 8) -#define STM32_RCC_D2CCIP2_RNGSEL_MASK (3 << 8) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_PCLK (0 << 28) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_PLL2 (1 << 28) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_PLL3 (2 << 28) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_LSE (3 << 28) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_LSI (4 << 28) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_PER (5 << 28) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_MASK (7 << 28) -#define STM32_RCC_CSR_LSION BIT(0) -#define STM32_RCC_CSR_LSIRDY BIT(1) - -#define STM32_SYSCFG_PMCR REG32(STM32_SYSCFG_BASE + 0x04) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) +#define STM32_RCC_D2CCIP2_USART234578SEL_HSI (3 << 0) +#define STM32_RCC_D2CCIP2_USART234578SEL_CSI (4 << 0) +#define STM32_RCC_D2CCIP2_USART234578SEL_LSE (5 << 0) +#define STM32_RCC_D2CCIP2_USART234578SEL_MASK (7 << 0) +#define STM32_RCC_D2CCIP2_USART16SEL_PCLK (0 << 3) +#define STM32_RCC_D2CCIP2_USART16SEL_PLL2Q (1 << 3) +#define STM32_RCC_D2CCIP2_USART16SEL_PLL3Q (2 << 3) +#define STM32_RCC_D2CCIP2_USART16SEL_HSI (3 << 3) +#define STM32_RCC_D2CCIP2_USART16SEL_CSI (4 << 3) +#define STM32_RCC_D2CCIP2_USART16SEL_LSE (5 << 3) +#define STM32_RCC_D2CCIP2_USART16SEL_MASK (7 << 3) +#define STM32_RCC_D2CCIP2_RNGSEL_HSI48 (0 << 8) +#define STM32_RCC_D2CCIP2_RNGSEL_PLL1Q (1 << 8) +#define STM32_RCC_D2CCIP2_RNGSEL_LSE (2 << 8) +#define STM32_RCC_D2CCIP2_RNGSEL_LSI (3 << 8) +#define STM32_RCC_D2CCIP2_RNGSEL_MASK (3 << 8) +#define STM32_RCC_D2CCIP2_LPTIM1SEL_PCLK (0 << 28) +#define STM32_RCC_D2CCIP2_LPTIM1SEL_PLL2 (1 << 28) +#define STM32_RCC_D2CCIP2_LPTIM1SEL_PLL3 (2 << 28) +#define STM32_RCC_D2CCIP2_LPTIM1SEL_LSE (3 << 28) +#define STM32_RCC_D2CCIP2_LPTIM1SEL_LSI (4 << 28) +#define STM32_RCC_D2CCIP2_LPTIM1SEL_PER (5 << 28) +#define STM32_RCC_D2CCIP2_LPTIM1SEL_MASK (7 << 28) +#define STM32_RCC_CSR_LSION BIT(0) +#define STM32_RCC_CSR_LSIRDY BIT(1) + +#define STM32_SYSCFG_PMCR REG32(STM32_SYSCFG_BASE + 0x04) +#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) /* Peripheral bits for APB1ENR regs */ -#define STM32_RCC_PB1_LPTIM1 BIT(9) +#define STM32_RCC_PB1_LPTIM1 BIT(9) /* Peripheral bits for APB2ENR regs */ -#define STM32_RCC_PB2_TIM1 BIT(0) -#define STM32_RCC_PB2_TIM2 BIT(1) -#define STM32_RCC_PB2_USART1 BIT(4) -#define STM32_RCC_PB2_SPI1 BIT(12) -#define STM32_RCC_PB2_SPI4 BIT(13) -#define STM32_RCC_PB2_TIM15 BIT(16) -#define STM32_RCC_PB2_TIM16 BIT(17) -#define STM32_RCC_PB2_TIM17 BIT(18) +#define STM32_RCC_PB2_TIM1 BIT(0) +#define STM32_RCC_PB2_TIM2 BIT(1) +#define STM32_RCC_PB2_USART1 BIT(4) +#define STM32_RCC_PB2_SPI1 BIT(12) +#define STM32_RCC_PB2_SPI4 BIT(13) +#define STM32_RCC_PB2_TIM15 BIT(16) +#define STM32_RCC_PB2_TIM16 BIT(17) +#define STM32_RCC_PB2_TIM17 BIT(18) /* Peripheral bits for AHB1/2/3/4ENR regs */ -#define STM32_RCC_HB1_DMA1 BIT(0) -#define STM32_RCC_HB1_DMA2 BIT(1) -#define STM32_RCC_HB3_MDMA BIT(0) -#define STM32_RCC_HB4_BDMA BIT(21) - +#define STM32_RCC_HB1_DMA1 BIT(0) +#define STM32_RCC_HB1_DMA2 BIT(1) +#define STM32_RCC_HB3_MDMA BIT(0) +#define STM32_RCC_HB4_BDMA BIT(21) /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB2_USART1 BIT(4) +#define STM32_RCC_PB2_USART1 BIT(4) /* Reset causes definitions */ #define STM32_RCC_RESET_CAUSE STM32_RCC_RSR -#define RESET_CAUSE_WDG (BIT(28)|BIT(26)) -#define RESET_CAUSE_SFT BIT(24) -#define RESET_CAUSE_POR BIT(23) -#define RESET_CAUSE_PIN BIT(22) -#define RESET_CAUSE_OTHER (BIT(31)|BIT(30)|BIT(29)|BIT(28)| \ - BIT(27)|BIT(26)|BIT(25)|BIT(24)| \ - BIT(23)|BIT(22)|BIT(21)|BIT(20)| \ - BIT(19)|BIT(18)|BIT(17)) -#define RESET_CAUSE_RMVF BIT(16) +#define RESET_CAUSE_WDG (BIT(28) | BIT(26)) +#define RESET_CAUSE_SFT BIT(24) +#define RESET_CAUSE_POR BIT(23) +#define RESET_CAUSE_PIN BIT(22) +#define RESET_CAUSE_OTHER \ + (BIT(31) | BIT(30) | BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25) | \ + BIT(24) | BIT(23) | BIT(22) | BIT(21) | BIT(20) | BIT(19) | BIT(18) | \ + BIT(17)) +#define RESET_CAUSE_RMVF BIT(16) /* Power cause in PWR CPUCR register (Standby&Stop modes) */ #define STM32_PWR_RESET_CAUSE STM32_PWR_CPUCR #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CPUCR -#define RESET_CAUSE_SBF BIT(6) -#define RESET_CAUSE_SBF_CLR BIT(9) +#define RESET_CAUSE_SBF BIT(6) +#define RESET_CAUSE_SBF_CLR BIT(9) /* --- Watchdogs --- */ /* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 128 +#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) +#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) +#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) +#define STM32_RTC_CR_BYPSHAD BIT(5) +#define STM32_RTC_CR_ALRAE BIT(8) +#define STM32_RTC_CR_ALRAIE BIT(12) +#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) +#define STM32_RTC_ISR_ALRAWF BIT(0) +#define STM32_RTC_ISR_RSF BIT(5) +#define STM32_RTC_ISR_INITF BIT(6) +#define STM32_RTC_ISR_INIT BIT(7) +#define STM32_RTC_ISR_ALRAF BIT(8) +#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) +#define STM32_RTC_PRER_A_MASK (0x7f << 16) +#define STM32_RTC_PRER_S_MASK (0x7fff << 0) +#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) +#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) +#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) +#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) +#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) +#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) +#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) +#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) +#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) +#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) +#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) + +#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) +#define STM32_BKP_BYTES 128 /* --- SPI --- */ @@ -634,163 +629,160 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) -#define STM32_SPI_CR1_SPE BIT(0) -#define STM32_SPI_CR1_CSTART BIT(9) -#define STM32_SPI_CR1_SSI BIT(12) -#define STM32_SPI_CR1_DIV(div) ((div) << 28) -#define STM32_SPI_CFG1_DATASIZE(n) (((n) - 1) << 0) -#define STM32_SPI_CFG1_FTHLV(n) (((n) - 1) << 5) -#define STM32_SPI_CFG1_UDRCFG_CONST (0 << 9) -#define STM32_SPI_CFG1_UDRCFG_LAST_RX (1 << 9) -#define STM32_SPI_CFG1_UDRCFG_LAST_TX (2 << 9) -#define STM32_SPI_CFG1_UDRDET_BEGIN_FRM (0 << 11) -#define STM32_SPI_CFG1_UDRDET_END_FRM (1 << 11) -#define STM32_SPI_CFG1_UDRDET_BEGIN_SS (2 << 11) -#define STM32_SPI_CFG1_RXDMAEN BIT(14) -#define STM32_SPI_CFG1_TXDMAEN BIT(15) -#define STM32_SPI_CFG1_CRCSIZE(n) (((n) - 1) << 16) -#define STM32_SPI_CFG2_MSTR BIT(22) -#define STM32_SPI_CFG2_SSM BIT(26) -#define STM32_SPI_CFG2_AFCNTR BIT(31) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_UDR BIT(5) -#define STM32_SPI_SR_FRLVL (3 << 13) -#define STM32_SPI_SR_TXC BIT(12) +#define STM32_SPI_CR1_SPE BIT(0) +#define STM32_SPI_CR1_CSTART BIT(9) +#define STM32_SPI_CR1_SSI BIT(12) +#define STM32_SPI_CR1_DIV(div) ((div) << 28) +#define STM32_SPI_CFG1_DATASIZE(n) (((n)-1) << 0) +#define STM32_SPI_CFG1_FTHLV(n) (((n)-1) << 5) +#define STM32_SPI_CFG1_UDRCFG_CONST (0 << 9) +#define STM32_SPI_CFG1_UDRCFG_LAST_RX (1 << 9) +#define STM32_SPI_CFG1_UDRCFG_LAST_TX (2 << 9) +#define STM32_SPI_CFG1_UDRDET_BEGIN_FRM (0 << 11) +#define STM32_SPI_CFG1_UDRDET_END_FRM (1 << 11) +#define STM32_SPI_CFG1_UDRDET_BEGIN_SS (2 << 11) +#define STM32_SPI_CFG1_RXDMAEN BIT(14) +#define STM32_SPI_CFG1_TXDMAEN BIT(15) +#define STM32_SPI_CFG1_CRCSIZE(n) (((n)-1) << 16) +#define STM32_SPI_CFG2_MSTR BIT(22) +#define STM32_SPI_CFG2_SSM BIT(26) +#define STM32_SPI_CFG2_AFCNTR BIT(31) + +#define STM32_SPI_SR_RXNE BIT(0) +#define STM32_SPI_SR_UDR BIT(5) +#define STM32_SPI_SR_FRLVL (3 << 13) +#define STM32_SPI_SR_TXC BIT(12) /* --- Debug --- */ -#define STM32_DBGMCU_APB3FZ REG32(STM32_DBGMCU_BASE + 0x34) -#define STM32_DBGMCU_APB1LFZ REG32(STM32_DBGMCU_BASE + 0x3C) -#define STM32_DBGMCU_APB1HFZ REG32(STM32_DBGMCU_BASE + 0x44) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x4C) -#define STM32_DBGMCU_APB4FZ REG32(STM32_DBGMCU_BASE + 0x54) +#define STM32_DBGMCU_APB3FZ REG32(STM32_DBGMCU_BASE + 0x34) +#define STM32_DBGMCU_APB1LFZ REG32(STM32_DBGMCU_BASE + 0x3C) +#define STM32_DBGMCU_APB1HFZ REG32(STM32_DBGMCU_BASE + 0x44) +#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x4C) +#define STM32_DBGMCU_APB4FZ REG32(STM32_DBGMCU_BASE + 0x54) /* Alias */ -#define STM32_DBGMCU_APB1FZ STM32_DBGMCU_APB1LFZ +#define STM32_DBGMCU_APB1FZ STM32_DBGMCU_APB1LFZ /* --- Flash --- */ -#define STM32_FLASH_REG(bank, offset) REG32(((bank) ? 0x100 : 0) + \ - STM32_FLASH_REGS_BASE + (offset)) +#define STM32_FLASH_REG(bank, offset) \ + REG32(((bank) ? 0x100 : 0) + STM32_FLASH_REGS_BASE + (offset)) -#define STM32_FLASH_ACR(bank) STM32_FLASH_REG(bank, 0x00) +#define STM32_FLASH_ACR(bank) STM32_FLASH_REG(bank, 0x00) #define STM32_FLASH_ACR_LATENCY_SHIFT (0) -#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) -#define STM32_FLASH_ACR_WRHIGHFREQ_85MHZ (0 << 4) +#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) +#define STM32_FLASH_ACR_WRHIGHFREQ_85MHZ (0 << 4) #define STM32_FLASH_ACR_WRHIGHFREQ_185MHZ (1 << 4) #define STM32_FLASH_ACR_WRHIGHFREQ_285MHZ (2 << 4) #define STM32_FLASH_ACR_WRHIGHFREQ_385MHZ (3 << 4) -#define STM32_FLASH_KEYR(bank) STM32_FLASH_REG(bank, 0x04) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB -#define STM32_FLASH_OPTKEYR(bank) STM32_FLASH_REG(bank, 0x08) -#define FLASH_OPTKEYR_KEY1 0x08192A3B -#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F -#define STM32_FLASH_CR(bank) STM32_FLASH_REG(bank, 0x0C) -#define FLASH_CR_LOCK BIT(0) -#define FLASH_CR_PG BIT(1) -#define FLASH_CR_SER BIT(2) -#define FLASH_CR_BER BIT(3) -#define FLASH_CR_PSIZE_BYTE (0 << 4) -#define FLASH_CR_PSIZE_HWORD (1 << 4) -#define FLASH_CR_PSIZE_WORD (2 << 4) -#define FLASH_CR_PSIZE_DWORD (3 << 4) -#define FLASH_CR_PSIZE_MASK (3 << 4) -#define FLASH_CR_FW BIT(6) -#define FLASH_CR_STRT BIT(7) -#define FLASH_CR_SNB(sec) (((sec) & 0x7) << 8) -#define FLASH_CR_SNB_MASK FLASH_CR_SNB(0x7) -#define STM32_FLASH_SR(bank) STM32_FLASH_REG(bank, 0x10) -#define FLASH_SR_BUSY BIT(0) -#define FLASH_SR_WBNE BIT(1) -#define FLASH_SR_QW BIT(2) -#define FLASH_SR_CRC_BUSY BIT(3) -#define FLASH_SR_EOP BIT(16) -#define FLASH_SR_WRPERR BIT(17) -#define FLASH_SR_PGSERR BIT(18) -#define FLASH_SR_STRBERR BIT(19) -#define FLASH_SR_INCERR BIT(21) -#define FLASH_SR_OPERR BIT(22) -#define FLASH_SR_RDPERR BIT(23) -#define FLASH_SR_RDSERR BIT(24) -#define FLASH_SR_SNECCERR BIT(25) -#define FLASH_SR_DBECCERR BIT(26) -#define FLASH_SR_CRCEND BIT(27) -#define STM32_FLASH_CCR(bank) STM32_FLASH_REG(bank, 0x14) -#define FLASH_CCR_ERR_MASK (FLASH_SR_WRPERR | FLASH_SR_PGSERR \ - | FLASH_SR_STRBERR | FLASH_SR_INCERR \ - | FLASH_SR_OPERR | FLASH_SR_RDPERR \ - | FLASH_SR_RDSERR | FLASH_SR_SNECCERR \ - | FLASH_SR_DBECCERR) -#define STM32_FLASH_OPTCR(bank) STM32_FLASH_REG(bank, 0x18) -#define FLASH_OPTCR_OPTLOCK BIT(0) -#define FLASH_OPTCR_OPTSTART BIT(1) -#define STM32_FLASH_OPTSR_CUR(bank) STM32_FLASH_REG(bank, 0x1C) -#define STM32_FLASH_OPTSR_PRG(bank) STM32_FLASH_REG(bank, 0x20) -#define FLASH_OPTSR_BUSY BIT(0) /* only in OPTSR_CUR */ -#define FLASH_OPTSR_RDP_MASK (0xFF << 8) -#define FLASH_OPTSR_RDP_LEVEL_0 (0xAA << 8) +#define STM32_FLASH_KEYR(bank) STM32_FLASH_REG(bank, 0x04) +#define FLASH_KEYR_KEY1 0x45670123 +#define FLASH_KEYR_KEY2 0xCDEF89AB +#define STM32_FLASH_OPTKEYR(bank) STM32_FLASH_REG(bank, 0x08) +#define FLASH_OPTKEYR_KEY1 0x08192A3B +#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F +#define STM32_FLASH_CR(bank) STM32_FLASH_REG(bank, 0x0C) +#define FLASH_CR_LOCK BIT(0) +#define FLASH_CR_PG BIT(1) +#define FLASH_CR_SER BIT(2) +#define FLASH_CR_BER BIT(3) +#define FLASH_CR_PSIZE_BYTE (0 << 4) +#define FLASH_CR_PSIZE_HWORD (1 << 4) +#define FLASH_CR_PSIZE_WORD (2 << 4) +#define FLASH_CR_PSIZE_DWORD (3 << 4) +#define FLASH_CR_PSIZE_MASK (3 << 4) +#define FLASH_CR_FW BIT(6) +#define FLASH_CR_STRT BIT(7) +#define FLASH_CR_SNB(sec) (((sec)&0x7) << 8) +#define FLASH_CR_SNB_MASK FLASH_CR_SNB(0x7) +#define STM32_FLASH_SR(bank) STM32_FLASH_REG(bank, 0x10) +#define FLASH_SR_BUSY BIT(0) +#define FLASH_SR_WBNE BIT(1) +#define FLASH_SR_QW BIT(2) +#define FLASH_SR_CRC_BUSY BIT(3) +#define FLASH_SR_EOP BIT(16) +#define FLASH_SR_WRPERR BIT(17) +#define FLASH_SR_PGSERR BIT(18) +#define FLASH_SR_STRBERR BIT(19) +#define FLASH_SR_INCERR BIT(21) +#define FLASH_SR_OPERR BIT(22) +#define FLASH_SR_RDPERR BIT(23) +#define FLASH_SR_RDSERR BIT(24) +#define FLASH_SR_SNECCERR BIT(25) +#define FLASH_SR_DBECCERR BIT(26) +#define FLASH_SR_CRCEND BIT(27) +#define STM32_FLASH_CCR(bank) STM32_FLASH_REG(bank, 0x14) +#define FLASH_CCR_ERR_MASK \ + (FLASH_SR_WRPERR | FLASH_SR_PGSERR | FLASH_SR_STRBERR | \ + FLASH_SR_INCERR | FLASH_SR_OPERR | FLASH_SR_RDPERR | \ + FLASH_SR_RDSERR | FLASH_SR_SNECCERR | FLASH_SR_DBECCERR) +#define STM32_FLASH_OPTCR(bank) STM32_FLASH_REG(bank, 0x18) +#define FLASH_OPTCR_OPTLOCK BIT(0) +#define FLASH_OPTCR_OPTSTART BIT(1) +#define STM32_FLASH_OPTSR_CUR(bank) STM32_FLASH_REG(bank, 0x1C) +#define STM32_FLASH_OPTSR_PRG(bank) STM32_FLASH_REG(bank, 0x20) +#define FLASH_OPTSR_BUSY BIT(0) /* only in OPTSR_CUR */ +#define FLASH_OPTSR_RDP_MASK (0xFF << 8) +#define FLASH_OPTSR_RDP_LEVEL_0 (0xAA << 8) /* RDP Level 1: Anything but 0xAA/0xCC */ -#define FLASH_OPTSR_RDP_LEVEL_1 (0x00 << 8) -#define FLASH_OPTSR_RDP_LEVEL_2 (0xCC << 8) -#define FLASH_OPTSR_RSS1 BIT(26) -#define FLASH_OPTSR_RSS2 BIT(27) -#define STM32_FLASH_OPTCCR(bank) STM32_FLASH_REG(bank, 0x24) -#define STM32_FLASH_PRAR_CUR(bank) STM32_FLASH_REG(bank, 0x28) -#define STM32_FLASH_PRAR_PRG(bank) STM32_FLASH_REG(bank, 0x2C) -#define STM32_FLASH_SCAR_CUR(bank) STM32_FLASH_REG(bank, 0x30) -#define STM32_FLASH_SCAR_PRG(bank) STM32_FLASH_REG(bank, 0x34) -#define STM32_FLASH_WPSN_CUR(bank) STM32_FLASH_REG(bank, 0x38) -#define STM32_FLASH_WPSN_PRG(bank) STM32_FLASH_REG(bank, 0x3C) -#define STM32_FLASH_BOOT_CUR(bank) STM32_FLASH_REG(bank, 0x40) -#define STM32_FLASH_BOOT_PRG(bank) STM32_FLASH_REG(bank, 0x44) -#define STM32_FLASH_CRC_CR(bank) STM32_FLASH_REG(bank, 0x50) -#define STM32_FLASH_CRC_SADDR(bank) STM32_FLASH_REG(bank, 0x54) -#define STM32_FLASH_CRC_EADDR(bank) STM32_FLASH_REG(bank, 0x58) -#define STM32_FLASH_CRC_DATA(bank) STM32_FLASH_REG(bank, 0x5C) -#define STM32_FLASH_ECC_FA(bank) STM32_FLASH_REG(bank, 0x60) +#define FLASH_OPTSR_RDP_LEVEL_1 (0x00 << 8) +#define FLASH_OPTSR_RDP_LEVEL_2 (0xCC << 8) +#define FLASH_OPTSR_RSS1 BIT(26) +#define FLASH_OPTSR_RSS2 BIT(27) +#define STM32_FLASH_OPTCCR(bank) STM32_FLASH_REG(bank, 0x24) +#define STM32_FLASH_PRAR_CUR(bank) STM32_FLASH_REG(bank, 0x28) +#define STM32_FLASH_PRAR_PRG(bank) STM32_FLASH_REG(bank, 0x2C) +#define STM32_FLASH_SCAR_CUR(bank) STM32_FLASH_REG(bank, 0x30) +#define STM32_FLASH_SCAR_PRG(bank) STM32_FLASH_REG(bank, 0x34) +#define STM32_FLASH_WPSN_CUR(bank) STM32_FLASH_REG(bank, 0x38) +#define STM32_FLASH_WPSN_PRG(bank) STM32_FLASH_REG(bank, 0x3C) +#define STM32_FLASH_BOOT_CUR(bank) STM32_FLASH_REG(bank, 0x40) +#define STM32_FLASH_BOOT_PRG(bank) STM32_FLASH_REG(bank, 0x44) +#define STM32_FLASH_CRC_CR(bank) STM32_FLASH_REG(bank, 0x50) +#define STM32_FLASH_CRC_SADDR(bank) STM32_FLASH_REG(bank, 0x54) +#define STM32_FLASH_CRC_EADDR(bank) STM32_FLASH_REG(bank, 0x58) +#define STM32_FLASH_CRC_DATA(bank) STM32_FLASH_REG(bank, 0x5C) +#define STM32_FLASH_ECC_FA(bank) STM32_FLASH_REG(bank, 0x60) /* --- External Interrupts --- */ -#define STM32_EXTI_RTSR1 REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_FTSR1 REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_SWIER1 REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_D3PMR1 REG32(STM32_EXTI_BASE + 0x0C) -#define STM32_EXTI_D3PCR1L REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_D3PCR1H REG32(STM32_EXTI_BASE + 0x14) -#define STM32_EXTI_RTSR2 REG32(STM32_EXTI_BASE + 0x20) -#define STM32_EXTI_FTSR2 REG32(STM32_EXTI_BASE + 0x24) -#define STM32_EXTI_SWIER2 REG32(STM32_EXTI_BASE + 0x28) -#define STM32_EXTI_D3PMR2 REG32(STM32_EXTI_BASE + 0x2C) -#define STM32_EXTI_D3PCR2L REG32(STM32_EXTI_BASE + 0x30) -#define STM32_EXTI_D3PCR2H REG32(STM32_EXTI_BASE + 0x34) -#define STM32_EXTI_RTSR3 REG32(STM32_EXTI_BASE + 0x40) -#define STM32_EXTI_FTSR3 REG32(STM32_EXTI_BASE + 0x44) -#define STM32_EXTI_SWIER3 REG32(STM32_EXTI_BASE + 0x48) -#define STM32_EXTI_D3PMR3 REG32(STM32_EXTI_BASE + 0x4C) -#define STM32_EXTI_D3PCR3L REG32(STM32_EXTI_BASE + 0x50) -#define STM32_EXTI_D3PCR3H REG32(STM32_EXTI_BASE + 0x54) -#define STM32_EXTI_CPUIMR1 REG32(STM32_EXTI_BASE + 0x80) -#define STM32_EXTI_CPUIER1 REG32(STM32_EXTI_BASE + 0x84) -#define STM32_EXTI_CPUPR1 REG32(STM32_EXTI_BASE + 0x88) -#define STM32_EXTI_CPUIMR2 REG32(STM32_EXTI_BASE + 0x90) -#define STM32_EXTI_CPUIER2 REG32(STM32_EXTI_BASE + 0x94) -#define STM32_EXTI_CPUPR2 REG32(STM32_EXTI_BASE + 0x98) -#define STM32_EXTI_CPUIMR3 REG32(STM32_EXTI_BASE + 0xA0) -#define STM32_EXTI_CPUIER3 REG32(STM32_EXTI_BASE + 0xA4) -#define STM32_EXTI_CPUPR3 REG32(STM32_EXTI_BASE + 0xA8) +#define STM32_EXTI_RTSR1 REG32(STM32_EXTI_BASE + 0x00) +#define STM32_EXTI_FTSR1 REG32(STM32_EXTI_BASE + 0x04) +#define STM32_EXTI_SWIER1 REG32(STM32_EXTI_BASE + 0x08) +#define STM32_EXTI_D3PMR1 REG32(STM32_EXTI_BASE + 0x0C) +#define STM32_EXTI_D3PCR1L REG32(STM32_EXTI_BASE + 0x10) +#define STM32_EXTI_D3PCR1H REG32(STM32_EXTI_BASE + 0x14) +#define STM32_EXTI_RTSR2 REG32(STM32_EXTI_BASE + 0x20) +#define STM32_EXTI_FTSR2 REG32(STM32_EXTI_BASE + 0x24) +#define STM32_EXTI_SWIER2 REG32(STM32_EXTI_BASE + 0x28) +#define STM32_EXTI_D3PMR2 REG32(STM32_EXTI_BASE + 0x2C) +#define STM32_EXTI_D3PCR2L REG32(STM32_EXTI_BASE + 0x30) +#define STM32_EXTI_D3PCR2H REG32(STM32_EXTI_BASE + 0x34) +#define STM32_EXTI_RTSR3 REG32(STM32_EXTI_BASE + 0x40) +#define STM32_EXTI_FTSR3 REG32(STM32_EXTI_BASE + 0x44) +#define STM32_EXTI_SWIER3 REG32(STM32_EXTI_BASE + 0x48) +#define STM32_EXTI_D3PMR3 REG32(STM32_EXTI_BASE + 0x4C) +#define STM32_EXTI_D3PCR3L REG32(STM32_EXTI_BASE + 0x50) +#define STM32_EXTI_D3PCR3H REG32(STM32_EXTI_BASE + 0x54) +#define STM32_EXTI_CPUIMR1 REG32(STM32_EXTI_BASE + 0x80) +#define STM32_EXTI_CPUIER1 REG32(STM32_EXTI_BASE + 0x84) +#define STM32_EXTI_CPUPR1 REG32(STM32_EXTI_BASE + 0x88) +#define STM32_EXTI_CPUIMR2 REG32(STM32_EXTI_BASE + 0x90) +#define STM32_EXTI_CPUIER2 REG32(STM32_EXTI_BASE + 0x94) +#define STM32_EXTI_CPUPR2 REG32(STM32_EXTI_BASE + 0x98) +#define STM32_EXTI_CPUIMR3 REG32(STM32_EXTI_BASE + 0xA0) +#define STM32_EXTI_CPUIER3 REG32(STM32_EXTI_BASE + 0xA4) +#define STM32_EXTI_CPUPR3 REG32(STM32_EXTI_BASE + 0xA8) /* Aliases */ -#define STM32_EXTI_IMR STM32_EXTI_CPUIMR1 -#define STM32_EXTI_EMR STM32_EXTI_CPUIMR1 -#define STM32_EXTI_RTSR STM32_EXTI_RTSR1 -#define STM32_EXTI_FTSR STM32_EXTI_FTSR1 -#define STM32_EXTI_SWIER STM32_EXTI_SWIER1 -#define STM32_EXTI_PR STM32_EXTI_CPUPR1 - +#define STM32_EXTI_IMR STM32_EXTI_CPUIMR1 +#define STM32_EXTI_EMR STM32_EXTI_CPUIMR1 +#define STM32_EXTI_RTSR STM32_EXTI_RTSR1 +#define STM32_EXTI_FTSR STM32_EXTI_FTSR1 +#define STM32_EXTI_SWIER STM32_EXTI_SWIER1 +#define STM32_EXTI_PR STM32_EXTI_CPUPR1 /* --- ADC --- */ /* --- Comparators --- */ - /* --- DMA --- */ /* * Available DMA streams, numbered from 0. @@ -879,12 +871,12 @@ enum dma_channel { /* Registers for a single stream of a DMA controller */ struct stm32_dma_stream { - uint32_t scr; /* Control */ - uint32_t sndtr; /* Number of data to transfer */ - uint32_t spar; /* Peripheral address */ - uint32_t sm0ar; /* Memory address 0 */ - uint32_t sm1ar; /* address 1 for double buffer */ - uint32_t sfcr; /* FIFO control */ + uint32_t scr; /* Control */ + uint32_t sndtr; /* Number of data to transfer */ + uint32_t spar; /* Peripheral address */ + uint32_t sm0ar; /* Memory address 0 */ + uint32_t sm1ar; /* address 1 for double buffer */ + uint32_t sfcr; /* FIFO control */ }; /* Always use stm32_dma_stream_t so volatile keyword is included! */ @@ -893,12 +885,11 @@ typedef volatile struct stm32_dma_stream stm32_dma_stream_t; /* Common code and header file must use this */ typedef stm32_dma_stream_t dma_chan_t; struct stm32_dma_regs { - uint32_t isr[2]; - uint32_t ifcr[2]; + uint32_t isr[2]; + uint32_t ifcr[2]; stm32_dma_stream_t stream[STM32_DMAS_COUNT]; }; - /* Always use stm32_dma_regs_t so volatile keyword is included! */ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; @@ -909,87 +900,85 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_DMA_REGS(channel) \ ((channel) < STM32_DMAS_COUNT ? STM32_DMA1_REGS : STM32_DMA2_REGS) -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_DMEIE BIT(1) -#define STM32_DMA_CCR_TEIE BIT(2) -#define STM32_DMA_CCR_HTIE BIT(3) -#define STM32_DMA_CCR_TCIE BIT(4) -#define STM32_DMA_CCR_PFCTRL BIT(5) -#define STM32_DMA_CCR_DIR_P2M (0 << 6) -#define STM32_DMA_CCR_DIR_M2P (1 << 6) -#define STM32_DMA_CCR_DIR_M2M (2 << 6) -#define STM32_DMA_CCR_CIRC BIT(8) -#define STM32_DMA_CCR_PINC BIT(9) -#define STM32_DMA_CCR_MINC BIT(10) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 11) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 11) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 11) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 13) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 13) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 13) -#define STM32_DMA_CCR_PINCOS BIT(15) -#define STM32_DMA_CCR_PL_LOW (0 << 16) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 16) -#define STM32_DMA_CCR_PL_HIGH (2 << 16) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 16) -#define STM32_DMA_CCR_DBM BIT(18) -#define STM32_DMA_CCR_CT BIT(19) -#define STM32_DMA_CCR_PBURST(b_len) ((((b_len) - 4) / 4) << 21) -#define STM32_DMA_CCR_MBURST(b_len) ((((b_len) - 4) / 4) << 21) -#define STM32_DMA_CCR_CHANNEL_MASK (0 << 25) -#define STM32_DMA_CCR_CHANNEL(channel) (0) -#define STM32_DMA_CCR_RSVD_MASK (0xF0100000) -#define STM32_DMA_SFCR_DMDIS BIT(2) -#define STM32_DMA_SFCR_FTH(level) (((level) - 1) << 0) - - -#define STM32_DMA_CH_LOCAL(channel) ((channel) % STM32_DMAS_COUNT) -#define STM32_DMA_CH_LH(channel) \ - ((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1) -#define STM32_DMA_CH_OFFSET(channel) \ +#define STM32_DMA_CCR_EN BIT(0) +#define STM32_DMA_CCR_DMEIE BIT(1) +#define STM32_DMA_CCR_TEIE BIT(2) +#define STM32_DMA_CCR_HTIE BIT(3) +#define STM32_DMA_CCR_TCIE BIT(4) +#define STM32_DMA_CCR_PFCTRL BIT(5) +#define STM32_DMA_CCR_DIR_P2M (0 << 6) +#define STM32_DMA_CCR_DIR_M2P (1 << 6) +#define STM32_DMA_CCR_DIR_M2M (2 << 6) +#define STM32_DMA_CCR_CIRC BIT(8) +#define STM32_DMA_CCR_PINC BIT(9) +#define STM32_DMA_CCR_MINC BIT(10) +#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 11) +#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 11) +#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 11) +#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 13) +#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 13) +#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 13) +#define STM32_DMA_CCR_PINCOS BIT(15) +#define STM32_DMA_CCR_PL_LOW (0 << 16) +#define STM32_DMA_CCR_PL_MEDIUM (1 << 16) +#define STM32_DMA_CCR_PL_HIGH (2 << 16) +#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 16) +#define STM32_DMA_CCR_DBM BIT(18) +#define STM32_DMA_CCR_CT BIT(19) +#define STM32_DMA_CCR_PBURST(b_len) ((((b_len)-4) / 4) << 21) +#define STM32_DMA_CCR_MBURST(b_len) ((((b_len)-4) / 4) << 21) +#define STM32_DMA_CCR_CHANNEL_MASK (0 << 25) +#define STM32_DMA_CCR_CHANNEL(channel) (0) +#define STM32_DMA_CCR_RSVD_MASK (0xF0100000) +#define STM32_DMA_SFCR_DMDIS BIT(2) +#define STM32_DMA_SFCR_FTH(level) (((level)-1) << 0) + +#define STM32_DMA_CH_LOCAL(channel) ((channel) % STM32_DMAS_COUNT) +#define STM32_DMA_CH_LH(channel) ((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1) +#define STM32_DMA_CH_OFFSET(channel) \ (((STM32_DMA_CH_LOCAL(channel) % 4) * 6) + \ - (((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0)) + (((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0)) #define STM32_DMA_CH_GETBITS(channel, val) \ (((val) >> STM32_DMA_CH_OFFSET(channel)) & 0x3f) -#define STM32_DMA_GET_IFCR(channel) \ - (STM32_DMA_CH_GETBITS(channel, \ - STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)])) -#define STM32_DMA_GET_ISR(channel) \ - (STM32_DMA_CH_GETBITS(channel, \ - STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)])) - -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \ - (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \ - ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel))) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \ - (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \ - ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel))) - -#define STM32_DMA_FEIF BIT(0) -#define STM32_DMA_DMEIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_HTIF BIT(4) -#define STM32_DMA_TCIF BIT(5) -#define STM32_DMA_ALL 0x3d - +#define STM32_DMA_GET_IFCR(channel) \ + (STM32_DMA_CH_GETBITS( \ + channel, \ + STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)])) +#define STM32_DMA_GET_ISR(channel) \ + (STM32_DMA_CH_GETBITS( \ + channel, \ + STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)])) + +#define STM32_DMA_SET_IFCR(channel, val) \ + (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \ + (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \ + ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&0x3f) << STM32_DMA_CH_OFFSET(channel))) +#define STM32_DMA_SET_ISR(channel, val) \ + (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \ + (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \ + ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&0x3f) << STM32_DMA_CH_OFFSET(channel))) + +#define STM32_DMA_FEIF BIT(0) +#define STM32_DMA_DMEIF BIT(2) +#define STM32_DMA_TEIF BIT(3) +#define STM32_DMA_HTIF BIT(4) +#define STM32_DMA_TCIF BIT(5) +#define STM32_DMA_ALL 0x3d /* The requests for the DMA1/DMA2 controllers are routed through DMAMUX1. */ /* DMAMUX1/2 registers */ #define DMAMUX1 0 #define DMAMUX2 1 -#define STM32_DMAMUX_BASE(n) ((n) ? STM32_DMAMUX2_BASE \ - : STM32_DMAMUX1_BASE) -#define STM32_DMAMUX_REG32(n, off) REG32(STM32_DMAMUX_BASE(n) + (off)) -#define STM2_DMAMUX_CxCR(n, x) STM32_DMAMUX_REG32(n, 4 * (x)) -#define STM2_DMAMUX_CSR(n) STM32_DMAMUX_REG32(n, 0x80) -#define STM2_DMAMUX_CFR(n) STM32_DMAMUX_REG32(n, 0x84) -#define STM2_DMAMUX_RGxCR(n, x) STM32_DMAMUX_REG32(n, 0x100 + 4 * (x)) -#define STM2_DMAMUX_RGSR(n) STM32_DMAMUX_REG32(n, 0x140) -#define STM2_DMAMUX_RGCFR(n) STM32_DMAMUX_REG32(n, 0x144) +#define STM32_DMAMUX_BASE(n) ((n) ? STM32_DMAMUX2_BASE : STM32_DMAMUX1_BASE) +#define STM32_DMAMUX_REG32(n, off) REG32(STM32_DMAMUX_BASE(n) + (off)) +#define STM2_DMAMUX_CxCR(n, x) STM32_DMAMUX_REG32(n, 4 * (x)) +#define STM2_DMAMUX_CSR(n) STM32_DMAMUX_REG32(n, 0x80) +#define STM2_DMAMUX_CFR(n) STM32_DMAMUX_REG32(n, 0x84) +#define STM2_DMAMUX_RGxCR(n, x) STM32_DMAMUX_REG32(n, 0x100 + 4 * (x)) +#define STM2_DMAMUX_RGSR(n) STM32_DMAMUX_REG32(n, 0x140) +#define STM2_DMAMUX_RGCFR(n) STM32_DMAMUX_REG32(n, 0x144) enum dmamux1_request { DMAMUX1_REQ_ADC1 = 9, @@ -1091,138 +1080,63 @@ enum dmamux1_request { }; /* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) +#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) +#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) +#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) +#define STM32_CRC_CR_RESET BIT(0) +#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) +#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) +#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) +#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) +#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) +#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) +#define STM32_CRC_CR_REV_IN_WORD (3 << 5) +#define STM32_CRC_CR_REV_OUT BIT(7) +#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) +#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) /* --- PMSE --- */ -#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) -#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) -#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) -#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) -#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) -#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) -#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) -#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x) * 4) -#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) -#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) -#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) -#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) -#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) -#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) -#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) -#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) -#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) -#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) -#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) - -/* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) +#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) +#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) +#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) +#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) +#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) +#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) +#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) +#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x)*4) +#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) +#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) +#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) +#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) +#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) +#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) +#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) +#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) +#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) +#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) +#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) /* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) +#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) +#define STM32_RNG_CR_RNGEN BIT(2) +#define STM32_RNG_CR_IE BIT(3) +#define STM32_RNG_CR_CED BIT(5) +#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) +#define STM32_RNG_SR_DRDY BIT(0) +#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) /* --- AXI interconnect --- */ /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) +#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x)) +#define WRITE_ISS_OVERRIDE BIT(1) +#define READ_ISS_OVERRIDE BIT(0) /* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) +#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) +#define STM32_UNIQUE_ID_LENGTH (3 * 4) #endif /* !__ASSEMBLER__ */ diff --git a/chip/stm32/registers-stm32l.h b/chip/stm32/registers-stm32l.h index 37b31ac302..07ead4411a 100644 --- a/chip/stm32/registers-stm32l.h +++ b/chip/stm32/registers-stm32l.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -20,401 +20,393 @@ #endif /* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_TAMPER_STAMP 2 -#define STM32_IRQ_RTC_WAKEUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#define STM32_IRQ_USB_HP 19 -#define STM32_IRQ_USB_LP 20 - -#define STM32_IRQ_ADC1 18 /* STM32L4 only */ -#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ -#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ -#define STM32_IRQ_DAC 21 -#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ - -#define STM32_IRQ_COMP 22 - -#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_LCD 24 /* STM32L15X only */ -#define STM32_IRQ_TIM15 24 /* STM32F373 only */ -#define STM32_IRQ_TIM9 25 /* STM32L15X only */ -#define STM32_IRQ_TIM16 25 /* STM32F373 only */ -#define STM32_IRQ_TIM10 26 /* STM32L15X only */ -#define STM32_IRQ_TIM17 26 /* STM32F373 only */ -#define STM32_IRQ_TIM11 27 /* STM32L15X only */ -#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_TIM3 29 -#define STM32_IRQ_TIM4 30 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ -#define STM32_IRQ_CEC 42 /* STM32F373 only */ -#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ -#define STM32_IRQ_TIM12 43 /* STM32F373 only */ -#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ -#define STM32_IRQ_TIM13 44 /* STM32F373 only */ -#define STM32_IRQ_TIM14 45 /* STM32F373 only */ -#define STM32_IRQ_TIM5 50 /* STM32F373 */ -#define STM32_IRQ_SPI3 51 /* STM32F373 */ -#define STM32_IRQ_USART4 52 /* STM32F446 only */ -#define STM32_IRQ_USART5 53 /* STM32F446 only */ -#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ -#define STM32_IRQ_TIM7 55 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ +#define STM32_IRQ_WWDG 0 +#define STM32_IRQ_PVD 1 +#define STM32_IRQ_TAMPER_STAMP 2 +#define STM32_IRQ_RTC_WAKEUP 3 +#define STM32_IRQ_FLASH 4 +#define STM32_IRQ_RCC 5 +#define STM32_IRQ_EXTI0 6 +#define STM32_IRQ_EXTI1 7 +#define STM32_IRQ_EXTI2 8 +#define STM32_IRQ_EXTI3 9 +#define STM32_IRQ_EXTI4 10 +#define STM32_IRQ_DMA_CHANNEL_1 11 +#define STM32_IRQ_DMA_CHANNEL_2 12 +#define STM32_IRQ_DMA_CHANNEL_3 13 +#define STM32_IRQ_DMA_CHANNEL_4 14 +#define STM32_IRQ_DMA_CHANNEL_5 15 +#define STM32_IRQ_DMA_CHANNEL_6 16 +#define STM32_IRQ_DMA_CHANNEL_7 17 +#define STM32_IRQ_USB_HP 19 +#define STM32_IRQ_USB_LP 20 + +#define STM32_IRQ_ADC1 18 /* STM32L4 only */ +#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ +#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ +#define STM32_IRQ_DAC 21 +#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ + +#define STM32_IRQ_COMP 22 + +#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ +#define STM32_IRQ_EXTI9_5 23 +#define STM32_IRQ_LCD 24 /* STM32L15X only */ +#define STM32_IRQ_TIM15 24 /* STM32F373 only */ +#define STM32_IRQ_TIM9 25 /* STM32L15X only */ +#define STM32_IRQ_TIM16 25 /* STM32F373 only */ +#define STM32_IRQ_TIM10 26 /* STM32L15X only */ +#define STM32_IRQ_TIM17 26 /* STM32F373 only */ +#define STM32_IRQ_TIM11 27 /* STM32L15X only */ +#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ +#define STM32_IRQ_TIM2 28 +#define STM32_IRQ_TIM3 29 +#define STM32_IRQ_TIM4 30 +#define STM32_IRQ_I2C1_EV 31 +#define STM32_IRQ_I2C1_ER 32 +#define STM32_IRQ_I2C2_EV 33 +#define STM32_IRQ_I2C2_ER 34 +#define STM32_IRQ_SPI1 35 +#define STM32_IRQ_SPI2 36 +#define STM32_IRQ_USART1 37 +#define STM32_IRQ_USART2 38 +#define STM32_IRQ_USART3 39 +#define STM32_IRQ_EXTI15_10 40 +#define STM32_IRQ_RTC_ALARM 41 +#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ +#define STM32_IRQ_CEC 42 /* STM32F373 only */ +#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ +#define STM32_IRQ_TIM12 43 /* STM32F373 only */ +#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ +#define STM32_IRQ_TIM13 44 /* STM32F373 only */ +#define STM32_IRQ_TIM14 45 /* STM32F373 only */ +#define STM32_IRQ_TIM5 50 /* STM32F373 */ +#define STM32_IRQ_SPI3 51 /* STM32F373 */ +#define STM32_IRQ_USART4 52 /* STM32F446 only */ +#define STM32_IRQ_USART5 53 /* STM32F446 only */ +#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ +#define STM32_IRQ_TIM7 55 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ /* if MISC_REMAP bits are set */ -#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ -#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ -#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ -#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ -#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ -#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ -#define STM32_IRQ_LPUART 70 /* STM32L4 only */ -#define STM32_IRQ_USART9 70 /* STM32L4 only */ -#define STM32_IRQ_USART6 71 /* STM32F446 only */ -#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ -#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ -#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ -#define STM32_IRQ_TIM19 78 /* STM32F373 only */ -#define STM32_IRQ_AES 79 /* STM32L4 only */ -#define STM32_IRQ_RNG 80 /* STM32L4 only */ -#define STM32_IRQ_FPU 81 /* STM32F373 only */ - +#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ +#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ +#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ +#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ +#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ +#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ +#define STM32_IRQ_LPUART 70 /* STM32L4 only */ +#define STM32_IRQ_USART9 70 /* STM32L4 only */ +#define STM32_IRQ_USART6 71 /* STM32F446 only */ +#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ +#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ +#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ +#define STM32_IRQ_TIM19 78 /* STM32F373 only */ +#define STM32_IRQ_AES 79 /* STM32L4 only */ +#define STM32_IRQ_RNG 80 /* STM32L4 only */ +#define STM32_IRQ_FPU 81 /* STM32F373 only */ /* To simplify code generation, define DMA channel 9..10 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 +#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 +#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 +#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 +#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 /* aliases for easier code sharing */ #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV #define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV #define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV - - /* Peripheral base addresses */ -#define STM32_ADC1_BASE 0x40012400 -#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */ - -#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ -#define STM32_CRC_BASE 0x40023000 -#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ -#define STM32_DAC_BASE 0x40007400 +#define STM32_ADC1_BASE 0x40012400 +#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */ -#define STM32_COMP_BASE 0x40007C00 +#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ +#define STM32_CRC_BASE 0x40023000 +#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ +#define STM32_DAC_BASE 0x40007400 -#define STM32_DBGMCU_BASE 0xE0042000 +#define STM32_COMP_BASE 0x40007C00 -#define STM32_DMA1_BASE 0x40026000 +#define STM32_DBGMCU_BASE 0xE0042000 -#define STM32_EXTI_BASE 0x40010400 +#define STM32_DMA1_BASE 0x40026000 -#define STM32_FLASH_REGS_BASE 0x40023c00 +#define STM32_EXTI_BASE 0x40010400 -#define STM32_GPIOA_BASE 0x40020000 -#define STM32_GPIOB_BASE 0x40020400 -#define STM32_GPIOC_BASE 0x40020800 -#define STM32_GPIOD_BASE 0x40020C00 -#define STM32_GPIOE_BASE 0x40021000 -#define STM32_GPIOF_BASE 0x40021800 /* see RM0038 table 5 */ -#define STM32_GPIOG_BASE 0x40021C00 -#define STM32_GPIOH_BASE 0x40021400 +#define STM32_FLASH_REGS_BASE 0x40023c00 -#define STM32_I2C1_BASE 0x40005400 -#define STM32_I2C2_BASE 0x40005800 -#define STM32_I2C3_BASE 0x40005C00 -#define STM32_I2C4_BASE 0x40006000 +#define STM32_GPIOA_BASE 0x40020000 +#define STM32_GPIOB_BASE 0x40020400 +#define STM32_GPIOC_BASE 0x40020800 +#define STM32_GPIOD_BASE 0x40020C00 +#define STM32_GPIOE_BASE 0x40021000 +#define STM32_GPIOF_BASE 0x40021800 /* see RM0038 table 5 */ +#define STM32_GPIOG_BASE 0x40021C00 +#define STM32_GPIOH_BASE 0x40021400 -#define STM32_IWDG_BASE 0x40003000 -#define STM32_LCD_BASE 0x40002400 +#define STM32_I2C1_BASE 0x40005400 +#define STM32_I2C2_BASE 0x40005800 +#define STM32_I2C3_BASE 0x40005C00 +#define STM32_I2C4_BASE 0x40006000 -#define STM32_OPTB_BASE 0x1ff80000 +#define STM32_IWDG_BASE 0x40003000 +#define STM32_LCD_BASE 0x40002400 -#define STM32_PMSE_BASE 0x40013400 -#define STM32_PWR_BASE 0x40007000 +#define STM32_OPTB_BASE 0x1ff80000 -#define STM32_RCC_BASE 0x40023800 +#define STM32_PMSE_BASE 0x40013400 +#define STM32_PWR_BASE 0x40007000 -#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ -#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ -#define STM32_RTC_BASE 0x40002800 +#define STM32_RCC_BASE 0x40023800 -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ +#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ +#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ +#define STM32_RTC_BASE 0x40002800 -#define STM32_SYSCFG_BASE 0x40010000 +#define STM32_SPI1_BASE 0x40013000 +#define STM32_SPI2_BASE 0x40003800 +#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ -#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM9_BASE 0x40010800 /* STM32L15X only */ -#define STM32_TIM10_BASE 0x40010C00 /* STM32L15X only */ -#define STM32_TIM11_BASE 0x40011000 /* STM32L15X only */ -#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ -#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ -#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 -#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ -#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ +#define STM32_SYSCFG_BASE 0x40010000 -#define STM32_UNIQUE_ID_BASE 0x1ffff7ac +#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ +#define STM32_TIM2_BASE 0x40000000 +#define STM32_TIM3_BASE 0x40000400 +#define STM32_TIM4_BASE 0x40000800 +#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ +#define STM32_TIM6_BASE 0x40001000 +#define STM32_TIM7_BASE 0x40001400 +#define STM32_TIM9_BASE 0x40010800 /* STM32L15X only */ +#define STM32_TIM10_BASE 0x40010C00 /* STM32L15X only */ +#define STM32_TIM11_BASE 0x40011000 /* STM32L15X only */ +#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ +#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ +#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ +#define STM32_TIM15_BASE 0x40014000 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ +#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ -#define STM32_USART1_BASE 0x40013800 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART9_BASE 0x40008000 /* LPUART */ +#define STM32_UNIQUE_ID_BASE 0x1ffff7ac -#define STM32_USB_CAN_SRAM_BASE 0x40006000 -#define STM32_USB_FS_BASE 0x40005C00 +#define STM32_USART1_BASE 0x40013800 +#define STM32_USART2_BASE 0x40004400 +#define STM32_USART3_BASE 0x40004800 +#define STM32_USART4_BASE 0x40004c00 +#define STM32_USART9_BASE 0x40008000 /* LPUART */ -#define STM32_WWDG_BASE 0x40002C00 +#define STM32_USB_CAN_SRAM_BASE 0x40006000 +#define STM32_USB_FS_BASE 0x40005C00 +#define STM32_WWDG_BASE 0x40002C00 #ifndef __ASSEMBLER__ /* Register definitions */ /* --- USART --- */ -#define STM32_USART_SR(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) -#define STM32_USART_DR(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_UE BIT(13) -#define STM32_USART_CR1_OVER8 BIT(15) /* STM32L only */ -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) /* STM32L only */ -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x18) +#define STM32_USART_SR(base) STM32_USART_REG(base, 0x00) +#define STM32_USART_SR_ORE BIT(3) +#define STM32_USART_SR_RXNE BIT(5) +#define STM32_USART_SR_TC BIT(6) +#define STM32_USART_SR_TXE BIT(7) +#define STM32_USART_DR(base) STM32_USART_REG(base, 0x04) +#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x08) +#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x0C) +#define STM32_USART_CR1_RE BIT(2) +#define STM32_USART_CR1_TE BIT(3) +#define STM32_USART_CR1_RXNEIE BIT(5) +#define STM32_USART_CR1_TCIE BIT(6) +#define STM32_USART_CR1_TXEIE BIT(7) +#define STM32_USART_CR1_PS BIT(9) +#define STM32_USART_CR1_PCE BIT(10) +#define STM32_USART_CR1_M BIT(12) +#define STM32_USART_CR1_UE BIT(13) +#define STM32_USART_CR1_OVER8 BIT(15) /* STM32L only */ +#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x10) +#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x14) +#define STM32_USART_CR3_EIE BIT(0) +#define STM32_USART_CR3_DMAR BIT(6) +#define STM32_USART_CR3_DMAT BIT(7) +#define STM32_USART_CR3_ONEBIT BIT(11) /* STM32L only */ +#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x18) /* register aliases */ -#define STM32_USART_TDR(base) STM32_USART_DR(base) -#define STM32_USART_RDR(base) STM32_USART_DR(base) +#define STM32_USART_TDR(base) STM32_USART_DR(base) +#define STM32_USART_RDR(base) STM32_USART_DR(base) /* --- GPIO --- */ - -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) - -#define GPIO_ALT_SYS 0x0 -#define GPIO_ALT_TIM2 0x1 -#define GPIO_ALT_TIM3_4 0x2 -#define GPIO_ALT_TIM9_11 0x3 -#define GPIO_ALT_I2C 0x4 -#define GPIO_ALT_SPI 0x5 -#define GPIO_ALT_SPI3 0x6 -#define GPIO_ALT_USART 0x7 -#define GPIO_ALT_I2C_23 0x9 -#define GPIO_ALT_USB 0xA -#define GPIO_ALT_LCD 0xB -#define GPIO_ALT_RI 0xE -#define GPIO_ALT_EVENTOUT 0xF +#define STM32_GPIO_MODER(b) REG32((b) + 0x00) +#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) +#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) +#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) +#define STM32_GPIO_IDR(b) REG16((b) + 0x10) +#define STM32_GPIO_ODR(b) REG16((b) + 0x14) +#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) +#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) +#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) +#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) + +#define GPIO_ALT_SYS 0x0 +#define GPIO_ALT_TIM2 0x1 +#define GPIO_ALT_TIM3_4 0x2 +#define GPIO_ALT_TIM9_11 0x3 +#define GPIO_ALT_I2C 0x4 +#define GPIO_ALT_SPI 0x5 +#define GPIO_ALT_SPI3 0x6 +#define GPIO_ALT_USART 0x7 +#define GPIO_ALT_I2C_23 0x9 +#define GPIO_ALT_USB 0xA +#define GPIO_ALT_LCD 0xB +#define GPIO_ALT_RI 0xE +#define GPIO_ALT_EVENTOUT 0xF /* --- I2C --- */ -#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_START BIT(8) -#define STM32_I2C_CR1_STOP BIT(9) -#define STM32_I2C_CR1_ACK BIT(10) -#define STM32_I2C_CR1_POS BIT(11) -#define STM32_I2C_CR1_SWRST BIT(15) -#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_ITERREN BIT(8) -#define STM32_I2C_CR2_ITEVTEN BIT(9) -#define STM32_I2C_CR2_ITBUFEN BIT(10) -#define STM32_I2C_CR2_DMAEN BIT(11) -#define STM32_I2C_CR2_LAST BIT(12) -#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR1_B14 BIT(14) -#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_OAR2_ENDUAL BIT(0) -#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_SR1_SB BIT(0) -#define STM32_I2C_SR1_ADDR BIT(1) -#define STM32_I2C_SR1_BTF BIT(2) -#define STM32_I2C_SR1_STOPF BIT(4) -#define STM32_I2C_SR1_RXNE BIT(6) -#define STM32_I2C_SR1_TXE BIT(7) -#define STM32_I2C_SR1_BERR BIT(8) -#define STM32_I2C_SR1_ARLO BIT(9) -#define STM32_I2C_SR1_AF BIT(10) - -#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_SR2_BUSY BIT(1) -#define STM32_I2C_SR2_TRA BIT(2) -#define STM32_I2C_SR2_DUALF BIT(7) - -#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_CCR_DUTY BIT(14) -#define STM32_I2C_CCR_FM BIT(15) -#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) - +#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) +#define STM32_I2C_CR1_PE BIT(0) +#define STM32_I2C_CR1_START BIT(8) +#define STM32_I2C_CR1_STOP BIT(9) +#define STM32_I2C_CR1_ACK BIT(10) +#define STM32_I2C_CR1_POS BIT(11) +#define STM32_I2C_CR1_SWRST BIT(15) +#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04)) +#define STM32_I2C_CR2_ITERREN BIT(8) +#define STM32_I2C_CR2_ITEVTEN BIT(9) +#define STM32_I2C_CR2_ITBUFEN BIT(10) +#define STM32_I2C_CR2_DMAEN BIT(11) +#define STM32_I2C_CR2_LAST BIT(12) +#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08)) +#define STM32_I2C_OAR1_B14 BIT(14) +#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C)) +#define STM32_I2C_OAR2_ENDUAL BIT(0) +#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10)) +#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14)) +#define STM32_I2C_SR1_SB BIT(0) +#define STM32_I2C_SR1_ADDR BIT(1) +#define STM32_I2C_SR1_BTF BIT(2) +#define STM32_I2C_SR1_STOPF BIT(4) +#define STM32_I2C_SR1_RXNE BIT(6) +#define STM32_I2C_SR1_TXE BIT(7) +#define STM32_I2C_SR1_BERR BIT(8) +#define STM32_I2C_SR1_ARLO BIT(9) +#define STM32_I2C_SR1_AF BIT(10) + +#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18)) +#define STM32_I2C_SR2_BUSY BIT(1) +#define STM32_I2C_SR2_TRA BIT(2) +#define STM32_I2C_SR2_DUALF BIT(7) + +#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) +#define STM32_I2C_CCR_DUTY BIT(14) +#define STM32_I2C_CCR_FM BIT(15) +#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) /* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) - - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_CR_HSION BIT(0) -#define STM32_RCC_CR_HSIRDY BIT(1) -#define STM32_RCC_CR_MSION BIT(8) -#define STM32_RCC_CR_MSIRDY BIT(9) -#define STM32_RCC_CR_PLLON BIT(24) -#define STM32_RCC_CR_PLLRDY BIT(25) -#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) -#define STM32_RCC_ICSCR_MSIRANGE(n) ((n) << 13) -#define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4) -#define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5) -#define STM32_RCC_ICSCR_MSIRANGE_MASK STM32_RCC_ICSCR_MSIRANGE(7) -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_CFGR_SW_MSI (0 << 0) -#define STM32_RCC_CFGR_SW_HSI (1 << 0) -#define STM32_RCC_CFGR_SW_HSE (2 << 0) -#define STM32_RCC_CFGR_SW_PLL (3 << 0) -#define STM32_RCC_CFGR_SW_MASK (3 << 0) -#define STM32_RCC_CFGR_SWS_MSI (0 << 2) -#define STM32_RCC_CFGR_SWS_HSI (1 << 2) -#define STM32_RCC_CFGR_SWS_HSE (2 << 2) -#define STM32_RCC_CFGR_SWS_PLL (3 << 2) -#define STM32_RCC_CFGR_SWS_MASK (3 << 2) -#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C) -#define STM32_RCC_AHBRSTR REG32(STM32_RCC_BASE + 0x10) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x18) -#define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x1C) -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_SYSCFGEN BIT(0) - -#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x24) -#define STM32_RCC_PWREN BIT(28) - -#define STM32_RCC_AHBLPENR REG32(STM32_RCC_BASE + 0x28) -#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x2C) -#define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x34) - -#define STM32_RCC_HB_DMA1 BIT(24) -#define STM32_RCC_PB2_TIM9 BIT(2) -#define STM32_RCC_PB2_TIM10 BIT(3) -#define STM32_RCC_PB2_TIM11 BIT(4) -#define STM32_RCC_PB1_USB BIT(23) - -#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00) -#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) - +#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) + +#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) +#define STM32_RCC_CR_HSION BIT(0) +#define STM32_RCC_CR_HSIRDY BIT(1) +#define STM32_RCC_CR_MSION BIT(8) +#define STM32_RCC_CR_MSIRDY BIT(9) +#define STM32_RCC_CR_PLLON BIT(24) +#define STM32_RCC_CR_PLLRDY BIT(25) +#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) +#define STM32_RCC_ICSCR_MSIRANGE(n) ((n) << 13) +#define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4) +#define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5) +#define STM32_RCC_ICSCR_MSIRANGE_MASK STM32_RCC_ICSCR_MSIRANGE(7) +#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) +#define STM32_RCC_CFGR_SW_MSI (0 << 0) +#define STM32_RCC_CFGR_SW_HSI (1 << 0) +#define STM32_RCC_CFGR_SW_HSE (2 << 0) +#define STM32_RCC_CFGR_SW_PLL (3 << 0) +#define STM32_RCC_CFGR_SW_MASK (3 << 0) +#define STM32_RCC_CFGR_SWS_MSI (0 << 2) +#define STM32_RCC_CFGR_SWS_HSI (1 << 2) +#define STM32_RCC_CFGR_SWS_HSE (2 << 2) +#define STM32_RCC_CFGR_SWS_PLL (3 << 2) +#define STM32_RCC_CFGR_SWS_MASK (3 << 2) +#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C) +#define STM32_RCC_AHBRSTR REG32(STM32_RCC_BASE + 0x10) +#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x14) +#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x18) +#define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x1C) +#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x20) +#define STM32_RCC_SYSCFGEN BIT(0) + +#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x24) +#define STM32_RCC_PWREN BIT(28) + +#define STM32_RCC_AHBLPENR REG32(STM32_RCC_BASE + 0x28) +#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x2C) +#define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x30) +#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x34) + +#define STM32_RCC_HB_DMA1 BIT(24) +#define STM32_RCC_PB2_TIM9 BIT(2) +#define STM32_RCC_PB2_TIM10 BIT(3) +#define STM32_RCC_PB2_TIM11 BIT(4) +#define STM32_RCC_PB1_USB BIT(23) + +#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00) +#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04) +#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB2_USART1 BIT(14) +#define STM32_RCC_PB2_USART1 BIT(14) /* Reset causes definitions */ /* Reset causes in RCC CSR register */ #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG 0x60000000 -#define RESET_CAUSE_SFT 0x10000000 -#define RESET_CAUSE_POR 0x08000000 -#define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xfe000000 -#define RESET_CAUSE_RMVF 0x01000000 +#define RESET_CAUSE_WDG 0x60000000 +#define RESET_CAUSE_SFT 0x10000000 +#define RESET_CAUSE_POR 0x08000000 +#define RESET_CAUSE_PIN 0x04000000 +#define RESET_CAUSE_OTHER 0xfe000000 +#define RESET_CAUSE_RMVF 0x01000000 /* Power cause in PWR CSR register */ #define STM32_PWR_RESET_CAUSE STM32_PWR_CSR #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR -#define RESET_CAUSE_SBF 0x00000002 -#define RESET_CAUSE_SBF_CLR 0x00000004 +#define RESET_CAUSE_SBF 0x00000002 +#define RESET_CAUSE_SBF_CLR 0x00000004 /* --- Watchdogs --- */ /* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 80 +#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) +#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) +#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) +#define STM32_RTC_CR_BYPSHAD BIT(5) +#define STM32_RTC_CR_ALRAE BIT(8) +#define STM32_RTC_CR_ALRAIE BIT(12) +#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) +#define STM32_RTC_ISR_ALRAWF BIT(0) +#define STM32_RTC_ISR_RSF BIT(5) +#define STM32_RTC_ISR_INITF BIT(6) +#define STM32_RTC_ISR_INIT BIT(7) +#define STM32_RTC_ISR_ALRAF BIT(8) +#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) +#define STM32_RTC_PRER_A_MASK (0x7f << 16) +#define STM32_RTC_PRER_S_MASK (0x7fff << 0) +#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) +#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) +#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) +#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) +#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) +#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) +#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) +#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) +#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) +#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) +#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) + +#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) +#define STM32_BKP_BYTES 80 /* --- SPI --- */ @@ -431,8 +423,8 @@ struct stm32_spi_regs { unsigned crcpr; unsigned rxcrcr; unsigned txcrcr; - unsigned i2scfgr; /* STM32L only */ - unsigned i2spr; /* STM32L only */ + unsigned i2scfgr; /* STM32L only */ + unsigned i2spr; /* STM32L only */ }; /* Must be volatile, or compiler optimizes out repeated accesses */ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; @@ -442,146 +434,144 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) +#define STM32_SPI_CR1_BIDIMODE BIT(15) +#define STM32_SPI_CR1_BIDIOE BIT(14) +#define STM32_SPI_CR1_CRCEN BIT(13) +#define STM32_SPI_CR1_SSM BIT(9) +#define STM32_SPI_CR1_SSI BIT(8) +#define STM32_SPI_CR1_LSBFIRST BIT(7) +#define STM32_SPI_CR1_SPE BIT(6) +#define STM32_SPI_CR1_BR_DIV64R (5 << 3) +#define STM32_SPI_CR1_BR_DIV4R BIT(3) +#define STM32_SPI_CR1_MSTR BIT(2) +#define STM32_SPI_CR1_CPOL BIT(1) +#define STM32_SPI_CR1_CPHA BIT(0) +#define STM32_SPI_CR2_FRXTH BIT(12) +#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8) +#define STM32_SPI_CR2_TXEIE BIT(7) +#define STM32_SPI_CR2_RXNEIE BIT(6) +#define STM32_SPI_CR2_NSSP BIT(3) +#define STM32_SPI_CR2_SSOE BIT(2) +#define STM32_SPI_CR2_TXDMAEN BIT(1) +#define STM32_SPI_CR2_RXDMAEN BIT(0) + +#define STM32_SPI_SR_RXNE BIT(0) +#define STM32_SPI_SR_TXE BIT(1) +#define STM32_SPI_SR_CRCERR BIT(4) +#define STM32_SPI_SR_BSY BIT(7) +#define STM32_SPI_SR_FRLVL (3 << 9) +#define STM32_SPI_SR_FTLVL (3 << 11) /* --- Debug --- */ -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) +#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) +#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) /* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) -#define STM32_FLASH_ACR_LATENCY BIT(0) -#define STM32_FLASH_ACR_PRFTEN BIT(1) -#define STM32_FLASH_ACR_ACC64 BIT(2) -#define STM32_FLASH_PECR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define STM32_FLASH_PECR_PE_LOCK BIT(0) -#define STM32_FLASH_PECR_PRG_LOCK BIT(1) -#define STM32_FLASH_PECR_OPT_LOCK BIT(2) -#define STM32_FLASH_PECR_PROG BIT(3) -#define STM32_FLASH_PECR_ERASE BIT(9) -#define STM32_FLASH_PECR_FPRG BIT(10) -#define STM32_FLASH_PECR_OBL_LAUNCH BIT(18) -#define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define STM32_FLASH_PEKEYR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define STM32_FLASH_PEKEYR_KEY1 0x89ABCDEF -#define STM32_FLASH_PEKEYR_KEY2 0x02030405 -#define STM32_FLASH_PRGKEYR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define STM32_FLASH_PRGKEYR_KEY1 0x8C9DAEBF -#define STM32_FLASH_PRGKEYR_KEY2 0x13141516 -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define STM32_FLASH_OPTKEYR_KEY1 0xFBEAD9C8 -#define STM32_FLASH_OPTKEYR_KEY2 0x24252627 -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x18) -#define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c) -#define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20) - -#define STM32_OPTB_RDP 0x00 -#define STM32_OPTB_USER 0x04 -#define STM32_OPTB_WRP1L 0x08 -#define STM32_OPTB_WRP1H 0x0c -#define STM32_OPTB_WRP2L 0x10 -#define STM32_OPTB_WRP2H 0x14 -#define STM32_OPTB_WRP3L 0x18 -#define STM32_OPTB_WRP3H 0x1c +#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) +#define STM32_FLASH_ACR_LATENCY BIT(0) +#define STM32_FLASH_ACR_PRFTEN BIT(1) +#define STM32_FLASH_ACR_ACC64 BIT(2) +#define STM32_FLASH_PECR REG32(STM32_FLASH_REGS_BASE + 0x04) +#define STM32_FLASH_PECR_PE_LOCK BIT(0) +#define STM32_FLASH_PECR_PRG_LOCK BIT(1) +#define STM32_FLASH_PECR_OPT_LOCK BIT(2) +#define STM32_FLASH_PECR_PROG BIT(3) +#define STM32_FLASH_PECR_ERASE BIT(9) +#define STM32_FLASH_PECR_FPRG BIT(10) +#define STM32_FLASH_PECR_OBL_LAUNCH BIT(18) +#define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) +#define STM32_FLASH_PEKEYR REG32(STM32_FLASH_REGS_BASE + 0x0c) +#define STM32_FLASH_PEKEYR_KEY1 0x89ABCDEF +#define STM32_FLASH_PEKEYR_KEY2 0x02030405 +#define STM32_FLASH_PRGKEYR REG32(STM32_FLASH_REGS_BASE + 0x10) +#define STM32_FLASH_PRGKEYR_KEY1 0x8C9DAEBF +#define STM32_FLASH_PRGKEYR_KEY2 0x13141516 +#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x14) +#define STM32_FLASH_OPTKEYR_KEY1 0xFBEAD9C8 +#define STM32_FLASH_OPTKEYR_KEY2 0x24252627 +#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x18) +#define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c) +#define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20) + +#define STM32_OPTB_RDP 0x00 +#define STM32_OPTB_USER 0x04 +#define STM32_OPTB_WRP1L 0x08 +#define STM32_OPTB_WRP1H 0x0c +#define STM32_OPTB_WRP2L 0x10 +#define STM32_OPTB_WRP2H 0x14 +#define STM32_OPTB_WRP3L 0x18 +#define STM32_OPTB_WRP3H 0x1c /* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) - +#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) +#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) +#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) +#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) +#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) +#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) /* --- ADC --- */ -#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) -#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) -#define STM32_ADC_SMPR3 REG32(STM32_ADC1_BASE + 0x14) -#define STM32_ADC_JOFR1 REG32(STM32_ADC1_BASE + 0x18) -#define STM32_ADC_JOFR2 REG32(STM32_ADC1_BASE + 0x1C) -#define STM32_ADC_JOFR3 REG32(STM32_ADC1_BASE + 0x20) -#define STM32_ADC_JOFR4 REG32(STM32_ADC1_BASE + 0x24) -#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x2C) -#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x2C + (n) * 4) -#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x30) -#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x34) -#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x38) -#define STM32_ADC_SQR4 REG32(STM32_ADC1_BASE + 0x3C) -#define STM32_ADC_SQR5 REG32(STM32_ADC1_BASE + 0x40) -#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x44) -#define STM32_ADC_JDR1 REG32(STM32_ADC1_BASE + 0x48) -#define STM32_ADC_JDR2 REG32(STM32_ADC1_BASE + 0x4C) -#define STM32_ADC_JDR3 REG32(STM32_ADC1_BASE + 0x50) -#define STM32_ADC_JDR3 REG32(STM32_ADC1_BASE + 0x50) -#define STM32_ADC_JDR4 REG32(STM32_ADC1_BASE + 0x54) -#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x58) -#define STM32_ADC_SMPR0 REG32(STM32_ADC1_BASE + 0x5C) - -#define STM32_ADC_CCR REG32(STM32_ADC_BASE + 0x04) +#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) +#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) +#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) +#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) +#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) +#define STM32_ADC_SMPR3 REG32(STM32_ADC1_BASE + 0x14) +#define STM32_ADC_JOFR1 REG32(STM32_ADC1_BASE + 0x18) +#define STM32_ADC_JOFR2 REG32(STM32_ADC1_BASE + 0x1C) +#define STM32_ADC_JOFR3 REG32(STM32_ADC1_BASE + 0x20) +#define STM32_ADC_JOFR4 REG32(STM32_ADC1_BASE + 0x24) +#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x28) +#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x2C) +#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x2C + (n)*4) +#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x30) +#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x34) +#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x38) +#define STM32_ADC_SQR4 REG32(STM32_ADC1_BASE + 0x3C) +#define STM32_ADC_SQR5 REG32(STM32_ADC1_BASE + 0x40) +#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x44) +#define STM32_ADC_JDR1 REG32(STM32_ADC1_BASE + 0x48) +#define STM32_ADC_JDR2 REG32(STM32_ADC1_BASE + 0x4C) +#define STM32_ADC_JDR3 REG32(STM32_ADC1_BASE + 0x50) +#define STM32_ADC_JDR3 REG32(STM32_ADC1_BASE + 0x50) +#define STM32_ADC_JDR4 REG32(STM32_ADC1_BASE + 0x54) +#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x58) +#define STM32_ADC_SMPR0 REG32(STM32_ADC1_BASE + 0x5C) + +#define STM32_ADC_CCR REG32(STM32_ADC_BASE + 0x04) /* --- Comparators --- */ -#define STM32_COMP_CSR REG32(STM32_COMP_BASE + 0x00) - -#define STM32_COMP_OUTSEL_TIM2_IC4 (0 << 21) -#define STM32_COMP_OUTSEL_TIM2_OCR (1 << 21) -#define STM32_COMP_OUTSEL_TIM3_IC4 (2 << 21) -#define STM32_COMP_OUTSEL_TIM3_OCR (3 << 21) -#define STM32_COMP_OUTSEL_TIM4_IC4 (4 << 21) -#define STM32_COMP_OUTSEL_TIM4_OCR (5 << 21) +#define STM32_COMP_CSR REG32(STM32_COMP_BASE + 0x00) + +#define STM32_COMP_OUTSEL_TIM2_IC4 (0 << 21) +#define STM32_COMP_OUTSEL_TIM2_OCR (1 << 21) +#define STM32_COMP_OUTSEL_TIM3_IC4 (2 << 21) +#define STM32_COMP_OUTSEL_TIM3_OCR (3 << 21) +#define STM32_COMP_OUTSEL_TIM4_IC4 (4 << 21) +#define STM32_COMP_OUTSEL_TIM4_OCR (5 << 21) #define STM32_COMP_OUTSEL_TIM10_IC1 (6 << 21) -#define STM32_COMP_OUTSEL_NONE (7 << 21) - -#define STM32_COMP_INSEL_NONE (0 << 18) -#define STM32_COMP_INSEL_PB3 (1 << 18) -#define STM32_COMP_INSEL_VREF (2 << 18) -#define STM32_COMP_INSEL_VREF34 (3 << 18) -#define STM32_COMP_INSEL_VREF12 (4 << 18) -#define STM32_COMP_INSEL_VREF14 (5 << 18) -#define STM32_COMP_INSEL_DAC_OUT1 (6 << 18) -#define STM32_COMP_INSEL_DAC_OUT2 (7 << 18) - -#define STM32_COMP_WNDWE BIT(17) -#define STM32_COMP_VREFOUTEN BIT(16) -#define STM32_COMP_CMP2OUT BIT(13) -#define STM32_COMP_SPEED_FAST BIT(12) - -#define STM32_COMP_CMP1OUT BIT(7) -#define STM32_COMP_CMP1EN BIT(4) - -#define STM32_COMP_400KPD BIT(3) -#define STM32_COMP_10KPD BIT(2) -#define STM32_COMP_400KPU BIT(1) -#define STM32_COMP_10KPU BIT(0) - +#define STM32_COMP_OUTSEL_NONE (7 << 21) + +#define STM32_COMP_INSEL_NONE (0 << 18) +#define STM32_COMP_INSEL_PB3 (1 << 18) +#define STM32_COMP_INSEL_VREF (2 << 18) +#define STM32_COMP_INSEL_VREF34 (3 << 18) +#define STM32_COMP_INSEL_VREF12 (4 << 18) +#define STM32_COMP_INSEL_VREF14 (5 << 18) +#define STM32_COMP_INSEL_DAC_OUT1 (6 << 18) +#define STM32_COMP_INSEL_DAC_OUT2 (7 << 18) + +#define STM32_COMP_WNDWE BIT(17) +#define STM32_COMP_VREFOUTEN BIT(16) +#define STM32_COMP_CMP2OUT BIT(13) +#define STM32_COMP_SPEED_FAST BIT(12) + +#define STM32_COMP_CMP1OUT BIT(7) +#define STM32_COMP_CMP1EN BIT(4) + +#define STM32_COMP_400KPD BIT(3) +#define STM32_COMP_10KPD BIT(2) +#define STM32_COMP_400KPU BIT(1) +#define STM32_COMP_10KPU BIT(0) /* --- DMA --- */ @@ -642,11 +632,11 @@ enum dma_channel { /* Registers for a single channel of the DMA controller */ struct stm32_dma_chan { - uint32_t ccr; /* Control */ - uint32_t cndtr; /* Number of data to transfer */ - uint32_t cpar; /* Peripheral address */ - uint32_t cmar; /* Memory address */ - uint32_t reserved; + uint32_t ccr; /* Control */ + uint32_t cndtr; /* Number of data to transfer */ + uint32_t cpar; /* Peripheral address */ + uint32_t cmar; /* Memory address */ + uint32_t reserved; }; /* Always use stm32_dma_chan_t so volatile keyword is included! */ @@ -657,8 +647,8 @@ typedef stm32_dma_chan_t dma_chan_t; /* Registers for the DMA controller */ struct stm32_dma_regs { - uint32_t isr; - uint32_t ifcr; + uint32_t isr; + uint32_t ifcr; stm32_dma_chan_t chan[STM32_DMAC_COUNT]; }; @@ -667,205 +657,124 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - -#define STM32_DMA_CCR_CHANNEL(channel) (0) +#define STM32_DMA_CCR_CHANNEL(channel) (0) #define STM32_DMA_REGS(channel) STM32_DMA1_REGS /* Bits for DMA controller regs (isr and ifcr) */ -#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) +#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) #define STM32_DMA_ISR_MASK(channel, mask) \ ((mask) << STM32_DMA_CH_OFFSET(channel)) -#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) -#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) -#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) -#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) -#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) - -#define STM32_DMA_GIF BIT(0) -#define STM32_DMA_TCIF BIT(1) -#define STM32_DMA_HTIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_ALL 0xf - -#define STM32_DMA_GET_ISR(channel) \ - ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr = \ - ((STM32_DMA_REGS(channel)->isr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) -#define STM32_DMA_GET_IFCR(channel) \ - ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr = \ - ((STM32_DMA_REGS(channel)->ifcr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) - +#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) +#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) +#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) +#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) +#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) + +#define STM32_DMA_GIF BIT(0) +#define STM32_DMA_TCIF BIT(1) +#define STM32_DMA_HTIF BIT(2) +#define STM32_DMA_TEIF BIT(3) +#define STM32_DMA_ALL 0xf + +#define STM32_DMA_GET_ISR(channel) \ + ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) & \ + STM32_DMA_ALL) +#define STM32_DMA_SET_ISR(channel, val) \ + (STM32_DMA_REGS(channel)->isr = \ + ((STM32_DMA_REGS(channel)->isr & \ + ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) +#define STM32_DMA_GET_IFCR(channel) \ + ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) & \ + STM32_DMA_ALL) +#define STM32_DMA_SET_IFCR(channel, val) \ + (STM32_DMA_REGS(channel)->ifcr = \ + ((STM32_DMA_REGS(channel)->ifcr & \ + ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) /* Bits for DMA channel regs */ -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_TCIE BIT(1) -#define STM32_DMA_CCR_HTIE BIT(2) -#define STM32_DMA_CCR_TEIE BIT(3) -#define STM32_DMA_CCR_DIR BIT(4) -#define STM32_DMA_CCR_CIRC BIT(5) -#define STM32_DMA_CCR_PINC BIT(6) -#define STM32_DMA_CCR_MINC BIT(7) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) -#define STM32_DMA_CCR_PL_LOW (0 << 12) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) -#define STM32_DMA_CCR_PL_HIGH (2 << 12) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) -#define STM32_DMA_CCR_MEM2MEM BIT(14) - +#define STM32_DMA_CCR_EN BIT(0) +#define STM32_DMA_CCR_TCIE BIT(1) +#define STM32_DMA_CCR_HTIE BIT(2) +#define STM32_DMA_CCR_TEIE BIT(3) +#define STM32_DMA_CCR_DIR BIT(4) +#define STM32_DMA_CCR_CIRC BIT(5) +#define STM32_DMA_CCR_PINC BIT(6) +#define STM32_DMA_CCR_MINC BIT(7) +#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) +#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) +#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) +#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) +#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) +#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) +#define STM32_DMA_CCR_PL_LOW (0 << 12) +#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) +#define STM32_DMA_CCR_PL_HIGH (2 << 12) +#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) +#define STM32_DMA_CCR_MEM2MEM BIT(14) /* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) +#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) + +#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) +#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) +#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) +#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) + +#define STM32_CRC_CR_RESET BIT(0) +#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) +#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) +#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) +#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) +#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) +#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) +#define STM32_CRC_CR_REV_IN_WORD (3 << 5) +#define STM32_CRC_CR_REV_OUT BIT(7) /* --- PMSE --- */ -#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) -#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) -#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) -#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) -#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) -#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) -#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) -#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x) * 4) -#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) -#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) -#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) -#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) -#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) -#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) -#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) -#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) -#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) -#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) -#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) - -/* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) +#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) +#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) +#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) +#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) +#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) +#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) +#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) +#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x)*4) +#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) +#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) +#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) +#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) +#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) +#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) +#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) +#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) +#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) +#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) +#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) /* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) +#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) +#define STM32_RNG_CR_RNGEN BIT(2) +#define STM32_RNG_CR_IE BIT(3) +#define STM32_RNG_CR_CED BIT(5) +#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) +#define STM32_RNG_SR_DRDY BIT(0) +#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) /* --- AXI interconnect --- */ /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) +#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x)) +#define WRITE_ISS_OVERRIDE BIT(1) +#define READ_ISS_OVERRIDE BIT(0) /* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) +#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) +#define STM32_UNIQUE_ID_LENGTH (3 * 4) #endif /* !__ASSEMBLER__ */ diff --git a/chip/stm32/registers-stm32l4.h b/chip/stm32/registers-stm32l4.h index 156994cc10..b55204be5e 100644 --- a/chip/stm32/registers-stm32l4.h +++ b/chip/stm32/registers-stm32l4.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -20,364 +20,364 @@ #endif /****** STM32 specific Interrupt Numbers ********/ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD_PVM 1 -#define STM32_IRQ_TAMP_STAMP 2 -#define STM32_IRQ_RTC_WKUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#define STM32_IRQ_ADC1 18 -#define STM32_IRQ_CAN1_TX 19 -#define STM32_IRQ_CAN1_RX0 20 -#define STM32_IRQ_CAN1_RX1 21 -#define STM32_IRQ_CAN1_SCE 22 -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_TIM1_BRK_TIM15 24 -#define STM32_IRQ_TIM1_UP_TIM16 25 -#define STM32_IRQ_TIM1_TRG_COM 26 -#define STM32_IRQ_TIM1_CC 27 -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_SDMMC1 49 -#define STM32_IRQ_TIM5 50 -#define STM32_IRQ_SPI3 51 -#define STM32_IRQ_TIM6_DAC 54 -#define STM32_IRQ_TIM7 55 -#define STM32_IRQ_DMA2_CHANNEL1 56 -#define STM32_IRQ_DMA2_CHANNEL2 57 -#define STM32_IRQ_DMA2_CHANNEL3 58 -#define STM32_IRQ_DMA2_CHANNEL4 59 -#define STM32_IRQ_DMA2_CHANNEL5 60 -#define STM32_IRQ_COMP 64 -#define LSTM32_IRQ_PTIM1 65 -#define STM32_IRQ_LPTIM2 66 -#define STM32_IRQ_DMA2_CHANNEL6 68 -#define STM32_IRQ_DMA2_CHANNEL7 69 -#define STM32_IRQ_LPUART1 70 -#define STM32_IRQ_QUADSPI 71 -#define STM32_IRQ_I2C3_EV 72 -#define STM32_IRQ_I2C3_ER 73 -#define STM32_IRQ_SAI1 74 -#define STM32_IRQ_SWPMI1 76 -#define STM32_IRQ_TSC 77 -#define STM32_IRQ_RNG 80 -#define STM32_IRQ_FPU 81 -#define STM32_IRQ_CRS 82 +#define STM32_IRQ_WWDG 0 +#define STM32_IRQ_PVD_PVM 1 +#define STM32_IRQ_TAMP_STAMP 2 +#define STM32_IRQ_RTC_WKUP 3 +#define STM32_IRQ_FLASH 4 +#define STM32_IRQ_RCC 5 +#define STM32_IRQ_EXTI0 6 +#define STM32_IRQ_EXTI1 7 +#define STM32_IRQ_EXTI2 8 +#define STM32_IRQ_EXTI3 9 +#define STM32_IRQ_EXTI4 10 +#define STM32_IRQ_DMA_CHANNEL_1 11 +#define STM32_IRQ_DMA_CHANNEL_2 12 +#define STM32_IRQ_DMA_CHANNEL_3 13 +#define STM32_IRQ_DMA_CHANNEL_4 14 +#define STM32_IRQ_DMA_CHANNEL_5 15 +#define STM32_IRQ_DMA_CHANNEL_6 16 +#define STM32_IRQ_DMA_CHANNEL_7 17 +#define STM32_IRQ_ADC1 18 +#define STM32_IRQ_CAN1_TX 19 +#define STM32_IRQ_CAN1_RX0 20 +#define STM32_IRQ_CAN1_RX1 21 +#define STM32_IRQ_CAN1_SCE 22 +#define STM32_IRQ_EXTI9_5 23 +#define STM32_IRQ_TIM1_BRK_TIM15 24 +#define STM32_IRQ_TIM1_UP_TIM16 25 +#define STM32_IRQ_TIM1_TRG_COM 26 +#define STM32_IRQ_TIM1_CC 27 +#define STM32_IRQ_TIM2 28 +#define STM32_IRQ_I2C1_EV 31 +#define STM32_IRQ_I2C1_ER 32 +#define STM32_IRQ_I2C2_EV 33 +#define STM32_IRQ_I2C2_ER 34 +#define STM32_IRQ_SPI1 35 +#define STM32_IRQ_SPI2 36 +#define STM32_IRQ_USART1 37 +#define STM32_IRQ_USART2 38 +#define STM32_IRQ_USART3 39 +#define STM32_IRQ_EXTI15_10 40 +#define STM32_IRQ_RTC_ALARM 41 +#define STM32_IRQ_SDMMC1 49 +#define STM32_IRQ_TIM5 50 +#define STM32_IRQ_SPI3 51 +#define STM32_IRQ_TIM6_DAC 54 +#define STM32_IRQ_TIM7 55 +#define STM32_IRQ_DMA2_CHANNEL1 56 +#define STM32_IRQ_DMA2_CHANNEL2 57 +#define STM32_IRQ_DMA2_CHANNEL3 58 +#define STM32_IRQ_DMA2_CHANNEL4 59 +#define STM32_IRQ_DMA2_CHANNEL5 60 +#define STM32_IRQ_COMP 64 +#define LSTM32_IRQ_PTIM1 65 +#define STM32_IRQ_LPTIM2 66 +#define STM32_IRQ_DMA2_CHANNEL6 68 +#define STM32_IRQ_DMA2_CHANNEL7 69 +#define STM32_IRQ_LPUART1 70 +#define STM32_IRQ_QUADSPI 71 +#define STM32_IRQ_I2C3_EV 72 +#define STM32_IRQ_I2C3_ER 73 +#define STM32_IRQ_SAI1 74 +#define STM32_IRQ_SWPMI1 76 +#define STM32_IRQ_TSC 77 +#define STM32_IRQ_RNG 80 +#define STM32_IRQ_FPU 81 +#define STM32_IRQ_CRS 82 /* To simplify code generation, define DMA channel 9..10 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_11 STM32_IRQ_DMA2_CHANNEL3 -#define STM32_IRQ_DMA_CHANNEL_12 STM32_IRQ_DMA2_CHANNEL4 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL5 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_15 STM32_IRQ_DMA2_CHANNEL7 -#define STM32_IRQ_USART9 STM32_IRQ_LPUART1 - +#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 +#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 +#define STM32_IRQ_DMA_CHANNEL_11 STM32_IRQ_DMA2_CHANNEL3 +#define STM32_IRQ_DMA_CHANNEL_12 STM32_IRQ_DMA2_CHANNEL4 +#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL5 +#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL6 +#define STM32_IRQ_DMA_CHANNEL_15 STM32_IRQ_DMA2_CHANNEL7 +#define STM32_IRQ_USART9 STM32_IRQ_LPUART1 /* Peripheral base addresses */ -#define FLASH_BASE 0x08000000UL -#define FLASH_END 0x0803FFFFUL -#define FLASH_BANK1_END 0x0803FFFFUL -#define SRAM1_BASE 0x20000000UL -#define SRAM2_BASE 0x10000000UL -#define PERIPH_BASE 0x40000000UL -#define QSPI_BASE 0x90000000UL -#define QSPI_R_BASE 0xA0001000UL -#define SRAM1_BB_BASE 0x22000000UL -#define PERIPH_BB_BASE 0x42000000UL +#define FLASH_BASE 0x08000000UL +#define FLASH_END 0x0803FFFFUL +#define FLASH_BANK1_END 0x0803FFFFUL +#define SRAM1_BASE 0x20000000UL +#define SRAM2_BASE 0x10000000UL +#define PERIPH_BASE 0x40000000UL +#define QSPI_BASE 0x90000000UL +#define QSPI_R_BASE 0xA0001000UL +#define SRAM1_BB_BASE 0x22000000UL +#define PERIPH_BB_BASE 0x42000000UL /* Legacy defines */ -#define SRAM_BASE SRAM1_BASE -#define SRAM_BB_BASE SRAM1_BB_BASE -#define SRAM1_SIZE_MAX 0x0000C000UL -#define SRAM2_SIZE 0x00004000UL +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE +#define SRAM1_SIZE_MAX 0x0000C000UL +#define SRAM2_SIZE 0x00004000UL #define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) -#define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) \ - & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \ - (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & \ - (0x0000FFFFU)) << 10U)) +#define FLASH_SIZE \ + (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == \ + 0x0000FFFFU)) ? \ + (0x100U << 10U) : \ + (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) \ + << 10U)) /*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) /*!< APB1 peripherals */ -#define STM32_TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) -#define STM32_TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) -#define STM32_TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) -#define STM32_TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) -#define STM32_RTC_BASE (APB1PERIPH_BASE + 0x2800UL) -#define STM32_WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) -#define STM32_IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) -#define STM32_SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) -#define STM32_SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) -#define STM32_USART2_BASE (APB1PERIPH_BASE + 0x4400UL) -#define STM32_USART3_BASE (APB1PERIPH_BASE + 0x4800UL) -#define STM32_I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) -#define STM32_I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) -#define STM32_I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) -#define STM32_CRS_BASE (APB1PERIPH_BASE + 0x6000UL) -#define STM32_CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) -#define STM32_PWR_BASE (APB1PERIPH_BASE + 0x7000UL) -#define STM32_DAC_BASE (APB1PERIPH_BASE + 0x7400UL) -#define STM32_DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) -#define STM32_OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) -#define STM32_OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL) -#define STM32_LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) -#define STM32_LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) -#define STM32_SWPMI1_BASE (APB1PERIPH_BASE + 0x8800UL) -#define STM32_LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) - -#define STM32_USART9_BASE STM32_LPUART1_BASE +#define STM32_TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define STM32_TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define STM32_TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define STM32_TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define STM32_RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define STM32_WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define STM32_IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define STM32_SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define STM32_SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define STM32_USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define STM32_USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define STM32_I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define STM32_I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define STM32_I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define STM32_CRS_BASE (APB1PERIPH_BASE + 0x6000UL) +#define STM32_CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define STM32_PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define STM32_DAC_BASE (APB1PERIPH_BASE + 0x7400UL) +#define STM32_DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) +#define STM32_OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) +#define STM32_OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL) +#define STM32_LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define STM32_LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define STM32_SWPMI1_BASE (APB1PERIPH_BASE + 0x8800UL) +#define STM32_LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) + +#define STM32_USART9_BASE STM32_LPUART1_BASE /*!< APB2 peripherals */ -#define STM32_SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) -#define STM32_VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) -#define STM32_OMP1_BASE (APB2PERIPH_BASE + 0x0200UL) -#define STM32_COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) -#define STM32_EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) -#define STM32_FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL) -#define STM32_SDMMC1_BASE (APB2PERIPH_BASE + 0x2800UL) -#define STM32_TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) -#define STM32_SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) -#define STM32_USART1_BASE (APB2PERIPH_BASE + 0x3800UL) -#define STM32_TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) -#define STM32_TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) -#define STM32_SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) -#define STM32_SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) -#define STM32_SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) +#define STM32_SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define STM32_VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) +#define STM32_OMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define STM32_COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define STM32_EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define STM32_FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL) +#define STM32_SDMMC1_BASE (APB2PERIPH_BASE + 0x2800UL) +#define STM32_TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define STM32_SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define STM32_USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define STM32_TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define STM32_TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define STM32_SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define STM32_SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define STM32_SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) /*!< AHB1 peripherals */ -#define STM32_DMA1_BASE (AHB1PERIPH_BASE) -#define STM32_DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) -#define STM32_RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) -#define STM32_FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) -#define STM32_CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) -#define STM32_TSC_BASE (AHB1PERIPH_BASE + 0x4000UL) -#define STM32_DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) -#define STM32_DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) -#define STM32_DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) -#define STM32_DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) -#define STM32_DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) -#define STM32_DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) -#define STM32_DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) -#define STM32_DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) -#define STM32_DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) -#define STM32_DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) -#define STM32_DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) -#define STM32_DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) -#define STM32_DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) -#define STM32_DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) -#define STM32_DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) -#define STM32_DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) +#define STM32_DMA1_BASE (AHB1PERIPH_BASE) +#define STM32_DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define STM32_RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define STM32_FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define STM32_CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) +#define STM32_TSC_BASE (AHB1PERIPH_BASE + 0x4000UL) +#define STM32_DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define STM32_DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define STM32_DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define STM32_DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define STM32_DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define STM32_DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define STM32_DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define STM32_DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) +#define STM32_DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define STM32_DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define STM32_DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define STM32_DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define STM32_DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define STM32_DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define STM32_DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define STM32_DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) /*!< AHB2 peripherals */ -#define STM32_GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) -#define STM32_GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) -#define STM32_GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) -#define STM32_GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) -#define STM32_GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) -#define STM32_GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) -#define STM32_GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) /* stm32l4x6 */ -#define STM32_GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL) -#define STM32_ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) -#define STM32_ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) -#define STM32_RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) +#define STM32_GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define STM32_GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define STM32_GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define STM32_GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define STM32_GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define STM32_GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) +#define STM32_GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) /* stm32l4x6 */ +#define STM32_GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL) +#define STM32_ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) +#define STM32_ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) +#define STM32_RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) /* Debug MCU registers base address */ -#define STM32_DBGMCU_BASE 0xE0042000UL -#define STM32_PACKAGE_BASE 0x1FFF7500UL -#define STM32_UID_BASE 0x1FFF7590UL -#define STM32_FLASHSIZE_BASE 0x1FFF75E0UL +#define STM32_DBGMCU_BASE 0xE0042000UL +#define STM32_PACKAGE_BASE 0x1FFF7500UL +#define STM32_UID_BASE 0x1FFF7590UL +#define STM32_FLASHSIZE_BASE 0x1FFF75E0UL -#define STM32_FLASH_REGS_BASE STM32_FLASH_R_BASE -#define STM32_UNIQUE_ID_BASE STM32_UID_BASE -#define STM32_OPTB_BASE 0x1FFF7800 +#define STM32_FLASH_REGS_BASE STM32_FLASH_R_BASE +#define STM32_UNIQUE_ID_BASE STM32_UID_BASE +#define STM32_OPTB_BASE 0x1FFF7800 #ifndef __ASSEMBLER__ /* Register definitions */ /* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_UESM BIT(1) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) - -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR2_SWAP BIT(15) - -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) -#define STM32_USART_CR3_OVRDIS BIT(12) +#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) +#define STM32_USART_CR1_UE BIT(0) +#define STM32_USART_CR1_UESM BIT(1) +#define STM32_USART_CR1_RE BIT(2) +#define STM32_USART_CR1_TE BIT(3) +#define STM32_USART_CR1_RXNEIE BIT(5) +#define STM32_USART_CR1_TCIE BIT(6) +#define STM32_USART_CR1_TXEIE BIT(7) +#define STM32_USART_CR1_PS BIT(9) +#define STM32_USART_CR1_PCE BIT(10) +#define STM32_USART_CR1_M BIT(12) +#define STM32_USART_CR1_OVER8 BIT(15) + +#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) +#define STM32_USART_CR2_SWAP BIT(15) + +#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) +#define STM32_USART_CR3_EIE BIT(0) +#define STM32_USART_CR3_DMAR BIT(6) +#define STM32_USART_CR3_DMAT BIT(7) +#define STM32_USART_CR3_ONEBIT BIT(11) +#define STM32_USART_CR3_OVRDIS BIT(12) #define STM32_USART_CR3_WUS_START_BIT (2 << 20) -#define STM32_USART_CR3_WUFIE BIT(22) - -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) -#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) -#define STM32_USART_ICR_ORECF BIT(3) -#define STM32_USART_ICR_TCCF BIT(6) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) -#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) +#define STM32_USART_CR3_WUFIE BIT(22) + +#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) +#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) +#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) +#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) +#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) +#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) +#define STM32_USART_ICR_ORECF BIT(3) +#define STM32_USART_ICR_TCCF BIT(6) +#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) +#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) +#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) /* register alias */ -#define STM32_USART_SR(base) STM32_USART_ISR(base) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) +#define STM32_USART_SR(base) STM32_USART_ISR(base) +#define STM32_USART_SR_ORE BIT(3) +#define STM32_USART_SR_RXNE BIT(5) +#define STM32_USART_SR_TC BIT(6) +#define STM32_USART_SR_TXE BIT(7) /* --- GPIO --- */ -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) -#define STM32_GPIO_BRR(b) REG32((b) + 0x28) -#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4x6 */ - -#define GPIO_ALT_F0 0x0 -#define GPIO_ALT_F1 0x1 -#define GPIO_ALT_F2 0x2 -#define GPIO_ALT_F3 0x3 -#define GPIO_ALT_F4 0x4 -#define GPIO_ALT_F5 0x5 -#define GPIO_ALT_F6 0x6 -#define GPIO_ALT_F7 0x7 -#define GPIO_ALT_F8 0x8 -#define GPIO_ALT_F9 0x9 -#define GPIO_ALT_FA 0xA -#define GPIO_ALT_FB 0xB -#define GPIO_ALT_FC 0xC -#define GPIO_ALT_FD 0xD -#define GPIO_ALT_FE 0xE -#define GPIO_ALT_FF 0xF +#define STM32_GPIO_MODER(b) REG32((b) + 0x00) +#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) +#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) +#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) +#define STM32_GPIO_IDR(b) REG16((b) + 0x10) +#define STM32_GPIO_ODR(b) REG16((b) + 0x14) +#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) +#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) +#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) +#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) +#define STM32_GPIO_BRR(b) REG32((b) + 0x28) +#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4x6 */ + +#define GPIO_ALT_F0 0x0 +#define GPIO_ALT_F1 0x1 +#define GPIO_ALT_F2 0x2 +#define GPIO_ALT_F3 0x3 +#define GPIO_ALT_F4 0x4 +#define GPIO_ALT_F5 0x5 +#define GPIO_ALT_F6 0x6 +#define GPIO_ALT_F7 0x7 +#define GPIO_ALT_F8 0x8 +#define GPIO_ALT_F9 0x9 +#define GPIO_ALT_FA 0xA +#define GPIO_ALT_FB 0xB +#define GPIO_ALT_FC 0xC +#define GPIO_ALT_FD 0xD +#define GPIO_ALT_FE 0xE +#define GPIO_ALT_FF 0xF /* --- I2C --- */ -#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_TXIE BIT(1) -#define STM32_I2C_CR1_RXIE BIT(2) -#define STM32_I2C_CR1_ADDRIE BIT(3) -#define STM32_I2C_CR1_NACKIE BIT(4) -#define STM32_I2C_CR1_STOPIE BIT(5) -#define STM32_I2C_CR1_ERRIE BIT(7) -#define STM32_I2C_CR1_WUPEN BIT(18) -#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_RD_WRN BIT(10) -#define STM32_I2C_CR2_START BIT(13) -#define STM32_I2C_CR2_STOP BIT(14) -#define STM32_I2C_CR2_NACK BIT(15) -#define STM32_I2C_CR2_RELOAD BIT(24) -#define STM32_I2C_CR2_AUTOEND BIT(25) -#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_ISR_TXE BIT(0) -#define STM32_I2C_ISR_TXIS BIT(1) -#define STM32_I2C_ISR_RXNE BIT(2) -#define STM32_I2C_ISR_ADDR BIT(3) -#define STM32_I2C_ISR_NACK BIT(4) -#define STM32_I2C_ISR_STOP BIT(5) -#define STM32_I2C_ISR_TC BIT(6) -#define STM32_I2C_ISR_TCR BIT(7) -#define STM32_I2C_ISR_BERR BIT(8) -#define STM32_I2C_ISR_ARLO BIT(9) -#define STM32_I2C_ISR_OVR BIT(10) -#define STM32_I2C_ISR_PECERR BIT(11) -#define STM32_I2C_ISR_TIMEOUT BIT(12) -#define STM32_I2C_ISR_ALERT BIT(13) -#define STM32_I2C_ISR_BUSY BIT(15) -#define STM32_I2C_ISR_DIR BIT(16) -#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe) -#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_ICR_ADDRCF BIT(3) -#define STM32_I2C_ICR_NACKCF BIT(4) -#define STM32_I2C_ICR_STOPCF BIT(5) -#define STM32_I2C_ICR_BERRCF BIT(8) -#define STM32_I2C_ICR_ARLOCF BIT(9) -#define STM32_I2C_ICR_OVRCF BIT(10) -#define STM32_I2C_ICR_TIMEOUTCF BIT(12) -#define STM32_I2C_ICR_ALL 0x3F38 -#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) -#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) -#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) +#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) +#define STM32_I2C_CR1_PE BIT(0) +#define STM32_I2C_CR1_TXIE BIT(1) +#define STM32_I2C_CR1_RXIE BIT(2) +#define STM32_I2C_CR1_ADDRIE BIT(3) +#define STM32_I2C_CR1_NACKIE BIT(4) +#define STM32_I2C_CR1_STOPIE BIT(5) +#define STM32_I2C_CR1_ERRIE BIT(7) +#define STM32_I2C_CR1_WUPEN BIT(18) +#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) +#define STM32_I2C_CR2_RD_WRN BIT(10) +#define STM32_I2C_CR2_START BIT(13) +#define STM32_I2C_CR2_STOP BIT(14) +#define STM32_I2C_CR2_NACK BIT(15) +#define STM32_I2C_CR2_RELOAD BIT(24) +#define STM32_I2C_CR2_AUTOEND BIT(25) +#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) +#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) +#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) +#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) +#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) +#define STM32_I2C_ISR_TXE BIT(0) +#define STM32_I2C_ISR_TXIS BIT(1) +#define STM32_I2C_ISR_RXNE BIT(2) +#define STM32_I2C_ISR_ADDR BIT(3) +#define STM32_I2C_ISR_NACK BIT(4) +#define STM32_I2C_ISR_STOP BIT(5) +#define STM32_I2C_ISR_TC BIT(6) +#define STM32_I2C_ISR_TCR BIT(7) +#define STM32_I2C_ISR_BERR BIT(8) +#define STM32_I2C_ISR_ARLO BIT(9) +#define STM32_I2C_ISR_OVR BIT(10) +#define STM32_I2C_ISR_PECERR BIT(11) +#define STM32_I2C_ISR_TIMEOUT BIT(12) +#define STM32_I2C_ISR_ALERT BIT(13) +#define STM32_I2C_ISR_BUSY BIT(15) +#define STM32_I2C_ISR_DIR BIT(16) +#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe) +#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) +#define STM32_I2C_ICR_ADDRCF BIT(3) +#define STM32_I2C_ICR_NACKCF BIT(4) +#define STM32_I2C_ICR_STOPCF BIT(5) +#define STM32_I2C_ICR_BERRCF BIT(8) +#define STM32_I2C_ICR_ARLOCF BIT(9) +#define STM32_I2C_ICR_OVRCF BIT(10) +#define STM32_I2C_ICR_TIMEOUTCF BIT(12) +#define STM32_I2C_ICR_ALL 0x3F38 +#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) +#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) +#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) /* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CR1 REG32(STM32_PWR_BASE + 0x00) -#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x04) -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x10) -#define STM32_PWR_SCR REG32(STM32_PWR_BASE + 0x18) - -#define PWR_CR1_LPMS_POS 0U -#define PWR_CR1_LPMS_MSK (0x7UL << PWR_CR1_LPMS_POS) -#define PWR_CR1_LPMS PWR_CR1_LPMS_MSK -#define PWR_CR1_LPMS_STOP0 (0x00000000UL) -#define PWR_CR1_LPMS_STOP1_POS 0U -#define PWR_CR1_LPMS_STOP1_MSK (0x1UL << PWR_CR1_LPMS_STOP1_POS) -#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_MSK -#define PWR_CR1_LPMS_STOP2_POS 1U -#define PWR_CR1_LPMS_STOP2_MSK (0x1UL << PWR_CR1_LPMS_STOP2_POS) -#define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_MSK -#define PWR_CR1_LPMS_STANDBY_POS 0U -#define PWR_CR1_LPMS_STANDBY_MSK (0x3UL << PWR_CR1_LPMS_STANDBY_POS) -#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_MSK -#define PWR_CR1_LPMS_SHUTDOWN_POS 2U -#define PWR_CR1_LPMS_SHUTDOWN_MSK (0x1UL << PWR_CR1_LPMS_SHUTDOWN_POS) -#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_MSK -#define PWR_CR1_VOS_POS 9U -#define PWR_CR1_VOS_MSK (0x3UL << PWR_CR1_VOS_POS) -#define PWR_CR1_VOS PWR_CR1_VOS_MSK -#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_POS) -#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_POS) - +#define STM32_PWR_CR1 REG32(STM32_PWR_BASE + 0x00) +#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x04) +#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x10) +#define STM32_PWR_SCR REG32(STM32_PWR_BASE + 0x18) + +#define PWR_CR1_LPMS_POS 0U +#define PWR_CR1_LPMS_MSK (0x7UL << PWR_CR1_LPMS_POS) +#define PWR_CR1_LPMS PWR_CR1_LPMS_MSK +#define PWR_CR1_LPMS_STOP0 (0x00000000UL) +#define PWR_CR1_LPMS_STOP1_POS 0U +#define PWR_CR1_LPMS_STOP1_MSK (0x1UL << PWR_CR1_LPMS_STOP1_POS) +#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_MSK +#define PWR_CR1_LPMS_STOP2_POS 1U +#define PWR_CR1_LPMS_STOP2_MSK (0x1UL << PWR_CR1_LPMS_STOP2_POS) +#define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_MSK +#define PWR_CR1_LPMS_STANDBY_POS 0U +#define PWR_CR1_LPMS_STANDBY_MSK (0x3UL << PWR_CR1_LPMS_STANDBY_POS) +#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_MSK +#define PWR_CR1_LPMS_SHUTDOWN_POS 2U +#define PWR_CR1_LPMS_SHUTDOWN_MSK (0x1UL << PWR_CR1_LPMS_SHUTDOWN_POS) +#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_MSK +#define PWR_CR1_VOS_POS 9U +#define PWR_CR1_VOS_MSK (0x3UL << PWR_CR1_VOS_POS) +#define PWR_CR1_VOS PWR_CR1_VOS_MSK +#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_POS) +#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_POS) /* --- Macro usage in ec code --- */ #define STM32_RCC_AHB2ENR_GPIOMASK \ @@ -388,133 +388,131 @@ #define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4) #define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5) #define STM32_RCC_ICSCR_MSIRANGE_MASK STM32_RCC_CR_MSIRANGE_MSK -#define STM32_RCC_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN +#define STM32_RCC_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN -#define STM32_RCC_PB2_TIM1 STM32_RCC_APB2ENR_TIM1EN -#define STM32_RCC_PB2_TIM15 STM32_RCC_APB2ENR_TIM15EN -#define STM32_RCC_PB2_TIM16 STM32_RCC_APB2ENR_TIM16EN +#define STM32_RCC_PB2_TIM1 STM32_RCC_APB2ENR_TIM1EN +#define STM32_RCC_PB2_TIM15 STM32_RCC_APB2ENR_TIM15EN +#define STM32_RCC_PB2_TIM16 STM32_RCC_APB2ENR_TIM16EN #ifndef CHIP_VARIANT_STM32L431X -#define STM32_RCC_PB2_TIM8 BIT(13) +#define STM32_RCC_PB2_TIM8 BIT(13) #endif #define STM32_RCC_PWREN STM32_RCC_APB1ENR1_PWREN -#define STM32_RCC_AHB2ENR_GPIO_PORTA BIT(0) -#define STM32_RCC_AHB2ENR_GPIO_PORTB BIT(1) -#define STM32_RCC_AHB2ENR_GPIO_PORTC BIT(2) -#define STM32_RCC_AHB2ENR_GPIO_PORTD BIT(3) -#define STM32_RCC_AHB2ENR_GPIO_PORTE BIT(4) -#define STM32_RCC_AHB2ENR_GPIO_PORTH BIT(7) +#define STM32_RCC_AHB2ENR_GPIO_PORTA BIT(0) +#define STM32_RCC_AHB2ENR_GPIO_PORTB BIT(1) +#define STM32_RCC_AHB2ENR_GPIO_PORTC BIT(2) +#define STM32_RCC_AHB2ENR_GPIO_PORTD BIT(3) +#define STM32_RCC_AHB2ENR_GPIO_PORTE BIT(4) +#define STM32_RCC_AHB2ENR_GPIO_PORTH BIT(7) #define STM32_RCC_CCIPR_USART1SEL_SHIFT (0) -#define STM32_RCC_CCIPR_USART1SEL_MASK (3 << STM32_RCC_CCIPR_USART1SEL_SHIFT) +#define STM32_RCC_CCIPR_USART1SEL_MASK (3 << STM32_RCC_CCIPR_USART1SEL_SHIFT) #define STM32_RCC_CCIPR_USART2SEL_SHIFT (2) -#define STM32_RCC_CCIPR_USART2SEL_MASK (3 << STM32_RCC_CCIPR_USART2SEL_SHIFT) +#define STM32_RCC_CCIPR_USART2SEL_MASK (3 << STM32_RCC_CCIPR_USART2SEL_SHIFT) #define STM32_RCC_CCIPR_USART3SEL_SHIFT (4) -#define STM32_RCC_CCIPR_USART3SEL_MASK (3 << STM32_RCC_CCIPR_USART3SEL_SHIFT) +#define STM32_RCC_CCIPR_USART3SEL_MASK (3 << STM32_RCC_CCIPR_USART3SEL_SHIFT) #define STM32_RCC_CCIPR_UART4SEL_SHIFT (6) -#define STM32_RCC_CCIPR_UART4SEL_MASK (3 << STM32_RCC_CCIPR_UART4SEL_SHIFT) +#define STM32_RCC_CCIPR_UART4SEL_MASK (3 << STM32_RCC_CCIPR_UART4SEL_SHIFT) #define STM32_RCC_CCIPR_UART5SEL_SHIFT (8) -#define STM32_RCC_CCIPR_UART5SEL_MASK (3 << STM32_RCC_CCIPR_UART5SEL_SHIFT) +#define STM32_RCC_CCIPR_UART5SEL_MASK (3 << STM32_RCC_CCIPR_UART5SEL_SHIFT) #define STM32_RCC_CCIPR_LPUART1SEL_SHIFT (10) -#define STM32_RCC_CCIPR_LPUART1SEL_MASK (3 << STM32_RCC_CCIPR_LPUART1SEL_SHIFT) +#define STM32_RCC_CCIPR_LPUART1SEL_MASK (3 << STM32_RCC_CCIPR_LPUART1SEL_SHIFT) #define STM32_RCC_CCIPR_I2C1SEL_SHIFT (12) -#define STM32_RCC_CCIPR_I2C1SEL_MASK (3 << STM32_RCC_CCIPR_I2C1SEL_SHIFT) +#define STM32_RCC_CCIPR_I2C1SEL_MASK (3 << STM32_RCC_CCIPR_I2C1SEL_SHIFT) #define STM32_RCC_CCIPR_I2C2SEL_SHIFT (14) -#define STM32_RCC_CCIPR_I2C2SEL_MASK (3 << STM32_RCC_CCIPR_I2C2SEL_SHIFT) +#define STM32_RCC_CCIPR_I2C2SEL_MASK (3 << STM32_RCC_CCIPR_I2C2SEL_SHIFT) #define STM32_RCC_CCIPR_I2C3SEL_SHIFT (16) -#define STM32_RCC_CCIPR_I2C3SEL_MASK (3 << STM32_RCC_CCIPR_I2C3SEL_SHIFT) +#define STM32_RCC_CCIPR_I2C3SEL_MASK (3 << STM32_RCC_CCIPR_I2C3SEL_SHIFT) #define STM32_RCC_CCIPR_LPTIM1SEL_SHIFT (18) -#define STM32_RCC_CCIPR_LPTIM1SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM1SEL_SHIFT) +#define STM32_RCC_CCIPR_LPTIM1SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM1SEL_SHIFT) #define STM32_RCC_CCIPR_LPTIM2SEL_SHIFT (20) -#define STM32_RCC_CCIPR_LPTIM2SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM2SEL_SHIFT) +#define STM32_RCC_CCIPR_LPTIM2SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM2SEL_SHIFT) #define STM32_RCC_CCIPR_SAI1SEL_SHIFT (22) -#define STM32_RCC_CCIPR_SAI1SEL_MASK (3 << STM32_RCC_CCIPR_SAI1SEL_SHIFT) +#define STM32_RCC_CCIPR_SAI1SEL_MASK (3 << STM32_RCC_CCIPR_SAI1SEL_SHIFT) #define STM32_RCC_CCIPR_SAI2SEL_SHIFT (24) -#define STM32_RCC_CCIPR_SAI2SEL_MASK (3 << STM32_RCC_CCIPR_SAI2SEL_SHIFT) +#define STM32_RCC_CCIPR_SAI2SEL_MASK (3 << STM32_RCC_CCIPR_SAI2SEL_SHIFT) #define STM32_RCC_CCIPR_CLK48SEL_SHIFT (26) -#define STM32_RCC_CCIPR_CLK48SEL_MASK (3 << STM32_RCC_CCIPR_CLK48SEL_SHIFT) +#define STM32_RCC_CCIPR_CLK48SEL_MASK (3 << STM32_RCC_CCIPR_CLK48SEL_SHIFT) #define STM32_RCC_CCIPR_ADCSEL_SHIFT (28) -#define STM32_RCC_CCIPR_ADCSEL_MASK (3 << STM32_RCC_CCIPR_ADCSEL_SHIFT) +#define STM32_RCC_CCIPR_ADCSEL_MASK (3 << STM32_RCC_CCIPR_ADCSEL_SHIFT) #define STM32_RCC_CCIPR_SWPMI1SEL_SHIFT (30) -#define STM32_RCC_CCIPR_SWPMI1SEL_MASK BIT(STM32_RCC_CCIPR_SWPMI1SEL_SHIFT) +#define STM32_RCC_CCIPR_SWPMI1SEL_MASK BIT(STM32_RCC_CCIPR_SWPMI1SEL_SHIFT) #define STM32_RCC_CCIPR_DFSDM1SEL_SHIFT (31) -#define STM32_RCC_CCIPR_DFSDM1SEL_MASK BIT(STM32_RCC_CCIPR_DFSDM1SEL_SHIFT) +#define STM32_RCC_CCIPR_DFSDM1SEL_MASK BIT(STM32_RCC_CCIPR_DFSDM1SEL_SHIFT) /* Possible clock sources for each peripheral */ -#define STM32_RCC_CCIPR_UART_PCLK 0 -#define STM32_RCC_CCIPR_UART_SYSCLK 1 -#define STM32_RCC_CCIPR_UART_HSI16 2 -#define STM32_RCC_CCIPR_UART_LSE 3 - -#define STM32_RCC_CCIPR_I2C_PCLK 0 -#define STM32_RCC_CCIPR_I2C_SYSCLK 1 -#define STM32_RCC_CCIPR_I2C_HSI16 2 - -#define STM32_RCC_CCIPR_LPTIM_PCLK 0 -#define STM32_RCC_CCIPR_LPTIM_LSI 1 -#define STM32_RCC_CCIPR_LPTIM_HSI16 2 -#define STM32_RCC_CCIPR_LPTIM_LSE 3 - -#define STM32_RCC_CCIPR_SAI_PLLSAI1CLK 0 -#define STM32_RCC_CCIPR_SAI_PLLSAI2CLK 1 -#define STM32_RCC_CCIPR_SAI_PLLSAI3CLK 2 -#define STM32_RCC_CCIPR_SAI_EXTCLK 3 - -#define STM32_RCC_CCIPR_CLK48_NONE 0 -#define STM32_RCC_CCIPR_CLK48_PLL48M2CLK 1 -#define STM32_RCC_CCIPR_CLK48_PLL48M1CLK 2 -#define STM32_RCC_CCIPR_CLK48_MSI 3 - -#define STM32_RCC_CCIPR_ADC_NONE 0 -#define STM32_RCC_CCIPR_ADC_PLLADC1CLK 1 -#define STM32_RCC_CCIPR_ADC_PLLADC2CLK 2 -#define STM32_RCC_CCIPR_ADC_SYSCLK 3 - -#define STM32_RCC_CCIPR_SWPMI_PCLK 0 -#define STM32_RCC_CCIPR_SWPMI_HSI16 1 - -#define STM32_RCC_CCIPR_DFSDM_PCLK 0 -#define STM32_RCC_CCIPR_DFSDM_SYSCLK 1 - - - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x0C) +#define STM32_RCC_CCIPR_UART_PCLK 0 +#define STM32_RCC_CCIPR_UART_SYSCLK 1 +#define STM32_RCC_CCIPR_UART_HSI16 2 +#define STM32_RCC_CCIPR_UART_LSE 3 + +#define STM32_RCC_CCIPR_I2C_PCLK 0 +#define STM32_RCC_CCIPR_I2C_SYSCLK 1 +#define STM32_RCC_CCIPR_I2C_HSI16 2 + +#define STM32_RCC_CCIPR_LPTIM_PCLK 0 +#define STM32_RCC_CCIPR_LPTIM_LSI 1 +#define STM32_RCC_CCIPR_LPTIM_HSI16 2 +#define STM32_RCC_CCIPR_LPTIM_LSE 3 + +#define STM32_RCC_CCIPR_SAI_PLLSAI1CLK 0 +#define STM32_RCC_CCIPR_SAI_PLLSAI2CLK 1 +#define STM32_RCC_CCIPR_SAI_PLLSAI3CLK 2 +#define STM32_RCC_CCIPR_SAI_EXTCLK 3 + +#define STM32_RCC_CCIPR_CLK48_NONE 0 +#define STM32_RCC_CCIPR_CLK48_PLL48M2CLK 1 +#define STM32_RCC_CCIPR_CLK48_PLL48M1CLK 2 +#define STM32_RCC_CCIPR_CLK48_MSI 3 + +#define STM32_RCC_CCIPR_ADC_NONE 0 +#define STM32_RCC_CCIPR_ADC_PLLADC1CLK 1 +#define STM32_RCC_CCIPR_ADC_PLLADC2CLK 2 +#define STM32_RCC_CCIPR_ADC_SYSCLK 3 + +#define STM32_RCC_CCIPR_SWPMI_PCLK 0 +#define STM32_RCC_CCIPR_SWPMI_HSI16 1 + +#define STM32_RCC_CCIPR_DFSDM_PCLK 0 +#define STM32_RCC_CCIPR_DFSDM_SYSCLK 1 + +#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) +#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) +#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) +#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x0C) #define STM32_RCC_PLLSAI1CFGR REG32(STM32_RCC_BASE + 0x10) -#define STM32_RCC_RESERVED REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x18) -#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x1C) -#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_RESERVED0 REG32(STM32_RCC_BASE + 0x24) -#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x28) -#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x2C) -#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_RESERVED1 REG32(STM32_RCC_BASE + 0x34) -#define STM32_RCC_APB1RSTR1 REG32(STM32_RCC_BASE + 0x38) -#define STM32_RCC_APB1RSTR2 REG32(STM32_RCC_BASE + 0x3C) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x40) -#define STM32_RCC_RESERVED2 REG32(STM32_RCC_BASE + 0x44) -#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x48) -#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x4C) -#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x50) -#define STM32_RCC_RESERVED3 REG32(STM32_RCC_BASE + 0x54) -#define STM32_RCC_APB1ENR1 REG32(STM32_RCC_BASE + 0x58) -#define STM32_RCC_APB1ENR2 REG32(STM32_RCC_BASE + 0x5C) -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60) -#define STM32_RCC_RESERVED4 REG32(STM32_RCC_BASE + 0x64) -#define STM32_RCC_AHB1SMENR REG32(STM32_RCC_BASE + 0x68) -#define STM32_RCC_AHB2SMENR REG32(STM32_RCC_BASE + 0x6C) -#define STM32_RCC_AHB3SMENR REG32(STM32_RCC_BASE + 0x70) -#define STM32_RCC_RESERVED5 REG32(STM32_RCC_BASE + 0x74) -#define STM32_RCC_APB1SMENR1 REG32(STM32_RCC_BASE + 0x78) -#define STM32_RCC_APB1SMENR2 REG32(STM32_RCC_BASE + 0x7C) -#define STM32_RCC_APB2SMENR REG32(STM32_RCC_BASE + 0x80) -#define STM32_RCC_RESERVED6 REG32(STM32_RCC_BASE + 0x84) -#define STM32_RCC_CCIPR REG32(STM32_RCC_BASE + 0x88) -#define STM32_RCC_RESERVED7 REG32(STM32_RCC_BASE + 0x8C) -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x94) -#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98) +#define STM32_RCC_RESERVED REG32(STM32_RCC_BASE + 0x14) +#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x18) +#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x1C) +#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x20) +#define STM32_RCC_RESERVED0 REG32(STM32_RCC_BASE + 0x24) +#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x28) +#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x2C) +#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x30) +#define STM32_RCC_RESERVED1 REG32(STM32_RCC_BASE + 0x34) +#define STM32_RCC_APB1RSTR1 REG32(STM32_RCC_BASE + 0x38) +#define STM32_RCC_APB1RSTR2 REG32(STM32_RCC_BASE + 0x3C) +#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x40) +#define STM32_RCC_RESERVED2 REG32(STM32_RCC_BASE + 0x44) +#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x48) +#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x4C) +#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x50) +#define STM32_RCC_RESERVED3 REG32(STM32_RCC_BASE + 0x54) +#define STM32_RCC_APB1ENR1 REG32(STM32_RCC_BASE + 0x58) +#define STM32_RCC_APB1ENR2 REG32(STM32_RCC_BASE + 0x5C) +#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60) +#define STM32_RCC_RESERVED4 REG32(STM32_RCC_BASE + 0x64) +#define STM32_RCC_AHB1SMENR REG32(STM32_RCC_BASE + 0x68) +#define STM32_RCC_AHB2SMENR REG32(STM32_RCC_BASE + 0x6C) +#define STM32_RCC_AHB3SMENR REG32(STM32_RCC_BASE + 0x70) +#define STM32_RCC_RESERVED5 REG32(STM32_RCC_BASE + 0x74) +#define STM32_RCC_APB1SMENR1 REG32(STM32_RCC_BASE + 0x78) +#define STM32_RCC_APB1SMENR2 REG32(STM32_RCC_BASE + 0x7C) +#define STM32_RCC_APB2SMENR REG32(STM32_RCC_BASE + 0x80) +#define STM32_RCC_RESERVED6 REG32(STM32_RCC_BASE + 0x84) +#define STM32_RCC_CCIPR REG32(STM32_RCC_BASE + 0x88) +#define STM32_RCC_RESERVED7 REG32(STM32_RCC_BASE + 0x8C) +#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90) +#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x94) +#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98) #define STM32_RCC_PLLSAI1_SUPPORT #define STM32_RCC_PLLP_SUPPORT @@ -522,236 +520,236 @@ #define STM32_RCC_PLLP_DIV_2_31_SUPPORT #define STM32_RCC_PLLSAI1P_DIV_2_31_SUPPORT -#define STM32_RCC_APB1ENR STM32_RCC_APB1ENR1 +#define STM32_RCC_APB1ENR STM32_RCC_APB1ENR1 /******************** BIT DEFINITION FOR STM32_RCC_CR REGISTER **************/ -#define STM32_RCC_CR_MSION_POS 0U -#define STM32_RCC_CR_MSION_MSK (0x1UL << STM32_RCC_CR_MSION_POS) -#define STM32_RCC_CR_MSION STM32_RCC_CR_MSION_MSK -#define STM32_RCC_CR_MSIRDY_POS 1U -#define STM32_RCC_CR_MSIRDY_MSK (0x1UL << STM32_RCC_CR_MSIRDY_POS) -#define STM32_RCC_CR_MSIRDY STM32_RCC_CR_MSIRDY_MSK -#define STM32_RCC_CR_MSIPLLEN_POS 2U -#define STM32_RCC_CR_MSIPLLEN_MSK (0x1UL << STM32_RCC_CR_MSIPLLEN_POS) -#define STM32_RCC_CR_MSIPLLEN STM32_RCC_CR_MSIPLLEN_MSK -#define STM32_RCC_CR_MSIRGSEL_POS 3U -#define STM32_RCC_CR_MSIRGSEL_MSK (0x1UL << STM32_RCC_CR_MSIRGSEL_POS) -#define STM32_RCC_CR_MSIRGSEL STM32_RCC_CR_MSIRGSEL_MSK +#define STM32_RCC_CR_MSION_POS 0U +#define STM32_RCC_CR_MSION_MSK (0x1UL << STM32_RCC_CR_MSION_POS) +#define STM32_RCC_CR_MSION STM32_RCC_CR_MSION_MSK +#define STM32_RCC_CR_MSIRDY_POS 1U +#define STM32_RCC_CR_MSIRDY_MSK (0x1UL << STM32_RCC_CR_MSIRDY_POS) +#define STM32_RCC_CR_MSIRDY STM32_RCC_CR_MSIRDY_MSK +#define STM32_RCC_CR_MSIPLLEN_POS 2U +#define STM32_RCC_CR_MSIPLLEN_MSK (0x1UL << STM32_RCC_CR_MSIPLLEN_POS) +#define STM32_RCC_CR_MSIPLLEN STM32_RCC_CR_MSIPLLEN_MSK +#define STM32_RCC_CR_MSIRGSEL_POS 3U +#define STM32_RCC_CR_MSIRGSEL_MSK (0x1UL << STM32_RCC_CR_MSIRGSEL_POS) +#define STM32_RCC_CR_MSIRGSEL STM32_RCC_CR_MSIRGSEL_MSK /*!< MSIRANGE CONFIGURATION : 12 FREQUENCY RANGES AVAILABLE */ -#define STM32_RCC_CR_MSIRANGE_POS 4U -#define STM32_RCC_CR_MSIRANGE_MSK (0xFUL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE STM32_RCC_CR_MSIRANGE_MSK -#define STM32_RCC_CR_MSIRANGE_0 (0x0UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_1 (0x1UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_2 (0x2UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_3 (0x3UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_4 (0x4UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_5 (0x5UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_6 (0x6UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_7 (0x7UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_8 (0x8UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_9 (0x9UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_10 (0xAUL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_11 (0xBUL << STM32_RCC_CR_MSIRANGE_POS) - -#define STM32_RCC_CR_HSION_POS 8U -#define STM32_RCC_CR_HSION_MSK (0x1UL << STM32_RCC_CR_HSION_POS) -#define STM32_RCC_CR_HSION STM32_RCC_CR_HSION_MSK -#define STM32_RCC_CR_HSIKERON_POS 9U -#define STM32_RCC_CR_HSIKERON_MSK (0x1UL << STM32_RCC_CR_HSIKERON_POS) -#define STM32_RCC_CR_HSIKERON STM32_RCC_CR_HSIKERON_MSK -#define STM32_RCC_CR_HSIRDY_POS 10U -#define STM32_RCC_CR_HSIRDY_MSK (0x1UL << STM32_RCC_CR_HSIRDY_POS) -#define STM32_RCC_CR_HSIRDY STM32_RCC_CR_HSIRDY_MSK -#define STM32_RCC_CR_HSIASFS_POS 11U -#define STM32_RCC_CR_HSIASFS_MSK (0x1UL << STM32_RCC_CR_HSIASFS_POS) -#define STM32_RCC_CR_HSIASFS STM32_RCC_CR_HSIASFS_MSK - -#define STM32_RCC_CR_HSEON_POS 16U -#define STM32_RCC_CR_HSEON_MSK (0x1UL << STM32_RCC_CR_HSEON_POS) -#define STM32_RCC_CR_HSEON STM32_RCC_CR_HSEON_MSK -#define STM32_RCC_CR_HSERDY_POS 17U -#define STM32_RCC_CR_HSERDY_MSK (0x1UL << STM32_RCC_CR_HSERDY_POS) -#define STM32_RCC_CR_HSERDY STM32_RCC_CR_HSERDY_MSK -#define STM32_RCC_CR_HSEBYP_POS 18U -#define STM32_RCC_CR_HSEBYP_MSK (0x1UL << STM32_RCC_CR_HSEBYP_POS) -#define STM32_RCC_CR_HSEBYP STM32_RCC_CR_HSEBYP_MSK -#define STM32_RCC_CR_CSSON_POS 19U -#define STM32_RCC_CR_CSSON_MSK (0x1UL << STM32_RCC_CR_CSSON_POS) -#define STM32_RCC_CR_CSSON STM32_RCC_CR_CSSON_MSK - -#define STM32_RCC_CR_PLLON_POS 24U -#define STM32_RCC_CR_PLLON_MSK (0x1UL << STM32_RCC_CR_PLLON_POS) -#define STM32_RCC_CR_PLLON STM32_RCC_CR_PLLON_MSK -#define STM32_RCC_CR_PLLRDY_POS 25U -#define STM32_RCC_CR_PLLRDY_MSK (0x1UL << STM32_RCC_CR_PLLRDY_POS) -#define STM32_RCC_CR_PLLRDY STM32_RCC_CR_PLLRDY_MSK -#define STM32_RCC_CR_PLLSAI1ON_POS 26U -#define STM32_RCC_CR_PLLSAI1ON_MSK (0x1UL << STM32_RCC_CR_PLLSAI1ON_POS) -#define STM32_RCC_CR_PLLSAI1ON STM32_RCC_CR_PLLSAI1ON_MSK -#define STM32_RCC_CR_PLLSAI1RDY_POS 27U -#define STM32_RCC_CR_PLLSAI1RDY_MSK (0x1UL << STM32_RCC_CR_PLLSAI1RDY_POS) -#define STM32_RCC_CR_PLLSAI1RDY STM32_RCC_CR_PLLSAI1RDY_MSK +#define STM32_RCC_CR_MSIRANGE_POS 4U +#define STM32_RCC_CR_MSIRANGE_MSK (0xFUL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE STM32_RCC_CR_MSIRANGE_MSK +#define STM32_RCC_CR_MSIRANGE_0 (0x0UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_1 (0x1UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_2 (0x2UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_3 (0x3UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_4 (0x4UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_5 (0x5UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_6 (0x6UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_7 (0x7UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_8 (0x8UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_9 (0x9UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_10 (0xAUL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_11 (0xBUL << STM32_RCC_CR_MSIRANGE_POS) + +#define STM32_RCC_CR_HSION_POS 8U +#define STM32_RCC_CR_HSION_MSK (0x1UL << STM32_RCC_CR_HSION_POS) +#define STM32_RCC_CR_HSION STM32_RCC_CR_HSION_MSK +#define STM32_RCC_CR_HSIKERON_POS 9U +#define STM32_RCC_CR_HSIKERON_MSK (0x1UL << STM32_RCC_CR_HSIKERON_POS) +#define STM32_RCC_CR_HSIKERON STM32_RCC_CR_HSIKERON_MSK +#define STM32_RCC_CR_HSIRDY_POS 10U +#define STM32_RCC_CR_HSIRDY_MSK (0x1UL << STM32_RCC_CR_HSIRDY_POS) +#define STM32_RCC_CR_HSIRDY STM32_RCC_CR_HSIRDY_MSK +#define STM32_RCC_CR_HSIASFS_POS 11U +#define STM32_RCC_CR_HSIASFS_MSK (0x1UL << STM32_RCC_CR_HSIASFS_POS) +#define STM32_RCC_CR_HSIASFS STM32_RCC_CR_HSIASFS_MSK + +#define STM32_RCC_CR_HSEON_POS 16U +#define STM32_RCC_CR_HSEON_MSK (0x1UL << STM32_RCC_CR_HSEON_POS) +#define STM32_RCC_CR_HSEON STM32_RCC_CR_HSEON_MSK +#define STM32_RCC_CR_HSERDY_POS 17U +#define STM32_RCC_CR_HSERDY_MSK (0x1UL << STM32_RCC_CR_HSERDY_POS) +#define STM32_RCC_CR_HSERDY STM32_RCC_CR_HSERDY_MSK +#define STM32_RCC_CR_HSEBYP_POS 18U +#define STM32_RCC_CR_HSEBYP_MSK (0x1UL << STM32_RCC_CR_HSEBYP_POS) +#define STM32_RCC_CR_HSEBYP STM32_RCC_CR_HSEBYP_MSK +#define STM32_RCC_CR_CSSON_POS 19U +#define STM32_RCC_CR_CSSON_MSK (0x1UL << STM32_RCC_CR_CSSON_POS) +#define STM32_RCC_CR_CSSON STM32_RCC_CR_CSSON_MSK + +#define STM32_RCC_CR_PLLON_POS 24U +#define STM32_RCC_CR_PLLON_MSK (0x1UL << STM32_RCC_CR_PLLON_POS) +#define STM32_RCC_CR_PLLON STM32_RCC_CR_PLLON_MSK +#define STM32_RCC_CR_PLLRDY_POS 25U +#define STM32_RCC_CR_PLLRDY_MSK (0x1UL << STM32_RCC_CR_PLLRDY_POS) +#define STM32_RCC_CR_PLLRDY STM32_RCC_CR_PLLRDY_MSK +#define STM32_RCC_CR_PLLSAI1ON_POS 26U +#define STM32_RCC_CR_PLLSAI1ON_MSK (0x1UL << STM32_RCC_CR_PLLSAI1ON_POS) +#define STM32_RCC_CR_PLLSAI1ON STM32_RCC_CR_PLLSAI1ON_MSK +#define STM32_RCC_CR_PLLSAI1RDY_POS 27U +#define STM32_RCC_CR_PLLSAI1RDY_MSK (0x1UL << STM32_RCC_CR_PLLSAI1RDY_POS) +#define STM32_RCC_CR_PLLSAI1RDY STM32_RCC_CR_PLLSAI1RDY_MSK /******************** BIT DEFINITION FOR STM32_RCC_ICSCR REGISTER ***********/ /*!< MSICAL CONFIGURATION */ -#define STM32_RCC_ICSCR_MSICAL_POS 0U -#define STM32_RCC_ICSCR_MSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL STM32_RCC_ICSCR_MSICAL_MSK -#define STM32_RCC_ICSCR_MSICAL_0 (0x01UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_1 (0x02UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_2 (0x04UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_3 (0x08UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_4 (0x10UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_5 (0x20UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_6 (0x40UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_7 (0x80UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_POS 0U +#define STM32_RCC_ICSCR_MSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL STM32_RCC_ICSCR_MSICAL_MSK +#define STM32_RCC_ICSCR_MSICAL_0 (0x01UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_1 (0x02UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_2 (0x04UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_3 (0x08UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_4 (0x10UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_5 (0x20UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_6 (0x40UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_7 (0x80UL << STM32_RCC_ICSCR_MSICAL_POS) /*!< MSITRIM CONFIGURATION */ -#define STM32_RCC_ICSCR_MSITRIM_POS 8U -#define STM32_RCC_ICSCR_MSITRIM_MSK (0xFFUL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM STM32_RCC_ICSCR_MSITRIM_MSK -#define STM32_RCC_ICSCR_MSITRIM_0 (0x01UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_1 (0x02UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_2 (0x04UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_3 (0x08UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_4 (0x10UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_5 (0x20UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_6 (0x40UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_7 (0x80UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_POS 8U +#define STM32_RCC_ICSCR_MSITRIM_MSK (0xFFUL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM STM32_RCC_ICSCR_MSITRIM_MSK +#define STM32_RCC_ICSCR_MSITRIM_0 (0x01UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_1 (0x02UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_2 (0x04UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_3 (0x08UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_4 (0x10UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_5 (0x20UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_6 (0x40UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_7 (0x80UL << STM32_RCC_ICSCR_MSITRIM_POS) /*!< HSICAL CONFIGURATION */ -#define STM32_RCC_ICSCR_HSICAL_POS 16U -#define STM32_RCC_ICSCR_HSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL STM32_RCC_ICSCR_HSICAL_MSK -#define STM32_RCC_ICSCR_HSICAL_0 (0x01UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_1 (0x02UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_2 (0x04UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_3 (0x08UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_4 (0x10UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_5 (0x20UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_6 (0x40UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_7 (0x80UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_POS 16U +#define STM32_RCC_ICSCR_HSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL STM32_RCC_ICSCR_HSICAL_MSK +#define STM32_RCC_ICSCR_HSICAL_0 (0x01UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_1 (0x02UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_2 (0x04UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_3 (0x08UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_4 (0x10UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_5 (0x20UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_6 (0x40UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_7 (0x80UL << STM32_RCC_ICSCR_HSICAL_POS) /*!< HSITRIM CONFIGURATION */ -#define STM32_RCC_ICSCR_HSITRIM_POS 24U -#define STM32_RCC_ICSCR_HSITRIM_MSK (0x1FUL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM STM32_RCC_ICSCR_HSITRIM_MSK -#define STM32_RCC_ICSCR_HSITRIM_0 (0x01UL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM_1 (0x02UL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM_2 (0x04UL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM_3 (0x08UL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM_4 (0x10UL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM_POS 24U +#define STM32_RCC_ICSCR_HSITRIM_MSK (0x1FUL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM STM32_RCC_ICSCR_HSITRIM_MSK +#define STM32_RCC_ICSCR_HSITRIM_0 (0x01UL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM_1 (0x02UL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM_2 (0x04UL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM_3 (0x08UL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM_4 (0x10UL << STM32_RCC_ICSCR_HSITRIM_POS) /**************** BIT DEFINITION FOR STM32_RCC_CFGR REGISTER **************/ /*!< SW CONFIGURATION */ -#define STM32_RCC_CFGR_SW_POS 0U -#define STM32_RCC_CFGR_SW_MSK (0x3UL << STM32_RCC_CFGR_SW_POS) -#define STM32_RCC_CFGR_SW STM32_RCC_CFGR_SW_MSK -#define STM32_RCC_CFGR_SW_0 (0x1UL << STM32_RCC_CFGR_SW_POS) -#define STM32_RCC_CFGR_SW_1 (0x2UL << STM32_RCC_CFGR_SW_POS) +#define STM32_RCC_CFGR_SW_POS 0U +#define STM32_RCC_CFGR_SW_MSK (0x3UL << STM32_RCC_CFGR_SW_POS) +#define STM32_RCC_CFGR_SW STM32_RCC_CFGR_SW_MSK +#define STM32_RCC_CFGR_SW_0 (0x1UL << STM32_RCC_CFGR_SW_POS) +#define STM32_RCC_CFGR_SW_1 (0x2UL << STM32_RCC_CFGR_SW_POS) -#define STM32_RCC_CFGR_SW_MSI (0x00000000UL) -#define STM32_RCC_CFGR_SW_HSI (0x00000001UL) -#define STM32_RCC_CFGR_SW_HSE (0x00000002UL) -#define STM32_RCC_CFGR_SW_PLL (0x00000003UL) +#define STM32_RCC_CFGR_SW_MSI (0x00000000UL) +#define STM32_RCC_CFGR_SW_HSI (0x00000001UL) +#define STM32_RCC_CFGR_SW_HSE (0x00000002UL) +#define STM32_RCC_CFGR_SW_PLL (0x00000003UL) /*!< SWS CONFIGURATION */ -#define STM32_RCC_CFGR_SWS_POS 2U -#define STM32_RCC_CFGR_SWS_MSK (0x3UL << STM32_RCC_CFGR_SWS_POS) -#define STM32_RCC_CFGR_SWS STM32_RCC_CFGR_SWS_MSK -#define STM32_RCC_CFGR_SWS_0 (0x1UL << STM32_RCC_CFGR_SWS_POS) -#define STM32_RCC_CFGR_SWS_1 (0x2UL << STM32_RCC_CFGR_SWS_POS) +#define STM32_RCC_CFGR_SWS_POS 2U +#define STM32_RCC_CFGR_SWS_MSK (0x3UL << STM32_RCC_CFGR_SWS_POS) +#define STM32_RCC_CFGR_SWS STM32_RCC_CFGR_SWS_MSK +#define STM32_RCC_CFGR_SWS_0 (0x1UL << STM32_RCC_CFGR_SWS_POS) +#define STM32_RCC_CFGR_SWS_1 (0x2UL << STM32_RCC_CFGR_SWS_POS) -#define STM32_RCC_CFGR_SWS_MSI (0x00000000UL) -#define STM32_RCC_CFGR_SWS_HSI (0x00000004UL) -#define STM32_RCC_CFGR_SWS_HSE (0x00000008UL) -#define STM32_RCC_CFGR_SWS_PLL (0x0000000CUL) +#define STM32_RCC_CFGR_SWS_MSI (0x00000000UL) +#define STM32_RCC_CFGR_SWS_HSI (0x00000004UL) +#define STM32_RCC_CFGR_SWS_HSE (0x00000008UL) +#define STM32_RCC_CFGR_SWS_PLL (0x0000000CUL) /*!< HPRE CONFIGURATION */ -#define STM32_RCC_CFGR_HPRE_POS 4U -#define STM32_RCC_CFGR_HPRE_MSK (0xFUL << STM32_RCC_CFGR_HPRE_POS) -#define STM32_RCC_CFGR_HPRE STM32_RCC_CFGR_HPRE_MSK -#define STM32_RCC_CFGR_HPRE_0 (0x1UL << STM32_RCC_CFGR_HPRE_POS) -#define STM32_RCC_CFGR_HPRE_1 (0x2UL << STM32_RCC_CFGR_HPRE_POS) -#define STM32_RCC_CFGR_HPRE_2 (0x4UL << STM32_RCC_CFGR_HPRE_POS) -#define STM32_RCC_CFGR_HPRE_3 (0x8UL << STM32_RCC_CFGR_HPRE_POS) - -#define STM32_RCC_CFGR_HPRE_DIV1 (0x00000000UL) -#define STM32_RCC_CFGR_HPRE_DIV2 (0x00000080UL) -#define STM32_RCC_CFGR_HPRE_DIV4 (0x00000090UL) -#define STM32_RCC_CFGR_HPRE_DIV8 (0x000000A0UL) -#define STM32_RCC_CFGR_HPRE_DIV16 (0x000000B0UL) -#define STM32_RCC_CFGR_HPRE_DIV64 (0x000000C0UL) -#define STM32_RCC_CFGR_HPRE_DIV128 (0x000000D0UL) -#define STM32_RCC_CFGR_HPRE_DIV256 (0x000000E0UL) -#define STM32_RCC_CFGR_HPRE_DIV512 (0x000000F0UL) +#define STM32_RCC_CFGR_HPRE_POS 4U +#define STM32_RCC_CFGR_HPRE_MSK (0xFUL << STM32_RCC_CFGR_HPRE_POS) +#define STM32_RCC_CFGR_HPRE STM32_RCC_CFGR_HPRE_MSK +#define STM32_RCC_CFGR_HPRE_0 (0x1UL << STM32_RCC_CFGR_HPRE_POS) +#define STM32_RCC_CFGR_HPRE_1 (0x2UL << STM32_RCC_CFGR_HPRE_POS) +#define STM32_RCC_CFGR_HPRE_2 (0x4UL << STM32_RCC_CFGR_HPRE_POS) +#define STM32_RCC_CFGR_HPRE_3 (0x8UL << STM32_RCC_CFGR_HPRE_POS) + +#define STM32_RCC_CFGR_HPRE_DIV1 (0x00000000UL) +#define STM32_RCC_CFGR_HPRE_DIV2 (0x00000080UL) +#define STM32_RCC_CFGR_HPRE_DIV4 (0x00000090UL) +#define STM32_RCC_CFGR_HPRE_DIV8 (0x000000A0UL) +#define STM32_RCC_CFGR_HPRE_DIV16 (0x000000B0UL) +#define STM32_RCC_CFGR_HPRE_DIV64 (0x000000C0UL) +#define STM32_RCC_CFGR_HPRE_DIV128 (0x000000D0UL) +#define STM32_RCC_CFGR_HPRE_DIV256 (0x000000E0UL) +#define STM32_RCC_CFGR_HPRE_DIV512 (0x000000F0UL) /*!< PPRE1 CONFIGURATION */ -#define STM32_RCC_CFGR_PPRE1_POS 8U -#define STM32_RCC_CFGR_PPRE1_MSK (0x7UL << STM32_RCC_CFGR_PPRE1_POS) -#define STM32_RCC_CFGR_PPRE1 STM32_RCC_CFGR_PPRE1_MSK -#define STM32_RCC_CFGR_PPRE1_0 (0x1UL << STM32_RCC_CFGR_PPRE1_POS) -#define STM32_RCC_CFGR_PPRE1_1 (0x2UL << STM32_RCC_CFGR_PPRE1_POS) -#define STM32_RCC_CFGR_PPRE1_2 (0x4UL << STM32_RCC_CFGR_PPRE1_POS) - -#define STM32_RCC_CFGR_PPRE1_DIV1 (0x00000000UL) -#define STM32_RCC_CFGR_PPRE1_DIV2 (0x00000400UL) -#define STM32_RCC_CFGR_PPRE1_DIV4 (0x00000500UL) -#define STM32_RCC_CFGR_PPRE1_DIV8 (0x00000600UL) -#define STM32_RCC_CFGR_PPRE1_DIV16 (0x00000700UL) +#define STM32_RCC_CFGR_PPRE1_POS 8U +#define STM32_RCC_CFGR_PPRE1_MSK (0x7UL << STM32_RCC_CFGR_PPRE1_POS) +#define STM32_RCC_CFGR_PPRE1 STM32_RCC_CFGR_PPRE1_MSK +#define STM32_RCC_CFGR_PPRE1_0 (0x1UL << STM32_RCC_CFGR_PPRE1_POS) +#define STM32_RCC_CFGR_PPRE1_1 (0x2UL << STM32_RCC_CFGR_PPRE1_POS) +#define STM32_RCC_CFGR_PPRE1_2 (0x4UL << STM32_RCC_CFGR_PPRE1_POS) + +#define STM32_RCC_CFGR_PPRE1_DIV1 (0x00000000UL) +#define STM32_RCC_CFGR_PPRE1_DIV2 (0x00000400UL) +#define STM32_RCC_CFGR_PPRE1_DIV4 (0x00000500UL) +#define STM32_RCC_CFGR_PPRE1_DIV8 (0x00000600UL) +#define STM32_RCC_CFGR_PPRE1_DIV16 (0x00000700UL) /*!< PPRE2 CONFIGURATION */ -#define STM32_RCC_CFGR_PPRE2_POS 11U -#define STM32_RCC_CFGR_PPRE2_MSK (0x7UL << STM32_RCC_CFGR_PPRE2_POS) -#define STM32_RCC_CFGR_PPRE2 STM32_RCC_CFGR_PPRE2_MSK -#define STM32_RCC_CFGR_PPRE2_0 (0x1UL << STM32_RCC_CFGR_PPRE2_POS) -#define STM32_RCC_CFGR_PPRE2_1 (0x2UL << STM32_RCC_CFGR_PPRE2_POS) -#define STM32_RCC_CFGR_PPRE2_2 (0x4UL << STM32_RCC_CFGR_PPRE2_POS) - -#define STM32_RCC_CFGR_PPRE2_DIV1 (0x00000000UL) -#define STM32_RCC_CFGR_PPRE2_DIV2 (0x00002000UL) -#define STM32_RCC_CFGR_PPRE2_DIV4 (0x00002800UL) -#define STM32_RCC_CFGR_PPRE2_DIV8 (0x00003000UL) -#define STM32_RCC_CFGR_PPRE2_DIV16 (0x00003800UL) - -#define STM32_RCC_CFGR_STOPWUCK_POS 15U -#define STM32_RCC_CFGR_STOPWUCK_MSK (0x1UL << STM32_RCC_CFGR_STOPWUCK_POS) -#define STM32_RCC_CFGR_STOPWUCK STM32_RCC_CFGR_STOPWUCK_MSK +#define STM32_RCC_CFGR_PPRE2_POS 11U +#define STM32_RCC_CFGR_PPRE2_MSK (0x7UL << STM32_RCC_CFGR_PPRE2_POS) +#define STM32_RCC_CFGR_PPRE2 STM32_RCC_CFGR_PPRE2_MSK +#define STM32_RCC_CFGR_PPRE2_0 (0x1UL << STM32_RCC_CFGR_PPRE2_POS) +#define STM32_RCC_CFGR_PPRE2_1 (0x2UL << STM32_RCC_CFGR_PPRE2_POS) +#define STM32_RCC_CFGR_PPRE2_2 (0x4UL << STM32_RCC_CFGR_PPRE2_POS) + +#define STM32_RCC_CFGR_PPRE2_DIV1 (0x00000000UL) +#define STM32_RCC_CFGR_PPRE2_DIV2 (0x00002000UL) +#define STM32_RCC_CFGR_PPRE2_DIV4 (0x00002800UL) +#define STM32_RCC_CFGR_PPRE2_DIV8 (0x00003000UL) +#define STM32_RCC_CFGR_PPRE2_DIV16 (0x00003800UL) + +#define STM32_RCC_CFGR_STOPWUCK_POS 15U +#define STM32_RCC_CFGR_STOPWUCK_MSK (0x1UL << STM32_RCC_CFGR_STOPWUCK_POS) +#define STM32_RCC_CFGR_STOPWUCK STM32_RCC_CFGR_STOPWUCK_MSK /*!< MCOSEL CONFIGURATION */ -#define STM32_RCC_CFGR_MCOSEL_POS 24U -#define STM32_RCC_CFGR_MCOSEL_MSK (0xFUL << STM32_RCC_CFGR_MCOSEL_POS) -#define STM32_RCC_CFGR_MCOSEL STM32_RCC_CFGR_MCOSEL_MSK -#define STM32_RCC_CFGR_MCOSEL_0 (0x1UL << STM32_RCC_CFGR_MCOSEL_POS) -#define STM32_RCC_CFGR_MCOSEL_1 (0x2UL << STM32_RCC_CFGR_MCOSEL_POS) -#define STM32_RCC_CFGR_MCOSEL_2 (0x4UL << STM32_RCC_CFGR_MCOSEL_POS) -#define STM32_RCC_CFGR_MCOSEL_3 (0x8UL << STM32_RCC_CFGR_MCOSEL_POS) - -#define STM32_RCC_CFGR_MCOPRE_POS 28U -#define STM32_RCC_CFGR_MCOPRE_MSK (0x7UL << STM32_RCC_CFGR_MCOPRE_POS) -#define STM32_RCC_CFGR_MCOPRE STM32_RCC_CFGR_MCOPRE_MSK -#define STM32_RCC_CFGR_MCOPRE_0 (0x1UL << STM32_RCC_CFGR_MCOPRE_POS) -#define STM32_RCC_CFGR_MCOPRE_1 (0x2UL << STM32_RCC_CFGR_MCOPRE_POS) -#define STM32_RCC_CFGR_MCOPRE_2 (0x4UL << STM32_RCC_CFGR_MCOPRE_POS) - -#define STM32_RCC_CFGR_MCOPRE_DIV1 (0x00000000UL) -#define STM32_RCC_CFGR_MCOPRE_DIV2 (0x10000000UL) -#define STM32_RCC_CFGR_MCOPRE_DIV4 (0x20000000UL) -#define STM32_RCC_CFGR_MCOPRE_DIV8 (0x30000000UL) -#define STM32_RCC_CFGR_MCOPRE_DIV16 (0x40000000UL) +#define STM32_RCC_CFGR_MCOSEL_POS 24U +#define STM32_RCC_CFGR_MCOSEL_MSK (0xFUL << STM32_RCC_CFGR_MCOSEL_POS) +#define STM32_RCC_CFGR_MCOSEL STM32_RCC_CFGR_MCOSEL_MSK +#define STM32_RCC_CFGR_MCOSEL_0 (0x1UL << STM32_RCC_CFGR_MCOSEL_POS) +#define STM32_RCC_CFGR_MCOSEL_1 (0x2UL << STM32_RCC_CFGR_MCOSEL_POS) +#define STM32_RCC_CFGR_MCOSEL_2 (0x4UL << STM32_RCC_CFGR_MCOSEL_POS) +#define STM32_RCC_CFGR_MCOSEL_3 (0x8UL << STM32_RCC_CFGR_MCOSEL_POS) + +#define STM32_RCC_CFGR_MCOPRE_POS 28U +#define STM32_RCC_CFGR_MCOPRE_MSK (0x7UL << STM32_RCC_CFGR_MCOPRE_POS) +#define STM32_RCC_CFGR_MCOPRE STM32_RCC_CFGR_MCOPRE_MSK +#define STM32_RCC_CFGR_MCOPRE_0 (0x1UL << STM32_RCC_CFGR_MCOPRE_POS) +#define STM32_RCC_CFGR_MCOPRE_1 (0x2UL << STM32_RCC_CFGR_MCOPRE_POS) +#define STM32_RCC_CFGR_MCOPRE_2 (0x4UL << STM32_RCC_CFGR_MCOPRE_POS) + +#define STM32_RCC_CFGR_MCOPRE_DIV1 (0x00000000UL) +#define STM32_RCC_CFGR_MCOPRE_DIV2 (0x10000000UL) +#define STM32_RCC_CFGR_MCOPRE_DIV4 (0x20000000UL) +#define STM32_RCC_CFGR_MCOPRE_DIV8 (0x30000000UL) +#define STM32_RCC_CFGR_MCOPRE_DIV16 (0x40000000UL) /* LEGACY ALIASES */ -#define STM32_RCC_CFGR_MCO_PRE STM32_RCC_CFGR_MCOPRE -#define STM32_RCC_CFGR_MCO_PRE_1 STM32_RCC_CFGR_MCOPRE_DIV1 -#define STM32_RCC_CFGR_MCO_PRE_2 STM32_RCC_CFGR_MCOPRE_DIV2 -#define STM32_RCC_CFGR_MCO_PRE_4 STM32_RCC_CFGR_MCOPRE_DIV4 -#define STM32_RCC_CFGR_MCO_PRE_8 STM32_RCC_CFGR_MCOPRE_DIV8 -#define STM32_RCC_CFGR_MCO_PRE_16 STM32_RCC_CFGR_MCOPRE_DIV16 +#define STM32_RCC_CFGR_MCO_PRE STM32_RCC_CFGR_MCOPRE +#define STM32_RCC_CFGR_MCO_PRE_1 STM32_RCC_CFGR_MCOPRE_DIV1 +#define STM32_RCC_CFGR_MCO_PRE_2 STM32_RCC_CFGR_MCOPRE_DIV2 +#define STM32_RCC_CFGR_MCO_PRE_4 STM32_RCC_CFGR_MCOPRE_DIV4 +#define STM32_RCC_CFGR_MCO_PRE_8 STM32_RCC_CFGR_MCOPRE_DIV8 +#define STM32_RCC_CFGR_MCO_PRE_16 STM32_RCC_CFGR_MCOPRE_DIV16 /**************** BIT DEFINITION FOR STM32_RCC_PLLCFGR REGISTER ***********/ -#define STM32_RCC_PLLCFGR_PLLSRC_POS 0U +#define STM32_RCC_PLLCFGR_PLLSRC_POS 0U #define STM32_RCC_PLLCFGR_PLLSRC_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLSRC_POS) #define STM32_RCC_PLLCFGR_PLLSRC STM32_RCC_PLLCFGR_PLLSRC_MSK @@ -766,59 +764,59 @@ #define STM32_RCC_PLLCFGR_PLLSRC_HSE_POS 0U #define STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK \ (0x3UL << STM32_RCC_PLLCFGR_PLLSRC_HSE_POS) -#define STM32_RCC_PLLCFGR_PLLSRC_HSE STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK - -#define STM32_RCC_PLLCFGR_PLLM_POS 4U -#define STM32_RCC_PLLCFGR_PLLM_MSK (0x7UL << STM32_RCC_PLLCFGR_PLLM_POS) -#define STM32_RCC_PLLCFGR_PLLM STM32_RCC_PLLCFGR_PLLM_MSK -#define STM32_RCC_PLLCFGR_PLLM_0 (0x1UL << STM32_RCC_PLLCFGR_PLLM_POS) -#define STM32_RCC_PLLCFGR_PLLM_1 (0x2UL << STM32_RCC_PLLCFGR_PLLM_POS) -#define STM32_RCC_PLLCFGR_PLLM_2 (0x4UL << STM32_RCC_PLLCFGR_PLLM_POS) - -#define STM32_RCC_PLLCFGR_PLLN_POS 8U -#define STM32_RCC_PLLCFGR_PLLN_MSK (0x7FUL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN STM32_RCC_PLLCFGR_PLLN_MSK -#define STM32_RCC_PLLCFGR_PLLN_0 (0x01UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_1 (0x02UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_2 (0x04UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_3 (0x08UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_4 (0x10UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_5 (0x20UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_6 (0x40UL << STM32_RCC_PLLCFGR_PLLN_POS) - -#define STM32_RCC_PLLCFGR_PLLPEN_POS 16U -#define STM32_RCC_PLLCFGR_PLLPEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLPEN_POS) -#define STM32_RCC_PLLCFGR_PLLPEN STM32_RCC_PLLCFGR_PLLPEN_MSK -#define STM32_RCC_PLLCFGR_PLLP_POS 17U -#define STM32_RCC_PLLCFGR_PLLP_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLP_POS) -#define STM32_RCC_PLLCFGR_PLLP STM32_RCC_PLLCFGR_PLLP_MSK -#define STM32_RCC_PLLCFGR_PLLQEN_POS 20U -#define STM32_RCC_PLLCFGR_PLLQEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLQEN_POS) -#define STM32_RCC_PLLCFGR_PLLQEN STM32_RCC_PLLCFGR_PLLQEN_MSK - -#define STM32_RCC_PLLCFGR_PLLQ_POS 21U -#define STM32_RCC_PLLCFGR_PLLQ_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLQ_POS) -#define STM32_RCC_PLLCFGR_PLLQ STM32_RCC_PLLCFGR_PLLQ_MSK -#define STM32_RCC_PLLCFGR_PLLQ_0 (0x1UL << STM32_RCC_PLLCFGR_PLLQ_POS) -#define STM32_RCC_PLLCFGR_PLLQ_1 (0x2UL << STM32_RCC_PLLCFGR_PLLQ_POS) - -#define STM32_RCC_PLLCFGR_PLLREN_POS 24U -#define STM32_RCC_PLLCFGR_PLLREN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLREN_POS) -#define STM32_RCC_PLLCFGR_PLLREN STM32_RCC_PLLCFGR_PLLREN_MSK -#define STM32_RCC_PLLCFGR_PLLR_POS 25U -#define STM32_RCC_PLLCFGR_PLLR_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLR_POS) -#define STM32_RCC_PLLCFGR_PLLR STM32_RCC_PLLCFGR_PLLR_MSK -#define STM32_RCC_PLLCFGR_PLLR_0 (0x1UL << STM32_RCC_PLLCFGR_PLLR_POS) -#define STM32_RCC_PLLCFGR_PLLR_1 (0x2UL << STM32_RCC_PLLCFGR_PLLR_POS) - -#define STM32_RCC_PLLCFGR_PLLPDIV_POS 27U -#define STM32_RCC_PLLCFGR_PLLPDIV_MSK (0x1FUL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV STM32_RCC_PLLCFGR_PLLPDIV_MSK -#define STM32_RCC_PLLCFGR_PLLPDIV_0 (0x01UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV_1 (0x02UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV_2 (0x04UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV_3 (0x08UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV_4 (0x10UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLSRC_HSE STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK + +#define STM32_RCC_PLLCFGR_PLLM_POS 4U +#define STM32_RCC_PLLCFGR_PLLM_MSK (0x7UL << STM32_RCC_PLLCFGR_PLLM_POS) +#define STM32_RCC_PLLCFGR_PLLM STM32_RCC_PLLCFGR_PLLM_MSK +#define STM32_RCC_PLLCFGR_PLLM_0 (0x1UL << STM32_RCC_PLLCFGR_PLLM_POS) +#define STM32_RCC_PLLCFGR_PLLM_1 (0x2UL << STM32_RCC_PLLCFGR_PLLM_POS) +#define STM32_RCC_PLLCFGR_PLLM_2 (0x4UL << STM32_RCC_PLLCFGR_PLLM_POS) + +#define STM32_RCC_PLLCFGR_PLLN_POS 8U +#define STM32_RCC_PLLCFGR_PLLN_MSK (0x7FUL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN STM32_RCC_PLLCFGR_PLLN_MSK +#define STM32_RCC_PLLCFGR_PLLN_0 (0x01UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_1 (0x02UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_2 (0x04UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_3 (0x08UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_4 (0x10UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_5 (0x20UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_6 (0x40UL << STM32_RCC_PLLCFGR_PLLN_POS) + +#define STM32_RCC_PLLCFGR_PLLPEN_POS 16U +#define STM32_RCC_PLLCFGR_PLLPEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLPEN_POS) +#define STM32_RCC_PLLCFGR_PLLPEN STM32_RCC_PLLCFGR_PLLPEN_MSK +#define STM32_RCC_PLLCFGR_PLLP_POS 17U +#define STM32_RCC_PLLCFGR_PLLP_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLP_POS) +#define STM32_RCC_PLLCFGR_PLLP STM32_RCC_PLLCFGR_PLLP_MSK +#define STM32_RCC_PLLCFGR_PLLQEN_POS 20U +#define STM32_RCC_PLLCFGR_PLLQEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLQEN_POS) +#define STM32_RCC_PLLCFGR_PLLQEN STM32_RCC_PLLCFGR_PLLQEN_MSK + +#define STM32_RCC_PLLCFGR_PLLQ_POS 21U +#define STM32_RCC_PLLCFGR_PLLQ_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLQ_POS) +#define STM32_RCC_PLLCFGR_PLLQ STM32_RCC_PLLCFGR_PLLQ_MSK +#define STM32_RCC_PLLCFGR_PLLQ_0 (0x1UL << STM32_RCC_PLLCFGR_PLLQ_POS) +#define STM32_RCC_PLLCFGR_PLLQ_1 (0x2UL << STM32_RCC_PLLCFGR_PLLQ_POS) + +#define STM32_RCC_PLLCFGR_PLLREN_POS 24U +#define STM32_RCC_PLLCFGR_PLLREN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLREN_POS) +#define STM32_RCC_PLLCFGR_PLLREN STM32_RCC_PLLCFGR_PLLREN_MSK +#define STM32_RCC_PLLCFGR_PLLR_POS 25U +#define STM32_RCC_PLLCFGR_PLLR_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLR_POS) +#define STM32_RCC_PLLCFGR_PLLR STM32_RCC_PLLCFGR_PLLR_MSK +#define STM32_RCC_PLLCFGR_PLLR_0 (0x1UL << STM32_RCC_PLLCFGR_PLLR_POS) +#define STM32_RCC_PLLCFGR_PLLR_1 (0x2UL << STM32_RCC_PLLCFGR_PLLR_POS) + +#define STM32_RCC_PLLCFGR_PLLPDIV_POS 27U +#define STM32_RCC_PLLCFGR_PLLPDIV_MSK (0x1FUL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLPDIV STM32_RCC_PLLCFGR_PLLPDIV_MSK +#define STM32_RCC_PLLCFGR_PLLPDIV_0 (0x01UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLPDIV_1 (0x02UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLPDIV_2 (0x04UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLPDIV_3 (0x08UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLPDIV_4 (0x10UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) /**************** BIT DEFINITION FOR STM32_RCC_PLLSAI1CFGR REGISTER ********/ #define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS 8U @@ -840,7 +838,7 @@ #define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_6 \ (0x40UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS 16U +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS 16U #define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK \ (0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS) #define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK @@ -1701,102 +1699,100 @@ #define STM32_SYSCFG_I2CFMP(n) BIT(n + 21) /* Peripheral bits for STM32_RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB1_PWREN BIT(28) +#define STM32_RCC_PB1_PWREN BIT(28) -#define STM32_RCC_PB2_SYSCFGEN BIT(0) -#define STM32_RCC_PB2_USART1 BIT(14) +#define STM32_RCC_PB2_SYSCFGEN BIT(0) +#define STM32_RCC_PB2_USART1 BIT(14) -#define STM32_RCC_HB1_DMA1 BIT(0) -#define STM32_RCC_HB1_DMA2 BIT(1) +#define STM32_RCC_HB1_DMA1 BIT(0) +#define STM32_RCC_HB1_DMA2 BIT(1) -#define STM32_RCC_HB2_GPIOA BIT(0) -#define STM32_RCC_HB2_GPIOB BIT(1) -#define STM32_RCC_HB2_GPIOC BIT(2) -#define STM32_RCC_HB2_GPIOD BIT(3) -#define STM32_RCC_HB2_GPIOE BIT(4) -#define STM32_RCC_HB2_GPIOH BIT(7) -#define STM32_RCC_HB2_ADC1 BIT(13) +#define STM32_RCC_HB2_GPIOA BIT(0) +#define STM32_RCC_HB2_GPIOB BIT(1) +#define STM32_RCC_HB2_GPIOC BIT(2) +#define STM32_RCC_HB2_GPIOD BIT(3) +#define STM32_RCC_HB2_GPIOE BIT(4) +#define STM32_RCC_HB2_GPIOH BIT(7) +#define STM32_RCC_HB2_ADC1 BIT(13) /* Reset causes definitions */ /* Reset causes in RCC CSR register */ -#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG 0x60000000 -#define RESET_CAUSE_SFT 0x10000000 -#define RESET_CAUSE_POR 0x08000000 -#define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xff000000 -#define RESET_CAUSE_RMVF BIT(23) +#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR +#define RESET_CAUSE_WDG 0x60000000 +#define RESET_CAUSE_SFT 0x10000000 +#define RESET_CAUSE_POR 0x08000000 +#define RESET_CAUSE_PIN 0x04000000 +#define RESET_CAUSE_OTHER 0xff000000 +#define RESET_CAUSE_RMVF BIT(23) /* Power cause in PWR CSR register */ -#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR -#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_SCR -#define RESET_CAUSE_SBF BIT(8) -#define RESET_CAUSE_SBF_CLR BIT(8) +#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR +#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_SCR +#define RESET_CAUSE_SBF BIT(8) +#define RESET_CAUSE_SBF_CLR BIT(8) /* --- Watchdogs --- */ /* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_WUTE BIT(10) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_CR_WUTIE BIT(14) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_WUTWF BIT(2) -#define STM32_RTC_ISR_INITS BIT(4) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_ISR_WUTF BIT(9) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) +#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) +#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) +#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) +#define STM32_RTC_CR_BYPSHAD BIT(5) +#define STM32_RTC_CR_ALRAE BIT(8) +#define STM32_RTC_CR_WUTE BIT(10) +#define STM32_RTC_CR_ALRAIE BIT(12) +#define STM32_RTC_CR_WUTIE BIT(14) +#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) +#define STM32_RTC_ISR_ALRAWF BIT(0) +#define STM32_RTC_ISR_WUTWF BIT(2) +#define STM32_RTC_ISR_INITS BIT(4) +#define STM32_RTC_ISR_RSF BIT(5) +#define STM32_RTC_ISR_INITF BIT(6) +#define STM32_RTC_ISR_INIT BIT(7) +#define STM32_RTC_ISR_ALRAF BIT(8) +#define STM32_RTC_ISR_WUTF BIT(9) +#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) +#define STM32_RTC_PRER_A_MASK (0x7f << 16) +#define STM32_RTC_PRER_S_MASK (0x7fff << 0) +#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) +#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) +#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) +#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) +#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) +#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) +#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) +#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) +#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) +#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) +#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) #define STM32_RTC_CLEAR_FLAG(x) \ - (STM32_RTC_ISR = (~((x) | STM32_RTC_ISR_INIT) | \ - (STM32_RTC_ISR & STM32_RTC_ISR_INIT))) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 128 - -#define RTC_TR_PM_POS 22U -#define RTC_TR_PM_MSK (0x1UL << RTC_TR_PM_POS) -#define RTC_TR_PM RTC_TR_PM_MSK -#define RTC_TR_HT_POS 20U -#define RTC_TR_HT_MSK (0x3UL << RTC_TR_HT_POS) -#define RTC_TR_HT RTC_TR_HT_MSK -#define RTC_TR_HU_POS 16U -#define RTC_TR_HU_MSK (0xFUL << RTC_TR_HU_POS) -#define RTC_TR_HU RTC_TR_HU_MSK -#define RTC_TR_MNT_POS 12U -#define RTC_TR_MNT_MSK (0x7UL << RTC_TR_MNT_POS) -#define RTC_TR_MNT RTC_TR_MNT_MSK -#define RTC_TR_MNU_POS 8U -#define RTC_TR_MNU_MSK (0xFUL << RTC_TR_MNU_POS) -#define RTC_TR_MNU RTC_TR_MNU_MSK -#define RTC_TR_ST_POS 4U -#define RTC_TR_ST_MSK (0x7UL << RTC_TR_ST_POS) -#define RTC_TR_ST RTC_TR_ST_MSK -#define RTC_TR_SU_POS 0U -#define RTC_TR_SU_MSK (0xFUL << RTC_TR_SU_POS) -#define RTC_TR_SU RTC_TR_SU_MSK - - + (STM32_RTC_ISR = (~((x) | STM32_RTC_ISR_INIT) | \ + (STM32_RTC_ISR & STM32_RTC_ISR_INIT))) + +#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) +#define STM32_BKP_BYTES 128 + +#define RTC_TR_PM_POS 22U +#define RTC_TR_PM_MSK (0x1UL << RTC_TR_PM_POS) +#define RTC_TR_PM RTC_TR_PM_MSK +#define RTC_TR_HT_POS 20U +#define RTC_TR_HT_MSK (0x3UL << RTC_TR_HT_POS) +#define RTC_TR_HT RTC_TR_HT_MSK +#define RTC_TR_HU_POS 16U +#define RTC_TR_HU_MSK (0xFUL << RTC_TR_HU_POS) +#define RTC_TR_HU RTC_TR_HU_MSK +#define RTC_TR_MNT_POS 12U +#define RTC_TR_MNT_MSK (0x7UL << RTC_TR_MNT_POS) +#define RTC_TR_MNT RTC_TR_MNT_MSK +#define RTC_TR_MNU_POS 8U +#define RTC_TR_MNU_MSK (0xFUL << RTC_TR_MNU_POS) +#define RTC_TR_MNU RTC_TR_MNU_MSK +#define RTC_TR_ST_POS 4U +#define RTC_TR_ST_MSK (0x7UL << RTC_TR_ST_POS) +#define RTC_TR_ST RTC_TR_ST_MSK +#define RTC_TR_SU_POS 0U +#define RTC_TR_SU_MSK (0xFUL << RTC_TR_SU_POS) +#define RTC_TR_SU RTC_TR_SU_MSK /* --- SPI --- */ @@ -1813,8 +1809,8 @@ struct stm32_spi_regs { unsigned int crcpr; unsigned int rxcrcr; unsigned int txcrcr; - unsigned int i2scfgr; /* STM32L only */ - unsigned int i2spr; /* STM32L only */ + unsigned int i2scfgr; /* STM32L only */ + unsigned int i2spr; /* STM32L only */ }; /* Must be volatile, or compiler optimizes out repeated accesses */ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; @@ -1824,152 +1820,152 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) +#define STM32_SPI_CR1_BIDIMODE BIT(15) +#define STM32_SPI_CR1_BIDIOE BIT(14) +#define STM32_SPI_CR1_CRCEN BIT(13) +#define STM32_SPI_CR1_SSM BIT(9) +#define STM32_SPI_CR1_SSI BIT(8) +#define STM32_SPI_CR1_LSBFIRST BIT(7) +#define STM32_SPI_CR1_SPE BIT(6) +#define STM32_SPI_CR1_BR_DIV64R (5 << 3) +#define STM32_SPI_CR1_BR_DIV4R BIT(3) +#define STM32_SPI_CR1_MSTR BIT(2) +#define STM32_SPI_CR1_CPOL BIT(1) +#define STM32_SPI_CR1_CPHA BIT(0) +#define STM32_SPI_CR2_FRXTH BIT(12) +#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8) +#define STM32_SPI_CR2_TXEIE BIT(7) +#define STM32_SPI_CR2_RXNEIE BIT(6) +#define STM32_SPI_CR2_NSSP BIT(3) +#define STM32_SPI_CR2_SSOE BIT(2) +#define STM32_SPI_CR2_TXDMAEN BIT(1) +#define STM32_SPI_CR2_RXDMAEN BIT(0) + +#define STM32_SPI_SR_RXNE BIT(0) +#define STM32_SPI_SR_TXE BIT(1) +#define STM32_SPI_SR_CRCERR BIT(4) +#define STM32_SPI_SR_BSY BIT(7) +#define STM32_SPI_SR_FRLVL (3 << 9) +#define STM32_SPI_SR_FTLVL (3 << 11) /* --- Debug --- */ -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) +#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) +#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) /* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) +#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) #define STM32_FLASH_ACR_LATENCY_SHIFT (0) -#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) -#define STM32_FLASH_ACR_PRFTEN BIT(8) -#define STM32_FLASH_ACR_ICEN BIT(9) -#define STM32_FLASH_ACR_DCEN BIT(10) -#define STM32_FLASH_ACR_ICRST BIT(11) -#define STM32_FLASH_ACR_DCRST BIT(12) -#define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define FLASH_OPTKEYR_KEY1 0x08192A3B -#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_SR_BUSY BIT(16) -#define FLASH_SR_ERR_MASK (0xc3fa) -#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_STRT BIT(16) -#define FLASH_CR_OPTSTRT BIT(17) -#define FLASH_CR_OBL_LAUNCH BIT(27) -#define FLASH_CR_OPTLOCK BIT(30) -#define FLASH_CR_LOCK BIT(31) -#define FLASH_CR_PNB(sec) (((sec) & 0xff) << 3) -#define FLASH_CR_PNB_MASK FLASH_CR_PNB(0xff) -#define STM32_FLASH_ECCR REG32(STM32_FLASH_REGS_BASE + 0x18) -#define STM32_FLASH_OPTR REG32(STM32_FLASH_REGS_BASE + 0x20) -#define STM32_FLASH_PCROP1SR REG32(STM32_FLASH_REGS_BASE + 0x24) -#define STM32_FLASH_PCROP1ER REG32(STM32_FLASH_REGS_BASE + 0x28) -#define STM32_FLASH_WRP1AR REG32(STM32_FLASH_REGS_BASE + 0x2C) -#define STM32_FLASH_WRP1BR REG32(STM32_FLASH_REGS_BASE + 0x30) +#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) +#define STM32_FLASH_ACR_PRFTEN BIT(8) +#define STM32_FLASH_ACR_ICEN BIT(9) +#define STM32_FLASH_ACR_DCEN BIT(10) +#define STM32_FLASH_ACR_ICRST BIT(11) +#define STM32_FLASH_ACR_DCRST BIT(12) +#define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x04) +#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x08) +#define FLASH_KEYR_KEY1 0x45670123 +#define FLASH_KEYR_KEY2 0xCDEF89AB +#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x0c) +#define FLASH_OPTKEYR_KEY1 0x08192A3B +#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F +#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x10) +#define FLASH_SR_BUSY BIT(16) +#define FLASH_SR_ERR_MASK (0xc3fa) +#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x14) +#define FLASH_CR_PG BIT(0) +#define FLASH_CR_PER BIT(1) +#define FLASH_CR_STRT BIT(16) +#define FLASH_CR_OPTSTRT BIT(17) +#define FLASH_CR_OBL_LAUNCH BIT(27) +#define FLASH_CR_OPTLOCK BIT(30) +#define FLASH_CR_LOCK BIT(31) +#define FLASH_CR_PNB(sec) (((sec)&0xff) << 3) +#define FLASH_CR_PNB_MASK FLASH_CR_PNB(0xff) +#define STM32_FLASH_ECCR REG32(STM32_FLASH_REGS_BASE + 0x18) +#define STM32_FLASH_OPTR REG32(STM32_FLASH_REGS_BASE + 0x20) +#define STM32_FLASH_PCROP1SR REG32(STM32_FLASH_REGS_BASE + 0x24) +#define STM32_FLASH_PCROP1ER REG32(STM32_FLASH_REGS_BASE + 0x28) +#define STM32_FLASH_WRP1AR REG32(STM32_FLASH_REGS_BASE + 0x2C) +#define STM32_FLASH_WRP1BR REG32(STM32_FLASH_REGS_BASE + 0x30) /* Minimum number of bytes that can be written to flash */ -#define STM32_FLASH_MIN_WRITE_SIZE CONFIG_FLASH_WRITE_SIZE +#define STM32_FLASH_MIN_WRITE_SIZE CONFIG_FLASH_WRITE_SIZE -#define STM32_OPTB_USER_RDP REG32(STM32_OPTB_BASE + 0x00) -#define STM32_OPTB_WRP1AR REG32(STM32_OPTB_BASE + 0x18) -#define STM32_OPTB_WRP1BR REG32(STM32_OPTB_BASE + 0x20) +#define STM32_OPTB_USER_RDP REG32(STM32_OPTB_BASE + 0x00) +#define STM32_OPTB_WRP1AR REG32(STM32_OPTB_BASE + 0x18) +#define STM32_OPTB_WRP1BR REG32(STM32_OPTB_BASE + 0x20) /* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) +#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) +#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) +#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) +#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) +#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) +#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) -#define EXTI_RTC_ALR_EVENT BIT(18) +#define EXTI_RTC_ALR_EVENT BIT(18) /* --- ADC --- */ -#define STM32_ADC1_ISR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC1_ISR_ADRDY BIT(0) -#define STM32_ADC1_IER REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC1_IER_AWDIE BIT(7) -#define STM32_ADC1_IER_OVRIE BIT(4) -#define STM32_ADC1_IER_EOSEQIE BIT(3) -#define STM32_ADC1_IER_EOCIE BIT(2) -#define STM32_ADC1_IER_EOSMPIE BIT(1) -#define STM32_ADC1_IER_ADRDYIE BIT(0) - -#define STM32_ADC1_CR REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC1_CR_ADEN BIT(0) -#define STM32_ADC1_CR_ADDIS BIT(1) -#define STM32_ADC1_CR_ADSTP BIT(4) -#define STM32_ADC1_CR_ADVREGEN BIT(28) -#define STM32_ADC1_CR_DEEPPWD BIT(29) -#define STM32_ADC1_CR_ADCAL BIT(31) -#define STM32_ADC1_CFGR REG32(STM32_ADC1_BASE + 0x0C) +#define STM32_ADC1_ISR REG32(STM32_ADC1_BASE + 0x00) +#define STM32_ADC1_ISR_ADRDY BIT(0) +#define STM32_ADC1_IER REG32(STM32_ADC1_BASE + 0x04) +#define STM32_ADC1_IER_AWDIE BIT(7) +#define STM32_ADC1_IER_OVRIE BIT(4) +#define STM32_ADC1_IER_EOSEQIE BIT(3) +#define STM32_ADC1_IER_EOCIE BIT(2) +#define STM32_ADC1_IER_EOSMPIE BIT(1) +#define STM32_ADC1_IER_ADRDYIE BIT(0) + +#define STM32_ADC1_CR REG32(STM32_ADC1_BASE + 0x08) +#define STM32_ADC1_CR_ADEN BIT(0) +#define STM32_ADC1_CR_ADDIS BIT(1) +#define STM32_ADC1_CR_ADSTP BIT(4) +#define STM32_ADC1_CR_ADVREGEN BIT(28) +#define STM32_ADC1_CR_DEEPPWD BIT(29) +#define STM32_ADC1_CR_ADCAL BIT(31) +#define STM32_ADC1_CFGR REG32(STM32_ADC1_BASE + 0x0C) /* Analog watchdog channel selection */ -#define STM32_ADC1_CFGR_AWDCH_MASK (0x1f << 26) -#define STM32_ADC1_CFGR_AWDEN BIT(23) -#define STM32_ADC1_CFGR_AWDSGL BIT(22) -#define STM32_ADC1_CFGR_AUTDLY BIT(14) +#define STM32_ADC1_CFGR_AWDCH_MASK (0x1f << 26) +#define STM32_ADC1_CFGR_AWDEN BIT(23) +#define STM32_ADC1_CFGR_AWDSGL BIT(22) +#define STM32_ADC1_CFGR_AUTDLY BIT(14) /* Selects single vs continuous */ -#define STM32_ADC1_CFGR_CONT BIT(13) +#define STM32_ADC1_CFGR_CONT BIT(13) /* Selects ADC_DR overwrite vs preserve */ -#define STM32_ADC1_CFGR_OVRMOD BIT(12) +#define STM32_ADC1_CFGR_OVRMOD BIT(12) /* External trigger polarity selection */ -#define STM32_ADC1_CFGR_EXTEN_DIS (0 << 10) -#define STM32_ADC1_CFGR_EXTEN_RISE (1 << 10) -#define STM32_ADC1_CFGR_EXTEN_FALL (2 << 10) -#define STM32_ADC1_CFGR_EXTEN_BOTH (3 << 10) -#define STM32_ADC1_CFGR_EXTEN_MASK (3 << 10) -#define STM32_ADC1_CFGR_ALIGN BIT(5) +#define STM32_ADC1_CFGR_EXTEN_DIS (0 << 10) +#define STM32_ADC1_CFGR_EXTEN_RISE (1 << 10) +#define STM32_ADC1_CFGR_EXTEN_FALL (2 << 10) +#define STM32_ADC1_CFGR_EXTEN_BOTH (3 << 10) +#define STM32_ADC1_CFGR_EXTEN_MASK (3 << 10) +#define STM32_ADC1_CFGR_ALIGN BIT(5) /* External trigger selection */ -#define STM32_ADC1_CFGR_TRG0 (0 << 6) -#define STM32_ADC1_CFGR_TRG1 (1 << 6) -#define STM32_ADC1_CFGR_TRG2 (2 << 6) -#define STM32_ADC1_CFGR_TRG3 (3 << 6) -#define STM32_ADC1_CFGR_TRG4 (4 << 6) -#define STM32_ADC1_CFGR_TRG5 (5 << 6) -#define STM32_ADC1_CFGR_TRG6 (6 << 6) -#define STM32_ADC1_CFGR_TRG7 (7 << 6) -#define STM32_ADC1_CFGR_TRG_MASK (7 << 6) +#define STM32_ADC1_CFGR_TRG0 (0 << 6) +#define STM32_ADC1_CFGR_TRG1 (1 << 6) +#define STM32_ADC1_CFGR_TRG2 (2 << 6) +#define STM32_ADC1_CFGR_TRG3 (3 << 6) +#define STM32_ADC1_CFGR_TRG4 (4 << 6) +#define STM32_ADC1_CFGR_TRG5 (5 << 6) +#define STM32_ADC1_CFGR_TRG6 (6 << 6) +#define STM32_ADC1_CFGR_TRG7 (7 << 6) +#define STM32_ADC1_CFGR_TRG_MASK (7 << 6) /* Selects circular vs one-shot */ -#define STM32_ADC1_CFGR_DMACFG BIT(1) -#define STM32_ADC1_CFGR_DMAEN BIT(0) -#define STM32_ADC1_CFGR2 REG32(STM32_ADC1_BASE + 0x10) +#define STM32_ADC1_CFGR_DMACFG BIT(1) +#define STM32_ADC1_CFGR_DMAEN BIT(0) +#define STM32_ADC1_CFGR2 REG32(STM32_ADC1_BASE + 0x10) /* Sampling time selection - 1.5 ADC cycles min, 239.5 cycles max */ -#define STM32_ADC1_SMPR1 REG32(STM32_ADC1_BASE + 0x14) -#define STM32_ADC1_SMPR2 REG32(STM32_ADC1_BASE + 0x18) +#define STM32_ADC1_SMPR1 REG32(STM32_ADC1_BASE + 0x14) +#define STM32_ADC1_SMPR2 REG32(STM32_ADC1_BASE + 0x18) /* Macro to convert enum stm32_adc_smpr to SMP bits of the ADC_SMPR register */ -#define STM32_ADC1_SMPR_SMP(s) ((s) - 1) -#define STM32_ADC1_TR REG32(STM32_ADC1_BASE + 0x20) -#define STM32_ADC1_CHSELR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC1_DR REG32(STM32_ADC1_BASE + 0x40) -#define STM32_ADC1_JSQR REG32(STM32_ADC1_BASE + 0x4C) -#define STM32_ADC1_JDR1 REG32(STM32_ADC1_BASE + 0x80) -#define STM32_ADC1_JDR2 REG32(STM32_ADC1_BASE + 0x84) -#define STM32_ADC1_JDR3 REG32(STM32_ADC1_BASE + 0x88) -#define STM32_ADC1_JDR4 REG32(STM32_ADC1_BASE + 0x8C) -#define STM32_ADC1_CCR REG32(STM32_ADC1_BASE + 0x308) +#define STM32_ADC1_SMPR_SMP(s) ((s)-1) +#define STM32_ADC1_TR REG32(STM32_ADC1_BASE + 0x20) +#define STM32_ADC1_CHSELR REG32(STM32_ADC1_BASE + 0x28) +#define STM32_ADC1_DR REG32(STM32_ADC1_BASE + 0x40) +#define STM32_ADC1_JSQR REG32(STM32_ADC1_BASE + 0x4C) +#define STM32_ADC1_JDR1 REG32(STM32_ADC1_BASE + 0x80) +#define STM32_ADC1_JDR2 REG32(STM32_ADC1_BASE + 0x84) +#define STM32_ADC1_JDR3 REG32(STM32_ADC1_BASE + 0x88) +#define STM32_ADC1_JDR4 REG32(STM32_ADC1_BASE + 0x8C) +#define STM32_ADC1_CCR REG32(STM32_ADC1_BASE + 0x308) /* --- DMA --- */ @@ -2021,11 +2017,11 @@ enum dma_channel { /* Registers for a single channel of the DMA controller */ struct stm32_dma_chan { - uint32_t ccr; /* Control */ - uint32_t cndtr; /* Number of data to transfer */ - uint32_t cpar; /* Peripheral address */ - uint32_t cmar; /* Memory address */ - uint32_t reserved; + uint32_t ccr; /* Control */ + uint32_t cndtr; /* Number of data to transfer */ + uint32_t cpar; /* Peripheral address */ + uint32_t cmar; /* Memory address */ + uint32_t reserved; }; /* Always use stm32_dma_chan_t so volatile keyword is included! */ @@ -2036,8 +2032,8 @@ typedef stm32_dma_chan_t dma_chan_t; /* Registers for the DMA controller */ struct stm32_dma_regs { - uint32_t isr; - uint32_t ifcr; + uint32_t isr; + uint32_t ifcr; stm32_dma_chan_t chan[STM32_DMAC_COUNT]; }; @@ -2046,68 +2042,67 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - -#define STM32_DMA_CCR_CHANNEL(channel) (0) +#define STM32_DMA_CCR_CHANNEL(channel) (0) #define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE) #define STM32_DMA_REGS(channel) \ ((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS) -#define STM32_DMA_CSELR(channel) \ - REG32(((channel) < STM32_DMAC_PER_CTLR ? \ - STM32_DMA1_BASE : STM32_DMA2_BASE) + 0xA8) +#define STM32_DMA_CSELR(channel) \ + REG32(((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_BASE : \ + STM32_DMA2_BASE) + \ + 0xA8) /* Bits for DMA controller regs (isr and ifcr) */ -#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) +#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) #define STM32_DMA_ISR_MASK(channel, mask) \ ((mask) << STM32_DMA_CH_OFFSET(channel)) -#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) -#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) -#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) -#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) -#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) - -#define STM32_DMA_GIF BIT(0) -#define STM32_DMA_TCIF BIT(1) -#define STM32_DMA_HTIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_ALL 0xf - -#define STM32_DMA_GET_ISR(channel) \ - ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr = \ - ((STM32_DMA_REGS(channel)->isr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) -#define STM32_DMA_GET_IFCR(channel) \ - ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr = \ - ((STM32_DMA_REGS(channel)->ifcr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) - +#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) +#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) +#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) +#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) +#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) + +#define STM32_DMA_GIF BIT(0) +#define STM32_DMA_TCIF BIT(1) +#define STM32_DMA_HTIF BIT(2) +#define STM32_DMA_TEIF BIT(3) +#define STM32_DMA_ALL 0xf + +#define STM32_DMA_GET_ISR(channel) \ + ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) & \ + STM32_DMA_ALL) +#define STM32_DMA_SET_ISR(channel, val) \ + (STM32_DMA_REGS(channel)->isr = \ + ((STM32_DMA_REGS(channel)->isr & \ + ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) +#define STM32_DMA_GET_IFCR(channel) \ + ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) & \ + STM32_DMA_ALL) +#define STM32_DMA_SET_IFCR(channel, val) \ + (STM32_DMA_REGS(channel)->ifcr = \ + ((STM32_DMA_REGS(channel)->ifcr & \ + ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) /* Bits for DMA channel regs */ -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_TCIE BIT(1) -#define STM32_DMA_CCR_HTIE BIT(2) -#define STM32_DMA_CCR_TEIE BIT(3) -#define STM32_DMA_CCR_DIR BIT(4) -#define STM32_DMA_CCR_CIRC BIT(5) -#define STM32_DMA_CCR_PINC BIT(6) -#define STM32_DMA_CCR_MINC BIT(7) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) -#define STM32_DMA_CCR_PL_LOW (0 << 12) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) -#define STM32_DMA_CCR_PL_HIGH (2 << 12) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) -#define STM32_DMA_CCR_MEM2MEM BIT(14) +#define STM32_DMA_CCR_EN BIT(0) +#define STM32_DMA_CCR_TCIE BIT(1) +#define STM32_DMA_CCR_HTIE BIT(2) +#define STM32_DMA_CCR_TEIE BIT(3) +#define STM32_DMA_CCR_DIR BIT(4) +#define STM32_DMA_CCR_CIRC BIT(5) +#define STM32_DMA_CCR_PINC BIT(6) +#define STM32_DMA_CCR_MINC BIT(7) +#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) +#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) +#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) +#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) +#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) +#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) +#define STM32_DMA_CCR_PL_LOW (0 << 12) +#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) +#define STM32_DMA_CCR_PL_HIGH (2 << 12) +#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) +#define STM32_DMA_CCR_MEM2MEM BIT(14) #endif /* !__ASSEMBLER__ */ diff --git a/chip/stm32/registers-stm32l5.h b/chip/stm32/registers-stm32l5.h index 5055bc9e19..47f766e035 100644 --- a/chip/stm32/registers-stm32l5.h +++ b/chip/stm32/registers-stm32l5.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,93 +19,93 @@ #endif /****** STM32 specific Interrupt Numbers ********/ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_RTC_ALARM 2 -#define STM32_IRQ_FLASH 6 -#define STM32_IRQ_FLASH_S 7 -#define STM32_IRQ_RCC 9 -#define STM32_IRQ_RCC_S 10 -#define STM32_IRQ_EXTI0 11 -#define STM32_IRQ_EXTI1 12 -#define STM32_IRQ_EXTI2 13 -#define STM32_IRQ_EXTI3 14 -#define STM32_IRQ_EXTI4 15 -#define STM32_IRQ_EXTI5 16 -#define STM32_IRQ_EXTI6 17 -#define STM32_IRQ_EXTI7 18 -#define STM32_IRQ_EXTI8 19 -#define STM32_IRQ_EXTI9 20 -#define STM32_IRQ_EXTI10 21 -#define STM32_IRQ_EXTI11 22 -#define STM32_IRQ_EXTI12 23 -#define STM32_IRQ_EXTI13 24 -#define STM32_IRQ_EXTI14 25 -#define STM32_IRQ_EXTI15 26 -#define STM32_IRQ_DMAMUX_OVR 27 -#define STM32_IRQ_DMAMUX_OVR_S 28 -#define STM32_IRQ_DMA_CHANNEL_1 29 -#define STM32_IRQ_DMA_CHANNEL_2 30 -#define STM32_IRQ_DMA_CHANNEL_3 31 -#define STM32_IRQ_DMA_CHANNEL_4 32 -#define STM32_IRQ_DMA_CHANNEL_5 33 -#define STM32_IRQ_DMA_CHANNEL_6 34 -#define STM32_IRQ_DMA_CHANNEL_7 35 -#define STM32_IRQ_DMA_CHANNEL_8 36 -#define STM32_IRQ_ADC1 37 -#define STM32_IRQ_TIM1_BRK 41 -#define STM32_IRQ_TIM1_UP 42 -#define STM32_IRQ_TIM1_TRG_COM 43 -#define STM32_IRQ_TIM1_CC 44 -#define STM32_IRQ_TIM2 45 -#define STM32_IRQ_TIM3 46 -#define STM32_IRQ_TIM4 47 -#define STM32_IRQ_TIM5 48 -#define STM32_IRQ_TIM6 49 -#define STM32_IRQ_TIM7 50 -#define STM32_IRQ_TIM8_BRK 51 -#define STM32_IRQ_TIM8_UP 52 -#define STM32_IRQ_TIM8_TRG_COM 53 -#define STM32_IRQ_TIM8_CC 54 -#define STM32_IRQ_I2C1_EV 55 -#define STM32_IRQ_I2C1_ER 56 -#define STM32_IRQ_I2C2_EV 57 -#define STM32_IRQ_I2C2_ER 58 -#define STM32_IRQ_SPI1 59 -#define STM32_IRQ_SPI2 60 -#define STM32_IRQ_USART1 61 -#define STM32_IRQ_USART2 62 -#define STM32_IRQ_USART3 63 -#define STM32_IRQ_USART4 64 -#define STM32_IRQ_USART5 65 -#define STM32_IRQ_LPUART1 66 -#define STM32_IRQ_LPTIM1 67 -#define STM32_IRQ_LPTIM2 68 -#define STM32_IRQ_TIM15 69 -#define STM32_IRQ_TIM16 70 -#define STM32_IRQ_TIM17 71 -#define STM32_IRQ_COMP 72 -#define STM32_IRQ_USB_FS 73 -#define STM32_IRQ_CRS 74 -#define STM32_IRQ_FMC 75 -#define STM32_IRQ_DMA2_CHANNEL1 80 -#define STM32_IRQ_DMA2_CHANNEL2 81 -#define STM32_IRQ_DMA2_CHANNEL3 82 -#define STM32_IRQ_DMA2_CHANNEL4 83 -#define STM32_IRQ_DMA2_CHANNEL5 84 -#define STM32_IRQ_DMA2_CHANNEL6 85 -#define STM32_IRQ_DMA2_CHANNEL7 86 -#define STM32_IRQ_DMA2_CHANNEL8 87 +#define STM32_IRQ_WWDG 0 +#define STM32_IRQ_PVD 1 +#define STM32_IRQ_RTC_ALARM 2 +#define STM32_IRQ_FLASH 6 +#define STM32_IRQ_FLASH_S 7 +#define STM32_IRQ_RCC 9 +#define STM32_IRQ_RCC_S 10 +#define STM32_IRQ_EXTI0 11 +#define STM32_IRQ_EXTI1 12 +#define STM32_IRQ_EXTI2 13 +#define STM32_IRQ_EXTI3 14 +#define STM32_IRQ_EXTI4 15 +#define STM32_IRQ_EXTI5 16 +#define STM32_IRQ_EXTI6 17 +#define STM32_IRQ_EXTI7 18 +#define STM32_IRQ_EXTI8 19 +#define STM32_IRQ_EXTI9 20 +#define STM32_IRQ_EXTI10 21 +#define STM32_IRQ_EXTI11 22 +#define STM32_IRQ_EXTI12 23 +#define STM32_IRQ_EXTI13 24 +#define STM32_IRQ_EXTI14 25 +#define STM32_IRQ_EXTI15 26 +#define STM32_IRQ_DMAMUX_OVR 27 +#define STM32_IRQ_DMAMUX_OVR_S 28 +#define STM32_IRQ_DMA_CHANNEL_1 29 +#define STM32_IRQ_DMA_CHANNEL_2 30 +#define STM32_IRQ_DMA_CHANNEL_3 31 +#define STM32_IRQ_DMA_CHANNEL_4 32 +#define STM32_IRQ_DMA_CHANNEL_5 33 +#define STM32_IRQ_DMA_CHANNEL_6 34 +#define STM32_IRQ_DMA_CHANNEL_7 35 +#define STM32_IRQ_DMA_CHANNEL_8 36 +#define STM32_IRQ_ADC1 37 +#define STM32_IRQ_TIM1_BRK 41 +#define STM32_IRQ_TIM1_UP 42 +#define STM32_IRQ_TIM1_TRG_COM 43 +#define STM32_IRQ_TIM1_CC 44 +#define STM32_IRQ_TIM2 45 +#define STM32_IRQ_TIM3 46 +#define STM32_IRQ_TIM4 47 +#define STM32_IRQ_TIM5 48 +#define STM32_IRQ_TIM6 49 +#define STM32_IRQ_TIM7 50 +#define STM32_IRQ_TIM8_BRK 51 +#define STM32_IRQ_TIM8_UP 52 +#define STM32_IRQ_TIM8_TRG_COM 53 +#define STM32_IRQ_TIM8_CC 54 +#define STM32_IRQ_I2C1_EV 55 +#define STM32_IRQ_I2C1_ER 56 +#define STM32_IRQ_I2C2_EV 57 +#define STM32_IRQ_I2C2_ER 58 +#define STM32_IRQ_SPI1 59 +#define STM32_IRQ_SPI2 60 +#define STM32_IRQ_USART1 61 +#define STM32_IRQ_USART2 62 +#define STM32_IRQ_USART3 63 +#define STM32_IRQ_USART4 64 +#define STM32_IRQ_USART5 65 +#define STM32_IRQ_LPUART1 66 +#define STM32_IRQ_LPTIM1 67 +#define STM32_IRQ_LPTIM2 68 +#define STM32_IRQ_TIM15 69 +#define STM32_IRQ_TIM16 70 +#define STM32_IRQ_TIM17 71 +#define STM32_IRQ_COMP 72 +#define STM32_IRQ_USB_FS 73 +#define STM32_IRQ_CRS 74 +#define STM32_IRQ_FMC 75 +#define STM32_IRQ_DMA2_CHANNEL1 80 +#define STM32_IRQ_DMA2_CHANNEL2 81 +#define STM32_IRQ_DMA2_CHANNEL3 82 +#define STM32_IRQ_DMA2_CHANNEL4 83 +#define STM32_IRQ_DMA2_CHANNEL5 84 +#define STM32_IRQ_DMA2_CHANNEL6 85 +#define STM32_IRQ_DMA2_CHANNEL7 86 +#define STM32_IRQ_DMA2_CHANNEL8 87 /* To simplify code generation, define DMA channel 9..16 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_11 STM32_IRQ_DMA2_CHANNEL3 -#define STM32_IRQ_DMA_CHANNEL_12 STM32_IRQ_DMA2_CHANNEL4 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL5 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_15 STM32_IRQ_DMA2_CHANNEL7 -#define STM32_IRQ_DMA_CHANNEL_16 STM32_IRQ_DMA2_CHANNEL8 +#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 +#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 +#define STM32_IRQ_DMA_CHANNEL_11 STM32_IRQ_DMA2_CHANNEL3 +#define STM32_IRQ_DMA_CHANNEL_12 STM32_IRQ_DMA2_CHANNEL4 +#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL5 +#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL6 +#define STM32_IRQ_DMA_CHANNEL_15 STM32_IRQ_DMA2_CHANNEL7 +#define STM32_IRQ_DMA_CHANNEL_16 STM32_IRQ_DMA2_CHANNEL8 /* aliases for easier code sharing */ #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV @@ -113,269 +113,268 @@ #define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV #define STM32_IRQ_USB_LP STM32_IRQ_USB_FS - -#define PERIPH_BASE 0x40000000UL +#define PERIPH_BASE 0x40000000UL /*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x02000000UL) +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x02000000UL) /*!< APB1 peripherals */ -#define STM32_TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) -#define STM32_TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) -#define STM32_TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) -#define STM32_TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) -#define STM32_TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) -#define STM32_TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) -#define STM32_RTC_BASE (APB1PERIPH_BASE + 0x2800UL) -#define STM32_WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) -#define STM32_IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) -#define STM32_SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) -#define STM32_SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) -#define STM32_USART2_BASE (APB1PERIPH_BASE + 0x4400UL) -#define STM32_USART3_BASE (APB1PERIPH_BASE + 0x4800UL) -#define STM32_USART4_BASE (APB1PERIPH_BASE + 0x4c00UL) -#define STM32_USART5_BASE (APB1PERIPH_BASE + 0x5000UL) -#define STM32_I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) -#define STM32_I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) -#define STM32_I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) -#define STM32_CRS_BASE (APB1PERIPH_BASE + 0x6000UL) -#define STM32_PWR_BASE (APB1PERIPH_BASE + 0x7000UL) -#define STM32_DAC_BASE (APB1PERIPH_BASE + 0x7400UL) -#define STM32_DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) -#define STM32_OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) -#define STM32_LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) -#define STM32_LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) -#define STM32_I2C4_BASE (APB1PERIPH_BASE + 0x8400UL) -#define STM32_LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) -#define STM32_LPTIM3_BASE (APB1PERIPH_BASE + 0x9800UL) -#define STM32_FDCAN_RAM_BASE (APB1PERIPH_BASE + 0xA400UL) -#define STM32_CAN_RAM_BASE (APB1PERIPH_BASE + 0xAC00UL) -#define STM32_USB_FS_BASE (APB1PERIPH_BASE + 0xD400UL) -#define STM32_USB_CAN_SRAM_BASE (APB1PERIPH_BASE + 0xD800UL) -#define STM32_UCPD1_BASE (APB1PERIPH_BASE + 0xDC00UL) +#define STM32_TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define STM32_TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define STM32_TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define STM32_TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define STM32_TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define STM32_TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define STM32_RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define STM32_WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define STM32_IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define STM32_SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define STM32_SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define STM32_USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define STM32_USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define STM32_USART4_BASE (APB1PERIPH_BASE + 0x4c00UL) +#define STM32_USART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define STM32_I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define STM32_I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define STM32_I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define STM32_CRS_BASE (APB1PERIPH_BASE + 0x6000UL) +#define STM32_PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define STM32_DAC_BASE (APB1PERIPH_BASE + 0x7400UL) +#define STM32_DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) +#define STM32_OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) +#define STM32_LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define STM32_LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define STM32_I2C4_BASE (APB1PERIPH_BASE + 0x8400UL) +#define STM32_LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) +#define STM32_LPTIM3_BASE (APB1PERIPH_BASE + 0x9800UL) +#define STM32_FDCAN_RAM_BASE (APB1PERIPH_BASE + 0xA400UL) +#define STM32_CAN_RAM_BASE (APB1PERIPH_BASE + 0xAC00UL) +#define STM32_USB_FS_BASE (APB1PERIPH_BASE + 0xD400UL) +#define STM32_USB_CAN_SRAM_BASE (APB1PERIPH_BASE + 0xD800UL) +#define STM32_UCPD1_BASE (APB1PERIPH_BASE + 0xDC00UL) /*!< APB2 peripherals */ -#define STM32_SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) -#define STM32_EXTI_BASE (AHB1PERIPH_BASE + 0xf400UL) -#define STM32_TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) -#define STM32_SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) -#define STM32_TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) -#define STM32_USART1_BASE (APB2PERIPH_BASE + 0x3800UL) -#define STM32_TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) -#define STM32_TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) -#define STM32_TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define STM32_SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define STM32_EXTI_BASE (AHB1PERIPH_BASE + 0xf400UL) +#define STM32_TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define STM32_SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define STM32_TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define STM32_USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define STM32_TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define STM32_TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define STM32_TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) /*!< AHB1 peripherals */ -#define STM32_DMA1_BASE (AHB1PERIPH_BASE + 0x0000UL) -#define STM32_DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) -#define STM32_RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) -#define STM32_FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) -#define STM32_CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) -#define STM32_DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) -#define STM32_DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) -#define STM32_DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) -#define STM32_DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) -#define STM32_DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) -#define STM32_DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) -#define STM32_DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) -#define STM32_DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) -#define STM32_DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) -#define STM32_DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) -#define STM32_DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) -#define STM32_DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) -#define STM32_DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) -#define STM32_DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) -#define STM32_DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) -#define STM32_DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) +#define STM32_DMA1_BASE (AHB1PERIPH_BASE + 0x0000UL) +#define STM32_DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define STM32_DMAMUX_BASE (AHB1PERIPH_BASE + 0x0800UL) +#define STM32_RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define STM32_FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define STM32_CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) +#define STM32_DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define STM32_DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define STM32_DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define STM32_DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define STM32_DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define STM32_DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define STM32_DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define STM32_DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) +#define STM32_DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define STM32_DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define STM32_DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define STM32_DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define STM32_DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define STM32_DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define STM32_DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define STM32_DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) /*!< AHB2 peripherals */ -#define STM32_GPIOA_BASE (AHB2PERIPH_BASE + 0x20000UL) -#define STM32_GPIOB_BASE (AHB2PERIPH_BASE + 0x20400UL) -#define STM32_GPIOC_BASE (AHB2PERIPH_BASE + 0x20800UL) -#define STM32_GPIOD_BASE (AHB2PERIPH_BASE + 0x20C00UL) -#define STM32_GPIOE_BASE (AHB2PERIPH_BASE + 0x21000UL) -#define STM32_GPIOF_BASE (AHB2PERIPH_BASE + 0x21400UL) -#define STM32_GPIOG_BASE (AHB2PERIPH_BASE + 0x21800UL) -#define STM32_GPIOH_BASE (AHB2PERIPH_BASE + 0x21C00UL) -#define STM32_RNG_BASE (AHB2PERIPH_BASE + 0xC4000UL) +#define STM32_GPIOA_BASE (AHB2PERIPH_BASE + 0x20000UL) +#define STM32_GPIOB_BASE (AHB2PERIPH_BASE + 0x20400UL) +#define STM32_GPIOC_BASE (AHB2PERIPH_BASE + 0x20800UL) +#define STM32_GPIOD_BASE (AHB2PERIPH_BASE + 0x20C00UL) +#define STM32_GPIOE_BASE (AHB2PERIPH_BASE + 0x21000UL) +#define STM32_GPIOF_BASE (AHB2PERIPH_BASE + 0x21400UL) +#define STM32_GPIOG_BASE (AHB2PERIPH_BASE + 0x21800UL) +#define STM32_GPIOH_BASE (AHB2PERIPH_BASE + 0x21C00UL) +#define STM32_RNG_BASE (AHB2PERIPH_BASE + 0xC4000UL) /* Debug MCU registers base address */ -#define STM32_PACKAGE_BASE 0x0BFA0500UL -#define STM32_UID_BASE 0x0BFA0590UL -#define STM32_FLASHSIZE_BASE 0x0BFA05E0UL +#define STM32_PACKAGE_BASE 0x0BFA0500UL +#define STM32_UID_BASE 0x0BFA0590UL +#define STM32_FLASHSIZE_BASE 0x0BFA05E0UL -#define STM32_FLASH_REGS_BASE STM32_FLASH_R_BASE -#define STM32_UNIQUE_ID_BASE STM32_UID_BASE +#define STM32_FLASH_REGS_BASE STM32_FLASH_R_BASE +#define STM32_UNIQUE_ID_BASE STM32_UID_BASE #ifndef __ASSEMBLER__ /* Register definitions */ /* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_UESM BIT(1) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) - -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR2_SWAP BIT(15) - -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) -#define STM32_USART_CR3_OVRDIS BIT(12) +#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) +#define STM32_USART_CR1_UE BIT(0) +#define STM32_USART_CR1_UESM BIT(1) +#define STM32_USART_CR1_RE BIT(2) +#define STM32_USART_CR1_TE BIT(3) +#define STM32_USART_CR1_RXNEIE BIT(5) +#define STM32_USART_CR1_TCIE BIT(6) +#define STM32_USART_CR1_TXEIE BIT(7) +#define STM32_USART_CR1_PS BIT(9) +#define STM32_USART_CR1_PCE BIT(10) +#define STM32_USART_CR1_M BIT(12) +#define STM32_USART_CR1_OVER8 BIT(15) + +#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) +#define STM32_USART_CR2_SWAP BIT(15) + +#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) +#define STM32_USART_CR3_EIE BIT(0) +#define STM32_USART_CR3_DMAR BIT(6) +#define STM32_USART_CR3_DMAT BIT(7) +#define STM32_USART_CR3_ONEBIT BIT(11) +#define STM32_USART_CR3_OVRDIS BIT(12) #define STM32_USART_CR3_WUS_START_BIT (2 << 20) -#define STM32_USART_CR3_WUFIE BIT(22) - -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) -#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) -#define STM32_USART_ICR_ORECF BIT(3) -#define STM32_USART_ICR_TCCF BIT(6) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) -#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) +#define STM32_USART_CR3_WUFIE BIT(22) + +#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) +#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) +#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) +#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) +#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) +#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) +#define STM32_USART_ICR_ORECF BIT(3) +#define STM32_USART_ICR_TCCF BIT(6) +#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) +#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) +#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) /* register alias */ -#define STM32_USART_SR(base) STM32_USART_ISR(base) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) +#define STM32_USART_SR(base) STM32_USART_ISR(base) +#define STM32_USART_SR_ORE BIT(3) +#define STM32_USART_SR_RXNE BIT(5) +#define STM32_USART_SR_TC BIT(6) +#define STM32_USART_SR_TXE BIT(7) /* --- GPIO --- */ -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) -#define STM32_GPIO_BRR(b) REG32((b) + 0x28) -#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4x6 */ - -#define GPIO_ALT_F0 0x0 -#define GPIO_ALT_F1 0x1 -#define GPIO_ALT_F2 0x2 -#define GPIO_ALT_F3 0x3 -#define GPIO_ALT_F4 0x4 -#define GPIO_ALT_F5 0x5 -#define GPIO_ALT_F6 0x6 -#define GPIO_ALT_F7 0x7 -#define GPIO_ALT_F8 0x8 -#define GPIO_ALT_F9 0x9 -#define GPIO_ALT_FA 0xA -#define GPIO_ALT_FB 0xB -#define GPIO_ALT_FC 0xC -#define GPIO_ALT_FD 0xD -#define GPIO_ALT_FE 0xE -#define GPIO_ALT_FF 0xF +#define STM32_GPIO_MODER(b) REG32((b) + 0x00) +#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) +#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) +#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) +#define STM32_GPIO_IDR(b) REG16((b) + 0x10) +#define STM32_GPIO_ODR(b) REG16((b) + 0x14) +#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) +#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) +#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) +#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) +#define STM32_GPIO_BRR(b) REG32((b) + 0x28) +#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4x6 */ + +#define GPIO_ALT_F0 0x0 +#define GPIO_ALT_F1 0x1 +#define GPIO_ALT_F2 0x2 +#define GPIO_ALT_F3 0x3 +#define GPIO_ALT_F4 0x4 +#define GPIO_ALT_F5 0x5 +#define GPIO_ALT_F6 0x6 +#define GPIO_ALT_F7 0x7 +#define GPIO_ALT_F8 0x8 +#define GPIO_ALT_F9 0x9 +#define GPIO_ALT_FA 0xA +#define GPIO_ALT_FB 0xB +#define GPIO_ALT_FC 0xC +#define GPIO_ALT_FD 0xD +#define GPIO_ALT_FE 0xE +#define GPIO_ALT_FF 0xF /* --- I2C --- */ -#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_TXIE BIT(1) -#define STM32_I2C_CR1_RXIE BIT(2) -#define STM32_I2C_CR1_ADDRIE BIT(3) -#define STM32_I2C_CR1_NACKIE BIT(4) -#define STM32_I2C_CR1_STOPIE BIT(5) -#define STM32_I2C_CR1_ERRIE BIT(7) -#define STM32_I2C_CR1_WUPEN BIT(18) -#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_RD_WRN BIT(10) -#define STM32_I2C_CR2_START BIT(13) -#define STM32_I2C_CR2_STOP BIT(14) -#define STM32_I2C_CR2_NACK BIT(15) -#define STM32_I2C_CR2_RELOAD BIT(24) -#define STM32_I2C_CR2_AUTOEND BIT(25) -#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_ISR_TXE BIT(0) -#define STM32_I2C_ISR_TXIS BIT(1) -#define STM32_I2C_ISR_RXNE BIT(2) -#define STM32_I2C_ISR_ADDR BIT(3) -#define STM32_I2C_ISR_NACK BIT(4) -#define STM32_I2C_ISR_STOP BIT(5) -#define STM32_I2C_ISR_TC BIT(6) -#define STM32_I2C_ISR_TCR BIT(7) -#define STM32_I2C_ISR_BERR BIT(8) -#define STM32_I2C_ISR_ARLO BIT(9) -#define STM32_I2C_ISR_OVR BIT(10) -#define STM32_I2C_ISR_PECERR BIT(11) -#define STM32_I2C_ISR_TIMEOUT BIT(12) -#define STM32_I2C_ISR_ALERT BIT(13) -#define STM32_I2C_ISR_BUSY BIT(15) -#define STM32_I2C_ISR_DIR BIT(16) -#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe) -#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_ICR_ADDRCF BIT(3) -#define STM32_I2C_ICR_NACKCF BIT(4) -#define STM32_I2C_ICR_STOPCF BIT(5) -#define STM32_I2C_ICR_BERRCF BIT(8) -#define STM32_I2C_ICR_ARLOCF BIT(9) -#define STM32_I2C_ICR_OVRCF BIT(10) -#define STM32_I2C_ICR_TIMEOUTCF BIT(12) -#define STM32_I2C_ICR_ALL 0x3F38 -#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) -#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) -#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) +#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) +#define STM32_I2C_CR1_PE BIT(0) +#define STM32_I2C_CR1_TXIE BIT(1) +#define STM32_I2C_CR1_RXIE BIT(2) +#define STM32_I2C_CR1_ADDRIE BIT(3) +#define STM32_I2C_CR1_NACKIE BIT(4) +#define STM32_I2C_CR1_STOPIE BIT(5) +#define STM32_I2C_CR1_ERRIE BIT(7) +#define STM32_I2C_CR1_WUPEN BIT(18) +#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) +#define STM32_I2C_CR2_RD_WRN BIT(10) +#define STM32_I2C_CR2_START BIT(13) +#define STM32_I2C_CR2_STOP BIT(14) +#define STM32_I2C_CR2_NACK BIT(15) +#define STM32_I2C_CR2_RELOAD BIT(24) +#define STM32_I2C_CR2_AUTOEND BIT(25) +#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) +#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) +#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) +#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) +#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) +#define STM32_I2C_ISR_TXE BIT(0) +#define STM32_I2C_ISR_TXIS BIT(1) +#define STM32_I2C_ISR_RXNE BIT(2) +#define STM32_I2C_ISR_ADDR BIT(3) +#define STM32_I2C_ISR_NACK BIT(4) +#define STM32_I2C_ISR_STOP BIT(5) +#define STM32_I2C_ISR_TC BIT(6) +#define STM32_I2C_ISR_TCR BIT(7) +#define STM32_I2C_ISR_BERR BIT(8) +#define STM32_I2C_ISR_ARLO BIT(9) +#define STM32_I2C_ISR_OVR BIT(10) +#define STM32_I2C_ISR_PECERR BIT(11) +#define STM32_I2C_ISR_TIMEOUT BIT(12) +#define STM32_I2C_ISR_ALERT BIT(13) +#define STM32_I2C_ISR_BUSY BIT(15) +#define STM32_I2C_ISR_DIR BIT(16) +#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe) +#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) +#define STM32_I2C_ICR_ADDRCF BIT(3) +#define STM32_I2C_ICR_NACKCF BIT(4) +#define STM32_I2C_ICR_STOPCF BIT(5) +#define STM32_I2C_ICR_BERRCF BIT(8) +#define STM32_I2C_ICR_ARLOCF BIT(9) +#define STM32_I2C_ICR_OVRCF BIT(10) +#define STM32_I2C_ICR_TIMEOUTCF BIT(12) +#define STM32_I2C_ICR_ALL 0x3F38 +#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) +#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) +#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) /* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CR1 REG32(STM32_PWR_BASE + 0x00) -#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x04) -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x10) -#define STM32_PWR_SCR REG32(STM32_PWR_BASE + 0x18) - -#define PWR_CR1_LPMS_POS 0U -#define PWR_CR1_LPMS_MSK (0x7UL << PWR_CR1_LPMS_POS) -#define PWR_CR1_LPMS PWR_CR1_LPMS_MSK -#define PWR_CR1_LPMS_STOP0 (0x00000000UL) -#define PWR_CR1_LPMS_STOP1_POS 0U -#define PWR_CR1_LPMS_STOP1_MSK (0x1UL << PWR_CR1_LPMS_STOP1_POS) -#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_MSK -#define PWR_CR1_LPMS_STOP2_POS 1U -#define PWR_CR1_LPMS_STOP2_MSK (0x1UL << PWR_CR1_LPMS_STOP2_POS) -#define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_MSK -#define PWR_CR1_LPMS_STANDBY_POS 0U -#define PWR_CR1_LPMS_STANDBY_MSK (0x3UL << PWR_CR1_LPMS_STANDBY_POS) -#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_MSK -#define PWR_CR1_LPMS_SHUTDOWN_POS 2U -#define PWR_CR1_LPMS_SHUTDOWN_MSK (0x1UL << PWR_CR1_LPMS_SHUTDOWN_POS) -#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_MSK -#define PWR_CR1_VOS_POS 9U -#define PWR_CR1_VOS_MSK (0x3UL << PWR_CR1_VOS_POS) -#define PWR_CR1_VOS PWR_CR1_VOS_MSK -#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_POS) -#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_POS) - -#define STM32_PWR_CR2_IOSV_POS 9U -#define STM32_PWR_CR2_IOSV_MASK BIT(STM32_PWR_CR2_IOSV_POS) -#define STM32_PWR_CR2_IOSV STM32_PWR_CR2_IOSV_MASK -#define STM32_PWR_CR2_USV_POS 10U -#define STM32_PWR_CR2_USV_MASK BIT(STM32_PWR_CR2_USV_POS) -#define STM32_PWR_CR2_USV STM32_PWR_CR2_USV_MASK - +#define STM32_PWR_CR1 REG32(STM32_PWR_BASE + 0x00) +#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x04) +#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x10) +#define STM32_PWR_SCR REG32(STM32_PWR_BASE + 0x18) + +#define PWR_CR1_LPMS_POS 0U +#define PWR_CR1_LPMS_MSK (0x7UL << PWR_CR1_LPMS_POS) +#define PWR_CR1_LPMS PWR_CR1_LPMS_MSK +#define PWR_CR1_LPMS_STOP0 (0x00000000UL) +#define PWR_CR1_LPMS_STOP1_POS 0U +#define PWR_CR1_LPMS_STOP1_MSK (0x1UL << PWR_CR1_LPMS_STOP1_POS) +#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_MSK +#define PWR_CR1_LPMS_STOP2_POS 1U +#define PWR_CR1_LPMS_STOP2_MSK (0x1UL << PWR_CR1_LPMS_STOP2_POS) +#define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_MSK +#define PWR_CR1_LPMS_STANDBY_POS 0U +#define PWR_CR1_LPMS_STANDBY_MSK (0x3UL << PWR_CR1_LPMS_STANDBY_POS) +#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_MSK +#define PWR_CR1_LPMS_SHUTDOWN_POS 2U +#define PWR_CR1_LPMS_SHUTDOWN_MSK (0x1UL << PWR_CR1_LPMS_SHUTDOWN_POS) +#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_MSK +#define PWR_CR1_VOS_POS 9U +#define PWR_CR1_VOS_MSK (0x3UL << PWR_CR1_VOS_POS) +#define PWR_CR1_VOS PWR_CR1_VOS_MSK +#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_POS) +#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_POS) + +#define STM32_PWR_CR2_IOSV_POS 9U +#define STM32_PWR_CR2_IOSV_MASK BIT(STM32_PWR_CR2_IOSV_POS) +#define STM32_PWR_CR2_IOSV STM32_PWR_CR2_IOSV_MASK +#define STM32_PWR_CR2_USV_POS 10U +#define STM32_PWR_CR2_USV_MASK BIT(STM32_PWR_CR2_USV_POS) +#define STM32_PWR_CR2_USV STM32_PWR_CR2_USV_MASK /* --- Macro usage in ec code --- */ #define STM32_RCC_AHB2ENR_GPIOMASK \ @@ -387,139 +386,137 @@ #define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4) #define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5) #define STM32_RCC_ICSCR_MSIRANGE_MASK STM32_RCC_CR_MSIRANGE_MSK -#define STM32_RCC_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN +#define STM32_RCC_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN -#define STM32_RCC_PB2_TIM1 STM32_RCC_APB2ENR_TIM1EN -#define STM32_RCC_PB2_TIM15 STM32_RCC_APB2ENR_TIM15EN -#define STM32_RCC_PB2_TIM16 STM32_RCC_APB2ENR_TIM16EN +#define STM32_RCC_PB2_TIM1 STM32_RCC_APB2ENR_TIM1EN +#define STM32_RCC_PB2_TIM15 STM32_RCC_APB2ENR_TIM15EN +#define STM32_RCC_PB2_TIM16 STM32_RCC_APB2ENR_TIM16EN #ifndef CHIP_VARIANT_STM32L431X -#define STM32_RCC_PB2_TIM8 BIT(13) +#define STM32_RCC_PB2_TIM8 BIT(13) #endif #define STM32_RCC_PWREN STM32_RCC_APB1ENR1_PWREN -#define STM32_RCC_AHB2ENR_GPIO_PORTA BIT(0) -#define STM32_RCC_AHB2ENR_GPIO_PORTB BIT(1) -#define STM32_RCC_AHB2ENR_GPIO_PORTC BIT(2) -#define STM32_RCC_AHB2ENR_GPIO_PORTD BIT(3) -#define STM32_RCC_AHB2ENR_GPIO_PORTE BIT(4) -#define STM32_RCC_AHB2ENR_GPIO_PORTH BIT(7) +#define STM32_RCC_AHB2ENR_GPIO_PORTA BIT(0) +#define STM32_RCC_AHB2ENR_GPIO_PORTB BIT(1) +#define STM32_RCC_AHB2ENR_GPIO_PORTC BIT(2) +#define STM32_RCC_AHB2ENR_GPIO_PORTD BIT(3) +#define STM32_RCC_AHB2ENR_GPIO_PORTE BIT(4) +#define STM32_RCC_AHB2ENR_GPIO_PORTH BIT(7) #define STM32_RCC_CCIPR_USART1SEL_SHIFT (0) -#define STM32_RCC_CCIPR_USART1SEL_MASK (3 << STM32_RCC_CCIPR_USART1SEL_SHIFT) +#define STM32_RCC_CCIPR_USART1SEL_MASK (3 << STM32_RCC_CCIPR_USART1SEL_SHIFT) #define STM32_RCC_CCIPR_USART2SEL_SHIFT (2) -#define STM32_RCC_CCIPR_USART2SEL_MASK (3 << STM32_RCC_CCIPR_USART2SEL_SHIFT) +#define STM32_RCC_CCIPR_USART2SEL_MASK (3 << STM32_RCC_CCIPR_USART2SEL_SHIFT) #define STM32_RCC_CCIPR_USART3SEL_SHIFT (4) -#define STM32_RCC_CCIPR_USART3SEL_MASK (3 << STM32_RCC_CCIPR_USART3SEL_SHIFT) +#define STM32_RCC_CCIPR_USART3SEL_MASK (3 << STM32_RCC_CCIPR_USART3SEL_SHIFT) #define STM32_RCC_CCIPR_UART4SEL_SHIFT (6) -#define STM32_RCC_CCIPR_UART4SEL_MASK (3 << STM32_RCC_CCIPR_UART4SEL_SHIFT) +#define STM32_RCC_CCIPR_UART4SEL_MASK (3 << STM32_RCC_CCIPR_UART4SEL_SHIFT) #define STM32_RCC_CCIPR_UART5SEL_SHIFT (8) -#define STM32_RCC_CCIPR_UART5SEL_MASK (3 << STM32_RCC_CCIPR_UART5SEL_SHIFT) +#define STM32_RCC_CCIPR_UART5SEL_MASK (3 << STM32_RCC_CCIPR_UART5SEL_SHIFT) #define STM32_RCC_CCIPR_LPUART1SEL_SHIFT (10) -#define STM32_RCC_CCIPR_LPUART1SEL_MASK (3 << STM32_RCC_CCIPR_LPUART1SEL_SHIFT) +#define STM32_RCC_CCIPR_LPUART1SEL_MASK (3 << STM32_RCC_CCIPR_LPUART1SEL_SHIFT) #define STM32_RCC_CCIPR_I2C1SEL_SHIFT (12) -#define STM32_RCC_CCIPR_I2C1SEL_MASK (3 << STM32_RCC_CCIPR_I2C1SEL_SHIFT) +#define STM32_RCC_CCIPR_I2C1SEL_MASK (3 << STM32_RCC_CCIPR_I2C1SEL_SHIFT) #define STM32_RCC_CCIPR_I2C2SEL_SHIFT (14) -#define STM32_RCC_CCIPR_I2C2SEL_MASK (3 << STM32_RCC_CCIPR_I2C2SEL_SHIFT) +#define STM32_RCC_CCIPR_I2C2SEL_MASK (3 << STM32_RCC_CCIPR_I2C2SEL_SHIFT) #define STM32_RCC_CCIPR_I2C3SEL_SHIFT (16) -#define STM32_RCC_CCIPR_I2C3SEL_MASK (3 << STM32_RCC_CCIPR_I2C3SEL_SHIFT) +#define STM32_RCC_CCIPR_I2C3SEL_MASK (3 << STM32_RCC_CCIPR_I2C3SEL_SHIFT) #define STM32_RCC_CCIPR_LPTIM1SEL_SHIFT (18) -#define STM32_RCC_CCIPR_LPTIM1SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM1SEL_SHIFT) +#define STM32_RCC_CCIPR_LPTIM1SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM1SEL_SHIFT) #define STM32_RCC_CCIPR_LPTIM2SEL_SHIFT (20) -#define STM32_RCC_CCIPR_LPTIM2SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM2SEL_SHIFT) +#define STM32_RCC_CCIPR_LPTIM2SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM2SEL_SHIFT) #define STM32_RCC_CCIPR_SAI1SEL_SHIFT (22) -#define STM32_RCC_CCIPR_SAI1SEL_MASK (3 << STM32_RCC_CCIPR_SAI1SEL_SHIFT) +#define STM32_RCC_CCIPR_SAI1SEL_MASK (3 << STM32_RCC_CCIPR_SAI1SEL_SHIFT) #define STM32_RCC_CCIPR_SAI2SEL_SHIFT (24) -#define STM32_RCC_CCIPR_SAI2SEL_MASK (3 << STM32_RCC_CCIPR_SAI2SEL_SHIFT) +#define STM32_RCC_CCIPR_SAI2SEL_MASK (3 << STM32_RCC_CCIPR_SAI2SEL_SHIFT) #define STM32_RCC_CCIPR_CLK48SEL_SHIFT (26) -#define STM32_RCC_CCIPR_CLK48SEL_MASK (3 << STM32_RCC_CCIPR_CLK48SEL_SHIFT) +#define STM32_RCC_CCIPR_CLK48SEL_MASK (3 << STM32_RCC_CCIPR_CLK48SEL_SHIFT) #define STM32_RCC_CCIPR_ADCSEL_SHIFT (28) -#define STM32_RCC_CCIPR_ADCSEL_MASK (3 << STM32_RCC_CCIPR_ADCSEL_SHIFT) +#define STM32_RCC_CCIPR_ADCSEL_MASK (3 << STM32_RCC_CCIPR_ADCSEL_SHIFT) #define STM32_RCC_CCIPR_SWPMI1SEL_SHIFT (30) -#define STM32_RCC_CCIPR_SWPMI1SEL_MASK BIT(STM32_RCC_CCIPR_SWPMI1SEL_SHIFT) +#define STM32_RCC_CCIPR_SWPMI1SEL_MASK BIT(STM32_RCC_CCIPR_SWPMI1SEL_SHIFT) #define STM32_RCC_CCIPR_DFSDM1SEL_SHIFT (31) -#define STM32_RCC_CCIPR_DFSDM1SEL_MASK BIT(STM32_RCC_CCIPR_DFSDM1SEL_SHIFT) +#define STM32_RCC_CCIPR_DFSDM1SEL_MASK BIT(STM32_RCC_CCIPR_DFSDM1SEL_SHIFT) /* Possible clock sources for each peripheral */ -#define STM32_RCC_CCIPR_UART_PCLK 0 -#define STM32_RCC_CCIPR_UART_SYSCLK 1 -#define STM32_RCC_CCIPR_UART_HSI16 2 -#define STM32_RCC_CCIPR_UART_LSE 3 - -#define STM32_RCC_CCIPR_I2C_PCLK 0 -#define STM32_RCC_CCIPR_I2C_SYSCLK 1 -#define STM32_RCC_CCIPR_I2C_HSI16 2 - -#define STM32_RCC_CCIPR_LPTIM_PCLK 0 -#define STM32_RCC_CCIPR_LPTIM_LSI 1 -#define STM32_RCC_CCIPR_LPTIM_HSI16 2 -#define STM32_RCC_CCIPR_LPTIM_LSE 3 - -#define STM32_RCC_CCIPR_SAI_PLLSAI1CLK 0 -#define STM32_RCC_CCIPR_SAI_PLLSAI2CLK 1 -#define STM32_RCC_CCIPR_SAI_PLLSAI3CLK 2 -#define STM32_RCC_CCIPR_SAI_EXTCLK 3 - -#define STM32_RCC_CCIPR_CLK48_NONE 0 -#define STM32_RCC_CCIPR_CLK48_PLL48M2CLK 1 -#define STM32_RCC_CCIPR_CLK48_PLL48M1CLK 2 -#define STM32_RCC_CCIPR_CLK48_MSI 3 - -#define STM32_RCC_CCIPR_ADC_NONE 0 -#define STM32_RCC_CCIPR_ADC_PLLADC1CLK 1 -#define STM32_RCC_CCIPR_ADC_PLLADC2CLK 2 -#define STM32_RCC_CCIPR_ADC_SYSCLK 3 - -#define STM32_RCC_CCIPR_SWPMI_PCLK 0 -#define STM32_RCC_CCIPR_SWPMI_HSI16 1 - -#define STM32_RCC_CCIPR_DFSDM_PCLK 0 -#define STM32_RCC_CCIPR_DFSDM_SYSCLK 1 - - - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x0C) +#define STM32_RCC_CCIPR_UART_PCLK 0 +#define STM32_RCC_CCIPR_UART_SYSCLK 1 +#define STM32_RCC_CCIPR_UART_HSI16 2 +#define STM32_RCC_CCIPR_UART_LSE 3 + +#define STM32_RCC_CCIPR_I2C_PCLK 0 +#define STM32_RCC_CCIPR_I2C_SYSCLK 1 +#define STM32_RCC_CCIPR_I2C_HSI16 2 + +#define STM32_RCC_CCIPR_LPTIM_PCLK 0 +#define STM32_RCC_CCIPR_LPTIM_LSI 1 +#define STM32_RCC_CCIPR_LPTIM_HSI16 2 +#define STM32_RCC_CCIPR_LPTIM_LSE 3 + +#define STM32_RCC_CCIPR_SAI_PLLSAI1CLK 0 +#define STM32_RCC_CCIPR_SAI_PLLSAI2CLK 1 +#define STM32_RCC_CCIPR_SAI_PLLSAI3CLK 2 +#define STM32_RCC_CCIPR_SAI_EXTCLK 3 + +#define STM32_RCC_CCIPR_CLK48_NONE 0 +#define STM32_RCC_CCIPR_CLK48_PLL48M2CLK 1 +#define STM32_RCC_CCIPR_CLK48_PLL48M1CLK 2 +#define STM32_RCC_CCIPR_CLK48_MSI 3 + +#define STM32_RCC_CCIPR_ADC_NONE 0 +#define STM32_RCC_CCIPR_ADC_PLLADC1CLK 1 +#define STM32_RCC_CCIPR_ADC_PLLADC2CLK 2 +#define STM32_RCC_CCIPR_ADC_SYSCLK 3 + +#define STM32_RCC_CCIPR_SWPMI_PCLK 0 +#define STM32_RCC_CCIPR_SWPMI_HSI16 1 + +#define STM32_RCC_CCIPR_DFSDM_PCLK 0 +#define STM32_RCC_CCIPR_DFSDM_SYSCLK 1 + +#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) +#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) +#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) +#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x0C) #define STM32_RCC_PLLSAI1CFGR REG32(STM32_RCC_BASE + 0x10) -#define STM32_RCC_RESERVED REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x18) -#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x1C) -#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_RESERVED0 REG32(STM32_RCC_BASE + 0x24) -#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x28) -#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x2C) -#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_RESERVED1 REG32(STM32_RCC_BASE + 0x34) -#define STM32_RCC_APB1RSTR1 REG32(STM32_RCC_BASE + 0x38) -#define STM32_RCC_APB1RSTR2 REG32(STM32_RCC_BASE + 0x3C) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x40) -#define STM32_RCC_RESERVED2 REG32(STM32_RCC_BASE + 0x44) -#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x48) -#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x4C) -#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x50) -#define STM32_RCC_RESERVED3 REG32(STM32_RCC_BASE + 0x54) -#define STM32_RCC_APB1ENR1 REG32(STM32_RCC_BASE + 0x58) -#define STM32_RCC_APB1ENR2 REG32(STM32_RCC_BASE + 0x5C) -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60) -#define STM32_RCC_RESERVED4 REG32(STM32_RCC_BASE + 0x64) -#define STM32_RCC_AHB1SMENR REG32(STM32_RCC_BASE + 0x68) -#define STM32_RCC_AHB2SMENR REG32(STM32_RCC_BASE + 0x6C) -#define STM32_RCC_AHB3SMENR REG32(STM32_RCC_BASE + 0x70) -#define STM32_RCC_RESERVED5 REG32(STM32_RCC_BASE + 0x74) -#define STM32_RCC_APB1SMENR1 REG32(STM32_RCC_BASE + 0x78) -#define STM32_RCC_APB1SMENR2 REG32(STM32_RCC_BASE + 0x7C) -#define STM32_RCC_APB2SMENR REG32(STM32_RCC_BASE + 0x80) -#define STM32_RCC_RESERVED6 REG32(STM32_RCC_BASE + 0x84) -#define STM32_RCC_CCIPR1 REG32(STM32_RCC_BASE + 0x88) -#define STM32_RCC_CCIPR STM32_RCC_CCIPR1 -#define STM32_RCC_RESERVED7 REG32(STM32_RCC_BASE + 0x8C) -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x94) -#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98) -#define STM32_RCC_CCIPR2 REG32(STM32_RCC_BASE + 0x9C) -#define STM32_CRS_CR REG32(STM32_CRS_BASE + 0x00) -#define STM32_CRS_CFGR REG32(STM32_CRS_BASE + 0x04) -#define STM32_CRS_ISR REG32(STM32_CRS_BASE + 0x08) -#define STM32_CRS_ICR REG32(STM32_CRS_BASE + 0x0C) +#define STM32_RCC_RESERVED REG32(STM32_RCC_BASE + 0x14) +#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x18) +#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x1C) +#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x20) +#define STM32_RCC_RESERVED0 REG32(STM32_RCC_BASE + 0x24) +#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x28) +#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x2C) +#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x30) +#define STM32_RCC_RESERVED1 REG32(STM32_RCC_BASE + 0x34) +#define STM32_RCC_APB1RSTR1 REG32(STM32_RCC_BASE + 0x38) +#define STM32_RCC_APB1RSTR2 REG32(STM32_RCC_BASE + 0x3C) +#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x40) +#define STM32_RCC_RESERVED2 REG32(STM32_RCC_BASE + 0x44) +#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x48) +#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x4C) +#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x50) +#define STM32_RCC_RESERVED3 REG32(STM32_RCC_BASE + 0x54) +#define STM32_RCC_APB1ENR1 REG32(STM32_RCC_BASE + 0x58) +#define STM32_RCC_APB1ENR2 REG32(STM32_RCC_BASE + 0x5C) +#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60) +#define STM32_RCC_RESERVED4 REG32(STM32_RCC_BASE + 0x64) +#define STM32_RCC_AHB1SMENR REG32(STM32_RCC_BASE + 0x68) +#define STM32_RCC_AHB2SMENR REG32(STM32_RCC_BASE + 0x6C) +#define STM32_RCC_AHB3SMENR REG32(STM32_RCC_BASE + 0x70) +#define STM32_RCC_RESERVED5 REG32(STM32_RCC_BASE + 0x74) +#define STM32_RCC_APB1SMENR1 REG32(STM32_RCC_BASE + 0x78) +#define STM32_RCC_APB1SMENR2 REG32(STM32_RCC_BASE + 0x7C) +#define STM32_RCC_APB2SMENR REG32(STM32_RCC_BASE + 0x80) +#define STM32_RCC_RESERVED6 REG32(STM32_RCC_BASE + 0x84) +#define STM32_RCC_CCIPR1 REG32(STM32_RCC_BASE + 0x88) +#define STM32_RCC_CCIPR STM32_RCC_CCIPR1 +#define STM32_RCC_RESERVED7 REG32(STM32_RCC_BASE + 0x8C) +#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90) +#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x94) +#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98) +#define STM32_RCC_CCIPR2 REG32(STM32_RCC_BASE + 0x9C) +#define STM32_CRS_CR REG32(STM32_CRS_BASE + 0x00) +#define STM32_CRS_CFGR REG32(STM32_CRS_BASE + 0x04) +#define STM32_CRS_ISR REG32(STM32_CRS_BASE + 0x08) +#define STM32_CRS_ICR REG32(STM32_CRS_BASE + 0x0C) #define STM32_RCC_PLLSAI1_SUPPORT #define STM32_RCC_PLLP_SUPPORT @@ -527,236 +524,236 @@ #define STM32_RCC_PLLP_DIV_2_31_SUPPORT #define STM32_RCC_PLLSAI1P_DIV_2_31_SUPPORT -#define STM32_RCC_APB1ENR STM32_RCC_APB1ENR1 +#define STM32_RCC_APB1ENR STM32_RCC_APB1ENR1 /******************** BIT DEFINITION FOR STM32_RCC_CR REGISTER **************/ -#define STM32_RCC_CR_MSION_POS 0U -#define STM32_RCC_CR_MSION_MSK (0x1UL << STM32_RCC_CR_MSION_POS) -#define STM32_RCC_CR_MSION STM32_RCC_CR_MSION_MSK -#define STM32_RCC_CR_MSIRDY_POS 1U -#define STM32_RCC_CR_MSIRDY_MSK (0x1UL << STM32_RCC_CR_MSIRDY_POS) -#define STM32_RCC_CR_MSIRDY STM32_RCC_CR_MSIRDY_MSK -#define STM32_RCC_CR_MSIPLLEN_POS 2U -#define STM32_RCC_CR_MSIPLLEN_MSK (0x1UL << STM32_RCC_CR_MSIPLLEN_POS) -#define STM32_RCC_CR_MSIPLLEN STM32_RCC_CR_MSIPLLEN_MSK -#define STM32_RCC_CR_MSIRGSEL_POS 3U -#define STM32_RCC_CR_MSIRGSEL_MSK (0x1UL << STM32_RCC_CR_MSIRGSEL_POS) -#define STM32_RCC_CR_MSIRGSEL STM32_RCC_CR_MSIRGSEL_MSK +#define STM32_RCC_CR_MSION_POS 0U +#define STM32_RCC_CR_MSION_MSK (0x1UL << STM32_RCC_CR_MSION_POS) +#define STM32_RCC_CR_MSION STM32_RCC_CR_MSION_MSK +#define STM32_RCC_CR_MSIRDY_POS 1U +#define STM32_RCC_CR_MSIRDY_MSK (0x1UL << STM32_RCC_CR_MSIRDY_POS) +#define STM32_RCC_CR_MSIRDY STM32_RCC_CR_MSIRDY_MSK +#define STM32_RCC_CR_MSIPLLEN_POS 2U +#define STM32_RCC_CR_MSIPLLEN_MSK (0x1UL << STM32_RCC_CR_MSIPLLEN_POS) +#define STM32_RCC_CR_MSIPLLEN STM32_RCC_CR_MSIPLLEN_MSK +#define STM32_RCC_CR_MSIRGSEL_POS 3U +#define STM32_RCC_CR_MSIRGSEL_MSK (0x1UL << STM32_RCC_CR_MSIRGSEL_POS) +#define STM32_RCC_CR_MSIRGSEL STM32_RCC_CR_MSIRGSEL_MSK /*!< MSIRANGE CONFIGURATION : 12 FREQUENCY RANGES AVAILABLE */ -#define STM32_RCC_CR_MSIRANGE_POS 4U -#define STM32_RCC_CR_MSIRANGE_MSK (0xFUL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE STM32_RCC_CR_MSIRANGE_MSK -#define STM32_RCC_CR_MSIRANGE_0 (0x0UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_1 (0x1UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_2 (0x2UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_3 (0x3UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_4 (0x4UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_5 (0x5UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_6 (0x6UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_7 (0x7UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_8 (0x8UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_9 (0x9UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_10 (0xAUL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_11 (0xBUL << STM32_RCC_CR_MSIRANGE_POS) - -#define STM32_RCC_CR_HSION_POS 8U -#define STM32_RCC_CR_HSION_MSK (0x1UL << STM32_RCC_CR_HSION_POS) -#define STM32_RCC_CR_HSION STM32_RCC_CR_HSION_MSK -#define STM32_RCC_CR_HSIKERON_POS 9U -#define STM32_RCC_CR_HSIKERON_MSK (0x1UL << STM32_RCC_CR_HSIKERON_POS) -#define STM32_RCC_CR_HSIKERON STM32_RCC_CR_HSIKERON_MSK -#define STM32_RCC_CR_HSIRDY_POS 10U -#define STM32_RCC_CR_HSIRDY_MSK (0x1UL << STM32_RCC_CR_HSIRDY_POS) -#define STM32_RCC_CR_HSIRDY STM32_RCC_CR_HSIRDY_MSK -#define STM32_RCC_CR_HSIASFS_POS 11U -#define STM32_RCC_CR_HSIASFS_MSK (0x1UL << STM32_RCC_CR_HSIASFS_POS) -#define STM32_RCC_CR_HSIASFS STM32_RCC_CR_HSIASFS_MSK - -#define STM32_RCC_CR_HSEON_POS 16U -#define STM32_RCC_CR_HSEON_MSK (0x1UL << STM32_RCC_CR_HSEON_POS) -#define STM32_RCC_CR_HSEON STM32_RCC_CR_HSEON_MSK -#define STM32_RCC_CR_HSERDY_POS 17U -#define STM32_RCC_CR_HSERDY_MSK (0x1UL << STM32_RCC_CR_HSERDY_POS) -#define STM32_RCC_CR_HSERDY STM32_RCC_CR_HSERDY_MSK -#define STM32_RCC_CR_HSEBYP_POS 18U -#define STM32_RCC_CR_HSEBYP_MSK (0x1UL << STM32_RCC_CR_HSEBYP_POS) -#define STM32_RCC_CR_HSEBYP STM32_RCC_CR_HSEBYP_MSK -#define STM32_RCC_CR_CSSON_POS 19U -#define STM32_RCC_CR_CSSON_MSK (0x1UL << STM32_RCC_CR_CSSON_POS) -#define STM32_RCC_CR_CSSON STM32_RCC_CR_CSSON_MSK - -#define STM32_RCC_CR_PLLON_POS 24U -#define STM32_RCC_CR_PLLON_MSK (0x1UL << STM32_RCC_CR_PLLON_POS) -#define STM32_RCC_CR_PLLON STM32_RCC_CR_PLLON_MSK -#define STM32_RCC_CR_PLLRDY_POS 25U -#define STM32_RCC_CR_PLLRDY_MSK (0x1UL << STM32_RCC_CR_PLLRDY_POS) -#define STM32_RCC_CR_PLLRDY STM32_RCC_CR_PLLRDY_MSK -#define STM32_RCC_CR_PLLSAI1ON_POS 26U -#define STM32_RCC_CR_PLLSAI1ON_MSK (0x1UL << STM32_RCC_CR_PLLSAI1ON_POS) -#define STM32_RCC_CR_PLLSAI1ON STM32_RCC_CR_PLLSAI1ON_MSK -#define STM32_RCC_CR_PLLSAI1RDY_POS 27U -#define STM32_RCC_CR_PLLSAI1RDY_MSK (0x1UL << STM32_RCC_CR_PLLSAI1RDY_POS) -#define STM32_RCC_CR_PLLSAI1RDY STM32_RCC_CR_PLLSAI1RDY_MSK +#define STM32_RCC_CR_MSIRANGE_POS 4U +#define STM32_RCC_CR_MSIRANGE_MSK (0xFUL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE STM32_RCC_CR_MSIRANGE_MSK +#define STM32_RCC_CR_MSIRANGE_0 (0x0UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_1 (0x1UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_2 (0x2UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_3 (0x3UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_4 (0x4UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_5 (0x5UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_6 (0x6UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_7 (0x7UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_8 (0x8UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_9 (0x9UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_10 (0xAUL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_11 (0xBUL << STM32_RCC_CR_MSIRANGE_POS) + +#define STM32_RCC_CR_HSION_POS 8U +#define STM32_RCC_CR_HSION_MSK (0x1UL << STM32_RCC_CR_HSION_POS) +#define STM32_RCC_CR_HSION STM32_RCC_CR_HSION_MSK +#define STM32_RCC_CR_HSIKERON_POS 9U +#define STM32_RCC_CR_HSIKERON_MSK (0x1UL << STM32_RCC_CR_HSIKERON_POS) +#define STM32_RCC_CR_HSIKERON STM32_RCC_CR_HSIKERON_MSK +#define STM32_RCC_CR_HSIRDY_POS 10U +#define STM32_RCC_CR_HSIRDY_MSK (0x1UL << STM32_RCC_CR_HSIRDY_POS) +#define STM32_RCC_CR_HSIRDY STM32_RCC_CR_HSIRDY_MSK +#define STM32_RCC_CR_HSIASFS_POS 11U +#define STM32_RCC_CR_HSIASFS_MSK (0x1UL << STM32_RCC_CR_HSIASFS_POS) +#define STM32_RCC_CR_HSIASFS STM32_RCC_CR_HSIASFS_MSK + +#define STM32_RCC_CR_HSEON_POS 16U +#define STM32_RCC_CR_HSEON_MSK (0x1UL << STM32_RCC_CR_HSEON_POS) +#define STM32_RCC_CR_HSEON STM32_RCC_CR_HSEON_MSK +#define STM32_RCC_CR_HSERDY_POS 17U +#define STM32_RCC_CR_HSERDY_MSK (0x1UL << STM32_RCC_CR_HSERDY_POS) +#define STM32_RCC_CR_HSERDY STM32_RCC_CR_HSERDY_MSK +#define STM32_RCC_CR_HSEBYP_POS 18U +#define STM32_RCC_CR_HSEBYP_MSK (0x1UL << STM32_RCC_CR_HSEBYP_POS) +#define STM32_RCC_CR_HSEBYP STM32_RCC_CR_HSEBYP_MSK +#define STM32_RCC_CR_CSSON_POS 19U +#define STM32_RCC_CR_CSSON_MSK (0x1UL << STM32_RCC_CR_CSSON_POS) +#define STM32_RCC_CR_CSSON STM32_RCC_CR_CSSON_MSK + +#define STM32_RCC_CR_PLLON_POS 24U +#define STM32_RCC_CR_PLLON_MSK (0x1UL << STM32_RCC_CR_PLLON_POS) +#define STM32_RCC_CR_PLLON STM32_RCC_CR_PLLON_MSK +#define STM32_RCC_CR_PLLRDY_POS 25U +#define STM32_RCC_CR_PLLRDY_MSK (0x1UL << STM32_RCC_CR_PLLRDY_POS) +#define STM32_RCC_CR_PLLRDY STM32_RCC_CR_PLLRDY_MSK +#define STM32_RCC_CR_PLLSAI1ON_POS 26U +#define STM32_RCC_CR_PLLSAI1ON_MSK (0x1UL << STM32_RCC_CR_PLLSAI1ON_POS) +#define STM32_RCC_CR_PLLSAI1ON STM32_RCC_CR_PLLSAI1ON_MSK +#define STM32_RCC_CR_PLLSAI1RDY_POS 27U +#define STM32_RCC_CR_PLLSAI1RDY_MSK (0x1UL << STM32_RCC_CR_PLLSAI1RDY_POS) +#define STM32_RCC_CR_PLLSAI1RDY STM32_RCC_CR_PLLSAI1RDY_MSK /******************** BIT DEFINITION FOR STM32_RCC_ICSCR REGISTER ***********/ /*!< MSICAL CONFIGURATION */ -#define STM32_RCC_ICSCR_MSICAL_POS 0U -#define STM32_RCC_ICSCR_MSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL STM32_RCC_ICSCR_MSICAL_MSK -#define STM32_RCC_ICSCR_MSICAL_0 (0x01UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_1 (0x02UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_2 (0x04UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_3 (0x08UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_4 (0x10UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_5 (0x20UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_6 (0x40UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_7 (0x80UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_POS 0U +#define STM32_RCC_ICSCR_MSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL STM32_RCC_ICSCR_MSICAL_MSK +#define STM32_RCC_ICSCR_MSICAL_0 (0x01UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_1 (0x02UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_2 (0x04UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_3 (0x08UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_4 (0x10UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_5 (0x20UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_6 (0x40UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_7 (0x80UL << STM32_RCC_ICSCR_MSICAL_POS) /*!< MSITRIM CONFIGURATION */ -#define STM32_RCC_ICSCR_MSITRIM_POS 8U -#define STM32_RCC_ICSCR_MSITRIM_MSK (0xFFUL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM STM32_RCC_ICSCR_MSITRIM_MSK -#define STM32_RCC_ICSCR_MSITRIM_0 (0x01UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_1 (0x02UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_2 (0x04UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_3 (0x08UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_4 (0x10UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_5 (0x20UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_6 (0x40UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_7 (0x80UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_POS 8U +#define STM32_RCC_ICSCR_MSITRIM_MSK (0xFFUL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM STM32_RCC_ICSCR_MSITRIM_MSK +#define STM32_RCC_ICSCR_MSITRIM_0 (0x01UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_1 (0x02UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_2 (0x04UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_3 (0x08UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_4 (0x10UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_5 (0x20UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_6 (0x40UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_7 (0x80UL << STM32_RCC_ICSCR_MSITRIM_POS) /*!< HSICAL CONFIGURATION */ -#define STM32_RCC_ICSCR_HSICAL_POS 16U -#define STM32_RCC_ICSCR_HSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL STM32_RCC_ICSCR_HSICAL_MSK -#define STM32_RCC_ICSCR_HSICAL_0 (0x01UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_1 (0x02UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_2 (0x04UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_3 (0x08UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_4 (0x10UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_5 (0x20UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_6 (0x40UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_7 (0x80UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_POS 16U +#define STM32_RCC_ICSCR_HSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL STM32_RCC_ICSCR_HSICAL_MSK +#define STM32_RCC_ICSCR_HSICAL_0 (0x01UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_1 (0x02UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_2 (0x04UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_3 (0x08UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_4 (0x10UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_5 (0x20UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_6 (0x40UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_7 (0x80UL << STM32_RCC_ICSCR_HSICAL_POS) /*!< HSITRIM CONFIGURATION */ -#define STM32_RCC_ICSCR_HSITRIM_POS 24U -#define STM32_RCC_ICSCR_HSITRIM_MSK (0x1FUL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM STM32_RCC_ICSCR_HSITRIM_MSK -#define STM32_RCC_ICSCR_HSITRIM_0 (0x01UL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM_1 (0x02UL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM_2 (0x04UL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM_3 (0x08UL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM_4 (0x10UL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM_POS 24U +#define STM32_RCC_ICSCR_HSITRIM_MSK (0x1FUL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM STM32_RCC_ICSCR_HSITRIM_MSK +#define STM32_RCC_ICSCR_HSITRIM_0 (0x01UL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM_1 (0x02UL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM_2 (0x04UL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM_3 (0x08UL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM_4 (0x10UL << STM32_RCC_ICSCR_HSITRIM_POS) /**************** BIT DEFINITION FOR STM32_RCC_CFGR REGISTER **************/ /*!< SW CONFIGURATION */ -#define STM32_RCC_CFGR_SW_POS 0U -#define STM32_RCC_CFGR_SW_MSK (0x3UL << STM32_RCC_CFGR_SW_POS) -#define STM32_RCC_CFGR_SW STM32_RCC_CFGR_SW_MSK -#define STM32_RCC_CFGR_SW_0 (0x1UL << STM32_RCC_CFGR_SW_POS) -#define STM32_RCC_CFGR_SW_1 (0x2UL << STM32_RCC_CFGR_SW_POS) +#define STM32_RCC_CFGR_SW_POS 0U +#define STM32_RCC_CFGR_SW_MSK (0x3UL << STM32_RCC_CFGR_SW_POS) +#define STM32_RCC_CFGR_SW STM32_RCC_CFGR_SW_MSK +#define STM32_RCC_CFGR_SW_0 (0x1UL << STM32_RCC_CFGR_SW_POS) +#define STM32_RCC_CFGR_SW_1 (0x2UL << STM32_RCC_CFGR_SW_POS) -#define STM32_RCC_CFGR_SW_MSI (0x00000000UL) -#define STM32_RCC_CFGR_SW_HSI (0x00000001UL) -#define STM32_RCC_CFGR_SW_HSE (0x00000002UL) -#define STM32_RCC_CFGR_SW_PLL (0x00000003UL) +#define STM32_RCC_CFGR_SW_MSI (0x00000000UL) +#define STM32_RCC_CFGR_SW_HSI (0x00000001UL) +#define STM32_RCC_CFGR_SW_HSE (0x00000002UL) +#define STM32_RCC_CFGR_SW_PLL (0x00000003UL) /*!< SWS CONFIGURATION */ -#define STM32_RCC_CFGR_SWS_POS 2U -#define STM32_RCC_CFGR_SWS_MSK (0x3UL << STM32_RCC_CFGR_SWS_POS) -#define STM32_RCC_CFGR_SWS STM32_RCC_CFGR_SWS_MSK -#define STM32_RCC_CFGR_SWS_0 (0x1UL << STM32_RCC_CFGR_SWS_POS) -#define STM32_RCC_CFGR_SWS_1 (0x2UL << STM32_RCC_CFGR_SWS_POS) +#define STM32_RCC_CFGR_SWS_POS 2U +#define STM32_RCC_CFGR_SWS_MSK (0x3UL << STM32_RCC_CFGR_SWS_POS) +#define STM32_RCC_CFGR_SWS STM32_RCC_CFGR_SWS_MSK +#define STM32_RCC_CFGR_SWS_0 (0x1UL << STM32_RCC_CFGR_SWS_POS) +#define STM32_RCC_CFGR_SWS_1 (0x2UL << STM32_RCC_CFGR_SWS_POS) -#define STM32_RCC_CFGR_SWS_MSI (0x00000000UL) -#define STM32_RCC_CFGR_SWS_HSI (0x00000004UL) -#define STM32_RCC_CFGR_SWS_HSE (0x00000008UL) -#define STM32_RCC_CFGR_SWS_PLL (0x0000000CUL) +#define STM32_RCC_CFGR_SWS_MSI (0x00000000UL) +#define STM32_RCC_CFGR_SWS_HSI (0x00000004UL) +#define STM32_RCC_CFGR_SWS_HSE (0x00000008UL) +#define STM32_RCC_CFGR_SWS_PLL (0x0000000CUL) /*!< HPRE CONFIGURATION */ -#define STM32_RCC_CFGR_HPRE_POS 4U -#define STM32_RCC_CFGR_HPRE_MSK (0xFUL << STM32_RCC_CFGR_HPRE_POS) -#define STM32_RCC_CFGR_HPRE STM32_RCC_CFGR_HPRE_MSK -#define STM32_RCC_CFGR_HPRE_0 (0x1UL << STM32_RCC_CFGR_HPRE_POS) -#define STM32_RCC_CFGR_HPRE_1 (0x2UL << STM32_RCC_CFGR_HPRE_POS) -#define STM32_RCC_CFGR_HPRE_2 (0x4UL << STM32_RCC_CFGR_HPRE_POS) -#define STM32_RCC_CFGR_HPRE_3 (0x8UL << STM32_RCC_CFGR_HPRE_POS) - -#define STM32_RCC_CFGR_HPRE_DIV1 (0x00000000UL) -#define STM32_RCC_CFGR_HPRE_DIV2 (0x00000080UL) -#define STM32_RCC_CFGR_HPRE_DIV4 (0x00000090UL) -#define STM32_RCC_CFGR_HPRE_DIV8 (0x000000A0UL) -#define STM32_RCC_CFGR_HPRE_DIV16 (0x000000B0UL) -#define STM32_RCC_CFGR_HPRE_DIV64 (0x000000C0UL) -#define STM32_RCC_CFGR_HPRE_DIV128 (0x000000D0UL) -#define STM32_RCC_CFGR_HPRE_DIV256 (0x000000E0UL) -#define STM32_RCC_CFGR_HPRE_DIV512 (0x000000F0UL) +#define STM32_RCC_CFGR_HPRE_POS 4U +#define STM32_RCC_CFGR_HPRE_MSK (0xFUL << STM32_RCC_CFGR_HPRE_POS) +#define STM32_RCC_CFGR_HPRE STM32_RCC_CFGR_HPRE_MSK +#define STM32_RCC_CFGR_HPRE_0 (0x1UL << STM32_RCC_CFGR_HPRE_POS) +#define STM32_RCC_CFGR_HPRE_1 (0x2UL << STM32_RCC_CFGR_HPRE_POS) +#define STM32_RCC_CFGR_HPRE_2 (0x4UL << STM32_RCC_CFGR_HPRE_POS) +#define STM32_RCC_CFGR_HPRE_3 (0x8UL << STM32_RCC_CFGR_HPRE_POS) + +#define STM32_RCC_CFGR_HPRE_DIV1 (0x00000000UL) +#define STM32_RCC_CFGR_HPRE_DIV2 (0x00000080UL) +#define STM32_RCC_CFGR_HPRE_DIV4 (0x00000090UL) +#define STM32_RCC_CFGR_HPRE_DIV8 (0x000000A0UL) +#define STM32_RCC_CFGR_HPRE_DIV16 (0x000000B0UL) +#define STM32_RCC_CFGR_HPRE_DIV64 (0x000000C0UL) +#define STM32_RCC_CFGR_HPRE_DIV128 (0x000000D0UL) +#define STM32_RCC_CFGR_HPRE_DIV256 (0x000000E0UL) +#define STM32_RCC_CFGR_HPRE_DIV512 (0x000000F0UL) /*!< PPRE1 CONFIGURATION */ -#define STM32_RCC_CFGR_PPRE1_POS 8U -#define STM32_RCC_CFGR_PPRE1_MSK (0x7UL << STM32_RCC_CFGR_PPRE1_POS) -#define STM32_RCC_CFGR_PPRE1 STM32_RCC_CFGR_PPRE1_MSK -#define STM32_RCC_CFGR_PPRE1_0 (0x1UL << STM32_RCC_CFGR_PPRE1_POS) -#define STM32_RCC_CFGR_PPRE1_1 (0x2UL << STM32_RCC_CFGR_PPRE1_POS) -#define STM32_RCC_CFGR_PPRE1_2 (0x4UL << STM32_RCC_CFGR_PPRE1_POS) - -#define STM32_RCC_CFGR_PPRE1_DIV1 (0x00000000UL) -#define STM32_RCC_CFGR_PPRE1_DIV2 (0x00000400UL) -#define STM32_RCC_CFGR_PPRE1_DIV4 (0x00000500UL) -#define STM32_RCC_CFGR_PPRE1_DIV8 (0x00000600UL) -#define STM32_RCC_CFGR_PPRE1_DIV16 (0x00000700UL) +#define STM32_RCC_CFGR_PPRE1_POS 8U +#define STM32_RCC_CFGR_PPRE1_MSK (0x7UL << STM32_RCC_CFGR_PPRE1_POS) +#define STM32_RCC_CFGR_PPRE1 STM32_RCC_CFGR_PPRE1_MSK +#define STM32_RCC_CFGR_PPRE1_0 (0x1UL << STM32_RCC_CFGR_PPRE1_POS) +#define STM32_RCC_CFGR_PPRE1_1 (0x2UL << STM32_RCC_CFGR_PPRE1_POS) +#define STM32_RCC_CFGR_PPRE1_2 (0x4UL << STM32_RCC_CFGR_PPRE1_POS) + +#define STM32_RCC_CFGR_PPRE1_DIV1 (0x00000000UL) +#define STM32_RCC_CFGR_PPRE1_DIV2 (0x00000400UL) +#define STM32_RCC_CFGR_PPRE1_DIV4 (0x00000500UL) +#define STM32_RCC_CFGR_PPRE1_DIV8 (0x00000600UL) +#define STM32_RCC_CFGR_PPRE1_DIV16 (0x00000700UL) /*!< PPRE2 CONFIGURATION */ -#define STM32_RCC_CFGR_PPRE2_POS 11U -#define STM32_RCC_CFGR_PPRE2_MSK (0x7UL << STM32_RCC_CFGR_PPRE2_POS) -#define STM32_RCC_CFGR_PPRE2 STM32_RCC_CFGR_PPRE2_MSK -#define STM32_RCC_CFGR_PPRE2_0 (0x1UL << STM32_RCC_CFGR_PPRE2_POS) -#define STM32_RCC_CFGR_PPRE2_1 (0x2UL << STM32_RCC_CFGR_PPRE2_POS) -#define STM32_RCC_CFGR_PPRE2_2 (0x4UL << STM32_RCC_CFGR_PPRE2_POS) - -#define STM32_RCC_CFGR_PPRE2_DIV1 (0x00000000UL) -#define STM32_RCC_CFGR_PPRE2_DIV2 (0x00002000UL) -#define STM32_RCC_CFGR_PPRE2_DIV4 (0x00002800UL) -#define STM32_RCC_CFGR_PPRE2_DIV8 (0x00003000UL) -#define STM32_RCC_CFGR_PPRE2_DIV16 (0x00003800UL) - -#define STM32_RCC_CFGR_STOPWUCK_POS 15U -#define STM32_RCC_CFGR_STOPWUCK_MSK (0x1UL << STM32_RCC_CFGR_STOPWUCK_POS) -#define STM32_RCC_CFGR_STOPWUCK STM32_RCC_CFGR_STOPWUCK_MSK +#define STM32_RCC_CFGR_PPRE2_POS 11U +#define STM32_RCC_CFGR_PPRE2_MSK (0x7UL << STM32_RCC_CFGR_PPRE2_POS) +#define STM32_RCC_CFGR_PPRE2 STM32_RCC_CFGR_PPRE2_MSK +#define STM32_RCC_CFGR_PPRE2_0 (0x1UL << STM32_RCC_CFGR_PPRE2_POS) +#define STM32_RCC_CFGR_PPRE2_1 (0x2UL << STM32_RCC_CFGR_PPRE2_POS) +#define STM32_RCC_CFGR_PPRE2_2 (0x4UL << STM32_RCC_CFGR_PPRE2_POS) + +#define STM32_RCC_CFGR_PPRE2_DIV1 (0x00000000UL) +#define STM32_RCC_CFGR_PPRE2_DIV2 (0x00002000UL) +#define STM32_RCC_CFGR_PPRE2_DIV4 (0x00002800UL) +#define STM32_RCC_CFGR_PPRE2_DIV8 (0x00003000UL) +#define STM32_RCC_CFGR_PPRE2_DIV16 (0x00003800UL) + +#define STM32_RCC_CFGR_STOPWUCK_POS 15U +#define STM32_RCC_CFGR_STOPWUCK_MSK (0x1UL << STM32_RCC_CFGR_STOPWUCK_POS) +#define STM32_RCC_CFGR_STOPWUCK STM32_RCC_CFGR_STOPWUCK_MSK /*!< MCOSEL CONFIGURATION */ -#define STM32_RCC_CFGR_MCOSEL_POS 24U -#define STM32_RCC_CFGR_MCOSEL_MSK (0xFUL << STM32_RCC_CFGR_MCOSEL_POS) -#define STM32_RCC_CFGR_MCOSEL STM32_RCC_CFGR_MCOSEL_MSK -#define STM32_RCC_CFGR_MCOSEL_0 (0x1UL << STM32_RCC_CFGR_MCOSEL_POS) -#define STM32_RCC_CFGR_MCOSEL_1 (0x2UL << STM32_RCC_CFGR_MCOSEL_POS) -#define STM32_RCC_CFGR_MCOSEL_2 (0x4UL << STM32_RCC_CFGR_MCOSEL_POS) -#define STM32_RCC_CFGR_MCOSEL_3 (0x8UL << STM32_RCC_CFGR_MCOSEL_POS) - -#define STM32_RCC_CFGR_MCOPRE_POS 28U -#define STM32_RCC_CFGR_MCOPRE_MSK (0x7UL << STM32_RCC_CFGR_MCOPRE_POS) -#define STM32_RCC_CFGR_MCOPRE STM32_RCC_CFGR_MCOPRE_MSK -#define STM32_RCC_CFGR_MCOPRE_0 (0x1UL << STM32_RCC_CFGR_MCOPRE_POS) -#define STM32_RCC_CFGR_MCOPRE_1 (0x2UL << STM32_RCC_CFGR_MCOPRE_POS) -#define STM32_RCC_CFGR_MCOPRE_2 (0x4UL << STM32_RCC_CFGR_MCOPRE_POS) - -#define STM32_RCC_CFGR_MCOPRE_DIV1 (0x00000000UL) -#define STM32_RCC_CFGR_MCOPRE_DIV2 (0x10000000UL) -#define STM32_RCC_CFGR_MCOPRE_DIV4 (0x20000000UL) -#define STM32_RCC_CFGR_MCOPRE_DIV8 (0x30000000UL) -#define STM32_RCC_CFGR_MCOPRE_DIV16 (0x40000000UL) +#define STM32_RCC_CFGR_MCOSEL_POS 24U +#define STM32_RCC_CFGR_MCOSEL_MSK (0xFUL << STM32_RCC_CFGR_MCOSEL_POS) +#define STM32_RCC_CFGR_MCOSEL STM32_RCC_CFGR_MCOSEL_MSK +#define STM32_RCC_CFGR_MCOSEL_0 (0x1UL << STM32_RCC_CFGR_MCOSEL_POS) +#define STM32_RCC_CFGR_MCOSEL_1 (0x2UL << STM32_RCC_CFGR_MCOSEL_POS) +#define STM32_RCC_CFGR_MCOSEL_2 (0x4UL << STM32_RCC_CFGR_MCOSEL_POS) +#define STM32_RCC_CFGR_MCOSEL_3 (0x8UL << STM32_RCC_CFGR_MCOSEL_POS) + +#define STM32_RCC_CFGR_MCOPRE_POS 28U +#define STM32_RCC_CFGR_MCOPRE_MSK (0x7UL << STM32_RCC_CFGR_MCOPRE_POS) +#define STM32_RCC_CFGR_MCOPRE STM32_RCC_CFGR_MCOPRE_MSK +#define STM32_RCC_CFGR_MCOPRE_0 (0x1UL << STM32_RCC_CFGR_MCOPRE_POS) +#define STM32_RCC_CFGR_MCOPRE_1 (0x2UL << STM32_RCC_CFGR_MCOPRE_POS) +#define STM32_RCC_CFGR_MCOPRE_2 (0x4UL << STM32_RCC_CFGR_MCOPRE_POS) + +#define STM32_RCC_CFGR_MCOPRE_DIV1 (0x00000000UL) +#define STM32_RCC_CFGR_MCOPRE_DIV2 (0x10000000UL) +#define STM32_RCC_CFGR_MCOPRE_DIV4 (0x20000000UL) +#define STM32_RCC_CFGR_MCOPRE_DIV8 (0x30000000UL) +#define STM32_RCC_CFGR_MCOPRE_DIV16 (0x40000000UL) /* LEGACY ALIASES */ -#define STM32_RCC_CFGR_MCO_PRE STM32_RCC_CFGR_MCOPRE -#define STM32_RCC_CFGR_MCO_PRE_1 STM32_RCC_CFGR_MCOPRE_DIV1 -#define STM32_RCC_CFGR_MCO_PRE_2 STM32_RCC_CFGR_MCOPRE_DIV2 -#define STM32_RCC_CFGR_MCO_PRE_4 STM32_RCC_CFGR_MCOPRE_DIV4 -#define STM32_RCC_CFGR_MCO_PRE_8 STM32_RCC_CFGR_MCOPRE_DIV8 -#define STM32_RCC_CFGR_MCO_PRE_16 STM32_RCC_CFGR_MCOPRE_DIV16 +#define STM32_RCC_CFGR_MCO_PRE STM32_RCC_CFGR_MCOPRE +#define STM32_RCC_CFGR_MCO_PRE_1 STM32_RCC_CFGR_MCOPRE_DIV1 +#define STM32_RCC_CFGR_MCO_PRE_2 STM32_RCC_CFGR_MCOPRE_DIV2 +#define STM32_RCC_CFGR_MCO_PRE_4 STM32_RCC_CFGR_MCOPRE_DIV4 +#define STM32_RCC_CFGR_MCO_PRE_8 STM32_RCC_CFGR_MCOPRE_DIV8 +#define STM32_RCC_CFGR_MCO_PRE_16 STM32_RCC_CFGR_MCOPRE_DIV16 /**************** BIT DEFINITION FOR STM32_RCC_PLLCFGR REGISTER ***********/ -#define STM32_RCC_PLLCFGR_PLLSRC_POS 0U +#define STM32_RCC_PLLCFGR_PLLSRC_POS 0U #define STM32_RCC_PLLCFGR_PLLSRC_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLSRC_POS) #define STM32_RCC_PLLCFGR_PLLSRC STM32_RCC_PLLCFGR_PLLSRC_MSK @@ -771,59 +768,59 @@ #define STM32_RCC_PLLCFGR_PLLSRC_HSE_POS 0U #define STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK \ (0x3UL << STM32_RCC_PLLCFGR_PLLSRC_HSE_POS) -#define STM32_RCC_PLLCFGR_PLLSRC_HSE STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK - -#define STM32_RCC_PLLCFGR_PLLM_POS 4U -#define STM32_RCC_PLLCFGR_PLLM_MSK (0x7UL << STM32_RCC_PLLCFGR_PLLM_POS) -#define STM32_RCC_PLLCFGR_PLLM STM32_RCC_PLLCFGR_PLLM_MSK -#define STM32_RCC_PLLCFGR_PLLM_0 (0x1UL << STM32_RCC_PLLCFGR_PLLM_POS) -#define STM32_RCC_PLLCFGR_PLLM_1 (0x2UL << STM32_RCC_PLLCFGR_PLLM_POS) -#define STM32_RCC_PLLCFGR_PLLM_2 (0x4UL << STM32_RCC_PLLCFGR_PLLM_POS) - -#define STM32_RCC_PLLCFGR_PLLN_POS 8U -#define STM32_RCC_PLLCFGR_PLLN_MSK (0x7FUL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN STM32_RCC_PLLCFGR_PLLN_MSK -#define STM32_RCC_PLLCFGR_PLLN_0 (0x01UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_1 (0x02UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_2 (0x04UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_3 (0x08UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_4 (0x10UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_5 (0x20UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_6 (0x40UL << STM32_RCC_PLLCFGR_PLLN_POS) - -#define STM32_RCC_PLLCFGR_PLLPEN_POS 16U -#define STM32_RCC_PLLCFGR_PLLPEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLPEN_POS) -#define STM32_RCC_PLLCFGR_PLLPEN STM32_RCC_PLLCFGR_PLLPEN_MSK -#define STM32_RCC_PLLCFGR_PLLP_POS 17U -#define STM32_RCC_PLLCFGR_PLLP_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLP_POS) -#define STM32_RCC_PLLCFGR_PLLP STM32_RCC_PLLCFGR_PLLP_MSK -#define STM32_RCC_PLLCFGR_PLLQEN_POS 20U -#define STM32_RCC_PLLCFGR_PLLQEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLQEN_POS) -#define STM32_RCC_PLLCFGR_PLLQEN STM32_RCC_PLLCFGR_PLLQEN_MSK - -#define STM32_RCC_PLLCFGR_PLLQ_POS 21U -#define STM32_RCC_PLLCFGR_PLLQ_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLQ_POS) -#define STM32_RCC_PLLCFGR_PLLQ STM32_RCC_PLLCFGR_PLLQ_MSK -#define STM32_RCC_PLLCFGR_PLLQ_0 (0x1UL << STM32_RCC_PLLCFGR_PLLQ_POS) -#define STM32_RCC_PLLCFGR_PLLQ_1 (0x2UL << STM32_RCC_PLLCFGR_PLLQ_POS) - -#define STM32_RCC_PLLCFGR_PLLREN_POS 24U -#define STM32_RCC_PLLCFGR_PLLREN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLREN_POS) -#define STM32_RCC_PLLCFGR_PLLREN STM32_RCC_PLLCFGR_PLLREN_MSK -#define STM32_RCC_PLLCFGR_PLLR_POS 25U -#define STM32_RCC_PLLCFGR_PLLR_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLR_POS) -#define STM32_RCC_PLLCFGR_PLLR STM32_RCC_PLLCFGR_PLLR_MSK -#define STM32_RCC_PLLCFGR_PLLR_0 (0x1UL << STM32_RCC_PLLCFGR_PLLR_POS) -#define STM32_RCC_PLLCFGR_PLLR_1 (0x2UL << STM32_RCC_PLLCFGR_PLLR_POS) - -#define STM32_RCC_PLLCFGR_PLLPDIV_POS 27U -#define STM32_RCC_PLLCFGR_PLLPDIV_MSK (0x1FUL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV STM32_RCC_PLLCFGR_PLLPDIV_MSK -#define STM32_RCC_PLLCFGR_PLLPDIV_0 (0x01UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV_1 (0x02UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV_2 (0x04UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV_3 (0x08UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV_4 (0x10UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLSRC_HSE STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK + +#define STM32_RCC_PLLCFGR_PLLM_POS 4U +#define STM32_RCC_PLLCFGR_PLLM_MSK (0x7UL << STM32_RCC_PLLCFGR_PLLM_POS) +#define STM32_RCC_PLLCFGR_PLLM STM32_RCC_PLLCFGR_PLLM_MSK +#define STM32_RCC_PLLCFGR_PLLM_0 (0x1UL << STM32_RCC_PLLCFGR_PLLM_POS) +#define STM32_RCC_PLLCFGR_PLLM_1 (0x2UL << STM32_RCC_PLLCFGR_PLLM_POS) +#define STM32_RCC_PLLCFGR_PLLM_2 (0x4UL << STM32_RCC_PLLCFGR_PLLM_POS) + +#define STM32_RCC_PLLCFGR_PLLN_POS 8U +#define STM32_RCC_PLLCFGR_PLLN_MSK (0x7FUL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN STM32_RCC_PLLCFGR_PLLN_MSK +#define STM32_RCC_PLLCFGR_PLLN_0 (0x01UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_1 (0x02UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_2 (0x04UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_3 (0x08UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_4 (0x10UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_5 (0x20UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_6 (0x40UL << STM32_RCC_PLLCFGR_PLLN_POS) + +#define STM32_RCC_PLLCFGR_PLLPEN_POS 16U +#define STM32_RCC_PLLCFGR_PLLPEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLPEN_POS) +#define STM32_RCC_PLLCFGR_PLLPEN STM32_RCC_PLLCFGR_PLLPEN_MSK +#define STM32_RCC_PLLCFGR_PLLP_POS 17U +#define STM32_RCC_PLLCFGR_PLLP_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLP_POS) +#define STM32_RCC_PLLCFGR_PLLP STM32_RCC_PLLCFGR_PLLP_MSK +#define STM32_RCC_PLLCFGR_PLLQEN_POS 20U +#define STM32_RCC_PLLCFGR_PLLQEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLQEN_POS) +#define STM32_RCC_PLLCFGR_PLLQEN STM32_RCC_PLLCFGR_PLLQEN_MSK + +#define STM32_RCC_PLLCFGR_PLLQ_POS 21U +#define STM32_RCC_PLLCFGR_PLLQ_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLQ_POS) +#define STM32_RCC_PLLCFGR_PLLQ STM32_RCC_PLLCFGR_PLLQ_MSK +#define STM32_RCC_PLLCFGR_PLLQ_0 (0x1UL << STM32_RCC_PLLCFGR_PLLQ_POS) +#define STM32_RCC_PLLCFGR_PLLQ_1 (0x2UL << STM32_RCC_PLLCFGR_PLLQ_POS) + +#define STM32_RCC_PLLCFGR_PLLREN_POS 24U +#define STM32_RCC_PLLCFGR_PLLREN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLREN_POS) +#define STM32_RCC_PLLCFGR_PLLREN STM32_RCC_PLLCFGR_PLLREN_MSK +#define STM32_RCC_PLLCFGR_PLLR_POS 25U +#define STM32_RCC_PLLCFGR_PLLR_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLR_POS) +#define STM32_RCC_PLLCFGR_PLLR STM32_RCC_PLLCFGR_PLLR_MSK +#define STM32_RCC_PLLCFGR_PLLR_0 (0x1UL << STM32_RCC_PLLCFGR_PLLR_POS) +#define STM32_RCC_PLLCFGR_PLLR_1 (0x2UL << STM32_RCC_PLLCFGR_PLLR_POS) + +#define STM32_RCC_PLLCFGR_PLLPDIV_POS 27U +#define STM32_RCC_PLLCFGR_PLLPDIV_MSK (0x1FUL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLPDIV STM32_RCC_PLLCFGR_PLLPDIV_MSK +#define STM32_RCC_PLLCFGR_PLLPDIV_0 (0x01UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLPDIV_1 (0x02UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLPDIV_2 (0x04UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLPDIV_3 (0x08UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLPDIV_4 (0x10UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) /**************** BIT DEFINITION FOR STM32_RCC_PLLSAI1CFGR REGISTER ********/ #define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS 8U @@ -845,7 +842,7 @@ #define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_6 \ (0x40UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS 16U +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS 16U #define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK \ (0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS) #define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK @@ -1225,8 +1222,10 @@ #define STM32_RCC_AHB1ENR_DMA2EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMA2EN_POS) #define STM32_RCC_AHB1ENR_DMA2EN STM32_RCC_AHB1ENR_DMA2EN_MSK #define STM32_RCC_AHB1ENR_DMAMUX1EN_POS 2U -#define STM32_RCC_AHB1ENR_DMAMUX1EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMAMUX1EN_POS) +#define STM32_RCC_AHB1ENR_DMAMUX1EN_MSK \ + (0x1UL << STM32_RCC_AHB1ENR_DMAMUX1EN_POS) #define STM32_RCC_AHB1ENR_DMAMUX1EN STM32_RCC_AHB1ENR_DMAMUX1EN_MSK +#define STM32_RCC_AHB1ENR_DMAMUXEN STM32_RCC_AHB1ENR_DMAMUX1EN_MSK #define STM32_RCC_AHB1ENR_FLASHEN_POS 8U #define STM32_RCC_AHB1ENR_FLASHEN_MSK (0x1UL << STM32_RCC_AHB1ENR_FLASHEN_POS) #define STM32_RCC_AHB1ENR_FLASHEN STM32_RCC_AHB1ENR_FLASHEN_MSK @@ -1337,12 +1336,10 @@ (0x1UL << STM32_RCC_APB1ENR1_USART3EN_POS) #define STM32_RCC_APB1ENR1_USART3EN STM32_RCC_APB1ENR1_USART3EN_MSK #define STM32_RCC_APB1ENR1_UART4EN_POS 19U -#define STM32_RCC_APB1ENR1_UART4EN_MSK \ - (0x1UL << STM32_RCC_APB1ENR1_UART4EN_POS) +#define STM32_RCC_APB1ENR1_UART4EN_MSK (0x1UL << STM32_RCC_APB1ENR1_UART4EN_POS) #define STM32_RCC_APB1ENR1_UART4EN STM32_RCC_APB1ENR1_UART4EN_MSK #define STM32_RCC_APB1ENR1_UART5EN_POS 20U -#define STM32_RCC_APB1ENR1_UART5EN_MSK \ - (0x1UL << STM32_RCC_APB1ENR1_UART5EN_POS) +#define STM32_RCC_APB1ENR1_UART5EN_MSK (0x1UL << STM32_RCC_APB1ENR1_UART5EN_POS) #define STM32_RCC_APB1ENR1_UART5EN STM32_RCC_APB1ENR1_UART5EN_MSK #define STM32_RCC_APB1ENR1_I2C1EN_POS 21U #define STM32_RCC_APB1ENR1_I2C1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C1EN_POS) @@ -1376,8 +1373,7 @@ (0x1UL << STM32_RCC_APB1ENR2_LPUART1EN_POS) #define STM32_RCC_APB1ENR2_LPUART1EN STM32_RCC_APB1ENR2_LPUART1EN_MSK #define STM32_RCC_APB1ENR2_I2C4EN_POS 1U -#define STM32_RCC_APB1ENR2_I2C4EN_MSK \ - (0x1UL << STM32_RCC_APB1ENR2_I2C4EN_POS) +#define STM32_RCC_APB1ENR2_I2C4EN_MSK (0x1UL << STM32_RCC_APB1ENR2_I2C4EN_POS) #define STM32_RCC_APB1ENR2_I2C4EN STM32_RCC_APB1ENR2_I2C4EN_MSK #define STM32_RCC_APB1ENR2_LPTIM2EN_POS 5U #define STM32_RCC_APB1ENR2_LPTIM2EN_MSK \ @@ -1392,12 +1388,10 @@ (0x1UL << STM32_RCC_APB1ENR2_FDCAN1EN_POS) #define STM32_RCC_APB1ENR2_FDCAN1EN STM32_RCC_APB1ENR2_FDCAN1EN_MSK #define STM32_RCC_APB1ENR2_USBFSEN_POS 21U -#define STM32_RCC_APB1ENR2_USBFSEN_MSK \ - (0x1UL << STM32_RCC_APB1ENR2_USBFSEN_POS) +#define STM32_RCC_APB1ENR2_USBFSEN_MSK (0x1UL << STM32_RCC_APB1ENR2_USBFSEN_POS) #define STM32_RCC_APB1ENR2_USBFSEN STM32_RCC_APB1ENR2_USBFSEN_MSK #define STM32_RCC_APB1ENR2_UCPD1EN_POS 23U -#define STM32_RCC_APB1ENR2_UCPD1EN_MSK \ - (0x1UL << STM32_RCC_APB1ENR2_UCPD1EN_POS) +#define STM32_RCC_APB1ENR2_UCPD1EN_MSK (0x1UL << STM32_RCC_APB1ENR2_UCPD1EN_POS) #define STM32_RCC_APB1ENR2_UCPD1EN STM32_RCC_APB1ENR2_UCPD1EN_MSK /************** BIT DEFINITION FOR STM32_RCC_APB2ENR REGISTER ***************/ @@ -1928,8 +1922,6 @@ #define STM32_CRS_CR_SWSYNC_MSK (0x1UL << STM32_CRS_CR_SWSYNC_POS) #define STM32_CRS_CR_SWSYNC STM32_CRS_CR_SWSYNC_MSK - - /*!< HSI48CAL configuration */ #define STM32_RCC_CRRCR_HSI48CAL_POS 7U #define STM32_RCC_CRRCR_HSI48CAL_MSK (0x1FFUL << STM32_RCC_CRRCR_HSI48CAL_POS) @@ -1949,102 +1941,100 @@ #define STM32_SYSCFG_I2CFMP(n) BIT(n + 21) /* Peripheral bits for STM32_RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB1_PWREN BIT(28) +#define STM32_RCC_PB1_PWREN BIT(28) -#define STM32_RCC_PB2_SYSCFGEN BIT(0) -#define STM32_RCC_PB2_USART1 BIT(14) +#define STM32_RCC_PB2_SYSCFGEN BIT(0) +#define STM32_RCC_PB2_USART1 BIT(14) -#define STM32_RCC_HB1_DMA1 BIT(0) -#define STM32_RCC_HB1_DMA2 BIT(1) +#define STM32_RCC_HB1_DMA1 BIT(0) +#define STM32_RCC_HB1_DMA2 BIT(1) -#define STM32_RCC_HB2_GPIOA BIT(0) -#define STM32_RCC_HB2_GPIOB BIT(1) -#define STM32_RCC_HB2_GPIOC BIT(2) -#define STM32_RCC_HB2_GPIOD BIT(3) -#define STM32_RCC_HB2_GPIOE BIT(4) -#define STM32_RCC_HB2_GPIOH BIT(7) -#define STM32_RCC_HB2_ADC1 BIT(13) +#define STM32_RCC_HB2_GPIOA BIT(0) +#define STM32_RCC_HB2_GPIOB BIT(1) +#define STM32_RCC_HB2_GPIOC BIT(2) +#define STM32_RCC_HB2_GPIOD BIT(3) +#define STM32_RCC_HB2_GPIOE BIT(4) +#define STM32_RCC_HB2_GPIOH BIT(7) +#define STM32_RCC_HB2_ADC1 BIT(13) /* Reset causes definitions */ /* Reset causes in RCC CSR register */ -#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG 0x60000000 -#define RESET_CAUSE_SFT 0x10000000 -#define RESET_CAUSE_POR 0x08000000 -#define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xff000000 -#define RESET_CAUSE_RMVF BIT(23) +#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR +#define RESET_CAUSE_WDG 0x60000000 +#define RESET_CAUSE_SFT 0x10000000 +#define RESET_CAUSE_POR 0x08000000 +#define RESET_CAUSE_PIN 0x04000000 +#define RESET_CAUSE_OTHER 0xff000000 +#define RESET_CAUSE_RMVF BIT(23) /* Power cause in PWR CSR register */ -#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR -#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_SCR -#define RESET_CAUSE_SBF BIT(8) -#define RESET_CAUSE_SBF_CLR BIT(8) +#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR +#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_SCR +#define RESET_CAUSE_SBF BIT(8) +#define RESET_CAUSE_SBF_CLR BIT(8) /* --- Watchdogs --- */ /* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_WUTE BIT(10) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_CR_WUTIE BIT(14) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_WUTWF BIT(2) -#define STM32_RTC_ISR_INITS BIT(4) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_ISR_WUTF BIT(9) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) +#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) +#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) +#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) +#define STM32_RTC_CR_BYPSHAD BIT(5) +#define STM32_RTC_CR_ALRAE BIT(8) +#define STM32_RTC_CR_WUTE BIT(10) +#define STM32_RTC_CR_ALRAIE BIT(12) +#define STM32_RTC_CR_WUTIE BIT(14) +#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) +#define STM32_RTC_ISR_ALRAWF BIT(0) +#define STM32_RTC_ISR_WUTWF BIT(2) +#define STM32_RTC_ISR_INITS BIT(4) +#define STM32_RTC_ISR_RSF BIT(5) +#define STM32_RTC_ISR_INITF BIT(6) +#define STM32_RTC_ISR_INIT BIT(7) +#define STM32_RTC_ISR_ALRAF BIT(8) +#define STM32_RTC_ISR_WUTF BIT(9) +#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) +#define STM32_RTC_PRER_A_MASK (0x7f << 16) +#define STM32_RTC_PRER_S_MASK (0x7fff << 0) +#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) +#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) +#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) +#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) +#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) +#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) +#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) +#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) +#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) +#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) +#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) #define STM32_RTC_CLEAR_FLAG(x) \ - (STM32_RTC_ISR = (~((x) | STM32_RTC_ISR_INIT) | \ - (STM32_RTC_ISR & STM32_RTC_ISR_INIT))) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 128 - -#define RTC_TR_PM_POS 22U -#define RTC_TR_PM_MSK (0x1UL << RTC_TR_PM_POS) -#define RTC_TR_PM RTC_TR_PM_MSK -#define RTC_TR_HT_POS 20U -#define RTC_TR_HT_MSK (0x3UL << RTC_TR_HT_POS) -#define RTC_TR_HT RTC_TR_HT_MSK -#define RTC_TR_HU_POS 16U -#define RTC_TR_HU_MSK (0xFUL << RTC_TR_HU_POS) -#define RTC_TR_HU RTC_TR_HU_MSK -#define RTC_TR_MNT_POS 12U -#define RTC_TR_MNT_MSK (0x7UL << RTC_TR_MNT_POS) -#define RTC_TR_MNT RTC_TR_MNT_MSK -#define RTC_TR_MNU_POS 8U -#define RTC_TR_MNU_MSK (0xFUL << RTC_TR_MNU_POS) -#define RTC_TR_MNU RTC_TR_MNU_MSK -#define RTC_TR_ST_POS 4U -#define RTC_TR_ST_MSK (0x7UL << RTC_TR_ST_POS) -#define RTC_TR_ST RTC_TR_ST_MSK -#define RTC_TR_SU_POS 0U -#define RTC_TR_SU_MSK (0xFUL << RTC_TR_SU_POS) -#define RTC_TR_SU RTC_TR_SU_MSK - - + (STM32_RTC_ISR = (~((x) | STM32_RTC_ISR_INIT) | \ + (STM32_RTC_ISR & STM32_RTC_ISR_INIT))) + +#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) +#define STM32_BKP_BYTES 128 + +#define RTC_TR_PM_POS 22U +#define RTC_TR_PM_MSK (0x1UL << RTC_TR_PM_POS) +#define RTC_TR_PM RTC_TR_PM_MSK +#define RTC_TR_HT_POS 20U +#define RTC_TR_HT_MSK (0x3UL << RTC_TR_HT_POS) +#define RTC_TR_HT RTC_TR_HT_MSK +#define RTC_TR_HU_POS 16U +#define RTC_TR_HU_MSK (0xFUL << RTC_TR_HU_POS) +#define RTC_TR_HU RTC_TR_HU_MSK +#define RTC_TR_MNT_POS 12U +#define RTC_TR_MNT_MSK (0x7UL << RTC_TR_MNT_POS) +#define RTC_TR_MNT RTC_TR_MNT_MSK +#define RTC_TR_MNU_POS 8U +#define RTC_TR_MNU_MSK (0xFUL << RTC_TR_MNU_POS) +#define RTC_TR_MNU RTC_TR_MNU_MSK +#define RTC_TR_ST_POS 4U +#define RTC_TR_ST_MSK (0x7UL << RTC_TR_ST_POS) +#define RTC_TR_ST RTC_TR_ST_MSK +#define RTC_TR_SU_POS 0U +#define RTC_TR_SU_MSK (0xFUL << RTC_TR_SU_POS) +#define RTC_TR_SU RTC_TR_SU_MSK /* --- SPI --- */ @@ -2061,8 +2051,8 @@ struct stm32_spi_regs { unsigned int crcpr; unsigned int rxcrcr; unsigned int txcrcr; - unsigned int i2scfgr; /* STM32L only */ - unsigned int i2spr; /* STM32L only */ + unsigned int i2scfgr; /* STM32L only */ + unsigned int i2spr; /* STM32L only */ }; /* Must be volatile, or compiler optimizes out repeated accesses */ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; @@ -2072,227 +2062,152 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) +#define STM32_SPI_CR1_BIDIMODE BIT(15) +#define STM32_SPI_CR1_BIDIOE BIT(14) +#define STM32_SPI_CR1_CRCEN BIT(13) +#define STM32_SPI_CR1_SSM BIT(9) +#define STM32_SPI_CR1_SSI BIT(8) +#define STM32_SPI_CR1_LSBFIRST BIT(7) +#define STM32_SPI_CR1_SPE BIT(6) +#define STM32_SPI_CR1_BR_DIV64R (5 << 3) +#define STM32_SPI_CR1_BR_DIV4R BIT(3) +#define STM32_SPI_CR1_MSTR BIT(2) +#define STM32_SPI_CR1_CPOL BIT(1) +#define STM32_SPI_CR1_CPHA BIT(0) +#define STM32_SPI_CR2_FRXTH BIT(12) +#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8) +#define STM32_SPI_CR2_TXEIE BIT(7) +#define STM32_SPI_CR2_RXNEIE BIT(6) +#define STM32_SPI_CR2_NSSP BIT(3) +#define STM32_SPI_CR2_SSOE BIT(2) +#define STM32_SPI_CR2_TXDMAEN BIT(1) +#define STM32_SPI_CR2_RXDMAEN BIT(0) + +#define STM32_SPI_SR_RXNE BIT(0) +#define STM32_SPI_SR_TXE BIT(1) +#define STM32_SPI_SR_CRCERR BIT(4) +#define STM32_SPI_SR_BSY BIT(7) +#define STM32_SPI_SR_FRLVL (3 << 9) +#define STM32_SPI_SR_FTLVL (3 << 11) /* --- Debug --- */ -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) +#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) +#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) /* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) +#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) #define STM32_FLASH_ACR_LATENCY_SHIFT (0) -#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) -#define STM32_FLASH_ACR_PRFTEN BIT(8) -#define STM32_FLASH_ACR_ICEN BIT(9) -#define STM32_FLASH_ACR_DCEN BIT(10) -#define STM32_FLASH_ACR_ICRST BIT(11) -#define STM32_FLASH_ACR_DCRST BIT(12) -#define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_OPTKEYR_KEY1 0x08192A3B -#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x20) -#define FLASH_SR_BUSY BIT(16) -#define FLASH_SR_ERR_MASK (0xc3fa) -#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x28) -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_STRT BIT(16) -#define FLASH_CR_OPTSTRT BIT(17) -#define FLASH_CR_OBL_LAUNCH BIT(27) -#define FLASH_CR_OPTLOCK BIT(30) -#define FLASH_CR_LOCK BIT(31) -#define FLASH_CR_PNB(sec) (((sec) & 0xff) << 3) -#define FLASH_CR_PNB_MASK FLASH_CR_PNB(0xff) -#define STM32_FLASH_ECCR REG32(STM32_FLASH_REGS_BASE + 0x30) -#define STM32_FLASH_OPTR REG32(STM32_FLASH_REGS_BASE + 0x40) -#define STM32_FLASH_WRP1AR REG32(STM32_FLASH_REGS_BASE + 0x58) -#define STM32_FLASH_WRP1BR REG32(STM32_FLASH_REGS_BASE + 0x5C) +#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) +#define STM32_FLASH_ACR_PRFTEN BIT(8) +#define STM32_FLASH_ACR_ICEN BIT(9) +#define STM32_FLASH_ACR_DCEN BIT(10) +#define STM32_FLASH_ACR_ICRST BIT(11) +#define STM32_FLASH_ACR_DCRST BIT(12) +#define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x04) +#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x08) +#define FLASH_KEYR_KEY1 0x45670123 +#define FLASH_KEYR_KEY2 0xCDEF89AB +#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x10) +#define FLASH_OPTKEYR_KEY1 0x08192A3B +#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F +#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x20) +#define FLASH_SR_BUSY BIT(16) +#define FLASH_SR_ERR_MASK (0xc3fa) +#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x28) +#define FLASH_CR_PG BIT(0) +#define FLASH_CR_PER BIT(1) +#define FLASH_CR_STRT BIT(16) +#define FLASH_CR_OPTSTRT BIT(17) +#define FLASH_CR_OBL_LAUNCH BIT(27) +#define FLASH_CR_OPTLOCK BIT(30) +#define FLASH_CR_LOCK BIT(31) +#define FLASH_CR_PNB(sec) (((sec)&0xff) << 3) +#define FLASH_CR_PNB_MASK FLASH_CR_PNB(0xff) +#define STM32_FLASH_ECCR REG32(STM32_FLASH_REGS_BASE + 0x30) +#define STM32_FLASH_OPTR REG32(STM32_FLASH_REGS_BASE + 0x40) +#define STM32_FLASH_WRP1AR REG32(STM32_FLASH_REGS_BASE + 0x58) +#define STM32_FLASH_WRP1BR REG32(STM32_FLASH_REGS_BASE + 0x5C) /* Minimum number of bytes that can be written to flash */ -#define STM32_FLASH_MIN_WRITE_SIZE CONFIG_FLASH_WRITE_SIZE +#define STM32_FLASH_MIN_WRITE_SIZE CONFIG_FLASH_WRITE_SIZE -#define STM32_OPTB_WRP1AR STM32_FLASH_WRP1AR -#define STM32_OPTB_WRP1BR STM32_FLASH_WRP1BR +#define STM32_OPTB_WRP1AR STM32_FLASH_WRP1AR +#define STM32_OPTB_WRP1BR STM32_FLASH_WRP1BR /* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) +#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) +#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) +#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) +#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) +#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) +#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) -#define EXTI_RTC_ALR_EVENT BIT(18) +#define EXTI_RTC_ALR_EVENT BIT(18) /* --- ADC --- */ -#define STM32_ADC1_ISR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC1_ISR_ADRDY BIT(0) -#define STM32_ADC1_IER REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC1_IER_AWDIE BIT(7) -#define STM32_ADC1_IER_OVRIE BIT(4) -#define STM32_ADC1_IER_EOSEQIE BIT(3) -#define STM32_ADC1_IER_EOCIE BIT(2) -#define STM32_ADC1_IER_EOSMPIE BIT(1) -#define STM32_ADC1_IER_ADRDYIE BIT(0) - -#define STM32_ADC1_CR REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC1_CR_ADEN BIT(0) -#define STM32_ADC1_CR_ADDIS BIT(1) -#define STM32_ADC1_CR_ADSTP BIT(4) -#define STM32_ADC1_CR_ADVREGEN BIT(28) -#define STM32_ADC1_CR_DEEPPWD BIT(29) -#define STM32_ADC1_CR_ADCAL BIT(31) -#define STM32_ADC1_CFGR REG32(STM32_ADC1_BASE + 0x0C) +#define STM32_ADC1_ISR REG32(STM32_ADC1_BASE + 0x00) +#define STM32_ADC1_ISR_ADRDY BIT(0) +#define STM32_ADC1_IER REG32(STM32_ADC1_BASE + 0x04) +#define STM32_ADC1_IER_AWDIE BIT(7) +#define STM32_ADC1_IER_OVRIE BIT(4) +#define STM32_ADC1_IER_EOSEQIE BIT(3) +#define STM32_ADC1_IER_EOCIE BIT(2) +#define STM32_ADC1_IER_EOSMPIE BIT(1) +#define STM32_ADC1_IER_ADRDYIE BIT(0) + +#define STM32_ADC1_CR REG32(STM32_ADC1_BASE + 0x08) +#define STM32_ADC1_CR_ADEN BIT(0) +#define STM32_ADC1_CR_ADDIS BIT(1) +#define STM32_ADC1_CR_ADSTP BIT(4) +#define STM32_ADC1_CR_ADVREGEN BIT(28) +#define STM32_ADC1_CR_DEEPPWD BIT(29) +#define STM32_ADC1_CR_ADCAL BIT(31) +#define STM32_ADC1_CFGR REG32(STM32_ADC1_BASE + 0x0C) /* Analog watchdog channel selection */ -#define STM32_ADC1_CFGR_AWDCH_MASK (0x1f << 26) -#define STM32_ADC1_CFGR_AWDEN BIT(23) -#define STM32_ADC1_CFGR_AWDSGL BIT(22) -#define STM32_ADC1_CFGR_AUTDLY BIT(14) +#define STM32_ADC1_CFGR_AWDCH_MASK (0x1f << 26) +#define STM32_ADC1_CFGR_AWDEN BIT(23) +#define STM32_ADC1_CFGR_AWDSGL BIT(22) +#define STM32_ADC1_CFGR_AUTDLY BIT(14) /* Selects single vs continuous */ -#define STM32_ADC1_CFGR_CONT BIT(13) +#define STM32_ADC1_CFGR_CONT BIT(13) /* Selects ADC_DR overwrite vs preserve */ -#define STM32_ADC1_CFGR_OVRMOD BIT(12) +#define STM32_ADC1_CFGR_OVRMOD BIT(12) /* External trigger polarity selection */ -#define STM32_ADC1_CFGR_EXTEN_DIS (0 << 10) -#define STM32_ADC1_CFGR_EXTEN_RISE (1 << 10) -#define STM32_ADC1_CFGR_EXTEN_FALL (2 << 10) -#define STM32_ADC1_CFGR_EXTEN_BOTH (3 << 10) -#define STM32_ADC1_CFGR_EXTEN_MASK (3 << 10) -#define STM32_ADC1_CFGR_ALIGN BIT(5) +#define STM32_ADC1_CFGR_EXTEN_DIS (0 << 10) +#define STM32_ADC1_CFGR_EXTEN_RISE (1 << 10) +#define STM32_ADC1_CFGR_EXTEN_FALL (2 << 10) +#define STM32_ADC1_CFGR_EXTEN_BOTH (3 << 10) +#define STM32_ADC1_CFGR_EXTEN_MASK (3 << 10) +#define STM32_ADC1_CFGR_ALIGN BIT(5) /* External trigger selection */ -#define STM32_ADC1_CFGR_TRG0 (0 << 6) -#define STM32_ADC1_CFGR_TRG1 (1 << 6) -#define STM32_ADC1_CFGR_TRG2 (2 << 6) -#define STM32_ADC1_CFGR_TRG3 (3 << 6) -#define STM32_ADC1_CFGR_TRG4 (4 << 6) -#define STM32_ADC1_CFGR_TRG5 (5 << 6) -#define STM32_ADC1_CFGR_TRG6 (6 << 6) -#define STM32_ADC1_CFGR_TRG7 (7 << 6) -#define STM32_ADC1_CFGR_TRG_MASK (7 << 6) +#define STM32_ADC1_CFGR_TRG0 (0 << 6) +#define STM32_ADC1_CFGR_TRG1 (1 << 6) +#define STM32_ADC1_CFGR_TRG2 (2 << 6) +#define STM32_ADC1_CFGR_TRG3 (3 << 6) +#define STM32_ADC1_CFGR_TRG4 (4 << 6) +#define STM32_ADC1_CFGR_TRG5 (5 << 6) +#define STM32_ADC1_CFGR_TRG6 (6 << 6) +#define STM32_ADC1_CFGR_TRG7 (7 << 6) +#define STM32_ADC1_CFGR_TRG_MASK (7 << 6) /* Selects circular vs one-shot */ -#define STM32_ADC1_CFGR_DMACFG BIT(1) -#define STM32_ADC1_CFGR_DMAEN BIT(0) -#define STM32_ADC1_CFGR2 REG32(STM32_ADC1_BASE + 0x10) +#define STM32_ADC1_CFGR_DMACFG BIT(1) +#define STM32_ADC1_CFGR_DMAEN BIT(0) +#define STM32_ADC1_CFGR2 REG32(STM32_ADC1_BASE + 0x10) /* Sampling time selection - 1.5 ADC cycles min, 239.5 cycles max */ -#define STM32_ADC1_SMPR1 REG32(STM32_ADC1_BASE + 0x14) -#define STM32_ADC1_SMPR2 REG32(STM32_ADC1_BASE + 0x18) +#define STM32_ADC1_SMPR1 REG32(STM32_ADC1_BASE + 0x14) +#define STM32_ADC1_SMPR2 REG32(STM32_ADC1_BASE + 0x18) /* Macro to convert enum stm32_adc_smpr to SMP bits of the ADC_SMPR register */ -#define STM32_ADC1_SMPR_SMP(s) ((s) - 1) -#define STM32_ADC1_TR REG32(STM32_ADC1_BASE + 0x20) -#define STM32_ADC1_CHSELR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC1_DR REG32(STM32_ADC1_BASE + 0x40) -#define STM32_ADC1_JSQR REG32(STM32_ADC1_BASE + 0x4C) -#define STM32_ADC1_JDR1 REG32(STM32_ADC1_BASE + 0x80) -#define STM32_ADC1_JDR2 REG32(STM32_ADC1_BASE + 0x84) -#define STM32_ADC1_JDR3 REG32(STM32_ADC1_BASE + 0x88) -#define STM32_ADC1_JDR4 REG32(STM32_ADC1_BASE + 0x8C) -#define STM32_ADC1_CCR REG32(STM32_ADC1_BASE + 0x308) +#define STM32_ADC1_SMPR_SMP(s) ((s)-1) +#define STM32_ADC1_TR REG32(STM32_ADC1_BASE + 0x20) +#define STM32_ADC1_CHSELR REG32(STM32_ADC1_BASE + 0x28) +#define STM32_ADC1_DR REG32(STM32_ADC1_BASE + 0x40) +#define STM32_ADC1_JSQR REG32(STM32_ADC1_BASE + 0x4C) +#define STM32_ADC1_JDR1 REG32(STM32_ADC1_BASE + 0x80) +#define STM32_ADC1_JDR2 REG32(STM32_ADC1_BASE + 0x84) +#define STM32_ADC1_JDR3 REG32(STM32_ADC1_BASE + 0x88) +#define STM32_ADC1_JDR4 REG32(STM32_ADC1_BASE + 0x8C) +#define STM32_ADC1_CCR REG32(STM32_ADC1_BASE + 0x308) /* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) -#define STM32_USB_BCDR_DPPU BIT(15) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) +#define STM32_USB_BCDR_DPPU BIT(15) /* --- DMA --- */ @@ -2344,11 +2259,11 @@ enum dma_channel { /* Registers for a single channel of the DMA controller */ struct stm32_dma_chan { - uint32_t ccr; /* Control */ - uint32_t cndtr; /* Number of data to transfer */ - uint32_t cpar; /* Peripheral address */ - uint32_t cmar; /* Memory address */ - uint32_t reserved; + uint32_t ccr; /* Control */ + uint32_t cndtr; /* Number of data to transfer */ + uint32_t cpar; /* Peripheral address */ + uint32_t cmar; /* Memory address */ + uint32_t reserved; }; /* Always use stm32_dma_chan_t so volatile keyword is included! */ @@ -2359,8 +2274,8 @@ typedef stm32_dma_chan_t dma_chan_t; /* Registers for the DMA controller */ struct stm32_dma_regs { - uint32_t isr; - uint32_t ifcr; + uint32_t isr; + uint32_t ifcr; stm32_dma_chan_t chan[STM32_DMAC_COUNT]; }; @@ -2369,74 +2284,175 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - -#define STM32_DMA_CCR_CHANNEL(channel) (0) +#define STM32_DMA_CCR_CHANNEL(channel) (0) #define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE) #define STM32_DMA_REGS(channel) \ ((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS) -#define STM32_DMA_CSELR(channel) \ - REG32(((channel) < STM32_DMAC_PER_CTLR ? \ - STM32_DMA1_BASE : STM32_DMA2_BASE) + 0xA8) +#define STM32_DMA_CSELR(channel) \ + REG32(((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_BASE : \ + STM32_DMA2_BASE) + \ + 0xA8) /* Bits for DMA controller regs (isr and ifcr) */ -#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) +#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) #define STM32_DMA_ISR_MASK(channel, mask) \ ((mask) << STM32_DMA_CH_OFFSET(channel)) -#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) -#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) -#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) -#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) -#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) - -#define STM32_DMA_GIF BIT(0) -#define STM32_DMA_TCIF BIT(1) -#define STM32_DMA_HTIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_ALL 0xf - -#define STM32_DMA_GET_ISR(channel) \ - ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr = \ - ((STM32_DMA_REGS(channel)->isr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) -#define STM32_DMA_GET_IFCR(channel) \ - ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr = \ - ((STM32_DMA_REGS(channel)->ifcr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) - +#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) +#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) +#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) +#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) +#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) + +#define STM32_DMA_GIF BIT(0) +#define STM32_DMA_TCIF BIT(1) +#define STM32_DMA_HTIF BIT(2) +#define STM32_DMA_TEIF BIT(3) +#define STM32_DMA_ALL 0xf + +#define STM32_DMA_GET_ISR(channel) \ + ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) & \ + STM32_DMA_ALL) +#define STM32_DMA_SET_ISR(channel, val) \ + (STM32_DMA_REGS(channel)->isr = \ + ((STM32_DMA_REGS(channel)->isr & \ + ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) +#define STM32_DMA_GET_IFCR(channel) \ + ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) & \ + STM32_DMA_ALL) +#define STM32_DMA_SET_IFCR(channel, val) \ + (STM32_DMA_REGS(channel)->ifcr = \ + ((STM32_DMA_REGS(channel)->ifcr & \ + ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) /* Bits for DMA channel regs */ -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_TCIE BIT(1) -#define STM32_DMA_CCR_HTIE BIT(2) -#define STM32_DMA_CCR_TEIE BIT(3) -#define STM32_DMA_CCR_DIR BIT(4) -#define STM32_DMA_CCR_CIRC BIT(5) -#define STM32_DMA_CCR_PINC BIT(6) -#define STM32_DMA_CCR_MINC BIT(7) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) -#define STM32_DMA_CCR_PL_LOW (0 << 12) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) -#define STM32_DMA_CCR_PL_HIGH (2 << 12) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) -#define STM32_DMA_CCR_MEM2MEM BIT(14) +#define STM32_DMA_CCR_EN BIT(0) +#define STM32_DMA_CCR_TCIE BIT(1) +#define STM32_DMA_CCR_HTIE BIT(2) +#define STM32_DMA_CCR_TEIE BIT(3) +#define STM32_DMA_CCR_DIR BIT(4) +#define STM32_DMA_CCR_CIRC BIT(5) +#define STM32_DMA_CCR_PINC BIT(6) +#define STM32_DMA_CCR_MINC BIT(7) +#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) +#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) +#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) +#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) +#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) +#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) +#define STM32_DMA_CCR_PL_LOW (0 << 12) +#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) +#define STM32_DMA_CCR_PL_HIGH (2 << 12) +#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) +#define STM32_DMA_CCR_MEM2MEM BIT(14) + +/* The requests for the DMA1/DMA2 controllers are routed through DMAMUX. */ +/* DMAMUX registers */ +#define STM32_DMAMUX_CxCR(x) REG32(STM32_DMAMUX_BASE + 4 * (x)) +#define STM32_DMAMUX_CSR REG32(STM32_DMAMUX_BASE + 0x80) +#define STM32_DMAMUX_CFR REG32(STM32_DMAMUX_BASE + 0x84) +#define STM32_DMAMUX_RGxCR(x) REG32(STM32_DMAMUX_BASE + 0x100 + 4 * (x)) +#define STM32_DMAMUX_RGSR REG32(STM32_DMAMUX_BASE + 0x140) +#define STM32_DMAMUX_RGCFR REG32(STM32_DMAMUX_BASE + 0x144) + +enum dmamux1_request { + DMAMUX_REQ_ADC1 = 5, + DMAMUX_REQ_ADC2 = 6, + DMAMUX_REQ_DAC1 = 7, + DMAMUX_REQ_DAC2 = 8, + DMAMUX_REQ_TIM6_UP = 9, + DMAMUX_REQ_TIM7_UP = 10, + DMAMUX_REQ_SPI1_RX = 11, + DMAMUX_REQ_SPI1_TX = 12, + DMAMUX_REQ_SPI2_RX = 13, + DMAMUX_REQ_SPI2_TX = 14, + DMAMUX_REQ_SPI3_RX = 15, + DMAMUX_REQ_SPI3_TX = 16, + DMAMUX_REQ_I2C1_RX = 17, + DMAMUX_REQ_I2C1_TX = 18, + DMAMUX_REQ_I2C2_RX = 19, + DMAMUX_REQ_I2C2_TX = 20, + DMAMUX_REQ_I2C3_RX = 21, + DMAMUX_REQ_I2C3_TX = 22, + DMAMUX_REQ_I2C4_RX = 23, + DMAMUX_REQ_I2C4_TX = 24, + DMAMUX_REQ_USART1_RX = 25, + DMAMUX_REQ_USART1_TX = 26, + DMAMUX_REQ_USART2_RX = 27, + DMAMUX_REQ_USART2_TX = 28, + DMAMUX_REQ_USART3_RX = 29, + DMAMUX_REQ_USART3_TX = 30, + DMAMUX_REQ_UART4_RX = 31, + DMAMUX_REQ_UART4_TX = 32, + DMAMUX_REQ_UART5_RX = 33, + DMAMUX_REQ_UART5_TX = 34, + DMAMUX_REQ_LPUART1_RX = 35, + DMAMUX_REQ_LPUART1_TX = 36, + DMAMUX_REQ_SAI1_A = 37, + DMAMUX_REQ_SAI1_B = 38, + DMAMUX_REQ_SAI2_A = 39, + DMAMUX_REQ_SAI2_B = 40, + DMAMUX_REQ_OCTOSPI1 = 41, + DMAMUX_REQ_TIM1_CH1 = 42, + DMAMUX_REQ_TIM1_CH2 = 43, + DMAMUX_REQ_TIM1_CH3 = 44, + DMAMUX_REQ_TIM1_CH4 = 45, + DMAMUX_REQ_TIM1_UP = 46, + DMAMUX_REQ_TIM1_TRIG = 47, + DMAMUX_REQ_TIM1_COM = 48, + DMAMUX_REQ_TIM8_CH1 = 49, + DMAMUX_REQ_TIM8_CH2 = 50, + DMAMUX_REQ_TIM8_CH3 = 51, + DMAMUX_REQ_TIM8_CH4 = 52, + DMAMUX_REQ_TIM8_UP = 53, + DMAMUX_REQ_TIM8_TRIG = 54, + DMAMUX_REQ_TIM8_COM = 55, + DMAMUX_REQ_TIM2_CH1 = 56, + DMAMUX_REQ_TIM2_CH2 = 57, + DMAMUX_REQ_TIM2_CH3 = 58, + DMAMUX_REQ_TIM2_CH4 = 59, + DMAMUX_REQ_TIM2_UP = 60, + DMAMUX_REQ_TIM3_CH1 = 61, + DMAMUX_REQ_TIM3_CH2 = 62, + DMAMUX_REQ_TIM3_CH3 = 63, + DMAMUX_REQ_TIM3_CH4 = 64, + DMAMUX_REQ_TIM3_UP = 65, + DMAMUX_REQ_TIM3_TRIG = 66, + DMAMUX_REQ_TIM4_CH1 = 67, + DMAMUX_REQ_TIM4_CH2 = 68, + DMAMUX_REQ_TIM4_CH3 = 69, + DMAMUX_REQ_TIM4_CH4 = 70, + DMAMUX_REQ_TIM4_UP = 71, + DMAMUX_REQ_TIM5_CH1 = 72, + DMAMUX_REQ_TIM5_CH2 = 73, + DMAMUX_REQ_TIM5_CH3 = 74, + DMAMUX_REQ_TIM5_CH4 = 75, + DMAMUX_REQ_TIM5_UP = 76, + DMAMUX_REQ_TIM5_TRIG = 77, + DMAMUX_REQ_TIM15_CH1 = 78, + DMAMUX_REQ_TIM15_UP = 79, + DMAMUX_REQ_TIM15_TRIG = 80, + DMAMUX_REQ_TIM15_COM = 81, + DMAMUX_REQ_TIM16_CH1 = 82, + DMAMUX_REQ_TIM16_UP = 83, + DMAMUX_REQ_TIM17_CH1 = 84, + DMAMUX_REQ_TIM17_UP = 85, + DMAMUX_REQ_DFSDM1_FLT0 = 86, + DMAMUX_REQ_DFSDM1_FLT1 = 87, + DMAMUX_REQ_DFSDM1_FLT2 = 88, + DMAMUX_REQ_DFSDM1_FLT3 = 89, + DMAMUX_REQ_AES_IN = 90, + DMAMUX_REQ_AES_OUT = 91, + DMAMUX_REQ_HASH_IN = 92, + DMAMUX_REQ_USBPD_TX = 93, + DMAMUX_REQ_USBPD_RX = 94, +}; /* LPUART gets accessed as UART9 in STM32 uart module */ -#define STM32_USART9_BASE STM32_LPUART1_BASE -#define STM32_IRQ_USART9 STM32_IRQ_LPUART1 -#define DMAMUX_REQ_UART9_RX DMAMUX_REQ_LPUART1_RX -#define DMAMUX_REQ_UART9_TX DMAMUX_REQ_LPUART1_TX +#define STM32_USART9_BASE STM32_LPUART1_BASE +#define STM32_IRQ_USART9 STM32_IRQ_LPUART1 +#define DMAMUX_REQ_UART9_RX DMAMUX_REQ_LPUART1_RX +#define DMAMUX_REQ_UART9_TX DMAMUX_REQ_LPUART1_TX #endif /* !__ASSEMBLER__ */ diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 320a3852f1..2ec0ff28fc 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -46,74 +46,71 @@ #include "common.h" #include "compile_time_macros.h" - #ifndef __ASSEMBLER__ /* Register definitions */ /* --- USART --- */ -#define STM32_USART_BASE(n) CONCAT3(STM32_USART, n, _BASE) +#define STM32_USART_BASE(n) CONCAT3(STM32_USART, n, _BASE) #define STM32_USART_REG(base, offset) REG32((base) + (offset)) -#define STM32_IRQ_USART(n) CONCAT2(STM32_IRQ_USART, n) +#define STM32_IRQ_USART(n) CONCAT2(STM32_IRQ_USART, n) /* --- TIMERS --- */ -#define STM32_TIM_BASE(n) CONCAT3(STM32_TIM, n, _BASE) - -#define STM32_TIM_REG(n, offset) \ - REG16(STM32_TIM_BASE(n) + (offset)) -#define STM32_TIM_REG32(n, offset) \ - REG32(STM32_TIM_BASE(n) + (offset)) - -#define STM32_TIM_CR1(n) STM32_TIM_REG(n, 0x00) -#define STM32_TIM_CR1_CEN BIT(0) -#define STM32_TIM_CR2(n) STM32_TIM_REG(n, 0x04) -#define STM32_TIM_SMCR(n) STM32_TIM_REG(n, 0x08) -#define STM32_TIM_DIER(n) STM32_TIM_REG(n, 0x0C) -#define STM32_TIM_SR(n) STM32_TIM_REG(n, 0x10) -#define STM32_TIM_EGR(n) STM32_TIM_REG(n, 0x14) -#define STM32_TIM_EGR_UG BIT(0) -#define STM32_TIM_CCMR1(n) STM32_TIM_REG(n, 0x18) -#define STM32_TIM_CCMR1_OC1PE BIT(2) +#define STM32_TIM_BASE(n) CONCAT3(STM32_TIM, n, _BASE) + +#define STM32_TIM_REG(n, offset) REG16(STM32_TIM_BASE(n) + (offset)) +#define STM32_TIM_REG32(n, offset) REG32(STM32_TIM_BASE(n) + (offset)) + +#define STM32_TIM_CR1(n) STM32_TIM_REG(n, 0x00) +#define STM32_TIM_CR1_CEN BIT(0) +#define STM32_TIM_CR2(n) STM32_TIM_REG(n, 0x04) +#define STM32_TIM_SMCR(n) STM32_TIM_REG(n, 0x08) +#define STM32_TIM_DIER(n) STM32_TIM_REG(n, 0x0C) +#define STM32_TIM_SR(n) STM32_TIM_REG(n, 0x10) +#define STM32_TIM_EGR(n) STM32_TIM_REG(n, 0x14) +#define STM32_TIM_EGR_UG BIT(0) +#define STM32_TIM_CCMR1(n) STM32_TIM_REG(n, 0x18) +#define STM32_TIM_CCMR1_OC1PE BIT(2) /* Use in place of TIM_CCMR1_OC1M_0 through 2 from STM documentation. */ -#define STM32_TIM_CCMR1_OC1M(n) (((n) & 0x7) << 4) -#define STM32_TIM_CCMR1_OC1M_MASK STM32_TIM_CCMR1_OC1M(~0) -#define STM32_TIM_CCMR1_OC1M_FROZEN STM32_TIM_CCMR1_OC1M(0x0) -#define STM32_TIM_CCMR1_OC1M_ACTIVE_ON_MATCH STM32_TIM_CCMR1_OC1M(0x1) +#define STM32_TIM_CCMR1_OC1M(n) (((n)&0x7) << 4) +#define STM32_TIM_CCMR1_OC1M_MASK STM32_TIM_CCMR1_OC1M(~0) +#define STM32_TIM_CCMR1_OC1M_FROZEN STM32_TIM_CCMR1_OC1M(0x0) +#define STM32_TIM_CCMR1_OC1M_ACTIVE_ON_MATCH STM32_TIM_CCMR1_OC1M(0x1) #define STM32_TIM_CCMR1_OC1M_INACTIVE_ON_MATCH STM32_TIM_CCMR1_OC1M(0x2) -#define STM32_TIM_CCMR1_OC1M_TOGGLE STM32_TIM_CCMR1_OC1M(0x3) -#define STM32_TIM_CCMR1_OC1M_FORCE_INACTIVE STM32_TIM_CCMR1_OC1M(0x4) -#define STM32_TIM_CCMR1_OC1M_FORCE_ACTIVE STM32_TIM_CCMR1_OC1M(0x5) -#define STM32_TIM_CCMR1_OC1M_PWM_MODE_1 STM32_TIM_CCMR1_OC1M(0x6) -#define STM32_TIM_CCMR1_OC1M_PWM_MODE_2 STM32_TIM_CCMR1_OC1M(0x7) -#define STM32_TIM_CCMR2(n) STM32_TIM_REG(n, 0x1C) -#define STM32_TIM_CCER(n) STM32_TIM_REG(n, 0x20) -#define STM32_TIM_CCER_CC1E BIT(0) -#define STM32_TIM_CCER_CC1P BIT(1) -#define STM32_TIM_CCER_CC1NE BIT(2) -#define STM32_TIM_CCER_CC1NP BIT(3) -#define STM32_TIM_CNT(n) STM32_TIM_REG(n, 0x24) -#define STM32_TIM_PSC(n) STM32_TIM_REG(n, 0x28) -#define STM32_TIM_ARR(n) STM32_TIM_REG(n, 0x2C) -#define STM32_TIM_RCR(n) STM32_TIM_REG(n, 0x30) -#define STM32_TIM_CCR1(n) STM32_TIM_REG(n, 0x34) -#define STM32_TIM_CCR2(n) STM32_TIM_REG(n, 0x38) -#define STM32_TIM_CCR3(n) STM32_TIM_REG(n, 0x3C) -#define STM32_TIM_CCR4(n) STM32_TIM_REG(n, 0x40) -#define STM32_TIM_BDTR(n) STM32_TIM_REG(n, 0x44) -#define STM32_TIM_BDTR_MOE BIT(15) -#define STM32_TIM_DCR(n) STM32_TIM_REG(n, 0x48) -#define STM32_TIM_DMAR(n) STM32_TIM_REG(n, 0x4C) -#define STM32_TIM_OR(n) STM32_TIM_REG(n, 0x50) - -#define STM32_TIM_CCRx(n, x) STM32_TIM_REG(n, 0x34 + ((x) - 1) * 4) - -#define STM32_TIM32_CNT(n) STM32_TIM_REG32(n, 0x24) -#define STM32_TIM32_ARR(n) STM32_TIM_REG32(n, 0x2C) -#define STM32_TIM32_CCR1(n) STM32_TIM_REG32(n, 0x34) -#define STM32_TIM32_CCR2(n) STM32_TIM_REG32(n, 0x38) -#define STM32_TIM32_CCR3(n) STM32_TIM_REG32(n, 0x3C) -#define STM32_TIM32_CCR4(n) STM32_TIM_REG32(n, 0x40) +#define STM32_TIM_CCMR1_OC1M_TOGGLE STM32_TIM_CCMR1_OC1M(0x3) +#define STM32_TIM_CCMR1_OC1M_FORCE_INACTIVE STM32_TIM_CCMR1_OC1M(0x4) +#define STM32_TIM_CCMR1_OC1M_FORCE_ACTIVE STM32_TIM_CCMR1_OC1M(0x5) +#define STM32_TIM_CCMR1_OC1M_PWM_MODE_1 STM32_TIM_CCMR1_OC1M(0x6) +#define STM32_TIM_CCMR1_OC1M_PWM_MODE_2 STM32_TIM_CCMR1_OC1M(0x7) +#define STM32_TIM_CCMR2(n) STM32_TIM_REG(n, 0x1C) +#define STM32_TIM_CCER(n) STM32_TIM_REG(n, 0x20) +#define STM32_TIM_CCER_CC1E BIT(0) +#define STM32_TIM_CCER_CC1P BIT(1) +#define STM32_TIM_CCER_CC1NE BIT(2) +#define STM32_TIM_CCER_CC1NP BIT(3) +#define STM32_TIM_CNT(n) STM32_TIM_REG(n, 0x24) +#define STM32_TIM_PSC(n) STM32_TIM_REG(n, 0x28) +#define STM32_TIM_ARR(n) STM32_TIM_REG(n, 0x2C) +#define STM32_TIM_RCR(n) STM32_TIM_REG(n, 0x30) +#define STM32_TIM_CCR1(n) STM32_TIM_REG(n, 0x34) +#define STM32_TIM_CCR2(n) STM32_TIM_REG(n, 0x38) +#define STM32_TIM_CCR3(n) STM32_TIM_REG(n, 0x3C) +#define STM32_TIM_CCR4(n) STM32_TIM_REG(n, 0x40) +#define STM32_TIM_BDTR(n) STM32_TIM_REG(n, 0x44) +#define STM32_TIM_BDTR_MOE BIT(15) +#define STM32_TIM_DCR(n) STM32_TIM_REG(n, 0x48) +#define STM32_TIM_DMAR(n) STM32_TIM_REG(n, 0x4C) +#define STM32_TIM_OR(n) STM32_TIM_REG(n, 0x50) + +#define STM32_TIM_CCRx(n, x) STM32_TIM_REG(n, 0x34 + ((x)-1) * 4) + +#define STM32_TIM32_CNT(n) STM32_TIM_REG32(n, 0x24) +#define STM32_TIM32_ARR(n) STM32_TIM_REG32(n, 0x2C) +#define STM32_TIM32_CCR1(n) STM32_TIM_REG32(n, 0x34) +#define STM32_TIM32_CCR2(n) STM32_TIM_REG32(n, 0x38) +#define STM32_TIM32_CCR3(n) STM32_TIM_REG32(n, 0x3C) +#define STM32_TIM32_CCR4(n) STM32_TIM_REG32(n, 0x40) /* Timer registers as struct */ struct timer_ctlr { unsigned cr1; @@ -145,327 +142,325 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define IRQ_TIM(n) CONCAT2(STM32_IRQ_TIM, n) /* --- Low power timers --- */ -#define STM32_LPTIM_BASE(n) CONCAT3(STM32_LPTIM, n, _BASE) - -#define STM32_LPTIM_REG(n, offset) REG32(STM32_LPTIM_BASE(n) + (offset)) - -#define STM32_LPTIM_ISR(n) STM32_LPTIM_REG(n, 0x00) -#define STM32_LPTIM_ICR(n) STM32_LPTIM_REG(n, 0x04) -#define STM32_LPTIM_IER(n) STM32_LPTIM_REG(n, 0x08) -#define STM32_LPTIM_INT_DOWN BIT(6) -#define STM32_LPTIM_INT_UP BIT(5) -#define STM32_LPTIM_INT_ARROK BIT(4) -#define STM32_LPTIM_INT_CMPOK BIT(3) -#define STM32_LPTIM_INT_EXTTRIG BIT(2) -#define STM32_LPTIM_INT_ARRM BIT(1) -#define STM32_LPTIM_INT_CMPM BIT(0) -#define STM32_LPTIM_CFGR(n) STM32_LPTIM_REG(n, 0x0C) -#define STM32_LPTIM_CR(n) STM32_LPTIM_REG(n, 0x10) -#define STM32_LPTIM_CR_RSTARE BIT(4) -#define STM32_LPTIM_CR_COUNTRST BIT(3) -#define STM32_LPTIM_CR_CNTSTRT BIT(2) -#define STM32_LPTIM_CR_SNGSTRT BIT(1) -#define STM32_LPTIM_CR_ENABLE BIT(0) -#define STM32_LPTIM_CMP(n) STM32_LPTIM_REG(n, 0x14) -#define STM32_LPTIM_ARR(n) STM32_LPTIM_REG(n, 0x18) -#define STM32_LPTIM_CNT(n) STM32_LPTIM_REG(n, 0x1C) -#define STM32_LPTIM_CFGR2(n) STM32_LPTIM_REG(n, 0x24) +#define STM32_LPTIM_BASE(n) CONCAT3(STM32_LPTIM, n, _BASE) + +#define STM32_LPTIM_REG(n, offset) REG32(STM32_LPTIM_BASE(n) + (offset)) + +#define STM32_LPTIM_ISR(n) STM32_LPTIM_REG(n, 0x00) +#define STM32_LPTIM_ICR(n) STM32_LPTIM_REG(n, 0x04) +#define STM32_LPTIM_IER(n) STM32_LPTIM_REG(n, 0x08) +#define STM32_LPTIM_INT_DOWN BIT(6) +#define STM32_LPTIM_INT_UP BIT(5) +#define STM32_LPTIM_INT_ARROK BIT(4) +#define STM32_LPTIM_INT_CMPOK BIT(3) +#define STM32_LPTIM_INT_EXTTRIG BIT(2) +#define STM32_LPTIM_INT_ARRM BIT(1) +#define STM32_LPTIM_INT_CMPM BIT(0) +#define STM32_LPTIM_CFGR(n) STM32_LPTIM_REG(n, 0x0C) +#define STM32_LPTIM_CR(n) STM32_LPTIM_REG(n, 0x10) +#define STM32_LPTIM_CR_RSTARE BIT(4) +#define STM32_LPTIM_CR_COUNTRST BIT(3) +#define STM32_LPTIM_CR_CNTSTRT BIT(2) +#define STM32_LPTIM_CR_SNGSTRT BIT(1) +#define STM32_LPTIM_CR_ENABLE BIT(0) +#define STM32_LPTIM_CMP(n) STM32_LPTIM_REG(n, 0x14) +#define STM32_LPTIM_ARR(n) STM32_LPTIM_REG(n, 0x18) +#define STM32_LPTIM_CNT(n) STM32_LPTIM_REG(n, 0x1C) +#define STM32_LPTIM_CFGR2(n) STM32_LPTIM_REG(n, 0x24) /* --- GPIO --- */ -#define GPIO_A STM32_GPIOA_BASE -#define GPIO_B STM32_GPIOB_BASE -#define GPIO_C STM32_GPIOC_BASE -#define GPIO_D STM32_GPIOD_BASE -#define GPIO_E STM32_GPIOE_BASE -#define GPIO_F STM32_GPIOF_BASE -#define GPIO_G STM32_GPIOG_BASE -#define GPIO_H STM32_GPIOH_BASE -#define GPIO_I STM32_GPIOI_BASE -#define GPIO_J STM32_GPIOJ_BASE -#define GPIO_K STM32_GPIOK_BASE +#define GPIO_A STM32_GPIOA_BASE +#define GPIO_B STM32_GPIOB_BASE +#define GPIO_C STM32_GPIOC_BASE +#define GPIO_D STM32_GPIOD_BASE +#define GPIO_E STM32_GPIOE_BASE +#define GPIO_F STM32_GPIOF_BASE +#define GPIO_G STM32_GPIOG_BASE +#define GPIO_H STM32_GPIOH_BASE +#define GPIO_I STM32_GPIOI_BASE +#define GPIO_J STM32_GPIOJ_BASE +#define GPIO_K STM32_GPIOK_BASE #define UNIMPLEMENTED_GPIO_BANK GPIO_A - /* --- I2C --- */ -#define STM32_I2C1_PORT 0 -#define STM32_I2C2_PORT 1 -#define STM32_I2C3_PORT 2 -#define STM32_FMPI2C4_PORT 3 +#define STM32_I2C1_PORT 0 +#define STM32_I2C2_PORT 1 +#define STM32_I2C3_PORT 2 +#define STM32_FMPI2C4_PORT 3 #define stm32_i2c_reg(port, offset) \ - ((uint16_t *)((STM32_I2C1_BASE + ((port) * 0x400)) + (offset))) + ((uint16_t *)((STM32_I2C1_BASE + ((port)*0x400)) + (offset))) /* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CR REG32(STM32_PWR_BASE + 0x00) -#define STM32_PWR_CR_LPSDSR (1 << 0) -#define STM32_PWR_CR_FLPS (1 << 9) -#define STM32_PWR_CR_SVOS5 (1 << 14) -#define STM32_PWR_CR_SVOS4 (2 << 14) -#define STM32_PWR_CR_SVOS3 (3 << 14) -#define STM32_PWR_CR_SVOS_MASK (3 << 14) +#define STM32_PWR_CR REG32(STM32_PWR_BASE + 0x00) +#define STM32_PWR_CR_LPSDSR (1 << 0) +#define STM32_PWR_CR_FLPS (1 << 9) +#define STM32_PWR_CR_SVOS5 (1 << 14) +#define STM32_PWR_CR_SVOS4 (2 << 14) +#define STM32_PWR_CR_SVOS3 (3 << 14) +#define STM32_PWR_CR_SVOS_MASK (3 << 14) /* RTC domain control register */ -#define STM32_RCC_BDCR_BDRST BIT(16) -#define STM32_RCC_BDCR_RTCEN BIT(15) -#define STM32_RCC_BDCR_LSERDY BIT(1) -#define STM32_RCC_BDCR_LSEON BIT(0) -#define BDCR_RTCSEL_MASK ((0x3) << 8) -#define BDCR_RTCSEL(source) (((source) << 8) & BDCR_RTCSEL_MASK) -#define BDCR_SRC_LSE 0x1 -#define BDCR_SRC_LSI 0x2 -#define BDCR_SRC_HSE 0x3 +#define STM32_RCC_BDCR_BDRST BIT(16) +#define STM32_RCC_BDCR_RTCEN BIT(15) +#define STM32_RCC_BDCR_LSERDY BIT(1) +#define STM32_RCC_BDCR_LSEON BIT(0) +#define BDCR_RTCSEL_MASK ((0x3) << 8) +#define BDCR_RTCSEL(source) (((source) << 8) & BDCR_RTCSEL_MASK) +#define BDCR_SRC_LSE 0x1 +#define BDCR_SRC_LSI 0x2 +#define BDCR_SRC_HSE 0x3 /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB1_TIM2 BIT(0) -#define STM32_RCC_PB1_TIM3 BIT(1) -#define STM32_RCC_PB1_TIM4 BIT(2) -#define STM32_RCC_PB1_TIM5 BIT(3) -#define STM32_RCC_PB1_TIM6 BIT(4) -#define STM32_RCC_PB1_TIM7 BIT(5) -#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32H7 */ -#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32H7 */ -#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32H7 */ -#define STM32_RCC_PB1_RTC BIT(10) /* DBGMCU only */ -#define STM32_RCC_PB1_WWDG BIT(11) -#define STM32_RCC_PB1_IWDG BIT(12) /* DBGMCU only */ -#define STM32_RCC_PB1_SPI2 BIT(14) -#define STM32_RCC_PB1_SPI3 BIT(15) -#define STM32_RCC_PB1_USART2 BIT(17) -#define STM32_RCC_PB1_USART3 BIT(18) -#define STM32_RCC_PB1_USART4 BIT(19) -#define STM32_RCC_PB1_USART5 BIT(20) -#define STM32_RCC_PB1_PWREN BIT(28) -#define STM32_RCC_PB2_SPI1 BIT(12) +#define STM32_RCC_PB1_TIM2 BIT(0) +#define STM32_RCC_PB1_TIM3 BIT(1) +#define STM32_RCC_PB1_TIM4 BIT(2) +#define STM32_RCC_PB1_TIM5 BIT(3) +#define STM32_RCC_PB1_TIM6 BIT(4) +#define STM32_RCC_PB1_TIM7 BIT(5) +#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32H7 */ +#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32H7 */ +#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32H7 */ +#define STM32_RCC_PB1_RTC BIT(10) /* DBGMCU only */ +#define STM32_RCC_PB1_WWDG BIT(11) +#define STM32_RCC_PB1_IWDG BIT(12) /* DBGMCU only */ +#define STM32_RCC_PB1_SPI2 BIT(14) +#define STM32_RCC_PB1_SPI3 BIT(15) +#define STM32_RCC_PB1_USART2 BIT(17) +#define STM32_RCC_PB1_USART3 BIT(18) +#define STM32_RCC_PB1_USART4 BIT(19) +#define STM32_RCC_PB1_USART5 BIT(20) +#define STM32_RCC_PB1_PWREN BIT(28) +#define STM32_RCC_PB2_SPI1 BIT(12) /* Reset causes definitions */ /* --- Watchdogs --- */ -#define STM32_WWDG_CR REG32(STM32_WWDG_BASE + 0x00) -#define STM32_WWDG_CFR REG32(STM32_WWDG_BASE + 0x04) -#define STM32_WWDG_SR REG32(STM32_WWDG_BASE + 0x08) - -#define STM32_WWDG_TB_8 (3 << 7) -#define STM32_WWDG_EWI BIT(9) - -#define STM32_IWDG_KR REG32(STM32_IWDG_BASE + 0x00) -#define STM32_IWDG_KR_UNLOCK 0x5555 -#define STM32_IWDG_KR_RELOAD 0xaaaa -#define STM32_IWDG_KR_START 0xcccc -#define STM32_IWDG_PR REG32(STM32_IWDG_BASE + 0x04) -#define STM32_IWDG_RLR REG32(STM32_IWDG_BASE + 0x08) -#define STM32_IWDG_RLR_MAX 0x0fff -#define STM32_IWDG_SR REG32(STM32_IWDG_BASE + 0x0C) -#define STM32_IWDG_SR_WVU BIT(2) -#define STM32_IWDG_SR_RVU BIT(1) -#define STM32_IWDG_SR_PVU BIT(0) -#define STM32_IWDG_WINR REG32(STM32_IWDG_BASE + 0x10) +#define STM32_WWDG_CR REG32(STM32_WWDG_BASE + 0x00) +#define STM32_WWDG_CFR REG32(STM32_WWDG_BASE + 0x04) +#define STM32_WWDG_SR REG32(STM32_WWDG_BASE + 0x08) + +#define STM32_WWDG_TB_8 (3 << 7) +#define STM32_WWDG_EWI BIT(9) + +#define STM32_IWDG_KR REG32(STM32_IWDG_BASE + 0x00) +#define STM32_IWDG_KR_UNLOCK 0x5555 +#define STM32_IWDG_KR_RELOAD 0xaaaa +#define STM32_IWDG_KR_START 0xcccc +#define STM32_IWDG_PR REG32(STM32_IWDG_BASE + 0x04) +#define STM32_IWDG_RLR REG32(STM32_IWDG_BASE + 0x08) +#define STM32_IWDG_RLR_MAX 0x0fff +#define STM32_IWDG_SR REG32(STM32_IWDG_BASE + 0x0C) +#define STM32_IWDG_SR_WVU BIT(2) +#define STM32_IWDG_SR_RVU BIT(1) +#define STM32_IWDG_SR_PVU BIT(0) +#define STM32_IWDG_WINR REG32(STM32_IWDG_BASE + 0x10) /* --- Real-Time Clock --- */ /* --- Debug --- */ -#define STM32_DBGMCU_IDCODE REG32(STM32_DBGMCU_BASE + 0x00) -#define STM32_DBGMCU_CR REG32(STM32_DBGMCU_BASE + 0x04) +#define STM32_DBGMCU_IDCODE REG32(STM32_DBGMCU_BASE + 0x00) +#define STM32_DBGMCU_CR REG32(STM32_DBGMCU_BASE + 0x04) /* --- Routing interface --- */ /* STM32L1xx only */ -#define STM32_RI_ICR REG32(STM32_COMP_BASE + 0x04) -#define STM32_RI_ASCR1 REG32(STM32_COMP_BASE + 0x08) -#define STM32_RI_ASCR2 REG32(STM32_COMP_BASE + 0x0C) -#define STM32_RI_HYSCR1 REG32(STM32_COMP_BASE + 0x10) -#define STM32_RI_HYSCR2 REG32(STM32_COMP_BASE + 0x14) -#define STM32_RI_HYSCR3 REG32(STM32_COMP_BASE + 0x18) -#define STM32_RI_AMSR1 REG32(STM32_COMP_BASE + 0x1C) -#define STM32_RI_CMR1 REG32(STM32_COMP_BASE + 0x20) -#define STM32_RI_CICR1 REG32(STM32_COMP_BASE + 0x24) -#define STM32_RI_AMSR2 REG32(STM32_COMP_BASE + 0x28) -#define STM32_RI_CMR2 REG32(STM32_COMP_BASE + 0x30) -#define STM32_RI_CICR2 REG32(STM32_COMP_BASE + 0x34) -#define STM32_RI_AMSR3 REG32(STM32_COMP_BASE + 0x38) -#define STM32_RI_CMR3 REG32(STM32_COMP_BASE + 0x3C) -#define STM32_RI_CICR3 REG32(STM32_COMP_BASE + 0x40) -#define STM32_RI_AMSR4 REG32(STM32_COMP_BASE + 0x44) -#define STM32_RI_CMR4 REG32(STM32_COMP_BASE + 0x48) -#define STM32_RI_CICR4 REG32(STM32_COMP_BASE + 0x4C) -#define STM32_RI_AMSR5 REG32(STM32_COMP_BASE + 0x50) -#define STM32_RI_CMR5 REG32(STM32_COMP_BASE + 0x54) -#define STM32_RI_CICR5 REG32(STM32_COMP_BASE + 0x58) +#define STM32_RI_ICR REG32(STM32_COMP_BASE + 0x04) +#define STM32_RI_ASCR1 REG32(STM32_COMP_BASE + 0x08) +#define STM32_RI_ASCR2 REG32(STM32_COMP_BASE + 0x0C) +#define STM32_RI_HYSCR1 REG32(STM32_COMP_BASE + 0x10) +#define STM32_RI_HYSCR2 REG32(STM32_COMP_BASE + 0x14) +#define STM32_RI_HYSCR3 REG32(STM32_COMP_BASE + 0x18) +#define STM32_RI_AMSR1 REG32(STM32_COMP_BASE + 0x1C) +#define STM32_RI_CMR1 REG32(STM32_COMP_BASE + 0x20) +#define STM32_RI_CICR1 REG32(STM32_COMP_BASE + 0x24) +#define STM32_RI_AMSR2 REG32(STM32_COMP_BASE + 0x28) +#define STM32_RI_CMR2 REG32(STM32_COMP_BASE + 0x30) +#define STM32_RI_CICR2 REG32(STM32_COMP_BASE + 0x34) +#define STM32_RI_AMSR3 REG32(STM32_COMP_BASE + 0x38) +#define STM32_RI_CMR3 REG32(STM32_COMP_BASE + 0x3C) +#define STM32_RI_CICR3 REG32(STM32_COMP_BASE + 0x40) +#define STM32_RI_AMSR4 REG32(STM32_COMP_BASE + 0x44) +#define STM32_RI_CMR4 REG32(STM32_COMP_BASE + 0x48) +#define STM32_RI_CICR4 REG32(STM32_COMP_BASE + 0x4C) +#define STM32_RI_AMSR5 REG32(STM32_COMP_BASE + 0x50) +#define STM32_RI_CMR5 REG32(STM32_COMP_BASE + 0x54) +#define STM32_RI_CICR5 REG32(STM32_COMP_BASE + 0x58) /* --- DAC --- */ -#define STM32_DAC_CR REG32(STM32_DAC_BASE + 0x00) -#define STM32_DAC_SWTRIGR REG32(STM32_DAC_BASE + 0x04) -#define STM32_DAC_DHR12R1 REG32(STM32_DAC_BASE + 0x08) -#define STM32_DAC_DHR12L1 REG32(STM32_DAC_BASE + 0x0C) -#define STM32_DAC_DHR8R1 REG32(STM32_DAC_BASE + 0x10) -#define STM32_DAC_DHR12R2 REG32(STM32_DAC_BASE + 0x14) -#define STM32_DAC_DHR12L2 REG32(STM32_DAC_BASE + 0x18) -#define STM32_DAC_DHR8R2 REG32(STM32_DAC_BASE + 0x1C) -#define STM32_DAC_DHR12RD REG32(STM32_DAC_BASE + 0x20) -#define STM32_DAC_DHR12LD REG32(STM32_DAC_BASE + 0x24) -#define STM32_DAC_DHR8RD REG32(STM32_DAC_BASE + 0x28) -#define STM32_DAC_DOR1 REG32(STM32_DAC_BASE + 0x2C) -#define STM32_DAC_DOR2 REG32(STM32_DAC_BASE + 0x30) -#define STM32_DAC_SR REG32(STM32_DAC_BASE + 0x34) - -#define STM32_DAC_CR_DMAEN2 BIT(28) -#define STM32_DAC_CR_TSEL2_SWTRG (7 << 19) -#define STM32_DAC_CR_TSEL2_TMR4 (5 << 19) -#define STM32_DAC_CR_TSEL2_TMR2 (4 << 19) -#define STM32_DAC_CR_TSEL2_TMR9 (3 << 19) -#define STM32_DAC_CR_TSEL2_TMR7 (2 << 19) -#define STM32_DAC_CR_TSEL2_TMR6 (0 << 19) -#define STM32_DAC_CR_TSEL2_MASK (7 << 19) -#define STM32_DAC_CR_TEN2 BIT(18) -#define STM32_DAC_CR_BOFF2 BIT(17) -#define STM32_DAC_CR_EN2 BIT(16) -#define STM32_DAC_CR_DMAEN1 BIT(12) -#define STM32_DAC_CR_TSEL1_SWTRG (7 << 3) -#define STM32_DAC_CR_TSEL1_TMR4 (5 << 3) -#define STM32_DAC_CR_TSEL1_TMR2 (4 << 3) -#define STM32_DAC_CR_TSEL1_TMR9 (3 << 3) -#define STM32_DAC_CR_TSEL1_TMR7 (2 << 3) -#define STM32_DAC_CR_TSEL1_TMR6 (0 << 3) -#define STM32_DAC_CR_TSEL1_MASK (7 << 3) -#define STM32_DAC_CR_TEN1 BIT(2) -#define STM32_DAC_CR_BOFF1 BIT(1) -#define STM32_DAC_CR_EN1 BIT(0) +#define STM32_DAC_CR REG32(STM32_DAC_BASE + 0x00) +#define STM32_DAC_SWTRIGR REG32(STM32_DAC_BASE + 0x04) +#define STM32_DAC_DHR12R1 REG32(STM32_DAC_BASE + 0x08) +#define STM32_DAC_DHR12L1 REG32(STM32_DAC_BASE + 0x0C) +#define STM32_DAC_DHR8R1 REG32(STM32_DAC_BASE + 0x10) +#define STM32_DAC_DHR12R2 REG32(STM32_DAC_BASE + 0x14) +#define STM32_DAC_DHR12L2 REG32(STM32_DAC_BASE + 0x18) +#define STM32_DAC_DHR8R2 REG32(STM32_DAC_BASE + 0x1C) +#define STM32_DAC_DHR12RD REG32(STM32_DAC_BASE + 0x20) +#define STM32_DAC_DHR12LD REG32(STM32_DAC_BASE + 0x24) +#define STM32_DAC_DHR8RD REG32(STM32_DAC_BASE + 0x28) +#define STM32_DAC_DOR1 REG32(STM32_DAC_BASE + 0x2C) +#define STM32_DAC_DOR2 REG32(STM32_DAC_BASE + 0x30) +#define STM32_DAC_SR REG32(STM32_DAC_BASE + 0x34) + +#define STM32_DAC_CR_DMAEN2 BIT(28) +#define STM32_DAC_CR_TSEL2_SWTRG (7 << 19) +#define STM32_DAC_CR_TSEL2_TMR4 (5 << 19) +#define STM32_DAC_CR_TSEL2_TMR2 (4 << 19) +#define STM32_DAC_CR_TSEL2_TMR9 (3 << 19) +#define STM32_DAC_CR_TSEL2_TMR7 (2 << 19) +#define STM32_DAC_CR_TSEL2_TMR6 (0 << 19) +#define STM32_DAC_CR_TSEL2_MASK (7 << 19) +#define STM32_DAC_CR_TEN2 BIT(18) +#define STM32_DAC_CR_BOFF2 BIT(17) +#define STM32_DAC_CR_EN2 BIT(16) +#define STM32_DAC_CR_DMAEN1 BIT(12) +#define STM32_DAC_CR_TSEL1_SWTRG (7 << 3) +#define STM32_DAC_CR_TSEL1_TMR4 (5 << 3) +#define STM32_DAC_CR_TSEL1_TMR2 (4 << 3) +#define STM32_DAC_CR_TSEL1_TMR9 (3 << 3) +#define STM32_DAC_CR_TSEL1_TMR7 (2 << 3) +#define STM32_DAC_CR_TSEL1_TMR6 (0 << 3) +#define STM32_DAC_CR_TSEL1_MASK (7 << 3) +#define STM32_DAC_CR_TEN1 BIT(2) +#define STM32_DAC_CR_BOFF1 BIT(1) +#define STM32_DAC_CR_EN1 BIT(0) /* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) +#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) + +#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) +#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) +#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) +#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) + +#define STM32_CRC_CR_RESET BIT(0) +#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) +#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) +#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) +#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) +#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) +#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) +#define STM32_CRC_CR_REV_IN_WORD (3 << 5) +#define STM32_CRC_CR_REV_OUT BIT(7) /* --- PMSE --- */ -#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) -#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) -#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) -#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) -#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) -#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) -#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) -#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x) * 4) -#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) -#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) -#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) -#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) -#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) -#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) -#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) -#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) -#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) -#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) -#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) +#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) +#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) +#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) +#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) +#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) +#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) +#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) +#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x)*4) +#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) +#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) +#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) +#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) +#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) +#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) +#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) +#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) +#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) +#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) +#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) /* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) +#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n)*4) + +#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) + +#define STM32_USB_CNTR_FRES BIT(0) +#define STM32_USB_CNTR_PDWN BIT(1) +#define STM32_USB_CNTR_LP_MODE BIT(2) +#define STM32_USB_CNTR_FSUSP BIT(3) +#define STM32_USB_CNTR_RESUME BIT(4) +#define STM32_USB_CNTR_L1RESUME BIT(5) +#define STM32_USB_CNTR_L1REQM BIT(7) +#define STM32_USB_CNTR_ESOFM BIT(8) +#define STM32_USB_CNTR_SOFM BIT(9) +#define STM32_USB_CNTR_RESETM BIT(10) +#define STM32_USB_CNTR_SUSPM BIT(11) +#define STM32_USB_CNTR_WKUPM BIT(12) +#define STM32_USB_CNTR_ERRM BIT(13) +#define STM32_USB_CNTR_PMAOVRM BIT(14) +#define STM32_USB_CNTR_CTRM BIT(15) + +#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) + +#define STM32_USB_ISTR_EP_ID_MASK (0x000f) +#define STM32_USB_ISTR_DIR BIT(4) +#define STM32_USB_ISTR_L1REQ BIT(7) +#define STM32_USB_ISTR_ESOF BIT(8) +#define STM32_USB_ISTR_SOF BIT(9) +#define STM32_USB_ISTR_RESET BIT(10) +#define STM32_USB_ISTR_SUSP BIT(11) +#define STM32_USB_ISTR_WKUP BIT(12) +#define STM32_USB_ISTR_ERR BIT(13) +#define STM32_USB_ISTR_PMAOVR BIT(14) +#define STM32_USB_ISTR_CTR BIT(15) + +#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) #define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 +#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) + +#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) +#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) +#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) +#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) + +#define STM32_USB_BCDR_BCDEN BIT(0) +#define STM32_USB_BCDR_DCDEN BIT(1) +#define STM32_USB_BCDR_PDEN BIT(2) +#define STM32_USB_BCDR_SDEN BIT(3) +#define STM32_USB_BCDR_DCDET BIT(4) +#define STM32_USB_BCDR_PDET BIT(5) +#define STM32_USB_BCDR_SDET BIT(6) +#define STM32_USB_BCDR_PS2DET BIT(7) + +#define EP_MASK 0x0F0F +#define EP_TX_DTOG 0x0040 +#define EP_TX_MASK 0x0030 #define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 +#define EP_TX_NAK 0x0020 #define EP_TX_STALL 0x0010 #define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 +#define EP_RX_DTOG 0x4000 +#define EP_RX_MASK 0x3000 #define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 +#define EP_RX_NAK 0x2000 #define EP_RX_STALL 0x1000 #define EP_RX_DISAB 0x0000 #define EP_STATUS_OUT 0x0100 -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) +#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) #define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) -#define EP_TX_RX_NAK (EP_TX_NAK | EP_RX_NAK) +#define EP_TX_RX_NAK (EP_TX_NAK | EP_RX_NAK) #define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) + STM32_USB_EP(n) = \ + (((STM32_USB_EP(n) & (EP_MASK | (mask))) ^ (val)) | (flags)) /* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) +#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) +#define STM32_RNG_CR_RNGEN BIT(2) +#define STM32_RNG_CR_IE BIT(3) +#define STM32_RNG_CR_CED BIT(5) +#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) +#define STM32_RNG_SR_DRDY BIT(0) +#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) /* --- AXI interconnect --- */ /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) +#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x)) +#define WRITE_ISS_OVERRIDE BIT(1) +#define READ_ISS_OVERRIDE BIT(0) /* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) +#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) +#define STM32_UNIQUE_ID_LENGTH (3 * 4) #endif /* !__ASSEMBLER__ */ diff --git a/chip/stm32/spi.c b/chip/stm32/spi.c index 268b7880e6..e6be946113 100644 --- a/chip/stm32/spi.c +++ b/chip/stm32/spi.c @@ -1,5 +1,5 @@ /* - * Copyright 2013 The Chromium OS Authors. All rights reserved. + * Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -8,6 +8,7 @@ * This uses DMA to handle transmission and reception. */ +#include "builtin/assert.h" #include "chipset.h" #include "clock.h" #include "console.h" @@ -24,8 +25,8 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_SPI, outstr) -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SPI, format, ##args) /* SPI FIFO registers */ #ifdef CHIP_FAMILY_STM32H7 @@ -41,7 +42,7 @@ static const struct dma_option dma_tx_option = { STM32_DMAC_SPI1_TX, (void *)&SPI_TXDR, STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT #ifdef CHIP_FAMILY_STM32F4 - | STM32_DMA_CCR_CHANNEL(STM32_SPI1_TX_REQ_CH) + | STM32_DMA_CCR_CHANNEL(STM32_SPI1_TX_REQ_CH) #endif }; @@ -49,7 +50,7 @@ static const struct dma_option dma_rx_option = { STM32_DMAC_SPI1_RX, (void *)&SPI_RXDR, STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT #ifdef CHIP_FAMILY_STM32F4 - | STM32_DMA_CCR_CHANNEL(STM32_SPI1_RX_REQ_CH) + | STM32_DMA_CCR_CHANNEL(STM32_SPI1_RX_REQ_CH) #endif }; @@ -71,8 +72,8 @@ static const struct dma_option dma_rx_option = { * the AP will have a known and identifiable value. */ #define SPI_PROTO2_OFFSET (EC_PROTO2_RESPONSE_HEADER_BYTES + 2) -#define SPI_PROTO2_OVERHEAD (SPI_PROTO2_OFFSET + \ - EC_PROTO2_RESPONSE_TRAILER_BYTES + 1) +#define SPI_PROTO2_OVERHEAD \ + (SPI_PROTO2_OFFSET + EC_PROTO2_RESPONSE_TRAILER_BYTES + 1) #endif /* defined(CONFIG_SPI_PROTOCOL_V2) */ /* * Max data size for a version 3 request/response packet. This is big enough @@ -92,10 +93,8 @@ static const struct dma_option dma_rx_option = { * 32-bit aligned. */ static const uint8_t out_preamble[4] = { - EC_SPI_PROCESSING, - EC_SPI_PROCESSING, - EC_SPI_PROCESSING, - EC_SPI_FRAME_START, /* This is the byte which matters */ + EC_SPI_PROCESSING, EC_SPI_PROCESSING, EC_SPI_PROCESSING, + EC_SPI_FRAME_START, /* This is the byte which matters */ }; /* @@ -117,7 +116,7 @@ static const uint8_t out_preamble[4] = { * message, including protocol overhead, and must be 32-bit aligned. */ static uint8_t out_msg[SPI_MAX_RESPONSE_SIZE + sizeof(out_preamble) + - EC_SPI_PAST_END_LENGTH] __aligned(4) __uncached; + EC_SPI_PAST_END_LENGTH] __aligned(4) __uncached; static uint8_t in_msg[SPI_MAX_REQUEST_SIZE] __aligned(4) __uncached; static uint8_t enabled; #ifdef CONFIG_SPI_PROTOCOL_V2 @@ -172,8 +171,7 @@ enum spi_state { * @param nss GPIO signal for NSS control line * @return 0 if bytes received, -1 if we hit a timeout or NSS went high */ -static int wait_for_bytes(dma_chan_t *rxdma, int needed, - enum gpio_signal nss) +static int wait_for_bytes(dma_chan_t *rxdma, int needed, enum gpio_signal nss) { timestamp_t deadline; @@ -230,8 +228,8 @@ static int wait_for_bytes(dma_chan_t *rxdma, int needed, * SPI_PROTO2_OFFSET bytes into out_msg * @param msg_len Number of message bytes to send */ -static void reply(dma_chan_t *txdma, - enum ec_status status, char *msg_ptr, int msg_len) +static void reply(dma_chan_t *txdma, enum ec_status status, char *msg_ptr, + int msg_len) { char *msg = out_msg; int need_copy = msg_ptr != msg + SPI_PROTO2_OFFSET; @@ -438,8 +436,10 @@ static void spi_send_response_packet(struct host_packet *pkt) /* Transmit the reply */ txdma = dma_get_channel(STM32_DMAC_SPI1_TX); - dma_prepare_tx(&dma_tx_option, sizeof(out_preamble) + pkt->response_size - + EC_SPI_PAST_END_LENGTH, out_msg); + dma_prepare_tx(&dma_tx_option, + sizeof(out_preamble) + pkt->response_size + + EC_SPI_PAST_END_LENGTH, + out_msg); dma_go(txdma); #ifdef CHIP_FAMILY_STM32H7 /* clear any previous underrun */ @@ -544,8 +544,9 @@ void spi_event(enum gpio_signal signal) memcpy(out_msg, out_preamble, sizeof(out_preamble)); spi_packet.response = out_msg + sizeof(out_preamble); /* Reserve space for the preamble and trailing past-end byte */ - spi_packet.response_max = sizeof(out_msg) - - sizeof(out_preamble) - EC_SPI_PAST_END_LENGTH; + spi_packet.response_max = sizeof(out_msg) - + sizeof(out_preamble) - + EC_SPI_PAST_END_LENGTH; spi_packet.response_size = 0; spi_packet.driver_result = EC_RES_SUCCESS; @@ -608,7 +609,7 @@ void spi_event(enum gpio_signal signal) #endif /* defined(CONFIG_SPI_PROTOCOL_V2) */ } - spi_event_error: +spi_event_error: /* Error, timeout, or protocol we can't handle. Ignore data. */ tx_status(EC_SPI_RX_BAD_DATA); state = SPI_STATE_RX_BAD; @@ -701,14 +702,13 @@ static void spi_init(void) #ifdef CHIP_FAMILY_STM32H7 spi->cfg2 = 0; spi->cfg1 = STM32_SPI_CFG1_DATASIZE(8) | STM32_SPI_CFG1_FTHLV(4) | - STM32_SPI_CFG1_CRCSIZE(8) | - STM32_SPI_CFG1_TXDMAEN | STM32_SPI_CFG1_RXDMAEN | - STM32_SPI_CFG1_UDRCFG_CONST | - STM32_SPI_CFG1_UDRDET_BEGIN_FRM; + STM32_SPI_CFG1_CRCSIZE(8) | STM32_SPI_CFG1_TXDMAEN | + STM32_SPI_CFG1_RXDMAEN | STM32_SPI_CFG1_UDRCFG_CONST | + STM32_SPI_CFG1_UDRDET_BEGIN_FRM; spi->cr1 = 0; #else /* !CHIP_FAMILY_STM32H7 */ spi->cr2 = STM32_SPI_CR2_RXDMAEN | STM32_SPI_CR2_TXDMAEN | - STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8); + STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8); /* Enable the SPI peripheral */ spi->cr1 |= STM32_SPI_CR1_SPE; diff --git a/chip/stm32/spi_controller-stm32h7.c b/chip/stm32/spi_controller-stm32h7.c index 7792204a85..705bf4e607 100644 --- a/chip/stm32/spi_controller-stm32h7.c +++ b/chip/stm32/spi_controller-stm32h7.c @@ -1,5 +1,5 @@ /* - * Copyright 2017 The Chromium OS Authors. All rights reserved. + * Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -50,44 +50,28 @@ static struct mutex spi_mutex[ARRAY_SIZE(SPI_REGS)]; static const struct dma_option dma_tx_option[] = { #ifdef CONFIG_STM32_SPI1_CONTROLLER - { - STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->txdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, + { STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->txdr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT }, #endif - { - STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->txdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, - { - STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->txdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, - { - STM32_DMAC_SPI4_TX, (void *)&STM32_SPI4_REGS->txdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, + { STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->txdr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT }, + { STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->txdr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT }, + { STM32_DMAC_SPI4_TX, (void *)&STM32_SPI4_REGS->txdr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT }, }; static const struct dma_option dma_rx_option[] = { #ifdef CONFIG_STM32_SPI1_CONTROLLER - { - STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->rxdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, + { STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->rxdr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT }, #endif - { - STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->rxdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, - { - STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->rxdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, - { - STM32_DMAC_SPI4_RX, (void *)&STM32_SPI4_REGS->rxdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, + { STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->rxdr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT }, + { STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->rxdr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT }, + { STM32_DMAC_SPI4_RX, (void *)&STM32_SPI4_REGS->rxdr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT }, }; static uint8_t spi_enabled[ARRAY_SIZE(SPI_REGS)]; @@ -252,8 +236,8 @@ static int spi_dma_wait(int port) } int spi_transaction_async(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) + const uint8_t *txdata, int txlen, uint8_t *rxdata, + int rxlen) { int rv = EC_SUCCESS; int port = spi_device->port; @@ -314,8 +298,8 @@ int spi_transaction_wait(const struct spi_device_t *spi_device) } int spi_transaction(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) + const uint8_t *txdata, int txlen, uint8_t *rxdata, + int rxlen) { int rv; int port = spi_device->port; diff --git a/chip/stm32/spi_controller.c b/chip/stm32/spi_controller.c index e34afde7e1..70e0eb3cd7 100644 --- a/chip/stm32/spi_controller.c +++ b/chip/stm32/spi_controller.c @@ -1,5 +1,5 @@ /* - * Copyright 2014 The Chromium OS Authors. All rights reserved. + * Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -17,12 +17,11 @@ #include "timer.h" #include "util.h" -#if defined(CHIP_VARIANT_STM32F373) || \ - defined(CHIP_FAMILY_STM32L4) || \ - defined(CHIP_VARIANT_STM32F76X) +#if defined(CHIP_VARIANT_STM32F373) || defined(CHIP_FAMILY_STM32L4) || \ + defined(CHIP_FAMILY_STM32L5) || defined(CHIP_VARIANT_STM32F76X) #define HAS_SPI3 #else -#undef HAS_SPI3 +#undef HAS_SPI3 #endif /* The second (and third if available) SPI port are used as controller */ @@ -36,14 +35,26 @@ static stm32_spi_regs_t *SPI_REGS[] = { #endif }; -#ifdef CHIP_FAMILY_STM32L4 /* DMA request mapping on channels */ -static uint8_t dma_req[ARRAY_SIZE(SPI_REGS)] = { +struct dma_req_t { + uint8_t tx_req; + uint8_t rx_req; +}; +#ifdef CHIP_FAMILY_STM32L4 +static struct dma_req_t dma_req[ARRAY_SIZE(SPI_REGS)] = { #ifdef CONFIG_STM32_SPI1_CONTROLLER - /* SPI1 */ 1, + /* SPI1 */ { 1, 1 }, #endif - /* SPI2 */ 1, - /* SPI3 */ 3, + /* SPI2 */ { 1, 1 }, + /* SPI3 */ { 3, 3 }, +}; +#elif defined(CHIP_FAMILY_STM32L5) +static struct dma_req_t dma_req[ARRAY_SIZE(SPI_REGS)] = { +#ifdef CONFIG_STM32_SPI1_CONTROLLER + /* SPI1 */ { DMAMUX_REQ_SPI1_TX, DMAMUX_REQ_SPI1_RX }, +#endif + /* SPI2 */ { DMAMUX_REQ_SPI2_TX, DMAMUX_REQ_SPI2_RX }, + /* SPI3 */ { DMAMUX_REQ_SPI3_TX, DMAMUX_REQ_SPI3_RX }, }; #endif @@ -53,52 +64,40 @@ static struct mutex spi_mutex[ARRAY_SIZE(SPI_REGS)]; /* Default DMA channel options */ #ifdef CHIP_FAMILY_STM32F4 -#define F4_CHANNEL(ch) STM32_DMA_CCR_CHANNEL(ch) +#define F4_CHANNEL(ch) STM32_DMA_CCR_CHANNEL(ch) #else -#define F4_CHANNEL(ch) 0 +#define F4_CHANNEL(ch) 0 #endif static const struct dma_option dma_tx_option[] = { #ifdef CONFIG_STM32_SPI1_CONTROLLER - { - STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - | F4_CHANNEL(STM32_SPI1_TX_REQ_CH) - }, + { STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->dr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + F4_CHANNEL(STM32_SPI1_TX_REQ_CH) }, #endif - { - STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - | F4_CHANNEL(STM32_SPI2_TX_REQ_CH) - }, + { STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->dr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + F4_CHANNEL(STM32_SPI2_TX_REQ_CH) }, #ifdef HAS_SPI3 - { - STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - | F4_CHANNEL(STM32_SPI3_TX_REQ_CH) - }, + { STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->dr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + F4_CHANNEL(STM32_SPI3_TX_REQ_CH) }, #endif }; static const struct dma_option dma_rx_option[] = { #ifdef CONFIG_STM32_SPI1_CONTROLLER - { - STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - | F4_CHANNEL(STM32_SPI1_RX_REQ_CH) - }, + { STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->dr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + F4_CHANNEL(STM32_SPI1_RX_REQ_CH) }, #endif - { - STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - | F4_CHANNEL(STM32_SPI2_RX_REQ_CH) - }, + { STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->dr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + F4_CHANNEL(STM32_SPI2_RX_REQ_CH) }, #ifdef HAS_SPI3 - { - STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - | F4_CHANNEL(STM32_SPI3_RX_REQ_CH) - }, + { STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->dr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + F4_CHANNEL(STM32_SPI3_RX_REQ_CH) }, #endif }; @@ -121,7 +120,7 @@ static int spi_clear_rx_fifo(stm32_spi_regs_t *spi) uint32_t start = __hw_clock_source_read(), delta; while (!spi_rx_done(spi)) { - unused = spi->dr; /* Read one byte from FIFO */ + unused = spi->dr; /* Read one byte from FIFO */ delta = __hw_clock_source_read() - start; if (delta >= SPI_TRANSACTION_TIMEOUT_USEC) return EC_ERROR_TIMEOUT; @@ -203,9 +202,9 @@ static int spi_controller_initialize(const struct spi_device_t *spi_device) spi->cr1 = STM32_SPI_CR1_MSTR | STM32_SPI_CR1_SSM | STM32_SPI_CR1_SSI | (spi_device->div << 3); -#ifdef CHIP_FAMILY_STM32L4 - dma_select_channel(dma_tx_option[port].channel, dma_req[port]); - dma_select_channel(dma_rx_option[port].channel, dma_req[port]); +#if defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5) + dma_select_channel(dma_tx_option[port].channel, dma_req[port].tx_req); + dma_select_channel(dma_rx_option[port].channel, dma_req[port].rx_req); #endif /* * Configure 8-bit datasize, set FRXTH, enable DMA, @@ -219,7 +218,7 @@ static int spi_controller_initialize(const struct spi_device_t *spi_device) * https://www.st.com/resource/en/reference_manual/dm00031936.pdf#page=803 */ spi->cr2 = STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_RXDMAEN | - STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8); + STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8); #ifdef CONFIG_SPI_HALFDUPLEX spi->cr1 |= STM32_SPI_CR1_BIDIMODE | STM32_SPI_CR1_BIDIOE; @@ -274,8 +273,8 @@ int spi_enable(const struct spi_device_t *spi_device, int enable) return spi_controller_shutdown(spi_device); } -static int spi_dma_start(int port, const uint8_t *txdata, - uint8_t *rxdata, int len) +static int spi_dma_start(int port, const uint8_t *txdata, uint8_t *rxdata, + int len) { dma_chan_t *txdma; @@ -337,8 +336,8 @@ static int spi_dma_wait(int port) static uint8_t spi_chip_select_already_asserted[ARRAY_SIZE(SPI_REGS)]; int spi_transaction_async(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) + const uint8_t *txdata, int txlen, uint8_t *rxdata, + int rxlen) { int rv = EC_SUCCESS; int port = spi_device->port; @@ -372,13 +371,14 @@ int spi_transaction_async(const struct spi_device_t *spi_device, spi_clear_rx_fifo(spi); - rv = spi_dma_start(port, txdata, buf, txlen); - if (rv != EC_SUCCESS) - goto err_free; - + if (txlen) { + rv = spi_dma_start(port, txdata, buf, txlen); + if (rv != EC_SUCCESS) + goto err_free; #ifdef CONFIG_SPI_HALFDUPLEX - spi->cr1 |= STM32_SPI_CR1_BIDIOE; + spi->cr1 |= STM32_SPI_CR1_BIDIOE; #endif + } if (full_readback) return EC_SUCCESS; @@ -410,8 +410,8 @@ int spi_transaction_flush(const struct spi_device_t *spi_device) { int rv = spi_dma_wait(spi_device->port); - if (!IS_ENABLED(CONFIG_USB_SPI) - || !spi_chip_select_already_asserted[spi_device->port]) { + if (!IS_ENABLED(CONFIG_USB_SPI) || + !spi_chip_select_already_asserted[spi_device->port]) { /* Drive SS high */ gpio_set_level(spi_device->gpio_cs, 1); } @@ -425,8 +425,8 @@ int spi_transaction_wait(const struct spi_device_t *spi_device) } int spi_transaction(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) + const uint8_t *txdata, int txlen, uint8_t *rxdata, + int rxlen) { int rv; int port = spi_device->port; diff --git a/chip/stm32/stm32-dma.h b/chip/stm32/stm32-dma.h index 06233b9c93..3bda9ec41d 100644 --- a/chip/stm32/stm32-dma.h +++ b/chip/stm32/stm32-dma.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/stm32/system.c b/chip/stm32/system.c index d7388055a9..dc53022c8b 100644 --- a/chip/stm32/system.c +++ b/chip/stm32/system.c @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -28,10 +28,10 @@ #define BDCR_SRC BDCR_SRC_LSI #define BDCR_RDY 0 #endif -#define BDCR_ENABLE_VALUE (STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC) | \ - BDCR_RDY) -#define BDCR_ENABLE_MASK (BDCR_ENABLE_VALUE | BDCR_RTCSEL_MASK | \ - STM32_RCC_BDCR_BDRST) +#define BDCR_ENABLE_VALUE \ + (STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC) | BDCR_RDY) +#define BDCR_ENABLE_MASK \ + (BDCR_ENABLE_VALUE | BDCR_RTCSEL_MASK | STM32_RCC_BDCR_BDRST) #ifdef CONFIG_USB_PD_DUAL_ROLE BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT <= 3); @@ -149,62 +149,61 @@ void chip_pre_init(void) uint32_t apb2fz_reg = 0; #if defined(CHIP_FAMILY_STM32F0) - apb1fz_reg = - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM6 | - STM32_RCC_PB1_TIM7 | STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; + apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | + STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | + STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; apb2fz_reg = STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 | - STM32_RCC_PB2_TIM17 | STM32_RCC_PB2_TIM1; + STM32_RCC_PB2_TIM17 | STM32_RCC_PB2_TIM1; /* enable clock to debug module before writing */ STM32_RCC_APB2ENR |= STM32_RCC_DBGMCUEN; #elif defined(CHIP_FAMILY_STM32F3) - apb1fz_reg = - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | - STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | - STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; - apb2fz_reg = - STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 | STM32_RCC_PB2_TIM17; + apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | + STM32_RCC_PB1_TIM4 | STM32_RCC_PB1_TIM5 | + STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | + STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; + apb2fz_reg = STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 | + STM32_RCC_PB2_TIM17; #elif defined(CHIP_FAMILY_STM32F4) - apb1fz_reg = - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | - STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | - STM32_RCC_PB1_TIM12 | STM32_RCC_PB1_TIM13 | STM32_RCC_PB1_TIM14| - STM32_RCC_PB1_RTC | STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; - apb2fz_reg = - STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM8 | STM32_RCC_PB2_TIM9 | - STM32_RCC_PB2_TIM10 | STM32_RCC_PB2_TIM11; + apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | + STM32_RCC_PB1_TIM4 | STM32_RCC_PB1_TIM5 | + STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | + STM32_RCC_PB1_TIM12 | STM32_RCC_PB1_TIM13 | + STM32_RCC_PB1_TIM14 | STM32_RCC_PB1_RTC | + STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; + apb2fz_reg = STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM8 | + STM32_RCC_PB2_TIM9 | STM32_RCC_PB2_TIM10 | + STM32_RCC_PB2_TIM11; #elif defined(CHIP_FAMILY_STM32L4) -#ifdef CHIP_VARIANT_STM32L431X - apb1fz_reg = - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM7 | STM32_RCC_PB1_TIM6 | - STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; - apb2fz_reg = - STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16; +#ifdef CHIP_VARIANT_STM32L431X + apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM7 | + STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_WWDG | + STM32_RCC_PB1_IWDG; + apb2fz_reg = STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM15 | + STM32_RCC_PB2_TIM16; #else - apb1fz_reg = - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | - STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | - STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; + apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | + STM32_RCC_PB1_TIM4 | STM32_RCC_PB1_TIM5 | + STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | + STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; apb2fz_reg = STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM8; #endif #elif defined(CHIP_FAMILY_STM32L) - apb1fz_reg = - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | - STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; + apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | + STM32_RCC_PB1_TIM4 | STM32_RCC_PB1_WWDG | + STM32_RCC_PB1_IWDG; apb2fz_reg = STM32_RCC_PB2_TIM9 | STM32_RCC_PB2_TIM10 | - STM32_RCC_PB2_TIM11; + STM32_RCC_PB2_TIM11; #elif defined(CHIP_FAMILY_STM32G4) - apb1fz_reg = - STM32_DBGMCU_APB1FZ_TIM2 | STM32_DBGMCU_APB1FZ_TIM3 | - STM32_DBGMCU_APB1FZ_TIM4 | STM32_DBGMCU_APB1FZ_TIM5 | - STM32_DBGMCU_APB1FZ_TIM6 | STM32_DBGMCU_APB1FZ_TIM7 | - STM32_DBGMCU_APB1FZ_RTC | STM32_DBGMCU_APB1FZ_WWDG | - STM32_DBGMCU_APB1FZ_IWDG; - apb2fz_reg = - STM32_DBGMCU_APB2FZ_TIM1 | STM32_DBGMCU_APB2FZ_TIM8 | - STM32_DBGMCU_APB2FZ_TIM15 | STM32_DBGMCU_APB2FZ_TIM16 | - STM32_DBGMCU_APB2FZ_TIM17 | STM32_DBGMCU_APB2FZ_TIM20; + apb1fz_reg = STM32_DBGMCU_APB1FZ_TIM2 | STM32_DBGMCU_APB1FZ_TIM3 | + STM32_DBGMCU_APB1FZ_TIM4 | STM32_DBGMCU_APB1FZ_TIM5 | + STM32_DBGMCU_APB1FZ_TIM6 | STM32_DBGMCU_APB1FZ_TIM7 | + STM32_DBGMCU_APB1FZ_RTC | STM32_DBGMCU_APB1FZ_WWDG | + STM32_DBGMCU_APB1FZ_IWDG; + apb2fz_reg = STM32_DBGMCU_APB2FZ_TIM1 | STM32_DBGMCU_APB2FZ_TIM8 | + STM32_DBGMCU_APB2FZ_TIM15 | STM32_DBGMCU_APB2FZ_TIM16 | + STM32_DBGMCU_APB2FZ_TIM17 | STM32_DBGMCU_APB2FZ_TIM20; #elif defined(CHIP_FAMILY_STM32H7) /* TODO(b/67081508) */ #endif @@ -274,7 +273,7 @@ void system_pre_init(void) /* enable clock on Power module */ #ifndef CHIP_FAMILY_STM32H7 -#ifdef CHIP_FAMILY_STM32L4 +#ifdef CHIP_FAMILY_STM32L4 STM32_RCC_APB1ENR1 |= STM32_RCC_PWREN; #else STM32_RCC_APB1ENR |= STM32_RCC_PWREN; @@ -322,10 +321,10 @@ void system_pre_init(void) /* Enable RTC and use LSI as clock source */ STM32_RCC_CSR = (STM32_RCC_CSR & ~0x00C30000) | 0x00420000; } -#elif defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \ - defined(CHIP_FAMILY_STM32L4) || \ - defined(CHIP_FAMILY_STM32L5) || defined(CHIP_FAMILY_STM32F4) || \ - defined(CHIP_FAMILY_STM32H7) || defined(CHIP_FAMILY_STM32G4) +#elif defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \ + defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5) || \ + defined(CHIP_FAMILY_STM32F4) || defined(CHIP_FAMILY_STM32H7) || \ + defined(CHIP_FAMILY_STM32G4) if ((STM32_RCC_BDCR & BDCR_ENABLE_MASK) != BDCR_ENABLE_VALUE) { /* The RTC settings are bad, we need to reset it */ STM32_RCC_BDCR |= STM32_RCC_BDCR_BDRST; @@ -438,9 +437,9 @@ void system_reset(int flags) bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_REASON, reason); bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_INFO, info); bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_EXCEPTION, - exception); + exception); bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_FLAGS, - panic_flags); + panic_flags); } #endif @@ -633,19 +632,19 @@ int system_is_reboot_warm(void) #elif defined(CHIP_FAMILY_STM32L) return ((STM32_RCC_AHBENR & 0x3f) == 0x3f); #elif defined(CHIP_FAMILY_STM32L4) - return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK) - == STM32_RCC_AHB2ENR_GPIOMASK); + return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK) == + STM32_RCC_AHB2ENR_GPIOMASK); #elif defined(CHIP_FAMILY_STM32L5) - return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK) - == STM32_RCC_AHB2ENR_GPIOMASK); + return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK) == + STM32_RCC_AHB2ENR_GPIOMASK); #elif defined(CHIP_FAMILY_STM32F4) - return ((STM32_RCC_AHB1ENR & STM32_RCC_AHB1ENR_GPIOMASK) - == gpio_required_clocks()); + return ((STM32_RCC_AHB1ENR & STM32_RCC_AHB1ENR_GPIOMASK) == + gpio_required_clocks()); #elif defined(CHIP_FAMILY_STM32G4) - return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK) - == gpio_required_clocks()); + return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK) == + gpio_required_clocks()); #elif defined(CHIP_FAMILY_STM32H7) - return ((STM32_RCC_AHB4ENR & STM32_RCC_AHB4ENR_GPIOMASK) - == STM32_RCC_AHB4ENR_GPIOMASK); + return ((STM32_RCC_AHB4ENR & STM32_RCC_AHB4ENR_GPIOMASK) == + STM32_RCC_AHB4ENR_GPIOMASK); #endif } diff --git a/chip/stm32/trng.c b/chip/stm32/trng.c index 48d5335c53..aafc0e89c1 100644 --- a/chip/stm32/trng.c +++ b/chip/stm32/trng.c @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,13 +9,14 @@ #include "console.h" #include "host_command.h" #include "panic.h" +#include "printf.h" #include "registers.h" #include "system.h" #include "task.h" #include "trng.h" #include "util.h" -uint32_t rand(void) +uint32_t trng_rand(void) { int tries = 300; /* Wait for a valid random number */ @@ -28,10 +29,10 @@ uint32_t rand(void) return STM32_RNG_DR; } -test_mockable void rand_bytes(void *buffer, size_t len) +test_mockable void trng_rand_bytes(void *buffer, size_t len) { while (len) { - uint32_t number = rand(); + uint32_t number = trng_rand(); size_t cnt = 4; /* deal with the lack of alignment guarantee in the API */ uintptr_t align = (uintptr_t)buffer & 3; @@ -47,7 +48,7 @@ test_mockable void rand_bytes(void *buffer, size_t len) } } -test_mockable void init_trng(void) +test_mockable void trng_init(void) { #ifdef CHIP_FAMILY_STM32L4 /* Enable the 48Mhz internal RC oscillator */ @@ -57,8 +58,8 @@ test_mockable void init_trng(void) ; /* Clock the TRNG using the HSI48 */ - STM32_RCC_CCIPR = (STM32_RCC_CCIPR & ~STM32_RCC_CCIPR_CLK48SEL_MASK) - | (0 << STM32_RCC_CCIPR_CLK48SEL_SHIFT); + STM32_RCC_CCIPR = (STM32_RCC_CCIPR & ~STM32_RCC_CCIPR_CLK48SEL_MASK) | + (0 << STM32_RCC_CCIPR_CLK48SEL_SHIFT); #elif defined(CHIP_FAMILY_STM32H7) /* Enable the 48Mhz internal RC oscillator */ STM32_RCC_CR |= STM32_RCC_CR_HSI48ON; @@ -68,8 +69,8 @@ test_mockable void init_trng(void) /* Clock the TRNG using the HSI48 */ STM32_RCC_D2CCIP2R = - (STM32_RCC_D2CCIP2R & ~STM32_RCC_D2CCIP2_RNGSEL_MASK) - | STM32_RCC_D2CCIP2_RNGSEL_HSI48; + (STM32_RCC_D2CCIP2R & ~STM32_RCC_D2CCIP2_RNGSEL_MASK) | + STM32_RCC_D2CCIP2_RNGSEL_HSI48; #elif defined(CHIP_FAMILY_STM32F4) /* * The RNG clock is the same as the SDIO/USB OTG clock, already set at @@ -84,7 +85,7 @@ test_mockable void init_trng(void) STM32_RNG_CR |= STM32_RNG_CR_RNGEN; } -test_mockable void exit_trng(void) +test_mockable void trng_exit(void) { STM32_RNG_CR &= ~STM32_RNG_CR_RNGEN; STM32_RCC_AHB2ENR &= ~STM32_RCC_AHB2ENR_RNGEN; @@ -103,20 +104,23 @@ test_mockable void exit_trng(void) * update RO once in production. */ #if defined(SECTION_IS_RW) -static int command_rand(int argc, char **argv) +static int command_rand(int argc, const char **argv) { uint8_t data[32]; + char str_buf[hex_str_buf_size(sizeof(data))]; - init_trng(); - rand_bytes(data, sizeof(data)); - exit_trng(); + trng_init(); + trng_rand_bytes(data, sizeof(data)); + trng_exit(); - ccprintf("rand %ph\n", HEX_BUF(data, sizeof(data))); + snprintf_hex_buffer(str_buf, sizeof(str_buf), + HEX_BUF(data, sizeof(data))); + ccprintf("rand %s\n", str_buf); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(rand, command_rand, - NULL, "Output random bytes to console."); +DECLARE_CONSOLE_COMMAND(rand, command_rand, NULL, + "Output random bytes to console."); static enum ec_status host_command_rand(struct host_cmd_handler_args *args) { @@ -130,9 +134,9 @@ static enum ec_status host_command_rand(struct host_cmd_handler_args *args) if (num_rand_bytes > args->response_max) return EC_RES_OVERFLOW; - init_trng(); - rand_bytes(r->rand, num_rand_bytes); - exit_trng(); + trng_init(); + trng_rand_bytes(r->rand, num_rand_bytes); + trng_exit(); args->response_size = num_rand_bytes; diff --git a/chip/stm32/uart.c b/chip/stm32/uart.c index 6be0790c63..1bb961a935 100644 --- a/chip/stm32/uart.c +++ b/chip/stm32/uart.c @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -18,7 +18,7 @@ #include "stm32-dma.h" /* Console USART index */ -#define UARTN CONFIG_UART_CONSOLE +#define UARTN CONFIG_UART_CONSOLE #define UARTN_BASE STM32_USART_BASE(CONFIG_UART_CONSOLE) #ifdef CONFIG_UART_TX_DMA @@ -33,7 +33,7 @@ static const struct dma_option dma_tx_option = { CONFIG_UART_TX_DMA_CH, (void *)&STM32_USART_TDR(UARTN_BASE), STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT #ifdef CHIP_FAMILY_STM32F4 - | STM32_DMA_CCR_CHANNEL(CONFIG_UART_TX_REQ_CH) + | STM32_DMA_CCR_CHANNEL(CONFIG_UART_TX_REQ_CH) #endif }; @@ -51,16 +51,16 @@ static const struct dma_option dma_rx_option = { CONFIG_UART_RX_DMA_CH, (void *)&STM32_USART_RDR(UARTN_BASE), STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | #ifdef CHIP_FAMILY_STM32F4 - STM32_DMA_CCR_CHANNEL(CONFIG_UART_RX_REQ_CH) | + STM32_DMA_CCR_CHANNEL(CONFIG_UART_RX_REQ_CH) | #endif - STM32_DMA_CCR_CIRC + STM32_DMA_CCR_CIRC }; -static int dma_rx_len; /* Size of receive DMA circular buffer */ +static int dma_rx_len; /* Size of receive DMA circular buffer */ #endif -static int init_done; /* Initialization done? */ -static int should_stop; /* Last TX control action */ +static int init_done; /* Initialization done? */ +static int should_stop; /* Last TX control action */ int uart_init_done(void) { @@ -249,13 +249,13 @@ static void uart_freq_change(void) freq = clock_get_freq(); #endif -#if (UARTN == 9) /* LPUART */ +#if (UARTN == 9) /* LPUART */ div = DIV_ROUND_NEAREST(freq, CONFIG_UART_BAUD_RATE) * 256; #else div = DIV_ROUND_NEAREST(freq, CONFIG_UART_BAUD_RATE); #endif -#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F0) || \ +#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F0) || \ defined(CHIP_FAMILY_STM32F3) || defined(CHIP_FAMILY_STM32L4) || \ defined(CHIP_FAMILY_STM32F4) || defined(CHIP_FAMILY_STM32G4) if (div / 16 > 0) { @@ -277,7 +277,6 @@ static void uart_freq_change(void) /* STM32F only supports x16 oversampling */ STM32_USART_BRR(UARTN_BASE) = div; #endif - } DECLARE_HOOK(HOOK_FREQ_CHANGE, uart_freq_change, HOOK_PRIO_DEFAULT); @@ -286,7 +285,7 @@ void uart_init(void) /* Select clock source */ #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) #if (UARTN == 1) - STM32_RCC_CFGR3 |= 0x0003; /* USART1 clock source from HSI(8MHz) */ + STM32_RCC_CFGR3 |= 0x0003; /* USART1 clock source from HSI(8MHz) */ #elif (UARTN == 2) STM32_RCC_CFGR3 |= 0x030000; /* USART2 clock source from HSI(8MHz) */ #endif /* UARTN */ @@ -339,8 +338,8 @@ void uart_init(void) /* Configure GPIOs */ gpio_config_module(MODULE_UART, 1); -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) \ -|| defined(CHIP_FAMILY_STM32H7) || defined(CHIP_FAMILY_STM32L4) +#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \ + defined(CHIP_FAMILY_STM32H7) || defined(CHIP_FAMILY_STM32L4) /* * Wake up on start bit detection. WUS can only be written when UE=0, * so clear UE first. @@ -352,7 +351,7 @@ void uart_init(void) * and we don't want to clear an extra flag in the interrupt */ STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_WUS_START_BIT | - STM32_USART_CR3_OVRDIS; + STM32_USART_CR3_OVRDIS; #endif /* @@ -360,11 +359,10 @@ void uart_init(void) * TX and RX enabled. */ #ifdef CHIP_FAMILY_STM32L4 - STM32_USART_CR1(UARTN_BASE) = - STM32_USART_CR1_TE | STM32_USART_CR1_RE; + STM32_USART_CR1(UARTN_BASE) = STM32_USART_CR1_TE | STM32_USART_CR1_RE; #else - STM32_USART_CR1(UARTN_BASE) = - STM32_USART_CR1_UE | STM32_USART_CR1_TE | STM32_USART_CR1_RE; + STM32_USART_CR1(UARTN_BASE) = STM32_USART_CR1_UE | STM32_USART_CR1_TE | + STM32_USART_CR1_RE; #endif /* 1 stop bit, no fancy stuff */ diff --git a/chip/stm32/ucpd-stm32gx.c b/chip/stm32/ucpd-stm32gx.c index d8c41c8f28..3fec860200 100644 --- a/chip/stm32/ucpd-stm32gx.c +++ b/chip/stm32/ucpd-stm32gx.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -20,8 +20,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #define USB_VID_STM32 0x0483 @@ -33,22 +33,19 @@ */ #define UCPD_BUF_LEN 30 -#define UCPD_IMR_RX_INT_MASK (STM32_UCPD_IMR_RXNEIE| \ - STM32_UCPD_IMR_RXORDDETIE | \ - STM32_UCPD_IMR_RXHRSTDETIE | \ - STM32_UCPD_IMR_RXOVRIE | \ - STM32_UCPD_IMR_RXMSGENDIE) +#define UCPD_IMR_RX_INT_MASK \ + (STM32_UCPD_IMR_RXNEIE | STM32_UCPD_IMR_RXORDDETIE | \ + STM32_UCPD_IMR_RXHRSTDETIE | STM32_UCPD_IMR_RXOVRIE | \ + STM32_UCPD_IMR_RXMSGENDIE) -#define UCPD_IMR_TX_INT_MASK (STM32_UCPD_IMR_TXISIE | \ - STM32_UCPD_IMR_TXMSGDISCIE | \ - STM32_UCPD_IMR_TXMSGSENTIE | \ - STM32_UCPD_IMR_TXMSGABTIE | \ - STM32_UCPD_IMR_TXUNDIE) +#define UCPD_IMR_TX_INT_MASK \ + (STM32_UCPD_IMR_TXISIE | STM32_UCPD_IMR_TXMSGDISCIE | \ + STM32_UCPD_IMR_TXMSGSENTIE | STM32_UCPD_IMR_TXMSGABTIE | \ + STM32_UCPD_IMR_TXUNDIE) -#define UCPD_ICR_TX_INT_MASK (STM32_UCPD_ICR_TXMSGDISCCF | \ - STM32_UCPD_ICR_TXMSGSENTCF | \ - STM32_UCPD_ICR_TXMSGABTCF | \ - STM32_UCPD_ICR_TXUNDCF) +#define UCPD_ICR_TX_INT_MASK \ + (STM32_UCPD_ICR_TXMSGDISCCF | STM32_UCPD_ICR_TXMSGSENTCF | \ + STM32_UCPD_ICR_TXMSGABTCF | STM32_UCPD_ICR_TXUNDCF) #define UCPD_ANASUB_TO_RP(r) ((r - 1) & 0x3) #define UCPD_RP_TO_ANASUB(r) ((r + 1) & 0x3) @@ -69,16 +66,16 @@ enum ucpd_state { }; /* Events for pd_interrupt_handler_task */ -#define UCPD_EVT_GOOD_CRC_REQ BIT(0) -#define UCPD_EVT_TCPM_MSG_REQ BIT(1) -#define UCPD_EVT_HR_REQ BIT(2) -#define UCPD_EVT_TX_MSG_FAIL BIT(3) -#define UCPD_EVT_TX_MSG_DISC BIT(4) +#define UCPD_EVT_GOOD_CRC_REQ BIT(0) +#define UCPD_EVT_TCPM_MSG_REQ BIT(1) +#define UCPD_EVT_HR_REQ BIT(2) +#define UCPD_EVT_TX_MSG_FAIL BIT(3) +#define UCPD_EVT_TX_MSG_DISC BIT(4) #define UCPD_EVT_TX_MSG_SUCCESS BIT(5) -#define UCPD_EVT_HR_DONE BIT(6) -#define UCPD_EVT_HR_FAIL BIT(7) -#define UCPD_EVT_RX_GOOD_CRC BIT(8) -#define UCPD_EVT_RX_MSG BIT(9) +#define UCPD_EVT_HR_DONE BIT(6) +#define UCPD_EVT_HR_FAIL BIT(7) +#define UCPD_EVT_RX_GOOD_CRC BIT(8) +#define UCPD_EVT_RX_MSG BIT(9) #define UCPD_T_RECEIVE_US (1 * MSEC) @@ -161,11 +158,7 @@ int ucpd_tx_state_log_idx; int ucpd_tx_state_log_freeze; static char ucpd_names[][12] = { - "TX_IDLE", - "ACT_TCPM", - "ACT_CRC", - "HARD_RST", - "WAIT_CRC", + "TX_IDLE", "ACT_TCPM", "ACT_CRC", "HARD_RST", "WAIT_CRC", }; /* Defines and macros used for ucpd pd message logging */ #define MSG_LOG_LEN 64 @@ -218,8 +211,8 @@ static void ucpd_log_add_msg(uint16_t header, int dir) * crc -> GoodCrc received following tx message */ if (msg_log_cnt++ < MSG_LOG_LEN) { - int msg_bytes = MIN((PD_HEADER_CNT(header) << 2) + 2, - MSG_BUF_LEN); + int msg_bytes = + MIN((PD_HEADER_CNT(header) << 2) + 2, MSG_BUF_LEN); msg_log[idx].header = header; msg_log[idx].ts = ts; @@ -278,10 +271,10 @@ static void ucpd_cc_status(int port) * values of CC voltage detector, polarity, and PD enable status are * displayed. */ - rv = stm32gx_ucpd_get_cc(port,&v_cc1, &v_cc2); + rv = stm32gx_ucpd_get_cc(port, &v_cc1, &v_cc2); rp_name = rp_string[(rc >> 4) % 0x3]; - ccprintf("\tcc1\t = %s\n\tcc2\t = %s\n\tRp\t = %s\n", - ccx[cc1_pull], ccx[cc2_pull], rp_name); + ccprintf("\tcc1\t = %s\n\tcc2\t = %s\n\tRp\t = %s\n", ccx[cc1_pull], + ccx[cc2_pull], rp_name); if (!rv) ccprintf("\tcc1_v\t = %d\n\tcc2_v\t = %d\n", v_cc1, v_cc2); } @@ -329,8 +322,8 @@ static void ucpd_cc_change_notify(void) ccprintf("vstate: cc1 = %x, cc2 = %x, Rp = %d\n", (sr >> STM32_UCPD_SR_VSTATE_CC1_SHIFT) & 0x3, (sr >> STM32_UCPD_SR_VSTATE_CC2_SHIFT) & 0x3, - (ucpd_cc_set_save >> STM32_UCPD_CR_ANASUBMODE_SHIFT) - & 0x3); + (ucpd_cc_set_save >> STM32_UCPD_CR_ANASUBMODE_SHIFT) & + 0x3); /* Display CC status on EC console */ ucpd_cc_status(0); } @@ -345,7 +338,9 @@ static int ucpd_msg_is_good_crc(uint16_t header) * type in the header. */ return ((PD_HEADER_CNT(header) == 0) && (PD_HEADER_EXT(header) == 0) && - (PD_HEADER_TYPE(header) == PD_CTRL_GOOD_CRC)) ? 1 : 0; + (PD_HEADER_TYPE(header) == PD_CTRL_GOOD_CRC)) ? + 1 : + 0; } static void ucpd_hard_reset_rx_log(void) @@ -365,7 +360,7 @@ static void ucpd_port_enable(int port, int enable) static int ucpd_is_cc_pull_active(int port, enum usbpd_cc_pin cc_line) { int cc_enable = (STM32_UCPD_CR(port) & STM32_UCPD_CR_CCENABLE_MASK) >> - STM32_UCPD_CR_CCENABLE_SHIFT; + STM32_UCPD_CR_CCENABLE_SHIFT; return ((cc_enable >> cc_line) & 0x1); } @@ -425,10 +420,10 @@ int stm32gx_ucpd_init(int port) task_disable_irq(STM32_IRQ_UCPD1); /* - * After exiting reset, stm32gx will have dead battery mode enabled by - * default which connects Rd to CC1/CC2. This should be disabled when EC - * is powered up. - */ + * After exiting reset, stm32gx will have dead battery mode enabled by + * default which connects Rd to CC1/CC2. This should be disabled when EC + * is powered up. + */ STM32_PWR_CR3 |= STM32_PWR_CR3_UCPD1_DBDIS; /* Ensure that clock to UCPD is enabled */ @@ -446,9 +441,9 @@ int stm32gx_ucpd_init(int port) ucpd_port_enable(port, 0); cfgr1_reg = STM32_UCPD_CFGR1_PSC_CLK_VAL(UCPD_PSC_DIV - 1) | - STM32_UCPD_CFGR1_TRANSWIN_VAL(UCPD_TRANSWIN_CNT - 1) | - STM32_UCPD_CFGR1_IFRGAP_VAL(UCPD_IFRGAP_CNT - 1) | - STM32_UCPD_CFGR1_HBITCLKD_VAL(UCPD_HBIT_DIV - 1); + STM32_UCPD_CFGR1_TRANSWIN_VAL(UCPD_TRANSWIN_CNT - 1) | + STM32_UCPD_CFGR1_IFRGAP_VAL(UCPD_IFRGAP_CNT - 1) | + STM32_UCPD_CFGR1_HBITCLKD_VAL(UCPD_HBIT_DIV - 1); STM32_UCPD_CFGR1(port) = cfgr1_reg; /* @@ -463,9 +458,9 @@ int stm32gx_ucpd_init(int port) /* Configure CC change interrupts */ STM32_UCPD_IMR(port) = STM32_UCPD_IMR_TYPECEVT1IE | - STM32_UCPD_IMR_TYPECEVT2IE; + STM32_UCPD_IMR_TYPECEVT2IE; STM32_UCPD_ICR(port) = STM32_UCPD_ICR_TYPECEVT1CF | - STM32_UCPD_ICR_TYPECEVT2CF; + STM32_UCPD_ICR_TYPECEVT2CF; /* SOP'/SOP'' must be enabled via TCPCI call */ ucpd_rx_sop_prime_enabled = false; @@ -486,7 +481,7 @@ int stm32gx_ucpd_release(int port) } int stm32gx_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2) + enum tcpc_cc_voltage_status *cc2) { int vstate_cc1; int vstate_cc2; @@ -500,7 +495,7 @@ int stm32gx_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1, * * vstate_cc maps directly to cc_state from tcpci spec when ANAMODE = 1, * but needs to be modified slightly for case ANAMODE = 0. - * + * * If presenting Rp (source), then need to to a circular shift of * vstate_ccx value: * vstate_cc | cc_state @@ -515,9 +510,9 @@ int stm32gx_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1, /* Get Rp or Rd active */ anamode = !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_ANAMODE); vstate_cc1 = (sr & STM32_UCPD_SR_VSTATE_CC1_MASK) >> - STM32_UCPD_SR_VSTATE_CC1_SHIFT; + STM32_UCPD_SR_VSTATE_CC1_SHIFT; vstate_cc2 = (sr & STM32_UCPD_SR_VSTATE_CC2_MASK) >> - STM32_UCPD_SR_VSTATE_CC2_SHIFT; + STM32_UCPD_SR_VSTATE_CC2_SHIFT; /* Do circular shift if port == source */ if (anamode) { @@ -544,8 +539,9 @@ int stm32gx_ucpd_get_role_control(int port) int cc1; int cc2; int anamode = !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_ANAMODE); - int anasubmode = (STM32_UCPD_CR(port) & STM32_UCPD_CR_ANASUBMODE_MASK) - >> STM32_UCPD_CR_ANASUBMODE_SHIFT; + int anasubmode = + (STM32_UCPD_CR(port) & STM32_UCPD_CR_ANASUBMODE_MASK) >> + STM32_UCPD_CR_ANASUBMODE_SHIFT; /* * Role control register is defined as: @@ -575,9 +571,9 @@ int stm32gx_ucpd_get_role_control(int port) * Rp = (ANASUBMODE - 1) & 0x3 */ cc1 = ucpd_is_cc_pull_active(port, USBPD_CC_PIN_1) ? anamode + 1 : - TYPEC_CC_OPEN; + TYPEC_CC_OPEN; cc2 = ucpd_is_cc_pull_active(port, USBPD_CC_PIN_2) ? anamode + 1 : - TYPEC_CC_OPEN; + TYPEC_CC_OPEN; role_control = cc1 | (cc2 << 2); /* Circular shift anasubmode to convert to Rp range */ role_control |= (UCPD_ANASUB_TO_RP(anasubmode) << 4); @@ -633,7 +629,7 @@ int stm32gx_ucpd_set_cc(int port, int cc_pull, int rp) /* Set ANAMODE if cc_pull is Rd */ if (cc_pull == TYPEC_CC_RD) { cr |= STM32_UCPD_CR_ANAMODE | STM32_UCPD_CR_CCENABLE_MASK; - /* Clear ANAMODE if cc_pull is Rp */ + /* Clear ANAMODE if cc_pull is Rp */ } else if (cc_pull == TYPEC_CC_RP) { cr &= ~(STM32_UCPD_CR_ANAMODE); cr |= ucpd_get_cc_enable_mask(port); @@ -650,7 +646,8 @@ int stm32gx_ucpd_set_cc(int port, int cc_pull, int rp) return EC_SUCCESS; } -int stm32gx_ucpd_set_polarity(int port, enum tcpc_cc_polarity polarity) { +int stm32gx_ucpd_set_polarity(int port, enum tcpc_cc_polarity polarity) +{ /* * Polarity impacts the PHYCCSEL, CCENABLE, and CCxTCDIS fields. This * function is called when polarity is updated at TCPM layer. STM32Gx @@ -707,7 +704,7 @@ int stm32gx_ucpd_sop_prime_enable(int port, bool enable) } int stm32gx_ucpd_get_chip_info(int port, int live, - struct ec_response_pd_chip_info_v1 *chip_info) + struct ec_response_pd_chip_info_v1 *chip_info) { chip_info->vendor_id = USB_VID_STM32; chip_info->product_id = 0; @@ -726,7 +723,7 @@ static int stm32gx_ucpd_start_transmit(int port, enum ucpd_tx_msg msg_type) type = ucpd_tx_active_buffer->type; if (type == TCPCI_MSG_TX_HARD_RESET) { - /* + /* * From RM0440 45.4.4: * In order to facilitate generation of a Hard Reset, a special * code of TXMODE field is used. No other fields need to be @@ -745,9 +742,9 @@ static int stm32gx_ucpd_start_transmit(int port, enum ucpd_tx_msg msg_type) */ /* Enable interrupt for Hard Reset sent/discarded */ STM32_UCPD_ICR(port) = STM32_UCPD_ICR_HRSTDISCCF | - STM32_UCPD_ICR_HRSTSENTCF; + STM32_UCPD_ICR_HRSTSENTCF; STM32_UCPD_IMR(port) |= STM32_UCPD_IMR_HRSTDISCIE | - STM32_UCPD_IMR_HRSTSENTIE; + STM32_UCPD_IMR_HRSTSENTIE; /* Initiate Hard Reset */ STM32_UCPD_CR(port) |= STM32_UCPD_CR_TXHRST; } else if (type != TCPCI_MSG_INVALID) { @@ -794,7 +791,7 @@ static int stm32gx_ucpd_start_transmit(int port, enum ucpd_tx_msg msg_type) STM32_UCPD_TX_ORDSETR(port) = ucpd_txorderset[type]; /* Reset msg byte index */ - ucpd_tx_active_buffer-> msg_index = 0; + ucpd_tx_active_buffer->msg_index = 0; /* Enable interrupts */ ucpd_tx_interrupts_enable(port, 1); @@ -860,13 +857,11 @@ static void ucpd_task_log_dump(void) ccprintf("\n\t UCDP Task Log\n"); for (n = 0; n < TX_STATE_LOG_LEN; n++) { - ccprintf("[%d]:\t\%8s\t%8s\t%02x\t%08x\t%09d\t%d\n", - n, + ccprintf("[%d]:\t\%8s\t%8s\t%02x\t%08x\t%09d\t%d\n", n, ucpd_names[ucpd_tx_statelog[idx].enter_state], ucpd_names[ucpd_tx_statelog[idx].exit_state], ucpd_tx_statelog[idx].tx_request, - ucpd_tx_statelog[idx].evt, - ucpd_tx_statelog[idx].ts, + ucpd_tx_statelog[idx].evt, ucpd_tx_statelog[idx].ts, ucpd_tx_statelog[idx].timeout_us); idx = (idx + 1) & TX_STATE_LOG_MASK; @@ -915,8 +910,8 @@ static void ucpd_manage_tx(int port, int evt) * not been sent yet, it needs to be discarded * based on the received message event. */ - pd_transmit_complete(port, - TCPC_TX_COMPLETE_DISCARDED); + pd_transmit_complete( + port, TCPC_TX_COMPLETE_DISCARDED); ucpd_tx_request &= ~MSG_TCPM_MASK; } else if (!ucpd_rx_msg_active) { ucpd_set_tx_state(STATE_ACTIVE_TCPM); @@ -924,9 +919,10 @@ static void ucpd_manage_tx(int port, int evt) /* Save msgID required for GoodCRC check */ hdr = ucpd_tx_buffers[TX_MSG_TCPM].data.header; msg_id_match = PD_HEADER_ID(hdr); - tx_retry_max = PD_HEADER_REV(hdr) == PD_REV30 ? - UCPD_N_RETRY_COUNT_REV30 : - UCPD_N_RETRY_COUNT_REV20; + tx_retry_max = + PD_HEADER_REV(hdr) == PD_REV30 ? + UCPD_N_RETRY_COUNT_REV30 : + UCPD_N_RETRY_COUNT_REV20; } } @@ -962,8 +958,9 @@ static void ucpd_manage_tx(int port, int evt) * was just received. */ ucpd_set_tx_state(STATE_IDLE); - pd_transmit_complete(port, - TCPC_TX_COMPLETE_DISCARDED); + pd_transmit_complete( + port, + TCPC_TX_COMPLETE_DISCARDED); ucpd_set_tx_state(STATE_IDLE); } else { /* @@ -977,8 +974,8 @@ static void ucpd_manage_tx(int port, int evt) enum tcpc_transmit_complete status; status = (evt & UCPD_EVT_TX_MSG_FAIL) ? - TCPC_TX_COMPLETE_FAILED : - TCPC_TX_COMPLETE_DISCARDED; + TCPC_TX_COMPLETE_FAILED : + TCPC_TX_COMPLETE_DISCARDED; ucpd_set_tx_state(STATE_IDLE); pd_transmit_complete(port, status); } @@ -997,11 +994,9 @@ static void ucpd_manage_tx(int port, int evt) break; case STATE_WAIT_CRC_ACK: - if (evt & UCPD_EVT_RX_GOOD_CRC && - ucpd_crc_id == msg_id_match) { + if (evt & UCPD_EVT_RX_GOOD_CRC && ucpd_crc_id == msg_id_match) { /* GoodCRC with matching ID was received */ - pd_transmit_complete(port, - TCPC_TX_COMPLETE_SUCCESS); + pd_transmit_complete(port, TCPC_TX_COMPLETE_SUCCESS); ucpd_set_tx_state(STATE_IDLE); #ifdef CONFIG_STM32G4_UCPD_DEBUG ucpd_log_mark_crc(); @@ -1026,8 +1021,7 @@ static void ucpd_manage_tx(int port, int evt) * in this state, then treat it as a discard from an * incoming message. */ - pd_transmit_complete(port, - TCPC_TX_COMPLETE_DISCARDED); + pd_transmit_complete(port, TCPC_TX_COMPLETE_DISCARDED); ucpd_set_tx_state(STATE_IDLE); } break; @@ -1064,7 +1058,7 @@ static void ucpd_manage_tx(int port, int evt) */ void ucpd_task(void *p) { - const int port = (int) ((intptr_t) p); + const int port = (int)((intptr_t)p); /* Init variables used to manage tx process */ stm32gx_ucpd_state_init(port); @@ -1117,8 +1111,8 @@ void ucpd_task(void *p) ucpd_manage_tx(port, evt); /* Look at task events only once. */ evt = 0; - } while (ucpd_tx_request && ucpd_tx_state == STATE_IDLE - && !ucpd_rx_msg_active); + } while (ucpd_tx_request && ucpd_tx_state == STATE_IDLE && + !ucpd_rx_msg_active); } } @@ -1176,9 +1170,7 @@ static void ucpd_send_good_crc(int port, uint16_t rx_header) task_set_event(TASK_ID_UCPD, UCPD_EVT_GOOD_CRC_REQ); } -int stm32gx_ucpd_transmit(int port, - enum tcpci_msg_type type, - uint16_t header, +int stm32gx_ucpd_transmit(int port, enum tcpci_msg_type type, uint16_t header, const uint32_t *data) { /* Length in bytes = (4 * object len) + 2 header byes */ @@ -1220,11 +1212,11 @@ int stm32gx_ucpd_get_message_raw(int port, uint32_t *payload, int *head) *head = *rx_header; #ifdef CONFIG_USB_PD_DECODE_SOP -/* - * The message header is a 16-bit value that's stored in a 32-bit data type. - * SOP* is encoded in bits 31 to 28 of the 32-bit data type. - * NOTE: The 4 byte header is not part of the PD spec. - */ + /* + * The message header is a 16-bit value that's stored in a 32-bit data + * type. SOP* is encoded in bits 31 to 28 of the 32-bit data type. NOTE: + * The 4 byte header is not part of the PD spec. + */ /* Get SOP value */ sop = STM32_UCPD_RX_ORDSETR(port) & STM32_UCPD_RXORDSETR_MASK; /* Put SOP in bits 31:28 of 32 bit header */ @@ -1253,9 +1245,10 @@ static void stm32gx_ucpd1_irq(void) /* STM32_IRQ_UCPD indicates this is from UCPD1, so port = 0 */ int port = 0; uint32_t sr = STM32_UCPD_SR(port); - uint32_t tx_done_mask = STM32_UCPD_SR_TXMSGSENT | STM32_UCPD_SR_TXMSGABT - | STM32_UCPD_SR_TXMSGDISC | STM32_UCPD_SR_HRSTSENT | - STM32_UCPD_SR_HRSTDISC; + uint32_t tx_done_mask = STM32_UCPD_SR_TXMSGSENT | + STM32_UCPD_SR_TXMSGABT | + STM32_UCPD_SR_TXMSGDISC | + STM32_UCPD_SR_HRSTSENT | STM32_UCPD_SR_HRSTDISC; /* Check for CC events, set event to wake PD task */ if (sr & (STM32_UCPD_SR_TYPECEVT1 | STM32_UCPD_SR_TYPECEVT2)) { @@ -1279,8 +1272,8 @@ static void stm32gx_ucpd1_irq(void) #ifdef CONFIG_STM32G4_UCPD_DEBUG ucpd_log_mark_tx_comp(); #endif - } else if (sr & (STM32_UCPD_SR_TXMSGABT | - STM32_UCPD_SR_TXUND)) { + } else if (sr & + (STM32_UCPD_SR_TXMSGABT | STM32_UCPD_SR_TXUND)) { task_set_event(TASK_ID_UCPD, UCPD_EVT_TX_MSG_FAIL); } else if (sr & STM32_UCPD_SR_TXMSGDISC) { task_set_event(TASK_ID_UCPD, UCPD_EVT_TX_MSG_DISC); @@ -1320,7 +1313,7 @@ static void stm32gx_ucpd1_irq(void) int good_crc = 0; type = STM32_UCPD_RX_ORDSETR(port) & - STM32_UCPD_RXORDSETR_MASK; + STM32_UCPD_RXORDSETR_MASK; good_crc = ucpd_msg_is_good_crc(*rx_header); @@ -1337,26 +1330,25 @@ static void stm32gx_ucpd1_irq(void) */ if (!good_crc && (ucpd_rx_sop_prime_enabled || type == TCPCI_MSG_SOP)) { - /* * If BIST test mode is active, then still need * to send GoodCRC reply, but there is no need * to send the message up to the tcpm layer. */ - if(!ucpd_rx_bist_mode) { + if (!ucpd_rx_bist_mode) { if (tcpm_enqueue_message(port)) - hook_call_deferred(&ucpd_rx_enque_error_data, - 0); + hook_call_deferred( + &ucpd_rx_enque_error_data, + 0); } - task_set_event(TASK_ID_UCPD, - UCPD_EVT_RX_MSG); + task_set_event(TASK_ID_UCPD, UCPD_EVT_RX_MSG); /* Send GoodCRC message (if required) */ ucpd_send_good_crc(port, *rx_header); } else if (good_crc) { task_set_event(TASK_ID_UCPD, - UCPD_EVT_RX_GOOD_CRC); + UCPD_EVT_RX_GOOD_CRC); ucpd_crc_id = PD_HEADER_ID(*rx_header); } } else { @@ -1379,44 +1371,16 @@ DECLARE_IRQ(STM32_IRQ_UCPD1, stm32gx_ucpd1_irq, 1); #ifdef CONFIG_STM32G4_UCPD_DEBUG static char ctrl_names[][12] = { - "rsvd", - "GoodCRC", - "Goto Min", - "Accept", - "Reject", - "Ping", - "PS_Rdy", - "Get_SRC", - "Get_SNK", - "DR_Swap", - "PR_Swap", - "VCONN_Swp", - "Wait", - "Soft_Rst", - "RSVD", - "RSVD", - "Not_Sup", - "Get_SRC_Ext", - "Get_Status", + "rsvd", "GoodCRC", "Goto Min", "Accept", "Reject", + "Ping", "PS_Rdy", "Get_SRC", "Get_SNK", "DR_Swap", + "PR_Swap", "VCONN_Swp", "Wait", "Soft_Rst", "RSVD", + "RSVD", "Not_Sup", "Get_SRC_Ext", "Get_Status", }; static char data_names[][10] = { - "RSVD", - "SRC_CAP", - "REQUEST", - "BIST", - "SINK_CAP", - "BATTERY", - "ALERT", - "GET_INFO", - "ENTER_USB", - "RSVD", - "RSVD", - "RSVD", - "RSVD", - "RSVD", - "RSVD", - "VDM", + "RSVD", "SRC_CAP", "REQUEST", "BIST", "SINK_CAP", "BATTERY", + "ALERT", "GET_INFO", "ENTER_USB", "RSVD", "RSVD", "RSVD", + "RSVD", "RSVD", "RSVD", "VDM", }; static void ucpd_dump_msg_log(void) @@ -1428,7 +1392,6 @@ static void ucpd_dump_msg_log(void) uint16_t header; char *name; - ccprintf("ucpd: msg_total = %d\n", msg_log_cnt); ccprintf("Idx\t Delta(us)\tDir\t Type\t\tLen\t s1 s2 PR\t DR\n"); ccprintf("-----------------------------------------------------------" @@ -1446,18 +1409,13 @@ static void ucpd_dump_msg_log(void) name = len ? data_names[type] : ctrl_names[type]; dir = msg_log[i].dir; if (i) { - delta_ts = msg_log[i].ts - msg_log[i-1].ts; + delta_ts = msg_log[i].ts - msg_log[i - 1].ts; } ccprintf("msg[%02d]: %08d\t %s\t %8s\t %02d\t %d %d\t" "%s\t %s", - i, - delta_ts, - dir ? "Rx" : "Tx", - name, - len, - msg_log[i].comp, - msg_log[i].crc, + i, delta_ts, dir ? "Rx" : "Tx", name, len, + msg_log[i].comp, msg_log[i].crc, PD_HEADER_PROLE(header) ? "SRC" : "SNK", PD_HEADER_DROLE(header) ? "DFP" : "UFP"); len = MIN((len * 4) + 2, MSG_BUF_LEN); @@ -1465,10 +1423,10 @@ static void ucpd_dump_msg_log(void) ccprintf(" %02x", msg_log[i].buf[j]); } else { if (i) { - delta_ts = msg_log[i].ts - msg_log[i-1].ts; + delta_ts = msg_log[i].ts - msg_log[i - 1].ts; } - ccprintf("msg[%02d]: %08d\t CC Voltage Change!", - i, delta_ts); + ccprintf("msg[%02d]: %08d\t CC Voltage Change!", i, + delta_ts); } ccprintf("\n"); msleep(5); @@ -1496,7 +1454,7 @@ static void stm32gx_ucpd_set_cc_debug(int port, int cc_mask, int pull, int rp) */ /* Get existing cc enable value */ cc_enable = (cr & STM32_UCPD_CR_CCENABLE_MASK) >> - STM32_UCPD_CR_CCENABLE_SHIFT; + STM32_UCPD_CR_CCENABLE_SHIFT; /* Apply cc_mask (enable CC line specified) */ cc_enable |= cc_mask; @@ -1527,12 +1485,12 @@ void ucpd_info(int port) /* Dump ucpd task state info */ ccprintf("ucpd: tx_state = %s, tx_req = %02x, timeout_us = %d\n", - ucpd_names[ucpd_tx_state], ucpd_tx_request, ucpd_timeout_us); + ucpd_names[ucpd_tx_state], ucpd_tx_request, ucpd_timeout_us); ucpd_task_log_dump(); } -static int command_ucpd(int argc, char **argv) +static int command_ucpd(int argc, const char **argv) { uint32_t tx_data = 0; char *e; diff --git a/chip/stm32/ucpd-stm32gx.h b/chip/stm32/ucpd-stm32gx.h index d3af41e5bc..d41503f9ef 100644 --- a/chip/stm32/ucpd-stm32gx.h +++ b/chip/stm32/ucpd-stm32gx.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -37,7 +37,6 @@ #define UCPD_TRANSWIN_CNT 8 #define UCPD_IFRGAP_CNT 17 - /* * K-codes and ordered set defines. These codes and sets are used to encode * which type of USB-PD message is being sent. This information can be found in @@ -47,48 +46,36 @@ #define UCPD_SYNC1 0x18u #define UCPD_SYNC2 0x11u #define UCPD_SYNC3 0x06u -#define UCPD_RST1 0x07u -#define UCPD_RST2 0x19u -#define UCPD_EOP 0x0Du +#define UCPD_RST1 0x07u +#define UCPD_RST2 0x19u +#define UCPD_EOP 0x0Du /* This order of this enum matches tcpm_sop_type */ enum ucpd_tx_ordset { - TX_ORDERSET_SOP = (UCPD_SYNC1 | - (UCPD_SYNC1<<5u) | - (UCPD_SYNC1<<10u) | - (UCPD_SYNC2<<15u)), - - TX_ORDERSET_SOP_PRIME = (UCPD_SYNC1 | - (UCPD_SYNC1<<5u) | - (UCPD_SYNC3<<10u) | - (UCPD_SYNC3<<15u)), - - TX_ORDERSET_SOP_PRIME_PRIME = (UCPD_SYNC1 | - (UCPD_SYNC3<<5u) | - (UCPD_SYNC1<<10u) | - (UCPD_SYNC3<<15u)), - - TX_ORDERSET_SOP_PRIME_DEBUG = (UCPD_SYNC1 | - (UCPD_RST2<<5u) | - (UCPD_RST2<<10u) | - (UCPD_SYNC3<<15u)), - - TX_ORDERSET_SOP_PRIME_PRIME_DEBUG = (UCPD_SYNC1 | - (UCPD_RST2<<5u) | - (UCPD_SYNC3<<10u) | - (UCPD_SYNC2<<15u)), - - TX_ORDERSET_HARD_RESET = (UCPD_RST1 | - (UCPD_RST1<<5u) | - (UCPD_RST1<<10u) | - (UCPD_RST2<<15u)), - - TX_ORDERSET_CABLE_RESET = (UCPD_RST1 | - (UCPD_SYNC1<<5u) | - (UCPD_RST1<<10u) | - (UCPD_SYNC3<<15u)), -}; + TX_ORDERSET_SOP = (UCPD_SYNC1 | (UCPD_SYNC1 << 5u) | + (UCPD_SYNC1 << 10u) | (UCPD_SYNC2 << 15u)), + + TX_ORDERSET_SOP_PRIME = (UCPD_SYNC1 | (UCPD_SYNC1 << 5u) | + (UCPD_SYNC3 << 10u) | (UCPD_SYNC3 << 15u)), + + TX_ORDERSET_SOP_PRIME_PRIME = + (UCPD_SYNC1 | (UCPD_SYNC3 << 5u) | (UCPD_SYNC1 << 10u) | + (UCPD_SYNC3 << 15u)), + TX_ORDERSET_SOP_PRIME_DEBUG = + (UCPD_SYNC1 | (UCPD_RST2 << 5u) | (UCPD_RST2 << 10u) | + (UCPD_SYNC3 << 15u)), + + TX_ORDERSET_SOP_PRIME_PRIME_DEBUG = + (UCPD_SYNC1 | (UCPD_RST2 << 5u) | (UCPD_SYNC3 << 10u) | + (UCPD_SYNC2 << 15u)), + + TX_ORDERSET_HARD_RESET = (UCPD_RST1 | (UCPD_RST1 << 5u) | + (UCPD_RST1 << 10u) | (UCPD_RST2 << 15u)), + + TX_ORDERSET_CABLE_RESET = (UCPD_RST1 | (UCPD_SYNC1 << 5u) | + (UCPD_RST1 << 10u) | (UCPD_SYNC3 << 15u)), +}; /** * STM32Gx UCPD implementation of tcpci .init method @@ -172,9 +159,7 @@ int stm32gx_ucpd_set_msg_header(int port, int power_role, int data_role); * @param *data -> pointer to message contents * @return EC_SUCCESS */ -int stm32gx_ucpd_transmit(int port, - enum tcpci_msg_type type, - uint16_t header, +int stm32gx_ucpd_transmit(int port, enum tcpci_msg_type type, uint16_t header, const uint32_t *data); /** diff --git a/chip/stm32/usart-stm32f0.c b/chip/stm32/usart-stm32f0.c index 740d3929bc..56325cdc74 100644 --- a/chip/stm32/usart-stm32f0.c +++ b/chip/stm32/usart-stm32f0.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -23,7 +23,7 @@ static struct usart_config const *configs[STM32_USARTS_MAX]; struct usart_configs usart_get_configs(void) { - return (struct usart_configs) {configs, ARRAY_SIZE(configs)}; + return (struct usart_configs){ configs, ARRAY_SIZE(configs) }; } static void usart_variant_enable(struct usart_config const *config) @@ -54,8 +54,7 @@ static void usart_variant_disable(struct usart_config const *config) * Only disable the shared interrupt for USART3/4 if both USARTs are * now disabled. */ - if ((index == 0) || - (index == 1) || + if ((index == 0) || (index == 1) || (index == 2 && configs[3] == NULL) || (index == 3 && configs[2] == NULL)) task_disable_irq(config->hw->irq); @@ -64,18 +63,18 @@ static void usart_variant_disable(struct usart_config const *config) } static struct usart_hw_ops const usart_variant_hw_ops = { - .enable = usart_variant_enable, + .enable = usart_variant_enable, .disable = usart_variant_disable, }; static void freq_change(void) { - size_t i; + size_t i; for (i = 0; i < ARRAY_SIZE(configs); ++i) if (configs[i]) usart_set_baud_f0_l(configs[i], configs[i]->baud, - clock_get_freq()); + clock_get_freq()); } DECLARE_HOOK(HOOK_FREQ_CHANGE, freq_change, HOOK_PRIO_DEFAULT); @@ -98,12 +97,12 @@ void usart_clear_tc(struct usart_config const *config) */ #if defined(CONFIG_STREAM_USART1) struct usart_hw_config const usart1_hw = { - .index = 0, - .base = STM32_USART1_BASE, - .irq = STM32_IRQ_USART1, + .index = 0, + .base = STM32_USART1_BASE, + .irq = STM32_IRQ_USART1, .clock_register = &STM32_RCC_APB2ENR, - .clock_enable = STM32_RCC_PB2_USART1, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB2_USART1, + .ops = &usart_variant_hw_ops, }; static void usart1_interrupt(void) @@ -116,12 +115,12 @@ DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2); #if defined(CONFIG_STREAM_USART2) struct usart_hw_config const usart2_hw = { - .index = 1, - .base = STM32_USART2_BASE, - .irq = STM32_IRQ_USART2, + .index = 1, + .base = STM32_USART2_BASE, + .irq = STM32_IRQ_USART2, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART2, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART2, + .ops = &usart_variant_hw_ops, }; static void usart2_interrupt(void) @@ -134,23 +133,23 @@ DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2); #if defined(CONFIG_STREAM_USART3) struct usart_hw_config const usart3_hw = { - .index = 2, - .base = STM32_USART3_BASE, - .irq = STM32_IRQ_USART3_4, + .index = 2, + .base = STM32_USART3_BASE, + .irq = STM32_IRQ_USART3_4, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART3, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART3, + .ops = &usart_variant_hw_ops, }; #endif #if defined(CONFIG_STREAM_USART4) struct usart_hw_config const usart4_hw = { - .index = 3, - .base = STM32_USART4_BASE, - .irq = STM32_IRQ_USART3_4, + .index = 3, + .base = STM32_USART4_BASE, + .irq = STM32_IRQ_USART3_4, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART4, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART4, + .ops = &usart_variant_hw_ops, }; #endif diff --git a/chip/stm32/usart-stm32f0.h b/chip/stm32/usart-stm32f0.h index 1b7eee95a7..72c88fba9c 100644 --- a/chip/stm32/usart-stm32f0.h +++ b/chip/stm32/usart-stm32f0.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/stm32/usart-stm32f3.c b/chip/stm32/usart-stm32f3.c index 887d79d21f..f5a138643c 100644 --- a/chip/stm32/usart-stm32f3.c +++ b/chip/stm32/usart-stm32f3.c @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -22,7 +22,7 @@ static struct usart_config const *configs[STM32_USARTS_MAX]; struct usart_configs usart_get_configs(void) { - return (struct usart_configs) {configs, ARRAY_SIZE(configs)}; + return (struct usart_configs){ configs, ARRAY_SIZE(configs) }; } static void usart_variant_enable(struct usart_config const *config) @@ -50,7 +50,7 @@ static void usart_variant_disable(struct usart_config const *config) } static struct usart_hw_ops const usart_variant_hw_ops = { - .enable = usart_variant_enable, + .enable = usart_variant_enable, .disable = usart_variant_disable, }; @@ -72,12 +72,12 @@ void usart_clear_tc(struct usart_config const *config) */ #if defined(CONFIG_STREAM_USART1) struct usart_hw_config const usart1_hw = { - .index = 0, - .base = STM32_USART1_BASE, - .irq = STM32_IRQ_USART1, + .index = 0, + .base = STM32_USART1_BASE, + .irq = STM32_IRQ_USART1, .clock_register = &STM32_RCC_APB2ENR, - .clock_enable = STM32_RCC_PB2_USART1, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB2_USART1, + .ops = &usart_variant_hw_ops, }; static void usart1_interrupt(void) @@ -90,12 +90,12 @@ DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2); #if defined(CONFIG_STREAM_USART2) struct usart_hw_config const usart2_hw = { - .index = 1, - .base = STM32_USART2_BASE, - .irq = STM32_IRQ_USART2, + .index = 1, + .base = STM32_USART2_BASE, + .irq = STM32_IRQ_USART2, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART2, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART2, + .ops = &usart_variant_hw_ops, }; static void usart2_interrupt(void) @@ -108,12 +108,12 @@ DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2); #if defined(CONFIG_STREAM_USART3) struct usart_hw_config const usart3_hw = { - .index = 2, - .base = STM32_USART3_BASE, - .irq = STM32_IRQ_USART3, + .index = 2, + .base = STM32_USART3_BASE, + .irq = STM32_IRQ_USART3, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART3, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART3, + .ops = &usart_variant_hw_ops, }; #endif diff --git a/chip/stm32/usart-stm32f3.h b/chip/stm32/usart-stm32f3.h index 09f1ba608c..e1c391183d 100644 --- a/chip/stm32/usart-stm32f3.h +++ b/chip/stm32/usart-stm32f3.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/stm32/usart-stm32f4.c b/chip/stm32/usart-stm32f4.c index 2c9e4b1f4a..a710760e3a 100644 --- a/chip/stm32/usart-stm32f4.c +++ b/chip/stm32/usart-stm32f4.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -24,14 +24,13 @@ static struct usart_config const *configs[STM32_USARTS_MAX]; struct usart_configs usart_get_configs(void) { - return (struct usart_configs) {configs, ARRAY_SIZE(configs)}; + return (struct usart_configs){ configs, ARRAY_SIZE(configs) }; } static void usart_variant_enable(struct usart_config const *config) { configs[config->hw->index] = config; - /* Use single-bit sampling */ STM32_USART_CR3(config->hw->base) |= STM32_USART_CR3_ONEBIT; @@ -48,7 +47,7 @@ static void usart_variant_disable(struct usart_config const *config) } static struct usart_hw_ops const usart_variant_hw_ops = { - .enable = usart_variant_enable, + .enable = usart_variant_enable, .disable = usart_variant_disable, }; @@ -58,12 +57,12 @@ static struct usart_hw_ops const usart_variant_hw_ops = { */ #if defined(CONFIG_STREAM_USART1) struct usart_hw_config const usart1_hw = { - .index = 0, - .base = STM32_USART1_BASE, - .irq = STM32_IRQ_USART1, + .index = 0, + .base = STM32_USART1_BASE, + .irq = STM32_IRQ_USART1, .clock_register = &STM32_RCC_APB2ENR, - .clock_enable = STM32_RCC_PB2_USART1, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB2_USART1, + .ops = &usart_variant_hw_ops, }; static void usart1_interrupt(void) @@ -76,12 +75,12 @@ DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2); #if defined(CONFIG_STREAM_USART2) struct usart_hw_config const usart2_hw = { - .index = 1, - .base = STM32_USART2_BASE, - .irq = STM32_IRQ_USART2, + .index = 1, + .base = STM32_USART2_BASE, + .irq = STM32_IRQ_USART2, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART2, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART2, + .ops = &usart_variant_hw_ops, }; static void usart2_interrupt(void) @@ -94,12 +93,12 @@ DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2); #if defined(CONFIG_STREAM_USART3) struct usart_hw_config const usart3_hw = { - .index = 2, - .base = STM32_USART3_BASE, - .irq = STM32_IRQ_USART3, + .index = 2, + .base = STM32_USART3_BASE, + .irq = STM32_IRQ_USART3, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART3, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART3, + .ops = &usart_variant_hw_ops, }; #endif diff --git a/chip/stm32/usart-stm32f4.h b/chip/stm32/usart-stm32f4.h index 49af2af405..5ecb4d62e1 100644 --- a/chip/stm32/usart-stm32f4.h +++ b/chip/stm32/usart-stm32f4.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/stm32/usart-stm32l.c b/chip/stm32/usart-stm32l.c index 8d23524bb0..dc300d598a 100644 --- a/chip/stm32/usart-stm32l.c +++ b/chip/stm32/usart-stm32l.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -23,7 +23,7 @@ static struct usart_config const *configs[STM32_USARTS_MAX]; struct usart_configs usart_get_configs(void) { - return (struct usart_configs) {configs, ARRAY_SIZE(configs)}; + return (struct usart_configs){ configs, ARRAY_SIZE(configs) }; } static void usart_variant_enable(struct usart_config const *config) @@ -52,18 +52,18 @@ static void usart_variant_disable(struct usart_config const *config) } static struct usart_hw_ops const usart_variant_hw_ops = { - .enable = usart_variant_enable, + .enable = usart_variant_enable, .disable = usart_variant_disable, }; static void freq_change(void) { - size_t i; + size_t i; for (i = 0; i < ARRAY_SIZE(configs); ++i) if (configs[i]) usart_set_baud_f0_l(configs[i], configs[i]->baud, - clock_get_freq()); + clock_get_freq()); } DECLARE_HOOK(HOOK_FREQ_CHANGE, freq_change, HOOK_PRIO_DEFAULT); @@ -79,12 +79,12 @@ void usart_clear_tc(struct usart_config const *config) */ #if defined(CONFIG_STREAM_USART1) struct usart_hw_config const usart1_hw = { - .index = 0, - .base = STM32_USART1_BASE, - .irq = STM32_IRQ_USART1, + .index = 0, + .base = STM32_USART1_BASE, + .irq = STM32_IRQ_USART1, .clock_register = &STM32_RCC_APB2ENR, - .clock_enable = STM32_RCC_PB2_USART1, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB2_USART1, + .ops = &usart_variant_hw_ops, }; static void usart1_interrupt(void) @@ -97,12 +97,12 @@ DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2); #if defined(CONFIG_STREAM_USART2) struct usart_hw_config const usart2_hw = { - .index = 1, - .base = STM32_USART2_BASE, - .irq = STM32_IRQ_USART2, + .index = 1, + .base = STM32_USART2_BASE, + .irq = STM32_IRQ_USART2, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART2, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART2, + .ops = &usart_variant_hw_ops, }; static void usart2_interrupt(void) @@ -115,12 +115,12 @@ DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2); #if defined(CONFIG_STREAM_USART3) struct usart_hw_config const usart3_hw = { - .index = 2, - .base = STM32_USART3_BASE, - .irq = STM32_IRQ_USART3, + .index = 2, + .base = STM32_USART3_BASE, + .irq = STM32_IRQ_USART3, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART3, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART3, + .ops = &usart_variant_hw_ops, }; static void usart3_interrupt(void) diff --git a/chip/stm32/usart-stm32l.h b/chip/stm32/usart-stm32l.h index eb1ae9db1d..2bb92fe1c7 100644 --- a/chip/stm32/usart-stm32l.h +++ b/chip/stm32/usart-stm32l.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/stm32/usart-stm32l5.c b/chip/stm32/usart-stm32l5.c index 2306f54606..30e0f009ff 100644 --- a/chip/stm32/usart-stm32l5.c +++ b/chip/stm32/usart-stm32l5.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,13 +17,13 @@ * each USART, an entry will be NULL if no USART driver is initialized for the * corresponding hardware instance. */ -#define STM32_USARTS_MAX 5 +#define STM32_USARTS_MAX 6 static struct usart_config const *configs[STM32_USARTS_MAX]; struct usart_configs usart_get_configs(void) { - return (struct usart_configs) {configs, ARRAY_SIZE(configs)}; + return (struct usart_configs){ configs, ARRAY_SIZE(configs) }; } static void usart_variant_enable(struct usart_config const *config) @@ -52,18 +52,18 @@ static void usart_variant_disable(struct usart_config const *config) } static struct usart_hw_ops const usart_variant_hw_ops = { - .enable = usart_variant_enable, + .enable = usart_variant_enable, .disable = usart_variant_disable, }; static void freq_change(void) { - size_t i; + size_t i; for (i = 0; i < ARRAY_SIZE(configs); ++i) if (configs[i]) usart_set_baud_f0_l(configs[i], configs[i]->baud, - clock_get_freq()); + clock_get_freq()); } DECLARE_HOOK(HOOK_FREQ_CHANGE, freq_change, HOOK_PRIO_DEFAULT); @@ -79,12 +79,12 @@ void usart_clear_tc(struct usart_config const *config) */ #if defined(CONFIG_STREAM_USART1) struct usart_hw_config const usart1_hw = { - .index = 0, - .base = STM32_USART1_BASE, - .irq = STM32_IRQ_USART1, + .index = 0, + .base = STM32_USART1_BASE, + .irq = STM32_IRQ_USART1, .clock_register = &STM32_RCC_APB2ENR, - .clock_enable = STM32_RCC_PB2_USART1, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB2_USART1, + .ops = &usart_variant_hw_ops, }; static void usart1_interrupt(void) @@ -97,12 +97,12 @@ DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2); #if defined(CONFIG_STREAM_USART2) struct usart_hw_config const usart2_hw = { - .index = 1, - .base = STM32_USART2_BASE, - .irq = STM32_IRQ_USART2, + .index = 1, + .base = STM32_USART2_BASE, + .irq = STM32_IRQ_USART2, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART2, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART2, + .ops = &usart_variant_hw_ops, }; static void usart2_interrupt(void) @@ -115,12 +115,12 @@ DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2); #if defined(CONFIG_STREAM_USART3) struct usart_hw_config const usart3_hw = { - .index = 2, - .base = STM32_USART3_BASE, - .irq = STM32_IRQ_USART3, + .index = 2, + .base = STM32_USART3_BASE, + .irq = STM32_IRQ_USART3, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART3, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART3, + .ops = &usart_variant_hw_ops, }; static void usart3_interrupt(void) @@ -133,12 +133,12 @@ DECLARE_IRQ(STM32_IRQ_USART3, usart3_interrupt, 2); #if defined(CONFIG_STREAM_USART4) struct usart_hw_config const usart4_hw = { - .index = 3, - .base = STM32_USART4_BASE, - .irq = STM32_IRQ_USART4, + .index = 3, + .base = STM32_USART4_BASE, + .irq = STM32_IRQ_USART4, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART4, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART4, + .ops = &usart_variant_hw_ops, }; static void usart4_interrupt(void) @@ -151,12 +151,12 @@ DECLARE_IRQ(STM32_IRQ_USART4, usart4_interrupt, 2); #if defined(CONFIG_STREAM_USART5) struct usart_hw_config const usart5_hw = { - .index = 4, - .base = STM32_USART5_BASE, - .irq = STM32_IRQ_USART5, + .index = 4, + .base = STM32_USART5_BASE, + .irq = STM32_IRQ_USART5, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART5, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART5, + .ops = &usart_variant_hw_ops, }; static void usart5_interrupt(void) @@ -166,3 +166,21 @@ static void usart5_interrupt(void) DECLARE_IRQ(STM32_IRQ_USART5, usart5_interrupt, 2); #endif + +#if defined(CONFIG_STREAM_USART9) +struct usart_hw_config const usart9_hw = { + .index = 5, + .base = STM32_USART9_BASE, + .irq = STM32_IRQ_USART9, + .clock_register = &STM32_RCC_APB1ENR2, + .clock_enable = STM32_RCC_APB1ENR2_LPUART1EN, + .ops = &usart_variant_hw_ops, +}; + +static void usart9_interrupt(void) +{ + usart_interrupt(configs[5]); +} + +DECLARE_IRQ(STM32_IRQ_USART9, usart9_interrupt, 2); +#endif diff --git a/chip/stm32/usart-stm32l5.h b/chip/stm32/usart-stm32l5.h index cf4f8cdd1f..ccc0985bda 100644 --- a/chip/stm32/usart-stm32l5.h +++ b/chip/stm32/usart-stm32l5.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -16,5 +16,6 @@ extern struct usart_hw_config const usart2_hw; extern struct usart_hw_config const usart3_hw; extern struct usart_hw_config const usart4_hw; extern struct usart_hw_config const usart5_hw; +extern struct usart_hw_config const usart9_hw; /* LPUART1 */ #endif /* __CROS_EC_USART_STM32L5_H */ diff --git a/chip/stm32/usart.c b/chip/stm32/usart.c index 7f8c55aaa6..be9d0a4571 100644 --- a/chip/stm32/usart.c +++ b/chip/stm32/usart.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -45,7 +45,7 @@ void usart_init(struct usart_config const *config) cr2 = 0x0000; cr3 = 0x0000; #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \ - defined(CHIP_FAMILY_STM32L4) + defined(CHIP_FAMILY_STM32L4) if (config->flags & USART_CONFIG_FLAG_RX_INV) cr2 |= BIT(16); if (config->flags & USART_CONFIG_FLAG_TX_INV) @@ -87,11 +87,16 @@ void usart_shutdown(struct usart_config const *config) } void usart_set_baud_f0_l(struct usart_config const *config, int baud, - int frequency_hz) + int frequency_hz) { - int div = DIV_ROUND_NEAREST(frequency_hz, baud); + int div = DIV_ROUND_NEAREST(frequency_hz, baud); intptr_t base = config->hw->base; +#ifdef STM32_USART9_BASE + if (config->hw->base == STM32_USART9_BASE) /* LPUART */ + div *= 256; +#endif + if (div / 16 > 0) { /* * CPU clock is high enough to support x16 oversampling. @@ -110,10 +115,15 @@ void usart_set_baud_f0_l(struct usart_config const *config, int baud, } void usart_set_baud_f(struct usart_config const *config, int baud, - int frequency_hz) + int frequency_hz) { int div = DIV_ROUND_NEAREST(frequency_hz, baud); +#ifdef STM32_USART9_BASE + if (config->hw->base == STM32_USART9_BASE) /* LPUART */ + div *= 256; +#endif + /* STM32F only supports x16 oversampling */ STM32_USART_BRR(config->hw->base) = div; } diff --git a/chip/stm32/usart.h b/chip/stm32/usart.h index 491bd66a04..9067fd4b6a 100644 --- a/chip/stm32/usart.h +++ b/chip/stm32/usart.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -97,12 +97,12 @@ extern struct usart_tx const usart_tx_interrupt; * structure are provided by each variants driver, one per physical USART. */ struct usart_hw_config { - int index; + int index; intptr_t base; - int irq; + int irq; uint32_t volatile *clock_register; - uint32_t clock_enable; + uint32_t clock_enable; struct usart_hw_ops const *ops; }; @@ -160,7 +160,7 @@ struct usart_config { * BUILD_ASSERT(RX_QUEUE.unit_bytes == 1); * BUILD_ASSERT(TX_QUEUE.unit_bytes == 1); */ -#define USART_CONFIG(HW, RX, TX, BAUD, FLAGS, RX_QUEUE, TX_QUEUE) \ +#define USART_CONFIG(HW, RX, TX, BAUD, FLAGS, RX_QUEUE, TX_QUEUE) \ ((struct usart_config const) { \ .hw = &HW, \ .rx = &RX, \ @@ -208,9 +208,9 @@ void usart_tx_start(struct usart_config const *config); * change. The baud rate divisor input frequency is passed in Hertz. */ void usart_set_baud_f0_l(struct usart_config const *config, int baud, - int frequency_hz); + int frequency_hz); void usart_set_baud_f(struct usart_config const *config, int baud, - int frequency_hz); + int frequency_hz); /* * Allow specification of parity for this usart. @@ -249,7 +249,7 @@ struct usart_configs { * * configs[i]->hw->index == i; */ - struct usart_config const * const *configs; + struct usart_config const *const *configs; /* * The total possible number of configs that this family supports. diff --git a/chip/stm32/usart_host_command.c b/chip/stm32/usart_host_command.c index f4d6a65fc4..437975e609 100644 --- a/chip/stm32/usart_host_command.c +++ b/chip/stm32/usart_host_command.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,8 +19,8 @@ #include "util.h" /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ##args) /* * Timeout to wait for complete request packet @@ -51,7 +51,7 @@ /* * Max data size for a version 3 request/response packet. This is big enough - * to handle a request/response header, flash write offset/size and 512 bytes + * to handle a request/response header, flash write offset/size and 512 bytes * of request payload or 224 bytes of response payload. */ #define USART_MAX_REQUEST_SIZE 0x220 @@ -271,12 +271,12 @@ static struct usart_rx_dma const usart_host_command_rx_dma = { * Configure USART structure with hardware, interrupt handlers, baudrate. */ static struct usart_config const tl_usart = { - .hw = &CONFIG_UART_HOST_COMMAND_HW, - .rx = &usart_host_command_rx_dma.usart_rx, - .tx = &usart_host_command_tx_interrupt, - .state = &((struct usart_state){}), - .baud = CONFIG_UART_HOST_COMMAND_BAUD_RATE, - .flags = 0, + .hw = &CONFIG_UART_HOST_COMMAND_HW, + .rx = &usart_host_command_rx_dma.usart_rx, + .tx = &usart_host_command_tx_interrupt, + .state = &((struct usart_state){}), + .baud = CONFIG_UART_HOST_COMMAND_BAUD_RATE, + .flags = 0, }; /* @@ -327,7 +327,7 @@ static void usart_host_command_process_request(void) { /* Handle usart_in_buffer as ec_host_request */ struct ec_host_request *ec_request = - (struct ec_host_request *)usart_in_buffer; + (struct ec_host_request *)usart_in_buffer; /* Prepare host_packet for host command task */ static struct host_packet uart_packet; @@ -362,16 +362,13 @@ static void usart_host_command_process_request(void) * Cancel deferred call to timeout handler as request * received was good. */ - hook_call_deferred( - &usart_host_command_request_timeout_data, - -1); + hook_call_deferred(&usart_host_command_request_timeout_data, -1); uart_packet.send_response = usart_host_command_process_response; uart_packet.request = usart_in_buffer; uart_packet.request_temp = NULL; uart_packet.request_max = sizeof(usart_in_buffer); - uart_packet.request_size = - host_request_expected_size(ec_request); + uart_packet.request_size = host_request_expected_size(ec_request); uart_packet.response = usart_out_buffer; uart_packet.response_max = sizeof(usart_out_buffer); uart_packet.response_size = 0; @@ -427,14 +424,10 @@ static void usart_host_command_process_response(struct host_packet *pkt) static void usart_host_command_reset(void) { /* Cancel deferred call to process_request. */ - hook_call_deferred( - &usart_host_command_process_request_data, - -1); + hook_call_deferred(&usart_host_command_process_request_data, -1); /* Cancel deferred call to timeout handler. */ - hook_call_deferred( - &usart_host_command_request_timeout_data, - -1); + hook_call_deferred(&usart_host_command_request_timeout_data, -1); /* * Disable interrupts before entering critical region @@ -491,7 +484,7 @@ size_t usart_host_command_rx_append_data(struct usart_config const *config, { /* Define ec_host_request pointer to process in bytes later*/ struct ec_host_request *ec_request = - (struct ec_host_request *) usart_in_buffer; + (struct ec_host_request *)usart_in_buffer; /* Once the header is received, store the datalen */ static int usart_in_datalen; @@ -504,8 +497,7 @@ size_t usart_host_command_rx_append_data(struct usart_config const *config, current_state == USART_HOST_CMD_RECEIVING || (usart_in_head + count) < USART_MAX_REQUEST_SIZE) { /* Copy all the bytes from DMA FIFO */ - memcpy(usart_in_buffer + usart_in_head, - src, count); + memcpy(usart_in_buffer + usart_in_head, src, count); } /* @@ -519,7 +511,7 @@ size_t usart_host_command_rx_append_data(struct usart_config const *config, if (current_state == USART_HOST_CMD_READY_TO_RX) { /* Kick deferred call to request timeout handler */ hook_call_deferred(&usart_host_command_request_timeout_data, - USART_REQ_RX_TIMEOUT); + USART_REQ_RX_TIMEOUT); /* Move current state to receiving */ current_state = USART_HOST_CMD_RECEIVING; @@ -551,8 +543,7 @@ size_t usart_host_command_rx_append_data(struct usart_config const *config, } else if (usart_in_head > usart_in_datalen) { /* Cancel deferred call to process_request */ hook_call_deferred( - &usart_host_command_process_request_data, - -1); + &usart_host_command_process_request_data, -1); /* Move state to overrun*/ current_state = USART_HOST_CMD_RX_OVERRUN; @@ -579,13 +570,12 @@ size_t usart_host_command_tx_remove_data(struct usart_config const *config, { size_t bytes_remaining = 0; - if (current_state == USART_HOST_CMD_SENDING && - usart_out_datalen != 0) { + if (current_state == USART_HOST_CMD_SENDING && usart_out_datalen != 0) { /* Calculate byte_remaining in out_buffer */ bytes_remaining = usart_out_datalen - usart_out_head; /* Get char on the head */ - *((uint8_t *) dest) = usart_out_buffer[usart_out_head++]; + *((uint8_t *)dest) = usart_out_buffer[usart_out_head++]; /* If no bytes remaining, reset layer to accept next * request. diff --git a/chip/stm32/usart_host_command.h b/chip/stm32/usart_host_command.h index ee41d8a59b..ee4bdd88dc 100644 --- a/chip/stm32/usart_host_command.h +++ b/chip/stm32/usart_host_command.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -6,7 +6,7 @@ #ifndef __CROS_EC_USART_HOST_COMMAND_H #define __CROS_EC_USART_HOST_COMMAND_H -#include <stdarg.h> /* For va_list */ +#include <stdarg.h> /* For va_list */ #include "common.h" #include "gpio.h" #include "host_command.h" diff --git a/chip/stm32/usart_info_command.c b/chip/stm32/usart_info_command.c index 7b7dc1362a..ca73b51210 100644 --- a/chip/stm32/usart_info_command.c +++ b/chip/stm32/usart_info_command.c @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -9,7 +9,7 @@ #include "console.h" #include "usart.h" -static int command_usart_info(int argc, char **argv) +static int command_usart_info(int argc, const char **argv) { struct usart_configs configs = usart_get_configs(); size_t i; @@ -39,7 +39,5 @@ static int command_usart_info(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(usart_info, - command_usart_info, - NULL, +DECLARE_CONSOLE_COMMAND(usart_info, command_usart_info, NULL, "Display USART info"); diff --git a/chip/stm32/usart_rx_dma.c b/chip/stm32/usart_rx_dma.c index c75ebdde41..21c8313c73 100644 --- a/chip/stm32/usart_rx_dma.c +++ b/chip/stm32/usart_rx_dma.c @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,7 +14,7 @@ #include "util.h" typedef size_t (*add_data_t)(struct usart_config const *config, - const uint8_t *src, size_t count); + const uint8_t *src, size_t count); void usart_rx_dma_init(struct usart_config const *config) { @@ -25,10 +25,9 @@ void usart_rx_dma_init(struct usart_config const *config) struct dma_option options = { .channel = dma_config->channel, - .periph = (void *)&STM32_USART_RDR(base), - .flags = (STM32_DMA_CCR_MSIZE_8_BIT | - STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CIRC), + .periph = (void *)&STM32_USART_RDR(base), + .flags = (STM32_DMA_CCR_MSIZE_8_BIT | + STM32_DMA_CCR_PSIZE_8_BIT | STM32_DMA_CCR_CIRC), }; if (IS_ENABLED(CHIP_FAMILY_STM32F4)) @@ -38,31 +37,29 @@ void usart_rx_dma_init(struct usart_config const *config) STM32_USART_CR1(base) |= STM32_USART_CR1_RE; STM32_USART_CR3(base) |= STM32_USART_CR3_DMAR; - dma_config->state->index = 0; + dma_config->state->index = 0; dma_config->state->max_bytes = 0; dma_start_rx(&options, dma_config->fifo_size, dma_config->fifo_buffer); } -static void usart_rx_dma_interrupt_common( - struct usart_config const *config, - add_data_t add_data) +static void usart_rx_dma_interrupt_common(struct usart_config const *config, + add_data_t add_data) { struct usart_rx_dma const *dma_config = DOWNCAST(config->rx, struct usart_rx_dma const, usart_rx); - dma_chan_t *channel = dma_get_channel(dma_config->channel); - size_t new_index = dma_bytes_done(channel, dma_config->fifo_size); - size_t old_index = dma_config->state->index; - size_t new_bytes = 0; - size_t added = 0; + dma_chan_t *channel = dma_get_channel(dma_config->channel); + size_t new_index = dma_bytes_done(channel, dma_config->fifo_size); + size_t old_index = dma_config->state->index; + size_t new_bytes = 0; + size_t added = 0; if (new_index > old_index) { new_bytes = new_index - old_index; - added = add_data(config, - dma_config->fifo_buffer + old_index, - new_bytes); + added = add_data(config, dma_config->fifo_buffer + old_index, + new_bytes); } else if (new_index < old_index) { /* * Handle the case where the received bytes are not contiguous @@ -71,12 +68,9 @@ static void usart_rx_dma_interrupt_common( */ new_bytes = dma_config->fifo_size - (old_index - new_index); - added = add_data(config, - dma_config->fifo_buffer + old_index, - dma_config->fifo_size - old_index) + - add_data(config, - dma_config->fifo_buffer, - new_index); + added = add_data(config, dma_config->fifo_buffer + old_index, + dma_config->fifo_size - old_index) + + add_data(config, dma_config->fifo_buffer, new_index); } else { /* (new_index == old_index): nothing to add to the queue. */ } @@ -89,8 +83,8 @@ static void usart_rx_dma_interrupt_common( dma_config->state->index = new_index; } -static size_t queue_add(struct usart_config const *config, - const uint8_t *src, size_t count) +static size_t queue_add(struct usart_config const *config, const uint8_t *src, + size_t count) { return queue_add_units(config->producer.queue, (void *)src, count); } @@ -100,7 +94,6 @@ void usart_rx_dma_interrupt(struct usart_config const *config) usart_rx_dma_interrupt_common(config, &queue_add); } - #if defined(CONFIG_USART_HOST_COMMAND) void usart_host_command_rx_dma_interrupt(struct usart_config const *config) { diff --git a/chip/stm32/usart_rx_dma.h b/chip/stm32/usart_rx_dma.h index 064ab8046c..6d273d18b9 100644 --- a/chip/stm32/usart_rx_dma.h +++ b/chip/stm32/usart_rx_dma.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -44,7 +44,7 @@ * reasonable stress test the "DMA RX max_bytes" value will be a reasonable * size for the FIFO (perhaps +10% for safety). */ -#define USART_RX_DMA(CHANNEL, FIFO_SIZE) \ +#define USART_RX_DMA(CHANNEL, FIFO_SIZE) \ ((struct usart_rx_dma const) { \ .usart_rx = { \ .producer_ops = { \ @@ -88,7 +88,7 @@ struct usart_rx_dma { struct usart_rx_dma_state volatile *state; uint8_t *fifo_buffer; - size_t fifo_size; + size_t fifo_size; enum dma_channel channel; }; diff --git a/chip/stm32/usart_rx_interrupt-stm32f0.c b/chip/stm32/usart_rx_interrupt-stm32f0.c index a756455f9b..dfbe6ec3ff 120000..100644 --- a/chip/stm32/usart_rx_interrupt-stm32f0.c +++ b/chip/stm32/usart_rx_interrupt-stm32f0.c @@ -1 +1,49 @@ -usart_rx_interrupt.c
\ No newline at end of file +/* Copyright 2014 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Interrupt based USART RX driver for STM32F0 and STM32F3 */ + +#include "usart.h" + +#include "atomic.h" +#include "common.h" +#include "queue.h" +#include "registers.h" + +static void usart_rx_init(struct usart_config const *config) +{ + intptr_t base = config->hw->base; + + STM32_USART_CR1(base) |= STM32_USART_CR1_RXNEIE; + STM32_USART_CR1(base) |= STM32_USART_CR1_RE; + STM32_USART_CR3(base) |= STM32_USART_CR3_OVRDIS; +} + +static void usart_rx_interrupt_handler(struct usart_config const *config) +{ + intptr_t base = config->hw->base; + int32_t status = STM32_USART_SR(base); + + if (status & STM32_USART_SR_RXNE) { + uint8_t byte = STM32_USART_RDR(base); + + if (!queue_add_unit(config->producer.queue, &byte)) + atomic_add((atomic_t *)&(config->state->rx_dropped), 1); + } +} + +struct usart_rx const usart_rx_interrupt = { + .producer_ops = { + /* + * Nothing to do here, we either had enough space in the queue + * when a character came in or we dropped it already. + */ + .read = NULL, + }, + + .init = usart_rx_init, + .interrupt = usart_rx_interrupt_handler, + .info = NULL, +}; diff --git a/chip/stm32/usart_rx_interrupt-stm32f3.c b/chip/stm32/usart_rx_interrupt-stm32f3.c index a756455f9b..dfbe6ec3ff 120000..100644 --- a/chip/stm32/usart_rx_interrupt-stm32f3.c +++ b/chip/stm32/usart_rx_interrupt-stm32f3.c @@ -1 +1,49 @@ -usart_rx_interrupt.c
\ No newline at end of file +/* Copyright 2014 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Interrupt based USART RX driver for STM32F0 and STM32F3 */ + +#include "usart.h" + +#include "atomic.h" +#include "common.h" +#include "queue.h" +#include "registers.h" + +static void usart_rx_init(struct usart_config const *config) +{ + intptr_t base = config->hw->base; + + STM32_USART_CR1(base) |= STM32_USART_CR1_RXNEIE; + STM32_USART_CR1(base) |= STM32_USART_CR1_RE; + STM32_USART_CR3(base) |= STM32_USART_CR3_OVRDIS; +} + +static void usart_rx_interrupt_handler(struct usart_config const *config) +{ + intptr_t base = config->hw->base; + int32_t status = STM32_USART_SR(base); + + if (status & STM32_USART_SR_RXNE) { + uint8_t byte = STM32_USART_RDR(base); + + if (!queue_add_unit(config->producer.queue, &byte)) + atomic_add((atomic_t *)&(config->state->rx_dropped), 1); + } +} + +struct usart_rx const usart_rx_interrupt = { + .producer_ops = { + /* + * Nothing to do here, we either had enough space in the queue + * when a character came in or we dropped it already. + */ + .read = NULL, + }, + + .init = usart_rx_init, + .interrupt = usart_rx_interrupt_handler, + .info = NULL, +}; diff --git a/chip/stm32/usart_rx_interrupt-stm32f4.c b/chip/stm32/usart_rx_interrupt-stm32f4.c index b796ae1175..1d86c7d5b6 100644 --- a/chip/stm32/usart_rx_interrupt-stm32f4.c +++ b/chip/stm32/usart_rx_interrupt-stm32f4.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -26,8 +26,8 @@ static void usart_rx_init(struct usart_config const *config) static void usart_rx_interrupt_handler(struct usart_config const *config) { - intptr_t base = config->hw->base; - int32_t status = STM32_USART_SR(base); + intptr_t base = config->hw->base; + int32_t status = STM32_USART_SR(base); if (status & STM32_USART_SR_RXNE) { uint8_t byte = STM32_USART_RDR(base); diff --git a/chip/stm32/usart_rx_interrupt-stm32l.c b/chip/stm32/usart_rx_interrupt-stm32l.c index a89d474d05..750809307b 100644 --- a/chip/stm32/usart_rx_interrupt-stm32l.c +++ b/chip/stm32/usart_rx_interrupt-stm32l.c @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -22,8 +22,8 @@ static void usart_rx_init(struct usart_config const *config) static void usart_rx_interrupt_handler(struct usart_config const *config) { - intptr_t base = config->hw->base; - int32_t status = STM32_USART_SR(base); + intptr_t base = config->hw->base; + int32_t status = STM32_USART_SR(base); /* * We have to check and clear the overrun error flag on STM32L because diff --git a/chip/stm32/usart_rx_interrupt-stm32l5.c b/chip/stm32/usart_rx_interrupt-stm32l5.c index fa644b6baf..45c2ecca9f 100644 --- a/chip/stm32/usart_rx_interrupt-stm32l5.c +++ b/chip/stm32/usart_rx_interrupt-stm32l5.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/stm32/usart_rx_interrupt.c b/chip/stm32/usart_rx_interrupt.c index 49d4e83894..dfbe6ec3ff 100644 --- a/chip/stm32/usart_rx_interrupt.c +++ b/chip/stm32/usart_rx_interrupt.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -23,8 +23,8 @@ static void usart_rx_init(struct usart_config const *config) static void usart_rx_interrupt_handler(struct usart_config const *config) { - intptr_t base = config->hw->base; - int32_t status = STM32_USART_SR(base); + intptr_t base = config->hw->base; + int32_t status = STM32_USART_SR(base); if (status & STM32_USART_SR_RXNE) { uint8_t byte = STM32_USART_RDR(base); diff --git a/chip/stm32/usart_tx_dma.c b/chip/stm32/usart_tx_dma.c index 0c8e2c73d6..8128231ff7 100644 --- a/chip/stm32/usart_tx_dma.c +++ b/chip/stm32/usart_tx_dma.c @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -36,13 +36,13 @@ static void usart_tx_dma_start(struct usart_config const *config, struct usart_tx_dma const *dma_config) { struct usart_tx_dma_state volatile *state = dma_config->state; - intptr_t base = config->hw->base; + intptr_t base = config->hw->base; struct dma_option options = { .channel = dma_config->channel, - .periph = (void *)&STM32_USART_TDR(base), - .flags = (STM32_DMA_CCR_MSIZE_8_BIT | - STM32_DMA_CCR_PSIZE_8_BIT), + .periph = (void *)&STM32_USART_TDR(base), + .flags = + (STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT), }; /* diff --git a/chip/stm32/usart_tx_dma.h b/chip/stm32/usart_tx_dma.h index c17164e04a..f1028e3a9e 100644 --- a/chip/stm32/usart_tx_dma.h +++ b/chip/stm32/usart_tx_dma.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -29,7 +29,7 @@ * required because the queue isn't notified that it has been read from until * after the DMA transfer completes. */ -#define USART_TX_DMA(CHANNEL, MAX_BYTES) \ +#define USART_TX_DMA(CHANNEL, MAX_BYTES) \ ((struct usart_tx_dma const) { \ .usart_tx = { \ .consumer_ops = { \ diff --git a/chip/stm32/usart_tx_interrupt.c b/chip/stm32/usart_tx_interrupt.c index d8d441ba1b..80d1d4df0f 100644 --- a/chip/stm32/usart_tx_interrupt.c +++ b/chip/stm32/usart_tx_interrupt.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -37,12 +37,11 @@ static void usart_written(struct consumer const *consumer, size_t count) STM32_USART_CR1(config->hw->base) |= STM32_USART_CR1_TXEIE; } -static void usart_tx_interrupt_handler_common( - struct usart_config const *config, - remove_data_t remove_data) +static void usart_tx_interrupt_handler_common(struct usart_config const *config, + remove_data_t remove_data) { intptr_t base = config->hw->base; - uint8_t byte; + uint8_t byte; if (!(STM32_USART_SR(base) & STM32_USART_SR_TXE)) return; @@ -73,7 +72,7 @@ static void usart_tx_interrupt_handler_common( static size_t queue_remove(struct usart_config const *config, uint8_t *dest) { - return queue_remove_unit(config->consumer.queue, (void *) dest); + return queue_remove_unit(config->consumer.queue, (void *)dest); } static void usart_tx_interrupt_handler(struct usart_config const *config) @@ -107,11 +106,11 @@ struct usart_tx const usart_tx_interrupt = { #if defined(CONFIG_USART_HOST_COMMAND) -static void usart_host_command_tx_interrupt_handler( - struct usart_config const *config) +static void +usart_host_command_tx_interrupt_handler(struct usart_config const *config) { usart_tx_interrupt_handler_common(config, - &usart_host_command_tx_remove_data); + &usart_host_command_tx_remove_data); } struct usart_tx const usart_host_command_tx_interrupt = { diff --git a/chip/stm32/usb-stm32f0.c b/chip/stm32/usb-stm32f0.c index 08c0a17455..227842f549 100644 --- a/chip/stm32/usb-stm32f0.c +++ b/chip/stm32/usb-stm32f0.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/chip/stm32/usb-stm32f3.c b/chip/stm32/usb-stm32f3.c index 2376d00b41..eb48129e09 100644 --- a/chip/stm32/usb-stm32f3.c +++ b/chip/stm32/usb-stm32f3.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/chip/stm32/usb-stm32f3.h b/chip/stm32/usb-stm32f3.h index 196c43a53a..62921fe491 100644 --- a/chip/stm32/usb-stm32f3.h +++ b/chip/stm32/usb-stm32f3.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/chip/stm32/usb-stm32g4.c b/chip/stm32/usb-stm32g4.c index b4402f670d..acd758584b 100644 --- a/chip/stm32/usb-stm32g4.c +++ b/chip/stm32/usb-stm32g4.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/chip/stm32/usb-stm32l.c b/chip/stm32/usb-stm32l.c index bb9838531b..3780dfed10 100644 --- a/chip/stm32/usb-stm32l.c +++ b/chip/stm32/usb-stm32l.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/chip/stm32/usb-stm32l5.c b/chip/stm32/usb-stm32l5.c index 9eaa622815..a286ab488e 100644 --- a/chip/stm32/usb-stm32l5.c +++ b/chip/stm32/usb-stm32l5.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/stm32/usb-stream.c b/chip/stm32/usb-stream.c index 7429832f10..76f7fbd340 100644 --- a/chip/stm32/usb-stream.c +++ b/chip/stm32/usb-stream.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -28,19 +28,16 @@ static size_t rx_read(struct usb_stream_config const *config) if (count > queue_space(config->producer.queue)) return 0; - return queue_add_memcpy(config->producer.queue, - (void *) address, - count, + return queue_add_memcpy(config->producer.queue, (void *)address, count, memcpy_from_usbram); } static size_t tx_write(struct usb_stream_config const *config) { uintptr_t address = btable_ep[config->endpoint].tx_addr; - size_t count = queue_remove_memcpy(config->consumer.queue, - (void *) address, - config->tx_size, - memcpy_to_usbram); + size_t count = queue_remove_memcpy(config->consumer.queue, + (void *)address, config->tx_size, + memcpy_to_usbram); btable_ep[config->endpoint].tx_count = count; @@ -127,36 +124,33 @@ void usb_stream_event(struct usb_stream_config const *config, i = config->endpoint; - btable_ep[i].tx_addr = usb_sram_addr(config->tx_ram); + btable_ep[i].tx_addr = usb_sram_addr(config->tx_ram); btable_ep[i].tx_count = 0; - btable_ep[i].rx_addr = usb_sram_addr(config->rx_ram); + btable_ep[i].rx_addr = usb_sram_addr(config->rx_ram); btable_ep[i].rx_count = usb_ep_rx_size(config->rx_size); config->state->rx_waiting = 0; - STM32_USB_EP(i) = ((i << 0) | /* Endpoint Addr*/ - (2 << 4) | /* TX NAK */ - (0 << 9) | /* Bulk EP */ + STM32_USB_EP(i) = ((i << 0) | /* Endpoint Addr*/ + (2 << 4) | /* TX NAK */ + (0 << 9) | /* Bulk EP */ (rx_disabled(config) ? EP_RX_NAK : EP_RX_VALID)); } int usb_usart_interface(struct usb_stream_config const *config, - struct usart_config const *usart, - int interface, + struct usart_config const *usart, int interface, usb_uint *rx_buf, usb_uint *tx_buf) { struct usb_setup_packet req; usb_read_setup_packet(rx_buf, &req); - if (req.bmRequestType != (USB_DIR_OUT | - USB_TYPE_VENDOR | - USB_RECIP_INTERFACE)) + if (req.bmRequestType != + (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_INTERFACE)) return -1; - if (req.wIndex != interface || - req.wLength != 0) + if (req.wIndex != interface || req.wLength != 0) return -1; switch (req.bRequest) { diff --git a/chip/stm32/usb-stream.h b/chip/stm32/usb-stream.h index 915d8905cd..b22ee56620 100644 --- a/chip/stm32/usb-stream.h +++ b/chip/stm32/usb-stream.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -118,32 +118,25 @@ extern struct producer_ops const usb_stream_producer_ops; * BUILD_ASSERT(RX_QUEUE.unit_bytes == 1); * BUILD_ASSERT(TX_QUEUE.unit_bytes == 1); */ -#define USB_STREAM_CONFIG_FULL(NAME, \ - INTERFACE, \ - INTERFACE_CLASS, \ - INTERFACE_SUBCLASS, \ - INTERFACE_PROTOCOL, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE) \ - \ - BUILD_ASSERT(RX_SIZE <= USB_MAX_PACKET_SIZE); \ - BUILD_ASSERT(TX_SIZE <= USB_MAX_PACKET_SIZE); \ - BUILD_ASSERT(RX_SIZE > 0); \ - BUILD_ASSERT(TX_SIZE > 0); \ - BUILD_ASSERT((RX_SIZE < 64 && (RX_SIZE & 0x01) == 0) || \ - (RX_SIZE < 1024 && (RX_SIZE & 0x1f) == 0)); \ - BUILD_ASSERT((TX_SIZE < 64 && (TX_SIZE & 0x01) == 0) || \ - (TX_SIZE < 1024 && (TX_SIZE & 0x1f) == 0)); \ - \ - static usb_uint CONCAT2(NAME, _ep_rx_buffer)[RX_SIZE / 2] __usb_ram; \ - static usb_uint CONCAT2(NAME, _ep_tx_buffer)[TX_SIZE / 2] __usb_ram; \ - static struct usb_stream_state CONCAT2(NAME, _state); \ - static void CONCAT2(NAME, _deferred_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_)); \ +#define USB_STREAM_CONFIG_FULL(NAME, INTERFACE, INTERFACE_CLASS, \ + INTERFACE_SUBCLASS, INTERFACE_PROTOCOL, \ + INTERFACE_NAME, ENDPOINT, RX_SIZE, TX_SIZE, \ + RX_QUEUE, TX_QUEUE) \ + \ + BUILD_ASSERT(RX_SIZE <= USB_MAX_PACKET_SIZE); \ + BUILD_ASSERT(TX_SIZE <= USB_MAX_PACKET_SIZE); \ + BUILD_ASSERT(RX_SIZE > 0); \ + BUILD_ASSERT(TX_SIZE > 0); \ + BUILD_ASSERT((RX_SIZE < 64 && (RX_SIZE & 0x01) == 0) || \ + (RX_SIZE < 1024 && (RX_SIZE & 0x1f) == 0)); \ + BUILD_ASSERT((TX_SIZE < 64 && (TX_SIZE & 0x01) == 0) || \ + (TX_SIZE < 1024 && (TX_SIZE & 0x1f) == 0)); \ + \ + static usb_uint CONCAT2(NAME, _ep_rx_buffer)[RX_SIZE / 2] __usb_ram; \ + static usb_uint CONCAT2(NAME, _ep_tx_buffer)[TX_SIZE / 2] __usb_ram; \ + static struct usb_stream_state CONCAT2(NAME, _state); \ + static void CONCAT2(NAME, _deferred_)(void); \ + DECLARE_DEFERRED(CONCAT2(NAME, _deferred_)); \ struct usb_stream_config const NAME = { \ .state = &CONCAT2(NAME, _state), \ .endpoint = ENDPOINT, \ @@ -160,107 +153,80 @@ extern struct producer_ops const usb_stream_producer_ops; .queue = &RX_QUEUE, \ .ops = &usb_stream_producer_ops, \ }, \ - }; \ - const struct usb_interface_descriptor \ - USB_IFACE_DESC(INTERFACE) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 0, \ - .bNumEndpoints = 2, \ - .bInterfaceClass = INTERFACE_CLASS, \ - .bInterfaceSubClass = INTERFACE_SUBCLASS, \ - .bInterfaceProtocol = INTERFACE_PROTOCOL, \ - .iInterface = INTERFACE_NAME, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 0) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = 0x80 | ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk IN */, \ - .wMaxPacketSize = TX_SIZE, \ - .bInterval = 10, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 1) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk OUT */, \ - .wMaxPacketSize = RX_SIZE, \ - .bInterval = 0, \ - }; \ - static void CONCAT2(NAME, _ep_tx)(void) \ - { \ - usb_stream_tx(&NAME); \ - } \ - static void CONCAT2(NAME, _ep_rx)(void) \ - { \ - usb_stream_rx(&NAME); \ - } \ - static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt) \ - { \ - usb_stream_event(&NAME, evt); \ - } \ - USB_DECLARE_EP(ENDPOINT, \ - CONCAT2(NAME, _ep_tx), \ - CONCAT2(NAME, _ep_rx), \ - CONCAT2(NAME, _ep_event)); \ - static void CONCAT2(NAME, _deferred_)(void) \ - { usb_stream_deferred(&NAME); } + }; \ + const struct usb_interface_descriptor USB_IFACE_DESC(INTERFACE) = { \ + .bLength = USB_DT_INTERFACE_SIZE, \ + .bDescriptorType = USB_DT_INTERFACE, \ + .bInterfaceNumber = INTERFACE, \ + .bAlternateSetting = 0, \ + .bNumEndpoints = 2, \ + .bInterfaceClass = INTERFACE_CLASS, \ + .bInterfaceSubClass = INTERFACE_SUBCLASS, \ + .bInterfaceProtocol = INTERFACE_PROTOCOL, \ + .iInterface = INTERFACE_NAME, \ + }; \ + const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 0) = { \ + .bLength = USB_DT_ENDPOINT_SIZE, \ + .bDescriptorType = USB_DT_ENDPOINT, \ + .bEndpointAddress = 0x80 | ENDPOINT, \ + .bmAttributes = 0x02 /* Bulk IN */, \ + .wMaxPacketSize = TX_SIZE, \ + .bInterval = 10, \ + }; \ + const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 1) = { \ + .bLength = USB_DT_ENDPOINT_SIZE, \ + .bDescriptorType = USB_DT_ENDPOINT, \ + .bEndpointAddress = ENDPOINT, \ + .bmAttributes = 0x02 /* Bulk OUT */, \ + .wMaxPacketSize = RX_SIZE, \ + .bInterval = 0, \ + }; \ + static void CONCAT2(NAME, _ep_tx)(void) \ + { \ + usb_stream_tx(&NAME); \ + } \ + static void CONCAT2(NAME, _ep_rx)(void) \ + { \ + usb_stream_rx(&NAME); \ + } \ + static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt) \ + { \ + usb_stream_event(&NAME, evt); \ + } \ + USB_DECLARE_EP(ENDPOINT, CONCAT2(NAME, _ep_tx), CONCAT2(NAME, _ep_rx), \ + CONCAT2(NAME, _ep_event)); \ + static void CONCAT2(NAME, _deferred_)(void) \ + { \ + usb_stream_deferred(&NAME); \ + } /* This is a short version for declaring Google serial endpoints */ -#define USB_STREAM_CONFIG(NAME, \ - INTERFACE, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE) \ - USB_STREAM_CONFIG_FULL(NAME, \ - INTERFACE, \ - USB_CLASS_VENDOR_SPEC, \ - USB_SUBCLASS_GOOGLE_SERIAL, \ - USB_PROTOCOL_GOOGLE_SERIAL, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE) +#define USB_STREAM_CONFIG(NAME, INTERFACE, INTERFACE_NAME, ENDPOINT, RX_SIZE, \ + TX_SIZE, RX_QUEUE, TX_QUEUE) \ + USB_STREAM_CONFIG_FULL(NAME, INTERFACE, USB_CLASS_VENDOR_SPEC, \ + USB_SUBCLASS_GOOGLE_SERIAL, \ + USB_PROTOCOL_GOOGLE_SERIAL, INTERFACE_NAME, \ + ENDPOINT, RX_SIZE, TX_SIZE, RX_QUEUE, TX_QUEUE) /* Declare a utility interface for setting parity/baud. */ -#define USB_USART_IFACE(NAME, INTERFACE, USART_CFG) \ - static int CONCAT2(NAME, _interface_)(usb_uint *rx_buf, \ - usb_uint *tx_buf) \ - { return usb_usart_interface(&NAME, &USART_CFG, INTERFACE, \ - rx_buf, tx_buf); } \ - USB_DECLARE_IFACE(INTERFACE, \ - CONCAT2(NAME, _interface_)) +#define USB_USART_IFACE(NAME, INTERFACE, USART_CFG) \ + static int CONCAT2(NAME, _interface_)(usb_uint * rx_buf, \ + usb_uint * tx_buf) \ + { \ + return usb_usart_interface(&NAME, &USART_CFG, INTERFACE, \ + rx_buf, tx_buf); \ + } \ + USB_DECLARE_IFACE(INTERFACE, CONCAT2(NAME, _interface_)) /* This is a medium version for declaring Google serial endpoints */ -#define USB_STREAM_CONFIG_USART_IFACE(NAME, \ - INTERFACE, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE, \ - USART_CFG) \ - USB_STREAM_CONFIG_FULL(NAME, \ - INTERFACE, \ - USB_CLASS_VENDOR_SPEC, \ - USB_SUBCLASS_GOOGLE_SERIAL, \ - USB_PROTOCOL_GOOGLE_SERIAL, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE); \ +#define USB_STREAM_CONFIG_USART_IFACE(NAME, INTERFACE, INTERFACE_NAME, \ + ENDPOINT, RX_SIZE, TX_SIZE, RX_QUEUE, \ + TX_QUEUE, USART_CFG) \ + USB_STREAM_CONFIG_FULL(NAME, INTERFACE, USB_CLASS_VENDOR_SPEC, \ + USB_SUBCLASS_GOOGLE_SERIAL, \ + USB_PROTOCOL_GOOGLE_SERIAL, INTERFACE_NAME, \ + ENDPOINT, RX_SIZE, TX_SIZE, RX_QUEUE, \ + TX_QUEUE); \ USB_USART_IFACE(NAME, INTERFACE, USART_CFG) /* @@ -285,8 +251,8 @@ enum usb_usart { #define USB_USART_BAUD_MULTIPLIER 100 int usb_usart_interface(struct usb_stream_config const *config, - struct usart_config const *usart, - int interface, usb_uint *rx_buf, usb_uint *tx_buf); + struct usart_config const *usart, int interface, + usb_uint *rx_buf, usb_uint *tx_buf); /* * These functions are used by the trampoline functions defined above to diff --git a/chip/stm32/usb.c b/chip/stm32/usb.c index a1f60e8906..1c621a32b3 100644 --- a/chip/stm32/usb.c +++ b/chip/stm32/usb.c @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -21,7 +21,7 @@ #include "usb_hw.h" /* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) #ifdef CONFIG_USB_BOS /* v2.10 (vs 2.00) BOS Descriptor provided */ @@ -73,11 +73,11 @@ const struct usb_config_descriptor USB_CONF_DESC(conf) = { .bConfigurationValue = 1, .iConfiguration = USB_STR_VERSION, .bmAttributes = 0x80 /* Reserved bit */ -#ifdef CONFIG_USB_SELF_POWERED /* bus or self powered */ - | 0x40 +#ifdef CONFIG_USB_SELF_POWERED /* bus or self powered */ + | 0x40 #endif #ifdef CONFIG_USB_REMOTE_WAKEUP - | 0x20 + | 0x20 #endif , .bMaxPower = (CONFIG_USB_MAXPOWER_MA / 2), @@ -85,8 +85,7 @@ const struct usb_config_descriptor USB_CONF_DESC(conf) = { const uint8_t usb_string_desc[] = { 4, /* Descriptor size */ - USB_DT_STRING, - 0x09, 0x04 /* LangID = 0x0409: U.S. English */ + USB_DT_STRING, 0x09, 0x04 /* LangID = 0x0409: U.S. English */ }; #ifdef CONFIG_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR @@ -95,7 +94,8 @@ const uint8_t usb_string_desc[] = { * descriptor is used by Windows OS to know to request a Windows Compatible ID * OS Descriptor so that Windows will load the proper WINUSB driver. */ -const void *const usb_ms_os_string_descriptor = {USB_MS_STRING_DESC("MSFT100")}; +const void *const usb_ms_os_string_descriptor = { USB_MS_STRING_DESC( + "MSFT100") }; /* * Extended Compat ID OS Feature descriptor. This descriptor is used by Windows @@ -125,7 +125,7 @@ struct stm32_endpoint btable_ep[USB_EP_COUNT] __aligned(8) __usb_btable; static usb_uint ep0_buf_tx[USB_MAX_PACKET_SIZE / 2] __usb_ram; static usb_uint ep0_buf_rx[USB_MAX_PACKET_SIZE / 2] __usb_ram; -#define EP0_BUF_TX_SRAM_ADDR ((void *) usb_sram_addr(ep0_buf_tx)) +#define EP0_BUF_TX_SRAM_ADDR ((void *)usb_sram_addr(ep0_buf_tx)) static int set_addr; /* remaining size of descriptor data to transfer */ @@ -142,10 +142,10 @@ static int remote_wakeup_enabled; void usb_read_setup_packet(usb_uint *buffer, struct usb_setup_packet *packet) { packet->bmRequestType = buffer[0] & 0xff; - packet->bRequest = buffer[0] >> 8; - packet->wValue = buffer[1]; - packet->wIndex = buffer[2]; - packet->wLength = buffer[3]; + packet->bRequest = buffer[0] >> 8; + packet->wValue = buffer[1]; + packet->wIndex = buffer[2]; + packet->wLength = buffer[3]; } struct usb_descriptor_patch { @@ -155,8 +155,8 @@ struct usb_descriptor_patch { static struct usb_descriptor_patch desc_patches[USB_DESC_PATCH_COUNT]; -void set_descriptor_patch(enum usb_desc_patch_type type, - const void *address, uint16_t data) +void set_descriptor_patch(enum usb_desc_patch_type type, const void *address, + uint16_t data) { desc_patches[type].address = address; desc_patches[type].data = data; @@ -176,7 +176,8 @@ void *memcpy_to_usbram_ep0_patch(const void *src, size_t n) continue; memcpy_to_usbram((void *)(usb_sram_addr(ep0_buf_tx) + offset), - &desc_patches[i].data, sizeof(desc_patches[i].data)); + &desc_patches[i].data, + sizeof(desc_patches[i].data)); } return ret; @@ -246,7 +247,7 @@ static void ep0_rx(void) #ifdef CONFIG_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR if (b_req == USB_MS_STRING_DESC_VENDOR_CODE && - w_index == USB_MS_EXT_COMPATIBLE_ID_INDEX) { + w_index == USB_MS_EXT_COMPATIBLE_ID_INDEX) { ep0_send_descriptor((uint8_t *)&winusb_desc, winusb_desc.dwLength, 0); return; @@ -310,8 +311,9 @@ static void ep0_rx(void) default: /* unhandled descriptor */ goto unknown_req; } - ep0_send_descriptor(desc, len, type == USB_DT_CONFIGURATION ? - USB_DESC_SIZE : 0); + ep0_send_descriptor( + desc, len, + type == USB_DT_CONFIGURATION ? USB_DESC_SIZE : 0); } else if (req == (USB_DIR_IN | (USB_REQ_GET_STATUS << 8))) { uint16_t data = 0; /* Get status */ @@ -325,14 +327,14 @@ static void ep0_rx(void) memcpy_to_usbram(EP0_BUF_TX_SRAM_ADDR, (void *)&data, 2); btable_ep[0].tx_count = 2; STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, - EP_STATUS_OUT /*null OUT transaction */); + EP_STATUS_OUT /*null OUT transaction */); } else if ((req & 0xff) == USB_DIR_OUT) { switch (req >> 8) { case USB_REQ_SET_FEATURE: case USB_REQ_CLEAR_FEATURE: #ifdef CONFIG_USB_REMOTE_WAKEUP if (ep0_buf_rx[1] == - USB_REQ_FEATURE_DEVICE_REMOTE_WAKEUP) { + USB_REQ_FEATURE_DEVICE_REMOTE_WAKEUP) { remote_wakeup_enabled = ((req >> 8) == USB_REQ_SET_FEATURE); btable_ep[0].tx_count = 0; @@ -407,13 +409,12 @@ static void ep0_event(enum usb_ep_event evt) if (evt != USB_EVENT_RESET) return; - STM32_USB_EP(0) = BIT(9) /* control EP */ | - (2 << 4) /* TX NAK */ | + STM32_USB_EP(0) = BIT(9) /* control EP */ | (2 << 4) /* TX NAK */ | (3 << 12) /* RX VALID */; btable_ep[0].tx_addr = usb_sram_addr(ep0_buf_tx); btable_ep[0].rx_addr = usb_sram_addr(ep0_buf_rx); - btable_ep[0].rx_count = 0x8000 | ((USB_MAX_PACKET_SIZE/32-1) << 10); + btable_ep[0].rx_count = 0x8000 | ((USB_MAX_PACKET_SIZE / 32 - 1) << 10); btable_ep[0].tx_count = 0; } USB_DECLARE_EP(0, ep0_tx, ep0_rx, ep0_event); @@ -473,8 +474,8 @@ static volatile int sof_received; static void usb_resume_deferred(void) { - uint32_t state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK) - >> STM32_USB_FNR_RXDP_RXDM_SHIFT; + uint32_t state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK) >> + STM32_USB_FNR_RXDP_RXDM_SHIFT; CPRINTF("RSMd %d %04x %d\n", state, STM32_USB_CNTR, sof_received); if (sof_received == 0 && (state == 2 || state == 3)) @@ -496,8 +497,8 @@ static void usb_resume(void) /* USB is in use again */ disable_sleep(SLEEP_MASK_USB_DEVICE); - state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK) - >> STM32_USB_FNR_RXDP_RXDM_SHIFT; + state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK) >> + STM32_USB_FNR_RXDP_RXDM_SHIFT; CPRINTF("RSM %d %04x\n", state, STM32_USB_CNTR); @@ -534,8 +535,7 @@ static volatile int usb_wake_done = 1; */ static volatile int esof_count; -__attribute__((weak)) -void board_usb_wake(void) +__attribute__((weak)) void board_usb_wake(void) { /* Side-band USB wake, do nothing by default. */ } @@ -598,8 +598,8 @@ void usb_wake(void) /* STM32_USB_CNTR can also be updated from interrupt context. */ interrupt_disable(); - STM32_USB_CNTR |= STM32_USB_CNTR_RESUME | - STM32_USB_CNTR_ESOFM | STM32_USB_CNTR_SOFM; + STM32_USB_CNTR |= STM32_USB_CNTR_RESUME | STM32_USB_CNTR_ESOFM | + STM32_USB_CNTR_SOFM; interrupt_enable(); /* Try side-band wake as well. */ @@ -654,8 +654,8 @@ static void usb_interrupt_handle_wake(uint16_t status) STM32_USB_CNTR &= ~STM32_USB_CNTR_RESUME; /* Then count down until state is resumed. */ - state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK) - >> STM32_USB_FNR_RXDP_RXDM_SHIFT; + state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK) >> + STM32_USB_FNR_RXDP_RXDM_SHIFT; /* * state 2, or receiving an SOF, means resume @@ -670,13 +670,13 @@ static void usb_interrupt_handle_wake(uint16_t status) STM32_USB_CNTR &= ~STM32_USB_CNTR_ESOFM; usb_wake_done = 1; if (!good) { - CPRINTF("wake error: cnt=%d state=%d\n", - esof_count, state); + CPRINTF("wake error: cnt=%d state=%d\n", esof_count, + state); usb_suspend(); return; } - CPRINTF("RSMOK%d %d\n", -esof_count, state); + CPRINTF("RSMOK%d %d\n", -esof_count, state); for (ep = 1; ep < USB_EP_COUNT; ep++) usb_ep_event[ep](USB_EVENT_DEVICE_RESUME); @@ -703,7 +703,7 @@ static void usb_interrupt(void) #ifdef CONFIG_USB_REMOTE_WAKEUP if (status & (STM32_USB_ISTR_ESOF | STM32_USB_ISTR_SOF) && - !usb_wake_done) + !usb_wake_done) usb_interrupt_handle_wake(status); #endif @@ -759,12 +759,10 @@ void usb_init(void) /* Enable interrupt handlers */ task_enable_irq(STM32_IRQ_USB_LP); /* set interrupts mask : reset/correct transfer/errors */ - STM32_USB_CNTR = STM32_USB_CNTR_CTRM | - STM32_USB_CNTR_PMAOVRM | + STM32_USB_CNTR = STM32_USB_CNTR_CTRM | STM32_USB_CNTR_PMAOVRM | STM32_USB_CNTR_ERRM | #ifdef CONFIG_USB_SUSPEND - STM32_USB_CNTR_WKUPM | - STM32_USB_CNTR_SUSPM | + STM32_USB_CNTR_WKUPM | STM32_USB_CNTR_SUSPM | #endif STM32_USB_CNTR_RESETM; @@ -809,10 +807,10 @@ int usb_is_enabled(void) void *memcpy_to_usbram(void *dest, const void *src, size_t n) { - int unaligned = (((uintptr_t) dest) & 1); - usb_uint *d = &__usb_ram_start[((uintptr_t) dest) / 2]; - uint8_t *s = (uint8_t *) src; - int i; + int unaligned = (((uintptr_t)dest) & 1); + usb_uint *d = &__usb_ram_start[((uintptr_t)dest) / 2]; + uint8_t *s = (uint8_t *)src; + int i; /* * Handle unaligned leading byte via read/modify/write. @@ -839,10 +837,10 @@ void *memcpy_to_usbram(void *dest, const void *src, size_t n) void *memcpy_from_usbram(void *dest, const void *src, size_t n) { - int unaligned = (((uintptr_t) src) & 1); - usb_uint const *s = &__usb_ram_start[((uintptr_t) src) / 2]; - uint8_t *d = (uint8_t *) dest; - int i; + int unaligned = (((uintptr_t)src) & 1); + usb_uint const *s = &__usb_ram_start[((uintptr_t)src) / 2]; + uint8_t *d = (uint8_t *)dest; + int i; if (unaligned && n) { *d = *s >> 8; @@ -923,7 +921,7 @@ static int usb_save_serial(const char *serialno) return rv; } -static int command_serialno(int argc, char **argv) +static int command_serialno(int argc, const char **argv) { struct usb_string_desc *sd = usb_serialno_desc; char buf[CONFIG_SERIALNO_LEN]; @@ -931,12 +929,10 @@ static int command_serialno(int argc, char **argv) int i; if (argc != 1) { - if ((strcasecmp(argv[1], "set") == 0) && - (argc == 3)) { + if ((strcasecmp(argv[1], "set") == 0) && (argc == 3)) { ccprintf("Saving serial number\n"); rv = usb_save_serial(argv[2]); - } else if ((strcasecmp(argv[1], "load") == 0) && - (argc == 2)) { + } else if ((strcasecmp(argv[1], "load") == 0) && (argc == 2)) { ccprintf("Loading serial number\n"); rv = usb_load_serial(); } else @@ -949,11 +945,10 @@ static int command_serialno(int argc, char **argv) return rv; } -DECLARE_CONSOLE_COMMAND(serialno, command_serialno, - "load/set [value]", - "Read and write USB serial number"); +DECLARE_CONSOLE_COMMAND(serialno, command_serialno, "load/set [value]", + "Read and write USB serial number"); -#endif /* CONFIG_USB_SERIALNO */ +#endif /* CONFIG_USB_SERIALNO */ #ifdef CONFIG_MAC_ADDR @@ -980,18 +975,16 @@ static int usb_save_mac_addr(const char *mac_addr) } } -static int command_macaddr(int argc, char **argv) +static int command_macaddr(int argc, const char **argv) { - const char* buf; + const char *buf; int rv = EC_SUCCESS; if (argc != 1) { - if ((strcasecmp(argv[1], "set") == 0) && - (argc == 3)) { + if ((strcasecmp(argv[1], "set") == 0) && (argc == 3)) { ccprintf("Saving MAC address\n"); rv = usb_save_mac_addr(argv[2]); - } else if ((strcasecmp(argv[1], "load") == 0) && - (argc == 2)) { + } else if ((strcasecmp(argv[1], "load") == 0) && (argc == 2)) { ccprintf("Loading MAC address\n"); } else { return EC_ERROR_INVAL; @@ -1006,8 +999,7 @@ static int command_macaddr(int argc, char **argv) return rv; } -DECLARE_CONSOLE_COMMAND(macaddr, command_macaddr, - "load/set [value]", - "Read and write MAC address"); +DECLARE_CONSOLE_COMMAND(macaddr, command_macaddr, "load/set [value]", + "Read and write MAC address"); -#endif /* CONFIG_MAC_ADDR */ +#endif /* CONFIG_MAC_ADDR */ diff --git a/chip/stm32/usb_console.c b/chip/stm32/usb_console.c index b5666c8fbf..fdadc243c1 100644 --- a/chip/stm32/usb_console.c +++ b/chip/stm32/usb_console.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -18,11 +18,11 @@ #include "usb_hw.h" /* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) #define USB_CONSOLE_TIMEOUT_US (30 * MSEC) -static struct queue const tx_q = QUEUE_NULL(CONFIG_USB_CONSOLE_TX_BUF_SIZE, - uint8_t); +static struct queue const tx_q = + QUEUE_NULL(CONFIG_USB_CONSOLE_TX_BUF_SIZE, uint8_t); static struct queue const rx_q = QUEUE_NULL(USB_MAX_PACKET_SIZE, uint8_t); static int last_tx_ok = 1; @@ -33,31 +33,31 @@ static int is_readonly; /* USB-Serial descriptors */ const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_CONSOLE) = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = USB_IFACE_CONSOLE, - .bAlternateSetting = 0, - .bNumEndpoints = 2, - .bInterfaceClass = USB_CLASS_VENDOR_SPEC, + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = USB_IFACE_CONSOLE, + .bAlternateSetting = 0, + .bNumEndpoints = 2, + .bInterfaceClass = USB_CLASS_VENDOR_SPEC, .bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SERIAL, .bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SERIAL, - .iInterface = USB_STR_CONSOLE_NAME, + .iInterface = USB_STR_CONSOLE_NAME, }; const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 0) = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0x80 | USB_EP_CONSOLE, - .bmAttributes = 0x02 /* Bulk IN */, - .wMaxPacketSize = USB_MAX_PACKET_SIZE, - .bInterval = 10 + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0x80 | USB_EP_CONSOLE, + .bmAttributes = 0x02 /* Bulk IN */, + .wMaxPacketSize = USB_MAX_PACKET_SIZE, + .bInterval = 10 }; const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 1) = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = USB_EP_CONSOLE, - .bmAttributes = 0x02 /* Bulk OUT */, - .wMaxPacketSize = USB_MAX_PACKET_SIZE, - .bInterval = 0 + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_EP_CONSOLE, + .bmAttributes = 0x02 /* Bulk OUT */, + .wMaxPacketSize = USB_MAX_PACKET_SIZE, + .bInterval = 0 }; static usb_uint ep_buf_tx[USB_MAX_PACKET_SIZE / 2] __usb_ram; @@ -81,9 +81,8 @@ static void con_ep_rx(void) for (i = 0; i < (btable_ep[USB_EP_CONSOLE].rx_count & RX_COUNT_MASK); i++) { - int val = ((i & 1) ? - (ep_buf_rx[i >> 1] >> 8) : - (ep_buf_rx[i >> 1] & 0xff)); + int val = ((i & 1) ? (ep_buf_rx[i >> 1] >> 8) : + (ep_buf_rx[i >> 1] & 0xff)); QUEUE_ADD_UNITS(&rx_q, &val, 1); } @@ -100,18 +99,18 @@ static void ep_event(enum usb_ep_event evt) if (evt != USB_EVENT_RESET) return; - btable_ep[USB_EP_CONSOLE].tx_addr = usb_sram_addr(ep_buf_tx); + btable_ep[USB_EP_CONSOLE].tx_addr = usb_sram_addr(ep_buf_tx); btable_ep[USB_EP_CONSOLE].tx_count = 0; - btable_ep[USB_EP_CONSOLE].rx_addr = usb_sram_addr(ep_buf_rx); + btable_ep[USB_EP_CONSOLE].rx_addr = usb_sram_addr(ep_buf_rx); btable_ep[USB_EP_CONSOLE].rx_count = 0x8000 | ((USB_MAX_PACKET_SIZE / 32 - 1) << 10); - STM32_USB_EP(USB_EP_CONSOLE) = (USB_EP_CONSOLE | /* Endpoint Addr */ - (2 << 4) | /* TX NAK */ - (0 << 9) | /* Bulk EP */ - (is_readonly ? EP_RX_NAK - : EP_RX_VALID)); + STM32_USB_EP(USB_EP_CONSOLE) = + (USB_EP_CONSOLE | /* Endpoint Addr */ + (2 << 4) | /* TX NAK */ + (0 << 9) | /* Bulk EP */ + (is_readonly ? EP_RX_NAK : EP_RX_VALID)); is_reset = 1; } @@ -201,9 +200,9 @@ static void tx_fifo_handler(void) break; if (!(count & 1)) - buf[count/2] = val; + buf[count / 2] = val; else - buf[count/2] |= val << 8; + buf[count / 2] |= val << 8; count++; } diff --git a/chip/stm32/usb_dfu_runtime.c b/chip/stm32/usb_dfu_runtime.c index 7626faec8e..92e152078b 100644 --- a/chip/stm32/usb_dfu_runtime.c +++ b/chip/stm32/usb_dfu_runtime.c @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -23,15 +23,15 @@ const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_DFU) = { }; /* DFU Functional Descriptor. */ -const struct usb_runtime_dfu_functional_desc USB_CUSTOM_DESC_VAR(USB_IFACE_DFU, - dfu, dfu_func_desc) = { - .bLength = USB_DFU_RUNTIME_DESC_SIZE, - .bDescriptorType = USB_DFU_RUNTIME_DESC_FUNCTIONAL, - .bmAttributes = USB_DFU_RUNTIME_DESC_ATTRS, - .wDetachTimeOut = USB_DFU_RUNTIME_DESC_DETACH_TIMEOUT, - .wTransferSize = USB_DFU_RUNTIME_DESC_TRANSFER_SIZE, - .bcdDFUVersion = USB_DFU_RUNTIME_DESC_DFU_VERSION, -}; +const struct usb_runtime_dfu_functional_desc + USB_CUSTOM_DESC_VAR(USB_IFACE_DFU, dfu, dfu_func_desc) = { + .bLength = USB_DFU_RUNTIME_DESC_SIZE, + .bDescriptorType = USB_DFU_RUNTIME_DESC_FUNCTIONAL, + .bmAttributes = USB_DFU_RUNTIME_DESC_ATTRS, + .wDetachTimeOut = USB_DFU_RUNTIME_DESC_DETACH_TIMEOUT, + .wTransferSize = USB_DFU_RUNTIME_DESC_TRANSFER_SIZE, + .bcdDFUVersion = USB_DFU_RUNTIME_DESC_DFU_VERSION, + }; static int dfu_runtime_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx) { @@ -40,21 +40,21 @@ static int dfu_runtime_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx) usb_read_setup_packet(ep0_buf_rx, &packet); btable_ep[0].tx_count = 0; if ((packet.bmRequestType == - (USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE)) && - (packet.bRequest == USB_REQ_SET_INTERFACE)) { + (USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE)) && + (packet.bRequest == USB_REQ_SET_INTERFACE)) { /* ACK the change alternative mode request. */ STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0); return 0; } else if ((packet.bmRequestType == - (USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE)) && - (packet.bRequest == USB_DFU_RUNTIME_REQ_DETACH)) { + (USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE)) && + (packet.bRequest == USB_DFU_RUNTIME_REQ_DETACH)) { /* Host is requesting a jump from application to DFU mode. */ STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0); return dfu_bootmanager_enter_dfu(); } else if (packet.bmRequestType == - (USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE)) { + (USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE)) { if (packet.bRequest == USB_DFU_RUNTIME_REQ_GET_STATUS) { /* Return the Get Status response. */ @@ -63,8 +63,8 @@ static int dfu_runtime_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx) .bState = USB_DFU_RUNTIME_STATE_APP_IDLE, }; - memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx), - &response, sizeof(response)); + memcpy_to_usbram((void *)usb_sram_addr(ep0_buf_tx), + &response, sizeof(response)); btable_ep[0].tx_count = sizeof(response); STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0); return 0; @@ -76,8 +76,8 @@ static int dfu_runtime_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx) .bState = USB_DFU_RUNTIME_STATE_APP_IDLE, }; - memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx), - &response, sizeof(response)); + memcpy_to_usbram((void *)usb_sram_addr(ep0_buf_tx), + &response, sizeof(response)); btable_ep[0].tx_count = sizeof(response); STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0); return 0; diff --git a/chip/stm32/usb_dfu_runtime.h b/chip/stm32/usb_dfu_runtime.h index 08781d77b0..8b0bbbe219 100644 --- a/chip/stm32/usb_dfu_runtime.h +++ b/chip/stm32/usb_dfu_runtime.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,47 +12,46 @@ * https://www.usb.org/sites/default/files/DFU_1.1.pdf */ -#define USB_DFU_RUNTIME_SUBCLASS 0x01 -#define USB_DFU_RUNTIME_PROTOCOL 0x01 +#define USB_DFU_RUNTIME_SUBCLASS 0x01 +#define USB_DFU_RUNTIME_PROTOCOL 0x01 -#define USB_DFU_RUNTIME_DESC_ATTR_CAN_DOWNLOAD BIT(0) -#define USB_DFU_RUNTIME_DESC_ATTR_CAN_UPLOAD BIT(1) -#define USB_DFU_RUNTIME_DESC_ATTR_MANIFEST_TOLERANT BIT(2) -#define USB_DFU_RUNTIME_DESC_ATTR_WILL_DETACH BIT(3) +#define USB_DFU_RUNTIME_DESC_ATTR_CAN_DOWNLOAD BIT(0) +#define USB_DFU_RUNTIME_DESC_ATTR_CAN_UPLOAD BIT(1) +#define USB_DFU_RUNTIME_DESC_ATTR_MANIFEST_TOLERANT BIT(2) +#define USB_DFU_RUNTIME_DESC_ATTR_WILL_DETACH BIT(3) -#define USB_DFU_RUNTIME_DESC_ATTRS \ +#define USB_DFU_RUNTIME_DESC_ATTRS \ (USB_DFU_RUNTIME_DESC_ATTR_CAN_DOWNLOAD | \ - USB_DFU_RUNTIME_DESC_ATTR_CAN_UPLOAD | \ - USB_DFU_RUNTIME_DESC_ATTR_WILL_DETACH) + USB_DFU_RUNTIME_DESC_ATTR_CAN_UPLOAD | \ + USB_DFU_RUNTIME_DESC_ATTR_WILL_DETACH) -#define USB_DFU_RUNTIME_DESC_SIZE 9 -#define USB_DFU_RUNTIME_DESC_FUNCTIONAL 0x21 -#define USB_DFU_RUNTIME_DESC_DETACH_TIMEOUT 0xffff -#define USB_DFU_RUNTIME_DESC_TRANSFER_SIZE 64 -#define USB_DFU_RUNTIME_DESC_DFU_VERSION 0x0022 +#define USB_DFU_RUNTIME_DESC_SIZE 9 +#define USB_DFU_RUNTIME_DESC_FUNCTIONAL 0x21 +#define USB_DFU_RUNTIME_DESC_DETACH_TIMEOUT 0xffff +#define USB_DFU_RUNTIME_DESC_TRANSFER_SIZE 64 +#define USB_DFU_RUNTIME_DESC_DFU_VERSION 0x0022 /* DFU states */ -#define USB_DFU_RUNTIME_STATE_APP_IDLE 0 -#define USB_DFU_RUNTIME_STATE_APP_DETACH 1 +#define USB_DFU_RUNTIME_STATE_APP_IDLE 0 +#define USB_DFU_RUNTIME_STATE_APP_DETACH 1 /* DFU status */ -#define USB_DFU_RUNTIME_STATUS_OK 0 +#define USB_DFU_RUNTIME_STATUS_OK 0 /* DFU Request types */ -#define USB_DFU_RUNTIME_REQ_DETACH 0 -#define USB_DFU_RUNTIME_REQ_DNLOAD 1 -#define USB_DFU_RUNTIME_REQ_UPLOAD 2 -#define USB_DFU_RUNTIME_REQ_GET_STATUS 3 -#define USB_DFU_RUNTIME_REQ_CLR_STATUS 4 -#define USB_DFU_RUNTIME_REQ_GET_STATE 5 -#define USB_DFU_RUNTIME_REQ_ABORT 6 - +#define USB_DFU_RUNTIME_REQ_DETACH 0 +#define USB_DFU_RUNTIME_REQ_DNLOAD 1 +#define USB_DFU_RUNTIME_REQ_UPLOAD 2 +#define USB_DFU_RUNTIME_REQ_GET_STATUS 3 +#define USB_DFU_RUNTIME_REQ_CLR_STATUS 4 +#define USB_DFU_RUNTIME_REQ_GET_STATE 5 +#define USB_DFU_RUNTIME_REQ_ABORT 6 /* DFU Functional Descriptor */ struct usb_runtime_dfu_functional_desc { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bmAttributes; + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bmAttributes; uint16_t wDetachTimeOut; uint16_t wTransferSize; uint16_t bcdDFUVersion; diff --git a/chip/stm32/usb_dwc.c b/chip/stm32/usb_dwc.c index 0028806432..67f89a5222 100644 --- a/chip/stm32/usb_dwc.c +++ b/chip/stm32/usb_dwc.c @@ -1,8 +1,9 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ +#include "builtin/assert.h" #include "clock.h" #include "common.h" #include "config.h" @@ -20,19 +21,17 @@ #include "usb_descriptor.h" #include "watchdog.h" - /****************************************************************************/ /* Debug output */ /* Console output macro */ -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USB, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) /* TODO: Something unexpected happened. Figure out how to report & fix it. */ -#define report_error(val) \ - CPRINTS("Unhandled USB event at %s line %d: 0x%x", \ - __FILE__, __LINE__, val) - +#define report_error(val) \ + CPRINTS("Unhandled USB event at %s line %d: 0x%x", __FILE__, __LINE__, \ + val) /****************************************************************************/ /* Standard USB stuff */ @@ -49,7 +48,7 @@ #endif #ifndef CONFIG_USB_BCD_DEV -#define CONFIG_USB_BCD_DEV 0x0100 /* 1.00 */ +#define CONFIG_USB_BCD_DEV 0x0100 /* 1.00 */ #endif #ifndef CONFIG_USB_SERIALNO @@ -58,7 +57,6 @@ static int usb_load_serial(void); #endif - /* USB Standard Device Descriptor */ static const struct usb_device_descriptor dev_desc = { .bLength = USB_DT_DEVICE_SIZE, @@ -81,25 +79,24 @@ static const struct usb_device_descriptor dev_desc = { const struct usb_config_descriptor USB_CONF_DESC(conf) = { .bLength = USB_DT_CONFIG_SIZE, .bDescriptorType = USB_DT_CONFIGURATION, - .wTotalLength = 0x0BAD, /* number of returned bytes, set at runtime */ + .wTotalLength = 0x0BAD, /* number of returned bytes, set at runtime */ .bNumInterfaces = USB_IFACE_COUNT, - .bConfigurationValue = 1, /* Caution: hard-coded value */ + .bConfigurationValue = 1, /* Caution: hard-coded value */ .iConfiguration = USB_STR_VERSION, .bmAttributes = 0x80 /* Reserved bit */ -#ifdef CONFIG_USB_SELF_POWERED /* bus or self powered */ - | 0x40 +#ifdef CONFIG_USB_SELF_POWERED /* bus or self powered */ + | 0x40 #endif #ifdef CONFIG_USB_REMOTE_WAKEUP - | 0x20 + | 0x20 #endif , .bMaxPower = (CONFIG_USB_MAXPOWER_MA / 2), }; const uint8_t usb_string_desc[] = { - 4, /* Descriptor size */ - USB_DT_STRING, - 0x09, 0x04 /* LangID = 0x0409: U.S. English */ + 4, /* Descriptor size */ + USB_DT_STRING, 0x09, 0x04 /* LangID = 0x0409: U.S. English */ }; /****************************************************************************/ @@ -113,7 +110,7 @@ static enum { } what_am_i_doing; #ifdef DEBUG_ME -static const char * const wat[3] = { +static const char *const wat[3] = { [WAITING_FOR_SETUP_PACKET] = "wait_for_setup", [DATA_STAGE_IN] = "data_in", [NO_DATA_STAGE] = "no_data", @@ -182,7 +179,6 @@ static enum { } device_state; static uint8_t configuration_value; - /* True if the HW Rx/OUT FIFO is currently listening. */ int rx_ep_is_active(uint32_t ep_num) { @@ -326,10 +322,9 @@ void usb_epN_rx(uint32_t ep_num) /* Bytes received decrement DOEPTSIZ XFERSIZE */ if (GR_USB_DOEPINT(ep_num) & DOEPINT_XFERCOMPL) { if (ep->out_expected > 0) { - ep->out_pending = - ep->out_expected - - (GR_USB_DOEPTSIZ(ep_num) & - GC_USB_DOEPTSIZ1_XFERSIZE_MASK); + ep->out_pending = ep->out_expected - + (GR_USB_DOEPTSIZ(ep_num) & + GC_USB_DOEPTSIZ1_XFERSIZE_MASK); } else { CPRINTF("usb_ep%d_rx: unexpected RX DOEPTSIZ %08x\n", ep_num, GR_USB_DOEPTSIZ(ep_num)); @@ -350,25 +345,22 @@ void usb_epN_rx(uint32_t ep_num) void epN_reset(uint32_t ep_num) { GR_USB_DOEPCTL(ep_num) = DXEPCTL_MPS(USB_MAX_PACKET_SIZE) | - DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_BULK; + DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_BULK; GR_USB_DIEPCTL(ep_num) = DXEPCTL_MPS(USB_MAX_PACKET_SIZE) | - DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_BULK | - DXEPCTL_TXFNUM(ep_num); - GR_USB_DAINTMSK |= DAINT_INEP(ep_num) | - DAINT_OUTEP(ep_num); + DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_BULK | + DXEPCTL_TXFNUM(ep_num); + GR_USB_DAINTMSK |= DAINT_INEP(ep_num) | DAINT_OUTEP(ep_num); } - /****************************************************************************** * Internal and EP0 functions. */ - static void flush_all_fifos(void) { /* Flush all FIFOs according to Section 2.1.1.2 */ - GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH - | GRSTCTL_RXFFLSH; + GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | + GRSTCTL_RXFFLSH; while (GR_USB_GRSTCTL & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) ; } @@ -390,7 +382,6 @@ int send_in_packet(uint32_t ep_num) GR_USB_DIEPTSIZ(0) |= DXEPTSIZ_XFERSIZE(len); GR_USB_DIEPDMA(0) = (uint32_t)ep->in_data; - /* We're sending this much. */ ep->in_pending -= len; ep->in_packets -= 1; @@ -400,7 +391,6 @@ int send_in_packet(uint32_t ep_num) return len; } - /* Load the EP0 IN FIFO buffer with some data (zero-length works too). Returns * len, or negative on error. */ @@ -418,7 +408,7 @@ int initialize_in_transfer(const void *source, uint32_t len) #else /* HS OTG port requires an external phy to support HS */ ASSERT(!((usb->phy_type == USB_PHY_INTERNAL) && - (usb->speed == USB_SPEED_HS))); + (usb->speed == USB_SPEED_HS))); ASSERT(usb->irq == STM32_IRQ_OTG_HS); #endif @@ -435,7 +425,7 @@ int initialize_in_transfer(const void *source, uint32_t len) /* We will send as many packets as necessary, including a final * packet of < USB_MAX_PACKET_SIZE (maybe zero length) */ - ep->in_packets = (len + USB_MAX_PACKET_SIZE)/USB_MAX_PACKET_SIZE; + ep->in_packets = (len + USB_MAX_PACKET_SIZE) / USB_MAX_PACKET_SIZE; ep->in_pending = len; send_in_packet(0); @@ -495,8 +485,8 @@ static void expect_data_phase_in(enum table_case tc) /* Send the reply (data phase in) */ if (tc == TABLE_CASE_SETUP) - GR_USB_DIEPCTL(0) |= DXEPCTL_USBACTEP | - DXEPCTL_CNAK | DXEPCTL_EPENA; + GR_USB_DIEPCTL(0) |= DXEPCTL_USBACTEP | DXEPCTL_CNAK | + DXEPCTL_EPENA; else GR_USB_DIEPCTL(0) |= DXEPCTL_EPENA; @@ -508,7 +498,6 @@ static void expect_data_phase_in(enum table_case tc) /* Get an interrupt when either IN or OUT arrives */ GR_USB_DAINTMSK |= (DAINT_OUTEP(0) | DAINT_INEP(0)); - } static void expect_data_phase_out(enum table_case tc) @@ -524,12 +513,12 @@ static void expect_status_phase_in(enum table_case tc) what_am_i_doing = NO_DATA_STAGE; /* Expect a zero-length IN for the Status phase */ - (void) initialize_in_transfer(0, 0); + (void)initialize_in_transfer(0, 0); /* Blindly following instructions here, too. */ if (tc == TABLE_CASE_SETUP) - GR_USB_DIEPCTL(0) |= DXEPCTL_USBACTEP - | DXEPCTL_CNAK | DXEPCTL_EPENA; + GR_USB_DIEPCTL(0) |= DXEPCTL_USBACTEP | DXEPCTL_CNAK | + DXEPCTL_EPENA; else GR_USB_DIEPCTL(0) |= DXEPCTL_EPENA; @@ -549,7 +538,7 @@ static int handle_setup_with_in_stage(enum table_case tc, const void *data = 0; uint32_t len = 0; int ugly_hack = 0; - static const uint16_t zero; /* == 0 */ + static const uint16_t zero; /* == 0 */ switch (req->bRequest) { case USB_REQ_GET_DESCRIPTOR: { @@ -564,7 +553,7 @@ static int handle_setup_with_in_stage(enum table_case tc, case USB_DT_CONFIGURATION: data = __usb_desc; len = USB_DESC_SIZE; - ugly_hack = 1; /* see below */ + ugly_hack = 1; /* see below */ break; #ifdef CONFIG_USB_BOS case USB_DT_BOS: @@ -657,7 +646,7 @@ static int handle_setup_with_in_stage(enum table_case tc, /* Handle a Setup that comes with additional data for us. */ static int handle_setup_with_out_stage(enum table_case tc, - struct usb_setup_packet *req) + struct usb_setup_packet *req) { /* TODO: We don't support any of these. We should. */ report_error(-1); @@ -720,7 +709,7 @@ static int handle_setup_with_no_data_stage(enum table_case tc, configuration_value = req->wValue; device_state = DS_ADDRESS; break; - case 1: /* Caution: Only one config descriptor TODAY */ + case 1: /* Caution: Only one config descriptor TODAY */ /* TODO: All endpoints set to DATA0 toggle state */ configuration_value = req->wValue; device_state = DS_CONFIGURED; @@ -756,7 +745,7 @@ static void handle_setup(enum table_case tc) (struct usb_setup_packet *)ep->out_databuffer; int data_phase_in = req->bmRequestType & USB_DIR_IN; int data_phase_out = !data_phase_in && req->wLength; - int bytes = -1; /* default is to stall */ + int bytes = -1; /* default is to stall */ if (0 == (req->bmRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))) { /* Standard Device requests */ @@ -900,20 +889,20 @@ static void ep0_interrupt(uint32_t intr_on_out, uint32_t intr_on_in) * We support up to 3 control EPs, no periodic IN EPs, up to 16 TX EPs. Max * data packet size is 64 bytes. Total SPRAM available is 1024 slots. */ -#define MAX_CONTROL_EPS 3 -#define MAX_NORMAL_EPS 16 -#define FIFO_RAM_DEPTH 1024 +#define MAX_CONTROL_EPS 3 +#define MAX_NORMAL_EPS 16 +#define FIFO_RAM_DEPTH 1024 /* * Device RX FIFO size is thus: * (4 * 3 + 6) + 2 * ((64 / 4) + 1) + (2 * 16) + 1 == 85 */ -#define RXFIFO_SIZE ((4 * MAX_CONTROL_EPS + 6) + \ - 2 * ((USB_MAX_PACKET_SIZE / 4) + 1) + \ - (2 * MAX_NORMAL_EPS) + 1) +#define RXFIFO_SIZE \ + ((4 * MAX_CONTROL_EPS + 6) + 2 * ((USB_MAX_PACKET_SIZE / 4) + 1) + \ + (2 * MAX_NORMAL_EPS) + 1) /* * Device TX FIFO size is 2 * (64 / 4) == 32 for each IN EP (Page 46). */ -#define TXFIFO_SIZE (2 * (USB_MAX_PACKET_SIZE / 4)) +#define TXFIFO_SIZE (2 * (USB_MAX_PACKET_SIZE / 4)) /* * We need 4 slots per endpoint direction for endpoint status stuff (Table 2-1, * unconfigurable). @@ -925,20 +914,19 @@ static void ep0_interrupt(uint32_t intr_on_out, uint32_t intr_on_in) BUILD_ASSERT(RXFIFO_SIZE + TXFIFO_SIZE * MAX_NORMAL_EPS + EP_STATUS_SIZE < FIFO_RAM_DEPTH); - /* Now put those constants into the correct registers */ static void setup_data_fifos(void) { int i; /* Programmer's Guide, p31 */ - GR_USB_GRXFSIZ = RXFIFO_SIZE; /* RXFIFO */ + GR_USB_GRXFSIZ = RXFIFO_SIZE; /* RXFIFO */ GR_USB_GNPTXFSIZ = (TXFIFO_SIZE << 16) | RXFIFO_SIZE; /* TXFIFO 0 */ /* TXFIFO 1..15 */ for (i = 1; i < MAX_NORMAL_EPS; i++) - GR_USB_DIEPTXF(i) = ((TXFIFO_SIZE << 16) | - (RXFIFO_SIZE + i * TXFIFO_SIZE)); + GR_USB_DIEPTXF(i) = + ((TXFIFO_SIZE << 16) | (RXFIFO_SIZE + i * TXFIFO_SIZE)); /* * TODO: The Programmer's Guide is confusing about when or whether to @@ -953,10 +941,10 @@ static void setup_data_fifos(void) */ /* Flush all FIFOs according to Section 2.1.1.2 */ - GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH - | GRSTCTL_RXFFLSH; + GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | + GRSTCTL_RXFFLSH; while (GR_USB_GRSTCTL & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) - ; /* TODO: timeout 100ms */ + ; /* TODO: timeout 100ms */ } static void usb_init_endpoints(void) @@ -998,7 +986,6 @@ static void usb_enumdone(void) GR_USB_DCTL |= DCTL_CGOUTNAK; } - static void usb_interrupt(void) { uint32_t status = GR_USB_GINTSTS & GR_USB_GINTMSK; @@ -1027,10 +1014,10 @@ static void usb_interrupt(void) * let it know which direction(s) had an interrupt. */ if (daint & (DAINT_OUTEP(0) | DAINT_INEP(0))) { - uint32_t intr_on_out = (oepint && - (daint & DAINT_OUTEP(0))); - uint32_t intr_on_in = (iepint && - (daint & DAINT_INEP(0))); + uint32_t intr_on_out = + (oepint && (daint & DAINT_OUTEP(0))); + uint32_t intr_on_in = + (iepint && (daint & DAINT_INEP(0))); ep0_interrupt(intr_on_out, intr_on_in); } @@ -1103,8 +1090,8 @@ void usb_reset_init_phy(void) if (usb->phy_type == USB_PHY_ULPI) { GR_USB_GCCFG &= ~GCCFG_PWRDWN; - GR_USB_GUSBCFG &= ~(GUSBCFG_TSDPS | - GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL); + GR_USB_GUSBCFG &= + ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL); GR_USB_GUSBCFG &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI); /* No suspend */ GR_USB_GUSBCFG |= GUSBCFG_ULPICSM | GUSBCFG_ULPIAR; @@ -1168,11 +1155,11 @@ void usb_init(void) * GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK) * | DCFG_DEVSPD_HSULPI; */ - GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK) - | DCFG_DEVSPD_FSULPI; + GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK) | + DCFG_DEVSPD_FSULPI; } else { - GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK) - | DCFG_DEVSPD_FS48; + GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK) | + DCFG_DEVSPD_FS48; } GR_USB_DCFG |= DCFG_NZLSOHSK; @@ -1190,10 +1177,11 @@ void usb_init(void) GR_USB_GAHBCFG |= GAHBCFG_TXFELVL | GAHBCFG_PTXFELVL; /* Device only, no SRP */ - GR_USB_GUSBCFG |= GUSBCFG_FDMOD - | GUSBCFG_TOUTCAL(7) - /* FIXME: Magic number! 14 is for 15MHz! Use 9 for 30MHz */ - | GUSBCFG_USBTRDTIM(14); + GR_USB_GUSBCFG |= GUSBCFG_FDMOD | + GUSBCFG_TOUTCAL(7) + /* FIXME: Magic number! 14 is for 15MHz! Use 9 for + 30MHz */ + | GUSBCFG_USBTRDTIM(14); /* Be in disconnected state until we are ready */ usb_disconnect(); @@ -1225,15 +1213,15 @@ void usb_init(void) if (usb->dma_en) { GR_USB_DTHRCTL = DTHRCTL_TXTHRLEN_6 | DTHRCTL_RXTHRLEN_6; - GR_USB_DTHRCTL |= DTHRCTL_RXTHREN | DTHRCTL_ISOTHREN - | DTHRCTL_NONISOTHREN; + GR_USB_DTHRCTL |= DTHRCTL_RXTHREN | DTHRCTL_ISOTHREN | + DTHRCTL_NONISOTHREN; i = GR_USB_DTHRCTL; } GR_USB_GINTSTS = 0xFFFFFFFF; - GR_USB_GAHBCFG |= GAHBCFG_GLB_INTR_EN | GAHBCFG_TXFELVL - | GAHBCFG_PTXFELVL; + GR_USB_GAHBCFG |= GAHBCFG_GLB_INTR_EN | GAHBCFG_TXFELVL | + GAHBCFG_PTXFELVL; if (!(usb->dma_en)) GR_USB_GINTMSK |= GINTMSK(RXFLVL); @@ -1241,7 +1229,7 @@ void usb_init(void) /* Unmask some endpoint interrupt causes */ GR_USB_DIEPMSK = DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK; GR_USB_DOEPMSK = DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK | - DOEPMSK_SETUPMSK; + DOEPMSK_SETUPMSK; /* Enable interrupt handlers */ task_enable_irq(usb->irq); @@ -1253,7 +1241,7 @@ void usb_init(void) /* Initialization events */ GINTMSK(USBRST) | GINTMSK(ENUMDONE) | /* Reset detected while suspended. Need to wake up. */ - GINTMSK(RESETDET) | /* TODO: Do we need this? */ + GINTMSK(RESETDET) | /* TODO: Do we need this? */ /* Idle, Suspend detected. Should go to sleep. */ GINTMSK(ERLYSUSP) | GINTMSK(USBSUSP); @@ -1314,7 +1302,7 @@ static void usb_info(void) } } -static int command_usb(int argc, char **argv) +static int command_usb(int argc, const char **argv) { if (argc > 1) { if (!strcasecmp("on", argv[1])) @@ -1328,8 +1316,7 @@ static int command_usb(int argc, char **argv) return EC_ERROR_PARAM1; } -DECLARE_CONSOLE_COMMAND(usb, command_usb, - "[on|off|info]", +DECLARE_CONSOLE_COMMAND(usb, command_usb, "[on|off|info]", "Get/set the USB connection state and PHY selection"); #ifdef CONFIG_USB_SERIALNO @@ -1391,7 +1378,7 @@ static int usb_save_serial(const char *serialno) return rv; } -static int command_serialno(int argc, char **argv) +static int command_serialno(int argc, const char **argv) { struct usb_string_desc *sd = usb_serialno_desc; char buf[CONFIG_SERIALNO_LEN]; @@ -1399,12 +1386,10 @@ static int command_serialno(int argc, char **argv) int i; if (argc != 1) { - if ((strcasecmp(argv[1], "set") == 0) && - (argc == 3)) { + if ((strcasecmp(argv[1], "set") == 0) && (argc == 3)) { ccprintf("Saving serial number\n"); rv = usb_save_serial(argv[2]); - } else if ((strcasecmp(argv[1], "load") == 0) && - (argc == 2)) { + } else if ((strcasecmp(argv[1], "load") == 0) && (argc == 2)) { ccprintf("Loading serial number\n"); rv = usb_load_serial(); } else @@ -1417,7 +1402,6 @@ static int command_serialno(int argc, char **argv) return rv; } -DECLARE_CONSOLE_COMMAND(serialno, command_serialno, - "load/set [value]", - "Read and write USB serial number"); -#endif /* CONFIG_USB_SERIALNO */ +DECLARE_CONSOLE_COMMAND(serialno, command_serialno, "load/set [value]", + "Read and write USB serial number"); +#endif /* CONFIG_USB_SERIALNO */ diff --git a/chip/stm32/usb_dwc_console.c b/chip/stm32/usb_dwc_console.c index 0d1340fb83..fd66db7380 100644 --- a/chip/stm32/usb_dwc_console.c +++ b/chip/stm32/usb_dwc_console.c @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,7 +17,7 @@ #include "usb_hw.h" /* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) #define USB_CONSOLE_TIMEOUT_US (30 * MSEC) static int last_tx_ok = 1; @@ -28,31 +28,31 @@ static int is_readonly; /* USB-Serial descriptors */ const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_CONSOLE) = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = USB_IFACE_CONSOLE, - .bAlternateSetting = 0, - .bNumEndpoints = 2, - .bInterfaceClass = USB_CLASS_VENDOR_SPEC, - .bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SERIAL, - .bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SERIAL, - .iInterface = USB_STR_CONSOLE_NAME, + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = USB_IFACE_CONSOLE, + .bAlternateSetting = 0, + .bNumEndpoints = 2, + .bInterfaceClass = USB_CLASS_VENDOR_SPEC, + .bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SERIAL, + .bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SERIAL, + .iInterface = USB_STR_CONSOLE_NAME, }; const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 0) = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0x80 | USB_EP_CONSOLE, - .bmAttributes = 0x02 /* Bulk IN */, - .wMaxPacketSize = USB_MAX_PACKET_SIZE, - .bInterval = 10, + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0x80 | USB_EP_CONSOLE, + .bmAttributes = 0x02 /* Bulk IN */, + .wMaxPacketSize = USB_MAX_PACKET_SIZE, + .bInterval = 10, }; const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 1) = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = USB_EP_CONSOLE, - .bmAttributes = 0x02 /* Bulk OUT */, - .wMaxPacketSize = USB_MAX_PACKET_SIZE, - .bInterval = 0 + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_EP_CONSOLE, + .bmAttributes = 0x02 /* Bulk OUT */, + .wMaxPacketSize = USB_MAX_PACKET_SIZE, + .bInterval = 0 }; static uint8_t ep_buf_tx[USB_MAX_PACKET_SIZE]; @@ -61,7 +61,6 @@ static uint8_t ep_buf_rx[USB_MAX_PACKET_SIZE]; static struct queue const tx_q = QUEUE_NULL(256, uint8_t); static struct queue const rx_q = QUEUE_NULL(USB_MAX_PACKET_SIZE, uint8_t); - struct dwc_usb_ep ep_console_ctl = { .max_packet = USB_MAX_PACKET_SIZE, .tx_fifo = USB_EP_CONSOLE, @@ -76,8 +75,6 @@ struct dwc_usb_ep ep_console_ctl = { .in_databuffer_max = sizeof(ep_buf_rx), }; - - /* Let the USB HW IN-to-host FIFO transmit some bytes */ static void usb_enable_tx(int len) { @@ -162,9 +159,8 @@ static void con_ep_rx(void) /* Bytes received decrement DOEPTSIZ XFERSIZE */ if (GR_USB_DOEPINT(USB_EP_CONSOLE) & DOEPINT_XFERCOMPL) { ep->out_pending = - ep->max_packet - - (GR_USB_DOEPTSIZ(USB_EP_CONSOLE) & - GC_USB_DOEPTSIZ1_XFERSIZE_MASK); + ep->max_packet - (GR_USB_DOEPTSIZ(USB_EP_CONSOLE) & + GC_USB_DOEPTSIZ1_XFERSIZE_MASK); } /* Wake up the Rx FIFO handler */ @@ -193,8 +189,8 @@ static void tx_fifo_handler(void) if (!tx_fifo_is_ready()) return; - count = QUEUE_REMOVE_UNITS(&tx_q, - ep->in_databuffer, USB_MAX_PACKET_SIZE); + count = QUEUE_REMOVE_UNITS(&tx_q, ep->in_databuffer, + USB_MAX_PACKET_SIZE); if (count) usb_enable_tx(count); } @@ -232,7 +228,6 @@ static void ep_event(enum usb_ep_event evt) usb_enable_rx(USB_MAX_PACKET_SIZE); } - USB_DECLARE_EP(USB_EP_CONSOLE, con_ep_tx, con_ep_rx, ep_event); static int usb_wait_console(void) @@ -274,8 +269,7 @@ static int usb_wait_console(void) } static int __tx_char(void *context, int c) { - struct queue *state = - (struct queue *) context; + struct queue *state = (struct queue *)context; if (c == '\n' && __tx_char(state, '\r')) return 1; @@ -308,7 +302,7 @@ int usb_puts(const char *outstr) if (is_readonly) return EC_SUCCESS; - ret = usb_wait_console(); + ret = usb_wait_console(); if (ret) return ret; diff --git a/chip/stm32/usb_dwc_console.h b/chip/stm32/usb_dwc_console.h index ab2206d359..f0a0732c7d 100644 --- a/chip/stm32/usb_dwc_console.h +++ b/chip/stm32/usb_dwc_console.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,4 +10,4 @@ extern struct dwc_usb_ep ep_console_ctl; -#endif /* __CHIP_STM32_USB_DWC_CONSOLE_H */ +#endif /* __CHIP_STM32_USB_DWC_CONSOLE_H */ diff --git a/chip/stm32/usb_dwc_hw.h b/chip/stm32/usb_dwc_hw.h index d1fe07cb87..ea87869257 100644 --- a/chip/stm32/usb_dwc_hw.h +++ b/chip/stm32/usb_dwc_hw.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -18,29 +18,27 @@ #define _EP_RX_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _rx_typecheck) #define _EP_EVENT_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _evt_typecheck) -#define USB_DECLARE_EP(num, tx_handler, rx_handler, evt_handler) \ - void _EP_TX_HANDLER(num)(void) \ - __attribute__ ((alias(STRINGIFY(tx_handler)))); \ - void _EP_RX_HANDLER(num)(void) \ - __attribute__ ((alias(STRINGIFY(rx_handler)))); \ - void _EP_EVENT_HANDLER(num)(enum usb_ep_event evt) \ - __attribute__ ((alias(STRINGIFY(evt_handler)))); \ - static __unused void \ - (*_EP_TX_HANDLER_TYPECHECK(num))(void) = tx_handler; \ - static __unused void \ - (*_EP_RX_HANDLER_TYPECHECK(num))(void) = rx_handler; \ - static __unused void \ - (*_EP_EVENT_HANDLER_TYPECHECK(num))(enum usb_ep_event evt)\ - = evt_handler +#define USB_DECLARE_EP(num, tx_handler, rx_handler, evt_handler) \ + void _EP_TX_HANDLER(num)(void) \ + __attribute__((alias(STRINGIFY(tx_handler)))); \ + void _EP_RX_HANDLER(num)(void) \ + __attribute__((alias(STRINGIFY(rx_handler)))); \ + void _EP_EVENT_HANDLER(num)(enum usb_ep_event evt) \ + __attribute__((alias(STRINGIFY(evt_handler)))); \ + static __unused void (*_EP_TX_HANDLER_TYPECHECK(num))(void) = \ + tx_handler; \ + static __unused void (*_EP_RX_HANDLER_TYPECHECK(num))(void) = \ + rx_handler; \ + static __unused void (*_EP_EVENT_HANDLER_TYPECHECK(num))( \ + enum usb_ep_event evt) = evt_handler /* Endpoint callbacks */ -extern void (*usb_ep_tx[]) (void); -extern void (*usb_ep_rx[]) (void); -extern void (*usb_ep_event[]) (enum usb_ep_event evt); +extern void (*usb_ep_tx[])(void); +extern void (*usb_ep_rx[])(void); +extern void (*usb_ep_event[])(enum usb_ep_event evt); struct usb_setup_packet; /* EP0 Interface handler callbacks */ -extern int (*usb_iface_request[]) (struct usb_setup_packet *req); - +extern int (*usb_iface_request[])(struct usb_setup_packet *req); /* True if the HW Rx/OUT FIFO is currently listening. */ int rx_ep_is_active(uint32_t ep_num); @@ -99,8 +97,8 @@ void epN_reset(uint32_t ep_num); * (and thus indicate error to the host). */ #define _IFACE_HANDLER(num) CONCAT3(iface_, num, _request) -#define USB_DECLARE_IFACE(num, handler) \ - int _IFACE_HANDLER(num)(struct usb_setup_packet *req) \ - __attribute__ ((alias(STRINGIFY(handler)))) +#define USB_DECLARE_IFACE(num, handler) \ + int _IFACE_HANDLER(num)(struct usb_setup_packet * req) \ + __attribute__((alias(STRINGIFY(handler)))) -#endif /* __CROS_EC_USB_DWC_HW_H */ +#endif /* __CROS_EC_USB_DWC_HW_H */ diff --git a/chip/stm32/usb_dwc_i2c.h b/chip/stm32/usb_dwc_i2c.h index e44002268a..6e6c72e22c 100644 --- a/chip/stm32/usb_dwc_i2c.h +++ b/chip/stm32/usb_dwc_i2c.h @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/stm32/usb_dwc_registers.h b/chip/stm32/usb_dwc_registers.h index faac9ca775..b5ada2ce65 100644 --- a/chip/stm32/usb_dwc_registers.h +++ b/chip/stm32/usb_dwc_registers.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -55,7479 +55,7467 @@ extern struct dwc_usb usb_ctl; * Added Alias Module Family Base Address to 0-instance Module Base Address * Simplify GBASE(mname) macro */ -#define GC_MODULE_OFFSET 0x10000 +#define GC_MODULE_OFFSET 0x10000 -#define GBASE(mname) \ - GC_ ## mname ## _BASE_ADDR -#define GOFFSET(mname, rname) \ - GC_ ## mname ## _ ## rname ## _OFFSET +#define GBASE(mname) GC_##mname##_BASE_ADDR +#define GOFFSET(mname, rname) GC_##mname##_##rname##_OFFSET -#define GREG8(mname, rname) \ - REG8(GBASE(mname) + GOFFSET(mname, rname)) -#define GREG32(mname, rname) \ - REG32(GBASE(mname) + GOFFSET(mname, rname)) +#define GREG8(mname, rname) REG8(GBASE(mname) + GOFFSET(mname, rname)) +#define GREG32(mname, rname) REG32(GBASE(mname) + GOFFSET(mname, rname)) #define GREG32_ADDR(mname, rname) \ REG32_ADDR(GBASE(mname) + GOFFSET(mname, rname)) #define GWRITE(mname, rname, value) (GREG32(mname, rname) = (value)) -#define GREAD(mname, rname) GREG32(mname, rname) +#define GREAD(mname, rname) GREG32(mname, rname) -#define GFIELD_MASK(mname, rname, fname) \ - GC_ ## mname ## _ ## rname ## _ ## fname ## _MASK +#define GFIELD_MASK(mname, rname, fname) GC_##mname##_##rname##_##fname##_MASK -#define GFIELD_LSB(mname, rname, fname) \ - GC_ ## mname ## _ ## rname ## _ ## fname ## _LSB +#define GFIELD_LSB(mname, rname, fname) GC_##mname##_##rname##_##fname##_LSB -#define GREAD_FIELD(mname, rname, fname) \ - ((GREG32(mname, rname) & GFIELD_MASK(mname, rname, fname)) \ - >> GFIELD_LSB(mname, rname, fname)) +#define GREAD_FIELD(mname, rname, fname) \ + ((GREG32(mname, rname) & GFIELD_MASK(mname, rname, fname)) >> \ + GFIELD_LSB(mname, rname, fname)) -#define GWRITE_FIELD(mname, rname, fname, fval) \ - (GREG32(mname, rname) = \ - ((GREG32(mname, rname) & (~GFIELD_MASK(mname, rname, fname))) | \ - (((fval) << GFIELD_LSB(mname, rname, fname)) & \ - GFIELD_MASK(mname, rname, fname)))) +#define GWRITE_FIELD(mname, rname, fname, fval) \ + (GREG32(mname, rname) = \ + ((GREG32(mname, rname) & \ + (~GFIELD_MASK(mname, rname, fname))) | \ + (((fval) << GFIELD_LSB(mname, rname, fname)) & \ + GFIELD_MASK(mname, rname, fname)))) - -#define GBASE_I(mname, i) (GBASE(mname) + i*GC_MODULE_OFFSET) +#define GBASE_I(mname, i) (GBASE(mname) + i * GC_MODULE_OFFSET) #define GREG32_I(mname, i, rname) \ - REG32(GBASE_I(mname, i) + GOFFSET(mname, rname)) + REG32(GBASE_I(mname, i) + GOFFSET(mname, rname)) #define GREG32_ADDR_I(mname, i, rname) \ - REG32_ADDR(GBASE_I(mname, i) + GOFFSET(mname, rname)) + REG32_ADDR(GBASE_I(mname, i) + GOFFSET(mname, rname)) #define GWRITE_I(mname, i, rname, value) (GREG32_I(mname, i, rname) = (value)) -#define GREAD_I(mname, i, rname) GREG32_I(mname, i, rname) +#define GREAD_I(mname, i, rname) GREG32_I(mname, i, rname) -#define GREAD_FIELD_I(mname, i, rname, fname) \ - ((GREG32_I(mname, i, rname) & GFIELD_MASK(mname, rname, fname)) \ - >> GFIELD_LSB(mname, rname, fname)) +#define GREAD_FIELD_I(mname, i, rname, fname) \ + ((GREG32_I(mname, i, rname) & GFIELD_MASK(mname, rname, fname)) >> \ + GFIELD_LSB(mname, rname, fname)) -#define GWRITE_FIELD_I(mname, i, rname, fname, fval) \ - (GREG32_I(mname, i, rname) = \ - ((GREG32_I(mname, i, rname) & (~GFIELD_MASK(mname, rname, fname))) | \ - (((fval) << GFIELD_LSB(mname, rname, fname)) & \ - GFIELD_MASK(mname, rname, fname)))) +#define GWRITE_FIELD_I(mname, i, rname, fname, fval) \ + (GREG32_I(mname, i, rname) = \ + ((GREG32_I(mname, i, rname) & \ + (~GFIELD_MASK(mname, rname, fname))) | \ + (((fval) << GFIELD_LSB(mname, rname, fname)) & \ + GFIELD_MASK(mname, rname, fname)))) /* Replace masked bits with val << lsb */ #define REG_WRITE_MLV(reg, mask, lsb, val) \ - (reg = ((reg & ~mask) | ((val << lsb) & mask))) - + (reg = ((reg & ~mask) | ((val << lsb) & mask))) /* USB device controller */ -#define GR_USB_REG(off) REG32(GC_USB_BASE_ADDR + (off)) -#define GR_USB_GOTGCTL GR_USB_REG(GC_USB_GOTGCTL_OFFSET) -#define GR_USB_GOTGINT GR_USB_REG(GC_USB_GOTGINT_OFFSET) -#define GR_USB_GAHBCFG GR_USB_REG(GC_USB_GAHBCFG_OFFSET) -#define GR_USB_GUSBCFG GR_USB_REG(GC_USB_GUSBCFG_OFFSET) -#define GR_USB_GRSTCTL GR_USB_REG(GC_USB_GRSTCTL_OFFSET) -#define GR_USB_GINTSTS GR_USB_REG(GC_USB_GINTSTS_OFFSET) -#define GINTSTS(bit) (1 << GC_USB_GINTSTS_ ## bit ## _LSB) -#define GR_USB_GINTMSK GR_USB_REG(GC_USB_GINTMSK_OFFSET) -#define GINTMSK(bit) (1 << GC_USB_GINTMSK_ ## bit ## MSK_LSB) -#define GR_USB_GRXSTSR GR_USB_REG(GC_USB_GRXSTSR_OFFSET) -#define GR_USB_GRXSTSP GR_USB_REG(GC_USB_GRXSTSP_OFFSET) -#define GR_USB_GRXFSIZ GR_USB_REG(GC_USB_GRXFSIZ_OFFSET) -#define GR_USB_GNPTXFSIZ GR_USB_REG(GC_USB_GNPTXFSIZ_OFFSET) +#define GR_USB_REG(off) REG32(GC_USB_BASE_ADDR + (off)) +#define GR_USB_GOTGCTL GR_USB_REG(GC_USB_GOTGCTL_OFFSET) +#define GR_USB_GOTGINT GR_USB_REG(GC_USB_GOTGINT_OFFSET) +#define GR_USB_GAHBCFG GR_USB_REG(GC_USB_GAHBCFG_OFFSET) +#define GR_USB_GUSBCFG GR_USB_REG(GC_USB_GUSBCFG_OFFSET) +#define GR_USB_GRSTCTL GR_USB_REG(GC_USB_GRSTCTL_OFFSET) +#define GR_USB_GINTSTS GR_USB_REG(GC_USB_GINTSTS_OFFSET) +#define GINTSTS(bit) (1 << GC_USB_GINTSTS_##bit##_LSB) +#define GR_USB_GINTMSK GR_USB_REG(GC_USB_GINTMSK_OFFSET) +#define GINTMSK(bit) (1 << GC_USB_GINTMSK_##bit##MSK_LSB) +#define GR_USB_GRXSTSR GR_USB_REG(GC_USB_GRXSTSR_OFFSET) +#define GR_USB_GRXSTSP GR_USB_REG(GC_USB_GRXSTSP_OFFSET) +#define GR_USB_GRXFSIZ GR_USB_REG(GC_USB_GRXFSIZ_OFFSET) +#define GR_USB_GNPTXFSIZ GR_USB_REG(GC_USB_GNPTXFSIZ_OFFSET) /*#define GR_USB_GGPIO GR_USB_REG(GC_USB_GGPIO_OFFSET)*/ -#define GR_USB_GCCFG GR_USB_REG(GC_USB_GCCFG_OFFSET) -#define GCCFG_VBDEN BIT(21) -#define GCCFG_PWRDWN BIT(16) -#define GR_USB_PCGCCTL GR_USB_REG(GC_USB_PCGCCTL_OFFSET) +#define GR_USB_GCCFG GR_USB_REG(GC_USB_GCCFG_OFFSET) +#define GCCFG_VBDEN BIT(21) +#define GCCFG_PWRDWN BIT(16) +#define GR_USB_PCGCCTL GR_USB_REG(GC_USB_PCGCCTL_OFFSET) -#define GR_USB_GSNPSID GR_USB_REG(GC_USB_GSNPSID_OFFSET) -#define GR_USB_GHWCFG1 GR_USB_REG(GC_USB_GHWCFG1_OFFSET) -#define GR_USB_GHWCFG2 GR_USB_REG(GC_USB_GHWCFG2_OFFSET) -#define GR_USB_GHWCFG3 GR_USB_REG(GC_USB_GHWCFG3_OFFSET) -#define GR_USB_GHWCFG4 GR_USB_REG(GC_USB_GHWCFG4_OFFSET) -#define GR_USB_GDFIFOCFG GR_USB_REG(GC_USB_GDFIFOCFG_OFFSET) -#define GR_USB_DIEPTXF(n) \ - GR_USB_REG(GC_USB_DIEPTXF1_OFFSET - 4 + (n)*4) -#define GR_USB_DCFG GR_USB_REG(GC_USB_DCFG_OFFSET) -#define GR_USB_DCTL GR_USB_REG(GC_USB_DCTL_OFFSET) -#define GR_USB_DSTS GR_USB_REG(GC_USB_DSTS_OFFSET) -#define GR_USB_DIEPMSK GR_USB_REG(GC_USB_DIEPMSK_OFFSET) -#define GR_USB_DOEPMSK GR_USB_REG(GC_USB_DOEPMSK_OFFSET) -#define GR_USB_DAINT GR_USB_REG(GC_USB_DAINT_OFFSET) -#define GR_USB_DAINTMSK GR_USB_REG(GC_USB_DAINTMSK_OFFSET) -#define DAINT_INEP(ep) (1 << (ep + GC_USB_DAINTMSK_INEPMSK0_LSB)) -#define DAINT_OUTEP(ep) \ - (1 << (ep + GC_USB_DAINTMSK_OUTEPMSK0_LSB)) -#define GR_USB_DTHRCTL GR_USB_REG(GC_USB_DTHRCTL_OFFSET) -#define DTHRCTL_TXTHRLEN_6 (0x40 << 2) -#define DTHRCTL_RXTHRLEN_6 (0x40 << 17) -#define DTHRCTL_RXTHREN BIT(16) -#define DTHRCTL_ISOTHREN BIT(1) -#define DTHRCTL_NONISOTHREN BIT(0) -#define GR_USB_DIEPEMPMSK GR_USB_REG(GC_USB_DIEPEMPMSK_OFFSET) +#define GR_USB_GSNPSID GR_USB_REG(GC_USB_GSNPSID_OFFSET) +#define GR_USB_GHWCFG1 GR_USB_REG(GC_USB_GHWCFG1_OFFSET) +#define GR_USB_GHWCFG2 GR_USB_REG(GC_USB_GHWCFG2_OFFSET) +#define GR_USB_GHWCFG3 GR_USB_REG(GC_USB_GHWCFG3_OFFSET) +#define GR_USB_GHWCFG4 GR_USB_REG(GC_USB_GHWCFG4_OFFSET) +#define GR_USB_GDFIFOCFG GR_USB_REG(GC_USB_GDFIFOCFG_OFFSET) +#define GR_USB_DIEPTXF(n) GR_USB_REG(GC_USB_DIEPTXF1_OFFSET - 4 + (n)*4) +#define GR_USB_DCFG GR_USB_REG(GC_USB_DCFG_OFFSET) +#define GR_USB_DCTL GR_USB_REG(GC_USB_DCTL_OFFSET) +#define GR_USB_DSTS GR_USB_REG(GC_USB_DSTS_OFFSET) +#define GR_USB_DIEPMSK GR_USB_REG(GC_USB_DIEPMSK_OFFSET) +#define GR_USB_DOEPMSK GR_USB_REG(GC_USB_DOEPMSK_OFFSET) +#define GR_USB_DAINT GR_USB_REG(GC_USB_DAINT_OFFSET) +#define GR_USB_DAINTMSK GR_USB_REG(GC_USB_DAINTMSK_OFFSET) +#define DAINT_INEP(ep) (1 << (ep + GC_USB_DAINTMSK_INEPMSK0_LSB)) +#define DAINT_OUTEP(ep) (1 << (ep + GC_USB_DAINTMSK_OUTEPMSK0_LSB)) +#define GR_USB_DTHRCTL GR_USB_REG(GC_USB_DTHRCTL_OFFSET) +#define DTHRCTL_TXTHRLEN_6 (0x40 << 2) +#define DTHRCTL_RXTHRLEN_6 (0x40 << 17) +#define DTHRCTL_RXTHREN BIT(16) +#define DTHRCTL_ISOTHREN BIT(1) +#define DTHRCTL_NONISOTHREN BIT(0) +#define GR_USB_DIEPEMPMSK GR_USB_REG(GC_USB_DIEPEMPMSK_OFFSET) -#define GR_USB_EPIREG(off, n) GR_USB_REG(0x900 + (n) * 0x20 + (off)) -#define GR_USB_EPOREG(off, n) GR_USB_REG(0xb00 + (n) * 0x20 + (off)) -#define GR_USB_DIEPCTL(n) GR_USB_EPIREG(0x00, n) -#define GR_USB_DIEPINT(n) GR_USB_EPIREG(0x08, n) -#define GR_USB_DIEPTSIZ(n) GR_USB_EPIREG(0x10, n) -#define GR_USB_DIEPDMA(n) GR_USB_EPIREG(0x14, n) -#define GR_USB_DTXFSTS(n) GR_USB_EPIREG(0x18, n) -#define GR_USB_DIEPDMAB(n) GR_USB_EPIREG(0x1c, n) -#define GR_USB_DOEPCTL(n) GR_USB_EPOREG(0x00, n) -#define GR_USB_DOEPINT(n) GR_USB_EPOREG(0x08, n) -#define GR_USB_DOEPTSIZ(n) GR_USB_EPOREG(0x10, n) -#define GR_USB_DOEPDMA(n) GR_USB_EPOREG(0x14, n) -#define GR_USB_DOEPDMAB(n) GR_USB_EPOREG(0x1c, n) +#define GR_USB_EPIREG(off, n) GR_USB_REG(0x900 + (n)*0x20 + (off)) +#define GR_USB_EPOREG(off, n) GR_USB_REG(0xb00 + (n)*0x20 + (off)) +#define GR_USB_DIEPCTL(n) GR_USB_EPIREG(0x00, n) +#define GR_USB_DIEPINT(n) GR_USB_EPIREG(0x08, n) +#define GR_USB_DIEPTSIZ(n) GR_USB_EPIREG(0x10, n) +#define GR_USB_DIEPDMA(n) GR_USB_EPIREG(0x14, n) +#define GR_USB_DTXFSTS(n) GR_USB_EPIREG(0x18, n) +#define GR_USB_DIEPDMAB(n) GR_USB_EPIREG(0x1c, n) +#define GR_USB_DOEPCTL(n) GR_USB_EPOREG(0x00, n) +#define GR_USB_DOEPINT(n) GR_USB_EPOREG(0x08, n) +#define GR_USB_DOEPTSIZ(n) GR_USB_EPOREG(0x10, n) +#define GR_USB_DOEPDMA(n) GR_USB_EPOREG(0x14, n) +#define GR_USB_DOEPDMAB(n) GR_USB_EPOREG(0x1c, n) -#define GOTGCTL_BVALOEN BIT(GC_USB_GOTGCTL_BVALIDOVEN_LSB) -#define GOTGCTL_BVALOVAL BIT(7) +#define GOTGCTL_BVALOEN BIT(GC_USB_GOTGCTL_BVALIDOVEN_LSB) +#define GOTGCTL_BVALOVAL BIT(7) /* Bit 5 */ -#define GAHBCFG_DMA_EN BIT(GC_USB_GAHBCFG_DMAEN_LSB) +#define GAHBCFG_DMA_EN BIT(GC_USB_GAHBCFG_DMAEN_LSB) /* Bit 1 */ -#define GAHBCFG_GLB_INTR_EN BIT(GC_USB_GAHBCFG_GLBLINTRMSK_LSB) +#define GAHBCFG_GLB_INTR_EN BIT(GC_USB_GAHBCFG_GLBLINTRMSK_LSB) /* HS Burst Len */ -#define GAHBCFG_HBSTLEN_INCR4 (3 << GC_USB_GAHBCFG_HBSTLEN_LSB) +#define GAHBCFG_HBSTLEN_INCR4 (3 << GC_USB_GAHBCFG_HBSTLEN_LSB) /* Bit 7 */ -#define GAHBCFG_NP_TXF_EMP_LVL (1 << GC_USB_GAHBCFG_NPTXFEMPLVL_LSB) -#define GAHBCFG_TXFELVL GAHBCFG_NP_TXF_EMP_LVL -#define GAHBCFG_PTXFELVL BIT(8) +#define GAHBCFG_NP_TXF_EMP_LVL (1 << GC_USB_GAHBCFG_NPTXFEMPLVL_LSB) +#define GAHBCFG_TXFELVL GAHBCFG_NP_TXF_EMP_LVL +#define GAHBCFG_PTXFELVL BIT(8) -#define GUSBCFG_TOUTCAL(n) (((n) << GC_USB_GUSBCFG_TOUTCAL_LSB) \ - & GC_USB_GUSBCFG_TOUTCAL_MASK) -#define GUSBCFG_USBTRDTIM(n) (((n) << GC_USB_GUSBCFG_USBTRDTIM_LSB) \ - & GC_USB_GUSBCFG_USBTRDTIM_MASK) +#define GUSBCFG_TOUTCAL(n) \ + (((n) << GC_USB_GUSBCFG_TOUTCAL_LSB) & GC_USB_GUSBCFG_TOUTCAL_MASK) +#define GUSBCFG_USBTRDTIM(n) \ + (((n) << GC_USB_GUSBCFG_USBTRDTIM_LSB) & GC_USB_GUSBCFG_USBTRDTIM_MASK) /* Force device mode */ -#define GUSBCFG_FDMOD BIT(GC_USB_GUSBCFG_FDMOD_LSB) -#define GUSBCFG_PHYSEL BIT(6) -#define GUSBCFG_SRPCAP BIT(8) -#define GUSBCFG_HNPCAP BIT(9) -#define GUSBCFG_ULPIFSLS BIT(17) -#define GUSBCFG_ULPIAR BIT(18) -#define GUSBCFG_ULPICSM BIT(19) -#define GUSBCFG_ULPIEVBUSD BIT(20) -#define GUSBCFG_ULPIEVBUSI BIT(21) -#define GUSBCFG_TSDPS BIT(22) -#define GUSBCFG_PCCI BIT(23) -#define GUSBCFG_PTCI BIT(24) -#define GUSBCFG_ULPIIPD BIT(25) -#define GUSBCFG_TSDPS BIT(22) - +#define GUSBCFG_FDMOD BIT(GC_USB_GUSBCFG_FDMOD_LSB) +#define GUSBCFG_PHYSEL BIT(6) +#define GUSBCFG_SRPCAP BIT(8) +#define GUSBCFG_HNPCAP BIT(9) +#define GUSBCFG_ULPIFSLS BIT(17) +#define GUSBCFG_ULPIAR BIT(18) +#define GUSBCFG_ULPICSM BIT(19) +#define GUSBCFG_ULPIEVBUSD BIT(20) +#define GUSBCFG_ULPIEVBUSI BIT(21) +#define GUSBCFG_TSDPS BIT(22) +#define GUSBCFG_PCCI BIT(23) +#define GUSBCFG_PTCI BIT(24) +#define GUSBCFG_ULPIIPD BIT(25) +#define GUSBCFG_TSDPS BIT(22) -#define GRSTCTL_CSFTRST BIT(GC_USB_GRSTCTL_CSFTRST_LSB) -#define GRSTCTL_AHBIDLE BIT(GC_USB_GRSTCTL_AHBIDLE_LSB) -#define GRSTCTL_TXFFLSH BIT(GC_USB_GRSTCTL_TXFFLSH_LSB) -#define GRSTCTL_RXFFLSH BIT(GC_USB_GRSTCTL_RXFFLSH_LSB) -#define GRSTCTL_TXFNUM(n) \ +#define GRSTCTL_CSFTRST BIT(GC_USB_GRSTCTL_CSFTRST_LSB) +#define GRSTCTL_AHBIDLE BIT(GC_USB_GRSTCTL_AHBIDLE_LSB) +#define GRSTCTL_TXFFLSH BIT(GC_USB_GRSTCTL_TXFFLSH_LSB) +#define GRSTCTL_RXFFLSH BIT(GC_USB_GRSTCTL_RXFFLSH_LSB) +#define GRSTCTL_TXFNUM(n) \ (((n) << GC_USB_GRSTCTL_TXFNUM_LSB) & GC_USB_GRSTCTL_TXFNUM_MASK) -#define DCFG_DEVSPD_HSULPI (0 << GC_USB_DCFG_DEVSPD_LSB) -#define DCFG_DEVSPD_FSULPI BIT(GC_USB_DCFG_DEVSPD_LSB) -#define DCFG_DEVSPD_FS48 (3 << GC_USB_DCFG_DEVSPD_LSB) -#define DCFG_DEVADDR(a) \ +#define DCFG_DEVSPD_HSULPI (0 << GC_USB_DCFG_DEVSPD_LSB) +#define DCFG_DEVSPD_FSULPI BIT(GC_USB_DCFG_DEVSPD_LSB) +#define DCFG_DEVSPD_FS48 (3 << GC_USB_DCFG_DEVSPD_LSB) +#define DCFG_DEVADDR(a) \ (((a) << GC_USB_DCFG_DEVADDR_LSB) & GC_USB_DCFG_DEVADDR_MASK) -#define DCFG_NZLSOHSK BIT(GC_USB_DCFG_NZSTSOUTHSHK_LSB) +#define DCFG_NZLSOHSK BIT(GC_USB_DCFG_NZSTSOUTHSHK_LSB) -#define DCTL_SFTDISCON BIT(GC_USB_DCTL_SFTDISCON_LSB) -#define DCTL_CGOUTNAK BIT(GC_USB_DCTL_CGOUTNAK_LSB) -#define DCTL_CGNPINNAK BIT(GC_USB_DCTL_CGNPINNAK_LSB) -#define DCTL_PWRONPRGDONE BIT(GC_USB_DCTL_PWRONPRGDONE_LSB) +#define DCTL_SFTDISCON BIT(GC_USB_DCTL_SFTDISCON_LSB) +#define DCTL_CGOUTNAK BIT(GC_USB_DCTL_CGOUTNAK_LSB) +#define DCTL_CGNPINNAK BIT(GC_USB_DCTL_CGNPINNAK_LSB) +#define DCTL_PWRONPRGDONE BIT(GC_USB_DCTL_PWRONPRGDONE_LSB) /* Device Endpoint Common IN Interrupt Mask bits */ -#define DIEPMSK_AHBERRMSK BIT(GC_USB_DIEPMSK_AHBERRMSK_LSB) -#define DIEPMSK_BNAININTRMSK BIT(GC_USB_DIEPMSK_BNAININTRMSK_LSB) -#define DIEPMSK_EPDISBLDMSK BIT(GC_USB_DIEPMSK_EPDISBLDMSK_LSB) -#define DIEPMSK_INEPNAKEFFMSK BIT(GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB) -#define DIEPMSK_INTKNEPMISMSK BIT(GC_USB_DIEPMSK_INTKNEPMISMSK_LSB) -#define DIEPMSK_INTKNTXFEMPMSK BIT(GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB) -#define DIEPMSK_NAKMSK BIT(GC_USB_DIEPMSK_NAKMSK_LSB) -#define DIEPMSK_TIMEOUTMSK BIT(GC_USB_DIEPMSK_TIMEOUTMSK_LSB) -#define DIEPMSK_TXFIFOUNDRNMSK BIT(GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB) -#define DIEPMSK_XFERCOMPLMSK BIT(GC_USB_DIEPMSK_XFERCOMPLMSK_LSB) +#define DIEPMSK_AHBERRMSK BIT(GC_USB_DIEPMSK_AHBERRMSK_LSB) +#define DIEPMSK_BNAININTRMSK BIT(GC_USB_DIEPMSK_BNAININTRMSK_LSB) +#define DIEPMSK_EPDISBLDMSK BIT(GC_USB_DIEPMSK_EPDISBLDMSK_LSB) +#define DIEPMSK_INEPNAKEFFMSK BIT(GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB) +#define DIEPMSK_INTKNEPMISMSK BIT(GC_USB_DIEPMSK_INTKNEPMISMSK_LSB) +#define DIEPMSK_INTKNTXFEMPMSK BIT(GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB) +#define DIEPMSK_NAKMSK BIT(GC_USB_DIEPMSK_NAKMSK_LSB) +#define DIEPMSK_TIMEOUTMSK BIT(GC_USB_DIEPMSK_TIMEOUTMSK_LSB) +#define DIEPMSK_TXFIFOUNDRNMSK BIT(GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB) +#define DIEPMSK_XFERCOMPLMSK BIT(GC_USB_DIEPMSK_XFERCOMPLMSK_LSB) /* Device Endpoint Common OUT Interrupt Mask bits */ -#define DOEPMSK_AHBERRMSK BIT(GC_USB_DOEPMSK_AHBERRMSK_LSB) -#define DOEPMSK_BBLEERRMSK BIT(GC_USB_DOEPMSK_BBLEERRMSK_LSB) -#define DOEPMSK_BNAOUTINTRMSK BIT(GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB) -#define DOEPMSK_EPDISBLDMSK BIT(GC_USB_DOEPMSK_EPDISBLDMSK_LSB) -#define DOEPMSK_NAKMSK BIT(GC_USB_DOEPMSK_NAKMSK_LSB) -#define DOEPMSK_NYETMSK BIT(GC_USB_DOEPMSK_NYETMSK_LSB) -#define DOEPMSK_OUTPKTERRMSK BIT(GC_USB_DOEPMSK_OUTPKTERRMSK_LSB) -#define DOEPMSK_OUTTKNEPDISMSK BIT(GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB) -#define DOEPMSK_SETUPMSK BIT(GC_USB_DOEPMSK_SETUPMSK_LSB) -#define DOEPMSK_STSPHSERCVDMSK BIT(GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB) -#define DOEPMSK_XFERCOMPLMSK BIT(GC_USB_DOEPMSK_XFERCOMPLMSK_LSB) +#define DOEPMSK_AHBERRMSK BIT(GC_USB_DOEPMSK_AHBERRMSK_LSB) +#define DOEPMSK_BBLEERRMSK BIT(GC_USB_DOEPMSK_BBLEERRMSK_LSB) +#define DOEPMSK_BNAOUTINTRMSK BIT(GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB) +#define DOEPMSK_EPDISBLDMSK BIT(GC_USB_DOEPMSK_EPDISBLDMSK_LSB) +#define DOEPMSK_NAKMSK BIT(GC_USB_DOEPMSK_NAKMSK_LSB) +#define DOEPMSK_NYETMSK BIT(GC_USB_DOEPMSK_NYETMSK_LSB) +#define DOEPMSK_OUTPKTERRMSK BIT(GC_USB_DOEPMSK_OUTPKTERRMSK_LSB) +#define DOEPMSK_OUTTKNEPDISMSK BIT(GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB) +#define DOEPMSK_SETUPMSK BIT(GC_USB_DOEPMSK_SETUPMSK_LSB) +#define DOEPMSK_STSPHSERCVDMSK BIT(GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB) +#define DOEPMSK_XFERCOMPLMSK BIT(GC_USB_DOEPMSK_XFERCOMPLMSK_LSB) /* Device Endpoint-n IN Interrupt Register bits */ -#define DIEPINT_AHBERR BIT(GC_USB_DIEPINT0_AHBERR_LSB) -#define DIEPINT_BBLEERR BIT(GC_USB_DIEPINT0_BBLEERR_LSB) -#define DIEPINT_BNAINTR BIT(GC_USB_DIEPINT0_BNAINTR_LSB) -#define DIEPINT_EPDISBLD BIT(GC_USB_DIEPINT0_EPDISBLD_LSB) -#define DIEPINT_INEPNAKEFF BIT(GC_USB_DIEPINT0_INEPNAKEFF_LSB) -#define DIEPINT_INTKNEPMIS BIT(GC_USB_DIEPINT0_INTKNEPMIS_LSB) -#define DIEPINT_INTKNTXFEMP BIT(GC_USB_DIEPINT0_INTKNTXFEMP_LSB) -#define DIEPINT_NAKINTRPT BIT(GC_USB_DIEPINT0_NAKINTRPT_LSB) -#define DIEPINT_NYETINTRPT BIT(GC_USB_DIEPINT0_NYETINTRPT_LSB) -#define DIEPINT_PKTDRPSTS BIT(GC_USB_DIEPINT0_PKTDRPSTS_LSB) -#define DIEPINT_TIMEOUT BIT(GC_USB_DIEPINT0_TIMEOUT_LSB) -#define DIEPINT_TXFEMP BIT(GC_USB_DIEPINT0_TXFEMP_LSB) -#define DIEPINT_TXFIFOUNDRN BIT(GC_USB_DIEPINT0_TXFIFOUNDRN_LSB) -#define DIEPINT_XFERCOMPL BIT(GC_USB_DIEPINT0_XFERCOMPL_LSB) +#define DIEPINT_AHBERR BIT(GC_USB_DIEPINT0_AHBERR_LSB) +#define DIEPINT_BBLEERR BIT(GC_USB_DIEPINT0_BBLEERR_LSB) +#define DIEPINT_BNAINTR BIT(GC_USB_DIEPINT0_BNAINTR_LSB) +#define DIEPINT_EPDISBLD BIT(GC_USB_DIEPINT0_EPDISBLD_LSB) +#define DIEPINT_INEPNAKEFF BIT(GC_USB_DIEPINT0_INEPNAKEFF_LSB) +#define DIEPINT_INTKNEPMIS BIT(GC_USB_DIEPINT0_INTKNEPMIS_LSB) +#define DIEPINT_INTKNTXFEMP BIT(GC_USB_DIEPINT0_INTKNTXFEMP_LSB) +#define DIEPINT_NAKINTRPT BIT(GC_USB_DIEPINT0_NAKINTRPT_LSB) +#define DIEPINT_NYETINTRPT BIT(GC_USB_DIEPINT0_NYETINTRPT_LSB) +#define DIEPINT_PKTDRPSTS BIT(GC_USB_DIEPINT0_PKTDRPSTS_LSB) +#define DIEPINT_TIMEOUT BIT(GC_USB_DIEPINT0_TIMEOUT_LSB) +#define DIEPINT_TXFEMP BIT(GC_USB_DIEPINT0_TXFEMP_LSB) +#define DIEPINT_TXFIFOUNDRN BIT(GC_USB_DIEPINT0_TXFIFOUNDRN_LSB) +#define DIEPINT_XFERCOMPL BIT(GC_USB_DIEPINT0_XFERCOMPL_LSB) /* Device Endpoint-n OUT Interrupt Register bits */ -#define DOEPINT_AHBERR BIT(GC_USB_DOEPINT0_AHBERR_LSB) -#define DOEPINT_BACK2BACKSETUP BIT(GC_USB_DOEPINT0_BACK2BACKSETUP_LSB) -#define DOEPINT_BBLEERR BIT(GC_USB_DOEPINT0_BBLEERR_LSB) -#define DOEPINT_BNAINTR BIT(GC_USB_DOEPINT0_BNAINTR_LSB) -#define DOEPINT_EPDISBLD BIT(GC_USB_DOEPINT0_EPDISBLD_LSB) -#define DOEPINT_NAKINTRPT BIT(GC_USB_DOEPINT0_NAKINTRPT_LSB) -#define DOEPINT_NYETINTRPT BIT(GC_USB_DOEPINT0_NYETINTRPT_LSB) -#define DOEPINT_OUTPKTERR BIT(GC_USB_DOEPINT0_OUTPKTERR_LSB) -#define DOEPINT_OUTTKNEPDIS BIT(GC_USB_DOEPINT0_OUTTKNEPDIS_LSB) -#define DOEPINT_PKTDRPSTS BIT(GC_USB_DOEPINT0_PKTDRPSTS_LSB) -#define DOEPINT_SETUP BIT(GC_USB_DOEPINT0_SETUP_LSB) -#define DOEPINT_STSPHSERCVD BIT(GC_USB_DOEPINT0_STSPHSERCVD_LSB) -#define DOEPINT_STUPPKTRCVD BIT(GC_USB_DOEPINT0_STUPPKTRCVD_LSB) -#define DOEPINT_XFERCOMPL BIT(GC_USB_DOEPINT0_XFERCOMPL_LSB) +#define DOEPINT_AHBERR BIT(GC_USB_DOEPINT0_AHBERR_LSB) +#define DOEPINT_BACK2BACKSETUP BIT(GC_USB_DOEPINT0_BACK2BACKSETUP_LSB) +#define DOEPINT_BBLEERR BIT(GC_USB_DOEPINT0_BBLEERR_LSB) +#define DOEPINT_BNAINTR BIT(GC_USB_DOEPINT0_BNAINTR_LSB) +#define DOEPINT_EPDISBLD BIT(GC_USB_DOEPINT0_EPDISBLD_LSB) +#define DOEPINT_NAKINTRPT BIT(GC_USB_DOEPINT0_NAKINTRPT_LSB) +#define DOEPINT_NYETINTRPT BIT(GC_USB_DOEPINT0_NYETINTRPT_LSB) +#define DOEPINT_OUTPKTERR BIT(GC_USB_DOEPINT0_OUTPKTERR_LSB) +#define DOEPINT_OUTTKNEPDIS BIT(GC_USB_DOEPINT0_OUTTKNEPDIS_LSB) +#define DOEPINT_PKTDRPSTS BIT(GC_USB_DOEPINT0_PKTDRPSTS_LSB) +#define DOEPINT_SETUP BIT(GC_USB_DOEPINT0_SETUP_LSB) +#define DOEPINT_STSPHSERCVD BIT(GC_USB_DOEPINT0_STSPHSERCVD_LSB) +#define DOEPINT_STUPPKTRCVD BIT(GC_USB_DOEPINT0_STUPPKTRCVD_LSB) +#define DOEPINT_XFERCOMPL BIT(GC_USB_DOEPINT0_XFERCOMPL_LSB) -#define DXEPCTL_EPTYPE_CTRL (0 << GC_USB_DIEPCTL0_EPTYPE_LSB) -#define DXEPCTL_EPTYPE_ISO (1 << GC_USB_DIEPCTL0_EPTYPE_LSB) -#define DXEPCTL_EPTYPE_BULK (2 << GC_USB_DIEPCTL0_EPTYPE_LSB) -#define DXEPCTL_EPTYPE_INT (3 << GC_USB_DIEPCTL0_EPTYPE_LSB) -#define DXEPCTL_EPTYPE_MASK GC_USB_DIEPCTL0_EPTYPE_MASK -#define DXEPCTL_TXFNUM(n) ((n) << GC_USB_DIEPCTL1_TXFNUM_LSB) -#define DXEPCTL_STALL BIT(GC_USB_DIEPCTL0_STALL_LSB) -#define DXEPCTL_CNAK BIT(GC_USB_DIEPCTL0_CNAK_LSB) -#define DXEPCTL_DPID BIT(GC_USB_DIEPCTL0_DPID_LSB) -#define DXEPCTL_SNAK BIT(GC_USB_DIEPCTL0_SNAK_LSB) -#define DXEPCTL_NAKSTS BIT(GC_USB_DIEPCTL0_NAKSTS_LSB) -#define DXEPCTL_EPENA BIT(GC_USB_DIEPCTL0_EPENA_LSB) -#define DXEPCTL_EPDIS BIT(GC_USB_DIEPCTL0_EPDIS_LSB) -#define DXEPCTL_USBACTEP BIT(GC_USB_DIEPCTL0_USBACTEP_LSB) -#define DXEPCTL_MPS64 (0 << GC_USB_DIEPCTL0_MPS_LSB) -#define DXEPCTL_MPS(cnt) ((cnt) << GC_USB_DIEPCTL1_MPS_LSB) +#define DXEPCTL_EPTYPE_CTRL (0 << GC_USB_DIEPCTL0_EPTYPE_LSB) +#define DXEPCTL_EPTYPE_ISO (1 << GC_USB_DIEPCTL0_EPTYPE_LSB) +#define DXEPCTL_EPTYPE_BULK (2 << GC_USB_DIEPCTL0_EPTYPE_LSB) +#define DXEPCTL_EPTYPE_INT (3 << GC_USB_DIEPCTL0_EPTYPE_LSB) +#define DXEPCTL_EPTYPE_MASK GC_USB_DIEPCTL0_EPTYPE_MASK +#define DXEPCTL_TXFNUM(n) ((n) << GC_USB_DIEPCTL1_TXFNUM_LSB) +#define DXEPCTL_STALL BIT(GC_USB_DIEPCTL0_STALL_LSB) +#define DXEPCTL_CNAK BIT(GC_USB_DIEPCTL0_CNAK_LSB) +#define DXEPCTL_DPID BIT(GC_USB_DIEPCTL0_DPID_LSB) +#define DXEPCTL_SNAK BIT(GC_USB_DIEPCTL0_SNAK_LSB) +#define DXEPCTL_NAKSTS BIT(GC_USB_DIEPCTL0_NAKSTS_LSB) +#define DXEPCTL_EPENA BIT(GC_USB_DIEPCTL0_EPENA_LSB) +#define DXEPCTL_EPDIS BIT(GC_USB_DIEPCTL0_EPDIS_LSB) +#define DXEPCTL_USBACTEP BIT(GC_USB_DIEPCTL0_USBACTEP_LSB) +#define DXEPCTL_MPS64 (0 << GC_USB_DIEPCTL0_MPS_LSB) +#define DXEPCTL_MPS(cnt) ((cnt) << GC_USB_DIEPCTL1_MPS_LSB) -#define DXEPTSIZ_SUPCNT(n) ((n) << GC_USB_DOEPTSIZ0_SUPCNT_LSB) -#define DXEPTSIZ_PKTCNT(n) ((n) << GC_USB_DIEPTSIZ0_PKTCNT_LSB) -#define DXEPTSIZ_XFERSIZE(n) ((n) << GC_USB_DIEPTSIZ0_XFERSIZE_LSB) - -#define DOEPDMA_BS_HOST_RDY (0 << 30) -#define DOEPDMA_BS_DMA_BSY (1 << 30) -#define DOEPDMA_BS_DMA_DONE (2 << 30) -#define DOEPDMA_BS_HOST_BSY (3 << 30) -#define DOEPDMA_BS_MASK (3 << 30) -#define DOEPDMA_RXSTS_MASK (3 << 28) -#define DOEPDMA_LAST BIT(27) -#define DOEPDMA_SP BIT(26) -#define DOEPDMA_IOC BIT(25) -#define DOEPDMA_SR BIT(24) -#define DOEPDMA_MTRF BIT(23) -#define DOEPDMA_NAK BIT(16) -#define DOEPDMA_RXBYTES(n) (((n) & 0xFFFF) << 0) -#define DOEPDMA_RXBYTES_MASK (0xFFFF << 0) - -#define DIEPDMA_BS_HOST_RDY (0 << 30) -#define DIEPDMA_BS_DMA_BSY (1 << 30) -#define DIEPDMA_BS_DMA_DONE (2 << 30) -#define DIEPDMA_BS_HOST_BSY (3 << 30) -#define DIEPDMA_BS_MASK (3 << 30) -#define DIEPDMA_TXSTS_MASK (3 << 28) -#define DIEPDMA_LAST BIT(27) -#define DIEPDMA_SP BIT(26) -#define DIEPDMA_IOC BIT(25) -#define DIEPDMA_TXBYTES(n) (((n) & 0xFFFF) << 0) -#define DIEPDMA_TXBYTES_MASK (0xFFFF << 0) +#define DXEPTSIZ_SUPCNT(n) ((n) << GC_USB_DOEPTSIZ0_SUPCNT_LSB) +#define DXEPTSIZ_PKTCNT(n) ((n) << GC_USB_DIEPTSIZ0_PKTCNT_LSB) +#define DXEPTSIZ_XFERSIZE(n) ((n) << GC_USB_DIEPTSIZ0_XFERSIZE_LSB) +#define DOEPDMA_BS_HOST_RDY (0 << 30) +#define DOEPDMA_BS_DMA_BSY (1 << 30) +#define DOEPDMA_BS_DMA_DONE (2 << 30) +#define DOEPDMA_BS_HOST_BSY (3 << 30) +#define DOEPDMA_BS_MASK (3 << 30) +#define DOEPDMA_RXSTS_MASK (3 << 28) +#define DOEPDMA_LAST BIT(27) +#define DOEPDMA_SP BIT(26) +#define DOEPDMA_IOC BIT(25) +#define DOEPDMA_SR BIT(24) +#define DOEPDMA_MTRF BIT(23) +#define DOEPDMA_NAK BIT(16) +#define DOEPDMA_RXBYTES(n) (((n)&0xFFFF) << 0) +#define DOEPDMA_RXBYTES_MASK (0xFFFF << 0) +#define DIEPDMA_BS_HOST_RDY (0 << 30) +#define DIEPDMA_BS_DMA_BSY (1 << 30) +#define DIEPDMA_BS_DMA_DONE (2 << 30) +#define DIEPDMA_BS_HOST_BSY (3 << 30) +#define DIEPDMA_BS_MASK (3 << 30) +#define DIEPDMA_TXSTS_MASK (3 << 28) +#define DIEPDMA_LAST BIT(27) +#define DIEPDMA_SP BIT(26) +#define DIEPDMA_IOC BIT(25) +#define DIEPDMA_TXBYTES(n) (((n)&0xFFFF) << 0) +#define DIEPDMA_TXBYTES_MASK (0xFFFF << 0) /* Register defs referenced from DWC block in CR50. This is not a native * ST block, so we'll use this modified regdefs list. */ -#define GC_USB_FS_BASE_ADDR 0x50000000 -#define GC_USB_HS_BASE_ADDR 0x40040000 +#define GC_USB_FS_BASE_ADDR 0x50000000 +#define GC_USB_HS_BASE_ADDR 0x40040000 #ifdef CONFIG_USB_DWC_FS -#define GC_USB_BASE_ADDR GC_USB_FS_BASE_ADDR +#define GC_USB_BASE_ADDR GC_USB_FS_BASE_ADDR #else -#define GC_USB_BASE_ADDR GC_USB_HS_BASE_ADDR +#define GC_USB_BASE_ADDR GC_USB_HS_BASE_ADDR #endif -#define GC_USB_GOTGCTL_OFFSET 0x0 -#define GC_USB_GOTGCTL_DEFAULT 0x0 -#define GC_USB_GOTGINT_OFFSET 0x4 -#define GC_USB_GOTGINT_DEFAULT 0x0 -#define GC_USB_GAHBCFG_OFFSET 0x8 -#define GC_USB_GAHBCFG_DEFAULT 0x0 -#define GC_USB_GUSBCFG_OFFSET 0xc -#define GC_USB_GUSBCFG_DEFAULT 0x0 -#define GC_USB_GRSTCTL_OFFSET 0x10 -#define GC_USB_GRSTCTL_DEFAULT 0x0 -#define GC_USB_GINTSTS_OFFSET 0x14 -#define GC_USB_GINTSTS_DEFAULT 0x0 -#define GC_USB_GINTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_DEFAULT 0x0 -#define GC_USB_GRXSTSR_OFFSET 0x1c -#define GC_USB_GRXSTSR_DEFAULT 0x0 -#define GC_USB_GRXSTSP_OFFSET 0x20 -#define GC_USB_GRXSTSP_DEFAULT 0x0 -#define GC_USB_GRXFSIZ_OFFSET 0x24 -#define GC_USB_GRXFSIZ_DEFAULT 0x0 -#define GC_USB_GNPTXFSIZ_OFFSET 0x28 -#define GC_USB_GNPTXFSIZ_DEFAULT 0x0 +#define GC_USB_GOTGCTL_OFFSET 0x0 +#define GC_USB_GOTGCTL_DEFAULT 0x0 +#define GC_USB_GOTGINT_OFFSET 0x4 +#define GC_USB_GOTGINT_DEFAULT 0x0 +#define GC_USB_GAHBCFG_OFFSET 0x8 +#define GC_USB_GAHBCFG_DEFAULT 0x0 +#define GC_USB_GUSBCFG_OFFSET 0xc +#define GC_USB_GUSBCFG_DEFAULT 0x0 +#define GC_USB_GRSTCTL_OFFSET 0x10 +#define GC_USB_GRSTCTL_DEFAULT 0x0 +#define GC_USB_GINTSTS_OFFSET 0x14 +#define GC_USB_GINTSTS_DEFAULT 0x0 +#define GC_USB_GINTMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_DEFAULT 0x0 +#define GC_USB_GRXSTSR_OFFSET 0x1c +#define GC_USB_GRXSTSR_DEFAULT 0x0 +#define GC_USB_GRXSTSP_OFFSET 0x20 +#define GC_USB_GRXSTSP_DEFAULT 0x0 +#define GC_USB_GRXFSIZ_OFFSET 0x24 +#define GC_USB_GRXFSIZ_DEFAULT 0x0 +#define GC_USB_GNPTXFSIZ_OFFSET 0x28 +#define GC_USB_GNPTXFSIZ_DEFAULT 0x0 -#define GC_USB_GCCFG_OFFSET 0x38 -#define GC_USB_GCCFG_DEFAULT 0x0 -#define GC_USB_GUID_OFFSET 0x3c -#define GC_USB_GUID_DEFAULT 0x0 -#define GC_USB_GSNPSID_OFFSET 0x40 -#define GC_USB_GSNPSID_DEFAULT 0x0 -#define GC_USB_GHWCFG1_OFFSET 0x44 -#define GC_USB_GHWCFG1_DEFAULT 0x0 -#define GC_USB_GHWCFG2_OFFSET 0x48 -#define GC_USB_GHWCFG2_DEFAULT 0x0 -#define GC_USB_GHWCFG3_OFFSET 0x4c -#define GC_USB_GHWCFG3_DEFAULT 0x0 -#define GC_USB_GHWCFG4_OFFSET 0x50 -#define GC_USB_GHWCFG4_DEFAULT 0x0 -#define GC_USB_GDFIFOCFG_OFFSET 0x5c -#define GC_USB_GDFIFOCFG_DEFAULT 0x0 -#define GC_USB_DIEPTXF1_OFFSET 0x104 -#define GC_USB_DIEPTXF1_DEFAULT 0x1000 -#define GC_USB_DIEPTXF2_OFFSET 0x108 -#define GC_USB_DIEPTXF2_DEFAULT 0x0 -#define GC_USB_DIEPTXF3_OFFSET 0x10c -#define GC_USB_DIEPTXF3_DEFAULT 0x0 -#define GC_USB_DIEPTXF4_OFFSET 0x110 -#define GC_USB_DIEPTXF4_DEFAULT 0x0 -#define GC_USB_DIEPTXF5_OFFSET 0x114 -#define GC_USB_DIEPTXF5_DEFAULT 0x0 -#define GC_USB_DIEPTXF6_OFFSET 0x118 -#define GC_USB_DIEPTXF6_DEFAULT 0x0 -#define GC_USB_DIEPTXF7_OFFSET 0x11c -#define GC_USB_DIEPTXF7_DEFAULT 0x0 -#define GC_USB_DIEPTXF8_OFFSET 0x120 -#define GC_USB_DIEPTXF8_DEFAULT 0x0 -#define GC_USB_DIEPTXF9_OFFSET 0x124 -#define GC_USB_DIEPTXF9_DEFAULT 0x0 -#define GC_USB_DIEPTXF10_OFFSET 0x128 -#define GC_USB_DIEPTXF10_DEFAULT 0x0 -#define GC_USB_DIEPTXF11_OFFSET 0x12c -#define GC_USB_DIEPTXF11_DEFAULT 0x0 -#define GC_USB_DIEPTXF12_OFFSET 0x130 -#define GC_USB_DIEPTXF12_DEFAULT 0x0 -#define GC_USB_DIEPTXF13_OFFSET 0x134 -#define GC_USB_DIEPTXF13_DEFAULT 0x0 -#define GC_USB_DIEPTXF14_OFFSET 0x138 -#define GC_USB_DIEPTXF14_DEFAULT 0x0 -#define GC_USB_DIEPTXF15_OFFSET 0x13c -#define GC_USB_DIEPTXF15_DEFAULT 0x0 -#define GC_USB_DCFG_OFFSET 0x800 -#define GC_USB_DCFG_DEFAULT 0x8000000 -#define GC_USB_DCTL_OFFSET 0x804 -#define GC_USB_DCTL_DEFAULT 0x0 -#define GC_USB_DSTS_OFFSET 0x808 -#define GC_USB_DSTS_DEFAULT 0x0 -#define GC_USB_DIEPMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_DEFAULT 0x80 -#define GC_USB_DOEPMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_DEFAULT 0x0 -#define GC_USB_DAINT_OFFSET 0x818 -#define GC_USB_DAINT_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OFFSET 0x81c -#define GC_USB_DAINTMSK_DEFAULT 0x0 -#define GC_USB_DVBUSDIS_OFFSET 0x828 -#define GC_USB_DVBUSDIS_DEFAULT 0x0 -#define GC_USB_DVBUSPULSE_OFFSET 0x82c -#define GC_USB_DVBUSPULSE_DEFAULT 0x0 -#define GC_USB_DTHRCTL_OFFSET 0x830 -#define GC_USB_DTHRCTL_DEFAULT 0x0 -#define GC_USB_DIEPEMPMSK_OFFSET 0x834 -#define GC_USB_DIEPEMPMSK_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_OFFSET 0x900 -#define GC_USB_DIEPCTL0_DEFAULT 0x0 -#define GC_USB_DIEPINT0_OFFSET 0x908 -#define GC_USB_DIEPINT0_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ0_OFFSET 0x910 -#define GC_USB_DIEPTSIZ0_DEFAULT 0x0 -#define GC_USB_DIEPDMA0_OFFSET 0x914 -#define GC_USB_DIEPDMA0_DEFAULT 0x0 -#define GC_USB_DTXFSTS0_OFFSET 0x918 -#define GC_USB_DTXFSTS0_DEFAULT 0x0 -#define GC_USB_DIEPDMAB0_OFFSET 0x91c -#define GC_USB_DIEPDMAB0_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_OFFSET 0x920 -#define GC_USB_DIEPCTL1_DEFAULT 0x0 -#define GC_USB_DIEPINT1_OFFSET 0x928 -#define GC_USB_DIEPINT1_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ1_OFFSET 0x930 -#define GC_USB_DIEPTSIZ1_DEFAULT 0x0 -#define GC_USB_DIEPDMA1_OFFSET 0x934 -#define GC_USB_DIEPDMA1_DEFAULT 0x0 -#define GC_USB_DTXFSTS1_OFFSET 0x938 -#define GC_USB_DTXFSTS1_DEFAULT 0x0 -#define GC_USB_DIEPDMAB1_OFFSET 0x93c -#define GC_USB_DIEPDMAB1_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_OFFSET 0x940 -#define GC_USB_DIEPCTL2_DEFAULT 0x0 -#define GC_USB_DIEPINT2_OFFSET 0x948 -#define GC_USB_DIEPINT2_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ2_OFFSET 0x950 -#define GC_USB_DIEPTSIZ2_DEFAULT 0x0 -#define GC_USB_DIEPDMA2_OFFSET 0x954 -#define GC_USB_DIEPDMA2_DEFAULT 0x0 -#define GC_USB_DTXFSTS2_OFFSET 0x958 -#define GC_USB_DTXFSTS2_DEFAULT 0x0 -#define GC_USB_DIEPDMAB2_OFFSET 0x95c -#define GC_USB_DIEPDMAB2_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_OFFSET 0x960 -#define GC_USB_DIEPCTL3_DEFAULT 0x0 -#define GC_USB_DIEPINT3_OFFSET 0x968 -#define GC_USB_DIEPINT3_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ3_OFFSET 0x970 -#define GC_USB_DIEPTSIZ3_DEFAULT 0x0 -#define GC_USB_DIEPDMA3_OFFSET 0x974 -#define GC_USB_DIEPDMA3_DEFAULT 0x0 -#define GC_USB_DTXFSTS3_OFFSET 0x978 -#define GC_USB_DTXFSTS3_DEFAULT 0x0 -#define GC_USB_DIEPDMAB3_OFFSET 0x97c -#define GC_USB_DIEPDMAB3_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_OFFSET 0x980 -#define GC_USB_DIEPCTL4_DEFAULT 0x0 -#define GC_USB_DIEPINT4_OFFSET 0x988 -#define GC_USB_DIEPINT4_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ4_OFFSET 0x990 -#define GC_USB_DIEPTSIZ4_DEFAULT 0x0 -#define GC_USB_DIEPDMA4_OFFSET 0x994 -#define GC_USB_DIEPDMA4_DEFAULT 0x0 -#define GC_USB_DTXFSTS4_OFFSET 0x998 -#define GC_USB_DTXFSTS4_DEFAULT 0x0 -#define GC_USB_DIEPDMAB4_OFFSET 0x99c -#define GC_USB_DIEPDMAB4_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_DEFAULT 0x0 -#define GC_USB_DIEPINT5_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ5_OFFSET 0x9b0 -#define GC_USB_DIEPTSIZ5_DEFAULT 0x0 -#define GC_USB_DIEPDMA5_OFFSET 0x9b4 -#define GC_USB_DIEPDMA5_DEFAULT 0x0 -#define GC_USB_DTXFSTS5_OFFSET 0x9b8 -#define GC_USB_DTXFSTS5_DEFAULT 0x0 -#define GC_USB_DIEPDMAB5_OFFSET 0x9bc -#define GC_USB_DIEPDMAB5_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_DEFAULT 0x0 -#define GC_USB_DIEPINT6_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ6_OFFSET 0x9d0 -#define GC_USB_DIEPTSIZ6_DEFAULT 0x0 -#define GC_USB_DIEPDMA6_OFFSET 0x9d4 -#define GC_USB_DIEPDMA6_DEFAULT 0x0 -#define GC_USB_DTXFSTS6_OFFSET 0x9d8 -#define GC_USB_DTXFSTS6_DEFAULT 0x0 -#define GC_USB_DIEPDMAB6_OFFSET 0x9dc -#define GC_USB_DIEPDMAB6_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_DEFAULT 0x0 -#define GC_USB_DIEPINT7_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ7_OFFSET 0x9f0 -#define GC_USB_DIEPTSIZ7_DEFAULT 0x0 -#define GC_USB_DIEPDMA7_OFFSET 0x9f4 -#define GC_USB_DIEPDMA7_DEFAULT 0x0 -#define GC_USB_DTXFSTS7_OFFSET 0x9f8 -#define GC_USB_DTXFSTS7_DEFAULT 0x0 -#define GC_USB_DIEPDMAB7_OFFSET 0x9fc -#define GC_USB_DIEPDMAB7_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_DEFAULT 0x0 -#define GC_USB_DIEPINT8_OFFSET 0xa08 -#define GC_USB_DIEPINT8_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ8_OFFSET 0xa10 -#define GC_USB_DIEPTSIZ8_DEFAULT 0x0 -#define GC_USB_DIEPDMA8_OFFSET 0xa14 -#define GC_USB_DIEPDMA8_DEFAULT 0x0 -#define GC_USB_DTXFSTS8_OFFSET 0xa18 -#define GC_USB_DTXFSTS8_DEFAULT 0x0 -#define GC_USB_DIEPDMAB8_OFFSET 0xa1c -#define GC_USB_DIEPDMAB8_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_DEFAULT 0x0 -#define GC_USB_DIEPINT9_OFFSET 0xa28 -#define GC_USB_DIEPINT9_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ9_OFFSET 0xa30 -#define GC_USB_DIEPTSIZ9_DEFAULT 0x0 -#define GC_USB_DIEPDMA9_OFFSET 0xa34 -#define GC_USB_DIEPDMA9_DEFAULT 0x0 -#define GC_USB_DTXFSTS9_OFFSET 0xa38 -#define GC_USB_DTXFSTS9_DEFAULT 0x0 -#define GC_USB_DIEPDMAB9_OFFSET 0xa3c -#define GC_USB_DIEPDMAB9_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_DEFAULT 0x0 -#define GC_USB_DIEPINT10_OFFSET 0xa48 -#define GC_USB_DIEPINT10_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ10_OFFSET 0xa50 -#define GC_USB_DIEPTSIZ10_DEFAULT 0x0 -#define GC_USB_DIEPDMA10_OFFSET 0xa54 -#define GC_USB_DIEPDMA10_DEFAULT 0x0 -#define GC_USB_DTXFSTS10_OFFSET 0xa58 -#define GC_USB_DTXFSTS10_DEFAULT 0x0 -#define GC_USB_DIEPDMAB10_OFFSET 0xa5c -#define GC_USB_DIEPDMAB10_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_DEFAULT 0x0 -#define GC_USB_DIEPINT11_OFFSET 0xa68 -#define GC_USB_DIEPINT11_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ11_OFFSET 0xa70 -#define GC_USB_DIEPTSIZ11_DEFAULT 0x0 -#define GC_USB_DIEPDMA11_OFFSET 0xa74 -#define GC_USB_DIEPDMA11_DEFAULT 0x0 -#define GC_USB_DTXFSTS11_OFFSET 0xa78 -#define GC_USB_DTXFSTS11_DEFAULT 0x0 -#define GC_USB_DIEPDMAB11_OFFSET 0xa7c -#define GC_USB_DIEPDMAB11_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_DEFAULT 0x0 -#define GC_USB_DIEPINT12_OFFSET 0xa88 -#define GC_USB_DIEPINT12_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ12_OFFSET 0xa90 -#define GC_USB_DIEPTSIZ12_DEFAULT 0x0 -#define GC_USB_DIEPDMA12_OFFSET 0xa94 -#define GC_USB_DIEPDMA12_DEFAULT 0x0 -#define GC_USB_DTXFSTS12_OFFSET 0xa98 -#define GC_USB_DTXFSTS12_DEFAULT 0x0 -#define GC_USB_DIEPDMAB12_OFFSET 0xa9c -#define GC_USB_DIEPDMAB12_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_DEFAULT 0x0 -#define GC_USB_DIEPINT13_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ13_OFFSET 0xab0 -#define GC_USB_DIEPTSIZ13_DEFAULT 0x0 -#define GC_USB_DIEPDMA13_OFFSET 0xab4 -#define GC_USB_DIEPDMA13_DEFAULT 0x0 -#define GC_USB_DTXFSTS13_OFFSET 0xab8 -#define GC_USB_DTXFSTS13_DEFAULT 0x0 -#define GC_USB_DIEPDMAB13_OFFSET 0xabc -#define GC_USB_DIEPDMAB13_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_DEFAULT 0x0 -#define GC_USB_DIEPINT14_OFFSET 0xac8 -#define GC_USB_DIEPINT14_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ14_OFFSET 0xad0 -#define GC_USB_DIEPTSIZ14_DEFAULT 0x0 -#define GC_USB_DIEPDMA14_OFFSET 0xad4 -#define GC_USB_DIEPDMA14_DEFAULT 0x0 -#define GC_USB_DTXFSTS14_OFFSET 0xad8 -#define GC_USB_DTXFSTS14_DEFAULT 0x0 -#define GC_USB_DIEPDMAB14_OFFSET 0xadc -#define GC_USB_DIEPDMAB14_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_DEFAULT 0x0 -#define GC_USB_DIEPINT15_OFFSET 0xae8 -#define GC_USB_DIEPINT15_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ15_OFFSET 0xaf0 -#define GC_USB_DIEPTSIZ15_DEFAULT 0x0 -#define GC_USB_DIEPDMA15_OFFSET 0xaf4 -#define GC_USB_DIEPDMA15_DEFAULT 0x0 -#define GC_USB_DTXFSTS15_OFFSET 0xaf8 -#define GC_USB_DTXFSTS15_DEFAULT 0x0 -#define GC_USB_DIEPDMAB15_OFFSET 0xafc -#define GC_USB_DIEPDMAB15_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_DEFAULT 0x0 -#define GC_USB_DOEPINT0_OFFSET 0xb08 -#define GC_USB_DOEPINT0_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ0_OFFSET 0xb10 -#define GC_USB_DOEPTSIZ0_DEFAULT 0x0 -#define GC_USB_DOEPDMA0_OFFSET 0xb14 -#define GC_USB_DOEPDMA0_DEFAULT 0x0 -#define GC_USB_DOEPDMAB0_OFFSET 0xb1c -#define GC_USB_DOEPDMAB0_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_DEFAULT 0x0 -#define GC_USB_DOEPINT1_OFFSET 0xb28 -#define GC_USB_DOEPINT1_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ1_OFFSET 0xb30 -#define GC_USB_DOEPTSIZ1_DEFAULT 0x0 -#define GC_USB_DOEPDMA1_OFFSET 0xb34 -#define GC_USB_DOEPDMA1_DEFAULT 0x0 -#define GC_USB_DOEPDMAB1_OFFSET 0xb3c -#define GC_USB_DOEPDMAB1_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_DEFAULT 0x0 -#define GC_USB_DOEPINT2_OFFSET 0xb48 -#define GC_USB_DOEPINT2_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ2_OFFSET 0xb50 -#define GC_USB_DOEPTSIZ2_DEFAULT 0x0 -#define GC_USB_DOEPDMA2_OFFSET 0xb54 -#define GC_USB_DOEPDMA2_DEFAULT 0x0 -#define GC_USB_DOEPDMAB2_OFFSET 0xb5c -#define GC_USB_DOEPDMAB2_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_DEFAULT 0x0 -#define GC_USB_DOEPINT3_OFFSET 0xb68 -#define GC_USB_DOEPINT3_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ3_OFFSET 0xb70 -#define GC_USB_DOEPTSIZ3_DEFAULT 0x0 -#define GC_USB_DOEPDMA3_OFFSET 0xb74 -#define GC_USB_DOEPDMA3_DEFAULT 0x0 -#define GC_USB_DOEPDMAB3_OFFSET 0xb7c -#define GC_USB_DOEPDMAB3_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_DEFAULT 0x0 -#define GC_USB_DOEPINT4_OFFSET 0xb88 -#define GC_USB_DOEPINT4_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ4_OFFSET 0xb90 -#define GC_USB_DOEPTSIZ4_DEFAULT 0x0 -#define GC_USB_DOEPDMA4_OFFSET 0xb94 -#define GC_USB_DOEPDMA4_DEFAULT 0x0 -#define GC_USB_DOEPDMAB4_OFFSET 0xb9c -#define GC_USB_DOEPDMAB4_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_DEFAULT 0x0 -#define GC_USB_DOEPINT5_OFFSET 0xba8 -#define GC_USB_DOEPINT5_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ5_OFFSET 0xbb0 -#define GC_USB_DOEPTSIZ5_DEFAULT 0x0 -#define GC_USB_DOEPDMA5_OFFSET 0xbb4 -#define GC_USB_DOEPDMA5_DEFAULT 0x0 -#define GC_USB_DOEPDMAB5_OFFSET 0xbbc -#define GC_USB_DOEPDMAB5_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_DEFAULT 0x0 -#define GC_USB_DOEPINT6_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ6_OFFSET 0xbd0 -#define GC_USB_DOEPTSIZ6_DEFAULT 0x0 -#define GC_USB_DOEPDMA6_OFFSET 0xbd4 -#define GC_USB_DOEPDMA6_DEFAULT 0x0 -#define GC_USB_DOEPDMAB6_OFFSET 0xbdc -#define GC_USB_DOEPDMAB6_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_DEFAULT 0x0 -#define GC_USB_DOEPINT7_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ7_OFFSET 0xbf0 -#define GC_USB_DOEPTSIZ7_DEFAULT 0x0 -#define GC_USB_DOEPDMA7_OFFSET 0xbf4 -#define GC_USB_DOEPDMA7_DEFAULT 0x0 -#define GC_USB_DOEPDMAB7_OFFSET 0xbfc -#define GC_USB_DOEPDMAB7_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_DEFAULT 0x0 -#define GC_USB_DOEPINT8_OFFSET 0xc08 -#define GC_USB_DOEPINT8_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ8_OFFSET 0xc10 -#define GC_USB_DOEPTSIZ8_DEFAULT 0x0 -#define GC_USB_DOEPDMA8_OFFSET 0xc14 -#define GC_USB_DOEPDMA8_DEFAULT 0x0 -#define GC_USB_DOEPDMAB8_OFFSET 0xc1c -#define GC_USB_DOEPDMAB8_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_DEFAULT 0x0 -#define GC_USB_DOEPINT9_OFFSET 0xc28 -#define GC_USB_DOEPINT9_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ9_OFFSET 0xc30 -#define GC_USB_DOEPTSIZ9_DEFAULT 0x0 -#define GC_USB_DOEPDMA9_OFFSET 0xc34 -#define GC_USB_DOEPDMA9_DEFAULT 0x0 -#define GC_USB_DOEPDMAB9_OFFSET 0xc3c -#define GC_USB_DOEPDMAB9_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_DEFAULT 0x0 -#define GC_USB_DOEPINT10_OFFSET 0xc48 -#define GC_USB_DOEPINT10_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ10_OFFSET 0xc50 -#define GC_USB_DOEPTSIZ10_DEFAULT 0x0 -#define GC_USB_DOEPDMA10_OFFSET 0xc54 -#define GC_USB_DOEPDMA10_DEFAULT 0x0 -#define GC_USB_DOEPDMAB10_OFFSET 0xc5c -#define GC_USB_DOEPDMAB10_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_DEFAULT 0x0 -#define GC_USB_DOEPINT11_OFFSET 0xc68 -#define GC_USB_DOEPINT11_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ11_OFFSET 0xc70 -#define GC_USB_DOEPTSIZ11_DEFAULT 0x0 -#define GC_USB_DOEPDMA11_OFFSET 0xc74 -#define GC_USB_DOEPDMA11_DEFAULT 0x0 -#define GC_USB_DOEPDMAB11_OFFSET 0xc7c -#define GC_USB_DOEPDMAB11_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_DEFAULT 0x0 -#define GC_USB_DOEPINT12_OFFSET 0xc88 -#define GC_USB_DOEPINT12_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ12_OFFSET 0xc90 -#define GC_USB_DOEPTSIZ12_DEFAULT 0x0 -#define GC_USB_DOEPDMA12_OFFSET 0xc94 -#define GC_USB_DOEPDMA12_DEFAULT 0x0 -#define GC_USB_DOEPDMAB12_OFFSET 0xc9c -#define GC_USB_DOEPDMAB12_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_DEFAULT 0x0 -#define GC_USB_DOEPINT13_OFFSET 0xca8 -#define GC_USB_DOEPINT13_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ13_OFFSET 0xcb0 -#define GC_USB_DOEPTSIZ13_DEFAULT 0x0 -#define GC_USB_DOEPDMA13_OFFSET 0xcb4 -#define GC_USB_DOEPDMA13_DEFAULT 0x0 -#define GC_USB_DOEPDMAB13_OFFSET 0xcbc -#define GC_USB_DOEPDMAB13_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_DEFAULT 0x0 -#define GC_USB_DOEPINT14_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ14_OFFSET 0xcd0 -#define GC_USB_DOEPTSIZ14_DEFAULT 0x0 -#define GC_USB_DOEPDMA14_OFFSET 0xcd4 -#define GC_USB_DOEPDMA14_DEFAULT 0x0 -#define GC_USB_DOEPDMAB14_OFFSET 0xcdc -#define GC_USB_DOEPDMAB14_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_DEFAULT 0x0 -#define GC_USB_DOEPINT15_OFFSET 0xce8 -#define GC_USB_DOEPINT15_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ15_OFFSET 0xcf0 -#define GC_USB_DOEPTSIZ15_DEFAULT 0x0 -#define GC_USB_DOEPDMA15_OFFSET 0xcf4 -#define GC_USB_DOEPDMA15_DEFAULT 0x0 -#define GC_USB_DOEPDMAB15_OFFSET 0xcfc -#define GC_USB_DOEPDMAB15_DEFAULT 0x0 -#define GC_USB_PCGCCTL_OFFSET 0xe00 -#define GC_USB_PCGCCTL_DEFAULT 0x0 -#define GC_USB_DFIFO_OFFSET 0x20000 -#define GC_USB_GOTGCTL_BVALIDOVEN_LSB 0x6 -#define GC_USB_GOTGCTL_BVALIDOVEN_MASK 0x40 -#define GC_USB_GOTGCTL_BVALIDOVEN_SIZE 0x1 -#define GC_USB_GOTGCTL_BVALIDOVEN_DEFAULT 0x0 -#define GC_USB_GOTGCTL_BVALIDOVEN_OFFSET 0x0 -#define GC_USB_GOTGCTL_BVALIDOVVAL_LSB 0x7 -#define GC_USB_GOTGCTL_BVALIDOVVAL_MASK 0x80 -#define GC_USB_GOTGCTL_BVALIDOVVAL_SIZE 0x1 -#define GC_USB_GOTGCTL_BVALIDOVVAL_DEFAULT 0x0 -#define GC_USB_GOTGCTL_BVALIDOVVAL_OFFSET 0x0 -#define GC_USB_GOTGCTL_CONIDSTS_LSB 0x10 -#define GC_USB_GOTGCTL_CONIDSTS_MASK 0x10000 -#define GC_USB_GOTGCTL_CONIDSTS_SIZE 0x1 -#define GC_USB_GOTGCTL_CONIDSTS_DEFAULT 0x0 -#define GC_USB_GOTGCTL_CONIDSTS_OFFSET 0x0 -#define GC_USB_GOTGCTL_BSESVLD_LSB 0x13 -#define GC_USB_GOTGCTL_BSESVLD_MASK 0x80000 -#define GC_USB_GOTGCTL_BSESVLD_SIZE 0x1 -#define GC_USB_GOTGCTL_BSESVLD_DEFAULT 0x0 -#define GC_USB_GOTGCTL_BSESVLD_OFFSET 0x0 -#define GC_USB_GOTGCTL_OTGVER_LSB 0x14 -#define GC_USB_GOTGCTL_OTGVER_MASK 0x100000 -#define GC_USB_GOTGCTL_OTGVER_SIZE 0x1 -#define GC_USB_GOTGCTL_OTGVER_DEFAULT 0x0 -#define GC_USB_GOTGCTL_OTGVER_OFFSET 0x0 -#define GC_USB_GOTGCTL_CURMOD_LSB 0x15 -#define GC_USB_GOTGCTL_CURMOD_MASK 0x200000 -#define GC_USB_GOTGCTL_CURMOD_SIZE 0x1 -#define GC_USB_GOTGCTL_CURMOD_DEFAULT 0x0 -#define GC_USB_GOTGCTL_CURMOD_OFFSET 0x0 -#define GC_USB_GOTGINT_SESENDDET_LSB 0x2 -#define GC_USB_GOTGINT_SESENDDET_MASK 0x4 -#define GC_USB_GOTGINT_SESENDDET_SIZE 0x1 -#define GC_USB_GOTGINT_SESENDDET_DEFAULT 0x0 -#define GC_USB_GOTGINT_SESENDDET_OFFSET 0x4 -#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_LSB 0x8 -#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_MASK 0x100 -#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_SIZE 0x1 -#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT 0x0 -#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_OFFSET 0x4 -#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_LSB 0x9 -#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_MASK 0x200 -#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_SIZE 0x1 -#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT 0x0 -#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_OFFSET 0x4 -#define GC_USB_GOTGINT_HSTNEGDET_LSB 0x11 -#define GC_USB_GOTGINT_HSTNEGDET_MASK 0x20000 -#define GC_USB_GOTGINT_HSTNEGDET_SIZE 0x1 -#define GC_USB_GOTGINT_HSTNEGDET_DEFAULT 0x0 -#define GC_USB_GOTGINT_HSTNEGDET_OFFSET 0x4 -#define GC_USB_GOTGINT_ADEVTOUTCHG_LSB 0x12 -#define GC_USB_GOTGINT_ADEVTOUTCHG_MASK 0x40000 -#define GC_USB_GOTGINT_ADEVTOUTCHG_SIZE 0x1 -#define GC_USB_GOTGINT_ADEVTOUTCHG_DEFAULT 0x0 -#define GC_USB_GOTGINT_ADEVTOUTCHG_OFFSET 0x4 -#define GC_USB_GAHBCFG_GLBLINTRMSK_LSB 0x0 -#define GC_USB_GAHBCFG_GLBLINTRMSK_MASK 0x1 -#define GC_USB_GAHBCFG_GLBLINTRMSK_SIZE 0x1 -#define GC_USB_GAHBCFG_GLBLINTRMSK_DEFAULT 0x0 -#define GC_USB_GAHBCFG_GLBLINTRMSK_OFFSET 0x8 -#define GC_USB_GAHBCFG_HBSTLEN_LSB 0x1 -#define GC_USB_GAHBCFG_HBSTLEN_MASK 0x1e -#define GC_USB_GAHBCFG_HBSTLEN_SIZE 0x4 -#define GC_USB_GAHBCFG_HBSTLEN_DEFAULT 0x0 -#define GC_USB_GAHBCFG_HBSTLEN_OFFSET 0x8 -#define GC_USB_GAHBCFG_DMAEN_LSB 0x5 -#define GC_USB_GAHBCFG_DMAEN_MASK 0x20 -#define GC_USB_GAHBCFG_DMAEN_SIZE 0x1 -#define GC_USB_GAHBCFG_DMAEN_DEFAULT 0x0 -#define GC_USB_GAHBCFG_DMAEN_OFFSET 0x8 +#define GC_USB_GCCFG_OFFSET 0x38 +#define GC_USB_GCCFG_DEFAULT 0x0 +#define GC_USB_GUID_OFFSET 0x3c +#define GC_USB_GUID_DEFAULT 0x0 +#define GC_USB_GSNPSID_OFFSET 0x40 +#define GC_USB_GSNPSID_DEFAULT 0x0 +#define GC_USB_GHWCFG1_OFFSET 0x44 +#define GC_USB_GHWCFG1_DEFAULT 0x0 +#define GC_USB_GHWCFG2_OFFSET 0x48 +#define GC_USB_GHWCFG2_DEFAULT 0x0 +#define GC_USB_GHWCFG3_OFFSET 0x4c +#define GC_USB_GHWCFG3_DEFAULT 0x0 +#define GC_USB_GHWCFG4_OFFSET 0x50 +#define GC_USB_GHWCFG4_DEFAULT 0x0 +#define GC_USB_GDFIFOCFG_OFFSET 0x5c +#define GC_USB_GDFIFOCFG_DEFAULT 0x0 +#define GC_USB_DIEPTXF1_OFFSET 0x104 +#define GC_USB_DIEPTXF1_DEFAULT 0x1000 +#define GC_USB_DIEPTXF2_OFFSET 0x108 +#define GC_USB_DIEPTXF2_DEFAULT 0x0 +#define GC_USB_DIEPTXF3_OFFSET 0x10c +#define GC_USB_DIEPTXF3_DEFAULT 0x0 +#define GC_USB_DIEPTXF4_OFFSET 0x110 +#define GC_USB_DIEPTXF4_DEFAULT 0x0 +#define GC_USB_DIEPTXF5_OFFSET 0x114 +#define GC_USB_DIEPTXF5_DEFAULT 0x0 +#define GC_USB_DIEPTXF6_OFFSET 0x118 +#define GC_USB_DIEPTXF6_DEFAULT 0x0 +#define GC_USB_DIEPTXF7_OFFSET 0x11c +#define GC_USB_DIEPTXF7_DEFAULT 0x0 +#define GC_USB_DIEPTXF8_OFFSET 0x120 +#define GC_USB_DIEPTXF8_DEFAULT 0x0 +#define GC_USB_DIEPTXF9_OFFSET 0x124 +#define GC_USB_DIEPTXF9_DEFAULT 0x0 +#define GC_USB_DIEPTXF10_OFFSET 0x128 +#define GC_USB_DIEPTXF10_DEFAULT 0x0 +#define GC_USB_DIEPTXF11_OFFSET 0x12c +#define GC_USB_DIEPTXF11_DEFAULT 0x0 +#define GC_USB_DIEPTXF12_OFFSET 0x130 +#define GC_USB_DIEPTXF12_DEFAULT 0x0 +#define GC_USB_DIEPTXF13_OFFSET 0x134 +#define GC_USB_DIEPTXF13_DEFAULT 0x0 +#define GC_USB_DIEPTXF14_OFFSET 0x138 +#define GC_USB_DIEPTXF14_DEFAULT 0x0 +#define GC_USB_DIEPTXF15_OFFSET 0x13c +#define GC_USB_DIEPTXF15_DEFAULT 0x0 +#define GC_USB_DCFG_OFFSET 0x800 +#define GC_USB_DCFG_DEFAULT 0x8000000 +#define GC_USB_DCTL_OFFSET 0x804 +#define GC_USB_DCTL_DEFAULT 0x0 +#define GC_USB_DSTS_OFFSET 0x808 +#define GC_USB_DSTS_DEFAULT 0x0 +#define GC_USB_DIEPMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_DEFAULT 0x80 +#define GC_USB_DOEPMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_DEFAULT 0x0 +#define GC_USB_DAINT_OFFSET 0x818 +#define GC_USB_DAINT_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OFFSET 0x81c +#define GC_USB_DAINTMSK_DEFAULT 0x0 +#define GC_USB_DVBUSDIS_OFFSET 0x828 +#define GC_USB_DVBUSDIS_DEFAULT 0x0 +#define GC_USB_DVBUSPULSE_OFFSET 0x82c +#define GC_USB_DVBUSPULSE_DEFAULT 0x0 +#define GC_USB_DTHRCTL_OFFSET 0x830 +#define GC_USB_DTHRCTL_DEFAULT 0x0 +#define GC_USB_DIEPEMPMSK_OFFSET 0x834 +#define GC_USB_DIEPEMPMSK_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_OFFSET 0x900 +#define GC_USB_DIEPCTL0_DEFAULT 0x0 +#define GC_USB_DIEPINT0_OFFSET 0x908 +#define GC_USB_DIEPINT0_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ0_OFFSET 0x910 +#define GC_USB_DIEPTSIZ0_DEFAULT 0x0 +#define GC_USB_DIEPDMA0_OFFSET 0x914 +#define GC_USB_DIEPDMA0_DEFAULT 0x0 +#define GC_USB_DTXFSTS0_OFFSET 0x918 +#define GC_USB_DTXFSTS0_DEFAULT 0x0 +#define GC_USB_DIEPDMAB0_OFFSET 0x91c +#define GC_USB_DIEPDMAB0_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_OFFSET 0x920 +#define GC_USB_DIEPCTL1_DEFAULT 0x0 +#define GC_USB_DIEPINT1_OFFSET 0x928 +#define GC_USB_DIEPINT1_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ1_OFFSET 0x930 +#define GC_USB_DIEPTSIZ1_DEFAULT 0x0 +#define GC_USB_DIEPDMA1_OFFSET 0x934 +#define GC_USB_DIEPDMA1_DEFAULT 0x0 +#define GC_USB_DTXFSTS1_OFFSET 0x938 +#define GC_USB_DTXFSTS1_DEFAULT 0x0 +#define GC_USB_DIEPDMAB1_OFFSET 0x93c +#define GC_USB_DIEPDMAB1_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_OFFSET 0x940 +#define GC_USB_DIEPCTL2_DEFAULT 0x0 +#define GC_USB_DIEPINT2_OFFSET 0x948 +#define GC_USB_DIEPINT2_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ2_OFFSET 0x950 +#define GC_USB_DIEPTSIZ2_DEFAULT 0x0 +#define GC_USB_DIEPDMA2_OFFSET 0x954 +#define GC_USB_DIEPDMA2_DEFAULT 0x0 +#define GC_USB_DTXFSTS2_OFFSET 0x958 +#define GC_USB_DTXFSTS2_DEFAULT 0x0 +#define GC_USB_DIEPDMAB2_OFFSET 0x95c +#define GC_USB_DIEPDMAB2_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_OFFSET 0x960 +#define GC_USB_DIEPCTL3_DEFAULT 0x0 +#define GC_USB_DIEPINT3_OFFSET 0x968 +#define GC_USB_DIEPINT3_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ3_OFFSET 0x970 +#define GC_USB_DIEPTSIZ3_DEFAULT 0x0 +#define GC_USB_DIEPDMA3_OFFSET 0x974 +#define GC_USB_DIEPDMA3_DEFAULT 0x0 +#define GC_USB_DTXFSTS3_OFFSET 0x978 +#define GC_USB_DTXFSTS3_DEFAULT 0x0 +#define GC_USB_DIEPDMAB3_OFFSET 0x97c +#define GC_USB_DIEPDMAB3_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_OFFSET 0x980 +#define GC_USB_DIEPCTL4_DEFAULT 0x0 +#define GC_USB_DIEPINT4_OFFSET 0x988 +#define GC_USB_DIEPINT4_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ4_OFFSET 0x990 +#define GC_USB_DIEPTSIZ4_DEFAULT 0x0 +#define GC_USB_DIEPDMA4_OFFSET 0x994 +#define GC_USB_DIEPDMA4_DEFAULT 0x0 +#define GC_USB_DTXFSTS4_OFFSET 0x998 +#define GC_USB_DTXFSTS4_DEFAULT 0x0 +#define GC_USB_DIEPDMAB4_OFFSET 0x99c +#define GC_USB_DIEPDMAB4_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_DEFAULT 0x0 +#define GC_USB_DIEPINT5_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ5_OFFSET 0x9b0 +#define GC_USB_DIEPTSIZ5_DEFAULT 0x0 +#define GC_USB_DIEPDMA5_OFFSET 0x9b4 +#define GC_USB_DIEPDMA5_DEFAULT 0x0 +#define GC_USB_DTXFSTS5_OFFSET 0x9b8 +#define GC_USB_DTXFSTS5_DEFAULT 0x0 +#define GC_USB_DIEPDMAB5_OFFSET 0x9bc +#define GC_USB_DIEPDMAB5_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_DEFAULT 0x0 +#define GC_USB_DIEPINT6_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ6_OFFSET 0x9d0 +#define GC_USB_DIEPTSIZ6_DEFAULT 0x0 +#define GC_USB_DIEPDMA6_OFFSET 0x9d4 +#define GC_USB_DIEPDMA6_DEFAULT 0x0 +#define GC_USB_DTXFSTS6_OFFSET 0x9d8 +#define GC_USB_DTXFSTS6_DEFAULT 0x0 +#define GC_USB_DIEPDMAB6_OFFSET 0x9dc +#define GC_USB_DIEPDMAB6_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_DEFAULT 0x0 +#define GC_USB_DIEPINT7_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ7_OFFSET 0x9f0 +#define GC_USB_DIEPTSIZ7_DEFAULT 0x0 +#define GC_USB_DIEPDMA7_OFFSET 0x9f4 +#define GC_USB_DIEPDMA7_DEFAULT 0x0 +#define GC_USB_DTXFSTS7_OFFSET 0x9f8 +#define GC_USB_DTXFSTS7_DEFAULT 0x0 +#define GC_USB_DIEPDMAB7_OFFSET 0x9fc +#define GC_USB_DIEPDMAB7_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_DEFAULT 0x0 +#define GC_USB_DIEPINT8_OFFSET 0xa08 +#define GC_USB_DIEPINT8_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ8_OFFSET 0xa10 +#define GC_USB_DIEPTSIZ8_DEFAULT 0x0 +#define GC_USB_DIEPDMA8_OFFSET 0xa14 +#define GC_USB_DIEPDMA8_DEFAULT 0x0 +#define GC_USB_DTXFSTS8_OFFSET 0xa18 +#define GC_USB_DTXFSTS8_DEFAULT 0x0 +#define GC_USB_DIEPDMAB8_OFFSET 0xa1c +#define GC_USB_DIEPDMAB8_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_DEFAULT 0x0 +#define GC_USB_DIEPINT9_OFFSET 0xa28 +#define GC_USB_DIEPINT9_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ9_OFFSET 0xa30 +#define GC_USB_DIEPTSIZ9_DEFAULT 0x0 +#define GC_USB_DIEPDMA9_OFFSET 0xa34 +#define GC_USB_DIEPDMA9_DEFAULT 0x0 +#define GC_USB_DTXFSTS9_OFFSET 0xa38 +#define GC_USB_DTXFSTS9_DEFAULT 0x0 +#define GC_USB_DIEPDMAB9_OFFSET 0xa3c +#define GC_USB_DIEPDMAB9_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_DEFAULT 0x0 +#define GC_USB_DIEPINT10_OFFSET 0xa48 +#define GC_USB_DIEPINT10_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ10_OFFSET 0xa50 +#define GC_USB_DIEPTSIZ10_DEFAULT 0x0 +#define GC_USB_DIEPDMA10_OFFSET 0xa54 +#define GC_USB_DIEPDMA10_DEFAULT 0x0 +#define GC_USB_DTXFSTS10_OFFSET 0xa58 +#define GC_USB_DTXFSTS10_DEFAULT 0x0 +#define GC_USB_DIEPDMAB10_OFFSET 0xa5c +#define GC_USB_DIEPDMAB10_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_DEFAULT 0x0 +#define GC_USB_DIEPINT11_OFFSET 0xa68 +#define GC_USB_DIEPINT11_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ11_OFFSET 0xa70 +#define GC_USB_DIEPTSIZ11_DEFAULT 0x0 +#define GC_USB_DIEPDMA11_OFFSET 0xa74 +#define GC_USB_DIEPDMA11_DEFAULT 0x0 +#define GC_USB_DTXFSTS11_OFFSET 0xa78 +#define GC_USB_DTXFSTS11_DEFAULT 0x0 +#define GC_USB_DIEPDMAB11_OFFSET 0xa7c +#define GC_USB_DIEPDMAB11_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_DEFAULT 0x0 +#define GC_USB_DIEPINT12_OFFSET 0xa88 +#define GC_USB_DIEPINT12_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ12_OFFSET 0xa90 +#define GC_USB_DIEPTSIZ12_DEFAULT 0x0 +#define GC_USB_DIEPDMA12_OFFSET 0xa94 +#define GC_USB_DIEPDMA12_DEFAULT 0x0 +#define GC_USB_DTXFSTS12_OFFSET 0xa98 +#define GC_USB_DTXFSTS12_DEFAULT 0x0 +#define GC_USB_DIEPDMAB12_OFFSET 0xa9c +#define GC_USB_DIEPDMAB12_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_DEFAULT 0x0 +#define GC_USB_DIEPINT13_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ13_OFFSET 0xab0 +#define GC_USB_DIEPTSIZ13_DEFAULT 0x0 +#define GC_USB_DIEPDMA13_OFFSET 0xab4 +#define GC_USB_DIEPDMA13_DEFAULT 0x0 +#define GC_USB_DTXFSTS13_OFFSET 0xab8 +#define GC_USB_DTXFSTS13_DEFAULT 0x0 +#define GC_USB_DIEPDMAB13_OFFSET 0xabc +#define GC_USB_DIEPDMAB13_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_DEFAULT 0x0 +#define GC_USB_DIEPINT14_OFFSET 0xac8 +#define GC_USB_DIEPINT14_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ14_OFFSET 0xad0 +#define GC_USB_DIEPTSIZ14_DEFAULT 0x0 +#define GC_USB_DIEPDMA14_OFFSET 0xad4 +#define GC_USB_DIEPDMA14_DEFAULT 0x0 +#define GC_USB_DTXFSTS14_OFFSET 0xad8 +#define GC_USB_DTXFSTS14_DEFAULT 0x0 +#define GC_USB_DIEPDMAB14_OFFSET 0xadc +#define GC_USB_DIEPDMAB14_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_DEFAULT 0x0 +#define GC_USB_DIEPINT15_OFFSET 0xae8 +#define GC_USB_DIEPINT15_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ15_OFFSET 0xaf0 +#define GC_USB_DIEPTSIZ15_DEFAULT 0x0 +#define GC_USB_DIEPDMA15_OFFSET 0xaf4 +#define GC_USB_DIEPDMA15_DEFAULT 0x0 +#define GC_USB_DTXFSTS15_OFFSET 0xaf8 +#define GC_USB_DTXFSTS15_DEFAULT 0x0 +#define GC_USB_DIEPDMAB15_OFFSET 0xafc +#define GC_USB_DIEPDMAB15_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_DEFAULT 0x0 +#define GC_USB_DOEPINT0_OFFSET 0xb08 +#define GC_USB_DOEPINT0_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ0_OFFSET 0xb10 +#define GC_USB_DOEPTSIZ0_DEFAULT 0x0 +#define GC_USB_DOEPDMA0_OFFSET 0xb14 +#define GC_USB_DOEPDMA0_DEFAULT 0x0 +#define GC_USB_DOEPDMAB0_OFFSET 0xb1c +#define GC_USB_DOEPDMAB0_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_DEFAULT 0x0 +#define GC_USB_DOEPINT1_OFFSET 0xb28 +#define GC_USB_DOEPINT1_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ1_OFFSET 0xb30 +#define GC_USB_DOEPTSIZ1_DEFAULT 0x0 +#define GC_USB_DOEPDMA1_OFFSET 0xb34 +#define GC_USB_DOEPDMA1_DEFAULT 0x0 +#define GC_USB_DOEPDMAB1_OFFSET 0xb3c +#define GC_USB_DOEPDMAB1_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_DEFAULT 0x0 +#define GC_USB_DOEPINT2_OFFSET 0xb48 +#define GC_USB_DOEPINT2_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ2_OFFSET 0xb50 +#define GC_USB_DOEPTSIZ2_DEFAULT 0x0 +#define GC_USB_DOEPDMA2_OFFSET 0xb54 +#define GC_USB_DOEPDMA2_DEFAULT 0x0 +#define GC_USB_DOEPDMAB2_OFFSET 0xb5c +#define GC_USB_DOEPDMAB2_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_DEFAULT 0x0 +#define GC_USB_DOEPINT3_OFFSET 0xb68 +#define GC_USB_DOEPINT3_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ3_OFFSET 0xb70 +#define GC_USB_DOEPTSIZ3_DEFAULT 0x0 +#define GC_USB_DOEPDMA3_OFFSET 0xb74 +#define GC_USB_DOEPDMA3_DEFAULT 0x0 +#define GC_USB_DOEPDMAB3_OFFSET 0xb7c +#define GC_USB_DOEPDMAB3_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_DEFAULT 0x0 +#define GC_USB_DOEPINT4_OFFSET 0xb88 +#define GC_USB_DOEPINT4_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ4_OFFSET 0xb90 +#define GC_USB_DOEPTSIZ4_DEFAULT 0x0 +#define GC_USB_DOEPDMA4_OFFSET 0xb94 +#define GC_USB_DOEPDMA4_DEFAULT 0x0 +#define GC_USB_DOEPDMAB4_OFFSET 0xb9c +#define GC_USB_DOEPDMAB4_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_DEFAULT 0x0 +#define GC_USB_DOEPINT5_OFFSET 0xba8 +#define GC_USB_DOEPINT5_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ5_OFFSET 0xbb0 +#define GC_USB_DOEPTSIZ5_DEFAULT 0x0 +#define GC_USB_DOEPDMA5_OFFSET 0xbb4 +#define GC_USB_DOEPDMA5_DEFAULT 0x0 +#define GC_USB_DOEPDMAB5_OFFSET 0xbbc +#define GC_USB_DOEPDMAB5_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_DEFAULT 0x0 +#define GC_USB_DOEPINT6_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ6_OFFSET 0xbd0 +#define GC_USB_DOEPTSIZ6_DEFAULT 0x0 +#define GC_USB_DOEPDMA6_OFFSET 0xbd4 +#define GC_USB_DOEPDMA6_DEFAULT 0x0 +#define GC_USB_DOEPDMAB6_OFFSET 0xbdc +#define GC_USB_DOEPDMAB6_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_DEFAULT 0x0 +#define GC_USB_DOEPINT7_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ7_OFFSET 0xbf0 +#define GC_USB_DOEPTSIZ7_DEFAULT 0x0 +#define GC_USB_DOEPDMA7_OFFSET 0xbf4 +#define GC_USB_DOEPDMA7_DEFAULT 0x0 +#define GC_USB_DOEPDMAB7_OFFSET 0xbfc +#define GC_USB_DOEPDMAB7_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_DEFAULT 0x0 +#define GC_USB_DOEPINT8_OFFSET 0xc08 +#define GC_USB_DOEPINT8_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ8_OFFSET 0xc10 +#define GC_USB_DOEPTSIZ8_DEFAULT 0x0 +#define GC_USB_DOEPDMA8_OFFSET 0xc14 +#define GC_USB_DOEPDMA8_DEFAULT 0x0 +#define GC_USB_DOEPDMAB8_OFFSET 0xc1c +#define GC_USB_DOEPDMAB8_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_DEFAULT 0x0 +#define GC_USB_DOEPINT9_OFFSET 0xc28 +#define GC_USB_DOEPINT9_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ9_OFFSET 0xc30 +#define GC_USB_DOEPTSIZ9_DEFAULT 0x0 +#define GC_USB_DOEPDMA9_OFFSET 0xc34 +#define GC_USB_DOEPDMA9_DEFAULT 0x0 +#define GC_USB_DOEPDMAB9_OFFSET 0xc3c +#define GC_USB_DOEPDMAB9_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_DEFAULT 0x0 +#define GC_USB_DOEPINT10_OFFSET 0xc48 +#define GC_USB_DOEPINT10_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ10_OFFSET 0xc50 +#define GC_USB_DOEPTSIZ10_DEFAULT 0x0 +#define GC_USB_DOEPDMA10_OFFSET 0xc54 +#define GC_USB_DOEPDMA10_DEFAULT 0x0 +#define GC_USB_DOEPDMAB10_OFFSET 0xc5c +#define GC_USB_DOEPDMAB10_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_DEFAULT 0x0 +#define GC_USB_DOEPINT11_OFFSET 0xc68 +#define GC_USB_DOEPINT11_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ11_OFFSET 0xc70 +#define GC_USB_DOEPTSIZ11_DEFAULT 0x0 +#define GC_USB_DOEPDMA11_OFFSET 0xc74 +#define GC_USB_DOEPDMA11_DEFAULT 0x0 +#define GC_USB_DOEPDMAB11_OFFSET 0xc7c +#define GC_USB_DOEPDMAB11_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_DEFAULT 0x0 +#define GC_USB_DOEPINT12_OFFSET 0xc88 +#define GC_USB_DOEPINT12_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ12_OFFSET 0xc90 +#define GC_USB_DOEPTSIZ12_DEFAULT 0x0 +#define GC_USB_DOEPDMA12_OFFSET 0xc94 +#define GC_USB_DOEPDMA12_DEFAULT 0x0 +#define GC_USB_DOEPDMAB12_OFFSET 0xc9c +#define GC_USB_DOEPDMAB12_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_DEFAULT 0x0 +#define GC_USB_DOEPINT13_OFFSET 0xca8 +#define GC_USB_DOEPINT13_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ13_OFFSET 0xcb0 +#define GC_USB_DOEPTSIZ13_DEFAULT 0x0 +#define GC_USB_DOEPDMA13_OFFSET 0xcb4 +#define GC_USB_DOEPDMA13_DEFAULT 0x0 +#define GC_USB_DOEPDMAB13_OFFSET 0xcbc +#define GC_USB_DOEPDMAB13_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_DEFAULT 0x0 +#define GC_USB_DOEPINT14_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ14_OFFSET 0xcd0 +#define GC_USB_DOEPTSIZ14_DEFAULT 0x0 +#define GC_USB_DOEPDMA14_OFFSET 0xcd4 +#define GC_USB_DOEPDMA14_DEFAULT 0x0 +#define GC_USB_DOEPDMAB14_OFFSET 0xcdc +#define GC_USB_DOEPDMAB14_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_DEFAULT 0x0 +#define GC_USB_DOEPINT15_OFFSET 0xce8 +#define GC_USB_DOEPINT15_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ15_OFFSET 0xcf0 +#define GC_USB_DOEPTSIZ15_DEFAULT 0x0 +#define GC_USB_DOEPDMA15_OFFSET 0xcf4 +#define GC_USB_DOEPDMA15_DEFAULT 0x0 +#define GC_USB_DOEPDMAB15_OFFSET 0xcfc +#define GC_USB_DOEPDMAB15_DEFAULT 0x0 +#define GC_USB_PCGCCTL_OFFSET 0xe00 +#define GC_USB_PCGCCTL_DEFAULT 0x0 +#define GC_USB_DFIFO_OFFSET 0x20000 +#define GC_USB_GOTGCTL_BVALIDOVEN_LSB 0x6 +#define GC_USB_GOTGCTL_BVALIDOVEN_MASK 0x40 +#define GC_USB_GOTGCTL_BVALIDOVEN_SIZE 0x1 +#define GC_USB_GOTGCTL_BVALIDOVEN_DEFAULT 0x0 +#define GC_USB_GOTGCTL_BVALIDOVEN_OFFSET 0x0 +#define GC_USB_GOTGCTL_BVALIDOVVAL_LSB 0x7 +#define GC_USB_GOTGCTL_BVALIDOVVAL_MASK 0x80 +#define GC_USB_GOTGCTL_BVALIDOVVAL_SIZE 0x1 +#define GC_USB_GOTGCTL_BVALIDOVVAL_DEFAULT 0x0 +#define GC_USB_GOTGCTL_BVALIDOVVAL_OFFSET 0x0 +#define GC_USB_GOTGCTL_CONIDSTS_LSB 0x10 +#define GC_USB_GOTGCTL_CONIDSTS_MASK 0x10000 +#define GC_USB_GOTGCTL_CONIDSTS_SIZE 0x1 +#define GC_USB_GOTGCTL_CONIDSTS_DEFAULT 0x0 +#define GC_USB_GOTGCTL_CONIDSTS_OFFSET 0x0 +#define GC_USB_GOTGCTL_BSESVLD_LSB 0x13 +#define GC_USB_GOTGCTL_BSESVLD_MASK 0x80000 +#define GC_USB_GOTGCTL_BSESVLD_SIZE 0x1 +#define GC_USB_GOTGCTL_BSESVLD_DEFAULT 0x0 +#define GC_USB_GOTGCTL_BSESVLD_OFFSET 0x0 +#define GC_USB_GOTGCTL_OTGVER_LSB 0x14 +#define GC_USB_GOTGCTL_OTGVER_MASK 0x100000 +#define GC_USB_GOTGCTL_OTGVER_SIZE 0x1 +#define GC_USB_GOTGCTL_OTGVER_DEFAULT 0x0 +#define GC_USB_GOTGCTL_OTGVER_OFFSET 0x0 +#define GC_USB_GOTGCTL_CURMOD_LSB 0x15 +#define GC_USB_GOTGCTL_CURMOD_MASK 0x200000 +#define GC_USB_GOTGCTL_CURMOD_SIZE 0x1 +#define GC_USB_GOTGCTL_CURMOD_DEFAULT 0x0 +#define GC_USB_GOTGCTL_CURMOD_OFFSET 0x0 +#define GC_USB_GOTGINT_SESENDDET_LSB 0x2 +#define GC_USB_GOTGINT_SESENDDET_MASK 0x4 +#define GC_USB_GOTGINT_SESENDDET_SIZE 0x1 +#define GC_USB_GOTGINT_SESENDDET_DEFAULT 0x0 +#define GC_USB_GOTGINT_SESENDDET_OFFSET 0x4 +#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_LSB 0x8 +#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_MASK 0x100 +#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_SIZE 0x1 +#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT 0x0 +#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_OFFSET 0x4 +#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_LSB 0x9 +#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_MASK 0x200 +#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_SIZE 0x1 +#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT 0x0 +#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_OFFSET 0x4 +#define GC_USB_GOTGINT_HSTNEGDET_LSB 0x11 +#define GC_USB_GOTGINT_HSTNEGDET_MASK 0x20000 +#define GC_USB_GOTGINT_HSTNEGDET_SIZE 0x1 +#define GC_USB_GOTGINT_HSTNEGDET_DEFAULT 0x0 +#define GC_USB_GOTGINT_HSTNEGDET_OFFSET 0x4 +#define GC_USB_GOTGINT_ADEVTOUTCHG_LSB 0x12 +#define GC_USB_GOTGINT_ADEVTOUTCHG_MASK 0x40000 +#define GC_USB_GOTGINT_ADEVTOUTCHG_SIZE 0x1 +#define GC_USB_GOTGINT_ADEVTOUTCHG_DEFAULT 0x0 +#define GC_USB_GOTGINT_ADEVTOUTCHG_OFFSET 0x4 +#define GC_USB_GAHBCFG_GLBLINTRMSK_LSB 0x0 +#define GC_USB_GAHBCFG_GLBLINTRMSK_MASK 0x1 +#define GC_USB_GAHBCFG_GLBLINTRMSK_SIZE 0x1 +#define GC_USB_GAHBCFG_GLBLINTRMSK_DEFAULT 0x0 +#define GC_USB_GAHBCFG_GLBLINTRMSK_OFFSET 0x8 +#define GC_USB_GAHBCFG_HBSTLEN_LSB 0x1 +#define GC_USB_GAHBCFG_HBSTLEN_MASK 0x1e +#define GC_USB_GAHBCFG_HBSTLEN_SIZE 0x4 +#define GC_USB_GAHBCFG_HBSTLEN_DEFAULT 0x0 +#define GC_USB_GAHBCFG_HBSTLEN_OFFSET 0x8 +#define GC_USB_GAHBCFG_DMAEN_LSB 0x5 +#define GC_USB_GAHBCFG_DMAEN_MASK 0x20 +#define GC_USB_GAHBCFG_DMAEN_SIZE 0x1 +#define GC_USB_GAHBCFG_DMAEN_DEFAULT 0x0 +#define GC_USB_GAHBCFG_DMAEN_OFFSET 0x8 -#define GC_USB_GAHBCFG_NPTXFEMPLVL_LSB 0x7 -#define GC_USB_GAHBCFG_NPTXFEMPLVL_MASK 0x80 -#define GC_USB_GAHBCFG_NPTXFEMPLVL_SIZE 0x1 -#define GC_USB_GAHBCFG_NPTXFEMPLVL_DEFAULT 0x0 -#define GC_USB_GAHBCFG_NPTXFEMPLVL_OFFSET 0x8 +#define GC_USB_GAHBCFG_NPTXFEMPLVL_LSB 0x7 +#define GC_USB_GAHBCFG_NPTXFEMPLVL_MASK 0x80 +#define GC_USB_GAHBCFG_NPTXFEMPLVL_SIZE 0x1 +#define GC_USB_GAHBCFG_NPTXFEMPLVL_DEFAULT 0x0 +#define GC_USB_GAHBCFG_NPTXFEMPLVL_OFFSET 0x8 -#define GC_USB_GAHBCFG_REMMEMSUPP_LSB 0x15 -#define GC_USB_GAHBCFG_REMMEMSUPP_MASK 0x200000 -#define GC_USB_GAHBCFG_REMMEMSUPP_SIZE 0x1 -#define GC_USB_GAHBCFG_REMMEMSUPP_DEFAULT 0x0 -#define GC_USB_GAHBCFG_REMMEMSUPP_OFFSET 0x8 -#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_LSB 0x16 -#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_MASK 0x400000 -#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_SIZE 0x1 -#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT 0x0 -#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_OFFSET 0x8 -#define GC_USB_GAHBCFG_AHBSINGLE_LSB 0x17 -#define GC_USB_GAHBCFG_AHBSINGLE_MASK 0x800000 -#define GC_USB_GAHBCFG_AHBSINGLE_SIZE 0x1 -#define GC_USB_GAHBCFG_AHBSINGLE_DEFAULT 0x0 -#define GC_USB_GAHBCFG_AHBSINGLE_OFFSET 0x8 -#define GC_USB_GAHBCFG_INVDESCENDIANESS_LSB 0x18 -#define GC_USB_GAHBCFG_INVDESCENDIANESS_MASK 0x1000000 -#define GC_USB_GAHBCFG_INVDESCENDIANESS_SIZE 0x1 -#define GC_USB_GAHBCFG_INVDESCENDIANESS_DEFAULT 0x0 -#define GC_USB_GAHBCFG_INVDESCENDIANESS_OFFSET 0x8 -#define GC_USB_GUSBCFG_TOUTCAL_LSB 0x0 -#define GC_USB_GUSBCFG_TOUTCAL_MASK 0x7 -#define GC_USB_GUSBCFG_TOUTCAL_SIZE 0x3 -#define GC_USB_GUSBCFG_TOUTCAL_DEFAULT 0x0 -#define GC_USB_GUSBCFG_TOUTCAL_OFFSET 0xc +#define GC_USB_GAHBCFG_REMMEMSUPP_LSB 0x15 +#define GC_USB_GAHBCFG_REMMEMSUPP_MASK 0x200000 +#define GC_USB_GAHBCFG_REMMEMSUPP_SIZE 0x1 +#define GC_USB_GAHBCFG_REMMEMSUPP_DEFAULT 0x0 +#define GC_USB_GAHBCFG_REMMEMSUPP_OFFSET 0x8 +#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_LSB 0x16 +#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_MASK 0x400000 +#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_SIZE 0x1 +#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT 0x0 +#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_OFFSET 0x8 +#define GC_USB_GAHBCFG_AHBSINGLE_LSB 0x17 +#define GC_USB_GAHBCFG_AHBSINGLE_MASK 0x800000 +#define GC_USB_GAHBCFG_AHBSINGLE_SIZE 0x1 +#define GC_USB_GAHBCFG_AHBSINGLE_DEFAULT 0x0 +#define GC_USB_GAHBCFG_AHBSINGLE_OFFSET 0x8 +#define GC_USB_GAHBCFG_INVDESCENDIANESS_LSB 0x18 +#define GC_USB_GAHBCFG_INVDESCENDIANESS_MASK 0x1000000 +#define GC_USB_GAHBCFG_INVDESCENDIANESS_SIZE 0x1 +#define GC_USB_GAHBCFG_INVDESCENDIANESS_DEFAULT 0x0 +#define GC_USB_GAHBCFG_INVDESCENDIANESS_OFFSET 0x8 +#define GC_USB_GUSBCFG_TOUTCAL_LSB 0x0 +#define GC_USB_GUSBCFG_TOUTCAL_MASK 0x7 +#define GC_USB_GUSBCFG_TOUTCAL_SIZE 0x3 +#define GC_USB_GUSBCFG_TOUTCAL_DEFAULT 0x0 +#define GC_USB_GUSBCFG_TOUTCAL_OFFSET 0xc -#define GC_USB_GUSBCFG_USBTRDTIM_LSB 0xa -#define GC_USB_GUSBCFG_USBTRDTIM_MASK 0x3c00 -#define GC_USB_GUSBCFG_USBTRDTIM_SIZE 0x4 -#define GC_USB_GUSBCFG_USBTRDTIM_DEFAULT 0x0 -#define GC_USB_GUSBCFG_USBTRDTIM_OFFSET 0xc -#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_LSB 15 -#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_MASK 0x8000 -#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_SIZE 0x1 -#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_DEFAULT 0x0 -#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_OFFSET 0xc -#define GC_USB_GUSBCFG_ULPIFSLS_LSB 17 -#define GC_USB_GUSBCFG_ULPIFSLS_MASK 0x20000 -#define GC_USB_GUSBCFG_ULPIFSLS_SIZE 0x1 -#define GC_USB_GUSBCFG_ULPIFSLS_DEFAULT 0x0 -#define GC_USB_GUSBCFG_ULPIFSLS_OFFSET 0xc -#define GC_USB_GUSBCFG_ULPIAUTORES_LSB 18 -#define GC_USB_GUSBCFG_ULPIAUTORES_MASK 0x40000 -#define GC_USB_GUSBCFG_ULPIAUTORES_SIZE 0x1 -#define GC_USB_GUSBCFG_ULPIAUTORES_DEFAULT 0x0 -#define GC_USB_GUSBCFG_ULPIAUTORES_OFFSET 0xc -#define GC_USB_GUSBCFG_ULPICLKSUSM_LSB 19 -#define GC_USB_GUSBCFG_ULPICLKSUSM_MASK 0x80000 -#define GC_USB_GUSBCFG_ULPICLKSUSM_SIZE 0x1 -#define GC_USB_GUSBCFG_ULPICLKSUSM_DEFAULT 0x0 -#define GC_USB_GUSBCFG_ULPICLKSUSM_OFFSET 0xc +#define GC_USB_GUSBCFG_USBTRDTIM_LSB 0xa +#define GC_USB_GUSBCFG_USBTRDTIM_MASK 0x3c00 +#define GC_USB_GUSBCFG_USBTRDTIM_SIZE 0x4 +#define GC_USB_GUSBCFG_USBTRDTIM_DEFAULT 0x0 +#define GC_USB_GUSBCFG_USBTRDTIM_OFFSET 0xc +#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_LSB 15 +#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_MASK 0x8000 +#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_SIZE 0x1 +#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_DEFAULT 0x0 +#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_OFFSET 0xc +#define GC_USB_GUSBCFG_ULPIFSLS_LSB 17 +#define GC_USB_GUSBCFG_ULPIFSLS_MASK 0x20000 +#define GC_USB_GUSBCFG_ULPIFSLS_SIZE 0x1 +#define GC_USB_GUSBCFG_ULPIFSLS_DEFAULT 0x0 +#define GC_USB_GUSBCFG_ULPIFSLS_OFFSET 0xc +#define GC_USB_GUSBCFG_ULPIAUTORES_LSB 18 +#define GC_USB_GUSBCFG_ULPIAUTORES_MASK 0x40000 +#define GC_USB_GUSBCFG_ULPIAUTORES_SIZE 0x1 +#define GC_USB_GUSBCFG_ULPIAUTORES_DEFAULT 0x0 +#define GC_USB_GUSBCFG_ULPIAUTORES_OFFSET 0xc +#define GC_USB_GUSBCFG_ULPICLKSUSM_LSB 19 +#define GC_USB_GUSBCFG_ULPICLKSUSM_MASK 0x80000 +#define GC_USB_GUSBCFG_ULPICLKSUSM_SIZE 0x1 +#define GC_USB_GUSBCFG_ULPICLKSUSM_DEFAULT 0x0 +#define GC_USB_GUSBCFG_ULPICLKSUSM_OFFSET 0xc -#define GC_USB_GUSBCFG_ULPIEVBUSD_LSB 20 -#define GC_USB_GUSBCFG_ULPIEVBUSD_MASK 0x100000 -#define GC_USB_GUSBCFG_ULPIEVBUSD_SIZE 0x1 -#define GC_USB_GUSBCFG_ULPIEVBUSD_DEFAULT 0x0 -#define GC_USB_GUSBCFG_ULPIEVBUSD_OFFSET 0xc +#define GC_USB_GUSBCFG_ULPIEVBUSD_LSB 20 +#define GC_USB_GUSBCFG_ULPIEVBUSD_MASK 0x100000 +#define GC_USB_GUSBCFG_ULPIEVBUSD_SIZE 0x1 +#define GC_USB_GUSBCFG_ULPIEVBUSD_DEFAULT 0x0 +#define GC_USB_GUSBCFG_ULPIEVBUSD_OFFSET 0xc -#define GC_USB_GUSBCFG_ULPIEVBUSI_LSB 21 -#define GC_USB_GUSBCFG_ULPIEVBUSI_MASK 0x200000 -#define GC_USB_GUSBCFG_ULPIEVBUSI_SIZE 0x1 -#define GC_USB_GUSBCFG_ULPIEVBUSI_DEFAULT 0x0 -#define GC_USB_GUSBCFG_ULPIEVBUSI_OFFSET 0xc +#define GC_USB_GUSBCFG_ULPIEVBUSI_LSB 21 +#define GC_USB_GUSBCFG_ULPIEVBUSI_MASK 0x200000 +#define GC_USB_GUSBCFG_ULPIEVBUSI_SIZE 0x1 +#define GC_USB_GUSBCFG_ULPIEVBUSI_DEFAULT 0x0 +#define GC_USB_GUSBCFG_ULPIEVBUSI_OFFSET 0xc -#define GC_USB_GUSBCFG_TERMSELDLPULSE_LSB 22 -#define GC_USB_GUSBCFG_TERMSELDLPULSE_MASK 0x400000 -#define GC_USB_GUSBCFG_TERMSELDLPULSE_SIZE 0x1 -#define GC_USB_GUSBCFG_TERMSELDLPULSE_DEFAULT 0x0 -#define GC_USB_GUSBCFG_TERMSELDLPULSE_OFFSET 0xc +#define GC_USB_GUSBCFG_TERMSELDLPULSE_LSB 22 +#define GC_USB_GUSBCFG_TERMSELDLPULSE_MASK 0x400000 +#define GC_USB_GUSBCFG_TERMSELDLPULSE_SIZE 0x1 +#define GC_USB_GUSBCFG_TERMSELDLPULSE_DEFAULT 0x0 +#define GC_USB_GUSBCFG_TERMSELDLPULSE_OFFSET 0xc -#define GC_USB_GUSBCFG_PCCI_LSB 23 -#define GC_USB_GUSBCFG_PCCI_MASK BIT(23) -#define GC_USB_GUSBCFG_PCCI_SIZE 0x1 -#define GC_USB_GUSBCFG_PCCI_DEFAULT 0x0 -#define GC_USB_GUSBCFG_PCCI_OFFSET 0xc +#define GC_USB_GUSBCFG_PCCI_LSB 23 +#define GC_USB_GUSBCFG_PCCI_MASK BIT(23) +#define GC_USB_GUSBCFG_PCCI_SIZE 0x1 +#define GC_USB_GUSBCFG_PCCI_DEFAULT 0x0 +#define GC_USB_GUSBCFG_PCCI_OFFSET 0xc -#define GC_USB_GUSBCFG_PTCI_LSB 24 -#define GC_USB_GUSBCFG_PTCI_MASK BIT(24) -#define GC_USB_GUSBCFG_PTCI_SIZE 0x1 -#define GC_USB_GUSBCFG_PTCI_DEFAULT 0x0 -#define GC_USB_GUSBCFG_PTCI_OFFSET 0xc +#define GC_USB_GUSBCFG_PTCI_LSB 24 +#define GC_USB_GUSBCFG_PTCI_MASK BIT(24) +#define GC_USB_GUSBCFG_PTCI_SIZE 0x1 +#define GC_USB_GUSBCFG_PTCI_DEFAULT 0x0 +#define GC_USB_GUSBCFG_PTCI_OFFSET 0xc -#define GC_USB_GUSBCFG_ULPIIPD_LSB 25 -#define GC_USB_GUSBCFG_ULPIIPD_MASK BIT(25) -#define GC_USB_GUSBCFG_ULPIIPD_SIZE 0x1 -#define GC_USB_GUSBCFG_ULPIIPD_DEFAULT 0x0 -#define GC_USB_GUSBCFG_ULPIIPD_OFFSET 0xc +#define GC_USB_GUSBCFG_ULPIIPD_LSB 25 +#define GC_USB_GUSBCFG_ULPIIPD_MASK BIT(25) +#define GC_USB_GUSBCFG_ULPIIPD_SIZE 0x1 +#define GC_USB_GUSBCFG_ULPIIPD_DEFAULT 0x0 +#define GC_USB_GUSBCFG_ULPIIPD_OFFSET 0xc -#define GC_USB_GUSBCFG_FHMOD_LSB 29 -#define GC_USB_GUSBCFG_FHMOD_MASK BIT(29) -#define GC_USB_GUSBCFG_FHMOD_SIZE 0x1 -#define GC_USB_GUSBCFG_FHMOD_DEFAULT 0x0 -#define GC_USB_GUSBCFG_FHMOD_OFFSET 0xc +#define GC_USB_GUSBCFG_FHMOD_LSB 29 +#define GC_USB_GUSBCFG_FHMOD_MASK BIT(29) +#define GC_USB_GUSBCFG_FHMOD_SIZE 0x1 +#define GC_USB_GUSBCFG_FHMOD_DEFAULT 0x0 +#define GC_USB_GUSBCFG_FHMOD_OFFSET 0xc -#define GC_USB_GUSBCFG_FDMOD_LSB 30 -#define GC_USB_GUSBCFG_FDMOD_MASK BIT(30) -#define GC_USB_GUSBCFG_FDMOD_SIZE 0x1 -#define GC_USB_GUSBCFG_FDMOD_DEFAULT 0x0 -#define GC_USB_GUSBCFG_FDMOD_OFFSET 0xc +#define GC_USB_GUSBCFG_FDMOD_LSB 30 +#define GC_USB_GUSBCFG_FDMOD_MASK BIT(30) +#define GC_USB_GUSBCFG_FDMOD_SIZE 0x1 +#define GC_USB_GUSBCFG_FDMOD_DEFAULT 0x0 +#define GC_USB_GUSBCFG_FDMOD_OFFSET 0xc -#define GC_USB_GRSTCTL_CSFTRST_LSB 0x0 -#define GC_USB_GRSTCTL_CSFTRST_MASK 0x1 -#define GC_USB_GRSTCTL_CSFTRST_SIZE 0x1 -#define GC_USB_GRSTCTL_CSFTRST_DEFAULT 0x0 -#define GC_USB_GRSTCTL_CSFTRST_OFFSET 0x10 -#define GC_USB_GRSTCTL_PIUFSSFTRST_LSB 0x1 -#define GC_USB_GRSTCTL_PIUFSSFTRST_MASK 0x2 -#define GC_USB_GRSTCTL_PIUFSSFTRST_SIZE 0x1 -#define GC_USB_GRSTCTL_PIUFSSFTRST_DEFAULT 0x0 -#define GC_USB_GRSTCTL_PIUFSSFTRST_OFFSET 0x10 -#define GC_USB_GRSTCTL_RXFFLSH_LSB 0x4 -#define GC_USB_GRSTCTL_RXFFLSH_MASK 0x10 -#define GC_USB_GRSTCTL_RXFFLSH_SIZE 0x1 -#define GC_USB_GRSTCTL_RXFFLSH_DEFAULT 0x0 -#define GC_USB_GRSTCTL_RXFFLSH_OFFSET 0x10 -#define GC_USB_GRSTCTL_TXFFLSH_LSB 0x5 -#define GC_USB_GRSTCTL_TXFFLSH_MASK 0x20 -#define GC_USB_GRSTCTL_TXFFLSH_SIZE 0x1 -#define GC_USB_GRSTCTL_TXFFLSH_DEFAULT 0x0 -#define GC_USB_GRSTCTL_TXFFLSH_OFFSET 0x10 -#define GC_USB_GRSTCTL_TXFNUM_LSB 0x6 -#define GC_USB_GRSTCTL_TXFNUM_MASK 0x7c0 -#define GC_USB_GRSTCTL_TXFNUM_SIZE 0x5 -#define GC_USB_GRSTCTL_TXFNUM_DEFAULT 0x0 -#define GC_USB_GRSTCTL_TXFNUM_OFFSET 0x10 -#define GC_USB_GRSTCTL_DMAREQ_LSB 0x1e -#define GC_USB_GRSTCTL_DMAREQ_MASK 0x40000000 -#define GC_USB_GRSTCTL_DMAREQ_SIZE 0x1 -#define GC_USB_GRSTCTL_DMAREQ_DEFAULT 0x0 -#define GC_USB_GRSTCTL_DMAREQ_OFFSET 0x10 -#define GC_USB_GRSTCTL_AHBIDLE_LSB 0x1f -#define GC_USB_GRSTCTL_AHBIDLE_MASK 0x80000000 -#define GC_USB_GRSTCTL_AHBIDLE_SIZE 0x1 -#define GC_USB_GRSTCTL_AHBIDLE_DEFAULT 0x0 -#define GC_USB_GRSTCTL_AHBIDLE_OFFSET 0x10 -#define GC_USB_GINTSTS_CURMOD_LSB 0x0 -#define GC_USB_GINTSTS_CURMOD_MASK 0x1 -#define GC_USB_GINTSTS_CURMOD_SIZE 0x1 -#define GC_USB_GINTSTS_CURMOD_DEFAULT 0x0 -#define GC_USB_GINTSTS_CURMOD_OFFSET 0x14 -#define GC_USB_GINTSTS_MODEMIS_LSB 0x1 -#define GC_USB_GINTSTS_MODEMIS_MASK 0x2 -#define GC_USB_GINTSTS_MODEMIS_SIZE 0x1 -#define GC_USB_GINTSTS_MODEMIS_DEFAULT 0x0 -#define GC_USB_GINTSTS_MODEMIS_OFFSET 0x14 -#define GC_USB_GINTSTS_OTGINT_LSB 0x2 -#define GC_USB_GINTSTS_OTGINT_MASK 0x4 -#define GC_USB_GINTSTS_OTGINT_SIZE 0x1 -#define GC_USB_GINTSTS_OTGINT_DEFAULT 0x0 -#define GC_USB_GINTSTS_OTGINT_OFFSET 0x14 -#define GC_USB_GINTSTS_SOF_LSB 0x3 -#define GC_USB_GINTSTS_SOF_MASK 0x8 -#define GC_USB_GINTSTS_SOF_SIZE 0x1 -#define GC_USB_GINTSTS_SOF_DEFAULT 0x0 -#define GC_USB_GINTSTS_SOF_OFFSET 0x14 -#define GC_USB_GINTSTS_RXFLVL_LSB 0x4 -#define GC_USB_GINTSTS_RXFLVL_MASK 0x10 -#define GC_USB_GINTSTS_RXFLVL_SIZE 0x1 -#define GC_USB_GINTSTS_RXFLVL_DEFAULT 0x0 -#define GC_USB_GINTSTS_RXFLVL_OFFSET 0x14 -#define GC_USB_GINTSTS_GINNAKEFF_LSB 0x6 -#define GC_USB_GINTSTS_GINNAKEFF_MASK 0x40 -#define GC_USB_GINTSTS_GINNAKEFF_SIZE 0x1 -#define GC_USB_GINTSTS_GINNAKEFF_DEFAULT 0x0 -#define GC_USB_GINTSTS_GINNAKEFF_OFFSET 0x14 -#define GC_USB_GINTSTS_GOUTNAKEFF_LSB 0x7 -#define GC_USB_GINTSTS_GOUTNAKEFF_MASK 0x80 -#define GC_USB_GINTSTS_GOUTNAKEFF_SIZE 0x1 -#define GC_USB_GINTSTS_GOUTNAKEFF_DEFAULT 0x0 -#define GC_USB_GINTSTS_GOUTNAKEFF_OFFSET 0x14 -#define GC_USB_GINTSTS_ERLYSUSP_LSB 0xa -#define GC_USB_GINTSTS_ERLYSUSP_MASK 0x400 -#define GC_USB_GINTSTS_ERLYSUSP_SIZE 0x1 -#define GC_USB_GINTSTS_ERLYSUSP_DEFAULT 0x0 -#define GC_USB_GINTSTS_ERLYSUSP_OFFSET 0x14 -#define GC_USB_GINTSTS_USBSUSP_LSB 0xb -#define GC_USB_GINTSTS_USBSUSP_MASK 0x800 -#define GC_USB_GINTSTS_USBSUSP_SIZE 0x1 -#define GC_USB_GINTSTS_USBSUSP_DEFAULT 0x0 -#define GC_USB_GINTSTS_USBSUSP_OFFSET 0x14 -#define GC_USB_GINTSTS_USBRST_LSB 0xc -#define GC_USB_GINTSTS_USBRST_MASK 0x1000 -#define GC_USB_GINTSTS_USBRST_SIZE 0x1 -#define GC_USB_GINTSTS_USBRST_DEFAULT 0x0 -#define GC_USB_GINTSTS_USBRST_OFFSET 0x14 -#define GC_USB_GINTSTS_ENUMDONE_LSB 0xd -#define GC_USB_GINTSTS_ENUMDONE_MASK 0x2000 -#define GC_USB_GINTSTS_ENUMDONE_SIZE 0x1 -#define GC_USB_GINTSTS_ENUMDONE_DEFAULT 0x0 -#define GC_USB_GINTSTS_ENUMDONE_OFFSET 0x14 -#define GC_USB_GINTSTS_ISOOUTDROP_LSB 0xe -#define GC_USB_GINTSTS_ISOOUTDROP_MASK 0x4000 -#define GC_USB_GINTSTS_ISOOUTDROP_SIZE 0x1 -#define GC_USB_GINTSTS_ISOOUTDROP_DEFAULT 0x0 -#define GC_USB_GINTSTS_ISOOUTDROP_OFFSET 0x14 -#define GC_USB_GINTSTS_EOPF_LSB 0xf -#define GC_USB_GINTSTS_EOPF_MASK 0x8000 -#define GC_USB_GINTSTS_EOPF_SIZE 0x1 -#define GC_USB_GINTSTS_EOPF_DEFAULT 0x0 -#define GC_USB_GINTSTS_EOPF_OFFSET 0x14 -#define GC_USB_GINTSTS_EPMIS_LSB 0x11 -#define GC_USB_GINTSTS_EPMIS_MASK 0x20000 -#define GC_USB_GINTSTS_EPMIS_SIZE 0x1 -#define GC_USB_GINTSTS_EPMIS_DEFAULT 0x0 -#define GC_USB_GINTSTS_EPMIS_OFFSET 0x14 -#define GC_USB_GINTSTS_IEPINT_LSB 0x12 -#define GC_USB_GINTSTS_IEPINT_MASK 0x40000 -#define GC_USB_GINTSTS_IEPINT_SIZE 0x1 -#define GC_USB_GINTSTS_IEPINT_DEFAULT 0x0 -#define GC_USB_GINTSTS_IEPINT_OFFSET 0x14 -#define GC_USB_GINTSTS_OEPINT_LSB 0x13 -#define GC_USB_GINTSTS_OEPINT_MASK 0x80000 -#define GC_USB_GINTSTS_OEPINT_SIZE 0x1 -#define GC_USB_GINTSTS_OEPINT_DEFAULT 0x0 -#define GC_USB_GINTSTS_OEPINT_OFFSET 0x14 -#define GC_USB_GINTSTS_INCOMPISOIN_LSB 0x14 -#define GC_USB_GINTSTS_INCOMPISOIN_MASK 0x100000 -#define GC_USB_GINTSTS_INCOMPISOIN_SIZE 0x1 -#define GC_USB_GINTSTS_INCOMPISOIN_DEFAULT 0x0 -#define GC_USB_GINTSTS_INCOMPISOIN_OFFSET 0x14 -#define GC_USB_GINTSTS_INCOMPLP_LSB 0x15 -#define GC_USB_GINTSTS_INCOMPLP_MASK 0x200000 -#define GC_USB_GINTSTS_INCOMPLP_SIZE 0x1 -#define GC_USB_GINTSTS_INCOMPLP_DEFAULT 0x0 -#define GC_USB_GINTSTS_INCOMPLP_OFFSET 0x14 -#define GC_USB_GINTSTS_FETSUSP_LSB 0x16 -#define GC_USB_GINTSTS_FETSUSP_MASK 0x400000 -#define GC_USB_GINTSTS_FETSUSP_SIZE 0x1 -#define GC_USB_GINTSTS_FETSUSP_DEFAULT 0x0 -#define GC_USB_GINTSTS_FETSUSP_OFFSET 0x14 -#define GC_USB_GINTSTS_RESETDET_LSB 0x17 -#define GC_USB_GINTSTS_RESETDET_MASK 0x800000 -#define GC_USB_GINTSTS_RESETDET_SIZE 0x1 -#define GC_USB_GINTSTS_RESETDET_DEFAULT 0x0 -#define GC_USB_GINTSTS_RESETDET_OFFSET 0x14 -#define GC_USB_GINTSTS_CONIDSTSCHNG_LSB 0x1c -#define GC_USB_GINTSTS_CONIDSTSCHNG_MASK 0x10000000 -#define GC_USB_GINTSTS_CONIDSTSCHNG_SIZE 0x1 -#define GC_USB_GINTSTS_CONIDSTSCHNG_DEFAULT 0x0 -#define GC_USB_GINTSTS_CONIDSTSCHNG_OFFSET 0x14 -#define GC_USB_GINTSTS_SESSREQINT_LSB 0x1e -#define GC_USB_GINTSTS_SESSREQINT_MASK 0x40000000 -#define GC_USB_GINTSTS_SESSREQINT_SIZE 0x1 -#define GC_USB_GINTSTS_SESSREQINT_DEFAULT 0x0 -#define GC_USB_GINTSTS_SESSREQINT_OFFSET 0x14 -#define GC_USB_GINTSTS_WKUPINT_LSB 0x1f -#define GC_USB_GINTSTS_WKUPINT_MASK 0x80000000 -#define GC_USB_GINTSTS_WKUPINT_SIZE 0x1 -#define GC_USB_GINTSTS_WKUPINT_DEFAULT 0x0 -#define GC_USB_GINTSTS_WKUPINT_OFFSET 0x14 -#define GC_USB_GINTMSK_MODEMISMSK_LSB 0x1 -#define GC_USB_GINTMSK_MODEMISMSK_MASK 0x2 -#define GC_USB_GINTMSK_MODEMISMSK_SIZE 0x1 -#define GC_USB_GINTMSK_MODEMISMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_MODEMISMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_OTGINTMSK_LSB 0x2 -#define GC_USB_GINTMSK_OTGINTMSK_MASK 0x4 -#define GC_USB_GINTMSK_OTGINTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_OTGINTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_OTGINTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_SOFMSK_LSB 0x3 -#define GC_USB_GINTMSK_SOFMSK_MASK 0x8 -#define GC_USB_GINTMSK_SOFMSK_SIZE 0x1 -#define GC_USB_GINTMSK_SOFMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_SOFMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_RXFLVLMSK_LSB 0x4 -#define GC_USB_GINTMSK_RXFLVLMSK_MASK 0x10 -#define GC_USB_GINTMSK_RXFLVLMSK_SIZE 0x1 -#define GC_USB_GINTMSK_RXFLVLMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_RXFLVLMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_UNKNOWN5_LSB 0x5 -#define GC_USB_GINTMSK_UNKNOWN5_MASK 0x20 -#define GC_USB_GINTMSK_UNKNOWN5_SIZE 0x1 -#define GC_USB_GINTMSK_UNKNOWN5_DEFAULT 0x0 -#define GC_USB_GINTMSK_UNKNOWN5_OFFSET 0x18 -#define GC_USB_GINTMSK_GINNAKEFFMSK_LSB 0x6 -#define GC_USB_GINTMSK_GINNAKEFFMSK_MASK 0x40 -#define GC_USB_GINTMSK_GINNAKEFFMSK_SIZE 0x1 -#define GC_USB_GINTMSK_GINNAKEFFMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_GINNAKEFFMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_GOUTNAKEFFMSK_LSB 0x7 -#define GC_USB_GINTMSK_GOUTNAKEFFMSK_MASK 0x80 -#define GC_USB_GINTMSK_GOUTNAKEFFMSK_SIZE 0x1 -#define GC_USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_GOUTNAKEFFMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_ERLYSUSPMSK_LSB 0xa -#define GC_USB_GINTMSK_ERLYSUSPMSK_MASK 0x400 -#define GC_USB_GINTMSK_ERLYSUSPMSK_SIZE 0x1 -#define GC_USB_GINTMSK_ERLYSUSPMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_ERLYSUSPMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_USBSUSPMSK_LSB 0xb -#define GC_USB_GINTMSK_USBSUSPMSK_MASK 0x800 -#define GC_USB_GINTMSK_USBSUSPMSK_SIZE 0x1 -#define GC_USB_GINTMSK_USBSUSPMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_USBSUSPMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_USBRSTMSK_LSB 0xc -#define GC_USB_GINTMSK_USBRSTMSK_MASK 0x1000 -#define GC_USB_GINTMSK_USBRSTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_USBRSTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_USBRSTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_ENUMDONEMSK_LSB 0xd -#define GC_USB_GINTMSK_ENUMDONEMSK_MASK 0x2000 -#define GC_USB_GINTMSK_ENUMDONEMSK_SIZE 0x1 -#define GC_USB_GINTMSK_ENUMDONEMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_ENUMDONEMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_ISOOUTDROPMSK_LSB 0xe -#define GC_USB_GINTMSK_ISOOUTDROPMSK_MASK 0x4000 -#define GC_USB_GINTMSK_ISOOUTDROPMSK_SIZE 0x1 -#define GC_USB_GINTMSK_ISOOUTDROPMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_ISOOUTDROPMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_EOPFMSK_LSB 0xf -#define GC_USB_GINTMSK_EOPFMSK_MASK 0x8000 -#define GC_USB_GINTMSK_EOPFMSK_SIZE 0x1 -#define GC_USB_GINTMSK_EOPFMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_EOPFMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_UNKNOWN16_LSB 0x10 -#define GC_USB_GINTMSK_UNKNOWN16_MASK 0x10000 -#define GC_USB_GINTMSK_UNKNOWN16_SIZE 0x1 -#define GC_USB_GINTMSK_UNKNOWN16_DEFAULT 0x0 -#define GC_USB_GINTMSK_UNKNOWN16_OFFSET 0x18 -#define GC_USB_GINTMSK_EPMISMSK_LSB 0x11 -#define GC_USB_GINTMSK_EPMISMSK_MASK 0x20000 -#define GC_USB_GINTMSK_EPMISMSK_SIZE 0x1 -#define GC_USB_GINTMSK_EPMISMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_EPMISMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_IEPINTMSK_LSB 0x12 -#define GC_USB_GINTMSK_IEPINTMSK_MASK 0x40000 -#define GC_USB_GINTMSK_IEPINTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_IEPINTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_IEPINTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_OEPINTMSK_LSB 0x13 -#define GC_USB_GINTMSK_OEPINTMSK_MASK 0x80000 -#define GC_USB_GINTMSK_OEPINTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_OEPINTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_OEPINTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_INCOMPISOINMSK_LSB 0x14 -#define GC_USB_GINTMSK_INCOMPISOINMSK_MASK 0x100000 -#define GC_USB_GINTMSK_INCOMPISOINMSK_SIZE 0x1 -#define GC_USB_GINTMSK_INCOMPISOINMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_INCOMPISOINMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_LSB 0x15 -#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_MASK 0x200000 -#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_FETSUSPMSK_LSB 0x16 -#define GC_USB_GINTMSK_FETSUSPMSK_MASK 0x400000 -#define GC_USB_GINTMSK_FETSUSPMSK_SIZE 0x1 -#define GC_USB_GINTMSK_FETSUSPMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_FETSUSPMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_RESETDETMSK_LSB 0x17 -#define GC_USB_GINTMSK_RESETDETMSK_MASK 0x800000 -#define GC_USB_GINTMSK_RESETDETMSK_SIZE 0x1 -#define GC_USB_GINTMSK_RESETDETMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_RESETDETMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_LSB 0x1c -#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_MASK 0x10000000 -#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_SIZE 0x1 -#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_DISCONNINTMSK_LSB 0x1d -#define GC_USB_GINTMSK_DISCONNINTMSK_MASK 0x20000000 -#define GC_USB_GINTMSK_DISCONNINTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_DISCONNINTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_DISCONNINTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_SESSREQINTMSK_LSB 0x1e -#define GC_USB_GINTMSK_SESSREQINTMSK_MASK 0x40000000 -#define GC_USB_GINTMSK_SESSREQINTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_SESSREQINTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_SESSREQINTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_WKUPINTMSK_LSB 0x1f -#define GC_USB_GINTMSK_WKUPINTMSK_MASK 0x80000000 -#define GC_USB_GINTMSK_WKUPINTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_WKUPINTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_WKUPINTMSK_OFFSET 0x18 -#define GC_USB_GRXSTSR_CHNUM_LSB 0x0 -#define GC_USB_GRXSTSR_CHNUM_MASK 0xf -#define GC_USB_GRXSTSR_CHNUM_SIZE 0x4 -#define GC_USB_GRXSTSR_CHNUM_DEFAULT 0x0 -#define GC_USB_GRXSTSR_CHNUM_OFFSET 0x1c -#define GC_USB_GRXSTSR_BCNT_LSB 0x4 -#define GC_USB_GRXSTSR_BCNT_MASK 0x7ff0 -#define GC_USB_GRXSTSR_BCNT_SIZE 0xb -#define GC_USB_GRXSTSR_BCNT_DEFAULT 0x0 -#define GC_USB_GRXSTSR_BCNT_OFFSET 0x1c -#define GC_USB_GRXSTSR_DPID_LSB 0xf -#define GC_USB_GRXSTSR_DPID_MASK 0x18000 -#define GC_USB_GRXSTSR_DPID_SIZE 0x2 -#define GC_USB_GRXSTSR_DPID_DEFAULT 0x0 -#define GC_USB_GRXSTSR_DPID_OFFSET 0x1c -#define GC_USB_GRXSTSR_PKTSTS_LSB 0x11 -#define GC_USB_GRXSTSR_PKTSTS_MASK 0x1e0000 -#define GC_USB_GRXSTSR_PKTSTS_SIZE 0x4 -#define GC_USB_GRXSTSR_PKTSTS_DEFAULT 0x0 -#define GC_USB_GRXSTSR_PKTSTS_OFFSET 0x1c -#define GC_USB_GRXSTSR_FN_LSB 0x15 -#define GC_USB_GRXSTSR_FN_MASK 0x1e00000 -#define GC_USB_GRXSTSR_FN_SIZE 0x4 -#define GC_USB_GRXSTSR_FN_DEFAULT 0x0 -#define GC_USB_GRXSTSR_FN_OFFSET 0x1c -#define GC_USB_GRXSTSP_CHNUM_LSB 0x0 -#define GC_USB_GRXSTSP_CHNUM_MASK 0xf -#define GC_USB_GRXSTSP_CHNUM_SIZE 0x4 -#define GC_USB_GRXSTSP_CHNUM_DEFAULT 0x0 -#define GC_USB_GRXSTSP_CHNUM_OFFSET 0x20 -#define GC_USB_GRXSTSP_BCNT_LSB 0x4 -#define GC_USB_GRXSTSP_BCNT_MASK 0x7ff0 -#define GC_USB_GRXSTSP_BCNT_SIZE 0xb -#define GC_USB_GRXSTSP_BCNT_DEFAULT 0x0 -#define GC_USB_GRXSTSP_BCNT_OFFSET 0x20 -#define GC_USB_GRXSTSP_DPID_LSB 0xf -#define GC_USB_GRXSTSP_DPID_MASK 0x18000 -#define GC_USB_GRXSTSP_DPID_SIZE 0x2 -#define GC_USB_GRXSTSP_DPID_DEFAULT 0x0 -#define GC_USB_GRXSTSP_DPID_OFFSET 0x20 -#define GC_USB_GRXSTSP_PKTSTS_LSB 0x11 -#define GC_USB_GRXSTSP_PKTSTS_MASK 0x1e0000 -#define GC_USB_GRXSTSP_PKTSTS_SIZE 0x4 -#define GC_USB_GRXSTSP_PKTSTS_DEFAULT 0x0 -#define GC_USB_GRXSTSP_PKTSTS_OFFSET 0x20 -#define GC_USB_GRXSTSP_FN_LSB 0x15 -#define GC_USB_GRXSTSP_FN_MASK 0x1e00000 -#define GC_USB_GRXSTSP_FN_SIZE 0x4 -#define GC_USB_GRXSTSP_FN_DEFAULT 0x0 -#define GC_USB_GRXSTSP_FN_OFFSET 0x20 -#define GC_USB_GRXFSIZ_RXFDEP_LSB 0x0 -#define GC_USB_GRXFSIZ_RXFDEP_MASK 0x7ff -#define GC_USB_GRXFSIZ_RXFDEP_SIZE 0xb -#define GC_USB_GRXFSIZ_RXFDEP_DEFAULT 0x0 -#define GC_USB_GRXFSIZ_RXFDEP_OFFSET 0x24 -#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_LSB 0x0 -#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_MASK 0xffff -#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_SIZE 0x10 -#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_DEFAULT 0x0 -#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_OFFSET 0x28 -#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_LSB 0x10 -#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_MASK 0xffff0000 -#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_SIZE 0x10 -#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_DEFAULT 0x0 -#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_OFFSET 0x28 +#define GC_USB_GRSTCTL_CSFTRST_LSB 0x0 +#define GC_USB_GRSTCTL_CSFTRST_MASK 0x1 +#define GC_USB_GRSTCTL_CSFTRST_SIZE 0x1 +#define GC_USB_GRSTCTL_CSFTRST_DEFAULT 0x0 +#define GC_USB_GRSTCTL_CSFTRST_OFFSET 0x10 +#define GC_USB_GRSTCTL_PIUFSSFTRST_LSB 0x1 +#define GC_USB_GRSTCTL_PIUFSSFTRST_MASK 0x2 +#define GC_USB_GRSTCTL_PIUFSSFTRST_SIZE 0x1 +#define GC_USB_GRSTCTL_PIUFSSFTRST_DEFAULT 0x0 +#define GC_USB_GRSTCTL_PIUFSSFTRST_OFFSET 0x10 +#define GC_USB_GRSTCTL_RXFFLSH_LSB 0x4 +#define GC_USB_GRSTCTL_RXFFLSH_MASK 0x10 +#define GC_USB_GRSTCTL_RXFFLSH_SIZE 0x1 +#define GC_USB_GRSTCTL_RXFFLSH_DEFAULT 0x0 +#define GC_USB_GRSTCTL_RXFFLSH_OFFSET 0x10 +#define GC_USB_GRSTCTL_TXFFLSH_LSB 0x5 +#define GC_USB_GRSTCTL_TXFFLSH_MASK 0x20 +#define GC_USB_GRSTCTL_TXFFLSH_SIZE 0x1 +#define GC_USB_GRSTCTL_TXFFLSH_DEFAULT 0x0 +#define GC_USB_GRSTCTL_TXFFLSH_OFFSET 0x10 +#define GC_USB_GRSTCTL_TXFNUM_LSB 0x6 +#define GC_USB_GRSTCTL_TXFNUM_MASK 0x7c0 +#define GC_USB_GRSTCTL_TXFNUM_SIZE 0x5 +#define GC_USB_GRSTCTL_TXFNUM_DEFAULT 0x0 +#define GC_USB_GRSTCTL_TXFNUM_OFFSET 0x10 +#define GC_USB_GRSTCTL_DMAREQ_LSB 0x1e +#define GC_USB_GRSTCTL_DMAREQ_MASK 0x40000000 +#define GC_USB_GRSTCTL_DMAREQ_SIZE 0x1 +#define GC_USB_GRSTCTL_DMAREQ_DEFAULT 0x0 +#define GC_USB_GRSTCTL_DMAREQ_OFFSET 0x10 +#define GC_USB_GRSTCTL_AHBIDLE_LSB 0x1f +#define GC_USB_GRSTCTL_AHBIDLE_MASK 0x80000000 +#define GC_USB_GRSTCTL_AHBIDLE_SIZE 0x1 +#define GC_USB_GRSTCTL_AHBIDLE_DEFAULT 0x0 +#define GC_USB_GRSTCTL_AHBIDLE_OFFSET 0x10 +#define GC_USB_GINTSTS_CURMOD_LSB 0x0 +#define GC_USB_GINTSTS_CURMOD_MASK 0x1 +#define GC_USB_GINTSTS_CURMOD_SIZE 0x1 +#define GC_USB_GINTSTS_CURMOD_DEFAULT 0x0 +#define GC_USB_GINTSTS_CURMOD_OFFSET 0x14 +#define GC_USB_GINTSTS_MODEMIS_LSB 0x1 +#define GC_USB_GINTSTS_MODEMIS_MASK 0x2 +#define GC_USB_GINTSTS_MODEMIS_SIZE 0x1 +#define GC_USB_GINTSTS_MODEMIS_DEFAULT 0x0 +#define GC_USB_GINTSTS_MODEMIS_OFFSET 0x14 +#define GC_USB_GINTSTS_OTGINT_LSB 0x2 +#define GC_USB_GINTSTS_OTGINT_MASK 0x4 +#define GC_USB_GINTSTS_OTGINT_SIZE 0x1 +#define GC_USB_GINTSTS_OTGINT_DEFAULT 0x0 +#define GC_USB_GINTSTS_OTGINT_OFFSET 0x14 +#define GC_USB_GINTSTS_SOF_LSB 0x3 +#define GC_USB_GINTSTS_SOF_MASK 0x8 +#define GC_USB_GINTSTS_SOF_SIZE 0x1 +#define GC_USB_GINTSTS_SOF_DEFAULT 0x0 +#define GC_USB_GINTSTS_SOF_OFFSET 0x14 +#define GC_USB_GINTSTS_RXFLVL_LSB 0x4 +#define GC_USB_GINTSTS_RXFLVL_MASK 0x10 +#define GC_USB_GINTSTS_RXFLVL_SIZE 0x1 +#define GC_USB_GINTSTS_RXFLVL_DEFAULT 0x0 +#define GC_USB_GINTSTS_RXFLVL_OFFSET 0x14 +#define GC_USB_GINTSTS_GINNAKEFF_LSB 0x6 +#define GC_USB_GINTSTS_GINNAKEFF_MASK 0x40 +#define GC_USB_GINTSTS_GINNAKEFF_SIZE 0x1 +#define GC_USB_GINTSTS_GINNAKEFF_DEFAULT 0x0 +#define GC_USB_GINTSTS_GINNAKEFF_OFFSET 0x14 +#define GC_USB_GINTSTS_GOUTNAKEFF_LSB 0x7 +#define GC_USB_GINTSTS_GOUTNAKEFF_MASK 0x80 +#define GC_USB_GINTSTS_GOUTNAKEFF_SIZE 0x1 +#define GC_USB_GINTSTS_GOUTNAKEFF_DEFAULT 0x0 +#define GC_USB_GINTSTS_GOUTNAKEFF_OFFSET 0x14 +#define GC_USB_GINTSTS_ERLYSUSP_LSB 0xa +#define GC_USB_GINTSTS_ERLYSUSP_MASK 0x400 +#define GC_USB_GINTSTS_ERLYSUSP_SIZE 0x1 +#define GC_USB_GINTSTS_ERLYSUSP_DEFAULT 0x0 +#define GC_USB_GINTSTS_ERLYSUSP_OFFSET 0x14 +#define GC_USB_GINTSTS_USBSUSP_LSB 0xb +#define GC_USB_GINTSTS_USBSUSP_MASK 0x800 +#define GC_USB_GINTSTS_USBSUSP_SIZE 0x1 +#define GC_USB_GINTSTS_USBSUSP_DEFAULT 0x0 +#define GC_USB_GINTSTS_USBSUSP_OFFSET 0x14 +#define GC_USB_GINTSTS_USBRST_LSB 0xc +#define GC_USB_GINTSTS_USBRST_MASK 0x1000 +#define GC_USB_GINTSTS_USBRST_SIZE 0x1 +#define GC_USB_GINTSTS_USBRST_DEFAULT 0x0 +#define GC_USB_GINTSTS_USBRST_OFFSET 0x14 +#define GC_USB_GINTSTS_ENUMDONE_LSB 0xd +#define GC_USB_GINTSTS_ENUMDONE_MASK 0x2000 +#define GC_USB_GINTSTS_ENUMDONE_SIZE 0x1 +#define GC_USB_GINTSTS_ENUMDONE_DEFAULT 0x0 +#define GC_USB_GINTSTS_ENUMDONE_OFFSET 0x14 +#define GC_USB_GINTSTS_ISOOUTDROP_LSB 0xe +#define GC_USB_GINTSTS_ISOOUTDROP_MASK 0x4000 +#define GC_USB_GINTSTS_ISOOUTDROP_SIZE 0x1 +#define GC_USB_GINTSTS_ISOOUTDROP_DEFAULT 0x0 +#define GC_USB_GINTSTS_ISOOUTDROP_OFFSET 0x14 +#define GC_USB_GINTSTS_EOPF_LSB 0xf +#define GC_USB_GINTSTS_EOPF_MASK 0x8000 +#define GC_USB_GINTSTS_EOPF_SIZE 0x1 +#define GC_USB_GINTSTS_EOPF_DEFAULT 0x0 +#define GC_USB_GINTSTS_EOPF_OFFSET 0x14 +#define GC_USB_GINTSTS_EPMIS_LSB 0x11 +#define GC_USB_GINTSTS_EPMIS_MASK 0x20000 +#define GC_USB_GINTSTS_EPMIS_SIZE 0x1 +#define GC_USB_GINTSTS_EPMIS_DEFAULT 0x0 +#define GC_USB_GINTSTS_EPMIS_OFFSET 0x14 +#define GC_USB_GINTSTS_IEPINT_LSB 0x12 +#define GC_USB_GINTSTS_IEPINT_MASK 0x40000 +#define GC_USB_GINTSTS_IEPINT_SIZE 0x1 +#define GC_USB_GINTSTS_IEPINT_DEFAULT 0x0 +#define GC_USB_GINTSTS_IEPINT_OFFSET 0x14 +#define GC_USB_GINTSTS_OEPINT_LSB 0x13 +#define GC_USB_GINTSTS_OEPINT_MASK 0x80000 +#define GC_USB_GINTSTS_OEPINT_SIZE 0x1 +#define GC_USB_GINTSTS_OEPINT_DEFAULT 0x0 +#define GC_USB_GINTSTS_OEPINT_OFFSET 0x14 +#define GC_USB_GINTSTS_INCOMPISOIN_LSB 0x14 +#define GC_USB_GINTSTS_INCOMPISOIN_MASK 0x100000 +#define GC_USB_GINTSTS_INCOMPISOIN_SIZE 0x1 +#define GC_USB_GINTSTS_INCOMPISOIN_DEFAULT 0x0 +#define GC_USB_GINTSTS_INCOMPISOIN_OFFSET 0x14 +#define GC_USB_GINTSTS_INCOMPLP_LSB 0x15 +#define GC_USB_GINTSTS_INCOMPLP_MASK 0x200000 +#define GC_USB_GINTSTS_INCOMPLP_SIZE 0x1 +#define GC_USB_GINTSTS_INCOMPLP_DEFAULT 0x0 +#define GC_USB_GINTSTS_INCOMPLP_OFFSET 0x14 +#define GC_USB_GINTSTS_FETSUSP_LSB 0x16 +#define GC_USB_GINTSTS_FETSUSP_MASK 0x400000 +#define GC_USB_GINTSTS_FETSUSP_SIZE 0x1 +#define GC_USB_GINTSTS_FETSUSP_DEFAULT 0x0 +#define GC_USB_GINTSTS_FETSUSP_OFFSET 0x14 +#define GC_USB_GINTSTS_RESETDET_LSB 0x17 +#define GC_USB_GINTSTS_RESETDET_MASK 0x800000 +#define GC_USB_GINTSTS_RESETDET_SIZE 0x1 +#define GC_USB_GINTSTS_RESETDET_DEFAULT 0x0 +#define GC_USB_GINTSTS_RESETDET_OFFSET 0x14 +#define GC_USB_GINTSTS_CONIDSTSCHNG_LSB 0x1c +#define GC_USB_GINTSTS_CONIDSTSCHNG_MASK 0x10000000 +#define GC_USB_GINTSTS_CONIDSTSCHNG_SIZE 0x1 +#define GC_USB_GINTSTS_CONIDSTSCHNG_DEFAULT 0x0 +#define GC_USB_GINTSTS_CONIDSTSCHNG_OFFSET 0x14 +#define GC_USB_GINTSTS_SESSREQINT_LSB 0x1e +#define GC_USB_GINTSTS_SESSREQINT_MASK 0x40000000 +#define GC_USB_GINTSTS_SESSREQINT_SIZE 0x1 +#define GC_USB_GINTSTS_SESSREQINT_DEFAULT 0x0 +#define GC_USB_GINTSTS_SESSREQINT_OFFSET 0x14 +#define GC_USB_GINTSTS_WKUPINT_LSB 0x1f +#define GC_USB_GINTSTS_WKUPINT_MASK 0x80000000 +#define GC_USB_GINTSTS_WKUPINT_SIZE 0x1 +#define GC_USB_GINTSTS_WKUPINT_DEFAULT 0x0 +#define GC_USB_GINTSTS_WKUPINT_OFFSET 0x14 +#define GC_USB_GINTMSK_MODEMISMSK_LSB 0x1 +#define GC_USB_GINTMSK_MODEMISMSK_MASK 0x2 +#define GC_USB_GINTMSK_MODEMISMSK_SIZE 0x1 +#define GC_USB_GINTMSK_MODEMISMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_MODEMISMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_OTGINTMSK_LSB 0x2 +#define GC_USB_GINTMSK_OTGINTMSK_MASK 0x4 +#define GC_USB_GINTMSK_OTGINTMSK_SIZE 0x1 +#define GC_USB_GINTMSK_OTGINTMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_OTGINTMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_SOFMSK_LSB 0x3 +#define GC_USB_GINTMSK_SOFMSK_MASK 0x8 +#define GC_USB_GINTMSK_SOFMSK_SIZE 0x1 +#define GC_USB_GINTMSK_SOFMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_SOFMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_RXFLVLMSK_LSB 0x4 +#define GC_USB_GINTMSK_RXFLVLMSK_MASK 0x10 +#define GC_USB_GINTMSK_RXFLVLMSK_SIZE 0x1 +#define GC_USB_GINTMSK_RXFLVLMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_RXFLVLMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_UNKNOWN5_LSB 0x5 +#define GC_USB_GINTMSK_UNKNOWN5_MASK 0x20 +#define GC_USB_GINTMSK_UNKNOWN5_SIZE 0x1 +#define GC_USB_GINTMSK_UNKNOWN5_DEFAULT 0x0 +#define GC_USB_GINTMSK_UNKNOWN5_OFFSET 0x18 +#define GC_USB_GINTMSK_GINNAKEFFMSK_LSB 0x6 +#define GC_USB_GINTMSK_GINNAKEFFMSK_MASK 0x40 +#define GC_USB_GINTMSK_GINNAKEFFMSK_SIZE 0x1 +#define GC_USB_GINTMSK_GINNAKEFFMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_GINNAKEFFMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_GOUTNAKEFFMSK_LSB 0x7 +#define GC_USB_GINTMSK_GOUTNAKEFFMSK_MASK 0x80 +#define GC_USB_GINTMSK_GOUTNAKEFFMSK_SIZE 0x1 +#define GC_USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_GOUTNAKEFFMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_ERLYSUSPMSK_LSB 0xa +#define GC_USB_GINTMSK_ERLYSUSPMSK_MASK 0x400 +#define GC_USB_GINTMSK_ERLYSUSPMSK_SIZE 0x1 +#define GC_USB_GINTMSK_ERLYSUSPMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_ERLYSUSPMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_USBSUSPMSK_LSB 0xb +#define GC_USB_GINTMSK_USBSUSPMSK_MASK 0x800 +#define GC_USB_GINTMSK_USBSUSPMSK_SIZE 0x1 +#define GC_USB_GINTMSK_USBSUSPMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_USBSUSPMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_USBRSTMSK_LSB 0xc +#define GC_USB_GINTMSK_USBRSTMSK_MASK 0x1000 +#define GC_USB_GINTMSK_USBRSTMSK_SIZE 0x1 +#define GC_USB_GINTMSK_USBRSTMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_USBRSTMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_ENUMDONEMSK_LSB 0xd +#define GC_USB_GINTMSK_ENUMDONEMSK_MASK 0x2000 +#define GC_USB_GINTMSK_ENUMDONEMSK_SIZE 0x1 +#define GC_USB_GINTMSK_ENUMDONEMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_ENUMDONEMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_ISOOUTDROPMSK_LSB 0xe +#define GC_USB_GINTMSK_ISOOUTDROPMSK_MASK 0x4000 +#define GC_USB_GINTMSK_ISOOUTDROPMSK_SIZE 0x1 +#define GC_USB_GINTMSK_ISOOUTDROPMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_ISOOUTDROPMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_EOPFMSK_LSB 0xf +#define GC_USB_GINTMSK_EOPFMSK_MASK 0x8000 +#define GC_USB_GINTMSK_EOPFMSK_SIZE 0x1 +#define GC_USB_GINTMSK_EOPFMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_EOPFMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_UNKNOWN16_LSB 0x10 +#define GC_USB_GINTMSK_UNKNOWN16_MASK 0x10000 +#define GC_USB_GINTMSK_UNKNOWN16_SIZE 0x1 +#define GC_USB_GINTMSK_UNKNOWN16_DEFAULT 0x0 +#define GC_USB_GINTMSK_UNKNOWN16_OFFSET 0x18 +#define GC_USB_GINTMSK_EPMISMSK_LSB 0x11 +#define GC_USB_GINTMSK_EPMISMSK_MASK 0x20000 +#define GC_USB_GINTMSK_EPMISMSK_SIZE 0x1 +#define GC_USB_GINTMSK_EPMISMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_EPMISMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_IEPINTMSK_LSB 0x12 +#define GC_USB_GINTMSK_IEPINTMSK_MASK 0x40000 +#define GC_USB_GINTMSK_IEPINTMSK_SIZE 0x1 +#define GC_USB_GINTMSK_IEPINTMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_IEPINTMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_OEPINTMSK_LSB 0x13 +#define GC_USB_GINTMSK_OEPINTMSK_MASK 0x80000 +#define GC_USB_GINTMSK_OEPINTMSK_SIZE 0x1 +#define GC_USB_GINTMSK_OEPINTMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_OEPINTMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_INCOMPISOINMSK_LSB 0x14 +#define GC_USB_GINTMSK_INCOMPISOINMSK_MASK 0x100000 +#define GC_USB_GINTMSK_INCOMPISOINMSK_SIZE 0x1 +#define GC_USB_GINTMSK_INCOMPISOINMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_INCOMPISOINMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_LSB 0x15 +#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_MASK 0x200000 +#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_SIZE 0x1 +#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_FETSUSPMSK_LSB 0x16 +#define GC_USB_GINTMSK_FETSUSPMSK_MASK 0x400000 +#define GC_USB_GINTMSK_FETSUSPMSK_SIZE 0x1 +#define GC_USB_GINTMSK_FETSUSPMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_FETSUSPMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_RESETDETMSK_LSB 0x17 +#define GC_USB_GINTMSK_RESETDETMSK_MASK 0x800000 +#define GC_USB_GINTMSK_RESETDETMSK_SIZE 0x1 +#define GC_USB_GINTMSK_RESETDETMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_RESETDETMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_LSB 0x1c +#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_MASK 0x10000000 +#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_SIZE 0x1 +#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_DISCONNINTMSK_LSB 0x1d +#define GC_USB_GINTMSK_DISCONNINTMSK_MASK 0x20000000 +#define GC_USB_GINTMSK_DISCONNINTMSK_SIZE 0x1 +#define GC_USB_GINTMSK_DISCONNINTMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_DISCONNINTMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_SESSREQINTMSK_LSB 0x1e +#define GC_USB_GINTMSK_SESSREQINTMSK_MASK 0x40000000 +#define GC_USB_GINTMSK_SESSREQINTMSK_SIZE 0x1 +#define GC_USB_GINTMSK_SESSREQINTMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_SESSREQINTMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_WKUPINTMSK_LSB 0x1f +#define GC_USB_GINTMSK_WKUPINTMSK_MASK 0x80000000 +#define GC_USB_GINTMSK_WKUPINTMSK_SIZE 0x1 +#define GC_USB_GINTMSK_WKUPINTMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_WKUPINTMSK_OFFSET 0x18 +#define GC_USB_GRXSTSR_CHNUM_LSB 0x0 +#define GC_USB_GRXSTSR_CHNUM_MASK 0xf +#define GC_USB_GRXSTSR_CHNUM_SIZE 0x4 +#define GC_USB_GRXSTSR_CHNUM_DEFAULT 0x0 +#define GC_USB_GRXSTSR_CHNUM_OFFSET 0x1c +#define GC_USB_GRXSTSR_BCNT_LSB 0x4 +#define GC_USB_GRXSTSR_BCNT_MASK 0x7ff0 +#define GC_USB_GRXSTSR_BCNT_SIZE 0xb +#define GC_USB_GRXSTSR_BCNT_DEFAULT 0x0 +#define GC_USB_GRXSTSR_BCNT_OFFSET 0x1c +#define GC_USB_GRXSTSR_DPID_LSB 0xf +#define GC_USB_GRXSTSR_DPID_MASK 0x18000 +#define GC_USB_GRXSTSR_DPID_SIZE 0x2 +#define GC_USB_GRXSTSR_DPID_DEFAULT 0x0 +#define GC_USB_GRXSTSR_DPID_OFFSET 0x1c +#define GC_USB_GRXSTSR_PKTSTS_LSB 0x11 +#define GC_USB_GRXSTSR_PKTSTS_MASK 0x1e0000 +#define GC_USB_GRXSTSR_PKTSTS_SIZE 0x4 +#define GC_USB_GRXSTSR_PKTSTS_DEFAULT 0x0 +#define GC_USB_GRXSTSR_PKTSTS_OFFSET 0x1c +#define GC_USB_GRXSTSR_FN_LSB 0x15 +#define GC_USB_GRXSTSR_FN_MASK 0x1e00000 +#define GC_USB_GRXSTSR_FN_SIZE 0x4 +#define GC_USB_GRXSTSR_FN_DEFAULT 0x0 +#define GC_USB_GRXSTSR_FN_OFFSET 0x1c +#define GC_USB_GRXSTSP_CHNUM_LSB 0x0 +#define GC_USB_GRXSTSP_CHNUM_MASK 0xf +#define GC_USB_GRXSTSP_CHNUM_SIZE 0x4 +#define GC_USB_GRXSTSP_CHNUM_DEFAULT 0x0 +#define GC_USB_GRXSTSP_CHNUM_OFFSET 0x20 +#define GC_USB_GRXSTSP_BCNT_LSB 0x4 +#define GC_USB_GRXSTSP_BCNT_MASK 0x7ff0 +#define GC_USB_GRXSTSP_BCNT_SIZE 0xb +#define GC_USB_GRXSTSP_BCNT_DEFAULT 0x0 +#define GC_USB_GRXSTSP_BCNT_OFFSET 0x20 +#define GC_USB_GRXSTSP_DPID_LSB 0xf +#define GC_USB_GRXSTSP_DPID_MASK 0x18000 +#define GC_USB_GRXSTSP_DPID_SIZE 0x2 +#define GC_USB_GRXSTSP_DPID_DEFAULT 0x0 +#define GC_USB_GRXSTSP_DPID_OFFSET 0x20 +#define GC_USB_GRXSTSP_PKTSTS_LSB 0x11 +#define GC_USB_GRXSTSP_PKTSTS_MASK 0x1e0000 +#define GC_USB_GRXSTSP_PKTSTS_SIZE 0x4 +#define GC_USB_GRXSTSP_PKTSTS_DEFAULT 0x0 +#define GC_USB_GRXSTSP_PKTSTS_OFFSET 0x20 +#define GC_USB_GRXSTSP_FN_LSB 0x15 +#define GC_USB_GRXSTSP_FN_MASK 0x1e00000 +#define GC_USB_GRXSTSP_FN_SIZE 0x4 +#define GC_USB_GRXSTSP_FN_DEFAULT 0x0 +#define GC_USB_GRXSTSP_FN_OFFSET 0x20 +#define GC_USB_GRXFSIZ_RXFDEP_LSB 0x0 +#define GC_USB_GRXFSIZ_RXFDEP_MASK 0x7ff +#define GC_USB_GRXFSIZ_RXFDEP_SIZE 0xb +#define GC_USB_GRXFSIZ_RXFDEP_DEFAULT 0x0 +#define GC_USB_GRXFSIZ_RXFDEP_OFFSET 0x24 +#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_LSB 0x0 +#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_MASK 0xffff +#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_SIZE 0x10 +#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_DEFAULT 0x0 +#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_OFFSET 0x28 +#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_LSB 0x10 +#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_MASK 0xffff0000 +#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_SIZE 0x10 +#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_DEFAULT 0x0 +#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_OFFSET 0x28 -#define GC_USB_GUID_GUID_LSB 0x0 -#define GC_USB_GUID_GUID_MASK 0xffffffff -#define GC_USB_GUID_GUID_SIZE 0x20 -#define GC_USB_GUID_GUID_DEFAULT 0x0 -#define GC_USB_GUID_GUID_OFFSET 0x3c -#define GC_USB_GSNPSID_SYNOPSYSID_LSB 0x0 -#define GC_USB_GSNPSID_SYNOPSYSID_MASK 0xffffffff -#define GC_USB_GSNPSID_SYNOPSYSID_SIZE 0x20 -#define GC_USB_GSNPSID_SYNOPSYSID_DEFAULT 0x0 -#define GC_USB_GSNPSID_SYNOPSYSID_OFFSET 0x40 -#define GC_USB_GHWCFG1_EPDIR_LSB 0x0 -#define GC_USB_GHWCFG1_EPDIR_MASK 0xffffffff -#define GC_USB_GHWCFG1_EPDIR_SIZE 0x20 -#define GC_USB_GHWCFG1_EPDIR_DEFAULT 0x0 -#define GC_USB_GHWCFG1_EPDIR_OFFSET 0x44 -#define GC_USB_GHWCFG2_OTGMODE_LSB 0x0 -#define GC_USB_GHWCFG2_OTGMODE_MASK 0x7 -#define GC_USB_GHWCFG2_OTGMODE_SIZE 0x3 -#define GC_USB_GHWCFG2_OTGMODE_DEFAULT 0x0 -#define GC_USB_GHWCFG2_OTGMODE_OFFSET 0x48 -#define GC_USB_GHWCFG2_OTGARCH_LSB 0x3 -#define GC_USB_GHWCFG2_OTGARCH_MASK 0x18 -#define GC_USB_GHWCFG2_OTGARCH_SIZE 0x2 -#define GC_USB_GHWCFG2_OTGARCH_DEFAULT 0x0 -#define GC_USB_GHWCFG2_OTGARCH_OFFSET 0x48 -#define GC_USB_GHWCFG2_SINGPNT_LSB 0x5 -#define GC_USB_GHWCFG2_SINGPNT_MASK 0x20 -#define GC_USB_GHWCFG2_SINGPNT_SIZE 0x1 -#define GC_USB_GHWCFG2_SINGPNT_DEFAULT 0x0 -#define GC_USB_GHWCFG2_SINGPNT_OFFSET 0x48 -#define GC_USB_GHWCFG2_HSPHYTYPE_LSB 0x6 -#define GC_USB_GHWCFG2_HSPHYTYPE_MASK 0xc0 -#define GC_USB_GHWCFG2_HSPHYTYPE_SIZE 0x2 -#define GC_USB_GHWCFG2_HSPHYTYPE_DEFAULT 0x0 -#define GC_USB_GHWCFG2_HSPHYTYPE_OFFSET 0x48 -#define GC_USB_GHWCFG2_FSPHYTYPE_LSB 0x8 -#define GC_USB_GHWCFG2_FSPHYTYPE_MASK 0x300 -#define GC_USB_GHWCFG2_FSPHYTYPE_SIZE 0x2 -#define GC_USB_GHWCFG2_FSPHYTYPE_DEFAULT 0x0 -#define GC_USB_GHWCFG2_FSPHYTYPE_OFFSET 0x48 -#define GC_USB_GHWCFG2_NUMDEVEPS_LSB 0xa -#define GC_USB_GHWCFG2_NUMDEVEPS_MASK 0x3c00 -#define GC_USB_GHWCFG2_NUMDEVEPS_SIZE 0x4 -#define GC_USB_GHWCFG2_NUMDEVEPS_DEFAULT 0x0 -#define GC_USB_GHWCFG2_NUMDEVEPS_OFFSET 0x48 -#define GC_USB_GHWCFG2_NUMHSTCHNL_LSB 0xe -#define GC_USB_GHWCFG2_NUMHSTCHNL_MASK 0x3c000 -#define GC_USB_GHWCFG2_NUMHSTCHNL_SIZE 0x4 -#define GC_USB_GHWCFG2_NUMHSTCHNL_DEFAULT 0x0 -#define GC_USB_GHWCFG2_NUMHSTCHNL_OFFSET 0x48 -#define GC_USB_GHWCFG2_PERIOSUPPORT_LSB 0x12 -#define GC_USB_GHWCFG2_PERIOSUPPORT_MASK 0x40000 -#define GC_USB_GHWCFG2_PERIOSUPPORT_SIZE 0x1 -#define GC_USB_GHWCFG2_PERIOSUPPORT_DEFAULT 0x0 -#define GC_USB_GHWCFG2_PERIOSUPPORT_OFFSET 0x48 -#define GC_USB_GHWCFG2_DYNFIFOSIZING_LSB 0x13 -#define GC_USB_GHWCFG2_DYNFIFOSIZING_MASK 0x80000 -#define GC_USB_GHWCFG2_DYNFIFOSIZING_SIZE 0x1 -#define GC_USB_GHWCFG2_DYNFIFOSIZING_DEFAULT 0x0 -#define GC_USB_GHWCFG2_DYNFIFOSIZING_OFFSET 0x48 -#define GC_USB_GHWCFG2_MULTIPROCINTRPT_LSB 0x14 -#define GC_USB_GHWCFG2_MULTIPROCINTRPT_MASK 0x100000 -#define GC_USB_GHWCFG2_MULTIPROCINTRPT_SIZE 0x1 -#define GC_USB_GHWCFG2_MULTIPROCINTRPT_DEFAULT 0x0 -#define GC_USB_GHWCFG2_MULTIPROCINTRPT_OFFSET 0x48 -#define GC_USB_GHWCFG2_NPTXQDEPTH_LSB 0x16 -#define GC_USB_GHWCFG2_NPTXQDEPTH_MASK 0xc00000 -#define GC_USB_GHWCFG2_NPTXQDEPTH_SIZE 0x2 -#define GC_USB_GHWCFG2_NPTXQDEPTH_DEFAULT 0x0 -#define GC_USB_GHWCFG2_NPTXQDEPTH_OFFSET 0x48 -#define GC_USB_GHWCFG2_PTXQDEPTH_LSB 0x18 -#define GC_USB_GHWCFG2_PTXQDEPTH_MASK 0x3000000 -#define GC_USB_GHWCFG2_PTXQDEPTH_SIZE 0x2 -#define GC_USB_GHWCFG2_PTXQDEPTH_DEFAULT 0x0 -#define GC_USB_GHWCFG2_PTXQDEPTH_OFFSET 0x48 -#define GC_USB_GHWCFG2_TKNQDEPTH_LSB 0x1a -#define GC_USB_GHWCFG2_TKNQDEPTH_MASK 0x7c000000 -#define GC_USB_GHWCFG2_TKNQDEPTH_SIZE 0x5 -#define GC_USB_GHWCFG2_TKNQDEPTH_DEFAULT 0x0 -#define GC_USB_GHWCFG2_TKNQDEPTH_OFFSET 0x48 -#define GC_USB_GHWCFG3_XFERSIZEWIDTH_LSB 0x0 -#define GC_USB_GHWCFG3_XFERSIZEWIDTH_MASK 0xf -#define GC_USB_GHWCFG3_XFERSIZEWIDTH_SIZE 0x4 -#define GC_USB_GHWCFG3_XFERSIZEWIDTH_DEFAULT 0x0 -#define GC_USB_GHWCFG3_XFERSIZEWIDTH_OFFSET 0x4c -#define GC_USB_GHWCFG3_PKTSIZEWIDTH_LSB 0x4 -#define GC_USB_GHWCFG3_PKTSIZEWIDTH_MASK 0x70 -#define GC_USB_GHWCFG3_PKTSIZEWIDTH_SIZE 0x3 -#define GC_USB_GHWCFG3_PKTSIZEWIDTH_DEFAULT 0x0 -#define GC_USB_GHWCFG3_PKTSIZEWIDTH_OFFSET 0x4c -#define GC_USB_GHWCFG3_OTGEN_LSB 0x7 -#define GC_USB_GHWCFG3_OTGEN_MASK 0x80 -#define GC_USB_GHWCFG3_OTGEN_SIZE 0x1 -#define GC_USB_GHWCFG3_OTGEN_DEFAULT 0x0 -#define GC_USB_GHWCFG3_OTGEN_OFFSET 0x4c -#define GC_USB_GHWCFG3_I2CINTSEL_LSB 0x8 -#define GC_USB_GHWCFG3_I2CINTSEL_MASK 0x100 -#define GC_USB_GHWCFG3_I2CINTSEL_SIZE 0x1 -#define GC_USB_GHWCFG3_I2CINTSEL_DEFAULT 0x0 -#define GC_USB_GHWCFG3_I2CINTSEL_OFFSET 0x4c -#define GC_USB_GHWCFG3_VNDCTLSUPT_LSB 0x9 -#define GC_USB_GHWCFG3_VNDCTLSUPT_MASK 0x200 -#define GC_USB_GHWCFG3_VNDCTLSUPT_SIZE 0x1 -#define GC_USB_GHWCFG3_VNDCTLSUPT_DEFAULT 0x0 -#define GC_USB_GHWCFG3_VNDCTLSUPT_OFFSET 0x4c -#define GC_USB_GHWCFG3_OPTFEATURE_LSB 0xa -#define GC_USB_GHWCFG3_OPTFEATURE_MASK 0x400 -#define GC_USB_GHWCFG3_OPTFEATURE_SIZE 0x1 -#define GC_USB_GHWCFG3_OPTFEATURE_DEFAULT 0x0 -#define GC_USB_GHWCFG3_OPTFEATURE_OFFSET 0x4c -#define GC_USB_GHWCFG3_RSTTYPE_LSB 0xb -#define GC_USB_GHWCFG3_RSTTYPE_MASK 0x800 -#define GC_USB_GHWCFG3_RSTTYPE_SIZE 0x1 -#define GC_USB_GHWCFG3_RSTTYPE_DEFAULT 0x0 -#define GC_USB_GHWCFG3_RSTTYPE_OFFSET 0x4c -#define GC_USB_GHWCFG3_ADPSUPPORT_LSB 0xc -#define GC_USB_GHWCFG3_ADPSUPPORT_MASK 0x1000 -#define GC_USB_GHWCFG3_ADPSUPPORT_SIZE 0x1 -#define GC_USB_GHWCFG3_ADPSUPPORT_DEFAULT 0x0 -#define GC_USB_GHWCFG3_ADPSUPPORT_OFFSET 0x4c -#define GC_USB_GHWCFG3_HSICMODE_LSB 0xd -#define GC_USB_GHWCFG3_HSICMODE_MASK 0x2000 -#define GC_USB_GHWCFG3_HSICMODE_SIZE 0x1 -#define GC_USB_GHWCFG3_HSICMODE_DEFAULT 0x0 -#define GC_USB_GHWCFG3_HSICMODE_OFFSET 0x4c -#define GC_USB_GHWCFG3_BCSUPPORT_LSB 0xe -#define GC_USB_GHWCFG3_BCSUPPORT_MASK 0x4000 -#define GC_USB_GHWCFG3_BCSUPPORT_SIZE 0x1 -#define GC_USB_GHWCFG3_BCSUPPORT_DEFAULT 0x0 -#define GC_USB_GHWCFG3_BCSUPPORT_OFFSET 0x4c -#define GC_USB_GHWCFG3_LPMMODE_LSB 0xf -#define GC_USB_GHWCFG3_LPMMODE_MASK 0x8000 -#define GC_USB_GHWCFG3_LPMMODE_SIZE 0x1 -#define GC_USB_GHWCFG3_LPMMODE_DEFAULT 0x0 -#define GC_USB_GHWCFG3_LPMMODE_OFFSET 0x4c -#define GC_USB_GHWCFG3_DFIFODEPTH_LSB 0x10 -#define GC_USB_GHWCFG3_DFIFODEPTH_MASK 0xffff0000 -#define GC_USB_GHWCFG3_DFIFODEPTH_SIZE 0x10 -#define GC_USB_GHWCFG3_DFIFODEPTH_DEFAULT 0x0 -#define GC_USB_GHWCFG3_DFIFODEPTH_OFFSET 0x4c -#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_LSB 0x0 -#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_MASK 0xf -#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_SIZE 0x4 -#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_DEFAULT 0x0 -#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_OFFSET 0x50 -#define GC_USB_GHWCFG4_PARTIALPWRDN_LSB 0x4 -#define GC_USB_GHWCFG4_PARTIALPWRDN_MASK 0x10 -#define GC_USB_GHWCFG4_PARTIALPWRDN_SIZE 0x1 -#define GC_USB_GHWCFG4_PARTIALPWRDN_DEFAULT 0x0 -#define GC_USB_GHWCFG4_PARTIALPWRDN_OFFSET 0x50 -#define GC_USB_GHWCFG4_AHBFREQ_LSB 0x5 -#define GC_USB_GHWCFG4_AHBFREQ_MASK 0x20 -#define GC_USB_GHWCFG4_AHBFREQ_SIZE 0x1 -#define GC_USB_GHWCFG4_AHBFREQ_DEFAULT 0x0 -#define GC_USB_GHWCFG4_AHBFREQ_OFFSET 0x50 -#define GC_USB_GHWCFG4_HIBERNATION_LSB 0x6 -#define GC_USB_GHWCFG4_HIBERNATION_MASK 0x40 -#define GC_USB_GHWCFG4_HIBERNATION_SIZE 0x1 -#define GC_USB_GHWCFG4_HIBERNATION_DEFAULT 0x0 -#define GC_USB_GHWCFG4_HIBERNATION_OFFSET 0x50 -#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_LSB 0x7 -#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_MASK 0x80 -#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_SIZE 0x1 +#define GC_USB_GUID_GUID_LSB 0x0 +#define GC_USB_GUID_GUID_MASK 0xffffffff +#define GC_USB_GUID_GUID_SIZE 0x20 +#define GC_USB_GUID_GUID_DEFAULT 0x0 +#define GC_USB_GUID_GUID_OFFSET 0x3c +#define GC_USB_GSNPSID_SYNOPSYSID_LSB 0x0 +#define GC_USB_GSNPSID_SYNOPSYSID_MASK 0xffffffff +#define GC_USB_GSNPSID_SYNOPSYSID_SIZE 0x20 +#define GC_USB_GSNPSID_SYNOPSYSID_DEFAULT 0x0 +#define GC_USB_GSNPSID_SYNOPSYSID_OFFSET 0x40 +#define GC_USB_GHWCFG1_EPDIR_LSB 0x0 +#define GC_USB_GHWCFG1_EPDIR_MASK 0xffffffff +#define GC_USB_GHWCFG1_EPDIR_SIZE 0x20 +#define GC_USB_GHWCFG1_EPDIR_DEFAULT 0x0 +#define GC_USB_GHWCFG1_EPDIR_OFFSET 0x44 +#define GC_USB_GHWCFG2_OTGMODE_LSB 0x0 +#define GC_USB_GHWCFG2_OTGMODE_MASK 0x7 +#define GC_USB_GHWCFG2_OTGMODE_SIZE 0x3 +#define GC_USB_GHWCFG2_OTGMODE_DEFAULT 0x0 +#define GC_USB_GHWCFG2_OTGMODE_OFFSET 0x48 +#define GC_USB_GHWCFG2_OTGARCH_LSB 0x3 +#define GC_USB_GHWCFG2_OTGARCH_MASK 0x18 +#define GC_USB_GHWCFG2_OTGARCH_SIZE 0x2 +#define GC_USB_GHWCFG2_OTGARCH_DEFAULT 0x0 +#define GC_USB_GHWCFG2_OTGARCH_OFFSET 0x48 +#define GC_USB_GHWCFG2_SINGPNT_LSB 0x5 +#define GC_USB_GHWCFG2_SINGPNT_MASK 0x20 +#define GC_USB_GHWCFG2_SINGPNT_SIZE 0x1 +#define GC_USB_GHWCFG2_SINGPNT_DEFAULT 0x0 +#define GC_USB_GHWCFG2_SINGPNT_OFFSET 0x48 +#define GC_USB_GHWCFG2_HSPHYTYPE_LSB 0x6 +#define GC_USB_GHWCFG2_HSPHYTYPE_MASK 0xc0 +#define GC_USB_GHWCFG2_HSPHYTYPE_SIZE 0x2 +#define GC_USB_GHWCFG2_HSPHYTYPE_DEFAULT 0x0 +#define GC_USB_GHWCFG2_HSPHYTYPE_OFFSET 0x48 +#define GC_USB_GHWCFG2_FSPHYTYPE_LSB 0x8 +#define GC_USB_GHWCFG2_FSPHYTYPE_MASK 0x300 +#define GC_USB_GHWCFG2_FSPHYTYPE_SIZE 0x2 +#define GC_USB_GHWCFG2_FSPHYTYPE_DEFAULT 0x0 +#define GC_USB_GHWCFG2_FSPHYTYPE_OFFSET 0x48 +#define GC_USB_GHWCFG2_NUMDEVEPS_LSB 0xa +#define GC_USB_GHWCFG2_NUMDEVEPS_MASK 0x3c00 +#define GC_USB_GHWCFG2_NUMDEVEPS_SIZE 0x4 +#define GC_USB_GHWCFG2_NUMDEVEPS_DEFAULT 0x0 +#define GC_USB_GHWCFG2_NUMDEVEPS_OFFSET 0x48 +#define GC_USB_GHWCFG2_NUMHSTCHNL_LSB 0xe +#define GC_USB_GHWCFG2_NUMHSTCHNL_MASK 0x3c000 +#define GC_USB_GHWCFG2_NUMHSTCHNL_SIZE 0x4 +#define GC_USB_GHWCFG2_NUMHSTCHNL_DEFAULT 0x0 +#define GC_USB_GHWCFG2_NUMHSTCHNL_OFFSET 0x48 +#define GC_USB_GHWCFG2_PERIOSUPPORT_LSB 0x12 +#define GC_USB_GHWCFG2_PERIOSUPPORT_MASK 0x40000 +#define GC_USB_GHWCFG2_PERIOSUPPORT_SIZE 0x1 +#define GC_USB_GHWCFG2_PERIOSUPPORT_DEFAULT 0x0 +#define GC_USB_GHWCFG2_PERIOSUPPORT_OFFSET 0x48 +#define GC_USB_GHWCFG2_DYNFIFOSIZING_LSB 0x13 +#define GC_USB_GHWCFG2_DYNFIFOSIZING_MASK 0x80000 +#define GC_USB_GHWCFG2_DYNFIFOSIZING_SIZE 0x1 +#define GC_USB_GHWCFG2_DYNFIFOSIZING_DEFAULT 0x0 +#define GC_USB_GHWCFG2_DYNFIFOSIZING_OFFSET 0x48 +#define GC_USB_GHWCFG2_MULTIPROCINTRPT_LSB 0x14 +#define GC_USB_GHWCFG2_MULTIPROCINTRPT_MASK 0x100000 +#define GC_USB_GHWCFG2_MULTIPROCINTRPT_SIZE 0x1 +#define GC_USB_GHWCFG2_MULTIPROCINTRPT_DEFAULT 0x0 +#define GC_USB_GHWCFG2_MULTIPROCINTRPT_OFFSET 0x48 +#define GC_USB_GHWCFG2_NPTXQDEPTH_LSB 0x16 +#define GC_USB_GHWCFG2_NPTXQDEPTH_MASK 0xc00000 +#define GC_USB_GHWCFG2_NPTXQDEPTH_SIZE 0x2 +#define GC_USB_GHWCFG2_NPTXQDEPTH_DEFAULT 0x0 +#define GC_USB_GHWCFG2_NPTXQDEPTH_OFFSET 0x48 +#define GC_USB_GHWCFG2_PTXQDEPTH_LSB 0x18 +#define GC_USB_GHWCFG2_PTXQDEPTH_MASK 0x3000000 +#define GC_USB_GHWCFG2_PTXQDEPTH_SIZE 0x2 +#define GC_USB_GHWCFG2_PTXQDEPTH_DEFAULT 0x0 +#define GC_USB_GHWCFG2_PTXQDEPTH_OFFSET 0x48 +#define GC_USB_GHWCFG2_TKNQDEPTH_LSB 0x1a +#define GC_USB_GHWCFG2_TKNQDEPTH_MASK 0x7c000000 +#define GC_USB_GHWCFG2_TKNQDEPTH_SIZE 0x5 +#define GC_USB_GHWCFG2_TKNQDEPTH_DEFAULT 0x0 +#define GC_USB_GHWCFG2_TKNQDEPTH_OFFSET 0x48 +#define GC_USB_GHWCFG3_XFERSIZEWIDTH_LSB 0x0 +#define GC_USB_GHWCFG3_XFERSIZEWIDTH_MASK 0xf +#define GC_USB_GHWCFG3_XFERSIZEWIDTH_SIZE 0x4 +#define GC_USB_GHWCFG3_XFERSIZEWIDTH_DEFAULT 0x0 +#define GC_USB_GHWCFG3_XFERSIZEWIDTH_OFFSET 0x4c +#define GC_USB_GHWCFG3_PKTSIZEWIDTH_LSB 0x4 +#define GC_USB_GHWCFG3_PKTSIZEWIDTH_MASK 0x70 +#define GC_USB_GHWCFG3_PKTSIZEWIDTH_SIZE 0x3 +#define GC_USB_GHWCFG3_PKTSIZEWIDTH_DEFAULT 0x0 +#define GC_USB_GHWCFG3_PKTSIZEWIDTH_OFFSET 0x4c +#define GC_USB_GHWCFG3_OTGEN_LSB 0x7 +#define GC_USB_GHWCFG3_OTGEN_MASK 0x80 +#define GC_USB_GHWCFG3_OTGEN_SIZE 0x1 +#define GC_USB_GHWCFG3_OTGEN_DEFAULT 0x0 +#define GC_USB_GHWCFG3_OTGEN_OFFSET 0x4c +#define GC_USB_GHWCFG3_I2CINTSEL_LSB 0x8 +#define GC_USB_GHWCFG3_I2CINTSEL_MASK 0x100 +#define GC_USB_GHWCFG3_I2CINTSEL_SIZE 0x1 +#define GC_USB_GHWCFG3_I2CINTSEL_DEFAULT 0x0 +#define GC_USB_GHWCFG3_I2CINTSEL_OFFSET 0x4c +#define GC_USB_GHWCFG3_VNDCTLSUPT_LSB 0x9 +#define GC_USB_GHWCFG3_VNDCTLSUPT_MASK 0x200 +#define GC_USB_GHWCFG3_VNDCTLSUPT_SIZE 0x1 +#define GC_USB_GHWCFG3_VNDCTLSUPT_DEFAULT 0x0 +#define GC_USB_GHWCFG3_VNDCTLSUPT_OFFSET 0x4c +#define GC_USB_GHWCFG3_OPTFEATURE_LSB 0xa +#define GC_USB_GHWCFG3_OPTFEATURE_MASK 0x400 +#define GC_USB_GHWCFG3_OPTFEATURE_SIZE 0x1 +#define GC_USB_GHWCFG3_OPTFEATURE_DEFAULT 0x0 +#define GC_USB_GHWCFG3_OPTFEATURE_OFFSET 0x4c +#define GC_USB_GHWCFG3_RSTTYPE_LSB 0xb +#define GC_USB_GHWCFG3_RSTTYPE_MASK 0x800 +#define GC_USB_GHWCFG3_RSTTYPE_SIZE 0x1 +#define GC_USB_GHWCFG3_RSTTYPE_DEFAULT 0x0 +#define GC_USB_GHWCFG3_RSTTYPE_OFFSET 0x4c +#define GC_USB_GHWCFG3_ADPSUPPORT_LSB 0xc +#define GC_USB_GHWCFG3_ADPSUPPORT_MASK 0x1000 +#define GC_USB_GHWCFG3_ADPSUPPORT_SIZE 0x1 +#define GC_USB_GHWCFG3_ADPSUPPORT_DEFAULT 0x0 +#define GC_USB_GHWCFG3_ADPSUPPORT_OFFSET 0x4c +#define GC_USB_GHWCFG3_HSICMODE_LSB 0xd +#define GC_USB_GHWCFG3_HSICMODE_MASK 0x2000 +#define GC_USB_GHWCFG3_HSICMODE_SIZE 0x1 +#define GC_USB_GHWCFG3_HSICMODE_DEFAULT 0x0 +#define GC_USB_GHWCFG3_HSICMODE_OFFSET 0x4c +#define GC_USB_GHWCFG3_BCSUPPORT_LSB 0xe +#define GC_USB_GHWCFG3_BCSUPPORT_MASK 0x4000 +#define GC_USB_GHWCFG3_BCSUPPORT_SIZE 0x1 +#define GC_USB_GHWCFG3_BCSUPPORT_DEFAULT 0x0 +#define GC_USB_GHWCFG3_BCSUPPORT_OFFSET 0x4c +#define GC_USB_GHWCFG3_LPMMODE_LSB 0xf +#define GC_USB_GHWCFG3_LPMMODE_MASK 0x8000 +#define GC_USB_GHWCFG3_LPMMODE_SIZE 0x1 +#define GC_USB_GHWCFG3_LPMMODE_DEFAULT 0x0 +#define GC_USB_GHWCFG3_LPMMODE_OFFSET 0x4c +#define GC_USB_GHWCFG3_DFIFODEPTH_LSB 0x10 +#define GC_USB_GHWCFG3_DFIFODEPTH_MASK 0xffff0000 +#define GC_USB_GHWCFG3_DFIFODEPTH_SIZE 0x10 +#define GC_USB_GHWCFG3_DFIFODEPTH_DEFAULT 0x0 +#define GC_USB_GHWCFG3_DFIFODEPTH_OFFSET 0x4c +#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_LSB 0x0 +#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_MASK 0xf +#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_SIZE 0x4 +#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_DEFAULT 0x0 +#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_OFFSET 0x50 +#define GC_USB_GHWCFG4_PARTIALPWRDN_LSB 0x4 +#define GC_USB_GHWCFG4_PARTIALPWRDN_MASK 0x10 +#define GC_USB_GHWCFG4_PARTIALPWRDN_SIZE 0x1 +#define GC_USB_GHWCFG4_PARTIALPWRDN_DEFAULT 0x0 +#define GC_USB_GHWCFG4_PARTIALPWRDN_OFFSET 0x50 +#define GC_USB_GHWCFG4_AHBFREQ_LSB 0x5 +#define GC_USB_GHWCFG4_AHBFREQ_MASK 0x20 +#define GC_USB_GHWCFG4_AHBFREQ_SIZE 0x1 +#define GC_USB_GHWCFG4_AHBFREQ_DEFAULT 0x0 +#define GC_USB_GHWCFG4_AHBFREQ_OFFSET 0x50 +#define GC_USB_GHWCFG4_HIBERNATION_LSB 0x6 +#define GC_USB_GHWCFG4_HIBERNATION_MASK 0x40 +#define GC_USB_GHWCFG4_HIBERNATION_SIZE 0x1 +#define GC_USB_GHWCFG4_HIBERNATION_DEFAULT 0x0 +#define GC_USB_GHWCFG4_HIBERNATION_OFFSET 0x50 +#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_LSB 0x7 +#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_MASK 0x80 +#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_SIZE 0x1 #define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_DEFAULT 0x0 #define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_OFFSET 0x50 -#define GC_USB_GHWCFG4_PHYDATAWIDTH_LSB 0xe -#define GC_USB_GHWCFG4_PHYDATAWIDTH_MASK 0xc000 -#define GC_USB_GHWCFG4_PHYDATAWIDTH_SIZE 0x2 -#define GC_USB_GHWCFG4_PHYDATAWIDTH_DEFAULT 0x0 -#define GC_USB_GHWCFG4_PHYDATAWIDTH_OFFSET 0x50 -#define GC_USB_GHWCFG4_NUMCTLEPS_LSB 0x10 -#define GC_USB_GHWCFG4_NUMCTLEPS_MASK 0xf0000 -#define GC_USB_GHWCFG4_NUMCTLEPS_SIZE 0x4 -#define GC_USB_GHWCFG4_NUMCTLEPS_DEFAULT 0x0 -#define GC_USB_GHWCFG4_NUMCTLEPS_OFFSET 0x50 -#define GC_USB_GHWCFG4_IDDGFLTR_LSB 0x14 -#define GC_USB_GHWCFG4_IDDGFLTR_MASK 0x100000 -#define GC_USB_GHWCFG4_IDDGFLTR_SIZE 0x1 -#define GC_USB_GHWCFG4_IDDGFLTR_DEFAULT 0x0 -#define GC_USB_GHWCFG4_IDDGFLTR_OFFSET 0x50 -#define GC_USB_GHWCFG4_VBUSVALIDFLTR_LSB 0x15 -#define GC_USB_GHWCFG4_VBUSVALIDFLTR_MASK 0x200000 -#define GC_USB_GHWCFG4_VBUSVALIDFLTR_SIZE 0x1 -#define GC_USB_GHWCFG4_VBUSVALIDFLTR_DEFAULT 0x0 -#define GC_USB_GHWCFG4_VBUSVALIDFLTR_OFFSET 0x50 -#define GC_USB_GHWCFG4_AVALIDFLTR_LSB 0x16 -#define GC_USB_GHWCFG4_AVALIDFLTR_MASK 0x400000 -#define GC_USB_GHWCFG4_AVALIDFLTR_SIZE 0x1 -#define GC_USB_GHWCFG4_AVALIDFLTR_DEFAULT 0x0 -#define GC_USB_GHWCFG4_AVALIDFLTR_OFFSET 0x50 -#define GC_USB_GHWCFG4_BVALIDFLTR_LSB 0x17 -#define GC_USB_GHWCFG4_BVALIDFLTR_MASK 0x800000 -#define GC_USB_GHWCFG4_BVALIDFLTR_SIZE 0x1 -#define GC_USB_GHWCFG4_BVALIDFLTR_DEFAULT 0x0 -#define GC_USB_GHWCFG4_BVALIDFLTR_OFFSET 0x50 -#define GC_USB_GHWCFG4_SESSENDFLTR_LSB 0x18 -#define GC_USB_GHWCFG4_SESSENDFLTR_MASK 0x1000000 -#define GC_USB_GHWCFG4_SESSENDFLTR_SIZE 0x1 -#define GC_USB_GHWCFG4_SESSENDFLTR_DEFAULT 0x0 -#define GC_USB_GHWCFG4_SESSENDFLTR_OFFSET 0x50 -#define GC_USB_GHWCFG4_DEDFIFOMODE_LSB 0x19 -#define GC_USB_GHWCFG4_DEDFIFOMODE_MASK 0x2000000 -#define GC_USB_GHWCFG4_DEDFIFOMODE_SIZE 0x1 -#define GC_USB_GHWCFG4_DEDFIFOMODE_DEFAULT 0x0 -#define GC_USB_GHWCFG4_DEDFIFOMODE_OFFSET 0x50 -#define GC_USB_GHWCFG4_INEPS_LSB 0x1a -#define GC_USB_GHWCFG4_INEPS_MASK 0x3c000000 -#define GC_USB_GHWCFG4_INEPS_SIZE 0x4 -#define GC_USB_GHWCFG4_INEPS_DEFAULT 0x0 -#define GC_USB_GHWCFG4_INEPS_OFFSET 0x50 -#define GC_USB_GHWCFG4_DESCDMAENABLED_LSB 0x1e -#define GC_USB_GHWCFG4_DESCDMAENABLED_MASK 0x40000000 -#define GC_USB_GHWCFG4_DESCDMAENABLED_SIZE 0x1 -#define GC_USB_GHWCFG4_DESCDMAENABLED_DEFAULT 0x0 -#define GC_USB_GHWCFG4_DESCDMAENABLED_OFFSET 0x50 -#define GC_USB_GHWCFG4_DESCDMA_LSB 0x1f -#define GC_USB_GHWCFG4_DESCDMA_MASK 0x80000000 -#define GC_USB_GHWCFG4_DESCDMA_SIZE 0x1 -#define GC_USB_GHWCFG4_DESCDMA_DEFAULT 0x0 -#define GC_USB_GHWCFG4_DESCDMA_OFFSET 0x50 -#define GC_USB_GDFIFOCFG_GDFIFOCFG_LSB 0x0 -#define GC_USB_GDFIFOCFG_GDFIFOCFG_MASK 0xffff -#define GC_USB_GDFIFOCFG_GDFIFOCFG_SIZE 0x10 -#define GC_USB_GDFIFOCFG_GDFIFOCFG_DEFAULT 0x0 -#define GC_USB_GDFIFOCFG_GDFIFOCFG_OFFSET 0x5c -#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_LSB 0x10 -#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_MASK 0xffff0000 -#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_SIZE 0x10 -#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT 0x0 -#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_OFFSET 0x5c -#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_OFFSET 0x104 -#define GC_USB_DIEPTXF1_RESERVED11_LSB 0xc -#define GC_USB_DIEPTXF1_RESERVED11_MASK 0x1000 -#define GC_USB_DIEPTXF1_RESERVED11_SIZE 0x1 -#define GC_USB_DIEPTXF1_RESERVED11_DEFAULT 0x1 -#define GC_USB_DIEPTXF1_RESERVED11_OFFSET 0x104 -#define GC_USB_DIEPTXF1_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF1_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF1_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF1_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF1_INEPNTXFDEP_OFFSET 0x104 -#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_OFFSET 0x108 -#define GC_USB_DIEPTXF2_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF2_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF2_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF2_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF2_INEPNTXFDEP_OFFSET 0x108 -#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_OFFSET 0x10c -#define GC_USB_DIEPTXF3_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF3_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF3_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF3_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF3_INEPNTXFDEP_OFFSET 0x10c -#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_OFFSET 0x110 -#define GC_USB_DIEPTXF4_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF4_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF4_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF4_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF4_INEPNTXFDEP_OFFSET 0x110 -#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_OFFSET 0x114 -#define GC_USB_DIEPTXF5_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF5_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF5_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF5_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF5_INEPNTXFDEP_OFFSET 0x114 -#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_OFFSET 0x118 -#define GC_USB_DIEPTXF6_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF6_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF6_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF6_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF6_INEPNTXFDEP_OFFSET 0x118 -#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_OFFSET 0x11c -#define GC_USB_DIEPTXF7_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF7_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF7_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF7_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF7_INEPNTXFDEP_OFFSET 0x11c -#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_OFFSET 0x120 -#define GC_USB_DIEPTXF8_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF8_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF8_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF8_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF8_INEPNTXFDEP_OFFSET 0x120 -#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_OFFSET 0x124 -#define GC_USB_DIEPTXF9_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF9_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF9_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF9_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF9_INEPNTXFDEP_OFFSET 0x124 -#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_OFFSET 0x128 -#define GC_USB_DIEPTXF10_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF10_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF10_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF10_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF10_INEPNTXFDEP_OFFSET 0x128 -#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_OFFSET 0x12c -#define GC_USB_DIEPTXF11_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF11_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF11_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF11_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF11_INEPNTXFDEP_OFFSET 0x12c -#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_OFFSET 0x130 -#define GC_USB_DIEPTXF12_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF12_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF12_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF12_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF12_INEPNTXFDEP_OFFSET 0x130 -#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_OFFSET 0x134 -#define GC_USB_DIEPTXF13_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF13_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF13_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF13_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF13_INEPNTXFDEP_OFFSET 0x134 -#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_OFFSET 0x138 -#define GC_USB_DIEPTXF14_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF14_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF14_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF14_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF14_INEPNTXFDEP_OFFSET 0x138 -#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_OFFSET 0x13c -#define GC_USB_DIEPTXF15_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF15_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF15_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF15_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF15_INEPNTXFDEP_OFFSET 0x13c -#define GC_USB_DCFG_DEVSPD_LSB 0x0 -#define GC_USB_DCFG_DEVSPD_MASK 0x3 -#define GC_USB_DCFG_DEVSPD_SIZE 0x2 -#define GC_USB_DCFG_DEVSPD_DEFAULT 0x0 -#define GC_USB_DCFG_DEVSPD_OFFSET 0x800 -#define GC_USB_DCFG_NZSTSOUTHSHK_LSB 0x2 -#define GC_USB_DCFG_NZSTSOUTHSHK_MASK 0x4 -#define GC_USB_DCFG_NZSTSOUTHSHK_SIZE 0x1 -#define GC_USB_DCFG_NZSTSOUTHSHK_DEFAULT 0x0 -#define GC_USB_DCFG_NZSTSOUTHSHK_OFFSET 0x800 -#define GC_USB_DCFG_ENA32KHZSUSP_LSB 0x3 -#define GC_USB_DCFG_ENA32KHZSUSP_MASK 0x8 -#define GC_USB_DCFG_ENA32KHZSUSP_SIZE 0x1 -#define GC_USB_DCFG_ENA32KHZSUSP_DEFAULT 0x0 -#define GC_USB_DCFG_ENA32KHZSUSP_OFFSET 0x800 -#define GC_USB_DCFG_DEVADDR_LSB 0x4 -#define GC_USB_DCFG_DEVADDR_MASK 0x7f0 -#define GC_USB_DCFG_DEVADDR_SIZE 0x7 -#define GC_USB_DCFG_DEVADDR_DEFAULT 0x0 -#define GC_USB_DCFG_DEVADDR_OFFSET 0x800 -#define GC_USB_DCFG_PERFRINT_LSB 0xb -#define GC_USB_DCFG_PERFRINT_MASK 0x1800 -#define GC_USB_DCFG_PERFRINT_SIZE 0x2 -#define GC_USB_DCFG_PERFRINT_DEFAULT 0x0 -#define GC_USB_DCFG_PERFRINT_OFFSET 0x800 -#define GC_USB_DCFG_ENDEVOUTNAK_LSB 0xd -#define GC_USB_DCFG_ENDEVOUTNAK_MASK 0x2000 -#define GC_USB_DCFG_ENDEVOUTNAK_SIZE 0x1 -#define GC_USB_DCFG_ENDEVOUTNAK_DEFAULT 0x0 -#define GC_USB_DCFG_ENDEVOUTNAK_OFFSET 0x800 -#define GC_USB_DCFG_XCVRDLY_LSB 0xe -#define GC_USB_DCFG_XCVRDLY_MASK 0x4000 -#define GC_USB_DCFG_XCVRDLY_SIZE 0x1 -#define GC_USB_DCFG_XCVRDLY_DEFAULT 0x0 -#define GC_USB_DCFG_XCVRDLY_OFFSET 0x800 -#define GC_USB_DCFG_ERRATICINTMSK_LSB 0xf -#define GC_USB_DCFG_ERRATICINTMSK_MASK 0x8000 -#define GC_USB_DCFG_ERRATICINTMSK_SIZE 0x1 -#define GC_USB_DCFG_ERRATICINTMSK_DEFAULT 0x0 -#define GC_USB_DCFG_ERRATICINTMSK_OFFSET 0x800 -#define GC_USB_DCFG_DESCDMA_LSB 0x17 -#define GC_USB_DCFG_DESCDMA_MASK 0x800000 -#define GC_USB_DCFG_DESCDMA_SIZE 0x1 -#define GC_USB_DCFG_DESCDMA_DEFAULT 0x0 -#define GC_USB_DCFG_DESCDMA_OFFSET 0x800 -#define GC_USB_DCFG_PERSCHINTVL_LSB 0x18 -#define GC_USB_DCFG_PERSCHINTVL_MASK 0x3000000 -#define GC_USB_DCFG_PERSCHINTVL_SIZE 0x2 -#define GC_USB_DCFG_PERSCHINTVL_DEFAULT 0x0 -#define GC_USB_DCFG_PERSCHINTVL_OFFSET 0x800 -#define GC_USB_DCFG_RESVALID_LSB 0x1a -#define GC_USB_DCFG_RESVALID_MASK 0xfc000000 -#define GC_USB_DCFG_RESVALID_SIZE 0x6 -#define GC_USB_DCFG_RESVALID_DEFAULT 0x2 -#define GC_USB_DCFG_RESVALID_OFFSET 0x800 -#define GC_USB_DCTL_RMTWKUPSIG_LSB 0x0 -#define GC_USB_DCTL_RMTWKUPSIG_MASK 0x1 -#define GC_USB_DCTL_RMTWKUPSIG_SIZE 0x1 -#define GC_USB_DCTL_RMTWKUPSIG_DEFAULT 0x0 -#define GC_USB_DCTL_RMTWKUPSIG_OFFSET 0x804 -#define GC_USB_DCTL_SFTDISCON_LSB 0x1 -#define GC_USB_DCTL_SFTDISCON_MASK 0x2 -#define GC_USB_DCTL_SFTDISCON_SIZE 0x1 -#define GC_USB_DCTL_SFTDISCON_DEFAULT 0x0 -#define GC_USB_DCTL_SFTDISCON_OFFSET 0x804 -#define GC_USB_DCTL_GNPINNAKSTS_LSB 0x2 -#define GC_USB_DCTL_GNPINNAKSTS_MASK 0x4 -#define GC_USB_DCTL_GNPINNAKSTS_SIZE 0x1 -#define GC_USB_DCTL_GNPINNAKSTS_DEFAULT 0x0 -#define GC_USB_DCTL_GNPINNAKSTS_OFFSET 0x804 -#define GC_USB_DCTL_GOUTNAKSTS_LSB 0x3 -#define GC_USB_DCTL_GOUTNAKSTS_MASK 0x8 -#define GC_USB_DCTL_GOUTNAKSTS_SIZE 0x1 -#define GC_USB_DCTL_GOUTNAKSTS_DEFAULT 0x0 -#define GC_USB_DCTL_GOUTNAKSTS_OFFSET 0x804 -#define GC_USB_DCTL_TSTCTL_LSB 0x4 -#define GC_USB_DCTL_TSTCTL_MASK 0x70 -#define GC_USB_DCTL_TSTCTL_SIZE 0x3 -#define GC_USB_DCTL_TSTCTL_DEFAULT 0x0 -#define GC_USB_DCTL_TSTCTL_OFFSET 0x804 -#define GC_USB_DCTL_SGNPINNAK_LSB 0x7 -#define GC_USB_DCTL_SGNPINNAK_MASK 0x80 -#define GC_USB_DCTL_SGNPINNAK_SIZE 0x1 -#define GC_USB_DCTL_SGNPINNAK_DEFAULT 0x0 -#define GC_USB_DCTL_SGNPINNAK_OFFSET 0x804 -#define GC_USB_DCTL_CGNPINNAK_LSB 0x8 -#define GC_USB_DCTL_CGNPINNAK_MASK 0x100 -#define GC_USB_DCTL_CGNPINNAK_SIZE 0x1 -#define GC_USB_DCTL_CGNPINNAK_DEFAULT 0x0 -#define GC_USB_DCTL_CGNPINNAK_OFFSET 0x804 -#define GC_USB_DCTL_SGOUTNAK_LSB 0x9 -#define GC_USB_DCTL_SGOUTNAK_MASK 0x200 -#define GC_USB_DCTL_SGOUTNAK_SIZE 0x1 -#define GC_USB_DCTL_SGOUTNAK_DEFAULT 0x0 -#define GC_USB_DCTL_SGOUTNAK_OFFSET 0x804 -#define GC_USB_DCTL_CGOUTNAK_LSB 0xa -#define GC_USB_DCTL_CGOUTNAK_MASK 0x400 -#define GC_USB_DCTL_CGOUTNAK_SIZE 0x1 -#define GC_USB_DCTL_CGOUTNAK_DEFAULT 0x0 -#define GC_USB_DCTL_CGOUTNAK_OFFSET 0x804 -#define GC_USB_DCTL_PWRONPRGDONE_LSB 0xb -#define GC_USB_DCTL_PWRONPRGDONE_MASK 0x800 -#define GC_USB_DCTL_PWRONPRGDONE_SIZE 0x1 -#define GC_USB_DCTL_PWRONPRGDONE_DEFAULT 0x0 -#define GC_USB_DCTL_PWRONPRGDONE_OFFSET 0x804 -#define GC_USB_DCTL_GMC_LSB 0xd -#define GC_USB_DCTL_GMC_MASK 0x6000 -#define GC_USB_DCTL_GMC_SIZE 0x2 -#define GC_USB_DCTL_GMC_DEFAULT 0x0 -#define GC_USB_DCTL_GMC_OFFSET 0x804 -#define GC_USB_DCTL_IGNRFRMNUM_LSB 0xf -#define GC_USB_DCTL_IGNRFRMNUM_MASK 0x8000 -#define GC_USB_DCTL_IGNRFRMNUM_SIZE 0x1 -#define GC_USB_DCTL_IGNRFRMNUM_DEFAULT 0x0 -#define GC_USB_DCTL_IGNRFRMNUM_OFFSET 0x804 -#define GC_USB_DCTL_NAKONBBLE_LSB 0x10 -#define GC_USB_DCTL_NAKONBBLE_MASK 0x10000 -#define GC_USB_DCTL_NAKONBBLE_SIZE 0x1 -#define GC_USB_DCTL_NAKONBBLE_DEFAULT 0x0 -#define GC_USB_DCTL_NAKONBBLE_OFFSET 0x804 -#define GC_USB_DCTL_ENCONTONBNA_LSB 0x11 -#define GC_USB_DCTL_ENCONTONBNA_MASK 0x20000 -#define GC_USB_DCTL_ENCONTONBNA_SIZE 0x1 -#define GC_USB_DCTL_ENCONTONBNA_DEFAULT 0x0 -#define GC_USB_DCTL_ENCONTONBNA_OFFSET 0x804 -#define GC_USB_DSTS_SUSPSTS_LSB 0x0 -#define GC_USB_DSTS_SUSPSTS_MASK 0x1 -#define GC_USB_DSTS_SUSPSTS_SIZE 0x1 -#define GC_USB_DSTS_SUSPSTS_DEFAULT 0x0 -#define GC_USB_DSTS_SUSPSTS_OFFSET 0x808 -#define GC_USB_DSTS_ENUMSPD_LSB 0x1 -#define GC_USB_DSTS_ENUMSPD_MASK 0x6 -#define GC_USB_DSTS_ENUMSPD_SIZE 0x2 -#define GC_USB_DSTS_ENUMSPD_DEFAULT 0x0 -#define GC_USB_DSTS_ENUMSPD_OFFSET 0x808 -#define GC_USB_DSTS_ERRTICERR_LSB 0x3 -#define GC_USB_DSTS_ERRTICERR_MASK 0x8 -#define GC_USB_DSTS_ERRTICERR_SIZE 0x1 -#define GC_USB_DSTS_ERRTICERR_DEFAULT 0x0 -#define GC_USB_DSTS_ERRTICERR_OFFSET 0x808 -#define GC_USB_DSTS_SOFFN_LSB 0x8 -#define GC_USB_DSTS_SOFFN_MASK 0x3fff00 -#define GC_USB_DSTS_SOFFN_SIZE 0xe -#define GC_USB_DSTS_SOFFN_DEFAULT 0x0 -#define GC_USB_DSTS_SOFFN_OFFSET 0x808 -#define GC_USB_DSTS_DEVLNSTS_LSB 0x16 -#define GC_USB_DSTS_DEVLNSTS_MASK 0xc00000 -#define GC_USB_DSTS_DEVLNSTS_SIZE 0x2 -#define GC_USB_DSTS_DEVLNSTS_DEFAULT 0x0 -#define GC_USB_DSTS_DEVLNSTS_OFFSET 0x808 -#define GC_USB_DIEPMSK_XFERCOMPLMSK_LSB 0x0 -#define GC_USB_DIEPMSK_XFERCOMPLMSK_MASK 0x1 -#define GC_USB_DIEPMSK_XFERCOMPLMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_XFERCOMPLMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_XFERCOMPLMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_EPDISBLDMSK_LSB 0x1 -#define GC_USB_DIEPMSK_EPDISBLDMSK_MASK 0x2 -#define GC_USB_DIEPMSK_EPDISBLDMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_EPDISBLDMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_EPDISBLDMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_AHBERRMSK_LSB 0x2 -#define GC_USB_DIEPMSK_AHBERRMSK_MASK 0x4 -#define GC_USB_DIEPMSK_AHBERRMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_AHBERRMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_AHBERRMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_TIMEOUTMSK_LSB 0x3 -#define GC_USB_DIEPMSK_TIMEOUTMSK_MASK 0x8 -#define GC_USB_DIEPMSK_TIMEOUTMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_TIMEOUTMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_TIMEOUTMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB 0x4 -#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_MASK 0x10 -#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_INTKNEPMISMSK_LSB 0x5 -#define GC_USB_DIEPMSK_INTKNEPMISMSK_MASK 0x20 -#define GC_USB_DIEPMSK_INTKNEPMISMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_INTKNEPMISMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_INTKNEPMISMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB 0x6 -#define GC_USB_DIEPMSK_INEPNAKEFFMSK_MASK 0x40 -#define GC_USB_DIEPMSK_INEPNAKEFFMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_INEPNAKEFFMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_RESERVED7_LSB 0x7 -#define GC_USB_DIEPMSK_RESERVED7_MASK 0x80 -#define GC_USB_DIEPMSK_RESERVED7_SIZE 0x1 -#define GC_USB_DIEPMSK_RESERVED7_DEFAULT 0x1 -#define GC_USB_DIEPMSK_RESERVED7_OFFSET 0x810 -#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB 0x8 -#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_MASK 0x100 -#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_BNAININTRMSK_LSB 0x9 -#define GC_USB_DIEPMSK_BNAININTRMSK_MASK 0x200 -#define GC_USB_DIEPMSK_BNAININTRMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_BNAININTRMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_BNAININTRMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_NAKMSK_LSB 0xd -#define GC_USB_DIEPMSK_NAKMSK_MASK 0x2000 -#define GC_USB_DIEPMSK_NAKMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_NAKMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_NAKMSK_OFFSET 0x810 -#define GC_USB_DOEPMSK_XFERCOMPLMSK_LSB 0x0 -#define GC_USB_DOEPMSK_XFERCOMPLMSK_MASK 0x1 -#define GC_USB_DOEPMSK_XFERCOMPLMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_XFERCOMPLMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_XFERCOMPLMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_EPDISBLDMSK_LSB 0x1 -#define GC_USB_DOEPMSK_EPDISBLDMSK_MASK 0x2 -#define GC_USB_DOEPMSK_EPDISBLDMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_EPDISBLDMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_EPDISBLDMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_AHBERRMSK_LSB 0x2 -#define GC_USB_DOEPMSK_AHBERRMSK_MASK 0x4 -#define GC_USB_DOEPMSK_AHBERRMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_AHBERRMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_AHBERRMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_SETUPMSK_LSB 0x3 -#define GC_USB_DOEPMSK_SETUPMSK_MASK 0x8 -#define GC_USB_DOEPMSK_SETUPMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_SETUPMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_SETUPMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB 0x4 -#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_MASK 0x10 -#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB 0x5 -#define GC_USB_DOEPMSK_STSPHSERCVDMSK_MASK 0x20 -#define GC_USB_DOEPMSK_STSPHSERCVDMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_STSPHSERCVDMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_STSPHSERCVDMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPMSK_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPMSK_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPMSK_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPMSK_BACK2BACKSETUP_OFFSET 0x814 -#define GC_USB_DOEPMSK_OUTPKTERRMSK_LSB 0x8 -#define GC_USB_DOEPMSK_OUTPKTERRMSK_MASK 0x100 -#define GC_USB_DOEPMSK_OUTPKTERRMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_OUTPKTERRMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_OUTPKTERRMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB 0x9 -#define GC_USB_DOEPMSK_BNAOUTINTRMSK_MASK 0x200 -#define GC_USB_DOEPMSK_BNAOUTINTRMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_BNAOUTINTRMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_BNAOUTINTRMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_BBLEERRMSK_LSB 0xc -#define GC_USB_DOEPMSK_BBLEERRMSK_MASK 0x1000 -#define GC_USB_DOEPMSK_BBLEERRMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_BBLEERRMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_BBLEERRMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_NAKMSK_LSB 0xd -#define GC_USB_DOEPMSK_NAKMSK_MASK 0x2000 -#define GC_USB_DOEPMSK_NAKMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_NAKMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_NAKMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_NYETMSK_LSB 0xe -#define GC_USB_DOEPMSK_NYETMSK_MASK 0x4000 -#define GC_USB_DOEPMSK_NYETMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_NYETMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_NYETMSK_OFFSET 0x814 -#define GC_USB_DAINT_INEPINT0_LSB 0x0 -#define GC_USB_DAINT_INEPINT0_MASK 0x1 -#define GC_USB_DAINT_INEPINT0_SIZE 0x1 -#define GC_USB_DAINT_INEPINT0_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT0_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT1_LSB 0x1 -#define GC_USB_DAINT_INEPINT1_MASK 0x2 -#define GC_USB_DAINT_INEPINT1_SIZE 0x1 -#define GC_USB_DAINT_INEPINT1_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT1_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT2_LSB 0x2 -#define GC_USB_DAINT_INEPINT2_MASK 0x4 -#define GC_USB_DAINT_INEPINT2_SIZE 0x1 -#define GC_USB_DAINT_INEPINT2_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT2_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT3_LSB 0x3 -#define GC_USB_DAINT_INEPINT3_MASK 0x8 -#define GC_USB_DAINT_INEPINT3_SIZE 0x1 -#define GC_USB_DAINT_INEPINT3_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT3_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT4_LSB 0x4 -#define GC_USB_DAINT_INEPINT4_MASK 0x10 -#define GC_USB_DAINT_INEPINT4_SIZE 0x1 -#define GC_USB_DAINT_INEPINT4_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT4_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT5_LSB 0x5 -#define GC_USB_DAINT_INEPINT5_MASK 0x20 -#define GC_USB_DAINT_INEPINT5_SIZE 0x1 -#define GC_USB_DAINT_INEPINT5_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT5_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT6_LSB 0x6 -#define GC_USB_DAINT_INEPINT6_MASK 0x40 -#define GC_USB_DAINT_INEPINT6_SIZE 0x1 -#define GC_USB_DAINT_INEPINT6_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT6_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT7_LSB 0x7 -#define GC_USB_DAINT_INEPINT7_MASK 0x80 -#define GC_USB_DAINT_INEPINT7_SIZE 0x1 -#define GC_USB_DAINT_INEPINT7_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT7_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT8_LSB 0x8 -#define GC_USB_DAINT_INEPINT8_MASK 0x100 -#define GC_USB_DAINT_INEPINT8_SIZE 0x1 -#define GC_USB_DAINT_INEPINT8_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT8_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT9_LSB 0x9 -#define GC_USB_DAINT_INEPINT9_MASK 0x200 -#define GC_USB_DAINT_INEPINT9_SIZE 0x1 -#define GC_USB_DAINT_INEPINT9_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT9_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT10_LSB 0xa -#define GC_USB_DAINT_INEPINT10_MASK 0x400 -#define GC_USB_DAINT_INEPINT10_SIZE 0x1 -#define GC_USB_DAINT_INEPINT10_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT10_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT11_LSB 0xb -#define GC_USB_DAINT_INEPINT11_MASK 0x800 -#define GC_USB_DAINT_INEPINT11_SIZE 0x1 -#define GC_USB_DAINT_INEPINT11_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT11_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT12_LSB 0xc -#define GC_USB_DAINT_INEPINT12_MASK 0x1000 -#define GC_USB_DAINT_INEPINT12_SIZE 0x1 -#define GC_USB_DAINT_INEPINT12_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT12_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT13_LSB 0xd -#define GC_USB_DAINT_INEPINT13_MASK 0x2000 -#define GC_USB_DAINT_INEPINT13_SIZE 0x1 -#define GC_USB_DAINT_INEPINT13_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT13_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT14_LSB 0xe -#define GC_USB_DAINT_INEPINT14_MASK 0x4000 -#define GC_USB_DAINT_INEPINT14_SIZE 0x1 -#define GC_USB_DAINT_INEPINT14_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT14_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT15_LSB 0xf -#define GC_USB_DAINT_INEPINT15_MASK 0x8000 -#define GC_USB_DAINT_INEPINT15_SIZE 0x1 -#define GC_USB_DAINT_INEPINT15_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT15_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT0_LSB 0x10 -#define GC_USB_DAINT_OUTEPINT0_MASK 0x10000 -#define GC_USB_DAINT_OUTEPINT0_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT0_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT0_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT1_LSB 0x11 -#define GC_USB_DAINT_OUTEPINT1_MASK 0x20000 -#define GC_USB_DAINT_OUTEPINT1_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT1_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT1_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT2_LSB 0x12 -#define GC_USB_DAINT_OUTEPINT2_MASK 0x40000 -#define GC_USB_DAINT_OUTEPINT2_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT2_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT2_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT3_LSB 0x13 -#define GC_USB_DAINT_OUTEPINT3_MASK 0x80000 -#define GC_USB_DAINT_OUTEPINT3_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT3_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT3_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT4_LSB 0x14 -#define GC_USB_DAINT_OUTEPINT4_MASK 0x100000 -#define GC_USB_DAINT_OUTEPINT4_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT4_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT4_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT5_LSB 0x15 -#define GC_USB_DAINT_OUTEPINT5_MASK 0x200000 -#define GC_USB_DAINT_OUTEPINT5_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT5_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT5_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT6_LSB 0x16 -#define GC_USB_DAINT_OUTEPINT6_MASK 0x400000 -#define GC_USB_DAINT_OUTEPINT6_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT6_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT6_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT7_LSB 0x17 -#define GC_USB_DAINT_OUTEPINT7_MASK 0x800000 -#define GC_USB_DAINT_OUTEPINT7_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT7_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT7_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT8_LSB 0x18 -#define GC_USB_DAINT_OUTEPINT8_MASK 0x1000000 -#define GC_USB_DAINT_OUTEPINT8_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT8_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT8_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT9_LSB 0x19 -#define GC_USB_DAINT_OUTEPINT9_MASK 0x2000000 -#define GC_USB_DAINT_OUTEPINT9_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT9_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT9_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT10_LSB 0x1a -#define GC_USB_DAINT_OUTEPINT10_MASK 0x4000000 -#define GC_USB_DAINT_OUTEPINT10_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT10_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT10_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT11_LSB 0x1b -#define GC_USB_DAINT_OUTEPINT11_MASK 0x8000000 -#define GC_USB_DAINT_OUTEPINT11_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT11_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT11_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT12_LSB 0x1c -#define GC_USB_DAINT_OUTEPINT12_MASK 0x10000000 -#define GC_USB_DAINT_OUTEPINT12_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT12_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT12_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT13_LSB 0x1d -#define GC_USB_DAINT_OUTEPINT13_MASK 0x20000000 -#define GC_USB_DAINT_OUTEPINT13_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT13_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT13_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT14_LSB 0x1e -#define GC_USB_DAINT_OUTEPINT14_MASK 0x40000000 -#define GC_USB_DAINT_OUTEPINT14_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT14_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT14_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT15_LSB 0x1f -#define GC_USB_DAINT_OUTEPINT15_MASK 0x80000000 -#define GC_USB_DAINT_OUTEPINT15_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT15_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT15_OFFSET 0x818 -#define GC_USB_DAINTMSK_INEPMSK0_LSB 0x0 -#define GC_USB_DAINTMSK_INEPMSK0_MASK 0x1 -#define GC_USB_DAINTMSK_INEPMSK0_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK0_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK0_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK1_LSB 0x1 -#define GC_USB_DAINTMSK_INEPMSK1_MASK 0x2 -#define GC_USB_DAINTMSK_INEPMSK1_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK1_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK1_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK2_LSB 0x2 -#define GC_USB_DAINTMSK_INEPMSK2_MASK 0x4 -#define GC_USB_DAINTMSK_INEPMSK2_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK2_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK2_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK3_LSB 0x3 -#define GC_USB_DAINTMSK_INEPMSK3_MASK 0x8 -#define GC_USB_DAINTMSK_INEPMSK3_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK3_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK3_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK4_LSB 0x4 -#define GC_USB_DAINTMSK_INEPMSK4_MASK 0x10 -#define GC_USB_DAINTMSK_INEPMSK4_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK4_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK4_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK5_LSB 0x5 -#define GC_USB_DAINTMSK_INEPMSK5_MASK 0x20 -#define GC_USB_DAINTMSK_INEPMSK5_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK5_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK5_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK6_LSB 0x6 -#define GC_USB_DAINTMSK_INEPMSK6_MASK 0x40 -#define GC_USB_DAINTMSK_INEPMSK6_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK6_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK6_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK7_LSB 0x7 -#define GC_USB_DAINTMSK_INEPMSK7_MASK 0x80 -#define GC_USB_DAINTMSK_INEPMSK7_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK7_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK7_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK8_LSB 0x8 -#define GC_USB_DAINTMSK_INEPMSK8_MASK 0x100 -#define GC_USB_DAINTMSK_INEPMSK8_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK8_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK8_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK9_LSB 0x9 -#define GC_USB_DAINTMSK_INEPMSK9_MASK 0x200 -#define GC_USB_DAINTMSK_INEPMSK9_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK9_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK9_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK10_LSB 0xa -#define GC_USB_DAINTMSK_INEPMSK10_MASK 0x400 -#define GC_USB_DAINTMSK_INEPMSK10_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK10_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK10_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK11_LSB 0xb -#define GC_USB_DAINTMSK_INEPMSK11_MASK 0x800 -#define GC_USB_DAINTMSK_INEPMSK11_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK11_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK11_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK12_LSB 0xc -#define GC_USB_DAINTMSK_INEPMSK12_MASK 0x1000 -#define GC_USB_DAINTMSK_INEPMSK12_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK12_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK12_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK13_LSB 0xd -#define GC_USB_DAINTMSK_INEPMSK13_MASK 0x2000 -#define GC_USB_DAINTMSK_INEPMSK13_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK13_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK13_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK14_LSB 0xe -#define GC_USB_DAINTMSK_INEPMSK14_MASK 0x4000 -#define GC_USB_DAINTMSK_INEPMSK14_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK14_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK14_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK15_LSB 0xf -#define GC_USB_DAINTMSK_INEPMSK15_MASK 0x8000 -#define GC_USB_DAINTMSK_INEPMSK15_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK15_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK15_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK0_LSB 0x10 -#define GC_USB_DAINTMSK_OUTEPMSK0_MASK 0x10000 -#define GC_USB_DAINTMSK_OUTEPMSK0_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK0_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK0_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK1_LSB 0x11 -#define GC_USB_DAINTMSK_OUTEPMSK1_MASK 0x20000 -#define GC_USB_DAINTMSK_OUTEPMSK1_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK1_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK1_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK2_LSB 0x12 -#define GC_USB_DAINTMSK_OUTEPMSK2_MASK 0x40000 -#define GC_USB_DAINTMSK_OUTEPMSK2_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK2_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK2_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK3_LSB 0x13 -#define GC_USB_DAINTMSK_OUTEPMSK3_MASK 0x80000 -#define GC_USB_DAINTMSK_OUTEPMSK3_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK3_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK3_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK4_LSB 0x14 -#define GC_USB_DAINTMSK_OUTEPMSK4_MASK 0x100000 -#define GC_USB_DAINTMSK_OUTEPMSK4_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK4_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK4_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK5_LSB 0x15 -#define GC_USB_DAINTMSK_OUTEPMSK5_MASK 0x200000 -#define GC_USB_DAINTMSK_OUTEPMSK5_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK5_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK5_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK6_LSB 0x16 -#define GC_USB_DAINTMSK_OUTEPMSK6_MASK 0x400000 -#define GC_USB_DAINTMSK_OUTEPMSK6_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK6_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK6_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK7_LSB 0x17 -#define GC_USB_DAINTMSK_OUTEPMSK7_MASK 0x800000 -#define GC_USB_DAINTMSK_OUTEPMSK7_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK7_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK7_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK8_LSB 0x18 -#define GC_USB_DAINTMSK_OUTEPMSK8_MASK 0x1000000 -#define GC_USB_DAINTMSK_OUTEPMSK8_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK8_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK8_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK9_LSB 0x19 -#define GC_USB_DAINTMSK_OUTEPMSK9_MASK 0x2000000 -#define GC_USB_DAINTMSK_OUTEPMSK9_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK9_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK9_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK10_LSB 0x1a -#define GC_USB_DAINTMSK_OUTEPMSK10_MASK 0x4000000 -#define GC_USB_DAINTMSK_OUTEPMSK10_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK10_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK10_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK11_LSB 0x1b -#define GC_USB_DAINTMSK_OUTEPMSK11_MASK 0x8000000 -#define GC_USB_DAINTMSK_OUTEPMSK11_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK11_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK11_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK12_LSB 0x1c -#define GC_USB_DAINTMSK_OUTEPMSK12_MASK 0x10000000 -#define GC_USB_DAINTMSK_OUTEPMSK12_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK12_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK12_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK13_LSB 0x1d -#define GC_USB_DAINTMSK_OUTEPMSK13_MASK 0x20000000 -#define GC_USB_DAINTMSK_OUTEPMSK13_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK13_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK13_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK14_LSB 0x1e -#define GC_USB_DAINTMSK_OUTEPMSK14_MASK 0x40000000 -#define GC_USB_DAINTMSK_OUTEPMSK14_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK14_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK14_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK15_LSB 0x1f -#define GC_USB_DAINTMSK_OUTEPMSK15_MASK 0x80000000 -#define GC_USB_DAINTMSK_OUTEPMSK15_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK15_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK15_OFFSET 0x81c -#define GC_USB_DVBUSDIS_DVBUSDIS_LSB 0x0 -#define GC_USB_DVBUSDIS_DVBUSDIS_MASK 0xffff -#define GC_USB_DVBUSDIS_DVBUSDIS_SIZE 0x10 -#define GC_USB_DVBUSDIS_DVBUSDIS_DEFAULT 0x0 -#define GC_USB_DVBUSDIS_DVBUSDIS_OFFSET 0x828 -#define GC_USB_DVBUSPULSE_DVBUSPULSE_LSB 0x0 -#define GC_USB_DVBUSPULSE_DVBUSPULSE_MASK 0xfff -#define GC_USB_DVBUSPULSE_DVBUSPULSE_SIZE 0xc -#define GC_USB_DVBUSPULSE_DVBUSPULSE_DEFAULT 0x0 -#define GC_USB_DVBUSPULSE_DVBUSPULSE_OFFSET 0x82c -#define GC_USB_DTHRCTL_NONISOTHREN_LSB 0x0 -#define GC_USB_DTHRCTL_NONISOTHREN_MASK 0x1 -#define GC_USB_DTHRCTL_NONISOTHREN_SIZE 0x1 -#define GC_USB_DTHRCTL_NONISOTHREN_DEFAULT 0x0 -#define GC_USB_DTHRCTL_NONISOTHREN_OFFSET 0x830 -#define GC_USB_DTHRCTL_ISOTHREN_LSB 0x1 -#define GC_USB_DTHRCTL_ISOTHREN_MASK 0x2 -#define GC_USB_DTHRCTL_ISOTHREN_SIZE 0x1 -#define GC_USB_DTHRCTL_ISOTHREN_DEFAULT 0x0 -#define GC_USB_DTHRCTL_ISOTHREN_OFFSET 0x830 -#define GC_USB_DTHRCTL_TXTHRLEN_LSB 0x2 -#define GC_USB_DTHRCTL_TXTHRLEN_MASK 0x7fc -#define GC_USB_DTHRCTL_TXTHRLEN_SIZE 0x9 -#define GC_USB_DTHRCTL_TXTHRLEN_DEFAULT 0x0 -#define GC_USB_DTHRCTL_TXTHRLEN_OFFSET 0x830 -#define GC_USB_DTHRCTL_AHBTHRRATIO_LSB 0xb -#define GC_USB_DTHRCTL_AHBTHRRATIO_MASK 0x1800 -#define GC_USB_DTHRCTL_AHBTHRRATIO_SIZE 0x2 -#define GC_USB_DTHRCTL_AHBTHRRATIO_DEFAULT 0x0 -#define GC_USB_DTHRCTL_AHBTHRRATIO_OFFSET 0x830 -#define GC_USB_DTHRCTL_RXTHREN_LSB 0x10 -#define GC_USB_DTHRCTL_RXTHREN_MASK 0x10000 -#define GC_USB_DTHRCTL_RXTHREN_SIZE 0x1 -#define GC_USB_DTHRCTL_RXTHREN_DEFAULT 0x0 -#define GC_USB_DTHRCTL_RXTHREN_OFFSET 0x830 -#define GC_USB_DTHRCTL_RXTHRLEN_LSB 0x11 -#define GC_USB_DTHRCTL_RXTHRLEN_MASK 0x3fe0000 -#define GC_USB_DTHRCTL_RXTHRLEN_SIZE 0x9 -#define GC_USB_DTHRCTL_RXTHRLEN_DEFAULT 0x0 -#define GC_USB_DTHRCTL_RXTHRLEN_OFFSET 0x830 -#define GC_USB_DTHRCTL_ARBPRKEN_LSB 0x1b -#define GC_USB_DTHRCTL_ARBPRKEN_MASK 0x8000000 -#define GC_USB_DTHRCTL_ARBPRKEN_SIZE 0x1 -#define GC_USB_DTHRCTL_ARBPRKEN_DEFAULT 0x0 -#define GC_USB_DTHRCTL_ARBPRKEN_OFFSET 0x830 -#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_LSB 0x0 -#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_MASK 0xffff -#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_SIZE 0x10 -#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_DEFAULT 0x0 -#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_OFFSET 0x834 -#define GC_USB_DIEPCTL0_MPS_LSB 0x0 -#define GC_USB_DIEPCTL0_MPS_MASK 0x3 -#define GC_USB_DIEPCTL0_MPS_SIZE 0x2 -#define GC_USB_DIEPCTL0_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_MPS_OFFSET 0x900 -#define GC_USB_DIEPCTL0_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL0_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL0_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL0_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_USBACTEP_OFFSET 0x900 -#define GC_USB_DIEPCTL0_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL0_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL0_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL0_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_NAKSTS_OFFSET 0x900 -#define GC_USB_DIEPCTL0_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL0_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL0_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL0_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_EPTYPE_OFFSET 0x900 -#define GC_USB_DIEPCTL0_STALL_LSB 0x15 -#define GC_USB_DIEPCTL0_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL0_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL0_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_STALL_OFFSET 0x900 -#define GC_USB_DIEPCTL0_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL0_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL0_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL0_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_TXFNUM_OFFSET 0x900 -#define GC_USB_DIEPCTL0_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL0_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL0_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL0_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_CNAK_OFFSET 0x900 -#define GC_USB_DIEPCTL0_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL0_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL0_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL0_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_SNAK_OFFSET 0x900 -#define GC_USB_DIEPCTL0_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL0_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL0_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL0_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_EPDIS_OFFSET 0x900 -#define GC_USB_DIEPCTL0_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL0_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL0_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL0_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_EPENA_OFFSET 0x900 -#define GC_USB_DIEPINT0_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT0_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT0_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT0_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT0_XFERCOMPL_OFFSET 0x908 -#define GC_USB_DIEPINT0_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT0_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT0_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT0_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT0_EPDISBLD_OFFSET 0x908 -#define GC_USB_DIEPINT0_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT0_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT0_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT0_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT0_AHBERR_OFFSET 0x908 -#define GC_USB_DIEPINT0_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT0_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT0_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT0_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT0_TIMEOUT_OFFSET 0x908 -#define GC_USB_DIEPINT0_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT0_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT0_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT0_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT0_INTKNTXFEMP_OFFSET 0x908 -#define GC_USB_DIEPINT0_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT0_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT0_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT0_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT0_INTKNEPMIS_OFFSET 0x908 -#define GC_USB_DIEPINT0_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT0_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT0_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT0_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT0_INEPNAKEFF_OFFSET 0x908 -#define GC_USB_DIEPINT0_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT0_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT0_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT0_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT0_TXFEMP_OFFSET 0x908 -#define GC_USB_DIEPINT0_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT0_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT0_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT0_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT0_TXFIFOUNDRN_OFFSET 0x908 -#define GC_USB_DIEPINT0_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT0_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT0_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT0_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT0_BNAINTR_OFFSET 0x908 -#define GC_USB_DIEPINT0_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT0_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT0_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT0_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT0_PKTDRPSTS_OFFSET 0x908 -#define GC_USB_DIEPINT0_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT0_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT0_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT0_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT0_BBLEERR_OFFSET 0x908 -#define GC_USB_DIEPINT0_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT0_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT0_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT0_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT0_NAKINTRPT_OFFSET 0x908 -#define GC_USB_DIEPINT0_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT0_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT0_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT0_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT0_NYETINTRPT_OFFSET 0x908 -#define GC_USB_DIEPTSIZ0_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ0_XFERSIZE_MASK 0x7f -#define GC_USB_DIEPTSIZ0_XFERSIZE_SIZE 0x7 -#define GC_USB_DIEPTSIZ0_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ0_XFERSIZE_OFFSET 0x910 -#define GC_USB_DIEPTSIZ0_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ0_PKTCNT_MASK 0x180000 -#define GC_USB_DIEPTSIZ0_PKTCNT_SIZE 0x2 -#define GC_USB_DIEPTSIZ0_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ0_PKTCNT_OFFSET 0x910 -#define GC_USB_DIEPDMA0_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA0_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA0_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA0_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA0_DMAADDR_OFFSET 0x914 -#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_OFFSET 0x918 -#define GC_USB_DIEPDMAB0_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB0_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB0_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB0_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB0_DMABUFFERADDR_OFFSET 0x91c -#define GC_USB_DIEPCTL1_MPS_LSB 0x0 -#define GC_USB_DIEPCTL1_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL1_MPS_SIZE 0xb -#define GC_USB_DIEPCTL1_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_MPS_OFFSET 0x920 -#define GC_USB_DIEPCTL1_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL1_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL1_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL1_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_USBACTEP_OFFSET 0x920 -#define GC_USB_DIEPCTL1_DPID_LSB 0x10 -#define GC_USB_DIEPCTL1_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL1_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL1_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_DPID_OFFSET 0x920 -#define GC_USB_DIEPCTL1_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL1_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL1_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL1_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_NAKSTS_OFFSET 0x920 -#define GC_USB_DIEPCTL1_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL1_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL1_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL1_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_EPTYPE_OFFSET 0x920 -#define GC_USB_DIEPCTL1_STALL_LSB 0x15 -#define GC_USB_DIEPCTL1_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL1_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL1_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_STALL_OFFSET 0x920 -#define GC_USB_DIEPCTL1_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL1_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL1_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL1_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_TXFNUM_OFFSET 0x920 -#define GC_USB_DIEPCTL1_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL1_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL1_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL1_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_CNAK_OFFSET 0x920 -#define GC_USB_DIEPCTL1_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL1_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL1_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL1_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_SNAK_OFFSET 0x920 -#define GC_USB_DIEPCTL1_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL1_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL1_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL1_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_SETD0PID_OFFSET 0x920 -#define GC_USB_DIEPCTL1_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL1_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL1_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL1_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_SETD1PID_OFFSET 0x920 -#define GC_USB_DIEPCTL1_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL1_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL1_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL1_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_EPDIS_OFFSET 0x920 -#define GC_USB_DIEPCTL1_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL1_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL1_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL1_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_EPENA_OFFSET 0x920 -#define GC_USB_DIEPINT1_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT1_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT1_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT1_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT1_XFERCOMPL_OFFSET 0x928 -#define GC_USB_DIEPINT1_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT1_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT1_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT1_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT1_EPDISBLD_OFFSET 0x928 -#define GC_USB_DIEPINT1_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT1_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT1_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT1_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT1_AHBERR_OFFSET 0x928 -#define GC_USB_DIEPINT1_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT1_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT1_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT1_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT1_TIMEOUT_OFFSET 0x928 -#define GC_USB_DIEPINT1_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT1_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT1_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT1_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT1_INTKNTXFEMP_OFFSET 0x928 -#define GC_USB_DIEPINT1_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT1_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT1_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT1_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT1_INTKNEPMIS_OFFSET 0x928 -#define GC_USB_DIEPINT1_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT1_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT1_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT1_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT1_INEPNAKEFF_OFFSET 0x928 -#define GC_USB_DIEPINT1_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT1_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT1_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT1_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT1_TXFEMP_OFFSET 0x928 -#define GC_USB_DIEPINT1_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT1_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT1_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT1_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT1_TXFIFOUNDRN_OFFSET 0x928 -#define GC_USB_DIEPINT1_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT1_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT1_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT1_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT1_BNAINTR_OFFSET 0x928 -#define GC_USB_DIEPINT1_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT1_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT1_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT1_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT1_PKTDRPSTS_OFFSET 0x928 -#define GC_USB_DIEPINT1_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT1_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT1_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT1_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT1_BBLEERR_OFFSET 0x928 -#define GC_USB_DIEPINT1_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT1_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT1_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT1_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT1_NAKINTRPT_OFFSET 0x928 -#define GC_USB_DIEPINT1_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT1_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT1_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT1_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT1_NYETINTRPT_OFFSET 0x928 -#define GC_USB_DIEPTSIZ1_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ1_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ1_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ1_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ1_XFERSIZE_OFFSET 0x930 -#define GC_USB_DIEPTSIZ1_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ1_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ1_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ1_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ1_PKTCNT_OFFSET 0x930 -#define GC_USB_DIEPTSIZ1_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ1_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ1_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ1_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ1_MC_OFFSET 0x930 -#define GC_USB_DIEPDMA1_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA1_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA1_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA1_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA1_DMAADDR_OFFSET 0x934 -#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_OFFSET 0x938 -#define GC_USB_DIEPDMAB1_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB1_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB1_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB1_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB1_DMABUFFERADDR_OFFSET 0x93c -#define GC_USB_DIEPCTL2_MPS_LSB 0x0 -#define GC_USB_DIEPCTL2_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL2_MPS_SIZE 0xb -#define GC_USB_DIEPCTL2_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_MPS_OFFSET 0x940 -#define GC_USB_DIEPCTL2_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL2_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL2_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL2_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_USBACTEP_OFFSET 0x940 -#define GC_USB_DIEPCTL2_DPID_LSB 0x10 -#define GC_USB_DIEPCTL2_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL2_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL2_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_DPID_OFFSET 0x940 -#define GC_USB_DIEPCTL2_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL2_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL2_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL2_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_NAKSTS_OFFSET 0x940 -#define GC_USB_DIEPCTL2_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL2_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL2_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL2_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_EPTYPE_OFFSET 0x940 -#define GC_USB_DIEPCTL2_STALL_LSB 0x15 -#define GC_USB_DIEPCTL2_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL2_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL2_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_STALL_OFFSET 0x940 -#define GC_USB_DIEPCTL2_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL2_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL2_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL2_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_TXFNUM_OFFSET 0x940 -#define GC_USB_DIEPCTL2_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL2_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL2_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL2_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_CNAK_OFFSET 0x940 -#define GC_USB_DIEPCTL2_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL2_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL2_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL2_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_SNAK_OFFSET 0x940 -#define GC_USB_DIEPCTL2_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL2_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL2_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL2_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_SETD0PID_OFFSET 0x940 -#define GC_USB_DIEPCTL2_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL2_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL2_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL2_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_SETD1PID_OFFSET 0x940 -#define GC_USB_DIEPCTL2_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL2_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL2_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL2_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_EPDIS_OFFSET 0x940 -#define GC_USB_DIEPCTL2_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL2_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL2_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL2_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_EPENA_OFFSET 0x940 -#define GC_USB_DIEPINT2_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT2_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT2_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT2_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT2_XFERCOMPL_OFFSET 0x948 -#define GC_USB_DIEPINT2_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT2_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT2_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT2_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT2_EPDISBLD_OFFSET 0x948 -#define GC_USB_DIEPINT2_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT2_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT2_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT2_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT2_AHBERR_OFFSET 0x948 -#define GC_USB_DIEPINT2_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT2_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT2_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT2_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT2_TIMEOUT_OFFSET 0x948 -#define GC_USB_DIEPINT2_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT2_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT2_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT2_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT2_INTKNTXFEMP_OFFSET 0x948 -#define GC_USB_DIEPINT2_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT2_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT2_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT2_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT2_INTKNEPMIS_OFFSET 0x948 -#define GC_USB_DIEPINT2_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT2_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT2_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT2_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT2_INEPNAKEFF_OFFSET 0x948 -#define GC_USB_DIEPINT2_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT2_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT2_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT2_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT2_TXFEMP_OFFSET 0x948 -#define GC_USB_DIEPINT2_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT2_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT2_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT2_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT2_TXFIFOUNDRN_OFFSET 0x948 -#define GC_USB_DIEPINT2_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT2_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT2_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT2_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT2_BNAINTR_OFFSET 0x948 -#define GC_USB_DIEPINT2_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT2_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT2_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT2_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT2_PKTDRPSTS_OFFSET 0x948 -#define GC_USB_DIEPINT2_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT2_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT2_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT2_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT2_BBLEERR_OFFSET 0x948 -#define GC_USB_DIEPINT2_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT2_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT2_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT2_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT2_NAKINTRPT_OFFSET 0x948 -#define GC_USB_DIEPINT2_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT2_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT2_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT2_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT2_NYETINTRPT_OFFSET 0x948 -#define GC_USB_DIEPTSIZ2_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ2_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ2_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ2_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ2_XFERSIZE_OFFSET 0x950 -#define GC_USB_DIEPTSIZ2_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ2_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ2_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ2_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ2_PKTCNT_OFFSET 0x950 -#define GC_USB_DIEPTSIZ2_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ2_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ2_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ2_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ2_MC_OFFSET 0x950 -#define GC_USB_DIEPDMA2_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA2_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA2_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA2_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA2_DMAADDR_OFFSET 0x954 -#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_OFFSET 0x958 -#define GC_USB_DIEPDMAB2_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB2_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB2_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB2_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB2_DMABUFFERADDR_OFFSET 0x95c -#define GC_USB_DIEPCTL3_MPS_LSB 0x0 -#define GC_USB_DIEPCTL3_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL3_MPS_SIZE 0xb -#define GC_USB_DIEPCTL3_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_MPS_OFFSET 0x960 -#define GC_USB_DIEPCTL3_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL3_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL3_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL3_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_USBACTEP_OFFSET 0x960 -#define GC_USB_DIEPCTL3_DPID_LSB 0x10 -#define GC_USB_DIEPCTL3_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL3_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL3_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_DPID_OFFSET 0x960 -#define GC_USB_DIEPCTL3_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL3_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL3_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL3_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_NAKSTS_OFFSET 0x960 -#define GC_USB_DIEPCTL3_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL3_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL3_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL3_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_EPTYPE_OFFSET 0x960 -#define GC_USB_DIEPCTL3_STALL_LSB 0x15 -#define GC_USB_DIEPCTL3_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL3_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL3_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_STALL_OFFSET 0x960 -#define GC_USB_DIEPCTL3_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL3_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL3_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL3_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_TXFNUM_OFFSET 0x960 -#define GC_USB_DIEPCTL3_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL3_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL3_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL3_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_CNAK_OFFSET 0x960 -#define GC_USB_DIEPCTL3_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL3_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL3_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL3_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_SNAK_OFFSET 0x960 -#define GC_USB_DIEPCTL3_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL3_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL3_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL3_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_SETD0PID_OFFSET 0x960 -#define GC_USB_DIEPCTL3_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL3_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL3_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL3_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_SETD1PID_OFFSET 0x960 -#define GC_USB_DIEPCTL3_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL3_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL3_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL3_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_EPDIS_OFFSET 0x960 -#define GC_USB_DIEPCTL3_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL3_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL3_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL3_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_EPENA_OFFSET 0x960 -#define GC_USB_DIEPINT3_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT3_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT3_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT3_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT3_XFERCOMPL_OFFSET 0x968 -#define GC_USB_DIEPINT3_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT3_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT3_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT3_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT3_EPDISBLD_OFFSET 0x968 -#define GC_USB_DIEPINT3_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT3_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT3_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT3_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT3_AHBERR_OFFSET 0x968 -#define GC_USB_DIEPINT3_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT3_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT3_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT3_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT3_TIMEOUT_OFFSET 0x968 -#define GC_USB_DIEPINT3_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT3_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT3_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT3_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT3_INTKNTXFEMP_OFFSET 0x968 -#define GC_USB_DIEPINT3_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT3_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT3_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT3_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT3_INTKNEPMIS_OFFSET 0x968 -#define GC_USB_DIEPINT3_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT3_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT3_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT3_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT3_INEPNAKEFF_OFFSET 0x968 -#define GC_USB_DIEPINT3_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT3_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT3_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT3_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT3_TXFEMP_OFFSET 0x968 -#define GC_USB_DIEPINT3_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT3_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT3_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT3_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT3_TXFIFOUNDRN_OFFSET 0x968 -#define GC_USB_DIEPINT3_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT3_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT3_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT3_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT3_BNAINTR_OFFSET 0x968 -#define GC_USB_DIEPINT3_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT3_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT3_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT3_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT3_PKTDRPSTS_OFFSET 0x968 -#define GC_USB_DIEPINT3_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT3_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT3_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT3_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT3_BBLEERR_OFFSET 0x968 -#define GC_USB_DIEPINT3_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT3_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT3_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT3_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT3_NAKINTRPT_OFFSET 0x968 -#define GC_USB_DIEPINT3_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT3_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT3_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT3_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT3_NYETINTRPT_OFFSET 0x968 -#define GC_USB_DIEPTSIZ3_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ3_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ3_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ3_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ3_XFERSIZE_OFFSET 0x970 -#define GC_USB_DIEPTSIZ3_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ3_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ3_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ3_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ3_PKTCNT_OFFSET 0x970 -#define GC_USB_DIEPTSIZ3_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ3_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ3_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ3_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ3_MC_OFFSET 0x970 -#define GC_USB_DIEPDMA3_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA3_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA3_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA3_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA3_DMAADDR_OFFSET 0x974 -#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_OFFSET 0x978 -#define GC_USB_DIEPDMAB3_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB3_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB3_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB3_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB3_DMABUFFERADDR_OFFSET 0x97c -#define GC_USB_DIEPCTL4_MPS_LSB 0x0 -#define GC_USB_DIEPCTL4_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL4_MPS_SIZE 0xb -#define GC_USB_DIEPCTL4_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_MPS_OFFSET 0x980 -#define GC_USB_DIEPCTL4_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL4_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL4_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL4_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_USBACTEP_OFFSET 0x980 -#define GC_USB_DIEPCTL4_DPID_LSB 0x10 -#define GC_USB_DIEPCTL4_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL4_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL4_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_DPID_OFFSET 0x980 -#define GC_USB_DIEPCTL4_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL4_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL4_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL4_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_NAKSTS_OFFSET 0x980 -#define GC_USB_DIEPCTL4_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL4_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL4_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL4_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_EPTYPE_OFFSET 0x980 -#define GC_USB_DIEPCTL4_STALL_LSB 0x15 -#define GC_USB_DIEPCTL4_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL4_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL4_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_STALL_OFFSET 0x980 -#define GC_USB_DIEPCTL4_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL4_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL4_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL4_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_TXFNUM_OFFSET 0x980 -#define GC_USB_DIEPCTL4_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL4_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL4_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL4_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_CNAK_OFFSET 0x980 -#define GC_USB_DIEPCTL4_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL4_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL4_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL4_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_SNAK_OFFSET 0x980 -#define GC_USB_DIEPCTL4_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL4_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL4_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL4_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_SETD0PID_OFFSET 0x980 -#define GC_USB_DIEPCTL4_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL4_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL4_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL4_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_SETD1PID_OFFSET 0x980 -#define GC_USB_DIEPCTL4_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL4_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL4_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL4_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_EPDIS_OFFSET 0x980 -#define GC_USB_DIEPCTL4_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL4_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL4_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL4_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_EPENA_OFFSET 0x980 -#define GC_USB_DIEPINT4_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT4_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT4_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT4_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT4_XFERCOMPL_OFFSET 0x988 -#define GC_USB_DIEPINT4_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT4_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT4_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT4_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT4_EPDISBLD_OFFSET 0x988 -#define GC_USB_DIEPINT4_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT4_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT4_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT4_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT4_AHBERR_OFFSET 0x988 -#define GC_USB_DIEPINT4_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT4_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT4_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT4_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT4_TIMEOUT_OFFSET 0x988 -#define GC_USB_DIEPINT4_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT4_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT4_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT4_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT4_INTKNTXFEMP_OFFSET 0x988 -#define GC_USB_DIEPINT4_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT4_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT4_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT4_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT4_INTKNEPMIS_OFFSET 0x988 -#define GC_USB_DIEPINT4_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT4_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT4_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT4_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT4_INEPNAKEFF_OFFSET 0x988 -#define GC_USB_DIEPINT4_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT4_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT4_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT4_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT4_TXFEMP_OFFSET 0x988 -#define GC_USB_DIEPINT4_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT4_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT4_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT4_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT4_TXFIFOUNDRN_OFFSET 0x988 -#define GC_USB_DIEPINT4_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT4_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT4_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT4_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT4_BNAINTR_OFFSET 0x988 -#define GC_USB_DIEPINT4_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT4_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT4_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT4_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT4_PKTDRPSTS_OFFSET 0x988 -#define GC_USB_DIEPINT4_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT4_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT4_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT4_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT4_BBLEERR_OFFSET 0x988 -#define GC_USB_DIEPINT4_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT4_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT4_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT4_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT4_NAKINTRPT_OFFSET 0x988 -#define GC_USB_DIEPINT4_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT4_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT4_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT4_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT4_NYETINTRPT_OFFSET 0x988 -#define GC_USB_DIEPTSIZ4_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ4_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ4_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ4_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ4_XFERSIZE_OFFSET 0x990 -#define GC_USB_DIEPTSIZ4_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ4_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ4_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ4_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ4_PKTCNT_OFFSET 0x990 -#define GC_USB_DIEPTSIZ4_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ4_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ4_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ4_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ4_MC_OFFSET 0x990 -#define GC_USB_DIEPDMA4_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA4_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA4_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA4_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA4_DMAADDR_OFFSET 0x994 -#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_OFFSET 0x998 -#define GC_USB_DIEPDMAB4_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB4_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB4_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB4_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB4_DMABUFFERADDR_OFFSET 0x99c -#define GC_USB_DIEPCTL5_MPS_LSB 0x0 -#define GC_USB_DIEPCTL5_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL5_MPS_SIZE 0xb -#define GC_USB_DIEPCTL5_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_MPS_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL5_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL5_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL5_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_USBACTEP_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_DPID_LSB 0x10 -#define GC_USB_DIEPCTL5_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL5_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL5_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_DPID_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL5_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL5_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL5_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_NAKSTS_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL5_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL5_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL5_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_EPTYPE_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_STALL_LSB 0x15 -#define GC_USB_DIEPCTL5_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL5_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL5_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_STALL_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL5_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL5_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL5_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_TXFNUM_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL5_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL5_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL5_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_CNAK_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL5_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL5_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL5_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_SNAK_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL5_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL5_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL5_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_SETD0PID_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL5_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL5_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL5_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_SETD1PID_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL5_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL5_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL5_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_EPDIS_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL5_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL5_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL5_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_EPENA_OFFSET 0x9a0 -#define GC_USB_DIEPINT5_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT5_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT5_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT5_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT5_XFERCOMPL_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT5_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT5_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT5_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT5_EPDISBLD_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT5_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT5_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT5_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT5_AHBERR_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT5_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT5_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT5_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT5_TIMEOUT_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT5_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT5_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT5_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT5_INTKNTXFEMP_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT5_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT5_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT5_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT5_INTKNEPMIS_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT5_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT5_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT5_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT5_INEPNAKEFF_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT5_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT5_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT5_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT5_TXFEMP_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT5_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT5_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT5_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT5_TXFIFOUNDRN_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT5_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT5_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT5_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT5_BNAINTR_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT5_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT5_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT5_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT5_PKTDRPSTS_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT5_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT5_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT5_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT5_BBLEERR_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT5_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT5_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT5_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT5_NAKINTRPT_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT5_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT5_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT5_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT5_NYETINTRPT_OFFSET 0x9a8 -#define GC_USB_DIEPTSIZ5_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ5_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ5_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ5_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ5_XFERSIZE_OFFSET 0x9b0 -#define GC_USB_DIEPTSIZ5_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ5_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ5_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ5_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ5_PKTCNT_OFFSET 0x9b0 -#define GC_USB_DIEPTSIZ5_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ5_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ5_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ5_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ5_MC_OFFSET 0x9b0 -#define GC_USB_DIEPDMA5_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA5_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA5_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA5_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA5_DMAADDR_OFFSET 0x9b4 -#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_OFFSET 0x9b8 -#define GC_USB_DIEPDMAB5_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB5_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB5_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB5_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB5_DMABUFFERADDR_OFFSET 0x9bc -#define GC_USB_DIEPCTL6_MPS_LSB 0x0 -#define GC_USB_DIEPCTL6_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL6_MPS_SIZE 0xb -#define GC_USB_DIEPCTL6_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_MPS_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL6_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL6_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL6_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_USBACTEP_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_DPID_LSB 0x10 -#define GC_USB_DIEPCTL6_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL6_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL6_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_DPID_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL6_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL6_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL6_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_NAKSTS_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL6_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL6_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL6_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_EPTYPE_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_STALL_LSB 0x15 -#define GC_USB_DIEPCTL6_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL6_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL6_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_STALL_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL6_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL6_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL6_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_TXFNUM_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL6_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL6_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL6_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_CNAK_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL6_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL6_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL6_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_SNAK_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL6_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL6_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL6_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_SETD0PID_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL6_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL6_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL6_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_SETD1PID_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL6_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL6_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL6_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_EPDIS_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL6_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL6_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL6_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_EPENA_OFFSET 0x9c0 -#define GC_USB_DIEPINT6_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT6_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT6_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT6_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT6_XFERCOMPL_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT6_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT6_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT6_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT6_EPDISBLD_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT6_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT6_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT6_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT6_AHBERR_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT6_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT6_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT6_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT6_TIMEOUT_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT6_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT6_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT6_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT6_INTKNTXFEMP_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT6_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT6_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT6_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT6_INTKNEPMIS_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT6_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT6_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT6_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT6_INEPNAKEFF_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT6_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT6_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT6_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT6_TXFEMP_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT6_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT6_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT6_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT6_TXFIFOUNDRN_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT6_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT6_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT6_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT6_BNAINTR_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT6_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT6_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT6_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT6_PKTDRPSTS_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT6_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT6_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT6_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT6_BBLEERR_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT6_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT6_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT6_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT6_NAKINTRPT_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT6_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT6_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT6_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT6_NYETINTRPT_OFFSET 0x9c8 -#define GC_USB_DIEPTSIZ6_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ6_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ6_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ6_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ6_XFERSIZE_OFFSET 0x9d0 -#define GC_USB_DIEPTSIZ6_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ6_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ6_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ6_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ6_PKTCNT_OFFSET 0x9d0 -#define GC_USB_DIEPTSIZ6_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ6_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ6_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ6_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ6_MC_OFFSET 0x9d0 -#define GC_USB_DIEPDMA6_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA6_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA6_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA6_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA6_DMAADDR_OFFSET 0x9d4 -#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_OFFSET 0x9d8 -#define GC_USB_DIEPDMAB6_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB6_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB6_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB6_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB6_DMABUFFERADDR_OFFSET 0x9dc -#define GC_USB_DIEPCTL7_MPS_LSB 0x0 -#define GC_USB_DIEPCTL7_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL7_MPS_SIZE 0xb -#define GC_USB_DIEPCTL7_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_MPS_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL7_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL7_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL7_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_USBACTEP_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_DPID_LSB 0x10 -#define GC_USB_DIEPCTL7_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL7_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL7_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_DPID_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL7_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL7_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL7_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_NAKSTS_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL7_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL7_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL7_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_EPTYPE_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_STALL_LSB 0x15 -#define GC_USB_DIEPCTL7_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL7_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL7_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_STALL_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL7_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL7_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL7_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_TXFNUM_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL7_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL7_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL7_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_CNAK_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL7_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL7_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL7_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_SNAK_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL7_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL7_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL7_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_SETD0PID_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL7_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL7_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL7_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_SETD1PID_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL7_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL7_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL7_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_EPDIS_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL7_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL7_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL7_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_EPENA_OFFSET 0x9e0 -#define GC_USB_DIEPINT7_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT7_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT7_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT7_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT7_XFERCOMPL_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT7_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT7_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT7_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT7_EPDISBLD_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT7_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT7_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT7_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT7_AHBERR_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT7_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT7_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT7_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT7_TIMEOUT_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT7_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT7_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT7_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT7_INTKNTXFEMP_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT7_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT7_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT7_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT7_INTKNEPMIS_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT7_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT7_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT7_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT7_INEPNAKEFF_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT7_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT7_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT7_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT7_TXFEMP_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT7_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT7_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT7_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT7_TXFIFOUNDRN_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT7_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT7_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT7_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT7_BNAINTR_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT7_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT7_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT7_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT7_PKTDRPSTS_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT7_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT7_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT7_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT7_BBLEERR_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT7_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT7_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT7_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT7_NAKINTRPT_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT7_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT7_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT7_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT7_NYETINTRPT_OFFSET 0x9e8 -#define GC_USB_DIEPTSIZ7_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ7_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ7_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ7_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ7_XFERSIZE_OFFSET 0x9f0 -#define GC_USB_DIEPTSIZ7_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ7_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ7_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ7_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ7_PKTCNT_OFFSET 0x9f0 -#define GC_USB_DIEPTSIZ7_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ7_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ7_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ7_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ7_MC_OFFSET 0x9f0 -#define GC_USB_DIEPDMA7_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA7_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA7_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA7_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA7_DMAADDR_OFFSET 0x9f4 -#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_OFFSET 0x9f8 -#define GC_USB_DIEPDMAB7_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB7_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB7_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB7_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB7_DMABUFFERADDR_OFFSET 0x9fc -#define GC_USB_DIEPCTL8_MPS_LSB 0x0 -#define GC_USB_DIEPCTL8_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL8_MPS_SIZE 0xb -#define GC_USB_DIEPCTL8_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_MPS_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL8_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL8_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL8_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_USBACTEP_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_DPID_LSB 0x10 -#define GC_USB_DIEPCTL8_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL8_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL8_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_DPID_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL8_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL8_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL8_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_NAKSTS_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL8_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL8_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL8_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_EPTYPE_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_STALL_LSB 0x15 -#define GC_USB_DIEPCTL8_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL8_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL8_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_STALL_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL8_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL8_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL8_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_TXFNUM_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL8_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL8_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL8_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_CNAK_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL8_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL8_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL8_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_SNAK_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL8_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL8_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL8_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_SETD0PID_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL8_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL8_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL8_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_SETD1PID_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL8_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL8_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL8_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_EPDIS_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL8_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL8_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL8_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_EPENA_OFFSET 0xa00 -#define GC_USB_DIEPINT8_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT8_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT8_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT8_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT8_XFERCOMPL_OFFSET 0xa08 -#define GC_USB_DIEPINT8_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT8_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT8_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT8_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT8_EPDISBLD_OFFSET 0xa08 -#define GC_USB_DIEPINT8_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT8_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT8_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT8_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT8_AHBERR_OFFSET 0xa08 -#define GC_USB_DIEPINT8_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT8_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT8_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT8_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT8_TIMEOUT_OFFSET 0xa08 -#define GC_USB_DIEPINT8_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT8_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT8_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT8_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT8_INTKNTXFEMP_OFFSET 0xa08 -#define GC_USB_DIEPINT8_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT8_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT8_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT8_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT8_INTKNEPMIS_OFFSET 0xa08 -#define GC_USB_DIEPINT8_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT8_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT8_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT8_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT8_INEPNAKEFF_OFFSET 0xa08 -#define GC_USB_DIEPINT8_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT8_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT8_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT8_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT8_TXFEMP_OFFSET 0xa08 -#define GC_USB_DIEPINT8_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT8_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT8_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT8_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT8_TXFIFOUNDRN_OFFSET 0xa08 -#define GC_USB_DIEPINT8_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT8_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT8_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT8_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT8_BNAINTR_OFFSET 0xa08 -#define GC_USB_DIEPINT8_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT8_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT8_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT8_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT8_PKTDRPSTS_OFFSET 0xa08 -#define GC_USB_DIEPINT8_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT8_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT8_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT8_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT8_BBLEERR_OFFSET 0xa08 -#define GC_USB_DIEPINT8_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT8_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT8_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT8_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT8_NAKINTRPT_OFFSET 0xa08 -#define GC_USB_DIEPINT8_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT8_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT8_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT8_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT8_NYETINTRPT_OFFSET 0xa08 -#define GC_USB_DIEPTSIZ8_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ8_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ8_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ8_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ8_XFERSIZE_OFFSET 0xa10 -#define GC_USB_DIEPTSIZ8_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ8_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ8_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ8_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ8_PKTCNT_OFFSET 0xa10 -#define GC_USB_DIEPTSIZ8_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ8_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ8_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ8_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ8_MC_OFFSET 0xa10 -#define GC_USB_DIEPDMA8_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA8_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA8_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA8_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA8_DMAADDR_OFFSET 0xa14 -#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_OFFSET 0xa18 -#define GC_USB_DIEPDMAB8_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB8_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB8_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB8_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB8_DMABUFFERADDR_OFFSET 0xa1c -#define GC_USB_DIEPCTL9_MPS_LSB 0x0 -#define GC_USB_DIEPCTL9_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL9_MPS_SIZE 0xb -#define GC_USB_DIEPCTL9_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_MPS_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL9_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL9_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL9_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_USBACTEP_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_DPID_LSB 0x10 -#define GC_USB_DIEPCTL9_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL9_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL9_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_DPID_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL9_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL9_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL9_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_NAKSTS_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL9_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL9_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL9_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_EPTYPE_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_STALL_LSB 0x15 -#define GC_USB_DIEPCTL9_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL9_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL9_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_STALL_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL9_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL9_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL9_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_TXFNUM_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL9_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL9_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL9_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_CNAK_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL9_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL9_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL9_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_SNAK_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL9_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL9_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL9_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_SETD0PID_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL9_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL9_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL9_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_SETD1PID_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL9_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL9_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL9_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_EPDIS_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL9_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL9_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL9_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_EPENA_OFFSET 0xa20 -#define GC_USB_DIEPINT9_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT9_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT9_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT9_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT9_XFERCOMPL_OFFSET 0xa28 -#define GC_USB_DIEPINT9_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT9_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT9_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT9_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT9_EPDISBLD_OFFSET 0xa28 -#define GC_USB_DIEPINT9_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT9_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT9_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT9_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT9_AHBERR_OFFSET 0xa28 -#define GC_USB_DIEPINT9_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT9_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT9_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT9_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT9_TIMEOUT_OFFSET 0xa28 -#define GC_USB_DIEPINT9_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT9_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT9_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT9_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT9_INTKNTXFEMP_OFFSET 0xa28 -#define GC_USB_DIEPINT9_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT9_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT9_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT9_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT9_INTKNEPMIS_OFFSET 0xa28 -#define GC_USB_DIEPINT9_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT9_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT9_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT9_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT9_INEPNAKEFF_OFFSET 0xa28 -#define GC_USB_DIEPINT9_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT9_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT9_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT9_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT9_TXFEMP_OFFSET 0xa28 -#define GC_USB_DIEPINT9_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT9_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT9_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT9_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT9_TXFIFOUNDRN_OFFSET 0xa28 -#define GC_USB_DIEPINT9_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT9_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT9_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT9_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT9_BNAINTR_OFFSET 0xa28 -#define GC_USB_DIEPINT9_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT9_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT9_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT9_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT9_PKTDRPSTS_OFFSET 0xa28 -#define GC_USB_DIEPINT9_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT9_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT9_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT9_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT9_BBLEERR_OFFSET 0xa28 -#define GC_USB_DIEPINT9_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT9_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT9_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT9_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT9_NAKINTRPT_OFFSET 0xa28 -#define GC_USB_DIEPINT9_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT9_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT9_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT9_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT9_NYETINTRPT_OFFSET 0xa28 -#define GC_USB_DIEPTSIZ9_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ9_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ9_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ9_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ9_XFERSIZE_OFFSET 0xa30 -#define GC_USB_DIEPTSIZ9_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ9_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ9_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ9_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ9_PKTCNT_OFFSET 0xa30 -#define GC_USB_DIEPTSIZ9_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ9_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ9_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ9_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ9_MC_OFFSET 0xa30 -#define GC_USB_DIEPDMA9_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA9_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA9_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA9_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA9_DMAADDR_OFFSET 0xa34 -#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_OFFSET 0xa38 -#define GC_USB_DIEPDMAB9_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB9_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB9_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB9_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB9_DMABUFFERADDR_OFFSET 0xa3c -#define GC_USB_DIEPCTL10_MPS_LSB 0x0 -#define GC_USB_DIEPCTL10_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL10_MPS_SIZE 0xb -#define GC_USB_DIEPCTL10_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_MPS_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL10_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL10_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL10_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_USBACTEP_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_DPID_LSB 0x10 -#define GC_USB_DIEPCTL10_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL10_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL10_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_DPID_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL10_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL10_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL10_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_NAKSTS_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL10_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL10_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL10_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_EPTYPE_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_STALL_LSB 0x15 -#define GC_USB_DIEPCTL10_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL10_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL10_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_STALL_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL10_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL10_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL10_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_TXFNUM_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL10_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL10_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL10_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_CNAK_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL10_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL10_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL10_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_SNAK_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL10_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL10_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL10_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_SETD0PID_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL10_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL10_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL10_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_SETD1PID_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL10_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL10_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL10_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_EPDIS_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL10_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL10_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL10_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_EPENA_OFFSET 0xa40 -#define GC_USB_DIEPINT10_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT10_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT10_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT10_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT10_XFERCOMPL_OFFSET 0xa48 -#define GC_USB_DIEPINT10_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT10_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT10_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT10_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT10_EPDISBLD_OFFSET 0xa48 -#define GC_USB_DIEPINT10_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT10_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT10_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT10_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT10_AHBERR_OFFSET 0xa48 -#define GC_USB_DIEPINT10_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT10_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT10_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT10_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT10_TIMEOUT_OFFSET 0xa48 -#define GC_USB_DIEPINT10_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT10_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT10_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT10_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT10_INTKNTXFEMP_OFFSET 0xa48 -#define GC_USB_DIEPINT10_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT10_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT10_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT10_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT10_INTKNEPMIS_OFFSET 0xa48 -#define GC_USB_DIEPINT10_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT10_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT10_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT10_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT10_INEPNAKEFF_OFFSET 0xa48 -#define GC_USB_DIEPINT10_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT10_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT10_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT10_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT10_TXFEMP_OFFSET 0xa48 -#define GC_USB_DIEPINT10_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT10_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT10_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT10_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT10_TXFIFOUNDRN_OFFSET 0xa48 -#define GC_USB_DIEPINT10_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT10_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT10_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT10_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT10_BNAINTR_OFFSET 0xa48 -#define GC_USB_DIEPINT10_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT10_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT10_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT10_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT10_PKTDRPSTS_OFFSET 0xa48 -#define GC_USB_DIEPINT10_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT10_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT10_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT10_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT10_BBLEERR_OFFSET 0xa48 -#define GC_USB_DIEPINT10_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT10_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT10_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT10_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT10_NAKINTRPT_OFFSET 0xa48 -#define GC_USB_DIEPINT10_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT10_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT10_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT10_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT10_NYETINTRPT_OFFSET 0xa48 -#define GC_USB_DIEPTSIZ10_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ10_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ10_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ10_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ10_XFERSIZE_OFFSET 0xa50 -#define GC_USB_DIEPTSIZ10_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ10_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ10_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ10_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ10_PKTCNT_OFFSET 0xa50 -#define GC_USB_DIEPTSIZ10_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ10_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ10_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ10_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ10_MC_OFFSET 0xa50 -#define GC_USB_DIEPDMA10_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA10_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA10_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA10_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA10_DMAADDR_OFFSET 0xa54 -#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_GHWCFG4_PHYDATAWIDTH_LSB 0xe +#define GC_USB_GHWCFG4_PHYDATAWIDTH_MASK 0xc000 +#define GC_USB_GHWCFG4_PHYDATAWIDTH_SIZE 0x2 +#define GC_USB_GHWCFG4_PHYDATAWIDTH_DEFAULT 0x0 +#define GC_USB_GHWCFG4_PHYDATAWIDTH_OFFSET 0x50 +#define GC_USB_GHWCFG4_NUMCTLEPS_LSB 0x10 +#define GC_USB_GHWCFG4_NUMCTLEPS_MASK 0xf0000 +#define GC_USB_GHWCFG4_NUMCTLEPS_SIZE 0x4 +#define GC_USB_GHWCFG4_NUMCTLEPS_DEFAULT 0x0 +#define GC_USB_GHWCFG4_NUMCTLEPS_OFFSET 0x50 +#define GC_USB_GHWCFG4_IDDGFLTR_LSB 0x14 +#define GC_USB_GHWCFG4_IDDGFLTR_MASK 0x100000 +#define GC_USB_GHWCFG4_IDDGFLTR_SIZE 0x1 +#define GC_USB_GHWCFG4_IDDGFLTR_DEFAULT 0x0 +#define GC_USB_GHWCFG4_IDDGFLTR_OFFSET 0x50 +#define GC_USB_GHWCFG4_VBUSVALIDFLTR_LSB 0x15 +#define GC_USB_GHWCFG4_VBUSVALIDFLTR_MASK 0x200000 +#define GC_USB_GHWCFG4_VBUSVALIDFLTR_SIZE 0x1 +#define GC_USB_GHWCFG4_VBUSVALIDFLTR_DEFAULT 0x0 +#define GC_USB_GHWCFG4_VBUSVALIDFLTR_OFFSET 0x50 +#define GC_USB_GHWCFG4_AVALIDFLTR_LSB 0x16 +#define GC_USB_GHWCFG4_AVALIDFLTR_MASK 0x400000 +#define GC_USB_GHWCFG4_AVALIDFLTR_SIZE 0x1 +#define GC_USB_GHWCFG4_AVALIDFLTR_DEFAULT 0x0 +#define GC_USB_GHWCFG4_AVALIDFLTR_OFFSET 0x50 +#define GC_USB_GHWCFG4_BVALIDFLTR_LSB 0x17 +#define GC_USB_GHWCFG4_BVALIDFLTR_MASK 0x800000 +#define GC_USB_GHWCFG4_BVALIDFLTR_SIZE 0x1 +#define GC_USB_GHWCFG4_BVALIDFLTR_DEFAULT 0x0 +#define GC_USB_GHWCFG4_BVALIDFLTR_OFFSET 0x50 +#define GC_USB_GHWCFG4_SESSENDFLTR_LSB 0x18 +#define GC_USB_GHWCFG4_SESSENDFLTR_MASK 0x1000000 +#define GC_USB_GHWCFG4_SESSENDFLTR_SIZE 0x1 +#define GC_USB_GHWCFG4_SESSENDFLTR_DEFAULT 0x0 +#define GC_USB_GHWCFG4_SESSENDFLTR_OFFSET 0x50 +#define GC_USB_GHWCFG4_DEDFIFOMODE_LSB 0x19 +#define GC_USB_GHWCFG4_DEDFIFOMODE_MASK 0x2000000 +#define GC_USB_GHWCFG4_DEDFIFOMODE_SIZE 0x1 +#define GC_USB_GHWCFG4_DEDFIFOMODE_DEFAULT 0x0 +#define GC_USB_GHWCFG4_DEDFIFOMODE_OFFSET 0x50 +#define GC_USB_GHWCFG4_INEPS_LSB 0x1a +#define GC_USB_GHWCFG4_INEPS_MASK 0x3c000000 +#define GC_USB_GHWCFG4_INEPS_SIZE 0x4 +#define GC_USB_GHWCFG4_INEPS_DEFAULT 0x0 +#define GC_USB_GHWCFG4_INEPS_OFFSET 0x50 +#define GC_USB_GHWCFG4_DESCDMAENABLED_LSB 0x1e +#define GC_USB_GHWCFG4_DESCDMAENABLED_MASK 0x40000000 +#define GC_USB_GHWCFG4_DESCDMAENABLED_SIZE 0x1 +#define GC_USB_GHWCFG4_DESCDMAENABLED_DEFAULT 0x0 +#define GC_USB_GHWCFG4_DESCDMAENABLED_OFFSET 0x50 +#define GC_USB_GHWCFG4_DESCDMA_LSB 0x1f +#define GC_USB_GHWCFG4_DESCDMA_MASK 0x80000000 +#define GC_USB_GHWCFG4_DESCDMA_SIZE 0x1 +#define GC_USB_GHWCFG4_DESCDMA_DEFAULT 0x0 +#define GC_USB_GHWCFG4_DESCDMA_OFFSET 0x50 +#define GC_USB_GDFIFOCFG_GDFIFOCFG_LSB 0x0 +#define GC_USB_GDFIFOCFG_GDFIFOCFG_MASK 0xffff +#define GC_USB_GDFIFOCFG_GDFIFOCFG_SIZE 0x10 +#define GC_USB_GDFIFOCFG_GDFIFOCFG_DEFAULT 0x0 +#define GC_USB_GDFIFOCFG_GDFIFOCFG_OFFSET 0x5c +#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_LSB 0x10 +#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_MASK 0xffff0000 +#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_SIZE 0x10 +#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT 0x0 +#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_OFFSET 0x5c +#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_OFFSET 0x104 +#define GC_USB_DIEPTXF1_RESERVED11_LSB 0xc +#define GC_USB_DIEPTXF1_RESERVED11_MASK 0x1000 +#define GC_USB_DIEPTXF1_RESERVED11_SIZE 0x1 +#define GC_USB_DIEPTXF1_RESERVED11_DEFAULT 0x1 +#define GC_USB_DIEPTXF1_RESERVED11_OFFSET 0x104 +#define GC_USB_DIEPTXF1_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF1_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF1_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF1_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF1_INEPNTXFDEP_OFFSET 0x104 +#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_OFFSET 0x108 +#define GC_USB_DIEPTXF2_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF2_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF2_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF2_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF2_INEPNTXFDEP_OFFSET 0x108 +#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_OFFSET 0x10c +#define GC_USB_DIEPTXF3_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF3_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF3_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF3_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF3_INEPNTXFDEP_OFFSET 0x10c +#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_OFFSET 0x110 +#define GC_USB_DIEPTXF4_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF4_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF4_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF4_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF4_INEPNTXFDEP_OFFSET 0x110 +#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_OFFSET 0x114 +#define GC_USB_DIEPTXF5_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF5_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF5_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF5_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF5_INEPNTXFDEP_OFFSET 0x114 +#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_OFFSET 0x118 +#define GC_USB_DIEPTXF6_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF6_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF6_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF6_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF6_INEPNTXFDEP_OFFSET 0x118 +#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_OFFSET 0x11c +#define GC_USB_DIEPTXF7_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF7_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF7_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF7_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF7_INEPNTXFDEP_OFFSET 0x11c +#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_OFFSET 0x120 +#define GC_USB_DIEPTXF8_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF8_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF8_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF8_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF8_INEPNTXFDEP_OFFSET 0x120 +#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_OFFSET 0x124 +#define GC_USB_DIEPTXF9_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF9_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF9_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF9_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF9_INEPNTXFDEP_OFFSET 0x124 +#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_OFFSET 0x128 +#define GC_USB_DIEPTXF10_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF10_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF10_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF10_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF10_INEPNTXFDEP_OFFSET 0x128 +#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_OFFSET 0x12c +#define GC_USB_DIEPTXF11_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF11_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF11_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF11_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF11_INEPNTXFDEP_OFFSET 0x12c +#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_OFFSET 0x130 +#define GC_USB_DIEPTXF12_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF12_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF12_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF12_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF12_INEPNTXFDEP_OFFSET 0x130 +#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_OFFSET 0x134 +#define GC_USB_DIEPTXF13_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF13_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF13_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF13_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF13_INEPNTXFDEP_OFFSET 0x134 +#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_OFFSET 0x138 +#define GC_USB_DIEPTXF14_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF14_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF14_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF14_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF14_INEPNTXFDEP_OFFSET 0x138 +#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_OFFSET 0x13c +#define GC_USB_DIEPTXF15_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF15_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF15_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF15_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF15_INEPNTXFDEP_OFFSET 0x13c +#define GC_USB_DCFG_DEVSPD_LSB 0x0 +#define GC_USB_DCFG_DEVSPD_MASK 0x3 +#define GC_USB_DCFG_DEVSPD_SIZE 0x2 +#define GC_USB_DCFG_DEVSPD_DEFAULT 0x0 +#define GC_USB_DCFG_DEVSPD_OFFSET 0x800 +#define GC_USB_DCFG_NZSTSOUTHSHK_LSB 0x2 +#define GC_USB_DCFG_NZSTSOUTHSHK_MASK 0x4 +#define GC_USB_DCFG_NZSTSOUTHSHK_SIZE 0x1 +#define GC_USB_DCFG_NZSTSOUTHSHK_DEFAULT 0x0 +#define GC_USB_DCFG_NZSTSOUTHSHK_OFFSET 0x800 +#define GC_USB_DCFG_ENA32KHZSUSP_LSB 0x3 +#define GC_USB_DCFG_ENA32KHZSUSP_MASK 0x8 +#define GC_USB_DCFG_ENA32KHZSUSP_SIZE 0x1 +#define GC_USB_DCFG_ENA32KHZSUSP_DEFAULT 0x0 +#define GC_USB_DCFG_ENA32KHZSUSP_OFFSET 0x800 +#define GC_USB_DCFG_DEVADDR_LSB 0x4 +#define GC_USB_DCFG_DEVADDR_MASK 0x7f0 +#define GC_USB_DCFG_DEVADDR_SIZE 0x7 +#define GC_USB_DCFG_DEVADDR_DEFAULT 0x0 +#define GC_USB_DCFG_DEVADDR_OFFSET 0x800 +#define GC_USB_DCFG_PERFRINT_LSB 0xb +#define GC_USB_DCFG_PERFRINT_MASK 0x1800 +#define GC_USB_DCFG_PERFRINT_SIZE 0x2 +#define GC_USB_DCFG_PERFRINT_DEFAULT 0x0 +#define GC_USB_DCFG_PERFRINT_OFFSET 0x800 +#define GC_USB_DCFG_ENDEVOUTNAK_LSB 0xd +#define GC_USB_DCFG_ENDEVOUTNAK_MASK 0x2000 +#define GC_USB_DCFG_ENDEVOUTNAK_SIZE 0x1 +#define GC_USB_DCFG_ENDEVOUTNAK_DEFAULT 0x0 +#define GC_USB_DCFG_ENDEVOUTNAK_OFFSET 0x800 +#define GC_USB_DCFG_XCVRDLY_LSB 0xe +#define GC_USB_DCFG_XCVRDLY_MASK 0x4000 +#define GC_USB_DCFG_XCVRDLY_SIZE 0x1 +#define GC_USB_DCFG_XCVRDLY_DEFAULT 0x0 +#define GC_USB_DCFG_XCVRDLY_OFFSET 0x800 +#define GC_USB_DCFG_ERRATICINTMSK_LSB 0xf +#define GC_USB_DCFG_ERRATICINTMSK_MASK 0x8000 +#define GC_USB_DCFG_ERRATICINTMSK_SIZE 0x1 +#define GC_USB_DCFG_ERRATICINTMSK_DEFAULT 0x0 +#define GC_USB_DCFG_ERRATICINTMSK_OFFSET 0x800 +#define GC_USB_DCFG_DESCDMA_LSB 0x17 +#define GC_USB_DCFG_DESCDMA_MASK 0x800000 +#define GC_USB_DCFG_DESCDMA_SIZE 0x1 +#define GC_USB_DCFG_DESCDMA_DEFAULT 0x0 +#define GC_USB_DCFG_DESCDMA_OFFSET 0x800 +#define GC_USB_DCFG_PERSCHINTVL_LSB 0x18 +#define GC_USB_DCFG_PERSCHINTVL_MASK 0x3000000 +#define GC_USB_DCFG_PERSCHINTVL_SIZE 0x2 +#define GC_USB_DCFG_PERSCHINTVL_DEFAULT 0x0 +#define GC_USB_DCFG_PERSCHINTVL_OFFSET 0x800 +#define GC_USB_DCFG_RESVALID_LSB 0x1a +#define GC_USB_DCFG_RESVALID_MASK 0xfc000000 +#define GC_USB_DCFG_RESVALID_SIZE 0x6 +#define GC_USB_DCFG_RESVALID_DEFAULT 0x2 +#define GC_USB_DCFG_RESVALID_OFFSET 0x800 +#define GC_USB_DCTL_RMTWKUPSIG_LSB 0x0 +#define GC_USB_DCTL_RMTWKUPSIG_MASK 0x1 +#define GC_USB_DCTL_RMTWKUPSIG_SIZE 0x1 +#define GC_USB_DCTL_RMTWKUPSIG_DEFAULT 0x0 +#define GC_USB_DCTL_RMTWKUPSIG_OFFSET 0x804 +#define GC_USB_DCTL_SFTDISCON_LSB 0x1 +#define GC_USB_DCTL_SFTDISCON_MASK 0x2 +#define GC_USB_DCTL_SFTDISCON_SIZE 0x1 +#define GC_USB_DCTL_SFTDISCON_DEFAULT 0x0 +#define GC_USB_DCTL_SFTDISCON_OFFSET 0x804 +#define GC_USB_DCTL_GNPINNAKSTS_LSB 0x2 +#define GC_USB_DCTL_GNPINNAKSTS_MASK 0x4 +#define GC_USB_DCTL_GNPINNAKSTS_SIZE 0x1 +#define GC_USB_DCTL_GNPINNAKSTS_DEFAULT 0x0 +#define GC_USB_DCTL_GNPINNAKSTS_OFFSET 0x804 +#define GC_USB_DCTL_GOUTNAKSTS_LSB 0x3 +#define GC_USB_DCTL_GOUTNAKSTS_MASK 0x8 +#define GC_USB_DCTL_GOUTNAKSTS_SIZE 0x1 +#define GC_USB_DCTL_GOUTNAKSTS_DEFAULT 0x0 +#define GC_USB_DCTL_GOUTNAKSTS_OFFSET 0x804 +#define GC_USB_DCTL_TSTCTL_LSB 0x4 +#define GC_USB_DCTL_TSTCTL_MASK 0x70 +#define GC_USB_DCTL_TSTCTL_SIZE 0x3 +#define GC_USB_DCTL_TSTCTL_DEFAULT 0x0 +#define GC_USB_DCTL_TSTCTL_OFFSET 0x804 +#define GC_USB_DCTL_SGNPINNAK_LSB 0x7 +#define GC_USB_DCTL_SGNPINNAK_MASK 0x80 +#define GC_USB_DCTL_SGNPINNAK_SIZE 0x1 +#define GC_USB_DCTL_SGNPINNAK_DEFAULT 0x0 +#define GC_USB_DCTL_SGNPINNAK_OFFSET 0x804 +#define GC_USB_DCTL_CGNPINNAK_LSB 0x8 +#define GC_USB_DCTL_CGNPINNAK_MASK 0x100 +#define GC_USB_DCTL_CGNPINNAK_SIZE 0x1 +#define GC_USB_DCTL_CGNPINNAK_DEFAULT 0x0 +#define GC_USB_DCTL_CGNPINNAK_OFFSET 0x804 +#define GC_USB_DCTL_SGOUTNAK_LSB 0x9 +#define GC_USB_DCTL_SGOUTNAK_MASK 0x200 +#define GC_USB_DCTL_SGOUTNAK_SIZE 0x1 +#define GC_USB_DCTL_SGOUTNAK_DEFAULT 0x0 +#define GC_USB_DCTL_SGOUTNAK_OFFSET 0x804 +#define GC_USB_DCTL_CGOUTNAK_LSB 0xa +#define GC_USB_DCTL_CGOUTNAK_MASK 0x400 +#define GC_USB_DCTL_CGOUTNAK_SIZE 0x1 +#define GC_USB_DCTL_CGOUTNAK_DEFAULT 0x0 +#define GC_USB_DCTL_CGOUTNAK_OFFSET 0x804 +#define GC_USB_DCTL_PWRONPRGDONE_LSB 0xb +#define GC_USB_DCTL_PWRONPRGDONE_MASK 0x800 +#define GC_USB_DCTL_PWRONPRGDONE_SIZE 0x1 +#define GC_USB_DCTL_PWRONPRGDONE_DEFAULT 0x0 +#define GC_USB_DCTL_PWRONPRGDONE_OFFSET 0x804 +#define GC_USB_DCTL_GMC_LSB 0xd +#define GC_USB_DCTL_GMC_MASK 0x6000 +#define GC_USB_DCTL_GMC_SIZE 0x2 +#define GC_USB_DCTL_GMC_DEFAULT 0x0 +#define GC_USB_DCTL_GMC_OFFSET 0x804 +#define GC_USB_DCTL_IGNRFRMNUM_LSB 0xf +#define GC_USB_DCTL_IGNRFRMNUM_MASK 0x8000 +#define GC_USB_DCTL_IGNRFRMNUM_SIZE 0x1 +#define GC_USB_DCTL_IGNRFRMNUM_DEFAULT 0x0 +#define GC_USB_DCTL_IGNRFRMNUM_OFFSET 0x804 +#define GC_USB_DCTL_NAKONBBLE_LSB 0x10 +#define GC_USB_DCTL_NAKONBBLE_MASK 0x10000 +#define GC_USB_DCTL_NAKONBBLE_SIZE 0x1 +#define GC_USB_DCTL_NAKONBBLE_DEFAULT 0x0 +#define GC_USB_DCTL_NAKONBBLE_OFFSET 0x804 +#define GC_USB_DCTL_ENCONTONBNA_LSB 0x11 +#define GC_USB_DCTL_ENCONTONBNA_MASK 0x20000 +#define GC_USB_DCTL_ENCONTONBNA_SIZE 0x1 +#define GC_USB_DCTL_ENCONTONBNA_DEFAULT 0x0 +#define GC_USB_DCTL_ENCONTONBNA_OFFSET 0x804 +#define GC_USB_DSTS_SUSPSTS_LSB 0x0 +#define GC_USB_DSTS_SUSPSTS_MASK 0x1 +#define GC_USB_DSTS_SUSPSTS_SIZE 0x1 +#define GC_USB_DSTS_SUSPSTS_DEFAULT 0x0 +#define GC_USB_DSTS_SUSPSTS_OFFSET 0x808 +#define GC_USB_DSTS_ENUMSPD_LSB 0x1 +#define GC_USB_DSTS_ENUMSPD_MASK 0x6 +#define GC_USB_DSTS_ENUMSPD_SIZE 0x2 +#define GC_USB_DSTS_ENUMSPD_DEFAULT 0x0 +#define GC_USB_DSTS_ENUMSPD_OFFSET 0x808 +#define GC_USB_DSTS_ERRTICERR_LSB 0x3 +#define GC_USB_DSTS_ERRTICERR_MASK 0x8 +#define GC_USB_DSTS_ERRTICERR_SIZE 0x1 +#define GC_USB_DSTS_ERRTICERR_DEFAULT 0x0 +#define GC_USB_DSTS_ERRTICERR_OFFSET 0x808 +#define GC_USB_DSTS_SOFFN_LSB 0x8 +#define GC_USB_DSTS_SOFFN_MASK 0x3fff00 +#define GC_USB_DSTS_SOFFN_SIZE 0xe +#define GC_USB_DSTS_SOFFN_DEFAULT 0x0 +#define GC_USB_DSTS_SOFFN_OFFSET 0x808 +#define GC_USB_DSTS_DEVLNSTS_LSB 0x16 +#define GC_USB_DSTS_DEVLNSTS_MASK 0xc00000 +#define GC_USB_DSTS_DEVLNSTS_SIZE 0x2 +#define GC_USB_DSTS_DEVLNSTS_DEFAULT 0x0 +#define GC_USB_DSTS_DEVLNSTS_OFFSET 0x808 +#define GC_USB_DIEPMSK_XFERCOMPLMSK_LSB 0x0 +#define GC_USB_DIEPMSK_XFERCOMPLMSK_MASK 0x1 +#define GC_USB_DIEPMSK_XFERCOMPLMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_XFERCOMPLMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_XFERCOMPLMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_EPDISBLDMSK_LSB 0x1 +#define GC_USB_DIEPMSK_EPDISBLDMSK_MASK 0x2 +#define GC_USB_DIEPMSK_EPDISBLDMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_EPDISBLDMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_EPDISBLDMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_AHBERRMSK_LSB 0x2 +#define GC_USB_DIEPMSK_AHBERRMSK_MASK 0x4 +#define GC_USB_DIEPMSK_AHBERRMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_AHBERRMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_AHBERRMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_TIMEOUTMSK_LSB 0x3 +#define GC_USB_DIEPMSK_TIMEOUTMSK_MASK 0x8 +#define GC_USB_DIEPMSK_TIMEOUTMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_TIMEOUTMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_TIMEOUTMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB 0x4 +#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_MASK 0x10 +#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_INTKNEPMISMSK_LSB 0x5 +#define GC_USB_DIEPMSK_INTKNEPMISMSK_MASK 0x20 +#define GC_USB_DIEPMSK_INTKNEPMISMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_INTKNEPMISMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_INTKNEPMISMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB 0x6 +#define GC_USB_DIEPMSK_INEPNAKEFFMSK_MASK 0x40 +#define GC_USB_DIEPMSK_INEPNAKEFFMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_INEPNAKEFFMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_RESERVED7_LSB 0x7 +#define GC_USB_DIEPMSK_RESERVED7_MASK 0x80 +#define GC_USB_DIEPMSK_RESERVED7_SIZE 0x1 +#define GC_USB_DIEPMSK_RESERVED7_DEFAULT 0x1 +#define GC_USB_DIEPMSK_RESERVED7_OFFSET 0x810 +#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB 0x8 +#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_MASK 0x100 +#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_BNAININTRMSK_LSB 0x9 +#define GC_USB_DIEPMSK_BNAININTRMSK_MASK 0x200 +#define GC_USB_DIEPMSK_BNAININTRMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_BNAININTRMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_BNAININTRMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_NAKMSK_LSB 0xd +#define GC_USB_DIEPMSK_NAKMSK_MASK 0x2000 +#define GC_USB_DIEPMSK_NAKMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_NAKMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_NAKMSK_OFFSET 0x810 +#define GC_USB_DOEPMSK_XFERCOMPLMSK_LSB 0x0 +#define GC_USB_DOEPMSK_XFERCOMPLMSK_MASK 0x1 +#define GC_USB_DOEPMSK_XFERCOMPLMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_XFERCOMPLMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_XFERCOMPLMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_EPDISBLDMSK_LSB 0x1 +#define GC_USB_DOEPMSK_EPDISBLDMSK_MASK 0x2 +#define GC_USB_DOEPMSK_EPDISBLDMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_EPDISBLDMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_EPDISBLDMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_AHBERRMSK_LSB 0x2 +#define GC_USB_DOEPMSK_AHBERRMSK_MASK 0x4 +#define GC_USB_DOEPMSK_AHBERRMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_AHBERRMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_AHBERRMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_SETUPMSK_LSB 0x3 +#define GC_USB_DOEPMSK_SETUPMSK_MASK 0x8 +#define GC_USB_DOEPMSK_SETUPMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_SETUPMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_SETUPMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB 0x4 +#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_MASK 0x10 +#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB 0x5 +#define GC_USB_DOEPMSK_STSPHSERCVDMSK_MASK 0x20 +#define GC_USB_DOEPMSK_STSPHSERCVDMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_STSPHSERCVDMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_STSPHSERCVDMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPMSK_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPMSK_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPMSK_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPMSK_BACK2BACKSETUP_OFFSET 0x814 +#define GC_USB_DOEPMSK_OUTPKTERRMSK_LSB 0x8 +#define GC_USB_DOEPMSK_OUTPKTERRMSK_MASK 0x100 +#define GC_USB_DOEPMSK_OUTPKTERRMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_OUTPKTERRMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_OUTPKTERRMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB 0x9 +#define GC_USB_DOEPMSK_BNAOUTINTRMSK_MASK 0x200 +#define GC_USB_DOEPMSK_BNAOUTINTRMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_BNAOUTINTRMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_BNAOUTINTRMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_BBLEERRMSK_LSB 0xc +#define GC_USB_DOEPMSK_BBLEERRMSK_MASK 0x1000 +#define GC_USB_DOEPMSK_BBLEERRMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_BBLEERRMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_BBLEERRMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_NAKMSK_LSB 0xd +#define GC_USB_DOEPMSK_NAKMSK_MASK 0x2000 +#define GC_USB_DOEPMSK_NAKMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_NAKMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_NAKMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_NYETMSK_LSB 0xe +#define GC_USB_DOEPMSK_NYETMSK_MASK 0x4000 +#define GC_USB_DOEPMSK_NYETMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_NYETMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_NYETMSK_OFFSET 0x814 +#define GC_USB_DAINT_INEPINT0_LSB 0x0 +#define GC_USB_DAINT_INEPINT0_MASK 0x1 +#define GC_USB_DAINT_INEPINT0_SIZE 0x1 +#define GC_USB_DAINT_INEPINT0_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT0_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT1_LSB 0x1 +#define GC_USB_DAINT_INEPINT1_MASK 0x2 +#define GC_USB_DAINT_INEPINT1_SIZE 0x1 +#define GC_USB_DAINT_INEPINT1_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT1_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT2_LSB 0x2 +#define GC_USB_DAINT_INEPINT2_MASK 0x4 +#define GC_USB_DAINT_INEPINT2_SIZE 0x1 +#define GC_USB_DAINT_INEPINT2_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT2_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT3_LSB 0x3 +#define GC_USB_DAINT_INEPINT3_MASK 0x8 +#define GC_USB_DAINT_INEPINT3_SIZE 0x1 +#define GC_USB_DAINT_INEPINT3_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT3_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT4_LSB 0x4 +#define GC_USB_DAINT_INEPINT4_MASK 0x10 +#define GC_USB_DAINT_INEPINT4_SIZE 0x1 +#define GC_USB_DAINT_INEPINT4_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT4_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT5_LSB 0x5 +#define GC_USB_DAINT_INEPINT5_MASK 0x20 +#define GC_USB_DAINT_INEPINT5_SIZE 0x1 +#define GC_USB_DAINT_INEPINT5_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT5_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT6_LSB 0x6 +#define GC_USB_DAINT_INEPINT6_MASK 0x40 +#define GC_USB_DAINT_INEPINT6_SIZE 0x1 +#define GC_USB_DAINT_INEPINT6_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT6_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT7_LSB 0x7 +#define GC_USB_DAINT_INEPINT7_MASK 0x80 +#define GC_USB_DAINT_INEPINT7_SIZE 0x1 +#define GC_USB_DAINT_INEPINT7_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT7_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT8_LSB 0x8 +#define GC_USB_DAINT_INEPINT8_MASK 0x100 +#define GC_USB_DAINT_INEPINT8_SIZE 0x1 +#define GC_USB_DAINT_INEPINT8_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT8_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT9_LSB 0x9 +#define GC_USB_DAINT_INEPINT9_MASK 0x200 +#define GC_USB_DAINT_INEPINT9_SIZE 0x1 +#define GC_USB_DAINT_INEPINT9_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT9_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT10_LSB 0xa +#define GC_USB_DAINT_INEPINT10_MASK 0x400 +#define GC_USB_DAINT_INEPINT10_SIZE 0x1 +#define GC_USB_DAINT_INEPINT10_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT10_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT11_LSB 0xb +#define GC_USB_DAINT_INEPINT11_MASK 0x800 +#define GC_USB_DAINT_INEPINT11_SIZE 0x1 +#define GC_USB_DAINT_INEPINT11_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT11_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT12_LSB 0xc +#define GC_USB_DAINT_INEPINT12_MASK 0x1000 +#define GC_USB_DAINT_INEPINT12_SIZE 0x1 +#define GC_USB_DAINT_INEPINT12_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT12_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT13_LSB 0xd +#define GC_USB_DAINT_INEPINT13_MASK 0x2000 +#define GC_USB_DAINT_INEPINT13_SIZE 0x1 +#define GC_USB_DAINT_INEPINT13_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT13_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT14_LSB 0xe +#define GC_USB_DAINT_INEPINT14_MASK 0x4000 +#define GC_USB_DAINT_INEPINT14_SIZE 0x1 +#define GC_USB_DAINT_INEPINT14_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT14_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT15_LSB 0xf +#define GC_USB_DAINT_INEPINT15_MASK 0x8000 +#define GC_USB_DAINT_INEPINT15_SIZE 0x1 +#define GC_USB_DAINT_INEPINT15_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT15_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT0_LSB 0x10 +#define GC_USB_DAINT_OUTEPINT0_MASK 0x10000 +#define GC_USB_DAINT_OUTEPINT0_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT0_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT0_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT1_LSB 0x11 +#define GC_USB_DAINT_OUTEPINT1_MASK 0x20000 +#define GC_USB_DAINT_OUTEPINT1_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT1_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT1_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT2_LSB 0x12 +#define GC_USB_DAINT_OUTEPINT2_MASK 0x40000 +#define GC_USB_DAINT_OUTEPINT2_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT2_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT2_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT3_LSB 0x13 +#define GC_USB_DAINT_OUTEPINT3_MASK 0x80000 +#define GC_USB_DAINT_OUTEPINT3_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT3_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT3_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT4_LSB 0x14 +#define GC_USB_DAINT_OUTEPINT4_MASK 0x100000 +#define GC_USB_DAINT_OUTEPINT4_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT4_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT4_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT5_LSB 0x15 +#define GC_USB_DAINT_OUTEPINT5_MASK 0x200000 +#define GC_USB_DAINT_OUTEPINT5_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT5_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT5_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT6_LSB 0x16 +#define GC_USB_DAINT_OUTEPINT6_MASK 0x400000 +#define GC_USB_DAINT_OUTEPINT6_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT6_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT6_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT7_LSB 0x17 +#define GC_USB_DAINT_OUTEPINT7_MASK 0x800000 +#define GC_USB_DAINT_OUTEPINT7_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT7_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT7_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT8_LSB 0x18 +#define GC_USB_DAINT_OUTEPINT8_MASK 0x1000000 +#define GC_USB_DAINT_OUTEPINT8_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT8_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT8_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT9_LSB 0x19 +#define GC_USB_DAINT_OUTEPINT9_MASK 0x2000000 +#define GC_USB_DAINT_OUTEPINT9_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT9_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT9_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT10_LSB 0x1a +#define GC_USB_DAINT_OUTEPINT10_MASK 0x4000000 +#define GC_USB_DAINT_OUTEPINT10_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT10_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT10_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT11_LSB 0x1b +#define GC_USB_DAINT_OUTEPINT11_MASK 0x8000000 +#define GC_USB_DAINT_OUTEPINT11_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT11_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT11_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT12_LSB 0x1c +#define GC_USB_DAINT_OUTEPINT12_MASK 0x10000000 +#define GC_USB_DAINT_OUTEPINT12_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT12_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT12_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT13_LSB 0x1d +#define GC_USB_DAINT_OUTEPINT13_MASK 0x20000000 +#define GC_USB_DAINT_OUTEPINT13_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT13_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT13_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT14_LSB 0x1e +#define GC_USB_DAINT_OUTEPINT14_MASK 0x40000000 +#define GC_USB_DAINT_OUTEPINT14_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT14_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT14_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT15_LSB 0x1f +#define GC_USB_DAINT_OUTEPINT15_MASK 0x80000000 +#define GC_USB_DAINT_OUTEPINT15_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT15_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT15_OFFSET 0x818 +#define GC_USB_DAINTMSK_INEPMSK0_LSB 0x0 +#define GC_USB_DAINTMSK_INEPMSK0_MASK 0x1 +#define GC_USB_DAINTMSK_INEPMSK0_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK0_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK0_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK1_LSB 0x1 +#define GC_USB_DAINTMSK_INEPMSK1_MASK 0x2 +#define GC_USB_DAINTMSK_INEPMSK1_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK1_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK1_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK2_LSB 0x2 +#define GC_USB_DAINTMSK_INEPMSK2_MASK 0x4 +#define GC_USB_DAINTMSK_INEPMSK2_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK2_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK2_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK3_LSB 0x3 +#define GC_USB_DAINTMSK_INEPMSK3_MASK 0x8 +#define GC_USB_DAINTMSK_INEPMSK3_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK3_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK3_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK4_LSB 0x4 +#define GC_USB_DAINTMSK_INEPMSK4_MASK 0x10 +#define GC_USB_DAINTMSK_INEPMSK4_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK4_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK4_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK5_LSB 0x5 +#define GC_USB_DAINTMSK_INEPMSK5_MASK 0x20 +#define GC_USB_DAINTMSK_INEPMSK5_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK5_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK5_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK6_LSB 0x6 +#define GC_USB_DAINTMSK_INEPMSK6_MASK 0x40 +#define GC_USB_DAINTMSK_INEPMSK6_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK6_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK6_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK7_LSB 0x7 +#define GC_USB_DAINTMSK_INEPMSK7_MASK 0x80 +#define GC_USB_DAINTMSK_INEPMSK7_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK7_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK7_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK8_LSB 0x8 +#define GC_USB_DAINTMSK_INEPMSK8_MASK 0x100 +#define GC_USB_DAINTMSK_INEPMSK8_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK8_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK8_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK9_LSB 0x9 +#define GC_USB_DAINTMSK_INEPMSK9_MASK 0x200 +#define GC_USB_DAINTMSK_INEPMSK9_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK9_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK9_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK10_LSB 0xa +#define GC_USB_DAINTMSK_INEPMSK10_MASK 0x400 +#define GC_USB_DAINTMSK_INEPMSK10_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK10_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK10_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK11_LSB 0xb +#define GC_USB_DAINTMSK_INEPMSK11_MASK 0x800 +#define GC_USB_DAINTMSK_INEPMSK11_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK11_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK11_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK12_LSB 0xc +#define GC_USB_DAINTMSK_INEPMSK12_MASK 0x1000 +#define GC_USB_DAINTMSK_INEPMSK12_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK12_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK12_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK13_LSB 0xd +#define GC_USB_DAINTMSK_INEPMSK13_MASK 0x2000 +#define GC_USB_DAINTMSK_INEPMSK13_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK13_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK13_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK14_LSB 0xe +#define GC_USB_DAINTMSK_INEPMSK14_MASK 0x4000 +#define GC_USB_DAINTMSK_INEPMSK14_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK14_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK14_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK15_LSB 0xf +#define GC_USB_DAINTMSK_INEPMSK15_MASK 0x8000 +#define GC_USB_DAINTMSK_INEPMSK15_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK15_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK15_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK0_LSB 0x10 +#define GC_USB_DAINTMSK_OUTEPMSK0_MASK 0x10000 +#define GC_USB_DAINTMSK_OUTEPMSK0_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK0_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK0_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK1_LSB 0x11 +#define GC_USB_DAINTMSK_OUTEPMSK1_MASK 0x20000 +#define GC_USB_DAINTMSK_OUTEPMSK1_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK1_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK1_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK2_LSB 0x12 +#define GC_USB_DAINTMSK_OUTEPMSK2_MASK 0x40000 +#define GC_USB_DAINTMSK_OUTEPMSK2_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK2_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK2_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK3_LSB 0x13 +#define GC_USB_DAINTMSK_OUTEPMSK3_MASK 0x80000 +#define GC_USB_DAINTMSK_OUTEPMSK3_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK3_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK3_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK4_LSB 0x14 +#define GC_USB_DAINTMSK_OUTEPMSK4_MASK 0x100000 +#define GC_USB_DAINTMSK_OUTEPMSK4_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK4_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK4_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK5_LSB 0x15 +#define GC_USB_DAINTMSK_OUTEPMSK5_MASK 0x200000 +#define GC_USB_DAINTMSK_OUTEPMSK5_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK5_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK5_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK6_LSB 0x16 +#define GC_USB_DAINTMSK_OUTEPMSK6_MASK 0x400000 +#define GC_USB_DAINTMSK_OUTEPMSK6_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK6_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK6_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK7_LSB 0x17 +#define GC_USB_DAINTMSK_OUTEPMSK7_MASK 0x800000 +#define GC_USB_DAINTMSK_OUTEPMSK7_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK7_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK7_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK8_LSB 0x18 +#define GC_USB_DAINTMSK_OUTEPMSK8_MASK 0x1000000 +#define GC_USB_DAINTMSK_OUTEPMSK8_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK8_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK8_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK9_LSB 0x19 +#define GC_USB_DAINTMSK_OUTEPMSK9_MASK 0x2000000 +#define GC_USB_DAINTMSK_OUTEPMSK9_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK9_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK9_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK10_LSB 0x1a +#define GC_USB_DAINTMSK_OUTEPMSK10_MASK 0x4000000 +#define GC_USB_DAINTMSK_OUTEPMSK10_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK10_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK10_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK11_LSB 0x1b +#define GC_USB_DAINTMSK_OUTEPMSK11_MASK 0x8000000 +#define GC_USB_DAINTMSK_OUTEPMSK11_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK11_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK11_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK12_LSB 0x1c +#define GC_USB_DAINTMSK_OUTEPMSK12_MASK 0x10000000 +#define GC_USB_DAINTMSK_OUTEPMSK12_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK12_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK12_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK13_LSB 0x1d +#define GC_USB_DAINTMSK_OUTEPMSK13_MASK 0x20000000 +#define GC_USB_DAINTMSK_OUTEPMSK13_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK13_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK13_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK14_LSB 0x1e +#define GC_USB_DAINTMSK_OUTEPMSK14_MASK 0x40000000 +#define GC_USB_DAINTMSK_OUTEPMSK14_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK14_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK14_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK15_LSB 0x1f +#define GC_USB_DAINTMSK_OUTEPMSK15_MASK 0x80000000 +#define GC_USB_DAINTMSK_OUTEPMSK15_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK15_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK15_OFFSET 0x81c +#define GC_USB_DVBUSDIS_DVBUSDIS_LSB 0x0 +#define GC_USB_DVBUSDIS_DVBUSDIS_MASK 0xffff +#define GC_USB_DVBUSDIS_DVBUSDIS_SIZE 0x10 +#define GC_USB_DVBUSDIS_DVBUSDIS_DEFAULT 0x0 +#define GC_USB_DVBUSDIS_DVBUSDIS_OFFSET 0x828 +#define GC_USB_DVBUSPULSE_DVBUSPULSE_LSB 0x0 +#define GC_USB_DVBUSPULSE_DVBUSPULSE_MASK 0xfff +#define GC_USB_DVBUSPULSE_DVBUSPULSE_SIZE 0xc +#define GC_USB_DVBUSPULSE_DVBUSPULSE_DEFAULT 0x0 +#define GC_USB_DVBUSPULSE_DVBUSPULSE_OFFSET 0x82c +#define GC_USB_DTHRCTL_NONISOTHREN_LSB 0x0 +#define GC_USB_DTHRCTL_NONISOTHREN_MASK 0x1 +#define GC_USB_DTHRCTL_NONISOTHREN_SIZE 0x1 +#define GC_USB_DTHRCTL_NONISOTHREN_DEFAULT 0x0 +#define GC_USB_DTHRCTL_NONISOTHREN_OFFSET 0x830 +#define GC_USB_DTHRCTL_ISOTHREN_LSB 0x1 +#define GC_USB_DTHRCTL_ISOTHREN_MASK 0x2 +#define GC_USB_DTHRCTL_ISOTHREN_SIZE 0x1 +#define GC_USB_DTHRCTL_ISOTHREN_DEFAULT 0x0 +#define GC_USB_DTHRCTL_ISOTHREN_OFFSET 0x830 +#define GC_USB_DTHRCTL_TXTHRLEN_LSB 0x2 +#define GC_USB_DTHRCTL_TXTHRLEN_MASK 0x7fc +#define GC_USB_DTHRCTL_TXTHRLEN_SIZE 0x9 +#define GC_USB_DTHRCTL_TXTHRLEN_DEFAULT 0x0 +#define GC_USB_DTHRCTL_TXTHRLEN_OFFSET 0x830 +#define GC_USB_DTHRCTL_AHBTHRRATIO_LSB 0xb +#define GC_USB_DTHRCTL_AHBTHRRATIO_MASK 0x1800 +#define GC_USB_DTHRCTL_AHBTHRRATIO_SIZE 0x2 +#define GC_USB_DTHRCTL_AHBTHRRATIO_DEFAULT 0x0 +#define GC_USB_DTHRCTL_AHBTHRRATIO_OFFSET 0x830 +#define GC_USB_DTHRCTL_RXTHREN_LSB 0x10 +#define GC_USB_DTHRCTL_RXTHREN_MASK 0x10000 +#define GC_USB_DTHRCTL_RXTHREN_SIZE 0x1 +#define GC_USB_DTHRCTL_RXTHREN_DEFAULT 0x0 +#define GC_USB_DTHRCTL_RXTHREN_OFFSET 0x830 +#define GC_USB_DTHRCTL_RXTHRLEN_LSB 0x11 +#define GC_USB_DTHRCTL_RXTHRLEN_MASK 0x3fe0000 +#define GC_USB_DTHRCTL_RXTHRLEN_SIZE 0x9 +#define GC_USB_DTHRCTL_RXTHRLEN_DEFAULT 0x0 +#define GC_USB_DTHRCTL_RXTHRLEN_OFFSET 0x830 +#define GC_USB_DTHRCTL_ARBPRKEN_LSB 0x1b +#define GC_USB_DTHRCTL_ARBPRKEN_MASK 0x8000000 +#define GC_USB_DTHRCTL_ARBPRKEN_SIZE 0x1 +#define GC_USB_DTHRCTL_ARBPRKEN_DEFAULT 0x0 +#define GC_USB_DTHRCTL_ARBPRKEN_OFFSET 0x830 +#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_LSB 0x0 +#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_MASK 0xffff +#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_SIZE 0x10 +#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_DEFAULT 0x0 +#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_OFFSET 0x834 +#define GC_USB_DIEPCTL0_MPS_LSB 0x0 +#define GC_USB_DIEPCTL0_MPS_MASK 0x3 +#define GC_USB_DIEPCTL0_MPS_SIZE 0x2 +#define GC_USB_DIEPCTL0_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_MPS_OFFSET 0x900 +#define GC_USB_DIEPCTL0_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL0_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL0_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL0_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_USBACTEP_OFFSET 0x900 +#define GC_USB_DIEPCTL0_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL0_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL0_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL0_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_NAKSTS_OFFSET 0x900 +#define GC_USB_DIEPCTL0_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL0_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL0_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL0_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_EPTYPE_OFFSET 0x900 +#define GC_USB_DIEPCTL0_STALL_LSB 0x15 +#define GC_USB_DIEPCTL0_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL0_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL0_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_STALL_OFFSET 0x900 +#define GC_USB_DIEPCTL0_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL0_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL0_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL0_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_TXFNUM_OFFSET 0x900 +#define GC_USB_DIEPCTL0_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL0_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL0_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL0_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_CNAK_OFFSET 0x900 +#define GC_USB_DIEPCTL0_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL0_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL0_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL0_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_SNAK_OFFSET 0x900 +#define GC_USB_DIEPCTL0_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL0_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL0_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL0_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_EPDIS_OFFSET 0x900 +#define GC_USB_DIEPCTL0_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL0_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL0_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL0_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_EPENA_OFFSET 0x900 +#define GC_USB_DIEPINT0_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT0_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT0_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT0_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT0_XFERCOMPL_OFFSET 0x908 +#define GC_USB_DIEPINT0_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT0_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT0_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT0_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT0_EPDISBLD_OFFSET 0x908 +#define GC_USB_DIEPINT0_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT0_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT0_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT0_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT0_AHBERR_OFFSET 0x908 +#define GC_USB_DIEPINT0_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT0_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT0_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT0_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT0_TIMEOUT_OFFSET 0x908 +#define GC_USB_DIEPINT0_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT0_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT0_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT0_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT0_INTKNTXFEMP_OFFSET 0x908 +#define GC_USB_DIEPINT0_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT0_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT0_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT0_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT0_INTKNEPMIS_OFFSET 0x908 +#define GC_USB_DIEPINT0_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT0_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT0_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT0_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT0_INEPNAKEFF_OFFSET 0x908 +#define GC_USB_DIEPINT0_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT0_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT0_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT0_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT0_TXFEMP_OFFSET 0x908 +#define GC_USB_DIEPINT0_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT0_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT0_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT0_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT0_TXFIFOUNDRN_OFFSET 0x908 +#define GC_USB_DIEPINT0_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT0_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT0_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT0_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT0_BNAINTR_OFFSET 0x908 +#define GC_USB_DIEPINT0_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT0_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT0_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT0_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT0_PKTDRPSTS_OFFSET 0x908 +#define GC_USB_DIEPINT0_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT0_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT0_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT0_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT0_BBLEERR_OFFSET 0x908 +#define GC_USB_DIEPINT0_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT0_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT0_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT0_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT0_NAKINTRPT_OFFSET 0x908 +#define GC_USB_DIEPINT0_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT0_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT0_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT0_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT0_NYETINTRPT_OFFSET 0x908 +#define GC_USB_DIEPTSIZ0_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ0_XFERSIZE_MASK 0x7f +#define GC_USB_DIEPTSIZ0_XFERSIZE_SIZE 0x7 +#define GC_USB_DIEPTSIZ0_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ0_XFERSIZE_OFFSET 0x910 +#define GC_USB_DIEPTSIZ0_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ0_PKTCNT_MASK 0x180000 +#define GC_USB_DIEPTSIZ0_PKTCNT_SIZE 0x2 +#define GC_USB_DIEPTSIZ0_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ0_PKTCNT_OFFSET 0x910 +#define GC_USB_DIEPDMA0_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA0_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA0_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA0_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA0_DMAADDR_OFFSET 0x914 +#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_OFFSET 0x918 +#define GC_USB_DIEPDMAB0_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB0_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB0_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB0_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB0_DMABUFFERADDR_OFFSET 0x91c +#define GC_USB_DIEPCTL1_MPS_LSB 0x0 +#define GC_USB_DIEPCTL1_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL1_MPS_SIZE 0xb +#define GC_USB_DIEPCTL1_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_MPS_OFFSET 0x920 +#define GC_USB_DIEPCTL1_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL1_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL1_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL1_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_USBACTEP_OFFSET 0x920 +#define GC_USB_DIEPCTL1_DPID_LSB 0x10 +#define GC_USB_DIEPCTL1_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL1_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL1_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_DPID_OFFSET 0x920 +#define GC_USB_DIEPCTL1_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL1_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL1_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL1_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_NAKSTS_OFFSET 0x920 +#define GC_USB_DIEPCTL1_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL1_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL1_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL1_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_EPTYPE_OFFSET 0x920 +#define GC_USB_DIEPCTL1_STALL_LSB 0x15 +#define GC_USB_DIEPCTL1_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL1_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL1_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_STALL_OFFSET 0x920 +#define GC_USB_DIEPCTL1_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL1_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL1_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL1_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_TXFNUM_OFFSET 0x920 +#define GC_USB_DIEPCTL1_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL1_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL1_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL1_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_CNAK_OFFSET 0x920 +#define GC_USB_DIEPCTL1_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL1_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL1_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL1_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_SNAK_OFFSET 0x920 +#define GC_USB_DIEPCTL1_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL1_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL1_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL1_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_SETD0PID_OFFSET 0x920 +#define GC_USB_DIEPCTL1_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL1_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL1_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL1_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_SETD1PID_OFFSET 0x920 +#define GC_USB_DIEPCTL1_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL1_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL1_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL1_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_EPDIS_OFFSET 0x920 +#define GC_USB_DIEPCTL1_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL1_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL1_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL1_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_EPENA_OFFSET 0x920 +#define GC_USB_DIEPINT1_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT1_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT1_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT1_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT1_XFERCOMPL_OFFSET 0x928 +#define GC_USB_DIEPINT1_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT1_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT1_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT1_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT1_EPDISBLD_OFFSET 0x928 +#define GC_USB_DIEPINT1_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT1_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT1_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT1_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT1_AHBERR_OFFSET 0x928 +#define GC_USB_DIEPINT1_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT1_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT1_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT1_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT1_TIMEOUT_OFFSET 0x928 +#define GC_USB_DIEPINT1_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT1_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT1_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT1_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT1_INTKNTXFEMP_OFFSET 0x928 +#define GC_USB_DIEPINT1_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT1_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT1_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT1_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT1_INTKNEPMIS_OFFSET 0x928 +#define GC_USB_DIEPINT1_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT1_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT1_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT1_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT1_INEPNAKEFF_OFFSET 0x928 +#define GC_USB_DIEPINT1_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT1_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT1_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT1_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT1_TXFEMP_OFFSET 0x928 +#define GC_USB_DIEPINT1_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT1_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT1_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT1_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT1_TXFIFOUNDRN_OFFSET 0x928 +#define GC_USB_DIEPINT1_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT1_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT1_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT1_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT1_BNAINTR_OFFSET 0x928 +#define GC_USB_DIEPINT1_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT1_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT1_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT1_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT1_PKTDRPSTS_OFFSET 0x928 +#define GC_USB_DIEPINT1_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT1_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT1_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT1_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT1_BBLEERR_OFFSET 0x928 +#define GC_USB_DIEPINT1_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT1_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT1_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT1_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT1_NAKINTRPT_OFFSET 0x928 +#define GC_USB_DIEPINT1_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT1_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT1_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT1_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT1_NYETINTRPT_OFFSET 0x928 +#define GC_USB_DIEPTSIZ1_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ1_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ1_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ1_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ1_XFERSIZE_OFFSET 0x930 +#define GC_USB_DIEPTSIZ1_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ1_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ1_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ1_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ1_PKTCNT_OFFSET 0x930 +#define GC_USB_DIEPTSIZ1_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ1_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ1_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ1_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ1_MC_OFFSET 0x930 +#define GC_USB_DIEPDMA1_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA1_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA1_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA1_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA1_DMAADDR_OFFSET 0x934 +#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_OFFSET 0x938 +#define GC_USB_DIEPDMAB1_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB1_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB1_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB1_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB1_DMABUFFERADDR_OFFSET 0x93c +#define GC_USB_DIEPCTL2_MPS_LSB 0x0 +#define GC_USB_DIEPCTL2_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL2_MPS_SIZE 0xb +#define GC_USB_DIEPCTL2_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_MPS_OFFSET 0x940 +#define GC_USB_DIEPCTL2_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL2_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL2_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL2_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_USBACTEP_OFFSET 0x940 +#define GC_USB_DIEPCTL2_DPID_LSB 0x10 +#define GC_USB_DIEPCTL2_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL2_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL2_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_DPID_OFFSET 0x940 +#define GC_USB_DIEPCTL2_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL2_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL2_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL2_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_NAKSTS_OFFSET 0x940 +#define GC_USB_DIEPCTL2_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL2_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL2_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL2_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_EPTYPE_OFFSET 0x940 +#define GC_USB_DIEPCTL2_STALL_LSB 0x15 +#define GC_USB_DIEPCTL2_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL2_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL2_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_STALL_OFFSET 0x940 +#define GC_USB_DIEPCTL2_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL2_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL2_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL2_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_TXFNUM_OFFSET 0x940 +#define GC_USB_DIEPCTL2_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL2_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL2_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL2_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_CNAK_OFFSET 0x940 +#define GC_USB_DIEPCTL2_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL2_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL2_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL2_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_SNAK_OFFSET 0x940 +#define GC_USB_DIEPCTL2_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL2_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL2_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL2_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_SETD0PID_OFFSET 0x940 +#define GC_USB_DIEPCTL2_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL2_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL2_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL2_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_SETD1PID_OFFSET 0x940 +#define GC_USB_DIEPCTL2_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL2_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL2_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL2_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_EPDIS_OFFSET 0x940 +#define GC_USB_DIEPCTL2_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL2_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL2_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL2_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_EPENA_OFFSET 0x940 +#define GC_USB_DIEPINT2_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT2_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT2_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT2_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT2_XFERCOMPL_OFFSET 0x948 +#define GC_USB_DIEPINT2_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT2_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT2_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT2_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT2_EPDISBLD_OFFSET 0x948 +#define GC_USB_DIEPINT2_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT2_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT2_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT2_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT2_AHBERR_OFFSET 0x948 +#define GC_USB_DIEPINT2_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT2_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT2_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT2_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT2_TIMEOUT_OFFSET 0x948 +#define GC_USB_DIEPINT2_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT2_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT2_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT2_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT2_INTKNTXFEMP_OFFSET 0x948 +#define GC_USB_DIEPINT2_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT2_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT2_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT2_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT2_INTKNEPMIS_OFFSET 0x948 +#define GC_USB_DIEPINT2_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT2_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT2_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT2_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT2_INEPNAKEFF_OFFSET 0x948 +#define GC_USB_DIEPINT2_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT2_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT2_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT2_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT2_TXFEMP_OFFSET 0x948 +#define GC_USB_DIEPINT2_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT2_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT2_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT2_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT2_TXFIFOUNDRN_OFFSET 0x948 +#define GC_USB_DIEPINT2_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT2_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT2_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT2_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT2_BNAINTR_OFFSET 0x948 +#define GC_USB_DIEPINT2_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT2_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT2_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT2_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT2_PKTDRPSTS_OFFSET 0x948 +#define GC_USB_DIEPINT2_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT2_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT2_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT2_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT2_BBLEERR_OFFSET 0x948 +#define GC_USB_DIEPINT2_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT2_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT2_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT2_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT2_NAKINTRPT_OFFSET 0x948 +#define GC_USB_DIEPINT2_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT2_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT2_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT2_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT2_NYETINTRPT_OFFSET 0x948 +#define GC_USB_DIEPTSIZ2_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ2_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ2_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ2_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ2_XFERSIZE_OFFSET 0x950 +#define GC_USB_DIEPTSIZ2_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ2_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ2_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ2_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ2_PKTCNT_OFFSET 0x950 +#define GC_USB_DIEPTSIZ2_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ2_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ2_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ2_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ2_MC_OFFSET 0x950 +#define GC_USB_DIEPDMA2_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA2_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA2_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA2_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA2_DMAADDR_OFFSET 0x954 +#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_OFFSET 0x958 +#define GC_USB_DIEPDMAB2_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB2_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB2_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB2_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB2_DMABUFFERADDR_OFFSET 0x95c +#define GC_USB_DIEPCTL3_MPS_LSB 0x0 +#define GC_USB_DIEPCTL3_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL3_MPS_SIZE 0xb +#define GC_USB_DIEPCTL3_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_MPS_OFFSET 0x960 +#define GC_USB_DIEPCTL3_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL3_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL3_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL3_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_USBACTEP_OFFSET 0x960 +#define GC_USB_DIEPCTL3_DPID_LSB 0x10 +#define GC_USB_DIEPCTL3_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL3_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL3_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_DPID_OFFSET 0x960 +#define GC_USB_DIEPCTL3_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL3_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL3_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL3_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_NAKSTS_OFFSET 0x960 +#define GC_USB_DIEPCTL3_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL3_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL3_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL3_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_EPTYPE_OFFSET 0x960 +#define GC_USB_DIEPCTL3_STALL_LSB 0x15 +#define GC_USB_DIEPCTL3_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL3_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL3_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_STALL_OFFSET 0x960 +#define GC_USB_DIEPCTL3_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL3_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL3_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL3_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_TXFNUM_OFFSET 0x960 +#define GC_USB_DIEPCTL3_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL3_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL3_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL3_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_CNAK_OFFSET 0x960 +#define GC_USB_DIEPCTL3_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL3_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL3_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL3_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_SNAK_OFFSET 0x960 +#define GC_USB_DIEPCTL3_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL3_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL3_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL3_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_SETD0PID_OFFSET 0x960 +#define GC_USB_DIEPCTL3_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL3_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL3_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL3_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_SETD1PID_OFFSET 0x960 +#define GC_USB_DIEPCTL3_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL3_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL3_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL3_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_EPDIS_OFFSET 0x960 +#define GC_USB_DIEPCTL3_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL3_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL3_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL3_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_EPENA_OFFSET 0x960 +#define GC_USB_DIEPINT3_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT3_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT3_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT3_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT3_XFERCOMPL_OFFSET 0x968 +#define GC_USB_DIEPINT3_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT3_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT3_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT3_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT3_EPDISBLD_OFFSET 0x968 +#define GC_USB_DIEPINT3_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT3_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT3_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT3_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT3_AHBERR_OFFSET 0x968 +#define GC_USB_DIEPINT3_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT3_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT3_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT3_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT3_TIMEOUT_OFFSET 0x968 +#define GC_USB_DIEPINT3_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT3_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT3_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT3_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT3_INTKNTXFEMP_OFFSET 0x968 +#define GC_USB_DIEPINT3_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT3_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT3_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT3_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT3_INTKNEPMIS_OFFSET 0x968 +#define GC_USB_DIEPINT3_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT3_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT3_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT3_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT3_INEPNAKEFF_OFFSET 0x968 +#define GC_USB_DIEPINT3_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT3_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT3_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT3_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT3_TXFEMP_OFFSET 0x968 +#define GC_USB_DIEPINT3_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT3_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT3_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT3_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT3_TXFIFOUNDRN_OFFSET 0x968 +#define GC_USB_DIEPINT3_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT3_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT3_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT3_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT3_BNAINTR_OFFSET 0x968 +#define GC_USB_DIEPINT3_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT3_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT3_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT3_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT3_PKTDRPSTS_OFFSET 0x968 +#define GC_USB_DIEPINT3_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT3_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT3_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT3_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT3_BBLEERR_OFFSET 0x968 +#define GC_USB_DIEPINT3_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT3_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT3_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT3_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT3_NAKINTRPT_OFFSET 0x968 +#define GC_USB_DIEPINT3_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT3_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT3_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT3_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT3_NYETINTRPT_OFFSET 0x968 +#define GC_USB_DIEPTSIZ3_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ3_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ3_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ3_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ3_XFERSIZE_OFFSET 0x970 +#define GC_USB_DIEPTSIZ3_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ3_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ3_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ3_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ3_PKTCNT_OFFSET 0x970 +#define GC_USB_DIEPTSIZ3_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ3_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ3_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ3_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ3_MC_OFFSET 0x970 +#define GC_USB_DIEPDMA3_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA3_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA3_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA3_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA3_DMAADDR_OFFSET 0x974 +#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_OFFSET 0x978 +#define GC_USB_DIEPDMAB3_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB3_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB3_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB3_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB3_DMABUFFERADDR_OFFSET 0x97c +#define GC_USB_DIEPCTL4_MPS_LSB 0x0 +#define GC_USB_DIEPCTL4_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL4_MPS_SIZE 0xb +#define GC_USB_DIEPCTL4_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_MPS_OFFSET 0x980 +#define GC_USB_DIEPCTL4_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL4_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL4_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL4_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_USBACTEP_OFFSET 0x980 +#define GC_USB_DIEPCTL4_DPID_LSB 0x10 +#define GC_USB_DIEPCTL4_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL4_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL4_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_DPID_OFFSET 0x980 +#define GC_USB_DIEPCTL4_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL4_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL4_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL4_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_NAKSTS_OFFSET 0x980 +#define GC_USB_DIEPCTL4_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL4_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL4_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL4_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_EPTYPE_OFFSET 0x980 +#define GC_USB_DIEPCTL4_STALL_LSB 0x15 +#define GC_USB_DIEPCTL4_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL4_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL4_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_STALL_OFFSET 0x980 +#define GC_USB_DIEPCTL4_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL4_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL4_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL4_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_TXFNUM_OFFSET 0x980 +#define GC_USB_DIEPCTL4_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL4_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL4_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL4_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_CNAK_OFFSET 0x980 +#define GC_USB_DIEPCTL4_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL4_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL4_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL4_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_SNAK_OFFSET 0x980 +#define GC_USB_DIEPCTL4_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL4_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL4_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL4_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_SETD0PID_OFFSET 0x980 +#define GC_USB_DIEPCTL4_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL4_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL4_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL4_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_SETD1PID_OFFSET 0x980 +#define GC_USB_DIEPCTL4_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL4_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL4_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL4_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_EPDIS_OFFSET 0x980 +#define GC_USB_DIEPCTL4_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL4_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL4_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL4_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_EPENA_OFFSET 0x980 +#define GC_USB_DIEPINT4_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT4_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT4_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT4_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT4_XFERCOMPL_OFFSET 0x988 +#define GC_USB_DIEPINT4_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT4_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT4_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT4_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT4_EPDISBLD_OFFSET 0x988 +#define GC_USB_DIEPINT4_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT4_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT4_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT4_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT4_AHBERR_OFFSET 0x988 +#define GC_USB_DIEPINT4_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT4_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT4_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT4_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT4_TIMEOUT_OFFSET 0x988 +#define GC_USB_DIEPINT4_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT4_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT4_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT4_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT4_INTKNTXFEMP_OFFSET 0x988 +#define GC_USB_DIEPINT4_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT4_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT4_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT4_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT4_INTKNEPMIS_OFFSET 0x988 +#define GC_USB_DIEPINT4_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT4_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT4_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT4_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT4_INEPNAKEFF_OFFSET 0x988 +#define GC_USB_DIEPINT4_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT4_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT4_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT4_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT4_TXFEMP_OFFSET 0x988 +#define GC_USB_DIEPINT4_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT4_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT4_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT4_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT4_TXFIFOUNDRN_OFFSET 0x988 +#define GC_USB_DIEPINT4_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT4_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT4_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT4_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT4_BNAINTR_OFFSET 0x988 +#define GC_USB_DIEPINT4_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT4_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT4_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT4_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT4_PKTDRPSTS_OFFSET 0x988 +#define GC_USB_DIEPINT4_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT4_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT4_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT4_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT4_BBLEERR_OFFSET 0x988 +#define GC_USB_DIEPINT4_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT4_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT4_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT4_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT4_NAKINTRPT_OFFSET 0x988 +#define GC_USB_DIEPINT4_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT4_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT4_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT4_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT4_NYETINTRPT_OFFSET 0x988 +#define GC_USB_DIEPTSIZ4_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ4_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ4_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ4_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ4_XFERSIZE_OFFSET 0x990 +#define GC_USB_DIEPTSIZ4_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ4_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ4_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ4_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ4_PKTCNT_OFFSET 0x990 +#define GC_USB_DIEPTSIZ4_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ4_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ4_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ4_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ4_MC_OFFSET 0x990 +#define GC_USB_DIEPDMA4_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA4_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA4_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA4_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA4_DMAADDR_OFFSET 0x994 +#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_OFFSET 0x998 +#define GC_USB_DIEPDMAB4_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB4_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB4_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB4_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB4_DMABUFFERADDR_OFFSET 0x99c +#define GC_USB_DIEPCTL5_MPS_LSB 0x0 +#define GC_USB_DIEPCTL5_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL5_MPS_SIZE 0xb +#define GC_USB_DIEPCTL5_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_MPS_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL5_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL5_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL5_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_USBACTEP_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_DPID_LSB 0x10 +#define GC_USB_DIEPCTL5_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL5_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL5_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_DPID_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL5_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL5_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL5_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_NAKSTS_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL5_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL5_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL5_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_EPTYPE_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_STALL_LSB 0x15 +#define GC_USB_DIEPCTL5_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL5_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL5_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_STALL_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL5_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL5_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL5_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_TXFNUM_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL5_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL5_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL5_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_CNAK_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL5_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL5_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL5_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_SNAK_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL5_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL5_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL5_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_SETD0PID_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL5_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL5_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL5_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_SETD1PID_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL5_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL5_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL5_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_EPDIS_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL5_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL5_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL5_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_EPENA_OFFSET 0x9a0 +#define GC_USB_DIEPINT5_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT5_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT5_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT5_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT5_XFERCOMPL_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT5_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT5_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT5_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT5_EPDISBLD_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT5_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT5_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT5_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT5_AHBERR_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT5_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT5_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT5_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT5_TIMEOUT_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT5_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT5_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT5_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT5_INTKNTXFEMP_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT5_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT5_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT5_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT5_INTKNEPMIS_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT5_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT5_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT5_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT5_INEPNAKEFF_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT5_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT5_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT5_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT5_TXFEMP_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT5_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT5_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT5_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT5_TXFIFOUNDRN_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT5_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT5_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT5_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT5_BNAINTR_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT5_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT5_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT5_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT5_PKTDRPSTS_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT5_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT5_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT5_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT5_BBLEERR_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT5_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT5_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT5_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT5_NAKINTRPT_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT5_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT5_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT5_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT5_NYETINTRPT_OFFSET 0x9a8 +#define GC_USB_DIEPTSIZ5_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ5_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ5_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ5_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ5_XFERSIZE_OFFSET 0x9b0 +#define GC_USB_DIEPTSIZ5_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ5_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ5_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ5_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ5_PKTCNT_OFFSET 0x9b0 +#define GC_USB_DIEPTSIZ5_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ5_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ5_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ5_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ5_MC_OFFSET 0x9b0 +#define GC_USB_DIEPDMA5_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA5_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA5_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA5_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA5_DMAADDR_OFFSET 0x9b4 +#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_OFFSET 0x9b8 +#define GC_USB_DIEPDMAB5_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB5_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB5_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB5_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB5_DMABUFFERADDR_OFFSET 0x9bc +#define GC_USB_DIEPCTL6_MPS_LSB 0x0 +#define GC_USB_DIEPCTL6_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL6_MPS_SIZE 0xb +#define GC_USB_DIEPCTL6_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_MPS_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL6_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL6_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL6_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_USBACTEP_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_DPID_LSB 0x10 +#define GC_USB_DIEPCTL6_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL6_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL6_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_DPID_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL6_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL6_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL6_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_NAKSTS_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL6_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL6_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL6_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_EPTYPE_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_STALL_LSB 0x15 +#define GC_USB_DIEPCTL6_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL6_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL6_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_STALL_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL6_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL6_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL6_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_TXFNUM_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL6_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL6_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL6_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_CNAK_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL6_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL6_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL6_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_SNAK_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL6_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL6_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL6_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_SETD0PID_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL6_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL6_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL6_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_SETD1PID_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL6_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL6_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL6_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_EPDIS_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL6_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL6_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL6_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_EPENA_OFFSET 0x9c0 +#define GC_USB_DIEPINT6_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT6_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT6_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT6_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT6_XFERCOMPL_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT6_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT6_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT6_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT6_EPDISBLD_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT6_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT6_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT6_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT6_AHBERR_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT6_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT6_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT6_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT6_TIMEOUT_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT6_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT6_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT6_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT6_INTKNTXFEMP_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT6_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT6_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT6_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT6_INTKNEPMIS_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT6_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT6_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT6_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT6_INEPNAKEFF_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT6_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT6_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT6_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT6_TXFEMP_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT6_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT6_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT6_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT6_TXFIFOUNDRN_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT6_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT6_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT6_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT6_BNAINTR_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT6_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT6_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT6_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT6_PKTDRPSTS_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT6_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT6_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT6_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT6_BBLEERR_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT6_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT6_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT6_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT6_NAKINTRPT_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT6_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT6_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT6_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT6_NYETINTRPT_OFFSET 0x9c8 +#define GC_USB_DIEPTSIZ6_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ6_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ6_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ6_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ6_XFERSIZE_OFFSET 0x9d0 +#define GC_USB_DIEPTSIZ6_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ6_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ6_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ6_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ6_PKTCNT_OFFSET 0x9d0 +#define GC_USB_DIEPTSIZ6_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ6_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ6_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ6_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ6_MC_OFFSET 0x9d0 +#define GC_USB_DIEPDMA6_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA6_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA6_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA6_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA6_DMAADDR_OFFSET 0x9d4 +#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_OFFSET 0x9d8 +#define GC_USB_DIEPDMAB6_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB6_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB6_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB6_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB6_DMABUFFERADDR_OFFSET 0x9dc +#define GC_USB_DIEPCTL7_MPS_LSB 0x0 +#define GC_USB_DIEPCTL7_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL7_MPS_SIZE 0xb +#define GC_USB_DIEPCTL7_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_MPS_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL7_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL7_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL7_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_USBACTEP_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_DPID_LSB 0x10 +#define GC_USB_DIEPCTL7_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL7_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL7_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_DPID_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL7_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL7_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL7_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_NAKSTS_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL7_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL7_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL7_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_EPTYPE_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_STALL_LSB 0x15 +#define GC_USB_DIEPCTL7_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL7_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL7_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_STALL_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL7_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL7_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL7_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_TXFNUM_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL7_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL7_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL7_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_CNAK_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL7_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL7_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL7_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_SNAK_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL7_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL7_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL7_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_SETD0PID_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL7_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL7_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL7_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_SETD1PID_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL7_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL7_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL7_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_EPDIS_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL7_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL7_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL7_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_EPENA_OFFSET 0x9e0 +#define GC_USB_DIEPINT7_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT7_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT7_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT7_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT7_XFERCOMPL_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT7_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT7_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT7_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT7_EPDISBLD_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT7_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT7_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT7_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT7_AHBERR_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT7_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT7_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT7_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT7_TIMEOUT_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT7_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT7_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT7_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT7_INTKNTXFEMP_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT7_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT7_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT7_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT7_INTKNEPMIS_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT7_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT7_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT7_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT7_INEPNAKEFF_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT7_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT7_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT7_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT7_TXFEMP_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT7_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT7_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT7_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT7_TXFIFOUNDRN_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT7_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT7_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT7_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT7_BNAINTR_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT7_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT7_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT7_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT7_PKTDRPSTS_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT7_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT7_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT7_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT7_BBLEERR_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT7_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT7_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT7_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT7_NAKINTRPT_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT7_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT7_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT7_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT7_NYETINTRPT_OFFSET 0x9e8 +#define GC_USB_DIEPTSIZ7_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ7_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ7_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ7_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ7_XFERSIZE_OFFSET 0x9f0 +#define GC_USB_DIEPTSIZ7_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ7_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ7_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ7_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ7_PKTCNT_OFFSET 0x9f0 +#define GC_USB_DIEPTSIZ7_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ7_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ7_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ7_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ7_MC_OFFSET 0x9f0 +#define GC_USB_DIEPDMA7_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA7_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA7_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA7_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA7_DMAADDR_OFFSET 0x9f4 +#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_OFFSET 0x9f8 +#define GC_USB_DIEPDMAB7_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB7_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB7_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB7_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB7_DMABUFFERADDR_OFFSET 0x9fc +#define GC_USB_DIEPCTL8_MPS_LSB 0x0 +#define GC_USB_DIEPCTL8_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL8_MPS_SIZE 0xb +#define GC_USB_DIEPCTL8_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_MPS_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL8_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL8_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL8_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_USBACTEP_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_DPID_LSB 0x10 +#define GC_USB_DIEPCTL8_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL8_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL8_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_DPID_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL8_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL8_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL8_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_NAKSTS_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL8_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL8_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL8_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_EPTYPE_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_STALL_LSB 0x15 +#define GC_USB_DIEPCTL8_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL8_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL8_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_STALL_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL8_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL8_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL8_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_TXFNUM_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL8_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL8_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL8_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_CNAK_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL8_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL8_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL8_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_SNAK_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL8_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL8_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL8_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_SETD0PID_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL8_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL8_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL8_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_SETD1PID_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL8_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL8_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL8_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_EPDIS_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL8_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL8_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL8_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_EPENA_OFFSET 0xa00 +#define GC_USB_DIEPINT8_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT8_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT8_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT8_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT8_XFERCOMPL_OFFSET 0xa08 +#define GC_USB_DIEPINT8_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT8_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT8_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT8_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT8_EPDISBLD_OFFSET 0xa08 +#define GC_USB_DIEPINT8_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT8_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT8_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT8_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT8_AHBERR_OFFSET 0xa08 +#define GC_USB_DIEPINT8_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT8_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT8_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT8_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT8_TIMEOUT_OFFSET 0xa08 +#define GC_USB_DIEPINT8_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT8_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT8_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT8_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT8_INTKNTXFEMP_OFFSET 0xa08 +#define GC_USB_DIEPINT8_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT8_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT8_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT8_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT8_INTKNEPMIS_OFFSET 0xa08 +#define GC_USB_DIEPINT8_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT8_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT8_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT8_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT8_INEPNAKEFF_OFFSET 0xa08 +#define GC_USB_DIEPINT8_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT8_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT8_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT8_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT8_TXFEMP_OFFSET 0xa08 +#define GC_USB_DIEPINT8_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT8_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT8_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT8_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT8_TXFIFOUNDRN_OFFSET 0xa08 +#define GC_USB_DIEPINT8_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT8_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT8_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT8_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT8_BNAINTR_OFFSET 0xa08 +#define GC_USB_DIEPINT8_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT8_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT8_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT8_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT8_PKTDRPSTS_OFFSET 0xa08 +#define GC_USB_DIEPINT8_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT8_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT8_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT8_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT8_BBLEERR_OFFSET 0xa08 +#define GC_USB_DIEPINT8_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT8_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT8_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT8_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT8_NAKINTRPT_OFFSET 0xa08 +#define GC_USB_DIEPINT8_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT8_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT8_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT8_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT8_NYETINTRPT_OFFSET 0xa08 +#define GC_USB_DIEPTSIZ8_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ8_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ8_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ8_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ8_XFERSIZE_OFFSET 0xa10 +#define GC_USB_DIEPTSIZ8_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ8_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ8_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ8_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ8_PKTCNT_OFFSET 0xa10 +#define GC_USB_DIEPTSIZ8_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ8_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ8_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ8_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ8_MC_OFFSET 0xa10 +#define GC_USB_DIEPDMA8_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA8_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA8_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA8_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA8_DMAADDR_OFFSET 0xa14 +#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_OFFSET 0xa18 +#define GC_USB_DIEPDMAB8_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB8_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB8_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB8_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB8_DMABUFFERADDR_OFFSET 0xa1c +#define GC_USB_DIEPCTL9_MPS_LSB 0x0 +#define GC_USB_DIEPCTL9_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL9_MPS_SIZE 0xb +#define GC_USB_DIEPCTL9_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_MPS_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL9_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL9_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL9_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_USBACTEP_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_DPID_LSB 0x10 +#define GC_USB_DIEPCTL9_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL9_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL9_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_DPID_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL9_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL9_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL9_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_NAKSTS_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL9_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL9_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL9_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_EPTYPE_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_STALL_LSB 0x15 +#define GC_USB_DIEPCTL9_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL9_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL9_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_STALL_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL9_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL9_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL9_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_TXFNUM_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL9_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL9_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL9_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_CNAK_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL9_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL9_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL9_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_SNAK_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL9_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL9_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL9_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_SETD0PID_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL9_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL9_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL9_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_SETD1PID_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL9_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL9_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL9_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_EPDIS_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL9_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL9_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL9_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_EPENA_OFFSET 0xa20 +#define GC_USB_DIEPINT9_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT9_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT9_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT9_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT9_XFERCOMPL_OFFSET 0xa28 +#define GC_USB_DIEPINT9_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT9_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT9_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT9_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT9_EPDISBLD_OFFSET 0xa28 +#define GC_USB_DIEPINT9_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT9_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT9_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT9_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT9_AHBERR_OFFSET 0xa28 +#define GC_USB_DIEPINT9_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT9_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT9_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT9_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT9_TIMEOUT_OFFSET 0xa28 +#define GC_USB_DIEPINT9_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT9_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT9_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT9_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT9_INTKNTXFEMP_OFFSET 0xa28 +#define GC_USB_DIEPINT9_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT9_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT9_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT9_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT9_INTKNEPMIS_OFFSET 0xa28 +#define GC_USB_DIEPINT9_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT9_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT9_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT9_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT9_INEPNAKEFF_OFFSET 0xa28 +#define GC_USB_DIEPINT9_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT9_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT9_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT9_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT9_TXFEMP_OFFSET 0xa28 +#define GC_USB_DIEPINT9_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT9_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT9_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT9_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT9_TXFIFOUNDRN_OFFSET 0xa28 +#define GC_USB_DIEPINT9_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT9_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT9_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT9_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT9_BNAINTR_OFFSET 0xa28 +#define GC_USB_DIEPINT9_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT9_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT9_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT9_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT9_PKTDRPSTS_OFFSET 0xa28 +#define GC_USB_DIEPINT9_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT9_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT9_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT9_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT9_BBLEERR_OFFSET 0xa28 +#define GC_USB_DIEPINT9_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT9_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT9_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT9_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT9_NAKINTRPT_OFFSET 0xa28 +#define GC_USB_DIEPINT9_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT9_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT9_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT9_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT9_NYETINTRPT_OFFSET 0xa28 +#define GC_USB_DIEPTSIZ9_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ9_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ9_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ9_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ9_XFERSIZE_OFFSET 0xa30 +#define GC_USB_DIEPTSIZ9_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ9_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ9_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ9_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ9_PKTCNT_OFFSET 0xa30 +#define GC_USB_DIEPTSIZ9_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ9_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ9_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ9_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ9_MC_OFFSET 0xa30 +#define GC_USB_DIEPDMA9_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA9_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA9_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA9_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA9_DMAADDR_OFFSET 0xa34 +#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_OFFSET 0xa38 +#define GC_USB_DIEPDMAB9_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB9_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB9_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB9_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB9_DMABUFFERADDR_OFFSET 0xa3c +#define GC_USB_DIEPCTL10_MPS_LSB 0x0 +#define GC_USB_DIEPCTL10_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL10_MPS_SIZE 0xb +#define GC_USB_DIEPCTL10_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_MPS_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL10_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL10_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL10_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_USBACTEP_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_DPID_LSB 0x10 +#define GC_USB_DIEPCTL10_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL10_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL10_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_DPID_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL10_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL10_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL10_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_NAKSTS_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL10_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL10_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL10_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_EPTYPE_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_STALL_LSB 0x15 +#define GC_USB_DIEPCTL10_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL10_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL10_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_STALL_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL10_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL10_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL10_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_TXFNUM_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL10_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL10_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL10_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_CNAK_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL10_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL10_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL10_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_SNAK_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL10_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL10_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL10_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_SETD0PID_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL10_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL10_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL10_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_SETD1PID_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL10_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL10_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL10_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_EPDIS_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL10_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL10_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL10_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_EPENA_OFFSET 0xa40 +#define GC_USB_DIEPINT10_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT10_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT10_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT10_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT10_XFERCOMPL_OFFSET 0xa48 +#define GC_USB_DIEPINT10_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT10_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT10_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT10_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT10_EPDISBLD_OFFSET 0xa48 +#define GC_USB_DIEPINT10_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT10_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT10_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT10_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT10_AHBERR_OFFSET 0xa48 +#define GC_USB_DIEPINT10_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT10_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT10_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT10_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT10_TIMEOUT_OFFSET 0xa48 +#define GC_USB_DIEPINT10_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT10_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT10_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT10_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT10_INTKNTXFEMP_OFFSET 0xa48 +#define GC_USB_DIEPINT10_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT10_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT10_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT10_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT10_INTKNEPMIS_OFFSET 0xa48 +#define GC_USB_DIEPINT10_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT10_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT10_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT10_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT10_INEPNAKEFF_OFFSET 0xa48 +#define GC_USB_DIEPINT10_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT10_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT10_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT10_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT10_TXFEMP_OFFSET 0xa48 +#define GC_USB_DIEPINT10_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT10_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT10_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT10_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT10_TXFIFOUNDRN_OFFSET 0xa48 +#define GC_USB_DIEPINT10_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT10_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT10_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT10_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT10_BNAINTR_OFFSET 0xa48 +#define GC_USB_DIEPINT10_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT10_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT10_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT10_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT10_PKTDRPSTS_OFFSET 0xa48 +#define GC_USB_DIEPINT10_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT10_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT10_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT10_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT10_BBLEERR_OFFSET 0xa48 +#define GC_USB_DIEPINT10_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT10_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT10_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT10_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT10_NAKINTRPT_OFFSET 0xa48 +#define GC_USB_DIEPINT10_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT10_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT10_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT10_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT10_NYETINTRPT_OFFSET 0xa48 +#define GC_USB_DIEPTSIZ10_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ10_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ10_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ10_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ10_XFERSIZE_OFFSET 0xa50 +#define GC_USB_DIEPTSIZ10_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ10_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ10_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ10_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ10_PKTCNT_OFFSET 0xa50 +#define GC_USB_DIEPTSIZ10_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ10_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ10_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ10_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ10_MC_OFFSET 0xa50 +#define GC_USB_DIEPDMA10_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA10_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA10_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA10_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA10_DMAADDR_OFFSET 0xa54 +#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_SIZE 0x10 #define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_OFFSET 0xa58 -#define GC_USB_DIEPDMAB10_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB10_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB10_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB10_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB10_DMABUFFERADDR_OFFSET 0xa5c -#define GC_USB_DIEPCTL11_MPS_LSB 0x0 -#define GC_USB_DIEPCTL11_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL11_MPS_SIZE 0xb -#define GC_USB_DIEPCTL11_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_MPS_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL11_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL11_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL11_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_USBACTEP_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_DPID_LSB 0x10 -#define GC_USB_DIEPCTL11_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL11_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL11_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_DPID_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL11_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL11_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL11_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_NAKSTS_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL11_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL11_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL11_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_EPTYPE_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_STALL_LSB 0x15 -#define GC_USB_DIEPCTL11_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL11_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL11_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_STALL_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL11_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL11_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL11_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_TXFNUM_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL11_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL11_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL11_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_CNAK_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL11_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL11_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL11_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_SNAK_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL11_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL11_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL11_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_SETD0PID_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL11_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL11_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL11_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_SETD1PID_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL11_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL11_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL11_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_EPDIS_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL11_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL11_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL11_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_EPENA_OFFSET 0xa60 -#define GC_USB_DIEPINT11_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT11_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT11_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT11_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT11_XFERCOMPL_OFFSET 0xa68 -#define GC_USB_DIEPINT11_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT11_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT11_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT11_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT11_EPDISBLD_OFFSET 0xa68 -#define GC_USB_DIEPINT11_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT11_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT11_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT11_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT11_AHBERR_OFFSET 0xa68 -#define GC_USB_DIEPINT11_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT11_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT11_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT11_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT11_TIMEOUT_OFFSET 0xa68 -#define GC_USB_DIEPINT11_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT11_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT11_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT11_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT11_INTKNTXFEMP_OFFSET 0xa68 -#define GC_USB_DIEPINT11_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT11_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT11_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT11_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT11_INTKNEPMIS_OFFSET 0xa68 -#define GC_USB_DIEPINT11_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT11_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT11_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT11_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT11_INEPNAKEFF_OFFSET 0xa68 -#define GC_USB_DIEPINT11_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT11_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT11_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT11_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT11_TXFEMP_OFFSET 0xa68 -#define GC_USB_DIEPINT11_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT11_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT11_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT11_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT11_TXFIFOUNDRN_OFFSET 0xa68 -#define GC_USB_DIEPINT11_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT11_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT11_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT11_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT11_BNAINTR_OFFSET 0xa68 -#define GC_USB_DIEPINT11_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT11_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT11_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT11_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT11_PKTDRPSTS_OFFSET 0xa68 -#define GC_USB_DIEPINT11_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT11_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT11_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT11_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT11_BBLEERR_OFFSET 0xa68 -#define GC_USB_DIEPINT11_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT11_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT11_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT11_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT11_NAKINTRPT_OFFSET 0xa68 -#define GC_USB_DIEPINT11_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT11_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT11_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT11_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT11_NYETINTRPT_OFFSET 0xa68 -#define GC_USB_DIEPTSIZ11_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ11_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ11_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ11_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ11_XFERSIZE_OFFSET 0xa70 -#define GC_USB_DIEPTSIZ11_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ11_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ11_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ11_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ11_PKTCNT_OFFSET 0xa70 -#define GC_USB_DIEPTSIZ11_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ11_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ11_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ11_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ11_MC_OFFSET 0xa70 -#define GC_USB_DIEPDMA11_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA11_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA11_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA11_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA11_DMAADDR_OFFSET 0xa74 -#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_OFFSET 0xa58 +#define GC_USB_DIEPDMAB10_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB10_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB10_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB10_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB10_DMABUFFERADDR_OFFSET 0xa5c +#define GC_USB_DIEPCTL11_MPS_LSB 0x0 +#define GC_USB_DIEPCTL11_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL11_MPS_SIZE 0xb +#define GC_USB_DIEPCTL11_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_MPS_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL11_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL11_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL11_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_USBACTEP_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_DPID_LSB 0x10 +#define GC_USB_DIEPCTL11_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL11_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL11_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_DPID_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL11_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL11_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL11_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_NAKSTS_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL11_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL11_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL11_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_EPTYPE_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_STALL_LSB 0x15 +#define GC_USB_DIEPCTL11_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL11_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL11_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_STALL_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL11_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL11_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL11_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_TXFNUM_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL11_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL11_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL11_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_CNAK_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL11_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL11_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL11_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_SNAK_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL11_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL11_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL11_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_SETD0PID_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL11_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL11_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL11_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_SETD1PID_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL11_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL11_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL11_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_EPDIS_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL11_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL11_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL11_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_EPENA_OFFSET 0xa60 +#define GC_USB_DIEPINT11_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT11_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT11_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT11_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT11_XFERCOMPL_OFFSET 0xa68 +#define GC_USB_DIEPINT11_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT11_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT11_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT11_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT11_EPDISBLD_OFFSET 0xa68 +#define GC_USB_DIEPINT11_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT11_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT11_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT11_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT11_AHBERR_OFFSET 0xa68 +#define GC_USB_DIEPINT11_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT11_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT11_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT11_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT11_TIMEOUT_OFFSET 0xa68 +#define GC_USB_DIEPINT11_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT11_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT11_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT11_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT11_INTKNTXFEMP_OFFSET 0xa68 +#define GC_USB_DIEPINT11_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT11_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT11_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT11_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT11_INTKNEPMIS_OFFSET 0xa68 +#define GC_USB_DIEPINT11_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT11_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT11_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT11_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT11_INEPNAKEFF_OFFSET 0xa68 +#define GC_USB_DIEPINT11_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT11_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT11_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT11_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT11_TXFEMP_OFFSET 0xa68 +#define GC_USB_DIEPINT11_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT11_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT11_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT11_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT11_TXFIFOUNDRN_OFFSET 0xa68 +#define GC_USB_DIEPINT11_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT11_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT11_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT11_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT11_BNAINTR_OFFSET 0xa68 +#define GC_USB_DIEPINT11_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT11_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT11_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT11_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT11_PKTDRPSTS_OFFSET 0xa68 +#define GC_USB_DIEPINT11_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT11_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT11_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT11_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT11_BBLEERR_OFFSET 0xa68 +#define GC_USB_DIEPINT11_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT11_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT11_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT11_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT11_NAKINTRPT_OFFSET 0xa68 +#define GC_USB_DIEPINT11_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT11_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT11_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT11_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT11_NYETINTRPT_OFFSET 0xa68 +#define GC_USB_DIEPTSIZ11_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ11_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ11_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ11_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ11_XFERSIZE_OFFSET 0xa70 +#define GC_USB_DIEPTSIZ11_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ11_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ11_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ11_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ11_PKTCNT_OFFSET 0xa70 +#define GC_USB_DIEPTSIZ11_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ11_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ11_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ11_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ11_MC_OFFSET 0xa70 +#define GC_USB_DIEPDMA11_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA11_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA11_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA11_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA11_DMAADDR_OFFSET 0xa74 +#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_SIZE 0x10 #define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_OFFSET 0xa78 -#define GC_USB_DIEPDMAB11_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB11_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB11_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB11_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB11_DMABUFFERADDR_OFFSET 0xa7c -#define GC_USB_DIEPCTL12_MPS_LSB 0x0 -#define GC_USB_DIEPCTL12_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL12_MPS_SIZE 0xb -#define GC_USB_DIEPCTL12_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_MPS_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL12_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL12_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL12_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_USBACTEP_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_DPID_LSB 0x10 -#define GC_USB_DIEPCTL12_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL12_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL12_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_DPID_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL12_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL12_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL12_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_NAKSTS_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL12_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL12_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL12_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_EPTYPE_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_STALL_LSB 0x15 -#define GC_USB_DIEPCTL12_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL12_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL12_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_STALL_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL12_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL12_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL12_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_TXFNUM_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL12_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL12_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL12_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_CNAK_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL12_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL12_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL12_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_SNAK_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL12_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL12_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL12_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_SETD0PID_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL12_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL12_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL12_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_SETD1PID_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL12_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL12_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL12_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_EPDIS_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL12_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL12_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL12_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_EPENA_OFFSET 0xa80 -#define GC_USB_DIEPINT12_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT12_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT12_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT12_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT12_XFERCOMPL_OFFSET 0xa88 -#define GC_USB_DIEPINT12_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT12_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT12_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT12_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT12_EPDISBLD_OFFSET 0xa88 -#define GC_USB_DIEPINT12_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT12_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT12_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT12_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT12_AHBERR_OFFSET 0xa88 -#define GC_USB_DIEPINT12_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT12_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT12_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT12_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT12_TIMEOUT_OFFSET 0xa88 -#define GC_USB_DIEPINT12_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT12_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT12_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT12_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT12_INTKNTXFEMP_OFFSET 0xa88 -#define GC_USB_DIEPINT12_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT12_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT12_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT12_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT12_INTKNEPMIS_OFFSET 0xa88 -#define GC_USB_DIEPINT12_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT12_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT12_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT12_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT12_INEPNAKEFF_OFFSET 0xa88 -#define GC_USB_DIEPINT12_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT12_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT12_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT12_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT12_TXFEMP_OFFSET 0xa88 -#define GC_USB_DIEPINT12_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT12_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT12_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT12_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT12_TXFIFOUNDRN_OFFSET 0xa88 -#define GC_USB_DIEPINT12_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT12_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT12_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT12_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT12_BNAINTR_OFFSET 0xa88 -#define GC_USB_DIEPINT12_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT12_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT12_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT12_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT12_PKTDRPSTS_OFFSET 0xa88 -#define GC_USB_DIEPINT12_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT12_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT12_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT12_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT12_BBLEERR_OFFSET 0xa88 -#define GC_USB_DIEPINT12_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT12_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT12_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT12_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT12_NAKINTRPT_OFFSET 0xa88 -#define GC_USB_DIEPINT12_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT12_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT12_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT12_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT12_NYETINTRPT_OFFSET 0xa88 -#define GC_USB_DIEPTSIZ12_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ12_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ12_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ12_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ12_XFERSIZE_OFFSET 0xa90 -#define GC_USB_DIEPTSIZ12_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ12_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ12_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ12_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ12_PKTCNT_OFFSET 0xa90 -#define GC_USB_DIEPTSIZ12_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ12_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ12_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ12_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ12_MC_OFFSET 0xa90 -#define GC_USB_DIEPDMA12_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA12_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA12_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA12_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA12_DMAADDR_OFFSET 0xa94 -#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_OFFSET 0xa78 +#define GC_USB_DIEPDMAB11_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB11_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB11_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB11_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB11_DMABUFFERADDR_OFFSET 0xa7c +#define GC_USB_DIEPCTL12_MPS_LSB 0x0 +#define GC_USB_DIEPCTL12_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL12_MPS_SIZE 0xb +#define GC_USB_DIEPCTL12_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_MPS_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL12_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL12_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL12_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_USBACTEP_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_DPID_LSB 0x10 +#define GC_USB_DIEPCTL12_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL12_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL12_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_DPID_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL12_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL12_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL12_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_NAKSTS_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL12_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL12_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL12_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_EPTYPE_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_STALL_LSB 0x15 +#define GC_USB_DIEPCTL12_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL12_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL12_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_STALL_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL12_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL12_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL12_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_TXFNUM_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL12_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL12_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL12_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_CNAK_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL12_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL12_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL12_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_SNAK_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL12_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL12_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL12_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_SETD0PID_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL12_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL12_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL12_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_SETD1PID_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL12_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL12_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL12_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_EPDIS_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL12_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL12_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL12_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_EPENA_OFFSET 0xa80 +#define GC_USB_DIEPINT12_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT12_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT12_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT12_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT12_XFERCOMPL_OFFSET 0xa88 +#define GC_USB_DIEPINT12_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT12_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT12_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT12_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT12_EPDISBLD_OFFSET 0xa88 +#define GC_USB_DIEPINT12_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT12_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT12_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT12_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT12_AHBERR_OFFSET 0xa88 +#define GC_USB_DIEPINT12_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT12_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT12_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT12_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT12_TIMEOUT_OFFSET 0xa88 +#define GC_USB_DIEPINT12_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT12_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT12_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT12_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT12_INTKNTXFEMP_OFFSET 0xa88 +#define GC_USB_DIEPINT12_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT12_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT12_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT12_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT12_INTKNEPMIS_OFFSET 0xa88 +#define GC_USB_DIEPINT12_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT12_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT12_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT12_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT12_INEPNAKEFF_OFFSET 0xa88 +#define GC_USB_DIEPINT12_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT12_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT12_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT12_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT12_TXFEMP_OFFSET 0xa88 +#define GC_USB_DIEPINT12_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT12_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT12_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT12_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT12_TXFIFOUNDRN_OFFSET 0xa88 +#define GC_USB_DIEPINT12_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT12_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT12_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT12_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT12_BNAINTR_OFFSET 0xa88 +#define GC_USB_DIEPINT12_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT12_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT12_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT12_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT12_PKTDRPSTS_OFFSET 0xa88 +#define GC_USB_DIEPINT12_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT12_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT12_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT12_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT12_BBLEERR_OFFSET 0xa88 +#define GC_USB_DIEPINT12_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT12_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT12_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT12_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT12_NAKINTRPT_OFFSET 0xa88 +#define GC_USB_DIEPINT12_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT12_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT12_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT12_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT12_NYETINTRPT_OFFSET 0xa88 +#define GC_USB_DIEPTSIZ12_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ12_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ12_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ12_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ12_XFERSIZE_OFFSET 0xa90 +#define GC_USB_DIEPTSIZ12_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ12_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ12_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ12_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ12_PKTCNT_OFFSET 0xa90 +#define GC_USB_DIEPTSIZ12_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ12_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ12_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ12_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ12_MC_OFFSET 0xa90 +#define GC_USB_DIEPDMA12_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA12_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA12_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA12_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA12_DMAADDR_OFFSET 0xa94 +#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_SIZE 0x10 #define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_OFFSET 0xa98 -#define GC_USB_DIEPDMAB12_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB12_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB12_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB12_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB12_DMABUFFERADDR_OFFSET 0xa9c -#define GC_USB_DIEPCTL13_MPS_LSB 0x0 -#define GC_USB_DIEPCTL13_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL13_MPS_SIZE 0xb -#define GC_USB_DIEPCTL13_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_MPS_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL13_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL13_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL13_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_USBACTEP_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_DPID_LSB 0x10 -#define GC_USB_DIEPCTL13_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL13_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL13_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_DPID_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL13_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL13_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL13_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_NAKSTS_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL13_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL13_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL13_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_EPTYPE_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_STALL_LSB 0x15 -#define GC_USB_DIEPCTL13_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL13_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL13_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_STALL_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL13_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL13_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL13_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_TXFNUM_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL13_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL13_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL13_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_CNAK_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL13_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL13_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL13_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_SNAK_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL13_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL13_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL13_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_SETD0PID_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL13_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL13_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL13_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_SETD1PID_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL13_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL13_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL13_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_EPDIS_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL13_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL13_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL13_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_EPENA_OFFSET 0xaa0 -#define GC_USB_DIEPINT13_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT13_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT13_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT13_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT13_XFERCOMPL_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT13_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT13_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT13_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT13_EPDISBLD_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT13_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT13_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT13_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT13_AHBERR_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT13_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT13_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT13_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT13_TIMEOUT_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT13_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT13_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT13_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT13_INTKNTXFEMP_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT13_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT13_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT13_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT13_INTKNEPMIS_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT13_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT13_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT13_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT13_INEPNAKEFF_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT13_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT13_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT13_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT13_TXFEMP_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT13_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT13_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT13_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT13_TXFIFOUNDRN_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT13_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT13_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT13_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT13_BNAINTR_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT13_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT13_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT13_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT13_PKTDRPSTS_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT13_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT13_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT13_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT13_BBLEERR_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT13_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT13_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT13_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT13_NAKINTRPT_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT13_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT13_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT13_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT13_NYETINTRPT_OFFSET 0xaa8 -#define GC_USB_DIEPTSIZ13_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ13_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ13_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ13_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ13_XFERSIZE_OFFSET 0xab0 -#define GC_USB_DIEPTSIZ13_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ13_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ13_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ13_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ13_PKTCNT_OFFSET 0xab0 -#define GC_USB_DIEPTSIZ13_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ13_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ13_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ13_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ13_MC_OFFSET 0xab0 -#define GC_USB_DIEPDMA13_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA13_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA13_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA13_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA13_DMAADDR_OFFSET 0xab4 -#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_OFFSET 0xa98 +#define GC_USB_DIEPDMAB12_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB12_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB12_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB12_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB12_DMABUFFERADDR_OFFSET 0xa9c +#define GC_USB_DIEPCTL13_MPS_LSB 0x0 +#define GC_USB_DIEPCTL13_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL13_MPS_SIZE 0xb +#define GC_USB_DIEPCTL13_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_MPS_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL13_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL13_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL13_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_USBACTEP_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_DPID_LSB 0x10 +#define GC_USB_DIEPCTL13_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL13_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL13_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_DPID_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL13_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL13_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL13_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_NAKSTS_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL13_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL13_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL13_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_EPTYPE_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_STALL_LSB 0x15 +#define GC_USB_DIEPCTL13_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL13_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL13_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_STALL_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL13_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL13_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL13_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_TXFNUM_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL13_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL13_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL13_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_CNAK_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL13_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL13_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL13_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_SNAK_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL13_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL13_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL13_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_SETD0PID_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL13_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL13_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL13_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_SETD1PID_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL13_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL13_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL13_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_EPDIS_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL13_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL13_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL13_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_EPENA_OFFSET 0xaa0 +#define GC_USB_DIEPINT13_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT13_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT13_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT13_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT13_XFERCOMPL_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT13_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT13_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT13_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT13_EPDISBLD_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT13_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT13_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT13_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT13_AHBERR_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT13_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT13_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT13_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT13_TIMEOUT_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT13_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT13_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT13_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT13_INTKNTXFEMP_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT13_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT13_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT13_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT13_INTKNEPMIS_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT13_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT13_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT13_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT13_INEPNAKEFF_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT13_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT13_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT13_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT13_TXFEMP_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT13_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT13_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT13_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT13_TXFIFOUNDRN_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT13_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT13_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT13_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT13_BNAINTR_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT13_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT13_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT13_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT13_PKTDRPSTS_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT13_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT13_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT13_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT13_BBLEERR_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT13_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT13_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT13_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT13_NAKINTRPT_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT13_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT13_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT13_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT13_NYETINTRPT_OFFSET 0xaa8 +#define GC_USB_DIEPTSIZ13_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ13_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ13_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ13_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ13_XFERSIZE_OFFSET 0xab0 +#define GC_USB_DIEPTSIZ13_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ13_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ13_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ13_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ13_PKTCNT_OFFSET 0xab0 +#define GC_USB_DIEPTSIZ13_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ13_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ13_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ13_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ13_MC_OFFSET 0xab0 +#define GC_USB_DIEPDMA13_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA13_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA13_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA13_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA13_DMAADDR_OFFSET 0xab4 +#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_SIZE 0x10 #define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_OFFSET 0xab8 -#define GC_USB_DIEPDMAB13_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB13_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB13_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB13_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB13_DMABUFFERADDR_OFFSET 0xabc -#define GC_USB_DIEPCTL14_MPS_LSB 0x0 -#define GC_USB_DIEPCTL14_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL14_MPS_SIZE 0xb -#define GC_USB_DIEPCTL14_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_MPS_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL14_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL14_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL14_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_USBACTEP_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_DPID_LSB 0x10 -#define GC_USB_DIEPCTL14_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL14_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL14_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_DPID_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL14_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL14_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL14_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_NAKSTS_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL14_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL14_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL14_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_EPTYPE_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_STALL_LSB 0x15 -#define GC_USB_DIEPCTL14_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL14_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL14_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_STALL_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL14_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL14_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL14_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_TXFNUM_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL14_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL14_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL14_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_CNAK_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL14_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL14_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL14_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_SNAK_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL14_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL14_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL14_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_SETD0PID_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL14_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL14_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL14_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_SETD1PID_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL14_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL14_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL14_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_EPDIS_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL14_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL14_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL14_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_EPENA_OFFSET 0xac0 -#define GC_USB_DIEPINT14_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT14_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT14_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT14_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT14_XFERCOMPL_OFFSET 0xac8 -#define GC_USB_DIEPINT14_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT14_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT14_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT14_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT14_EPDISBLD_OFFSET 0xac8 -#define GC_USB_DIEPINT14_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT14_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT14_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT14_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT14_AHBERR_OFFSET 0xac8 -#define GC_USB_DIEPINT14_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT14_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT14_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT14_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT14_TIMEOUT_OFFSET 0xac8 -#define GC_USB_DIEPINT14_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT14_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT14_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT14_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT14_INTKNTXFEMP_OFFSET 0xac8 -#define GC_USB_DIEPINT14_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT14_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT14_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT14_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT14_INTKNEPMIS_OFFSET 0xac8 -#define GC_USB_DIEPINT14_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT14_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT14_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT14_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT14_INEPNAKEFF_OFFSET 0xac8 -#define GC_USB_DIEPINT14_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT14_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT14_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT14_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT14_TXFEMP_OFFSET 0xac8 -#define GC_USB_DIEPINT14_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT14_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT14_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT14_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT14_TXFIFOUNDRN_OFFSET 0xac8 -#define GC_USB_DIEPINT14_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT14_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT14_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT14_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT14_BNAINTR_OFFSET 0xac8 -#define GC_USB_DIEPINT14_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT14_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT14_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT14_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT14_PKTDRPSTS_OFFSET 0xac8 -#define GC_USB_DIEPINT14_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT14_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT14_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT14_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT14_BBLEERR_OFFSET 0xac8 -#define GC_USB_DIEPINT14_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT14_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT14_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT14_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT14_NAKINTRPT_OFFSET 0xac8 -#define GC_USB_DIEPINT14_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT14_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT14_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT14_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT14_NYETINTRPT_OFFSET 0xac8 -#define GC_USB_DIEPTSIZ14_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ14_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ14_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ14_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ14_XFERSIZE_OFFSET 0xad0 -#define GC_USB_DIEPTSIZ14_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ14_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ14_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ14_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ14_PKTCNT_OFFSET 0xad0 -#define GC_USB_DIEPTSIZ14_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ14_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ14_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ14_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ14_MC_OFFSET 0xad0 -#define GC_USB_DIEPDMA14_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA14_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA14_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA14_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA14_DMAADDR_OFFSET 0xad4 -#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_OFFSET 0xab8 +#define GC_USB_DIEPDMAB13_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB13_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB13_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB13_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB13_DMABUFFERADDR_OFFSET 0xabc +#define GC_USB_DIEPCTL14_MPS_LSB 0x0 +#define GC_USB_DIEPCTL14_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL14_MPS_SIZE 0xb +#define GC_USB_DIEPCTL14_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_MPS_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL14_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL14_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL14_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_USBACTEP_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_DPID_LSB 0x10 +#define GC_USB_DIEPCTL14_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL14_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL14_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_DPID_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL14_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL14_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL14_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_NAKSTS_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL14_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL14_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL14_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_EPTYPE_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_STALL_LSB 0x15 +#define GC_USB_DIEPCTL14_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL14_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL14_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_STALL_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL14_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL14_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL14_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_TXFNUM_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL14_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL14_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL14_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_CNAK_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL14_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL14_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL14_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_SNAK_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL14_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL14_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL14_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_SETD0PID_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL14_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL14_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL14_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_SETD1PID_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL14_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL14_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL14_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_EPDIS_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL14_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL14_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL14_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_EPENA_OFFSET 0xac0 +#define GC_USB_DIEPINT14_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT14_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT14_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT14_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT14_XFERCOMPL_OFFSET 0xac8 +#define GC_USB_DIEPINT14_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT14_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT14_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT14_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT14_EPDISBLD_OFFSET 0xac8 +#define GC_USB_DIEPINT14_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT14_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT14_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT14_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT14_AHBERR_OFFSET 0xac8 +#define GC_USB_DIEPINT14_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT14_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT14_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT14_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT14_TIMEOUT_OFFSET 0xac8 +#define GC_USB_DIEPINT14_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT14_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT14_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT14_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT14_INTKNTXFEMP_OFFSET 0xac8 +#define GC_USB_DIEPINT14_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT14_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT14_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT14_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT14_INTKNEPMIS_OFFSET 0xac8 +#define GC_USB_DIEPINT14_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT14_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT14_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT14_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT14_INEPNAKEFF_OFFSET 0xac8 +#define GC_USB_DIEPINT14_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT14_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT14_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT14_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT14_TXFEMP_OFFSET 0xac8 +#define GC_USB_DIEPINT14_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT14_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT14_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT14_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT14_TXFIFOUNDRN_OFFSET 0xac8 +#define GC_USB_DIEPINT14_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT14_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT14_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT14_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT14_BNAINTR_OFFSET 0xac8 +#define GC_USB_DIEPINT14_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT14_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT14_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT14_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT14_PKTDRPSTS_OFFSET 0xac8 +#define GC_USB_DIEPINT14_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT14_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT14_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT14_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT14_BBLEERR_OFFSET 0xac8 +#define GC_USB_DIEPINT14_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT14_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT14_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT14_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT14_NAKINTRPT_OFFSET 0xac8 +#define GC_USB_DIEPINT14_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT14_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT14_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT14_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT14_NYETINTRPT_OFFSET 0xac8 +#define GC_USB_DIEPTSIZ14_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ14_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ14_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ14_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ14_XFERSIZE_OFFSET 0xad0 +#define GC_USB_DIEPTSIZ14_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ14_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ14_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ14_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ14_PKTCNT_OFFSET 0xad0 +#define GC_USB_DIEPTSIZ14_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ14_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ14_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ14_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ14_MC_OFFSET 0xad0 +#define GC_USB_DIEPDMA14_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA14_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA14_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA14_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA14_DMAADDR_OFFSET 0xad4 +#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_SIZE 0x10 #define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_OFFSET 0xad8 -#define GC_USB_DIEPDMAB14_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB14_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB14_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB14_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB14_DMABUFFERADDR_OFFSET 0xadc -#define GC_USB_DIEPCTL15_MPS_LSB 0x0 -#define GC_USB_DIEPCTL15_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL15_MPS_SIZE 0xb -#define GC_USB_DIEPCTL15_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_MPS_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL15_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL15_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL15_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_USBACTEP_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_DPID_LSB 0x10 -#define GC_USB_DIEPCTL15_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL15_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL15_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_DPID_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL15_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL15_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL15_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_NAKSTS_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL15_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL15_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL15_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_EPTYPE_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_STALL_LSB 0x15 -#define GC_USB_DIEPCTL15_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL15_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL15_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_STALL_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL15_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL15_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL15_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_TXFNUM_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL15_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL15_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL15_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_CNAK_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL15_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL15_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL15_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_SNAK_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL15_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL15_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL15_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_SETD0PID_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL15_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL15_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL15_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_SETD1PID_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL15_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL15_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL15_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_EPDIS_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL15_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL15_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL15_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_EPENA_OFFSET 0xae0 -#define GC_USB_DIEPINT15_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT15_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT15_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT15_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT15_XFERCOMPL_OFFSET 0xae8 -#define GC_USB_DIEPINT15_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT15_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT15_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT15_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT15_EPDISBLD_OFFSET 0xae8 -#define GC_USB_DIEPINT15_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT15_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT15_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT15_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT15_AHBERR_OFFSET 0xae8 -#define GC_USB_DIEPINT15_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT15_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT15_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT15_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT15_TIMEOUT_OFFSET 0xae8 -#define GC_USB_DIEPINT15_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT15_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT15_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT15_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT15_INTKNTXFEMP_OFFSET 0xae8 -#define GC_USB_DIEPINT15_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT15_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT15_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT15_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT15_INTKNEPMIS_OFFSET 0xae8 -#define GC_USB_DIEPINT15_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT15_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT15_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT15_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT15_INEPNAKEFF_OFFSET 0xae8 -#define GC_USB_DIEPINT15_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT15_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT15_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT15_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT15_TXFEMP_OFFSET 0xae8 -#define GC_USB_DIEPINT15_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT15_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT15_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT15_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT15_TXFIFOUNDRN_OFFSET 0xae8 -#define GC_USB_DIEPINT15_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT15_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT15_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT15_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT15_BNAINTR_OFFSET 0xae8 -#define GC_USB_DIEPINT15_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT15_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT15_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT15_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT15_PKTDRPSTS_OFFSET 0xae8 -#define GC_USB_DIEPINT15_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT15_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT15_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT15_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT15_BBLEERR_OFFSET 0xae8 -#define GC_USB_DIEPINT15_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT15_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT15_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT15_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT15_NAKINTRPT_OFFSET 0xae8 -#define GC_USB_DIEPINT15_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT15_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT15_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT15_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT15_NYETINTRPT_OFFSET 0xae8 -#define GC_USB_DIEPTSIZ15_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ15_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ15_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ15_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ15_XFERSIZE_OFFSET 0xaf0 -#define GC_USB_DIEPTSIZ15_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ15_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ15_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ15_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ15_PKTCNT_OFFSET 0xaf0 -#define GC_USB_DIEPTSIZ15_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ15_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ15_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ15_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ15_MC_OFFSET 0xaf0 -#define GC_USB_DIEPDMA15_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA15_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA15_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA15_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA15_DMAADDR_OFFSET 0xaf4 -#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_OFFSET 0xad8 +#define GC_USB_DIEPDMAB14_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB14_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB14_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB14_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB14_DMABUFFERADDR_OFFSET 0xadc +#define GC_USB_DIEPCTL15_MPS_LSB 0x0 +#define GC_USB_DIEPCTL15_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL15_MPS_SIZE 0xb +#define GC_USB_DIEPCTL15_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_MPS_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL15_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL15_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL15_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_USBACTEP_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_DPID_LSB 0x10 +#define GC_USB_DIEPCTL15_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL15_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL15_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_DPID_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL15_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL15_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL15_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_NAKSTS_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL15_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL15_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL15_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_EPTYPE_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_STALL_LSB 0x15 +#define GC_USB_DIEPCTL15_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL15_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL15_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_STALL_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL15_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL15_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL15_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_TXFNUM_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL15_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL15_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL15_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_CNAK_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL15_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL15_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL15_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_SNAK_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL15_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL15_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL15_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_SETD0PID_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL15_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL15_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL15_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_SETD1PID_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL15_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL15_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL15_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_EPDIS_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL15_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL15_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL15_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_EPENA_OFFSET 0xae0 +#define GC_USB_DIEPINT15_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT15_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT15_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT15_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT15_XFERCOMPL_OFFSET 0xae8 +#define GC_USB_DIEPINT15_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT15_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT15_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT15_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT15_EPDISBLD_OFFSET 0xae8 +#define GC_USB_DIEPINT15_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT15_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT15_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT15_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT15_AHBERR_OFFSET 0xae8 +#define GC_USB_DIEPINT15_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT15_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT15_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT15_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT15_TIMEOUT_OFFSET 0xae8 +#define GC_USB_DIEPINT15_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT15_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT15_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT15_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT15_INTKNTXFEMP_OFFSET 0xae8 +#define GC_USB_DIEPINT15_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT15_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT15_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT15_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT15_INTKNEPMIS_OFFSET 0xae8 +#define GC_USB_DIEPINT15_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT15_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT15_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT15_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT15_INEPNAKEFF_OFFSET 0xae8 +#define GC_USB_DIEPINT15_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT15_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT15_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT15_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT15_TXFEMP_OFFSET 0xae8 +#define GC_USB_DIEPINT15_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT15_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT15_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT15_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT15_TXFIFOUNDRN_OFFSET 0xae8 +#define GC_USB_DIEPINT15_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT15_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT15_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT15_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT15_BNAINTR_OFFSET 0xae8 +#define GC_USB_DIEPINT15_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT15_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT15_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT15_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT15_PKTDRPSTS_OFFSET 0xae8 +#define GC_USB_DIEPINT15_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT15_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT15_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT15_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT15_BBLEERR_OFFSET 0xae8 +#define GC_USB_DIEPINT15_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT15_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT15_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT15_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT15_NAKINTRPT_OFFSET 0xae8 +#define GC_USB_DIEPINT15_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT15_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT15_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT15_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT15_NYETINTRPT_OFFSET 0xae8 +#define GC_USB_DIEPTSIZ15_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ15_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ15_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ15_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ15_XFERSIZE_OFFSET 0xaf0 +#define GC_USB_DIEPTSIZ15_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ15_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ15_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ15_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ15_PKTCNT_OFFSET 0xaf0 +#define GC_USB_DIEPTSIZ15_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ15_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ15_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ15_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ15_MC_OFFSET 0xaf0 +#define GC_USB_DIEPDMA15_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA15_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA15_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA15_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA15_DMAADDR_OFFSET 0xaf4 +#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_SIZE 0x10 #define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_OFFSET 0xaf8 -#define GC_USB_DIEPDMAB15_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB15_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB15_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB15_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB15_DMABUFFERADDR_OFFSET 0xafc -#define GC_USB_DOEPCTL0_MPS_LSB 0x0 -#define GC_USB_DOEPCTL0_MPS_MASK 0x3 -#define GC_USB_DOEPCTL0_MPS_SIZE 0x2 -#define GC_USB_DOEPCTL0_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_MPS_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL0_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL0_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL0_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_USBACTEP_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL0_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL0_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL0_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_NAKSTS_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL0_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL0_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL0_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_EPTYPE_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_SNP_LSB 0x14 -#define GC_USB_DOEPCTL0_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL0_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL0_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_SNP_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_STALL_LSB 0x15 -#define GC_USB_DOEPCTL0_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL0_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL0_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_STALL_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL0_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL0_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL0_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_CNAK_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL0_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL0_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL0_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_SNAK_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL0_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL0_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL0_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_EPDIS_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL0_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL0_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL0_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_EPENA_OFFSET 0xb00 -#define GC_USB_DOEPINT0_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT0_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT0_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT0_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT0_XFERCOMPL_OFFSET 0xb08 -#define GC_USB_DOEPINT0_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT0_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT0_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT0_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT0_EPDISBLD_OFFSET 0xb08 -#define GC_USB_DOEPINT0_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT0_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT0_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT0_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT0_AHBERR_OFFSET 0xb08 -#define GC_USB_DOEPINT0_SETUP_LSB 0x3 -#define GC_USB_DOEPINT0_SETUP_MASK 0x8 -#define GC_USB_DOEPINT0_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT0_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT0_SETUP_OFFSET 0xb08 -#define GC_USB_DOEPINT0_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT0_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT0_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT0_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT0_OUTTKNEPDIS_OFFSET 0xb08 -#define GC_USB_DOEPINT0_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT0_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT0_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT0_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT0_STSPHSERCVD_OFFSET 0xb08 -#define GC_USB_DOEPINT0_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT0_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT0_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT0_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT0_BACK2BACKSETUP_OFFSET 0xb08 -#define GC_USB_DOEPINT0_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT0_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT0_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT0_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT0_OUTPKTERR_OFFSET 0xb08 -#define GC_USB_DOEPINT0_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT0_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT0_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT0_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT0_BNAINTR_OFFSET 0xb08 -#define GC_USB_DOEPINT0_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT0_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT0_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT0_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT0_PKTDRPSTS_OFFSET 0xb08 -#define GC_USB_DOEPINT0_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT0_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT0_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT0_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT0_BBLEERR_OFFSET 0xb08 -#define GC_USB_DOEPINT0_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT0_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT0_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT0_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT0_NAKINTRPT_OFFSET 0xb08 -#define GC_USB_DOEPINT0_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT0_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT0_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT0_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT0_NYETINTRPT_OFFSET 0xb08 -#define GC_USB_DOEPINT0_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT0_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT0_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT0_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT0_STUPPKTRCVD_OFFSET 0xb08 -#define GC_USB_DOEPTSIZ0_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ0_XFERSIZE_MASK 0x7f -#define GC_USB_DOEPTSIZ0_XFERSIZE_SIZE 0x7 -#define GC_USB_DOEPTSIZ0_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ0_XFERSIZE_OFFSET 0xb10 -#define GC_USB_DOEPTSIZ0_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ0_PKTCNT_MASK 0x80000 -#define GC_USB_DOEPTSIZ0_PKTCNT_SIZE 0x1 -#define GC_USB_DOEPTSIZ0_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ0_PKTCNT_OFFSET 0xb10 -#define GC_USB_DOEPTSIZ0_SUPCNT_LSB 0x1d -#define GC_USB_DOEPTSIZ0_SUPCNT_MASK 0x60000000 -#define GC_USB_DOEPTSIZ0_SUPCNT_SIZE 0x2 -#define GC_USB_DOEPTSIZ0_SUPCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ0_SUPCNT_OFFSET 0xb10 -#define GC_USB_DOEPDMA0_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA0_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA0_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA0_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA0_DMAADDR_OFFSET 0xb14 -#define GC_USB_DOEPDMAB0_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB0_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB0_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB0_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB0_DMABUFFERADDR_OFFSET 0xb1c -#define GC_USB_DOEPCTL1_MPS_LSB 0x0 -#define GC_USB_DOEPCTL1_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL1_MPS_SIZE 0xb -#define GC_USB_DOEPCTL1_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_MPS_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL1_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL1_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL1_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_USBACTEP_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_DPID_LSB 0x10 -#define GC_USB_DOEPCTL1_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL1_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL1_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_DPID_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL1_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL1_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL1_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_NAKSTS_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL1_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL1_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL1_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_EPTYPE_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_SNP_LSB 0x14 -#define GC_USB_DOEPCTL1_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL1_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL1_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_SNP_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_STALL_LSB 0x15 -#define GC_USB_DOEPCTL1_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL1_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL1_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_STALL_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL1_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL1_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL1_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_CNAK_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL1_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL1_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL1_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_SNAK_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL1_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL1_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL1_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_SETD0PID_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL1_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL1_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL1_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_SETD1PID_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL1_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL1_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL1_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_EPDIS_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL1_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL1_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL1_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_EPENA_OFFSET 0xb20 -#define GC_USB_DOEPINT1_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT1_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT1_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT1_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT1_XFERCOMPL_OFFSET 0xb28 -#define GC_USB_DOEPINT1_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT1_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT1_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT1_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT1_EPDISBLD_OFFSET 0xb28 -#define GC_USB_DOEPINT1_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT1_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT1_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT1_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT1_AHBERR_OFFSET 0xb28 -#define GC_USB_DOEPINT1_SETUP_LSB 0x3 -#define GC_USB_DOEPINT1_SETUP_MASK 0x8 -#define GC_USB_DOEPINT1_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT1_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT1_SETUP_OFFSET 0xb28 -#define GC_USB_DOEPINT1_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT1_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT1_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT1_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT1_OUTTKNEPDIS_OFFSET 0xb28 -#define GC_USB_DOEPINT1_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT1_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT1_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT1_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT1_STSPHSERCVD_OFFSET 0xb28 -#define GC_USB_DOEPINT1_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT1_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT1_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT1_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT1_BACK2BACKSETUP_OFFSET 0xb28 -#define GC_USB_DOEPINT1_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT1_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT1_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT1_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT1_OUTPKTERR_OFFSET 0xb28 -#define GC_USB_DOEPINT1_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT1_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT1_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT1_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT1_BNAINTR_OFFSET 0xb28 -#define GC_USB_DOEPINT1_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT1_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT1_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT1_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT1_PKTDRPSTS_OFFSET 0xb28 -#define GC_USB_DOEPINT1_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT1_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT1_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT1_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT1_BBLEERR_OFFSET 0xb28 -#define GC_USB_DOEPINT1_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT1_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT1_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT1_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT1_NAKINTRPT_OFFSET 0xb28 -#define GC_USB_DOEPINT1_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT1_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT1_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT1_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT1_NYETINTRPT_OFFSET 0xb28 -#define GC_USB_DOEPINT1_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT1_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT1_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT1_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT1_STUPPKTRCVD_OFFSET 0xb28 -#define GC_USB_DOEPTSIZ1_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ1_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ1_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ1_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ1_XFERSIZE_OFFSET 0xb30 -#define GC_USB_DOEPTSIZ1_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ1_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ1_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ1_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ1_PKTCNT_OFFSET 0xb30 -#define GC_USB_DOEPTSIZ1_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ1_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ1_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ1_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ1_RXDPID_OFFSET 0xb30 -#define GC_USB_DOEPDMA1_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA1_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA1_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA1_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA1_DMAADDR_OFFSET 0xb34 -#define GC_USB_DOEPDMAB1_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB1_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB1_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB1_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB1_DMABUFFERADDR_OFFSET 0xb3c -#define GC_USB_DOEPCTL2_MPS_LSB 0x0 -#define GC_USB_DOEPCTL2_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL2_MPS_SIZE 0xb -#define GC_USB_DOEPCTL2_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_MPS_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL2_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL2_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL2_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_USBACTEP_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_DPID_LSB 0x10 -#define GC_USB_DOEPCTL2_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL2_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL2_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_DPID_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL2_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL2_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL2_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_NAKSTS_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL2_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL2_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL2_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_EPTYPE_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_SNP_LSB 0x14 -#define GC_USB_DOEPCTL2_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL2_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL2_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_SNP_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_STALL_LSB 0x15 -#define GC_USB_DOEPCTL2_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL2_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL2_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_STALL_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL2_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL2_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL2_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_CNAK_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL2_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL2_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL2_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_SNAK_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL2_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL2_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL2_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_SETD0PID_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL2_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL2_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL2_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_SETD1PID_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL2_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL2_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL2_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_EPDIS_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL2_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL2_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL2_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_EPENA_OFFSET 0xb40 -#define GC_USB_DOEPINT2_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT2_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT2_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT2_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT2_XFERCOMPL_OFFSET 0xb48 -#define GC_USB_DOEPINT2_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT2_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT2_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT2_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT2_EPDISBLD_OFFSET 0xb48 -#define GC_USB_DOEPINT2_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT2_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT2_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT2_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT2_AHBERR_OFFSET 0xb48 -#define GC_USB_DOEPINT2_SETUP_LSB 0x3 -#define GC_USB_DOEPINT2_SETUP_MASK 0x8 -#define GC_USB_DOEPINT2_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT2_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT2_SETUP_OFFSET 0xb48 -#define GC_USB_DOEPINT2_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT2_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT2_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT2_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT2_OUTTKNEPDIS_OFFSET 0xb48 -#define GC_USB_DOEPINT2_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT2_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT2_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT2_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT2_STSPHSERCVD_OFFSET 0xb48 -#define GC_USB_DOEPINT2_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT2_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT2_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT2_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT2_BACK2BACKSETUP_OFFSET 0xb48 -#define GC_USB_DOEPINT2_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT2_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT2_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT2_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT2_OUTPKTERR_OFFSET 0xb48 -#define GC_USB_DOEPINT2_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT2_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT2_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT2_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT2_BNAINTR_OFFSET 0xb48 -#define GC_USB_DOEPINT2_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT2_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT2_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT2_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT2_PKTDRPSTS_OFFSET 0xb48 -#define GC_USB_DOEPINT2_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT2_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT2_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT2_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT2_BBLEERR_OFFSET 0xb48 -#define GC_USB_DOEPINT2_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT2_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT2_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT2_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT2_NAKINTRPT_OFFSET 0xb48 -#define GC_USB_DOEPINT2_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT2_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT2_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT2_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT2_NYETINTRPT_OFFSET 0xb48 -#define GC_USB_DOEPINT2_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT2_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT2_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT2_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT2_STUPPKTRCVD_OFFSET 0xb48 -#define GC_USB_DOEPTSIZ2_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ2_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ2_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ2_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ2_XFERSIZE_OFFSET 0xb50 -#define GC_USB_DOEPTSIZ2_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ2_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ2_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ2_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ2_PKTCNT_OFFSET 0xb50 -#define GC_USB_DOEPTSIZ2_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ2_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ2_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ2_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ2_RXDPID_OFFSET 0xb50 -#define GC_USB_DOEPDMA2_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA2_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA2_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA2_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA2_DMAADDR_OFFSET 0xb54 -#define GC_USB_DOEPDMAB2_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB2_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB2_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB2_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB2_DMABUFFERADDR_OFFSET 0xb5c -#define GC_USB_DOEPCTL3_MPS_LSB 0x0 -#define GC_USB_DOEPCTL3_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL3_MPS_SIZE 0xb -#define GC_USB_DOEPCTL3_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_MPS_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL3_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL3_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL3_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_USBACTEP_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_DPID_LSB 0x10 -#define GC_USB_DOEPCTL3_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL3_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL3_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_DPID_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL3_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL3_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL3_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_NAKSTS_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL3_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL3_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL3_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_EPTYPE_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_SNP_LSB 0x14 -#define GC_USB_DOEPCTL3_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL3_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL3_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_SNP_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_STALL_LSB 0x15 -#define GC_USB_DOEPCTL3_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL3_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL3_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_STALL_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL3_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL3_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL3_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_CNAK_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL3_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL3_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL3_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_SNAK_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL3_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL3_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL3_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_SETD0PID_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL3_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL3_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL3_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_SETD1PID_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL3_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL3_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL3_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_EPDIS_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL3_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL3_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL3_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_EPENA_OFFSET 0xb60 -#define GC_USB_DOEPINT3_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT3_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT3_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT3_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT3_XFERCOMPL_OFFSET 0xb68 -#define GC_USB_DOEPINT3_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT3_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT3_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT3_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT3_EPDISBLD_OFFSET 0xb68 -#define GC_USB_DOEPINT3_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT3_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT3_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT3_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT3_AHBERR_OFFSET 0xb68 -#define GC_USB_DOEPINT3_SETUP_LSB 0x3 -#define GC_USB_DOEPINT3_SETUP_MASK 0x8 -#define GC_USB_DOEPINT3_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT3_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT3_SETUP_OFFSET 0xb68 -#define GC_USB_DOEPINT3_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT3_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT3_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT3_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT3_OUTTKNEPDIS_OFFSET 0xb68 -#define GC_USB_DOEPINT3_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT3_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT3_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT3_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT3_STSPHSERCVD_OFFSET 0xb68 -#define GC_USB_DOEPINT3_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT3_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT3_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT3_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT3_BACK2BACKSETUP_OFFSET 0xb68 -#define GC_USB_DOEPINT3_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT3_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT3_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT3_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT3_OUTPKTERR_OFFSET 0xb68 -#define GC_USB_DOEPINT3_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT3_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT3_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT3_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT3_BNAINTR_OFFSET 0xb68 -#define GC_USB_DOEPINT3_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT3_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT3_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT3_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT3_PKTDRPSTS_OFFSET 0xb68 -#define GC_USB_DOEPINT3_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT3_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT3_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT3_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT3_BBLEERR_OFFSET 0xb68 -#define GC_USB_DOEPINT3_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT3_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT3_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT3_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT3_NAKINTRPT_OFFSET 0xb68 -#define GC_USB_DOEPINT3_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT3_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT3_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT3_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT3_NYETINTRPT_OFFSET 0xb68 -#define GC_USB_DOEPINT3_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT3_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT3_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT3_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT3_STUPPKTRCVD_OFFSET 0xb68 -#define GC_USB_DOEPTSIZ3_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ3_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ3_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ3_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ3_XFERSIZE_OFFSET 0xb70 -#define GC_USB_DOEPTSIZ3_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ3_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ3_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ3_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ3_PKTCNT_OFFSET 0xb70 -#define GC_USB_DOEPTSIZ3_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ3_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ3_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ3_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ3_RXDPID_OFFSET 0xb70 -#define GC_USB_DOEPDMA3_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA3_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA3_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA3_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA3_DMAADDR_OFFSET 0xb74 -#define GC_USB_DOEPDMAB3_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB3_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB3_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB3_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB3_DMABUFFERADDR_OFFSET 0xb7c -#define GC_USB_DOEPCTL4_MPS_LSB 0x0 -#define GC_USB_DOEPCTL4_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL4_MPS_SIZE 0xb -#define GC_USB_DOEPCTL4_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_MPS_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL4_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL4_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL4_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_USBACTEP_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_DPID_LSB 0x10 -#define GC_USB_DOEPCTL4_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL4_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL4_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_DPID_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL4_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL4_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL4_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_NAKSTS_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL4_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL4_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL4_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_EPTYPE_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_SNP_LSB 0x14 -#define GC_USB_DOEPCTL4_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL4_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL4_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_SNP_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_STALL_LSB 0x15 -#define GC_USB_DOEPCTL4_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL4_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL4_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_STALL_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL4_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL4_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL4_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_CNAK_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL4_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL4_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL4_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_SNAK_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL4_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL4_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL4_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_SETD0PID_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL4_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL4_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL4_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_SETD1PID_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL4_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL4_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL4_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_EPDIS_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL4_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL4_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL4_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_EPENA_OFFSET 0xb80 -#define GC_USB_DOEPINT4_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT4_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT4_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT4_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT4_XFERCOMPL_OFFSET 0xb88 -#define GC_USB_DOEPINT4_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT4_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT4_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT4_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT4_EPDISBLD_OFFSET 0xb88 -#define GC_USB_DOEPINT4_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT4_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT4_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT4_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT4_AHBERR_OFFSET 0xb88 -#define GC_USB_DOEPINT4_SETUP_LSB 0x3 -#define GC_USB_DOEPINT4_SETUP_MASK 0x8 -#define GC_USB_DOEPINT4_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT4_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT4_SETUP_OFFSET 0xb88 -#define GC_USB_DOEPINT4_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT4_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT4_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT4_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT4_OUTTKNEPDIS_OFFSET 0xb88 -#define GC_USB_DOEPINT4_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT4_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT4_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT4_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT4_STSPHSERCVD_OFFSET 0xb88 -#define GC_USB_DOEPINT4_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT4_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT4_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT4_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT4_BACK2BACKSETUP_OFFSET 0xb88 -#define GC_USB_DOEPINT4_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT4_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT4_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT4_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT4_OUTPKTERR_OFFSET 0xb88 -#define GC_USB_DOEPINT4_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT4_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT4_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT4_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT4_BNAINTR_OFFSET 0xb88 -#define GC_USB_DOEPINT4_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT4_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT4_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT4_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT4_PKTDRPSTS_OFFSET 0xb88 -#define GC_USB_DOEPINT4_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT4_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT4_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT4_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT4_BBLEERR_OFFSET 0xb88 -#define GC_USB_DOEPINT4_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT4_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT4_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT4_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT4_NAKINTRPT_OFFSET 0xb88 -#define GC_USB_DOEPINT4_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT4_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT4_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT4_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT4_NYETINTRPT_OFFSET 0xb88 -#define GC_USB_DOEPINT4_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT4_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT4_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT4_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT4_STUPPKTRCVD_OFFSET 0xb88 -#define GC_USB_DOEPTSIZ4_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ4_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ4_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ4_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ4_XFERSIZE_OFFSET 0xb90 -#define GC_USB_DOEPTSIZ4_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ4_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ4_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ4_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ4_PKTCNT_OFFSET 0xb90 -#define GC_USB_DOEPTSIZ4_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ4_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ4_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ4_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ4_RXDPID_OFFSET 0xb90 -#define GC_USB_DOEPDMA4_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA4_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA4_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA4_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA4_DMAADDR_OFFSET 0xb94 -#define GC_USB_DOEPDMAB4_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB4_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB4_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB4_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB4_DMABUFFERADDR_OFFSET 0xb9c -#define GC_USB_DOEPCTL5_MPS_LSB 0x0 -#define GC_USB_DOEPCTL5_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL5_MPS_SIZE 0xb -#define GC_USB_DOEPCTL5_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_MPS_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL5_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL5_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL5_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_USBACTEP_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_DPID_LSB 0x10 -#define GC_USB_DOEPCTL5_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL5_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL5_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_DPID_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL5_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL5_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL5_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_NAKSTS_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL5_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL5_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL5_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_EPTYPE_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_SNP_LSB 0x14 -#define GC_USB_DOEPCTL5_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL5_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL5_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_SNP_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_STALL_LSB 0x15 -#define GC_USB_DOEPCTL5_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL5_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL5_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_STALL_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL5_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL5_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL5_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_CNAK_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL5_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL5_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL5_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_SNAK_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL5_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL5_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL5_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_SETD0PID_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL5_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL5_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL5_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_SETD1PID_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL5_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL5_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL5_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_EPDIS_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL5_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL5_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL5_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_EPENA_OFFSET 0xba0 -#define GC_USB_DOEPINT5_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT5_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT5_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT5_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT5_XFERCOMPL_OFFSET 0xba8 -#define GC_USB_DOEPINT5_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT5_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT5_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT5_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT5_EPDISBLD_OFFSET 0xba8 -#define GC_USB_DOEPINT5_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT5_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT5_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT5_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT5_AHBERR_OFFSET 0xba8 -#define GC_USB_DOEPINT5_SETUP_LSB 0x3 -#define GC_USB_DOEPINT5_SETUP_MASK 0x8 -#define GC_USB_DOEPINT5_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT5_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT5_SETUP_OFFSET 0xba8 -#define GC_USB_DOEPINT5_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT5_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT5_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT5_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT5_OUTTKNEPDIS_OFFSET 0xba8 -#define GC_USB_DOEPINT5_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT5_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT5_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT5_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT5_STSPHSERCVD_OFFSET 0xba8 -#define GC_USB_DOEPINT5_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT5_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT5_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT5_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT5_BACK2BACKSETUP_OFFSET 0xba8 -#define GC_USB_DOEPINT5_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT5_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT5_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT5_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT5_OUTPKTERR_OFFSET 0xba8 -#define GC_USB_DOEPINT5_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT5_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT5_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT5_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT5_BNAINTR_OFFSET 0xba8 -#define GC_USB_DOEPINT5_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT5_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT5_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT5_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT5_PKTDRPSTS_OFFSET 0xba8 -#define GC_USB_DOEPINT5_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT5_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT5_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT5_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT5_BBLEERR_OFFSET 0xba8 -#define GC_USB_DOEPINT5_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT5_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT5_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT5_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT5_NAKINTRPT_OFFSET 0xba8 -#define GC_USB_DOEPINT5_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT5_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT5_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT5_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT5_NYETINTRPT_OFFSET 0xba8 -#define GC_USB_DOEPINT5_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT5_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT5_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT5_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT5_STUPPKTRCVD_OFFSET 0xba8 -#define GC_USB_DOEPTSIZ5_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ5_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ5_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ5_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ5_XFERSIZE_OFFSET 0xbb0 -#define GC_USB_DOEPTSIZ5_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ5_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ5_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ5_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ5_PKTCNT_OFFSET 0xbb0 -#define GC_USB_DOEPTSIZ5_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ5_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ5_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ5_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ5_RXDPID_OFFSET 0xbb0 -#define GC_USB_DOEPDMA5_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA5_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA5_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA5_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA5_DMAADDR_OFFSET 0xbb4 -#define GC_USB_DOEPDMAB5_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB5_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB5_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB5_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB5_DMABUFFERADDR_OFFSET 0xbbc -#define GC_USB_DOEPCTL6_MPS_LSB 0x0 -#define GC_USB_DOEPCTL6_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL6_MPS_SIZE 0xb -#define GC_USB_DOEPCTL6_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_MPS_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL6_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL6_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL6_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_USBACTEP_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_DPID_LSB 0x10 -#define GC_USB_DOEPCTL6_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL6_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL6_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_DPID_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL6_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL6_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL6_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_NAKSTS_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL6_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL6_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL6_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_EPTYPE_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_SNP_LSB 0x14 -#define GC_USB_DOEPCTL6_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL6_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL6_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_SNP_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_STALL_LSB 0x15 -#define GC_USB_DOEPCTL6_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL6_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL6_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_STALL_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL6_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL6_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL6_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_CNAK_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL6_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL6_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL6_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_SNAK_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL6_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL6_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL6_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_SETD0PID_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL6_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL6_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL6_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_SETD1PID_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL6_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL6_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL6_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_EPDIS_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL6_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL6_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL6_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_EPENA_OFFSET 0xbc0 -#define GC_USB_DOEPINT6_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT6_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT6_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT6_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT6_XFERCOMPL_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT6_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT6_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT6_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT6_EPDISBLD_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT6_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT6_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT6_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT6_AHBERR_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_SETUP_LSB 0x3 -#define GC_USB_DOEPINT6_SETUP_MASK 0x8 -#define GC_USB_DOEPINT6_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT6_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT6_SETUP_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT6_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT6_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT6_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT6_OUTTKNEPDIS_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT6_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT6_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT6_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT6_STSPHSERCVD_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT6_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT6_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT6_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT6_BACK2BACKSETUP_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT6_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT6_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT6_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT6_OUTPKTERR_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT6_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT6_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT6_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT6_BNAINTR_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT6_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT6_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT6_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT6_PKTDRPSTS_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT6_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT6_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT6_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT6_BBLEERR_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT6_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT6_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT6_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT6_NAKINTRPT_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT6_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT6_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT6_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT6_NYETINTRPT_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT6_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT6_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT6_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT6_STUPPKTRCVD_OFFSET 0xbc8 -#define GC_USB_DOEPTSIZ6_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ6_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ6_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ6_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ6_XFERSIZE_OFFSET 0xbd0 -#define GC_USB_DOEPTSIZ6_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ6_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ6_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ6_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ6_PKTCNT_OFFSET 0xbd0 -#define GC_USB_DOEPTSIZ6_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ6_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ6_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ6_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ6_RXDPID_OFFSET 0xbd0 -#define GC_USB_DOEPDMA6_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA6_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA6_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA6_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA6_DMAADDR_OFFSET 0xbd4 -#define GC_USB_DOEPDMAB6_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB6_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB6_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB6_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB6_DMABUFFERADDR_OFFSET 0xbdc -#define GC_USB_DOEPCTL7_MPS_LSB 0x0 -#define GC_USB_DOEPCTL7_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL7_MPS_SIZE 0xb -#define GC_USB_DOEPCTL7_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_MPS_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL7_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL7_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL7_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_USBACTEP_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_DPID_LSB 0x10 -#define GC_USB_DOEPCTL7_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL7_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL7_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_DPID_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL7_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL7_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL7_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_NAKSTS_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL7_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL7_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL7_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_EPTYPE_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_SNP_LSB 0x14 -#define GC_USB_DOEPCTL7_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL7_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL7_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_SNP_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_STALL_LSB 0x15 -#define GC_USB_DOEPCTL7_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL7_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL7_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_STALL_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL7_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL7_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL7_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_CNAK_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL7_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL7_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL7_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_SNAK_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL7_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL7_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL7_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_SETD0PID_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL7_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL7_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL7_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_SETD1PID_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL7_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL7_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL7_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_EPDIS_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL7_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL7_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL7_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_EPENA_OFFSET 0xbe0 -#define GC_USB_DOEPINT7_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT7_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT7_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT7_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT7_XFERCOMPL_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT7_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT7_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT7_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT7_EPDISBLD_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT7_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT7_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT7_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT7_AHBERR_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_SETUP_LSB 0x3 -#define GC_USB_DOEPINT7_SETUP_MASK 0x8 -#define GC_USB_DOEPINT7_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT7_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT7_SETUP_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT7_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT7_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT7_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT7_OUTTKNEPDIS_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT7_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT7_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT7_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT7_STSPHSERCVD_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT7_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT7_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT7_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT7_BACK2BACKSETUP_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT7_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT7_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT7_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT7_OUTPKTERR_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT7_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT7_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT7_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT7_BNAINTR_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT7_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT7_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT7_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT7_PKTDRPSTS_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT7_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT7_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT7_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT7_BBLEERR_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT7_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT7_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT7_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT7_NAKINTRPT_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT7_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT7_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT7_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT7_NYETINTRPT_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT7_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT7_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT7_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT7_STUPPKTRCVD_OFFSET 0xbe8 -#define GC_USB_DOEPTSIZ7_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ7_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ7_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ7_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ7_XFERSIZE_OFFSET 0xbf0 -#define GC_USB_DOEPTSIZ7_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ7_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ7_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ7_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ7_PKTCNT_OFFSET 0xbf0 -#define GC_USB_DOEPTSIZ7_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ7_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ7_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ7_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ7_RXDPID_OFFSET 0xbf0 -#define GC_USB_DOEPDMA7_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA7_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA7_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA7_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA7_DMAADDR_OFFSET 0xbf4 -#define GC_USB_DOEPDMAB7_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB7_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB7_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB7_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB7_DMABUFFERADDR_OFFSET 0xbfc -#define GC_USB_DOEPCTL8_MPS_LSB 0x0 -#define GC_USB_DOEPCTL8_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL8_MPS_SIZE 0xb -#define GC_USB_DOEPCTL8_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_MPS_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL8_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL8_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL8_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_USBACTEP_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_DPID_LSB 0x10 -#define GC_USB_DOEPCTL8_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL8_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL8_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_DPID_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL8_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL8_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL8_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_NAKSTS_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL8_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL8_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL8_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_EPTYPE_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_SNP_LSB 0x14 -#define GC_USB_DOEPCTL8_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL8_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL8_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_SNP_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_STALL_LSB 0x15 -#define GC_USB_DOEPCTL8_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL8_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL8_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_STALL_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL8_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL8_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL8_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_CNAK_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL8_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL8_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL8_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_SNAK_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL8_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL8_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL8_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_SETD0PID_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL8_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL8_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL8_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_SETD1PID_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL8_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL8_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL8_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_EPDIS_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL8_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL8_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL8_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_EPENA_OFFSET 0xc00 -#define GC_USB_DOEPINT8_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT8_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT8_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT8_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT8_XFERCOMPL_OFFSET 0xc08 -#define GC_USB_DOEPINT8_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT8_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT8_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT8_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT8_EPDISBLD_OFFSET 0xc08 -#define GC_USB_DOEPINT8_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT8_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT8_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT8_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT8_AHBERR_OFFSET 0xc08 -#define GC_USB_DOEPINT8_SETUP_LSB 0x3 -#define GC_USB_DOEPINT8_SETUP_MASK 0x8 -#define GC_USB_DOEPINT8_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT8_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT8_SETUP_OFFSET 0xc08 -#define GC_USB_DOEPINT8_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT8_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT8_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT8_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT8_OUTTKNEPDIS_OFFSET 0xc08 -#define GC_USB_DOEPINT8_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT8_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT8_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT8_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT8_STSPHSERCVD_OFFSET 0xc08 -#define GC_USB_DOEPINT8_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT8_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT8_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT8_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT8_BACK2BACKSETUP_OFFSET 0xc08 -#define GC_USB_DOEPINT8_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT8_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT8_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT8_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT8_OUTPKTERR_OFFSET 0xc08 -#define GC_USB_DOEPINT8_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT8_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT8_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT8_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT8_BNAINTR_OFFSET 0xc08 -#define GC_USB_DOEPINT8_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT8_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT8_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT8_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT8_PKTDRPSTS_OFFSET 0xc08 -#define GC_USB_DOEPINT8_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT8_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT8_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT8_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT8_BBLEERR_OFFSET 0xc08 -#define GC_USB_DOEPINT8_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT8_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT8_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT8_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT8_NAKINTRPT_OFFSET 0xc08 -#define GC_USB_DOEPINT8_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT8_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT8_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT8_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT8_NYETINTRPT_OFFSET 0xc08 -#define GC_USB_DOEPINT8_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT8_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT8_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT8_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT8_STUPPKTRCVD_OFFSET 0xc08 -#define GC_USB_DOEPTSIZ8_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ8_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ8_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ8_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ8_XFERSIZE_OFFSET 0xc10 -#define GC_USB_DOEPTSIZ8_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ8_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ8_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ8_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ8_PKTCNT_OFFSET 0xc10 -#define GC_USB_DOEPTSIZ8_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ8_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ8_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ8_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ8_RXDPID_OFFSET 0xc10 -#define GC_USB_DOEPDMA8_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA8_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA8_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA8_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA8_DMAADDR_OFFSET 0xc14 -#define GC_USB_DOEPDMAB8_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB8_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB8_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB8_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB8_DMABUFFERADDR_OFFSET 0xc1c -#define GC_USB_DOEPCTL9_MPS_LSB 0x0 -#define GC_USB_DOEPCTL9_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL9_MPS_SIZE 0xb -#define GC_USB_DOEPCTL9_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_MPS_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL9_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL9_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL9_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_USBACTEP_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_DPID_LSB 0x10 -#define GC_USB_DOEPCTL9_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL9_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL9_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_DPID_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL9_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL9_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL9_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_NAKSTS_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL9_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL9_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL9_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_EPTYPE_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_SNP_LSB 0x14 -#define GC_USB_DOEPCTL9_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL9_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL9_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_SNP_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_STALL_LSB 0x15 -#define GC_USB_DOEPCTL9_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL9_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL9_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_STALL_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL9_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL9_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL9_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_CNAK_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL9_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL9_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL9_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_SNAK_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL9_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL9_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL9_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_SETD0PID_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL9_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL9_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL9_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_SETD1PID_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL9_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL9_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL9_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_EPDIS_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL9_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL9_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL9_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_EPENA_OFFSET 0xc20 -#define GC_USB_DOEPINT9_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT9_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT9_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT9_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT9_XFERCOMPL_OFFSET 0xc28 -#define GC_USB_DOEPINT9_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT9_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT9_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT9_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT9_EPDISBLD_OFFSET 0xc28 -#define GC_USB_DOEPINT9_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT9_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT9_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT9_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT9_AHBERR_OFFSET 0xc28 -#define GC_USB_DOEPINT9_SETUP_LSB 0x3 -#define GC_USB_DOEPINT9_SETUP_MASK 0x8 -#define GC_USB_DOEPINT9_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT9_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT9_SETUP_OFFSET 0xc28 -#define GC_USB_DOEPINT9_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT9_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT9_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT9_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT9_OUTTKNEPDIS_OFFSET 0xc28 -#define GC_USB_DOEPINT9_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT9_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT9_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT9_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT9_STSPHSERCVD_OFFSET 0xc28 -#define GC_USB_DOEPINT9_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT9_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT9_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT9_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT9_BACK2BACKSETUP_OFFSET 0xc28 -#define GC_USB_DOEPINT9_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT9_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT9_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT9_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT9_OUTPKTERR_OFFSET 0xc28 -#define GC_USB_DOEPINT9_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT9_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT9_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT9_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT9_BNAINTR_OFFSET 0xc28 -#define GC_USB_DOEPINT9_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT9_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT9_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT9_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT9_PKTDRPSTS_OFFSET 0xc28 -#define GC_USB_DOEPINT9_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT9_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT9_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT9_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT9_BBLEERR_OFFSET 0xc28 -#define GC_USB_DOEPINT9_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT9_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT9_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT9_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT9_NAKINTRPT_OFFSET 0xc28 -#define GC_USB_DOEPINT9_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT9_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT9_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT9_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT9_NYETINTRPT_OFFSET 0xc28 -#define GC_USB_DOEPINT9_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT9_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT9_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT9_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT9_STUPPKTRCVD_OFFSET 0xc28 -#define GC_USB_DOEPTSIZ9_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ9_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ9_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ9_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ9_XFERSIZE_OFFSET 0xc30 -#define GC_USB_DOEPTSIZ9_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ9_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ9_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ9_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ9_PKTCNT_OFFSET 0xc30 -#define GC_USB_DOEPTSIZ9_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ9_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ9_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ9_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ9_RXDPID_OFFSET 0xc30 -#define GC_USB_DOEPDMA9_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA9_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA9_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA9_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA9_DMAADDR_OFFSET 0xc34 -#define GC_USB_DOEPDMAB9_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB9_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB9_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB9_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB9_DMABUFFERADDR_OFFSET 0xc3c -#define GC_USB_DOEPCTL10_MPS_LSB 0x0 -#define GC_USB_DOEPCTL10_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL10_MPS_SIZE 0xb -#define GC_USB_DOEPCTL10_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_MPS_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL10_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL10_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL10_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_USBACTEP_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_DPID_LSB 0x10 -#define GC_USB_DOEPCTL10_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL10_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL10_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_DPID_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL10_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL10_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL10_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_NAKSTS_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL10_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL10_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL10_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_EPTYPE_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_SNP_LSB 0x14 -#define GC_USB_DOEPCTL10_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL10_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL10_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_SNP_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_STALL_LSB 0x15 -#define GC_USB_DOEPCTL10_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL10_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL10_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_STALL_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL10_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL10_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL10_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_CNAK_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL10_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL10_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL10_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_SNAK_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL10_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL10_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL10_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_SETD0PID_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL10_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL10_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL10_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_SETD1PID_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL10_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL10_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL10_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_EPDIS_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL10_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL10_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL10_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_EPENA_OFFSET 0xc40 -#define GC_USB_DOEPINT10_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT10_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT10_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT10_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT10_XFERCOMPL_OFFSET 0xc48 -#define GC_USB_DOEPINT10_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT10_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT10_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT10_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT10_EPDISBLD_OFFSET 0xc48 -#define GC_USB_DOEPINT10_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT10_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT10_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT10_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT10_AHBERR_OFFSET 0xc48 -#define GC_USB_DOEPINT10_SETUP_LSB 0x3 -#define GC_USB_DOEPINT10_SETUP_MASK 0x8 -#define GC_USB_DOEPINT10_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT10_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT10_SETUP_OFFSET 0xc48 -#define GC_USB_DOEPINT10_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT10_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT10_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT10_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT10_OUTTKNEPDIS_OFFSET 0xc48 -#define GC_USB_DOEPINT10_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT10_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT10_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT10_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT10_STSPHSERCVD_OFFSET 0xc48 -#define GC_USB_DOEPINT10_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT10_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT10_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT10_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT10_BACK2BACKSETUP_OFFSET 0xc48 -#define GC_USB_DOEPINT10_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT10_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT10_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT10_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT10_OUTPKTERR_OFFSET 0xc48 -#define GC_USB_DOEPINT10_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT10_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT10_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT10_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT10_BNAINTR_OFFSET 0xc48 -#define GC_USB_DOEPINT10_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT10_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT10_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT10_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT10_PKTDRPSTS_OFFSET 0xc48 -#define GC_USB_DOEPINT10_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT10_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT10_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT10_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT10_BBLEERR_OFFSET 0xc48 -#define GC_USB_DOEPINT10_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT10_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT10_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT10_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT10_NAKINTRPT_OFFSET 0xc48 -#define GC_USB_DOEPINT10_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT10_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT10_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT10_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT10_NYETINTRPT_OFFSET 0xc48 -#define GC_USB_DOEPINT10_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT10_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT10_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT10_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT10_STUPPKTRCVD_OFFSET 0xc48 -#define GC_USB_DOEPTSIZ10_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ10_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ10_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ10_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ10_XFERSIZE_OFFSET 0xc50 -#define GC_USB_DOEPTSIZ10_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ10_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ10_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ10_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ10_PKTCNT_OFFSET 0xc50 -#define GC_USB_DOEPTSIZ10_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ10_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ10_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ10_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ10_RXDPID_OFFSET 0xc50 -#define GC_USB_DOEPDMA10_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA10_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA10_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA10_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA10_DMAADDR_OFFSET 0xc54 -#define GC_USB_DOEPDMAB10_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB10_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB10_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB10_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB10_DMABUFFERADDR_OFFSET 0xc5c -#define GC_USB_DOEPCTL11_MPS_LSB 0x0 -#define GC_USB_DOEPCTL11_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL11_MPS_SIZE 0xb -#define GC_USB_DOEPCTL11_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_MPS_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL11_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL11_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL11_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_USBACTEP_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_DPID_LSB 0x10 -#define GC_USB_DOEPCTL11_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL11_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL11_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_DPID_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL11_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL11_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL11_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_NAKSTS_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL11_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL11_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL11_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_EPTYPE_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_SNP_LSB 0x14 -#define GC_USB_DOEPCTL11_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL11_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL11_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_SNP_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_STALL_LSB 0x15 -#define GC_USB_DOEPCTL11_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL11_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL11_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_STALL_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL11_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL11_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL11_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_CNAK_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL11_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL11_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL11_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_SNAK_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL11_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL11_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL11_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_SETD0PID_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL11_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL11_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL11_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_SETD1PID_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL11_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL11_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL11_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_EPDIS_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL11_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL11_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL11_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_EPENA_OFFSET 0xc60 -#define GC_USB_DOEPINT11_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT11_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT11_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT11_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT11_XFERCOMPL_OFFSET 0xc68 -#define GC_USB_DOEPINT11_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT11_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT11_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT11_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT11_EPDISBLD_OFFSET 0xc68 -#define GC_USB_DOEPINT11_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT11_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT11_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT11_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT11_AHBERR_OFFSET 0xc68 -#define GC_USB_DOEPINT11_SETUP_LSB 0x3 -#define GC_USB_DOEPINT11_SETUP_MASK 0x8 -#define GC_USB_DOEPINT11_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT11_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT11_SETUP_OFFSET 0xc68 -#define GC_USB_DOEPINT11_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT11_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT11_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT11_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT11_OUTTKNEPDIS_OFFSET 0xc68 -#define GC_USB_DOEPINT11_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT11_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT11_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT11_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT11_STSPHSERCVD_OFFSET 0xc68 -#define GC_USB_DOEPINT11_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT11_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT11_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT11_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT11_BACK2BACKSETUP_OFFSET 0xc68 -#define GC_USB_DOEPINT11_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT11_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT11_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT11_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT11_OUTPKTERR_OFFSET 0xc68 -#define GC_USB_DOEPINT11_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT11_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT11_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT11_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT11_BNAINTR_OFFSET 0xc68 -#define GC_USB_DOEPINT11_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT11_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT11_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT11_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT11_PKTDRPSTS_OFFSET 0xc68 -#define GC_USB_DOEPINT11_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT11_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT11_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT11_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT11_BBLEERR_OFFSET 0xc68 -#define GC_USB_DOEPINT11_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT11_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT11_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT11_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT11_NAKINTRPT_OFFSET 0xc68 -#define GC_USB_DOEPINT11_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT11_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT11_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT11_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT11_NYETINTRPT_OFFSET 0xc68 -#define GC_USB_DOEPINT11_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT11_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT11_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT11_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT11_STUPPKTRCVD_OFFSET 0xc68 -#define GC_USB_DOEPTSIZ11_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ11_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ11_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ11_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ11_XFERSIZE_OFFSET 0xc70 -#define GC_USB_DOEPTSIZ11_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ11_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ11_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ11_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ11_PKTCNT_OFFSET 0xc70 -#define GC_USB_DOEPTSIZ11_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ11_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ11_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ11_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ11_RXDPID_OFFSET 0xc70 -#define GC_USB_DOEPDMA11_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA11_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA11_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA11_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA11_DMAADDR_OFFSET 0xc74 -#define GC_USB_DOEPDMAB11_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB11_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB11_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB11_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB11_DMABUFFERADDR_OFFSET 0xc7c -#define GC_USB_DOEPCTL12_MPS_LSB 0x0 -#define GC_USB_DOEPCTL12_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL12_MPS_SIZE 0xb -#define GC_USB_DOEPCTL12_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_MPS_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL12_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL12_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL12_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_USBACTEP_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_DPID_LSB 0x10 -#define GC_USB_DOEPCTL12_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL12_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL12_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_DPID_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL12_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL12_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL12_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_NAKSTS_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL12_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL12_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL12_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_EPTYPE_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_SNP_LSB 0x14 -#define GC_USB_DOEPCTL12_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL12_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL12_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_SNP_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_STALL_LSB 0x15 -#define GC_USB_DOEPCTL12_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL12_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL12_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_STALL_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL12_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL12_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL12_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_CNAK_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL12_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL12_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL12_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_SNAK_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL12_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL12_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL12_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_SETD0PID_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL12_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL12_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL12_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_SETD1PID_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL12_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL12_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL12_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_EPDIS_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL12_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL12_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL12_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_EPENA_OFFSET 0xc80 -#define GC_USB_DOEPINT12_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT12_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT12_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT12_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT12_XFERCOMPL_OFFSET 0xc88 -#define GC_USB_DOEPINT12_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT12_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT12_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT12_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT12_EPDISBLD_OFFSET 0xc88 -#define GC_USB_DOEPINT12_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT12_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT12_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT12_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT12_AHBERR_OFFSET 0xc88 -#define GC_USB_DOEPINT12_SETUP_LSB 0x3 -#define GC_USB_DOEPINT12_SETUP_MASK 0x8 -#define GC_USB_DOEPINT12_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT12_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT12_SETUP_OFFSET 0xc88 -#define GC_USB_DOEPINT12_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT12_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT12_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT12_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT12_OUTTKNEPDIS_OFFSET 0xc88 -#define GC_USB_DOEPINT12_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT12_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT12_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT12_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT12_STSPHSERCVD_OFFSET 0xc88 -#define GC_USB_DOEPINT12_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT12_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT12_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT12_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT12_BACK2BACKSETUP_OFFSET 0xc88 -#define GC_USB_DOEPINT12_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT12_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT12_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT12_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT12_OUTPKTERR_OFFSET 0xc88 -#define GC_USB_DOEPINT12_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT12_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT12_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT12_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT12_BNAINTR_OFFSET 0xc88 -#define GC_USB_DOEPINT12_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT12_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT12_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT12_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT12_PKTDRPSTS_OFFSET 0xc88 -#define GC_USB_DOEPINT12_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT12_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT12_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT12_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT12_BBLEERR_OFFSET 0xc88 -#define GC_USB_DOEPINT12_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT12_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT12_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT12_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT12_NAKINTRPT_OFFSET 0xc88 -#define GC_USB_DOEPINT12_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT12_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT12_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT12_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT12_NYETINTRPT_OFFSET 0xc88 -#define GC_USB_DOEPINT12_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT12_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT12_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT12_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT12_STUPPKTRCVD_OFFSET 0xc88 -#define GC_USB_DOEPTSIZ12_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ12_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ12_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ12_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ12_XFERSIZE_OFFSET 0xc90 -#define GC_USB_DOEPTSIZ12_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ12_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ12_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ12_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ12_PKTCNT_OFFSET 0xc90 -#define GC_USB_DOEPTSIZ12_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ12_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ12_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ12_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ12_RXDPID_OFFSET 0xc90 -#define GC_USB_DOEPDMA12_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA12_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA12_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA12_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA12_DMAADDR_OFFSET 0xc94 -#define GC_USB_DOEPDMAB12_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB12_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB12_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB12_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB12_DMABUFFERADDR_OFFSET 0xc9c -#define GC_USB_DOEPCTL13_MPS_LSB 0x0 -#define GC_USB_DOEPCTL13_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL13_MPS_SIZE 0xb -#define GC_USB_DOEPCTL13_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_MPS_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL13_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL13_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL13_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_USBACTEP_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_DPID_LSB 0x10 -#define GC_USB_DOEPCTL13_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL13_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL13_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_DPID_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL13_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL13_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL13_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_NAKSTS_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL13_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL13_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL13_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_EPTYPE_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_SNP_LSB 0x14 -#define GC_USB_DOEPCTL13_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL13_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL13_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_SNP_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_STALL_LSB 0x15 -#define GC_USB_DOEPCTL13_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL13_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL13_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_STALL_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL13_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL13_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL13_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_CNAK_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL13_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL13_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL13_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_SNAK_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL13_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL13_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL13_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_SETD0PID_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL13_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL13_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL13_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_SETD1PID_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL13_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL13_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL13_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_EPDIS_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL13_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL13_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL13_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_EPENA_OFFSET 0xca0 -#define GC_USB_DOEPINT13_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT13_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT13_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT13_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT13_XFERCOMPL_OFFSET 0xca8 -#define GC_USB_DOEPINT13_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT13_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT13_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT13_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT13_EPDISBLD_OFFSET 0xca8 -#define GC_USB_DOEPINT13_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT13_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT13_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT13_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT13_AHBERR_OFFSET 0xca8 -#define GC_USB_DOEPINT13_SETUP_LSB 0x3 -#define GC_USB_DOEPINT13_SETUP_MASK 0x8 -#define GC_USB_DOEPINT13_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT13_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT13_SETUP_OFFSET 0xca8 -#define GC_USB_DOEPINT13_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT13_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT13_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT13_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT13_OUTTKNEPDIS_OFFSET 0xca8 -#define GC_USB_DOEPINT13_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT13_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT13_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT13_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT13_STSPHSERCVD_OFFSET 0xca8 -#define GC_USB_DOEPINT13_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT13_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT13_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT13_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT13_BACK2BACKSETUP_OFFSET 0xca8 -#define GC_USB_DOEPINT13_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT13_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT13_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT13_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT13_OUTPKTERR_OFFSET 0xca8 -#define GC_USB_DOEPINT13_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT13_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT13_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT13_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT13_BNAINTR_OFFSET 0xca8 -#define GC_USB_DOEPINT13_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT13_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT13_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT13_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT13_PKTDRPSTS_OFFSET 0xca8 -#define GC_USB_DOEPINT13_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT13_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT13_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT13_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT13_BBLEERR_OFFSET 0xca8 -#define GC_USB_DOEPINT13_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT13_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT13_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT13_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT13_NAKINTRPT_OFFSET 0xca8 -#define GC_USB_DOEPINT13_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT13_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT13_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT13_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT13_NYETINTRPT_OFFSET 0xca8 -#define GC_USB_DOEPINT13_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT13_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT13_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT13_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT13_STUPPKTRCVD_OFFSET 0xca8 -#define GC_USB_DOEPTSIZ13_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ13_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ13_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ13_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ13_XFERSIZE_OFFSET 0xcb0 -#define GC_USB_DOEPTSIZ13_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ13_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ13_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ13_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ13_PKTCNT_OFFSET 0xcb0 -#define GC_USB_DOEPTSIZ13_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ13_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ13_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ13_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ13_RXDPID_OFFSET 0xcb0 -#define GC_USB_DOEPDMA13_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA13_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA13_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA13_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA13_DMAADDR_OFFSET 0xcb4 -#define GC_USB_DOEPDMAB13_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB13_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB13_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB13_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB13_DMABUFFERADDR_OFFSET 0xcbc -#define GC_USB_DOEPCTL14_MPS_LSB 0x0 -#define GC_USB_DOEPCTL14_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL14_MPS_SIZE 0xb -#define GC_USB_DOEPCTL14_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_MPS_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL14_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL14_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL14_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_USBACTEP_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_DPID_LSB 0x10 -#define GC_USB_DOEPCTL14_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL14_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL14_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_DPID_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL14_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL14_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL14_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_NAKSTS_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL14_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL14_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL14_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_EPTYPE_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_SNP_LSB 0x14 -#define GC_USB_DOEPCTL14_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL14_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL14_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_SNP_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_STALL_LSB 0x15 -#define GC_USB_DOEPCTL14_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL14_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL14_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_STALL_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL14_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL14_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL14_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_CNAK_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL14_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL14_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL14_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_SNAK_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL14_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL14_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL14_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_SETD0PID_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL14_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL14_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL14_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_SETD1PID_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL14_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL14_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL14_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_EPDIS_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL14_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL14_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL14_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_EPENA_OFFSET 0xcc0 -#define GC_USB_DOEPINT14_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT14_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT14_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT14_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT14_XFERCOMPL_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT14_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT14_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT14_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT14_EPDISBLD_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT14_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT14_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT14_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT14_AHBERR_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_SETUP_LSB 0x3 -#define GC_USB_DOEPINT14_SETUP_MASK 0x8 -#define GC_USB_DOEPINT14_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT14_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT14_SETUP_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT14_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT14_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT14_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT14_OUTTKNEPDIS_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT14_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT14_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT14_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT14_STSPHSERCVD_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT14_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT14_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT14_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT14_BACK2BACKSETUP_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT14_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT14_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT14_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT14_OUTPKTERR_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT14_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT14_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT14_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT14_BNAINTR_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT14_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT14_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT14_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT14_PKTDRPSTS_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT14_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT14_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT14_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT14_BBLEERR_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT14_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT14_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT14_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT14_NAKINTRPT_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT14_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT14_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT14_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT14_NYETINTRPT_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT14_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT14_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT14_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT14_STUPPKTRCVD_OFFSET 0xcc8 -#define GC_USB_DOEPTSIZ14_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ14_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ14_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ14_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ14_XFERSIZE_OFFSET 0xcd0 -#define GC_USB_DOEPTSIZ14_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ14_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ14_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ14_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ14_PKTCNT_OFFSET 0xcd0 -#define GC_USB_DOEPTSIZ14_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ14_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ14_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ14_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ14_RXDPID_OFFSET 0xcd0 -#define GC_USB_DOEPDMA14_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA14_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA14_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA14_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA14_DMAADDR_OFFSET 0xcd4 -#define GC_USB_DOEPDMAB14_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB14_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB14_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB14_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB14_DMABUFFERADDR_OFFSET 0xcdc -#define GC_USB_DOEPCTL15_MPS_LSB 0x0 -#define GC_USB_DOEPCTL15_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL15_MPS_SIZE 0xb -#define GC_USB_DOEPCTL15_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_MPS_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL15_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL15_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL15_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_USBACTEP_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_DPID_LSB 0x10 -#define GC_USB_DOEPCTL15_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL15_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL15_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_DPID_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL15_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL15_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL15_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_NAKSTS_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL15_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL15_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL15_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_EPTYPE_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_SNP_LSB 0x14 -#define GC_USB_DOEPCTL15_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL15_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL15_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_SNP_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_STALL_LSB 0x15 -#define GC_USB_DOEPCTL15_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL15_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL15_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_STALL_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL15_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL15_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL15_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_CNAK_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL15_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL15_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL15_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_SNAK_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL15_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL15_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL15_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_SETD0PID_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL15_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL15_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL15_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_SETD1PID_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL15_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL15_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL15_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_EPDIS_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL15_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL15_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL15_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_EPENA_OFFSET 0xce0 -#define GC_USB_DOEPINT15_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT15_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT15_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT15_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT15_XFERCOMPL_OFFSET 0xce8 -#define GC_USB_DOEPINT15_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT15_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT15_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT15_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT15_EPDISBLD_OFFSET 0xce8 -#define GC_USB_DOEPINT15_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT15_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT15_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT15_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT15_AHBERR_OFFSET 0xce8 -#define GC_USB_DOEPINT15_SETUP_LSB 0x3 -#define GC_USB_DOEPINT15_SETUP_MASK 0x8 -#define GC_USB_DOEPINT15_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT15_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT15_SETUP_OFFSET 0xce8 -#define GC_USB_DOEPINT15_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT15_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT15_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT15_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT15_OUTTKNEPDIS_OFFSET 0xce8 -#define GC_USB_DOEPINT15_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT15_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT15_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT15_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT15_STSPHSERCVD_OFFSET 0xce8 -#define GC_USB_DOEPINT15_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT15_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT15_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT15_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT15_BACK2BACKSETUP_OFFSET 0xce8 -#define GC_USB_DOEPINT15_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT15_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT15_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT15_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT15_OUTPKTERR_OFFSET 0xce8 -#define GC_USB_DOEPINT15_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT15_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT15_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT15_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT15_BNAINTR_OFFSET 0xce8 -#define GC_USB_DOEPINT15_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT15_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT15_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT15_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT15_PKTDRPSTS_OFFSET 0xce8 -#define GC_USB_DOEPINT15_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT15_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT15_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT15_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT15_BBLEERR_OFFSET 0xce8 -#define GC_USB_DOEPINT15_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT15_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT15_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT15_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT15_NAKINTRPT_OFFSET 0xce8 -#define GC_USB_DOEPINT15_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT15_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT15_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT15_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT15_NYETINTRPT_OFFSET 0xce8 -#define GC_USB_DOEPINT15_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT15_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT15_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT15_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT15_STUPPKTRCVD_OFFSET 0xce8 -#define GC_USB_DOEPTSIZ15_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ15_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ15_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ15_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ15_XFERSIZE_OFFSET 0xcf0 -#define GC_USB_DOEPTSIZ15_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ15_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ15_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ15_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ15_PKTCNT_OFFSET 0xcf0 -#define GC_USB_DOEPTSIZ15_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ15_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ15_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ15_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ15_RXDPID_OFFSET 0xcf0 -#define GC_USB_DOEPDMA15_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA15_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA15_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA15_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA15_DMAADDR_OFFSET 0xcf4 -#define GC_USB_DOEPDMAB15_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB15_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB15_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB15_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB15_DMABUFFERADDR_OFFSET 0xcfc -#define GC_USB_PCGCCTL_STOPPCLK_LSB 0x0 -#define GC_USB_PCGCCTL_STOPPCLK_MASK 0x1 -#define GC_USB_PCGCCTL_STOPPCLK_SIZE 0x1 -#define GC_USB_PCGCCTL_STOPPCLK_DEFAULT 0x0 -#define GC_USB_PCGCCTL_STOPPCLK_OFFSET 0xe00 -#define GC_USB_PCGCCTL_GATEHCLK_LSB 0x1 -#define GC_USB_PCGCCTL_GATEHCLK_MASK 0x2 -#define GC_USB_PCGCCTL_GATEHCLK_SIZE 0x1 -#define GC_USB_PCGCCTL_GATEHCLK_DEFAULT 0x0 -#define GC_USB_PCGCCTL_GATEHCLK_OFFSET 0xe00 -#define GC_USB_PCGCCTL_PWRCLMP_LSB 0x2 -#define GC_USB_PCGCCTL_PWRCLMP_MASK 0x4 -#define GC_USB_PCGCCTL_PWRCLMP_SIZE 0x1 -#define GC_USB_PCGCCTL_PWRCLMP_DEFAULT 0x0 -#define GC_USB_PCGCCTL_PWRCLMP_OFFSET 0xe00 -#define GC_USB_PCGCCTL_RSTPDWNMODULE_LSB 0x3 -#define GC_USB_PCGCCTL_RSTPDWNMODULE_MASK 0x8 -#define GC_USB_PCGCCTL_RSTPDWNMODULE_SIZE 0x1 -#define GC_USB_PCGCCTL_RSTPDWNMODULE_DEFAULT 0x0 -#define GC_USB_PCGCCTL_RSTPDWNMODULE_OFFSET 0xe00 -#define GC_USB_PCGCCTL_PHYSLEEP_LSB 0x6 -#define GC_USB_PCGCCTL_PHYSLEEP_MASK 0x40 -#define GC_USB_PCGCCTL_PHYSLEEP_SIZE 0x1 -#define GC_USB_PCGCCTL_PHYSLEEP_DEFAULT 0x0 -#define GC_USB_PCGCCTL_PHYSLEEP_OFFSET 0xe00 -#define GC_USB_PCGCCTL_L1SUSPENDED_LSB 0x7 -#define GC_USB_PCGCCTL_L1SUSPENDED_MASK 0x80 -#define GC_USB_PCGCCTL_L1SUSPENDED_SIZE 0x1 -#define GC_USB_PCGCCTL_L1SUSPENDED_DEFAULT 0x0 -#define GC_USB_PCGCCTL_L1SUSPENDED_OFFSET 0xe00 -#define GC_USB_DFIFO_SIZE 0x1000 - +#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_OFFSET 0xaf8 +#define GC_USB_DIEPDMAB15_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB15_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB15_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB15_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB15_DMABUFFERADDR_OFFSET 0xafc +#define GC_USB_DOEPCTL0_MPS_LSB 0x0 +#define GC_USB_DOEPCTL0_MPS_MASK 0x3 +#define GC_USB_DOEPCTL0_MPS_SIZE 0x2 +#define GC_USB_DOEPCTL0_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_MPS_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL0_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL0_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL0_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_USBACTEP_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL0_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL0_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL0_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_NAKSTS_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL0_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL0_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL0_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_EPTYPE_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_SNP_LSB 0x14 +#define GC_USB_DOEPCTL0_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL0_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL0_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_SNP_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_STALL_LSB 0x15 +#define GC_USB_DOEPCTL0_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL0_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL0_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_STALL_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL0_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL0_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL0_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_CNAK_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL0_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL0_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL0_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_SNAK_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL0_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL0_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL0_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_EPDIS_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL0_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL0_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL0_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_EPENA_OFFSET 0xb00 +#define GC_USB_DOEPINT0_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT0_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT0_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT0_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT0_XFERCOMPL_OFFSET 0xb08 +#define GC_USB_DOEPINT0_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT0_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT0_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT0_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT0_EPDISBLD_OFFSET 0xb08 +#define GC_USB_DOEPINT0_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT0_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT0_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT0_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT0_AHBERR_OFFSET 0xb08 +#define GC_USB_DOEPINT0_SETUP_LSB 0x3 +#define GC_USB_DOEPINT0_SETUP_MASK 0x8 +#define GC_USB_DOEPINT0_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT0_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT0_SETUP_OFFSET 0xb08 +#define GC_USB_DOEPINT0_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT0_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT0_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT0_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT0_OUTTKNEPDIS_OFFSET 0xb08 +#define GC_USB_DOEPINT0_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT0_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT0_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT0_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT0_STSPHSERCVD_OFFSET 0xb08 +#define GC_USB_DOEPINT0_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT0_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT0_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT0_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT0_BACK2BACKSETUP_OFFSET 0xb08 +#define GC_USB_DOEPINT0_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT0_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT0_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT0_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT0_OUTPKTERR_OFFSET 0xb08 +#define GC_USB_DOEPINT0_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT0_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT0_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT0_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT0_BNAINTR_OFFSET 0xb08 +#define GC_USB_DOEPINT0_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT0_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT0_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT0_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT0_PKTDRPSTS_OFFSET 0xb08 +#define GC_USB_DOEPINT0_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT0_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT0_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT0_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT0_BBLEERR_OFFSET 0xb08 +#define GC_USB_DOEPINT0_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT0_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT0_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT0_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT0_NAKINTRPT_OFFSET 0xb08 +#define GC_USB_DOEPINT0_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT0_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT0_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT0_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT0_NYETINTRPT_OFFSET 0xb08 +#define GC_USB_DOEPINT0_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT0_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT0_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT0_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT0_STUPPKTRCVD_OFFSET 0xb08 +#define GC_USB_DOEPTSIZ0_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ0_XFERSIZE_MASK 0x7f +#define GC_USB_DOEPTSIZ0_XFERSIZE_SIZE 0x7 +#define GC_USB_DOEPTSIZ0_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ0_XFERSIZE_OFFSET 0xb10 +#define GC_USB_DOEPTSIZ0_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ0_PKTCNT_MASK 0x80000 +#define GC_USB_DOEPTSIZ0_PKTCNT_SIZE 0x1 +#define GC_USB_DOEPTSIZ0_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ0_PKTCNT_OFFSET 0xb10 +#define GC_USB_DOEPTSIZ0_SUPCNT_LSB 0x1d +#define GC_USB_DOEPTSIZ0_SUPCNT_MASK 0x60000000 +#define GC_USB_DOEPTSIZ0_SUPCNT_SIZE 0x2 +#define GC_USB_DOEPTSIZ0_SUPCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ0_SUPCNT_OFFSET 0xb10 +#define GC_USB_DOEPDMA0_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA0_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA0_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA0_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA0_DMAADDR_OFFSET 0xb14 +#define GC_USB_DOEPDMAB0_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB0_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB0_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB0_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB0_DMABUFFERADDR_OFFSET 0xb1c +#define GC_USB_DOEPCTL1_MPS_LSB 0x0 +#define GC_USB_DOEPCTL1_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL1_MPS_SIZE 0xb +#define GC_USB_DOEPCTL1_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_MPS_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL1_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL1_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL1_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_USBACTEP_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_DPID_LSB 0x10 +#define GC_USB_DOEPCTL1_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL1_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL1_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_DPID_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL1_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL1_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL1_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_NAKSTS_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL1_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL1_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL1_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_EPTYPE_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_SNP_LSB 0x14 +#define GC_USB_DOEPCTL1_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL1_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL1_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_SNP_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_STALL_LSB 0x15 +#define GC_USB_DOEPCTL1_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL1_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL1_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_STALL_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL1_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL1_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL1_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_CNAK_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL1_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL1_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL1_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_SNAK_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL1_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL1_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL1_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_SETD0PID_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL1_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL1_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL1_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_SETD1PID_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL1_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL1_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL1_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_EPDIS_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL1_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL1_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL1_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_EPENA_OFFSET 0xb20 +#define GC_USB_DOEPINT1_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT1_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT1_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT1_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT1_XFERCOMPL_OFFSET 0xb28 +#define GC_USB_DOEPINT1_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT1_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT1_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT1_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT1_EPDISBLD_OFFSET 0xb28 +#define GC_USB_DOEPINT1_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT1_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT1_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT1_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT1_AHBERR_OFFSET 0xb28 +#define GC_USB_DOEPINT1_SETUP_LSB 0x3 +#define GC_USB_DOEPINT1_SETUP_MASK 0x8 +#define GC_USB_DOEPINT1_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT1_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT1_SETUP_OFFSET 0xb28 +#define GC_USB_DOEPINT1_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT1_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT1_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT1_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT1_OUTTKNEPDIS_OFFSET 0xb28 +#define GC_USB_DOEPINT1_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT1_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT1_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT1_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT1_STSPHSERCVD_OFFSET 0xb28 +#define GC_USB_DOEPINT1_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT1_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT1_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT1_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT1_BACK2BACKSETUP_OFFSET 0xb28 +#define GC_USB_DOEPINT1_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT1_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT1_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT1_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT1_OUTPKTERR_OFFSET 0xb28 +#define GC_USB_DOEPINT1_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT1_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT1_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT1_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT1_BNAINTR_OFFSET 0xb28 +#define GC_USB_DOEPINT1_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT1_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT1_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT1_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT1_PKTDRPSTS_OFFSET 0xb28 +#define GC_USB_DOEPINT1_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT1_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT1_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT1_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT1_BBLEERR_OFFSET 0xb28 +#define GC_USB_DOEPINT1_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT1_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT1_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT1_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT1_NAKINTRPT_OFFSET 0xb28 +#define GC_USB_DOEPINT1_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT1_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT1_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT1_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT1_NYETINTRPT_OFFSET 0xb28 +#define GC_USB_DOEPINT1_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT1_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT1_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT1_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT1_STUPPKTRCVD_OFFSET 0xb28 +#define GC_USB_DOEPTSIZ1_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ1_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ1_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ1_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ1_XFERSIZE_OFFSET 0xb30 +#define GC_USB_DOEPTSIZ1_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ1_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ1_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ1_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ1_PKTCNT_OFFSET 0xb30 +#define GC_USB_DOEPTSIZ1_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ1_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ1_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ1_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ1_RXDPID_OFFSET 0xb30 +#define GC_USB_DOEPDMA1_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA1_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA1_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA1_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA1_DMAADDR_OFFSET 0xb34 +#define GC_USB_DOEPDMAB1_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB1_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB1_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB1_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB1_DMABUFFERADDR_OFFSET 0xb3c +#define GC_USB_DOEPCTL2_MPS_LSB 0x0 +#define GC_USB_DOEPCTL2_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL2_MPS_SIZE 0xb +#define GC_USB_DOEPCTL2_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_MPS_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL2_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL2_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL2_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_USBACTEP_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_DPID_LSB 0x10 +#define GC_USB_DOEPCTL2_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL2_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL2_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_DPID_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL2_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL2_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL2_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_NAKSTS_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL2_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL2_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL2_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_EPTYPE_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_SNP_LSB 0x14 +#define GC_USB_DOEPCTL2_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL2_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL2_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_SNP_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_STALL_LSB 0x15 +#define GC_USB_DOEPCTL2_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL2_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL2_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_STALL_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL2_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL2_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL2_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_CNAK_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL2_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL2_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL2_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_SNAK_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL2_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL2_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL2_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_SETD0PID_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL2_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL2_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL2_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_SETD1PID_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL2_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL2_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL2_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_EPDIS_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL2_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL2_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL2_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_EPENA_OFFSET 0xb40 +#define GC_USB_DOEPINT2_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT2_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT2_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT2_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT2_XFERCOMPL_OFFSET 0xb48 +#define GC_USB_DOEPINT2_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT2_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT2_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT2_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT2_EPDISBLD_OFFSET 0xb48 +#define GC_USB_DOEPINT2_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT2_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT2_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT2_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT2_AHBERR_OFFSET 0xb48 +#define GC_USB_DOEPINT2_SETUP_LSB 0x3 +#define GC_USB_DOEPINT2_SETUP_MASK 0x8 +#define GC_USB_DOEPINT2_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT2_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT2_SETUP_OFFSET 0xb48 +#define GC_USB_DOEPINT2_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT2_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT2_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT2_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT2_OUTTKNEPDIS_OFFSET 0xb48 +#define GC_USB_DOEPINT2_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT2_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT2_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT2_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT2_STSPHSERCVD_OFFSET 0xb48 +#define GC_USB_DOEPINT2_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT2_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT2_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT2_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT2_BACK2BACKSETUP_OFFSET 0xb48 +#define GC_USB_DOEPINT2_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT2_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT2_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT2_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT2_OUTPKTERR_OFFSET 0xb48 +#define GC_USB_DOEPINT2_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT2_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT2_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT2_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT2_BNAINTR_OFFSET 0xb48 +#define GC_USB_DOEPINT2_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT2_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT2_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT2_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT2_PKTDRPSTS_OFFSET 0xb48 +#define GC_USB_DOEPINT2_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT2_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT2_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT2_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT2_BBLEERR_OFFSET 0xb48 +#define GC_USB_DOEPINT2_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT2_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT2_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT2_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT2_NAKINTRPT_OFFSET 0xb48 +#define GC_USB_DOEPINT2_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT2_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT2_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT2_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT2_NYETINTRPT_OFFSET 0xb48 +#define GC_USB_DOEPINT2_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT2_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT2_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT2_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT2_STUPPKTRCVD_OFFSET 0xb48 +#define GC_USB_DOEPTSIZ2_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ2_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ2_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ2_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ2_XFERSIZE_OFFSET 0xb50 +#define GC_USB_DOEPTSIZ2_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ2_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ2_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ2_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ2_PKTCNT_OFFSET 0xb50 +#define GC_USB_DOEPTSIZ2_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ2_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ2_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ2_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ2_RXDPID_OFFSET 0xb50 +#define GC_USB_DOEPDMA2_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA2_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA2_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA2_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA2_DMAADDR_OFFSET 0xb54 +#define GC_USB_DOEPDMAB2_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB2_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB2_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB2_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB2_DMABUFFERADDR_OFFSET 0xb5c +#define GC_USB_DOEPCTL3_MPS_LSB 0x0 +#define GC_USB_DOEPCTL3_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL3_MPS_SIZE 0xb +#define GC_USB_DOEPCTL3_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_MPS_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL3_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL3_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL3_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_USBACTEP_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_DPID_LSB 0x10 +#define GC_USB_DOEPCTL3_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL3_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL3_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_DPID_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL3_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL3_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL3_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_NAKSTS_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL3_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL3_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL3_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_EPTYPE_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_SNP_LSB 0x14 +#define GC_USB_DOEPCTL3_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL3_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL3_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_SNP_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_STALL_LSB 0x15 +#define GC_USB_DOEPCTL3_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL3_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL3_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_STALL_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL3_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL3_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL3_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_CNAK_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL3_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL3_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL3_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_SNAK_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL3_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL3_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL3_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_SETD0PID_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL3_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL3_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL3_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_SETD1PID_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL3_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL3_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL3_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_EPDIS_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL3_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL3_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL3_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_EPENA_OFFSET 0xb60 +#define GC_USB_DOEPINT3_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT3_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT3_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT3_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT3_XFERCOMPL_OFFSET 0xb68 +#define GC_USB_DOEPINT3_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT3_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT3_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT3_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT3_EPDISBLD_OFFSET 0xb68 +#define GC_USB_DOEPINT3_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT3_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT3_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT3_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT3_AHBERR_OFFSET 0xb68 +#define GC_USB_DOEPINT3_SETUP_LSB 0x3 +#define GC_USB_DOEPINT3_SETUP_MASK 0x8 +#define GC_USB_DOEPINT3_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT3_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT3_SETUP_OFFSET 0xb68 +#define GC_USB_DOEPINT3_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT3_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT3_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT3_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT3_OUTTKNEPDIS_OFFSET 0xb68 +#define GC_USB_DOEPINT3_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT3_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT3_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT3_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT3_STSPHSERCVD_OFFSET 0xb68 +#define GC_USB_DOEPINT3_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT3_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT3_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT3_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT3_BACK2BACKSETUP_OFFSET 0xb68 +#define GC_USB_DOEPINT3_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT3_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT3_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT3_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT3_OUTPKTERR_OFFSET 0xb68 +#define GC_USB_DOEPINT3_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT3_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT3_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT3_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT3_BNAINTR_OFFSET 0xb68 +#define GC_USB_DOEPINT3_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT3_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT3_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT3_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT3_PKTDRPSTS_OFFSET 0xb68 +#define GC_USB_DOEPINT3_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT3_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT3_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT3_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT3_BBLEERR_OFFSET 0xb68 +#define GC_USB_DOEPINT3_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT3_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT3_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT3_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT3_NAKINTRPT_OFFSET 0xb68 +#define GC_USB_DOEPINT3_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT3_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT3_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT3_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT3_NYETINTRPT_OFFSET 0xb68 +#define GC_USB_DOEPINT3_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT3_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT3_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT3_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT3_STUPPKTRCVD_OFFSET 0xb68 +#define GC_USB_DOEPTSIZ3_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ3_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ3_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ3_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ3_XFERSIZE_OFFSET 0xb70 +#define GC_USB_DOEPTSIZ3_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ3_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ3_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ3_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ3_PKTCNT_OFFSET 0xb70 +#define GC_USB_DOEPTSIZ3_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ3_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ3_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ3_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ3_RXDPID_OFFSET 0xb70 +#define GC_USB_DOEPDMA3_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA3_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA3_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA3_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA3_DMAADDR_OFFSET 0xb74 +#define GC_USB_DOEPDMAB3_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB3_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB3_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB3_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB3_DMABUFFERADDR_OFFSET 0xb7c +#define GC_USB_DOEPCTL4_MPS_LSB 0x0 +#define GC_USB_DOEPCTL4_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL4_MPS_SIZE 0xb +#define GC_USB_DOEPCTL4_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_MPS_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL4_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL4_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL4_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_USBACTEP_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_DPID_LSB 0x10 +#define GC_USB_DOEPCTL4_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL4_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL4_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_DPID_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL4_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL4_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL4_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_NAKSTS_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL4_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL4_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL4_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_EPTYPE_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_SNP_LSB 0x14 +#define GC_USB_DOEPCTL4_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL4_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL4_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_SNP_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_STALL_LSB 0x15 +#define GC_USB_DOEPCTL4_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL4_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL4_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_STALL_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL4_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL4_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL4_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_CNAK_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL4_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL4_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL4_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_SNAK_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL4_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL4_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL4_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_SETD0PID_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL4_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL4_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL4_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_SETD1PID_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL4_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL4_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL4_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_EPDIS_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL4_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL4_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL4_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_EPENA_OFFSET 0xb80 +#define GC_USB_DOEPINT4_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT4_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT4_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT4_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT4_XFERCOMPL_OFFSET 0xb88 +#define GC_USB_DOEPINT4_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT4_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT4_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT4_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT4_EPDISBLD_OFFSET 0xb88 +#define GC_USB_DOEPINT4_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT4_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT4_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT4_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT4_AHBERR_OFFSET 0xb88 +#define GC_USB_DOEPINT4_SETUP_LSB 0x3 +#define GC_USB_DOEPINT4_SETUP_MASK 0x8 +#define GC_USB_DOEPINT4_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT4_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT4_SETUP_OFFSET 0xb88 +#define GC_USB_DOEPINT4_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT4_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT4_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT4_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT4_OUTTKNEPDIS_OFFSET 0xb88 +#define GC_USB_DOEPINT4_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT4_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT4_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT4_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT4_STSPHSERCVD_OFFSET 0xb88 +#define GC_USB_DOEPINT4_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT4_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT4_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT4_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT4_BACK2BACKSETUP_OFFSET 0xb88 +#define GC_USB_DOEPINT4_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT4_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT4_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT4_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT4_OUTPKTERR_OFFSET 0xb88 +#define GC_USB_DOEPINT4_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT4_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT4_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT4_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT4_BNAINTR_OFFSET 0xb88 +#define GC_USB_DOEPINT4_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT4_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT4_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT4_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT4_PKTDRPSTS_OFFSET 0xb88 +#define GC_USB_DOEPINT4_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT4_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT4_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT4_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT4_BBLEERR_OFFSET 0xb88 +#define GC_USB_DOEPINT4_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT4_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT4_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT4_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT4_NAKINTRPT_OFFSET 0xb88 +#define GC_USB_DOEPINT4_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT4_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT4_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT4_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT4_NYETINTRPT_OFFSET 0xb88 +#define GC_USB_DOEPINT4_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT4_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT4_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT4_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT4_STUPPKTRCVD_OFFSET 0xb88 +#define GC_USB_DOEPTSIZ4_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ4_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ4_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ4_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ4_XFERSIZE_OFFSET 0xb90 +#define GC_USB_DOEPTSIZ4_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ4_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ4_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ4_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ4_PKTCNT_OFFSET 0xb90 +#define GC_USB_DOEPTSIZ4_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ4_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ4_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ4_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ4_RXDPID_OFFSET 0xb90 +#define GC_USB_DOEPDMA4_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA4_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA4_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA4_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA4_DMAADDR_OFFSET 0xb94 +#define GC_USB_DOEPDMAB4_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB4_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB4_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB4_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB4_DMABUFFERADDR_OFFSET 0xb9c +#define GC_USB_DOEPCTL5_MPS_LSB 0x0 +#define GC_USB_DOEPCTL5_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL5_MPS_SIZE 0xb +#define GC_USB_DOEPCTL5_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_MPS_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL5_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL5_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL5_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_USBACTEP_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_DPID_LSB 0x10 +#define GC_USB_DOEPCTL5_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL5_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL5_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_DPID_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL5_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL5_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL5_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_NAKSTS_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL5_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL5_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL5_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_EPTYPE_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_SNP_LSB 0x14 +#define GC_USB_DOEPCTL5_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL5_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL5_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_SNP_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_STALL_LSB 0x15 +#define GC_USB_DOEPCTL5_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL5_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL5_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_STALL_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL5_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL5_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL5_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_CNAK_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL5_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL5_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL5_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_SNAK_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL5_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL5_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL5_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_SETD0PID_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL5_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL5_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL5_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_SETD1PID_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL5_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL5_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL5_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_EPDIS_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL5_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL5_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL5_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_EPENA_OFFSET 0xba0 +#define GC_USB_DOEPINT5_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT5_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT5_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT5_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT5_XFERCOMPL_OFFSET 0xba8 +#define GC_USB_DOEPINT5_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT5_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT5_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT5_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT5_EPDISBLD_OFFSET 0xba8 +#define GC_USB_DOEPINT5_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT5_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT5_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT5_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT5_AHBERR_OFFSET 0xba8 +#define GC_USB_DOEPINT5_SETUP_LSB 0x3 +#define GC_USB_DOEPINT5_SETUP_MASK 0x8 +#define GC_USB_DOEPINT5_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT5_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT5_SETUP_OFFSET 0xba8 +#define GC_USB_DOEPINT5_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT5_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT5_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT5_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT5_OUTTKNEPDIS_OFFSET 0xba8 +#define GC_USB_DOEPINT5_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT5_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT5_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT5_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT5_STSPHSERCVD_OFFSET 0xba8 +#define GC_USB_DOEPINT5_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT5_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT5_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT5_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT5_BACK2BACKSETUP_OFFSET 0xba8 +#define GC_USB_DOEPINT5_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT5_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT5_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT5_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT5_OUTPKTERR_OFFSET 0xba8 +#define GC_USB_DOEPINT5_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT5_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT5_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT5_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT5_BNAINTR_OFFSET 0xba8 +#define GC_USB_DOEPINT5_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT5_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT5_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT5_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT5_PKTDRPSTS_OFFSET 0xba8 +#define GC_USB_DOEPINT5_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT5_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT5_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT5_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT5_BBLEERR_OFFSET 0xba8 +#define GC_USB_DOEPINT5_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT5_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT5_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT5_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT5_NAKINTRPT_OFFSET 0xba8 +#define GC_USB_DOEPINT5_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT5_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT5_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT5_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT5_NYETINTRPT_OFFSET 0xba8 +#define GC_USB_DOEPINT5_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT5_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT5_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT5_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT5_STUPPKTRCVD_OFFSET 0xba8 +#define GC_USB_DOEPTSIZ5_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ5_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ5_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ5_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ5_XFERSIZE_OFFSET 0xbb0 +#define GC_USB_DOEPTSIZ5_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ5_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ5_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ5_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ5_PKTCNT_OFFSET 0xbb0 +#define GC_USB_DOEPTSIZ5_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ5_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ5_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ5_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ5_RXDPID_OFFSET 0xbb0 +#define GC_USB_DOEPDMA5_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA5_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA5_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA5_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA5_DMAADDR_OFFSET 0xbb4 +#define GC_USB_DOEPDMAB5_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB5_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB5_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB5_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB5_DMABUFFERADDR_OFFSET 0xbbc +#define GC_USB_DOEPCTL6_MPS_LSB 0x0 +#define GC_USB_DOEPCTL6_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL6_MPS_SIZE 0xb +#define GC_USB_DOEPCTL6_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_MPS_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL6_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL6_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL6_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_USBACTEP_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_DPID_LSB 0x10 +#define GC_USB_DOEPCTL6_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL6_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL6_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_DPID_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL6_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL6_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL6_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_NAKSTS_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL6_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL6_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL6_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_EPTYPE_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_SNP_LSB 0x14 +#define GC_USB_DOEPCTL6_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL6_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL6_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_SNP_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_STALL_LSB 0x15 +#define GC_USB_DOEPCTL6_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL6_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL6_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_STALL_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL6_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL6_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL6_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_CNAK_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL6_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL6_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL6_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_SNAK_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL6_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL6_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL6_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_SETD0PID_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL6_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL6_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL6_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_SETD1PID_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL6_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL6_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL6_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_EPDIS_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL6_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL6_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL6_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_EPENA_OFFSET 0xbc0 +#define GC_USB_DOEPINT6_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT6_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT6_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT6_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT6_XFERCOMPL_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT6_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT6_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT6_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT6_EPDISBLD_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT6_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT6_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT6_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT6_AHBERR_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_SETUP_LSB 0x3 +#define GC_USB_DOEPINT6_SETUP_MASK 0x8 +#define GC_USB_DOEPINT6_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT6_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT6_SETUP_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT6_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT6_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT6_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT6_OUTTKNEPDIS_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT6_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT6_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT6_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT6_STSPHSERCVD_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT6_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT6_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT6_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT6_BACK2BACKSETUP_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT6_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT6_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT6_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT6_OUTPKTERR_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT6_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT6_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT6_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT6_BNAINTR_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT6_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT6_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT6_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT6_PKTDRPSTS_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT6_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT6_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT6_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT6_BBLEERR_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT6_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT6_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT6_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT6_NAKINTRPT_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT6_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT6_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT6_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT6_NYETINTRPT_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT6_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT6_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT6_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT6_STUPPKTRCVD_OFFSET 0xbc8 +#define GC_USB_DOEPTSIZ6_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ6_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ6_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ6_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ6_XFERSIZE_OFFSET 0xbd0 +#define GC_USB_DOEPTSIZ6_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ6_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ6_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ6_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ6_PKTCNT_OFFSET 0xbd0 +#define GC_USB_DOEPTSIZ6_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ6_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ6_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ6_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ6_RXDPID_OFFSET 0xbd0 +#define GC_USB_DOEPDMA6_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA6_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA6_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA6_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA6_DMAADDR_OFFSET 0xbd4 +#define GC_USB_DOEPDMAB6_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB6_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB6_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB6_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB6_DMABUFFERADDR_OFFSET 0xbdc +#define GC_USB_DOEPCTL7_MPS_LSB 0x0 +#define GC_USB_DOEPCTL7_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL7_MPS_SIZE 0xb +#define GC_USB_DOEPCTL7_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_MPS_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL7_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL7_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL7_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_USBACTEP_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_DPID_LSB 0x10 +#define GC_USB_DOEPCTL7_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL7_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL7_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_DPID_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL7_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL7_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL7_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_NAKSTS_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL7_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL7_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL7_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_EPTYPE_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_SNP_LSB 0x14 +#define GC_USB_DOEPCTL7_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL7_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL7_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_SNP_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_STALL_LSB 0x15 +#define GC_USB_DOEPCTL7_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL7_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL7_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_STALL_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL7_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL7_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL7_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_CNAK_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL7_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL7_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL7_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_SNAK_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL7_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL7_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL7_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_SETD0PID_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL7_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL7_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL7_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_SETD1PID_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL7_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL7_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL7_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_EPDIS_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL7_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL7_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL7_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_EPENA_OFFSET 0xbe0 +#define GC_USB_DOEPINT7_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT7_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT7_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT7_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT7_XFERCOMPL_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT7_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT7_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT7_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT7_EPDISBLD_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT7_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT7_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT7_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT7_AHBERR_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_SETUP_LSB 0x3 +#define GC_USB_DOEPINT7_SETUP_MASK 0x8 +#define GC_USB_DOEPINT7_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT7_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT7_SETUP_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT7_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT7_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT7_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT7_OUTTKNEPDIS_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT7_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT7_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT7_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT7_STSPHSERCVD_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT7_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT7_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT7_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT7_BACK2BACKSETUP_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT7_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT7_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT7_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT7_OUTPKTERR_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT7_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT7_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT7_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT7_BNAINTR_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT7_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT7_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT7_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT7_PKTDRPSTS_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT7_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT7_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT7_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT7_BBLEERR_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT7_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT7_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT7_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT7_NAKINTRPT_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT7_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT7_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT7_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT7_NYETINTRPT_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT7_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT7_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT7_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT7_STUPPKTRCVD_OFFSET 0xbe8 +#define GC_USB_DOEPTSIZ7_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ7_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ7_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ7_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ7_XFERSIZE_OFFSET 0xbf0 +#define GC_USB_DOEPTSIZ7_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ7_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ7_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ7_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ7_PKTCNT_OFFSET 0xbf0 +#define GC_USB_DOEPTSIZ7_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ7_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ7_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ7_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ7_RXDPID_OFFSET 0xbf0 +#define GC_USB_DOEPDMA7_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA7_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA7_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA7_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA7_DMAADDR_OFFSET 0xbf4 +#define GC_USB_DOEPDMAB7_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB7_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB7_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB7_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB7_DMABUFFERADDR_OFFSET 0xbfc +#define GC_USB_DOEPCTL8_MPS_LSB 0x0 +#define GC_USB_DOEPCTL8_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL8_MPS_SIZE 0xb +#define GC_USB_DOEPCTL8_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_MPS_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL8_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL8_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL8_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_USBACTEP_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_DPID_LSB 0x10 +#define GC_USB_DOEPCTL8_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL8_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL8_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_DPID_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL8_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL8_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL8_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_NAKSTS_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL8_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL8_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL8_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_EPTYPE_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_SNP_LSB 0x14 +#define GC_USB_DOEPCTL8_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL8_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL8_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_SNP_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_STALL_LSB 0x15 +#define GC_USB_DOEPCTL8_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL8_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL8_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_STALL_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL8_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL8_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL8_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_CNAK_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL8_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL8_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL8_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_SNAK_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL8_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL8_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL8_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_SETD0PID_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL8_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL8_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL8_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_SETD1PID_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL8_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL8_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL8_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_EPDIS_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL8_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL8_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL8_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_EPENA_OFFSET 0xc00 +#define GC_USB_DOEPINT8_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT8_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT8_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT8_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT8_XFERCOMPL_OFFSET 0xc08 +#define GC_USB_DOEPINT8_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT8_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT8_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT8_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT8_EPDISBLD_OFFSET 0xc08 +#define GC_USB_DOEPINT8_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT8_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT8_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT8_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT8_AHBERR_OFFSET 0xc08 +#define GC_USB_DOEPINT8_SETUP_LSB 0x3 +#define GC_USB_DOEPINT8_SETUP_MASK 0x8 +#define GC_USB_DOEPINT8_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT8_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT8_SETUP_OFFSET 0xc08 +#define GC_USB_DOEPINT8_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT8_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT8_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT8_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT8_OUTTKNEPDIS_OFFSET 0xc08 +#define GC_USB_DOEPINT8_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT8_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT8_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT8_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT8_STSPHSERCVD_OFFSET 0xc08 +#define GC_USB_DOEPINT8_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT8_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT8_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT8_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT8_BACK2BACKSETUP_OFFSET 0xc08 +#define GC_USB_DOEPINT8_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT8_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT8_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT8_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT8_OUTPKTERR_OFFSET 0xc08 +#define GC_USB_DOEPINT8_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT8_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT8_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT8_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT8_BNAINTR_OFFSET 0xc08 +#define GC_USB_DOEPINT8_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT8_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT8_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT8_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT8_PKTDRPSTS_OFFSET 0xc08 +#define GC_USB_DOEPINT8_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT8_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT8_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT8_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT8_BBLEERR_OFFSET 0xc08 +#define GC_USB_DOEPINT8_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT8_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT8_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT8_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT8_NAKINTRPT_OFFSET 0xc08 +#define GC_USB_DOEPINT8_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT8_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT8_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT8_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT8_NYETINTRPT_OFFSET 0xc08 +#define GC_USB_DOEPINT8_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT8_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT8_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT8_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT8_STUPPKTRCVD_OFFSET 0xc08 +#define GC_USB_DOEPTSIZ8_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ8_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ8_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ8_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ8_XFERSIZE_OFFSET 0xc10 +#define GC_USB_DOEPTSIZ8_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ8_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ8_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ8_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ8_PKTCNT_OFFSET 0xc10 +#define GC_USB_DOEPTSIZ8_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ8_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ8_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ8_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ8_RXDPID_OFFSET 0xc10 +#define GC_USB_DOEPDMA8_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA8_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA8_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA8_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA8_DMAADDR_OFFSET 0xc14 +#define GC_USB_DOEPDMAB8_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB8_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB8_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB8_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB8_DMABUFFERADDR_OFFSET 0xc1c +#define GC_USB_DOEPCTL9_MPS_LSB 0x0 +#define GC_USB_DOEPCTL9_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL9_MPS_SIZE 0xb +#define GC_USB_DOEPCTL9_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_MPS_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL9_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL9_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL9_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_USBACTEP_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_DPID_LSB 0x10 +#define GC_USB_DOEPCTL9_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL9_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL9_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_DPID_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL9_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL9_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL9_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_NAKSTS_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL9_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL9_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL9_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_EPTYPE_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_SNP_LSB 0x14 +#define GC_USB_DOEPCTL9_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL9_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL9_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_SNP_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_STALL_LSB 0x15 +#define GC_USB_DOEPCTL9_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL9_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL9_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_STALL_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL9_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL9_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL9_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_CNAK_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL9_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL9_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL9_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_SNAK_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL9_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL9_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL9_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_SETD0PID_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL9_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL9_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL9_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_SETD1PID_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL9_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL9_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL9_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_EPDIS_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL9_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL9_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL9_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_EPENA_OFFSET 0xc20 +#define GC_USB_DOEPINT9_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT9_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT9_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT9_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT9_XFERCOMPL_OFFSET 0xc28 +#define GC_USB_DOEPINT9_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT9_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT9_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT9_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT9_EPDISBLD_OFFSET 0xc28 +#define GC_USB_DOEPINT9_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT9_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT9_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT9_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT9_AHBERR_OFFSET 0xc28 +#define GC_USB_DOEPINT9_SETUP_LSB 0x3 +#define GC_USB_DOEPINT9_SETUP_MASK 0x8 +#define GC_USB_DOEPINT9_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT9_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT9_SETUP_OFFSET 0xc28 +#define GC_USB_DOEPINT9_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT9_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT9_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT9_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT9_OUTTKNEPDIS_OFFSET 0xc28 +#define GC_USB_DOEPINT9_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT9_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT9_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT9_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT9_STSPHSERCVD_OFFSET 0xc28 +#define GC_USB_DOEPINT9_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT9_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT9_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT9_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT9_BACK2BACKSETUP_OFFSET 0xc28 +#define GC_USB_DOEPINT9_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT9_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT9_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT9_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT9_OUTPKTERR_OFFSET 0xc28 +#define GC_USB_DOEPINT9_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT9_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT9_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT9_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT9_BNAINTR_OFFSET 0xc28 +#define GC_USB_DOEPINT9_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT9_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT9_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT9_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT9_PKTDRPSTS_OFFSET 0xc28 +#define GC_USB_DOEPINT9_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT9_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT9_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT9_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT9_BBLEERR_OFFSET 0xc28 +#define GC_USB_DOEPINT9_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT9_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT9_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT9_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT9_NAKINTRPT_OFFSET 0xc28 +#define GC_USB_DOEPINT9_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT9_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT9_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT9_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT9_NYETINTRPT_OFFSET 0xc28 +#define GC_USB_DOEPINT9_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT9_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT9_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT9_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT9_STUPPKTRCVD_OFFSET 0xc28 +#define GC_USB_DOEPTSIZ9_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ9_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ9_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ9_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ9_XFERSIZE_OFFSET 0xc30 +#define GC_USB_DOEPTSIZ9_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ9_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ9_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ9_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ9_PKTCNT_OFFSET 0xc30 +#define GC_USB_DOEPTSIZ9_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ9_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ9_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ9_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ9_RXDPID_OFFSET 0xc30 +#define GC_USB_DOEPDMA9_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA9_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA9_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA9_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA9_DMAADDR_OFFSET 0xc34 +#define GC_USB_DOEPDMAB9_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB9_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB9_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB9_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB9_DMABUFFERADDR_OFFSET 0xc3c +#define GC_USB_DOEPCTL10_MPS_LSB 0x0 +#define GC_USB_DOEPCTL10_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL10_MPS_SIZE 0xb +#define GC_USB_DOEPCTL10_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_MPS_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL10_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL10_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL10_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_USBACTEP_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_DPID_LSB 0x10 +#define GC_USB_DOEPCTL10_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL10_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL10_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_DPID_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL10_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL10_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL10_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_NAKSTS_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL10_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL10_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL10_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_EPTYPE_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_SNP_LSB 0x14 +#define GC_USB_DOEPCTL10_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL10_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL10_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_SNP_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_STALL_LSB 0x15 +#define GC_USB_DOEPCTL10_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL10_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL10_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_STALL_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL10_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL10_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL10_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_CNAK_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL10_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL10_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL10_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_SNAK_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL10_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL10_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL10_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_SETD0PID_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL10_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL10_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL10_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_SETD1PID_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL10_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL10_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL10_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_EPDIS_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL10_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL10_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL10_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_EPENA_OFFSET 0xc40 +#define GC_USB_DOEPINT10_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT10_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT10_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT10_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT10_XFERCOMPL_OFFSET 0xc48 +#define GC_USB_DOEPINT10_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT10_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT10_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT10_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT10_EPDISBLD_OFFSET 0xc48 +#define GC_USB_DOEPINT10_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT10_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT10_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT10_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT10_AHBERR_OFFSET 0xc48 +#define GC_USB_DOEPINT10_SETUP_LSB 0x3 +#define GC_USB_DOEPINT10_SETUP_MASK 0x8 +#define GC_USB_DOEPINT10_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT10_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT10_SETUP_OFFSET 0xc48 +#define GC_USB_DOEPINT10_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT10_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT10_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT10_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT10_OUTTKNEPDIS_OFFSET 0xc48 +#define GC_USB_DOEPINT10_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT10_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT10_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT10_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT10_STSPHSERCVD_OFFSET 0xc48 +#define GC_USB_DOEPINT10_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT10_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT10_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT10_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT10_BACK2BACKSETUP_OFFSET 0xc48 +#define GC_USB_DOEPINT10_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT10_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT10_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT10_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT10_OUTPKTERR_OFFSET 0xc48 +#define GC_USB_DOEPINT10_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT10_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT10_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT10_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT10_BNAINTR_OFFSET 0xc48 +#define GC_USB_DOEPINT10_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT10_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT10_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT10_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT10_PKTDRPSTS_OFFSET 0xc48 +#define GC_USB_DOEPINT10_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT10_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT10_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT10_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT10_BBLEERR_OFFSET 0xc48 +#define GC_USB_DOEPINT10_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT10_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT10_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT10_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT10_NAKINTRPT_OFFSET 0xc48 +#define GC_USB_DOEPINT10_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT10_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT10_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT10_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT10_NYETINTRPT_OFFSET 0xc48 +#define GC_USB_DOEPINT10_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT10_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT10_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT10_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT10_STUPPKTRCVD_OFFSET 0xc48 +#define GC_USB_DOEPTSIZ10_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ10_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ10_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ10_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ10_XFERSIZE_OFFSET 0xc50 +#define GC_USB_DOEPTSIZ10_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ10_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ10_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ10_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ10_PKTCNT_OFFSET 0xc50 +#define GC_USB_DOEPTSIZ10_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ10_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ10_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ10_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ10_RXDPID_OFFSET 0xc50 +#define GC_USB_DOEPDMA10_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA10_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA10_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA10_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA10_DMAADDR_OFFSET 0xc54 +#define GC_USB_DOEPDMAB10_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB10_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB10_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB10_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB10_DMABUFFERADDR_OFFSET 0xc5c +#define GC_USB_DOEPCTL11_MPS_LSB 0x0 +#define GC_USB_DOEPCTL11_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL11_MPS_SIZE 0xb +#define GC_USB_DOEPCTL11_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_MPS_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL11_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL11_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL11_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_USBACTEP_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_DPID_LSB 0x10 +#define GC_USB_DOEPCTL11_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL11_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL11_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_DPID_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL11_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL11_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL11_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_NAKSTS_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL11_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL11_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL11_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_EPTYPE_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_SNP_LSB 0x14 +#define GC_USB_DOEPCTL11_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL11_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL11_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_SNP_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_STALL_LSB 0x15 +#define GC_USB_DOEPCTL11_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL11_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL11_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_STALL_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL11_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL11_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL11_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_CNAK_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL11_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL11_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL11_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_SNAK_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL11_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL11_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL11_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_SETD0PID_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL11_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL11_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL11_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_SETD1PID_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL11_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL11_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL11_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_EPDIS_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL11_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL11_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL11_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_EPENA_OFFSET 0xc60 +#define GC_USB_DOEPINT11_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT11_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT11_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT11_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT11_XFERCOMPL_OFFSET 0xc68 +#define GC_USB_DOEPINT11_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT11_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT11_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT11_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT11_EPDISBLD_OFFSET 0xc68 +#define GC_USB_DOEPINT11_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT11_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT11_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT11_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT11_AHBERR_OFFSET 0xc68 +#define GC_USB_DOEPINT11_SETUP_LSB 0x3 +#define GC_USB_DOEPINT11_SETUP_MASK 0x8 +#define GC_USB_DOEPINT11_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT11_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT11_SETUP_OFFSET 0xc68 +#define GC_USB_DOEPINT11_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT11_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT11_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT11_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT11_OUTTKNEPDIS_OFFSET 0xc68 +#define GC_USB_DOEPINT11_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT11_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT11_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT11_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT11_STSPHSERCVD_OFFSET 0xc68 +#define GC_USB_DOEPINT11_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT11_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT11_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT11_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT11_BACK2BACKSETUP_OFFSET 0xc68 +#define GC_USB_DOEPINT11_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT11_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT11_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT11_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT11_OUTPKTERR_OFFSET 0xc68 +#define GC_USB_DOEPINT11_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT11_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT11_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT11_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT11_BNAINTR_OFFSET 0xc68 +#define GC_USB_DOEPINT11_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT11_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT11_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT11_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT11_PKTDRPSTS_OFFSET 0xc68 +#define GC_USB_DOEPINT11_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT11_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT11_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT11_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT11_BBLEERR_OFFSET 0xc68 +#define GC_USB_DOEPINT11_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT11_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT11_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT11_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT11_NAKINTRPT_OFFSET 0xc68 +#define GC_USB_DOEPINT11_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT11_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT11_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT11_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT11_NYETINTRPT_OFFSET 0xc68 +#define GC_USB_DOEPINT11_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT11_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT11_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT11_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT11_STUPPKTRCVD_OFFSET 0xc68 +#define GC_USB_DOEPTSIZ11_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ11_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ11_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ11_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ11_XFERSIZE_OFFSET 0xc70 +#define GC_USB_DOEPTSIZ11_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ11_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ11_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ11_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ11_PKTCNT_OFFSET 0xc70 +#define GC_USB_DOEPTSIZ11_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ11_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ11_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ11_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ11_RXDPID_OFFSET 0xc70 +#define GC_USB_DOEPDMA11_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA11_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA11_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA11_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA11_DMAADDR_OFFSET 0xc74 +#define GC_USB_DOEPDMAB11_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB11_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB11_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB11_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB11_DMABUFFERADDR_OFFSET 0xc7c +#define GC_USB_DOEPCTL12_MPS_LSB 0x0 +#define GC_USB_DOEPCTL12_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL12_MPS_SIZE 0xb +#define GC_USB_DOEPCTL12_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_MPS_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL12_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL12_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL12_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_USBACTEP_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_DPID_LSB 0x10 +#define GC_USB_DOEPCTL12_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL12_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL12_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_DPID_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL12_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL12_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL12_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_NAKSTS_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL12_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL12_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL12_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_EPTYPE_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_SNP_LSB 0x14 +#define GC_USB_DOEPCTL12_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL12_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL12_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_SNP_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_STALL_LSB 0x15 +#define GC_USB_DOEPCTL12_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL12_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL12_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_STALL_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL12_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL12_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL12_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_CNAK_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL12_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL12_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL12_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_SNAK_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL12_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL12_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL12_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_SETD0PID_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL12_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL12_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL12_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_SETD1PID_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL12_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL12_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL12_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_EPDIS_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL12_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL12_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL12_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_EPENA_OFFSET 0xc80 +#define GC_USB_DOEPINT12_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT12_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT12_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT12_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT12_XFERCOMPL_OFFSET 0xc88 +#define GC_USB_DOEPINT12_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT12_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT12_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT12_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT12_EPDISBLD_OFFSET 0xc88 +#define GC_USB_DOEPINT12_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT12_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT12_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT12_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT12_AHBERR_OFFSET 0xc88 +#define GC_USB_DOEPINT12_SETUP_LSB 0x3 +#define GC_USB_DOEPINT12_SETUP_MASK 0x8 +#define GC_USB_DOEPINT12_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT12_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT12_SETUP_OFFSET 0xc88 +#define GC_USB_DOEPINT12_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT12_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT12_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT12_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT12_OUTTKNEPDIS_OFFSET 0xc88 +#define GC_USB_DOEPINT12_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT12_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT12_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT12_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT12_STSPHSERCVD_OFFSET 0xc88 +#define GC_USB_DOEPINT12_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT12_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT12_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT12_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT12_BACK2BACKSETUP_OFFSET 0xc88 +#define GC_USB_DOEPINT12_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT12_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT12_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT12_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT12_OUTPKTERR_OFFSET 0xc88 +#define GC_USB_DOEPINT12_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT12_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT12_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT12_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT12_BNAINTR_OFFSET 0xc88 +#define GC_USB_DOEPINT12_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT12_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT12_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT12_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT12_PKTDRPSTS_OFFSET 0xc88 +#define GC_USB_DOEPINT12_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT12_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT12_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT12_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT12_BBLEERR_OFFSET 0xc88 +#define GC_USB_DOEPINT12_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT12_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT12_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT12_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT12_NAKINTRPT_OFFSET 0xc88 +#define GC_USB_DOEPINT12_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT12_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT12_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT12_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT12_NYETINTRPT_OFFSET 0xc88 +#define GC_USB_DOEPINT12_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT12_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT12_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT12_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT12_STUPPKTRCVD_OFFSET 0xc88 +#define GC_USB_DOEPTSIZ12_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ12_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ12_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ12_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ12_XFERSIZE_OFFSET 0xc90 +#define GC_USB_DOEPTSIZ12_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ12_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ12_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ12_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ12_PKTCNT_OFFSET 0xc90 +#define GC_USB_DOEPTSIZ12_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ12_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ12_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ12_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ12_RXDPID_OFFSET 0xc90 +#define GC_USB_DOEPDMA12_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA12_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA12_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA12_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA12_DMAADDR_OFFSET 0xc94 +#define GC_USB_DOEPDMAB12_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB12_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB12_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB12_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB12_DMABUFFERADDR_OFFSET 0xc9c +#define GC_USB_DOEPCTL13_MPS_LSB 0x0 +#define GC_USB_DOEPCTL13_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL13_MPS_SIZE 0xb +#define GC_USB_DOEPCTL13_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_MPS_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL13_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL13_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL13_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_USBACTEP_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_DPID_LSB 0x10 +#define GC_USB_DOEPCTL13_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL13_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL13_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_DPID_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL13_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL13_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL13_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_NAKSTS_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL13_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL13_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL13_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_EPTYPE_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_SNP_LSB 0x14 +#define GC_USB_DOEPCTL13_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL13_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL13_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_SNP_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_STALL_LSB 0x15 +#define GC_USB_DOEPCTL13_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL13_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL13_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_STALL_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL13_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL13_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL13_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_CNAK_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL13_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL13_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL13_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_SNAK_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL13_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL13_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL13_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_SETD0PID_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL13_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL13_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL13_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_SETD1PID_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL13_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL13_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL13_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_EPDIS_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL13_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL13_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL13_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_EPENA_OFFSET 0xca0 +#define GC_USB_DOEPINT13_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT13_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT13_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT13_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT13_XFERCOMPL_OFFSET 0xca8 +#define GC_USB_DOEPINT13_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT13_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT13_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT13_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT13_EPDISBLD_OFFSET 0xca8 +#define GC_USB_DOEPINT13_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT13_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT13_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT13_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT13_AHBERR_OFFSET 0xca8 +#define GC_USB_DOEPINT13_SETUP_LSB 0x3 +#define GC_USB_DOEPINT13_SETUP_MASK 0x8 +#define GC_USB_DOEPINT13_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT13_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT13_SETUP_OFFSET 0xca8 +#define GC_USB_DOEPINT13_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT13_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT13_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT13_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT13_OUTTKNEPDIS_OFFSET 0xca8 +#define GC_USB_DOEPINT13_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT13_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT13_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT13_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT13_STSPHSERCVD_OFFSET 0xca8 +#define GC_USB_DOEPINT13_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT13_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT13_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT13_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT13_BACK2BACKSETUP_OFFSET 0xca8 +#define GC_USB_DOEPINT13_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT13_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT13_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT13_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT13_OUTPKTERR_OFFSET 0xca8 +#define GC_USB_DOEPINT13_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT13_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT13_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT13_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT13_BNAINTR_OFFSET 0xca8 +#define GC_USB_DOEPINT13_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT13_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT13_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT13_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT13_PKTDRPSTS_OFFSET 0xca8 +#define GC_USB_DOEPINT13_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT13_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT13_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT13_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT13_BBLEERR_OFFSET 0xca8 +#define GC_USB_DOEPINT13_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT13_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT13_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT13_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT13_NAKINTRPT_OFFSET 0xca8 +#define GC_USB_DOEPINT13_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT13_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT13_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT13_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT13_NYETINTRPT_OFFSET 0xca8 +#define GC_USB_DOEPINT13_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT13_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT13_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT13_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT13_STUPPKTRCVD_OFFSET 0xca8 +#define GC_USB_DOEPTSIZ13_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ13_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ13_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ13_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ13_XFERSIZE_OFFSET 0xcb0 +#define GC_USB_DOEPTSIZ13_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ13_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ13_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ13_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ13_PKTCNT_OFFSET 0xcb0 +#define GC_USB_DOEPTSIZ13_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ13_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ13_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ13_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ13_RXDPID_OFFSET 0xcb0 +#define GC_USB_DOEPDMA13_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA13_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA13_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA13_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA13_DMAADDR_OFFSET 0xcb4 +#define GC_USB_DOEPDMAB13_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB13_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB13_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB13_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB13_DMABUFFERADDR_OFFSET 0xcbc +#define GC_USB_DOEPCTL14_MPS_LSB 0x0 +#define GC_USB_DOEPCTL14_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL14_MPS_SIZE 0xb +#define GC_USB_DOEPCTL14_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_MPS_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL14_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL14_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL14_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_USBACTEP_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_DPID_LSB 0x10 +#define GC_USB_DOEPCTL14_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL14_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL14_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_DPID_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL14_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL14_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL14_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_NAKSTS_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL14_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL14_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL14_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_EPTYPE_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_SNP_LSB 0x14 +#define GC_USB_DOEPCTL14_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL14_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL14_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_SNP_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_STALL_LSB 0x15 +#define GC_USB_DOEPCTL14_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL14_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL14_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_STALL_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL14_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL14_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL14_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_CNAK_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL14_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL14_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL14_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_SNAK_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL14_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL14_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL14_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_SETD0PID_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL14_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL14_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL14_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_SETD1PID_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL14_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL14_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL14_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_EPDIS_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL14_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL14_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL14_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_EPENA_OFFSET 0xcc0 +#define GC_USB_DOEPINT14_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT14_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT14_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT14_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT14_XFERCOMPL_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT14_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT14_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT14_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT14_EPDISBLD_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT14_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT14_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT14_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT14_AHBERR_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_SETUP_LSB 0x3 +#define GC_USB_DOEPINT14_SETUP_MASK 0x8 +#define GC_USB_DOEPINT14_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT14_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT14_SETUP_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT14_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT14_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT14_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT14_OUTTKNEPDIS_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT14_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT14_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT14_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT14_STSPHSERCVD_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT14_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT14_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT14_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT14_BACK2BACKSETUP_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT14_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT14_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT14_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT14_OUTPKTERR_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT14_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT14_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT14_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT14_BNAINTR_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT14_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT14_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT14_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT14_PKTDRPSTS_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT14_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT14_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT14_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT14_BBLEERR_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT14_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT14_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT14_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT14_NAKINTRPT_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT14_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT14_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT14_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT14_NYETINTRPT_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT14_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT14_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT14_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT14_STUPPKTRCVD_OFFSET 0xcc8 +#define GC_USB_DOEPTSIZ14_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ14_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ14_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ14_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ14_XFERSIZE_OFFSET 0xcd0 +#define GC_USB_DOEPTSIZ14_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ14_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ14_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ14_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ14_PKTCNT_OFFSET 0xcd0 +#define GC_USB_DOEPTSIZ14_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ14_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ14_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ14_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ14_RXDPID_OFFSET 0xcd0 +#define GC_USB_DOEPDMA14_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA14_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA14_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA14_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA14_DMAADDR_OFFSET 0xcd4 +#define GC_USB_DOEPDMAB14_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB14_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB14_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB14_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB14_DMABUFFERADDR_OFFSET 0xcdc +#define GC_USB_DOEPCTL15_MPS_LSB 0x0 +#define GC_USB_DOEPCTL15_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL15_MPS_SIZE 0xb +#define GC_USB_DOEPCTL15_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_MPS_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL15_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL15_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL15_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_USBACTEP_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_DPID_LSB 0x10 +#define GC_USB_DOEPCTL15_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL15_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL15_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_DPID_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL15_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL15_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL15_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_NAKSTS_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL15_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL15_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL15_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_EPTYPE_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_SNP_LSB 0x14 +#define GC_USB_DOEPCTL15_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL15_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL15_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_SNP_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_STALL_LSB 0x15 +#define GC_USB_DOEPCTL15_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL15_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL15_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_STALL_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL15_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL15_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL15_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_CNAK_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL15_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL15_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL15_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_SNAK_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL15_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL15_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL15_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_SETD0PID_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL15_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL15_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL15_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_SETD1PID_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL15_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL15_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL15_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_EPDIS_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL15_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL15_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL15_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_EPENA_OFFSET 0xce0 +#define GC_USB_DOEPINT15_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT15_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT15_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT15_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT15_XFERCOMPL_OFFSET 0xce8 +#define GC_USB_DOEPINT15_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT15_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT15_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT15_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT15_EPDISBLD_OFFSET 0xce8 +#define GC_USB_DOEPINT15_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT15_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT15_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT15_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT15_AHBERR_OFFSET 0xce8 +#define GC_USB_DOEPINT15_SETUP_LSB 0x3 +#define GC_USB_DOEPINT15_SETUP_MASK 0x8 +#define GC_USB_DOEPINT15_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT15_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT15_SETUP_OFFSET 0xce8 +#define GC_USB_DOEPINT15_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT15_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT15_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT15_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT15_OUTTKNEPDIS_OFFSET 0xce8 +#define GC_USB_DOEPINT15_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT15_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT15_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT15_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT15_STSPHSERCVD_OFFSET 0xce8 +#define GC_USB_DOEPINT15_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT15_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT15_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT15_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT15_BACK2BACKSETUP_OFFSET 0xce8 +#define GC_USB_DOEPINT15_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT15_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT15_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT15_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT15_OUTPKTERR_OFFSET 0xce8 +#define GC_USB_DOEPINT15_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT15_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT15_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT15_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT15_BNAINTR_OFFSET 0xce8 +#define GC_USB_DOEPINT15_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT15_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT15_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT15_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT15_PKTDRPSTS_OFFSET 0xce8 +#define GC_USB_DOEPINT15_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT15_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT15_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT15_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT15_BBLEERR_OFFSET 0xce8 +#define GC_USB_DOEPINT15_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT15_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT15_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT15_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT15_NAKINTRPT_OFFSET 0xce8 +#define GC_USB_DOEPINT15_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT15_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT15_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT15_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT15_NYETINTRPT_OFFSET 0xce8 +#define GC_USB_DOEPINT15_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT15_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT15_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT15_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT15_STUPPKTRCVD_OFFSET 0xce8 +#define GC_USB_DOEPTSIZ15_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ15_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ15_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ15_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ15_XFERSIZE_OFFSET 0xcf0 +#define GC_USB_DOEPTSIZ15_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ15_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ15_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ15_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ15_PKTCNT_OFFSET 0xcf0 +#define GC_USB_DOEPTSIZ15_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ15_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ15_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ15_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ15_RXDPID_OFFSET 0xcf0 +#define GC_USB_DOEPDMA15_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA15_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA15_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA15_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA15_DMAADDR_OFFSET 0xcf4 +#define GC_USB_DOEPDMAB15_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB15_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB15_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB15_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB15_DMABUFFERADDR_OFFSET 0xcfc +#define GC_USB_PCGCCTL_STOPPCLK_LSB 0x0 +#define GC_USB_PCGCCTL_STOPPCLK_MASK 0x1 +#define GC_USB_PCGCCTL_STOPPCLK_SIZE 0x1 +#define GC_USB_PCGCCTL_STOPPCLK_DEFAULT 0x0 +#define GC_USB_PCGCCTL_STOPPCLK_OFFSET 0xe00 +#define GC_USB_PCGCCTL_GATEHCLK_LSB 0x1 +#define GC_USB_PCGCCTL_GATEHCLK_MASK 0x2 +#define GC_USB_PCGCCTL_GATEHCLK_SIZE 0x1 +#define GC_USB_PCGCCTL_GATEHCLK_DEFAULT 0x0 +#define GC_USB_PCGCCTL_GATEHCLK_OFFSET 0xe00 +#define GC_USB_PCGCCTL_PWRCLMP_LSB 0x2 +#define GC_USB_PCGCCTL_PWRCLMP_MASK 0x4 +#define GC_USB_PCGCCTL_PWRCLMP_SIZE 0x1 +#define GC_USB_PCGCCTL_PWRCLMP_DEFAULT 0x0 +#define GC_USB_PCGCCTL_PWRCLMP_OFFSET 0xe00 +#define GC_USB_PCGCCTL_RSTPDWNMODULE_LSB 0x3 +#define GC_USB_PCGCCTL_RSTPDWNMODULE_MASK 0x8 +#define GC_USB_PCGCCTL_RSTPDWNMODULE_SIZE 0x1 +#define GC_USB_PCGCCTL_RSTPDWNMODULE_DEFAULT 0x0 +#define GC_USB_PCGCCTL_RSTPDWNMODULE_OFFSET 0xe00 +#define GC_USB_PCGCCTL_PHYSLEEP_LSB 0x6 +#define GC_USB_PCGCCTL_PHYSLEEP_MASK 0x40 +#define GC_USB_PCGCCTL_PHYSLEEP_SIZE 0x1 +#define GC_USB_PCGCCTL_PHYSLEEP_DEFAULT 0x0 +#define GC_USB_PCGCCTL_PHYSLEEP_OFFSET 0xe00 +#define GC_USB_PCGCCTL_L1SUSPENDED_LSB 0x7 +#define GC_USB_PCGCCTL_L1SUSPENDED_MASK 0x80 +#define GC_USB_PCGCCTL_L1SUSPENDED_SIZE 0x1 +#define GC_USB_PCGCCTL_L1SUSPENDED_DEFAULT 0x0 +#define GC_USB_PCGCCTL_L1SUSPENDED_OFFSET 0xe00 +#define GC_USB_DFIFO_SIZE 0x1000 #endif /* __CHIP_STM32_USB_DWC_REGISTERS_H */ diff --git a/chip/stm32/usb_dwc_stream.c b/chip/stm32/usb_dwc_stream.c index 2f20d88dda..670c93b437 100644 --- a/chip/stm32/usb_dwc_stream.c +++ b/chip/stm32/usb_dwc_stream.c @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,7 +9,7 @@ #include "util.h" #include "console.h" -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) /* * This function tries to shove new bytes from the USB host into the queue for @@ -24,9 +24,8 @@ int rx_stream_handler(struct usb_stream_config const *config) /* If we have some, try to shove them into the queue */ if (rx_count) { - size_t added = QUEUE_ADD_UNITS( - config->producer.queue, config->rx_ram, - rx_count); + size_t added = QUEUE_ADD_UNITS(config->producer.queue, + config->rx_ram, rx_count); if (added != rx_count) { CPRINTF("rx_stream_handler: failed ep%d " "queue %d bytes, accepted %d\n", @@ -60,7 +59,7 @@ int tx_stream_handler(struct usb_stream_config const *config) /* Reset stream */ void usb_stream_event(struct usb_stream_config const *config, - enum usb_ep_event evt) + enum usb_ep_event evt) { if (evt != USB_EVENT_RESET) return; diff --git a/chip/stm32/usb_dwc_stream.h b/chip/stm32/usb_dwc_stream.h index e46e7a929c..7e5e938053 100644 --- a/chip/stm32/usb_dwc_stream.h +++ b/chip/stm32/usb_dwc_stream.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -54,7 +54,6 @@ struct usb_stream_config { extern struct consumer_ops const usb_stream_consumer_ops; extern struct producer_ops const usb_stream_producer_ops; - /* * Convenience macro for defining USB streams and their associated state and * buffers. @@ -92,26 +91,19 @@ extern struct producer_ops const usb_stream_producer_ops; * BUILD_ASSERT(RX_QUEUE.unit_bytes == 1); * BUILD_ASSERT(TX_QUEUE.unit_bytes == 1); */ -#define USB_STREAM_CONFIG_FULL(NAME, \ - INTERFACE, \ - INTERFACE_CLASS, \ - INTERFACE_SUBCLASS, \ - INTERFACE_PROTOCOL, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE) \ - \ - static uint8_t CONCAT2(NAME, _buf_rx_)[RX_SIZE]; \ - static uint8_t CONCAT2(NAME, _buf_tx_)[TX_SIZE]; \ - static int CONCAT2(NAME, _is_reset_); \ - static int CONCAT2(NAME, _overflow_); \ - static void CONCAT2(NAME, _deferred_tx_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_tx_)); \ - static void CONCAT2(NAME, _deferred_rx_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_rx_)); \ +#define USB_STREAM_CONFIG_FULL(NAME, INTERFACE, INTERFACE_CLASS, \ + INTERFACE_SUBCLASS, INTERFACE_PROTOCOL, \ + INTERFACE_NAME, ENDPOINT, RX_SIZE, TX_SIZE, \ + RX_QUEUE, TX_QUEUE) \ + \ + static uint8_t CONCAT2(NAME, _buf_rx_)[RX_SIZE]; \ + static uint8_t CONCAT2(NAME, _buf_tx_)[TX_SIZE]; \ + static int CONCAT2(NAME, _is_reset_); \ + static int CONCAT2(NAME, _overflow_); \ + static void CONCAT2(NAME, _deferred_tx_)(void); \ + DECLARE_DEFERRED(CONCAT2(NAME, _deferred_tx_)); \ + static void CONCAT2(NAME, _deferred_rx_)(void); \ + DECLARE_DEFERRED(CONCAT2(NAME, _deferred_rx_)); \ struct usb_stream_config const NAME = { \ .endpoint = ENDPOINT, \ .is_reset = &CONCAT2(NAME, _is_reset_), \ @@ -130,94 +122,80 @@ extern struct producer_ops const usb_stream_producer_ops; .queue = &RX_QUEUE, \ .ops = &usb_stream_producer_ops, \ }, \ - }; \ - const struct usb_interface_descriptor \ - USB_IFACE_DESC(INTERFACE) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 0, \ - .bNumEndpoints = 2, \ - .bInterfaceClass = INTERFACE_CLASS, \ - .bInterfaceSubClass = INTERFACE_SUBCLASS, \ - .bInterfaceProtocol = INTERFACE_PROTOCOL, \ - .iInterface = INTERFACE_NAME, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 0) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = 0x80 | ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk IN */, \ - .wMaxPacketSize = TX_SIZE, \ - .bInterval = 10, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 1) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk OUT */, \ - .wMaxPacketSize = RX_SIZE, \ - .bInterval = 0, \ - }; \ - static void CONCAT2(NAME, _deferred_tx_)(void) \ - { tx_stream_handler(&NAME); } \ - static void CONCAT2(NAME, _deferred_rx_)(void) \ - { rx_stream_handler(&NAME); } \ - static void CONCAT2(NAME, _ep_tx)(void) \ - { \ - usb_epN_tx(ENDPOINT); \ - } \ - static void CONCAT2(NAME, _ep_rx)(void) \ - { \ - usb_epN_rx(ENDPOINT); \ - } \ - static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt) \ - { \ - usb_stream_event(&NAME, evt); \ - } \ - struct dwc_usb_ep CONCAT2(NAME, _ep_ctl) = { \ - .max_packet = USB_MAX_PACKET_SIZE, \ - .tx_fifo = ENDPOINT, \ - .out_pending = 0, \ - .out_expected = 0, \ - .out_data = 0, \ - .out_databuffer = CONCAT2(NAME, _buf_rx_), \ - .out_databuffer_max = RX_SIZE, \ - .rx_deferred = &CONCAT2(NAME, _deferred_rx__data), \ - .in_packets = 0, \ - .in_pending = 0, \ - .in_data = 0, \ - .in_databuffer = CONCAT2(NAME, _buf_tx_), \ - .in_databuffer_max = TX_SIZE, \ - .tx_deferred = &CONCAT2(NAME, _deferred_tx__data), \ - }; \ - USB_DECLARE_EP(ENDPOINT, \ - CONCAT2(NAME, _ep_tx), \ - CONCAT2(NAME, _ep_rx), \ + }; \ + const struct usb_interface_descriptor USB_IFACE_DESC(INTERFACE) = { \ + .bLength = USB_DT_INTERFACE_SIZE, \ + .bDescriptorType = USB_DT_INTERFACE, \ + .bInterfaceNumber = INTERFACE, \ + .bAlternateSetting = 0, \ + .bNumEndpoints = 2, \ + .bInterfaceClass = INTERFACE_CLASS, \ + .bInterfaceSubClass = INTERFACE_SUBCLASS, \ + .bInterfaceProtocol = INTERFACE_PROTOCOL, \ + .iInterface = INTERFACE_NAME, \ + }; \ + const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 0) = { \ + .bLength = USB_DT_ENDPOINT_SIZE, \ + .bDescriptorType = USB_DT_ENDPOINT, \ + .bEndpointAddress = 0x80 | ENDPOINT, \ + .bmAttributes = 0x02 /* Bulk IN */, \ + .wMaxPacketSize = TX_SIZE, \ + .bInterval = 10, \ + }; \ + const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 1) = { \ + .bLength = USB_DT_ENDPOINT_SIZE, \ + .bDescriptorType = USB_DT_ENDPOINT, \ + .bEndpointAddress = ENDPOINT, \ + .bmAttributes = 0x02 /* Bulk OUT */, \ + .wMaxPacketSize = RX_SIZE, \ + .bInterval = 0, \ + }; \ + static void CONCAT2(NAME, _deferred_tx_)(void) \ + { \ + tx_stream_handler(&NAME); \ + } \ + static void CONCAT2(NAME, _deferred_rx_)(void) \ + { \ + rx_stream_handler(&NAME); \ + } \ + static void CONCAT2(NAME, _ep_tx)(void) \ + { \ + usb_epN_tx(ENDPOINT); \ + } \ + static void CONCAT2(NAME, _ep_rx)(void) \ + { \ + usb_epN_rx(ENDPOINT); \ + } \ + static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt) \ + { \ + usb_stream_event(&NAME, evt); \ + } \ + struct dwc_usb_ep CONCAT2(NAME, _ep_ctl) = { \ + .max_packet = USB_MAX_PACKET_SIZE, \ + .tx_fifo = ENDPOINT, \ + .out_pending = 0, \ + .out_expected = 0, \ + .out_data = 0, \ + .out_databuffer = CONCAT2(NAME, _buf_rx_), \ + .out_databuffer_max = RX_SIZE, \ + .rx_deferred = &CONCAT2(NAME, _deferred_rx__data), \ + .in_packets = 0, \ + .in_pending = 0, \ + .in_data = 0, \ + .in_databuffer = CONCAT2(NAME, _buf_tx_), \ + .in_databuffer_max = TX_SIZE, \ + .tx_deferred = &CONCAT2(NAME, _deferred_tx__data), \ + }; \ + USB_DECLARE_EP(ENDPOINT, CONCAT2(NAME, _ep_tx), CONCAT2(NAME, _ep_rx), \ CONCAT2(NAME, _ep_event)); /* This is a short version for declaring Google serial endpoints */ -#define USB_STREAM_CONFIG(NAME, \ - INTERFACE, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE) \ - USB_STREAM_CONFIG_FULL(NAME, \ - INTERFACE, \ - USB_CLASS_VENDOR_SPEC, \ - USB_SUBCLASS_GOOGLE_SERIAL, \ - USB_PROTOCOL_GOOGLE_SERIAL, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE) +#define USB_STREAM_CONFIG(NAME, INTERFACE, INTERFACE_NAME, ENDPOINT, RX_SIZE, \ + TX_SIZE, RX_QUEUE, TX_QUEUE) \ + USB_STREAM_CONFIG_FULL(NAME, INTERFACE, USB_CLASS_VENDOR_SPEC, \ + USB_SUBCLASS_GOOGLE_SERIAL, \ + USB_PROTOCOL_GOOGLE_SERIAL, INTERFACE_NAME, \ + ENDPOINT, RX_SIZE, TX_SIZE, RX_QUEUE, TX_QUEUE) /* * Handle USB and Queue request in a deferred callback. @@ -232,6 +210,6 @@ int tx_stream_handler(struct usb_stream_config const *config); void usb_stream_tx(struct usb_stream_config const *config); void usb_stream_rx(struct usb_stream_config const *config); void usb_stream_event(struct usb_stream_config const *config, - enum usb_ep_event evt); + enum usb_ep_event evt); #endif /* __CROS_EC_USB_STREAM_H */ diff --git a/chip/stm32/usb_dwc_update.h b/chip/stm32/usb_dwc_update.h index 6d79f3aca9..1d5027a01f 100644 --- a/chip/stm32/usb_dwc_update.h +++ b/chip/stm32/usb_dwc_update.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/stm32/usb_endpoints.c b/chip/stm32/usb_endpoints.c index 7cdff25a6a..b435a88846 100644 --- a/chip/stm32/usb_endpoints.c +++ b/chip/stm32/usb_endpoints.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -12,7 +12,7 @@ #include "usb_hw.h" typedef void (*xfer_func)(void); -typedef void (*evt_func) (enum usb_ep_event evt); +typedef void (*evt_func)(enum usb_ep_event evt); #if defined(CHIP_FAMILY_STM32F4) #define iface_arguments struct usb_setup_packet *req @@ -44,18 +44,18 @@ int iface_undefined(iface_arguments) #define table(type, name, x) x -#define endpoint_tx(number) \ +#define endpoint_tx(number) \ extern void __attribute__((used, weak, alias("ep_undefined"))) \ - ep_ ## number ## _tx(void); -#define endpoint_rx(number) \ + ep_##number##_tx(void); +#define endpoint_rx(number) \ extern void __attribute__((used, weak, alias("ep_undefined"))) \ - ep_ ## number ## _rx(void); -#define endpoint_evt(number) \ + ep_##number##_rx(void); +#define endpoint_evt(number) \ extern void __attribute__((used, weak, alias("ep_evt_undefined"))) \ - ep_ ## number ## _evt(enum usb_ep_event evt); -#define interface(number) \ + ep_##number##_evt(enum usb_ep_event evt); +#define interface(number) \ extern int __attribute__((used, weak, alias("iface_undefined"))) \ - iface_ ## number ## _request(iface_arguments); + iface_##number##_request(iface_arguments); #define null @@ -79,20 +79,23 @@ int iface_undefined(iface_arguments) #endif /* __clang__ */ /* align function pointers on a 32-bit boundary */ -#define table(type, name, x) type name[] __attribute__((aligned(4), section(".rodata.usb_ep." #name ",\"a\" @"))) = { x }; -#define null (void*)0 +#define table(type, name, x) \ + type name[] __attribute__((aligned(4), section(".rodata.usb_ep." #name \ + ",\"a\" @"))) = { x }; +#define null (void *)0 #define ep_(num, suf) CONCAT3(ep_, num, suf) #define ep(num, suf) ep_(num, suf) #define endpoint_tx(number) \ - [number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _tx, + [number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_##number##_tx, #define endpoint_rx(number) \ - [number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _rx, + [number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_##number##_rx, #define endpoint_evt(number) \ - [number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _evt, -#define interface(number) \ - [number < USB_IFACE_COUNT ? number : USB_IFACE_COUNT - 1] = iface_ ## number ## _request, + [number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_##number##_evt, +#define interface(number) \ + [number < USB_IFACE_COUNT ? number : USB_IFACE_COUNT - 1] = \ + iface_##number##_request, #endif /* PASS 2 */ /* @@ -102,73 +105,36 @@ int iface_undefined(iface_arguments) * It all sorts out nicely */ table(xfer_func, usb_ep_tx, - endpoint_tx(15) - endpoint_tx(14) - endpoint_tx(13) - endpoint_tx(12) - endpoint_tx(11) - endpoint_tx(10) - endpoint_tx(9) - endpoint_tx(8) - endpoint_tx(7) - endpoint_tx(6) - endpoint_tx(5) - endpoint_tx(4) - endpoint_tx(3) - endpoint_tx(2) - endpoint_tx(1) - endpoint_tx(0) -) - -table(xfer_func, usb_ep_rx, - endpoint_rx(15) - endpoint_rx(14) - endpoint_rx(13) - endpoint_rx(12) - endpoint_rx(11) - endpoint_rx(10) - endpoint_rx(9) - endpoint_rx(8) - endpoint_rx(7) - endpoint_rx(6) - endpoint_rx(5) - endpoint_rx(4) - endpoint_rx(3) - endpoint_rx(2) - endpoint_rx(1) - endpoint_rx(0) -) - -table(evt_func, usb_ep_event, - endpoint_evt(15) - endpoint_evt(14) - endpoint_evt(13) - endpoint_evt(12) - endpoint_evt(11) - endpoint_evt(10) - endpoint_evt(9) - endpoint_evt(8) - endpoint_evt(7) - endpoint_evt(6) - endpoint_evt(5) - endpoint_evt(4) - endpoint_evt(3) - endpoint_evt(2) - endpoint_evt(1) - endpoint_evt(0) -) + endpoint_tx(15) endpoint_tx(14) endpoint_tx(13) endpoint_tx(12) + endpoint_tx(11) endpoint_tx(10) endpoint_tx(9) endpoint_tx(8) + endpoint_tx(7) endpoint_tx(6) endpoint_tx(5) + endpoint_tx(4) endpoint_tx(3) endpoint_tx(2) + endpoint_tx(1) endpoint_tx(0)) + + table(xfer_func, usb_ep_rx, + endpoint_rx(15) endpoint_rx(14) endpoint_rx(13) endpoint_rx(12) + endpoint_rx(11) endpoint_rx(10) endpoint_rx(9) + endpoint_rx(8) endpoint_rx(7) endpoint_rx(6) + endpoint_rx(5) endpoint_rx(4) + endpoint_rx(3) endpoint_rx(2) + endpoint_rx(1) + endpoint_rx(0)) + + table(evt_func, usb_ep_event, + endpoint_evt(15) endpoint_evt(14) endpoint_evt( + 13) endpoint_evt(12) endpoint_evt(11) + endpoint_evt(10) endpoint_evt(9) endpoint_evt( + 8) endpoint_evt(7) endpoint_evt(6) + endpoint_evt(5) endpoint_evt(4) + endpoint_evt(3) endpoint_evt(2) + endpoint_evt(1) + endpoint_evt(0)) #if USB_IFACE_COUNT > 0 -table(iface_func, usb_iface_request, - interface(7) - interface(6) - interface(5) - interface(4) - interface(3) - interface(2) - interface(1) - interface(0) -) + table(iface_func, usb_iface_request, + interface(7) interface(6) interface(5) + interface(4) interface(3) interface(2) + interface(1) interface(0)) #endif #if PASS == 2 diff --git a/chip/stm32/usb_gpio.c b/chip/stm32/usb_gpio.c index 64d46875b5..a0655fd045 100644 --- a/chip/stm32/usb_gpio.c +++ b/chip/stm32/usb_gpio.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,8 +11,8 @@ void usb_gpio_tx(struct usb_gpio_config const *config) { - size_t i; - uint32_t mask = 1; + size_t i; + uint32_t mask = 1; uint32_t value = 0; for (i = 0; i < config->num_gpios; ++i, mask <<= 1) @@ -31,12 +31,12 @@ void usb_gpio_tx(struct usb_gpio_config const *config) void usb_gpio_rx(struct usb_gpio_config const *config) { - size_t i; - uint32_t mask = 1; - uint32_t set_mask = ((uint32_t)(config->rx_ram[0]) | - (uint32_t)(config->rx_ram[1]) << 16); - uint32_t clear_mask = ((uint32_t)(config->rx_ram[2]) | - (uint32_t)(config->rx_ram[3]) << 16); + size_t i; + uint32_t mask = 1; + uint32_t set_mask = ((uint32_t)(config->rx_ram[0]) | + (uint32_t)(config->rx_ram[1]) << 16); + uint32_t clear_mask = ((uint32_t)(config->rx_ram[2]) | + (uint32_t)(config->rx_ram[3]) << 16); uint32_t ignore_mask = set_mask & clear_mask; config->state->set_mask = set_mask; @@ -69,10 +69,10 @@ void usb_gpio_event(struct usb_gpio_config const *config, enum usb_ep_event evt) i = config->endpoint; - btable_ep[i].tx_addr = usb_sram_addr(config->tx_ram); + btable_ep[i].tx_addr = usb_sram_addr(config->tx_ram); btable_ep[i].tx_count = USB_GPIO_TX_PACKET_SIZE; - btable_ep[i].rx_addr = usb_sram_addr(config->rx_ram); + btable_ep[i].rx_addr = usb_sram_addr(config->rx_ram); btable_ep[i].rx_count = ((USB_GPIO_RX_PACKET_SIZE / 2) << 10); /* @@ -82,8 +82,8 @@ void usb_gpio_event(struct usb_gpio_config const *config, enum usb_ep_event evt) config->tx_ram[0] = 0; config->tx_ram[1] = 0; - STM32_USB_EP(i) = ((i << 0) | /* Endpoint Addr*/ - (3 << 4) | /* TX Valid */ - (0 << 9) | /* Bulk EP */ + STM32_USB_EP(i) = ((i << 0) | /* Endpoint Addr*/ + (3 << 4) | /* TX Valid */ + (0 << 9) | /* Bulk EP */ (3 << 12)); /* RX Valid */ } diff --git a/chip/stm32/usb_gpio.h b/chip/stm32/usb_gpio.h index b27c7f9485..a54801048b 100644 --- a/chip/stm32/usb_gpio.h +++ b/chip/stm32/usb_gpio.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -55,69 +55,62 @@ struct usb_gpio_config { * ENDPOINT is the index of the USB bulk endpoint used for receiving and * transmitting bytes. */ -#define USB_GPIO_CONFIG(NAME, \ - GPIO_LIST, \ - INTERFACE, \ - ENDPOINT) \ - BUILD_ASSERT(ARRAY_SIZE(GPIO_LIST) <= 32); \ - static usb_uint CONCAT2(NAME, _ep_rx_buffer)[USB_GPIO_RX_PACKET_SIZE / 2] __usb_ram; \ - static usb_uint CONCAT2(NAME, _ep_tx_buffer)[USB_GPIO_TX_PACKET_SIZE / 2] __usb_ram; \ - struct usb_gpio_config const NAME = { \ - .state = &((struct usb_gpio_state){}), \ - .endpoint = ENDPOINT, \ - .rx_ram = CONCAT2(NAME, _ep_rx_buffer), \ - .tx_ram = CONCAT2(NAME, _ep_tx_buffer), \ - .gpios = GPIO_LIST, \ - .num_gpios = ARRAY_SIZE(GPIO_LIST), \ - }; \ - const struct usb_interface_descriptor \ - USB_IFACE_DESC(INTERFACE) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 0, \ - .bNumEndpoints = 2, \ - .bInterfaceClass = USB_CLASS_VENDOR_SPEC, \ - .bInterfaceSubClass = 0, \ - .bInterfaceProtocol = 0, \ - .iInterface = 0, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 0) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = 0x80 | ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk IN */, \ - .wMaxPacketSize = USB_GPIO_TX_PACKET_SIZE, \ - .bInterval = 10, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 1) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk OUT */, \ - .wMaxPacketSize = USB_GPIO_RX_PACKET_SIZE, \ - .bInterval = 0, \ - }; \ - static void CONCAT2(NAME, _ep_tx)(void) \ - { \ - usb_gpio_tx(&NAME); \ - } \ - static void CONCAT2(NAME, _ep_rx)(void) \ - { \ - usb_gpio_rx(&NAME); \ - } \ - static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt) \ - { \ - usb_gpio_event(&NAME, evt); \ - } \ - USB_DECLARE_EP(ENDPOINT, \ - CONCAT2(NAME, _ep_tx), \ - CONCAT2(NAME, _ep_rx), \ +#define USB_GPIO_CONFIG(NAME, GPIO_LIST, INTERFACE, ENDPOINT) \ + BUILD_ASSERT(ARRAY_SIZE(GPIO_LIST) <= 32); \ + static usb_uint CONCAT2( \ + NAME, _ep_rx_buffer)[USB_GPIO_RX_PACKET_SIZE / 2] __usb_ram; \ + static usb_uint CONCAT2( \ + NAME, _ep_tx_buffer)[USB_GPIO_TX_PACKET_SIZE / 2] __usb_ram; \ + struct usb_gpio_config const NAME = { \ + .state = &((struct usb_gpio_state){}), \ + .endpoint = ENDPOINT, \ + .rx_ram = CONCAT2(NAME, _ep_rx_buffer), \ + .tx_ram = CONCAT2(NAME, _ep_tx_buffer), \ + .gpios = GPIO_LIST, \ + .num_gpios = ARRAY_SIZE(GPIO_LIST), \ + }; \ + const struct usb_interface_descriptor USB_IFACE_DESC(INTERFACE) = { \ + .bLength = USB_DT_INTERFACE_SIZE, \ + .bDescriptorType = USB_DT_INTERFACE, \ + .bInterfaceNumber = INTERFACE, \ + .bAlternateSetting = 0, \ + .bNumEndpoints = 2, \ + .bInterfaceClass = USB_CLASS_VENDOR_SPEC, \ + .bInterfaceSubClass = 0, \ + .bInterfaceProtocol = 0, \ + .iInterface = 0, \ + }; \ + const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 0) = { \ + .bLength = USB_DT_ENDPOINT_SIZE, \ + .bDescriptorType = USB_DT_ENDPOINT, \ + .bEndpointAddress = 0x80 | ENDPOINT, \ + .bmAttributes = 0x02 /* Bulk IN */, \ + .wMaxPacketSize = USB_GPIO_TX_PACKET_SIZE, \ + .bInterval = 10, \ + }; \ + const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 1) = { \ + .bLength = USB_DT_ENDPOINT_SIZE, \ + .bDescriptorType = USB_DT_ENDPOINT, \ + .bEndpointAddress = ENDPOINT, \ + .bmAttributes = 0x02 /* Bulk OUT */, \ + .wMaxPacketSize = USB_GPIO_RX_PACKET_SIZE, \ + .bInterval = 0, \ + }; \ + static void CONCAT2(NAME, _ep_tx)(void) \ + { \ + usb_gpio_tx(&NAME); \ + } \ + static void CONCAT2(NAME, _ep_rx)(void) \ + { \ + usb_gpio_rx(&NAME); \ + } \ + static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt) \ + { \ + usb_gpio_event(&NAME, evt); \ + } \ + USB_DECLARE_EP(ENDPOINT, CONCAT2(NAME, _ep_tx), CONCAT2(NAME, _ep_rx), \ CONCAT2(NAME, _ep_event)) - /* * These functions are used by the trampoline functions defined above to * connect USB endpoint events with the generic USB GPIO driver. diff --git a/chip/stm32/usb_hid.c b/chip/stm32/usb_hid.c index b8336fa0a0..e9426b690d 100644 --- a/chip/stm32/usb_hid.c +++ b/chip/stm32/usb_hid.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -20,7 +20,7 @@ #include "usb_hid_hw.h" /* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) void hid_tx(int ep) { @@ -41,17 +41,15 @@ void hid_reset(int ep, usb_uint *hid_ep_tx_buf, int tx_len, for (i = 0; i < DIV_ROUND_UP(tx_len, 2); i++) hid_ep_tx_buf[i] = 0; - ep_reg = (ep << 0) /* Endpoint Address */ | - EP_TX_VALID | - (3 << 9) /* interrupt EP */ | - EP_RX_DISAB; + ep_reg = (ep << 0) /* Endpoint Address */ | EP_TX_VALID | + (3 << 9) /* interrupt EP */ | EP_RX_DISAB; /* Enable RX for output reports */ if (hid_ep_rx_buf && rx_len > 0) { btable_ep[ep].rx_addr = usb_sram_addr(hid_ep_rx_buf); btable_ep[ep].rx_count = ((rx_len + 1) / 2) << 10; - ep_reg |= EP_RX_VALID; /* RX Valid */ + ep_reg |= EP_RX_VALID; /* RX Valid */ } STM32_USB_EP(ep) = ep_reg; @@ -73,14 +71,13 @@ static const uint8_t *report_ptr; * * @return 0 if entire report is sent, 1 if there are remaining data. */ -static int send_report(usb_uint *ep0_buf_tx, - const uint8_t *report, +static int send_report(usb_uint *ep0_buf_tx, const uint8_t *report, int report_size) { int packet_size = MIN(report_size, USB_MAX_PACKET_SIZE); - memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx), - report, packet_size); + memcpy_to_usbram((void *)usb_sram_addr(ep0_buf_tx), report, + packet_size); btable_ep[0].tx_count = packet_size; /* report_left != 0 if report doesn't fit in 1 packet. */ report_left = report_size - packet_size; @@ -108,8 +105,8 @@ int hid_iface_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx, if (report_left == 0) return -1; report_size = MIN(USB_MAX_PACKET_SIZE, report_left); - memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx), - report_ptr, report_size); + memcpy_to_usbram((void *)usb_sram_addr(ep0_buf_tx), report_ptr, + report_size); btable_ep[0].tx_count = report_size; report_left -= report_size; report_ptr += report_size; @@ -117,7 +114,7 @@ int hid_iface_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx, report_left ? 0 : EP_STATUS_OUT); return report_left ? 1 : 0; } else if (ep0_buf_rx[0] == (USB_DIR_IN | USB_RECIP_INTERFACE | - (USB_REQ_GET_DESCRIPTOR << 8))) { + (USB_REQ_GET_DESCRIPTOR << 8))) { if (ep0_buf_rx[1] == (USB_HID_DT_REPORT << 8)) { /* Setup : HID specific : Get Report descriptor */ return send_report(ep0_buf_tx, report_desc, @@ -130,10 +127,9 @@ int hid_iface_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx, EP_STATUS_OUT); return 0; } - } else if (ep0_buf_rx[0] == (USB_DIR_IN | - USB_RECIP_INTERFACE | - USB_TYPE_CLASS | - (USB_HID_REQ_GET_REPORT << 8))) { + } else if (ep0_buf_rx[0] == + (USB_DIR_IN | USB_RECIP_INTERFACE | USB_TYPE_CLASS | + (USB_HID_REQ_GET_REPORT << 8))) { const uint8_t report_type = (ep0_buf_rx[1] >> 8) & 0xFF; const uint8_t report_id = ep0_buf_rx[1] & 0xFF; int retval; @@ -142,9 +138,7 @@ int hid_iface_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx, if (!config->get_report) /* not supported */ return -1; - retval = config->get_report(report_id, - report_type, - &report_ptr, + retval = config->get_report(report_id, report_type, &report_ptr, &report_left); if (retval) return retval; diff --git a/chip/stm32/usb_hid_hw.h b/chip/stm32/usb_hid_hw.h index a36a66567e..54bfca0808 100644 --- a/chip/stm32/usb_hid_hw.h +++ b/chip/stm32/usb_hid_hw.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -25,10 +25,8 @@ struct usb_hid_config_t { * @param buffer_size: handler should set it to the size of returned * buffer. */ - int (*get_report)(uint8_t report_id, - uint8_t report_type, - const uint8_t **buffer_ptr, - int *buffer_size); + int (*get_report)(uint8_t report_id, uint8_t report_type, + const uint8_t **buffer_ptr, int *buffer_size); }; /* internal callbacks for HID class drivers */ diff --git a/chip/stm32/usb_hid_keyboard.c b/chip/stm32/usb_hid_keyboard.c index 99775fd7fb..7f3caac960 100644 --- a/chip/stm32/usb_hid_keyboard.c +++ b/chip/stm32/usb_hid_keyboard.c @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -28,7 +28,7 @@ #include "usb_hid_hw.h" /* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) static const int keyboard_debug; @@ -51,7 +51,7 @@ enum hid_protocol { static enum hid_protocol protocol = HID_REPORT_PROTOCOL; #if defined(CONFIG_KEYBOARD_ASSISTANT_KEY) || \ - defined(CONFIG_KEYBOARD_TABLET_MODE_SWITCH) + defined(CONFIG_KEYBOARD_TABLET_MODE_SWITCH) #define HID_KEYBOARD_EXTRA_FIELD #endif @@ -126,19 +126,20 @@ struct usb_hid_keyboard_output_report { * Assistant key is mapped as 0xf0, but this key code is never actually send. */ const uint8_t keycodes[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = { - {0x00, 0x00, 0xe0, 0xe3, 0xe4, HID_KEYBOARD_ASSISTANT_KEY, 0x00, 0x00}, - {0xe3, 0x29, 0x2b, 0x35, 0x04, 0x1d, 0x1e, 0x14}, - {0x3a, 0x3d, 0x3c, 0x3b, 0x07, 0x06, 0x20, 0x08}, - {0x05, 0x0a, 0x17, 0x22, 0x09, 0x19, 0x21, 0x15}, - {0x43, 0x40, 0x3f, 0x3e, 0x16, 0x1b, 0x1f, 0x1a}, - {0x87, 0x00, 0x30, 0x00, 0x0e, 0x36, 0x25, 0x0c}, - {0x11, 0x0b, 0x1c, 0x23, 0x0d, 0x10, 0x24, 0x18}, - {0x00, 0x00, 0x64, 0x00, 0x00, 0xe1, 0x00, 0xe5}, - {0x2e, 0x34, 0x2F, 0x2d, 0x33, 0x38, 0x27, 0x13}, - {0x00, 0x42, 0x41, 0x68, 0x0f, 0x37, 0x26, 0x12}, - {0xe6, 0x00, 0x89, 0x00, 0x31, 0x00, 0xe2, 0x00}, - {0x00, 0x2a, 0x00, 0x31, 0x28, 0x2c, 0x51, 0x52}, - {0x00, 0x8a, 0x00, 0x8b, 0x00, 0x00, 0x4f, 0x50}, + { 0x00, 0x00, 0xe0, 0xe3, 0xe4, HID_KEYBOARD_ASSISTANT_KEY, 0x00, + 0x00 }, + { 0xe3, 0x29, 0x2b, 0x35, 0x04, 0x1d, 0x1e, 0x14 }, + { 0x3a, 0x3d, 0x3c, 0x3b, 0x07, 0x06, 0x20, 0x08 }, + { 0x05, 0x0a, 0x17, 0x22, 0x09, 0x19, 0x21, 0x15 }, + { 0x43, 0x40, 0x3f, 0x3e, 0x16, 0x1b, 0x1f, 0x1a }, + { 0x87, 0x00, 0x30, 0x00, 0x0e, 0x36, 0x25, 0x0c }, + { 0x11, 0x0b, 0x1c, 0x23, 0x0d, 0x10, 0x24, 0x18 }, + { 0x00, 0x00, 0x64, 0x00, 0x00, 0xe1, 0x00, 0xe5 }, + { 0x2e, 0x34, 0x2F, 0x2d, 0x33, 0x38, 0x27, 0x13 }, + { 0x00, 0x42, 0x41, 0x68, 0x0f, 0x37, 0x26, 0x12 }, + { 0xe6, 0x00, 0x89, 0x00, 0x31, 0x00, 0xe2, 0x00 }, + { 0x00, 0x2a, 0x00, 0x31, 0x28, 0x2c, 0x51, 0x52 }, + { 0x00, 0x8a, 0x00, 0x8b, 0x00, 0x00, 0x4f, 0x50 }, }; /* HID descriptors */ @@ -177,80 +178,84 @@ const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_KEYBOARD, 02) = { }; #endif -#define KEYBOARD_BASE_DESC \ - 0x05, 0x01, /* Usage Page (Generic Desktop) */ \ - 0x09, 0x06, /* Usage (Keyboard) */ \ - 0xA1, 0x01, /* Collection (Application) */ \ - \ - /* Modifiers */ \ - 0x05, 0x07, /* Usage Page (Key Codes) */ \ - 0x19, HID_KEYBOARD_MODIFIER_LOW, /* Usage Minimum */ \ - 0x29, HID_KEYBOARD_MODIFIER_HIGH, /* Usage Maximum */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0x01, /* Logical Maximum (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x95, 0x08, /* Report Count (8) */ \ - 0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */ \ - \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x75, 0x08, /* Report Size (8) */ \ - 0x81, 0x01, /* Input (Constant), ;Reserved byte */ \ - \ - /* Normal keys */ \ - 0x95, 0x06, /* Report Count (6) */ \ - 0x75, 0x08, /* Report Size (8) */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0xa4, /* Logical Maximum (164) */ \ - 0x05, 0x07, /* Usage Page (Key Codes) */ \ - 0x19, 0x00, /* Usage Minimum (0) */ \ - 0x29, 0xa4, /* Usage Maximum (164) */ \ - 0x81, 0x00, /* Input (Data, Array), ;Key arrays (6 bytes) */ - -#define KEYBOARD_TOP_ROW_DESC \ - /* Modifiers */ \ - 0x05, 0x0C, /* Consumer Page */ \ - 0x0A, 0x24, 0x02, /* AC Back (0x224) */ \ - 0x0A, 0x25, 0x02, /* AC Forward (0x225) */ \ - 0x0A, 0x27, 0x02, /* AC Refresh (0x227) */ \ - 0x0A, 0x32, 0x02, /* AC View Toggle (0x232) */ \ - 0x0A, 0x9F, 0x02, /* AC Desktop Show All windows (0x29F) */ \ - 0x09, 0x70, /* Display Brightness Decrement (0x70) */ \ - 0x09, 0x6F, /* Display Brightness Increment (0x6F) */ \ - 0x09, 0xE2, /* Mute (0xE2) */ \ - 0x09, 0xEA, /* Volume Decrement (0xEA) */ \ - 0x09, 0xE9, /* Volume Increment (0xE9) */ \ - 0x0B, 0x46, 0x00, 0x07, 0x00, /* PrintScreen (Page 0x7, Usage 0x46) */ \ - 0x0A, 0xD0, 0x02, /* Privacy Screen Toggle (0x2D0) */ \ - 0x09, 0x7A, /* Keyboard Brightness Decrement (0x7A) */ \ - 0x09, 0x79, /* Keyboard Brightness Increment (0x79)*/ \ - 0x09, 0xCD, /* Play / Pause (0xCD) */ \ - 0x09, 0xB5, /* Scan Next Track (0xB5) */ \ - 0x09, 0xB6, /* Scan Previous Track (0xB6) */ \ - 0x09, 0x7C, /* Keyboard Backlight OOC (0x7C) */ \ - 0x0B, 0x2F, 0x00, 0x0B, 0x00, /* Phone Mute (Page 0xB, Usage 0x2F) */ \ - 0x09, 0x32, /* Sleep (0x32) */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0x01, /* Logical Maximum (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x95, 0x14, /* Report Count (20) */ \ - 0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */ \ - \ - /* 12-bit padding */ \ - 0x95, 0x0C, /* Report Count (12) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x81, 0x01, /* Input (Constant), ;1-bit padding */ - -#define KEYBOARD_TOP_ROW_FEATURE_DESC \ - 0x06, 0xd1, 0xff, /* Usage Page (Google) */ \ - 0x09, 0x01, /* Usage (Top Row List) */ \ - 0xa1, 0x02, /* Collection (Logical) */ \ - 0x05, 0x0a, /* Usage Page (Ordinal) */ \ - 0x19, 0x01, /* Usage Minimum (1) */ \ - 0x29, CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS, /* Usage Maximum */ \ - 0x95, CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS, /* Report Count */ \ - 0x75, 0x20, /* Report Size (32) */ \ - 0xb1, 0x03, /* Feature (Cnst,Var,Abs) */ \ - 0xc0, /* End Collection */ +#define KEYBOARD_BASE_DESC \ + 0x05, 0x01, /* Usage Page (Generic Desktop) */ \ + 0x09, 0x06, /* Usage (Keyboard) */ \ + 0xA1, 0x01, /* Collection (Application) */ \ + \ + /* Modifiers */ \ + 0x05, 0x07, /* Usage Page (Key Codes) */ \ + 0x19, HID_KEYBOARD_MODIFIER_LOW, /* Usage Minimum */ \ + 0x29, HID_KEYBOARD_MODIFIER_HIGH, /* Usage Maximum */ \ + 0x15, 0x00, /* Logical Minimum (0) */ \ + 0x25, 0x01, /* Logical Maximum (1) */ \ + 0x75, 0x01, /* Report Size (1) */ \ + 0x95, 0x08, /* Report Count (8) */ \ + 0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier \ + byte */ \ + \ + 0x95, 0x01, /* Report Count (1) */ \ + 0x75, 0x08, /* Report Size (8) */ \ + 0x81, 0x01, /* Input (Constant), ;Reserved byte */ \ + \ + /* Normal keys */ \ + 0x95, 0x06, /* Report Count (6) */ \ + 0x75, 0x08, /* Report Size (8) */ \ + 0x15, 0x00, /* Logical Minimum (0) */ \ + 0x25, 0xa4, /* Logical Maximum (164) */ \ + 0x05, 0x07, /* Usage Page (Key Codes) */ \ + 0x19, 0x00, /* Usage Minimum (0) */ \ + 0x29, 0xa4, /* Usage Maximum (164) */ \ + 0x81, 0x00, /* Input (Data, Array), ;Key arrays (6 bytes) */ + +#define KEYBOARD_TOP_ROW_DESC \ + /* Modifiers */ \ + 0x05, 0x0C, /* Consumer Page */ \ + 0x0A, 0x24, 0x02, /* AC Back (0x224) */ \ + 0x0A, 0x25, 0x02, /* AC Forward (0x225) */ \ + 0x0A, 0x27, 0x02, /* AC Refresh (0x227) */ \ + 0x0A, 0x32, 0x02, /* AC View Toggle (0x232) */ \ + 0x0A, 0x9F, 0x02, /* AC Desktop Show All windows (0x29F) */ \ + 0x09, 0x70, /* Display Brightness Decrement (0x70) */ \ + 0x09, 0x6F, /* Display Brightness Increment (0x6F) */ \ + 0x09, 0xE2, /* Mute (0xE2) */ \ + 0x09, 0xEA, /* Volume Decrement (0xEA) */ \ + 0x09, 0xE9, /* Volume Increment (0xE9) */ \ + 0x0B, 0x46, 0x00, 0x07, 0x00, /* PrintScreen (Page 0x7, Usage \ + 0x46) */ \ + 0x0A, 0xD0, 0x02, /* Privacy Screen Toggle (0x2D0) */ \ + 0x09, 0x7A, /* Keyboard Brightness Decrement (0x7A) */ \ + 0x09, 0x79, /* Keyboard Brightness Increment (0x79)*/ \ + 0x09, 0xCD, /* Play / Pause (0xCD) */ \ + 0x09, 0xB5, /* Scan Next Track (0xB5) */ \ + 0x09, 0xB6, /* Scan Previous Track (0xB6) */ \ + 0x09, 0x7C, /* Keyboard Backlight OOC (0x7C) */ \ + 0x0B, 0x2F, 0x00, 0x0B, 0x00, /* Phone Mute (Page 0xB, Usage \ + 0x2F) */ \ + 0x09, 0x32, /* Sleep (0x32) */ \ + 0x15, 0x00, /* Logical Minimum (0) */ \ + 0x25, 0x01, /* Logical Maximum (1) */ \ + 0x75, 0x01, /* Report Size (1) */ \ + 0x95, 0x14, /* Report Count (20) */ \ + 0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier \ + byte */ \ + \ + /* 12-bit padding */ \ + 0x95, 0x0C, /* Report Count (12) */ \ + 0x75, 0x01, /* Report Size (1) */ \ + 0x81, 0x01, /* Input (Constant), ;1-bit padding */ + +#define KEYBOARD_TOP_ROW_FEATURE_DESC \ + 0x06, 0xd1, 0xff, /* Usage Page (Google) */ \ + 0x09, 0x01, /* Usage (Top Row List) */ \ + 0xa1, 0x02, /* Collection (Logical) */ \ + 0x05, 0x0a, /* Usage Page (Ordinal) */ \ + 0x19, 0x01, /* Usage Minimum (1) */ \ + 0x29, CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS, /* Usage Maximum */ \ + 0x95, CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS, /* Report Count */ \ + 0x75, 0x20, /* Report Size (32) */ \ + 0xb1, 0x03, /* Feature (Cnst,Var,Abs) */ \ + 0xc0, /* End Collection */ /* * Vendor-defined Usage Page 0xffd1: @@ -259,60 +264,62 @@ const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_KEYBOARD, 02) = { */ #ifdef HID_KEYBOARD_EXTRA_FIELD #ifdef CONFIG_KEYBOARD_ASSISTANT_KEY -#define KEYBOARD_ASSISTANT_KEY_DESC \ - 0x19, 0x18, /* Usage Minimum */ \ - 0x29, 0x18, /* Usage Maximum */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0x01, /* Logical Maximum (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */ +#define KEYBOARD_ASSISTANT_KEY_DESC \ + 0x19, 0x18, /* Usage Minimum */ \ + 0x29, 0x18, /* Usage Maximum */ \ + 0x15, 0x00, /* Logical Minimum (0) */ \ + 0x25, 0x01, /* Logical Maximum (1) */ \ + 0x75, 0x01, /* Report Size (1) */ \ + 0x95, 0x01, /* Report Count (1) */ \ + 0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier \ + byte */ #else /* No assistant key: just pad 1 bit. */ -#define KEYBOARD_ASSISTANT_KEY_DESC \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x81, 0x01, /* Input (Constant), ;1-bit padding */ +#define KEYBOARD_ASSISTANT_KEY_DESC \ + 0x95, 0x01, /* Report Count (1) */ \ + 0x75, 0x01, /* Report Size (1) */ \ + 0x81, 0x01, /* Input (Constant), ;1-bit padding */ #endif /* !CONFIG_KEYBOARD_ASSISTANT_KEY */ #ifdef CONFIG_KEYBOARD_TABLET_MODE_SWITCH -#define KEYBOARD_TABLET_MODE_SWITCH_DESC \ - 0x19, 0x19, /* Usage Minimum */ \ - 0x29, 0x19, /* Usage Maximum */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0x01, /* Logical Maximum (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */ +#define KEYBOARD_TABLET_MODE_SWITCH_DESC \ + 0x19, 0x19, /* Usage Minimum */ \ + 0x29, 0x19, /* Usage Maximum */ \ + 0x15, 0x00, /* Logical Minimum (0) */ \ + 0x25, 0x01, /* Logical Maximum (1) */ \ + 0x75, 0x01, /* Report Size (1) */ \ + 0x95, 0x01, /* Report Count (1) */ \ + 0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier \ + byte */ #else /* No tablet mode swtch: just pad 1 bit. */ -#define KEYBOARD_TABLET_MODE_SWITCH_DESC \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x81, 0x01, /* Input (Constant), ;1-bit padding */ +#define KEYBOARD_TABLET_MODE_SWITCH_DESC \ + 0x95, 0x01, /* Report Count (1) */ \ + 0x75, 0x01, /* Report Size (1) */ \ + 0x81, 0x01, /* Input (Constant), ;1-bit padding */ #endif /* CONFIG_KEYBOARD_TABLET_MODE_SWITCH */ -#define KEYBOARD_VENDOR_DESC \ - 0x06, 0xd1, 0xff, /* Usage Page (Vendor-defined 0xffd1) */ \ - \ - KEYBOARD_ASSISTANT_KEY_DESC \ - KEYBOARD_TABLET_MODE_SWITCH_DESC \ - \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x75, 0x06, /* Report Size (6) */ \ - 0x81, 0x01, /* Input (Constant), ;6-bit padding */ +#define KEYBOARD_VENDOR_DESC \ + 0x06, 0xd1, 0xff, /* Usage Page (Vendor-defined 0xffd1) */ \ + \ + KEYBOARD_ASSISTANT_KEY_DESC KEYBOARD_TABLET_MODE_SWITCH_DESC \ + \ + 0x95, \ + 0x01, /* Report Count (1) */ \ + 0x75, 0x06, /* Report Size (6) */ \ + 0x81, 0x01, /* Input (Constant), ;6-bit padding */ #endif /* HID_KEYBOARD_EXTRA_FIELD */ -#define KEYBOARD_BACKLIGHT_DESC \ - 0xA1, 0x02, /* Collection (Logical) */ \ - 0x05, 0x14, /* Usage Page (Alphanumeric Display) */ \ - 0x09, 0x46, /* Usage (Display Brightness) */ \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x75, 0x08, /* Report Size (8) */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0x64, /* Logical Maximum (100) */ \ - 0x91, 0x02, /* Output (Data, Variable, Absolute) */ \ - 0xC0, /* End Collection */ +#define KEYBOARD_BACKLIGHT_DESC \ + 0xA1, 0x02, /* Collection (Logical) */ \ + 0x05, 0x14, /* Usage Page (Alphanumeric Display) */ \ + 0x09, 0x46, /* Usage (Display Brightness) */ \ + 0x95, 0x01, /* Report Count (1) */ \ + 0x75, 0x08, /* Report Size (8) */ \ + 0x15, 0x00, /* Logical Minimum (0) */ \ + 0x25, 0x64, /* Logical Maximum (100) */ \ + 0x91, 0x02, /* Output (Data, Variable, Absolute) */ \ + 0xC0, /* End Collection */ /* * To allow dynamic detection of keyboard backlights, we define two descriptors. @@ -325,17 +332,15 @@ static const uint8_t report_desc[] = { KEYBOARD_BASE_DESC #ifdef KEYBOARD_VENDOR_DESC - KEYBOARD_VENDOR_DESC + KEYBOARD_VENDOR_DESC #endif #ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI - KEYBOARD_TOP_ROW_DESC - KEYBOARD_TOP_ROW_FEATURE_DESC + KEYBOARD_TOP_ROW_DESC KEYBOARD_TOP_ROW_FEATURE_DESC #endif - 0xC0 /* End Collection */ + 0xC0 /* End Collection */ }; - #ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT /* HID : Report Descriptor with keyboard backlight */ @@ -344,32 +349,29 @@ static const uint8_t report_desc_with_backlight[] = { KEYBOARD_BASE_DESC #ifdef KEYBOARD_VENDOR_DESC - KEYBOARD_VENDOR_DESC + KEYBOARD_VENDOR_DESC #endif #ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI - KEYBOARD_TOP_ROW_DESC - KEYBOARD_TOP_ROW_FEATURE_DESC + KEYBOARD_TOP_ROW_DESC KEYBOARD_TOP_ROW_FEATURE_DESC #endif - KEYBOARD_BACKLIGHT_DESC + KEYBOARD_BACKLIGHT_DESC - 0xC0 /* End Collection */ + 0xC0 /* End Collection */ }; #endif /* HID: HID Descriptor */ -const struct usb_hid_descriptor USB_CUSTOM_DESC_VAR(USB_IFACE_HID_KEYBOARD, - hid, hid_desc_kb) = { +const struct usb_hid_descriptor USB_CUSTOM_DESC_VAR(USB_IFACE_HID_KEYBOARD, hid, + hid_desc_kb) = { .bLength = 9, .bDescriptorType = USB_HID_DT_HID, .bcdHID = 0x0100, .bCountryCode = 0x00, /* Hardware target country */ .bNumDescriptors = 1, - .desc = {{ - .bDescriptorType = USB_HID_DT_REPORT, - .wDescriptorLength = sizeof(report_desc) - }} + .desc = { { .bDescriptorType = USB_HID_DT_REPORT, + .wDescriptorLength = sizeof(report_desc) } } }; #define EP_TX_BUF_SIZE DIV_ROUND_UP(HID_KEYBOARD_REPORT_SIZE, 2) @@ -403,10 +405,10 @@ static void write_keyboard_report(void) * send the buffer: enable TX. */ - memcpy_to_usbram((void *) usb_sram_addr(hid_ep_tx_buf), - &report, sizeof(report)); - STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK, - EP_TX_VALID, 0); + memcpy_to_usbram((void *)usb_sram_addr(hid_ep_tx_buf), &report, + sizeof(report)); + STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK, EP_TX_VALID, + 0); } /* @@ -422,7 +424,7 @@ static void write_keyboard_report(void) static void hid_keyboard_rx(void) { struct usb_hid_keyboard_output_report report; - memcpy_from_usbram(&report, (void *) usb_sram_addr(hid_ep_rx_buf), + memcpy_from_usbram(&report, (void *)usb_sram_addr(hid_ep_rx_buf), HID_KEYBOARD_OUTPUT_REPORT_SIZE); CPRINTF("Keyboard backlight set to %d%%\n", report.brightness); @@ -439,10 +441,10 @@ static void hid_keyboard_tx(void) { hid_tx(USB_EP_HID_KEYBOARD); if (hid_ep_data_ready) { - memcpy_to_usbram((void *) usb_sram_addr(hid_ep_tx_buf), - &report, sizeof(report)); - STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK, - EP_TX_VALID, 0); + memcpy_to_usbram((void *)usb_sram_addr(hid_ep_tx_buf), &report, + sizeof(report)); + STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK, EP_TX_VALID, + 0); hid_ep_data_ready = 0; } @@ -455,16 +457,14 @@ static void hid_keyboard_event(enum usb_ep_event evt) if (evt == USB_EVENT_RESET) { protocol = HID_REPORT_PROTOCOL; - hid_reset(USB_EP_HID_KEYBOARD, - hid_ep_tx_buf, + hid_reset(USB_EP_HID_KEYBOARD, hid_ep_tx_buf, HID_KEYBOARD_REPORT_SIZE, #ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT - hid_ep_rx_buf, - HID_KEYBOARD_OUTPUT_REPORT_SIZE + hid_ep_rx_buf, HID_KEYBOARD_OUTPUT_REPORT_SIZE #else NULL, 0 #endif - ); + ); /* * Reload endpoint on reset, to make sure we report accurate @@ -547,8 +547,8 @@ static int hid_keyboard_get_report(uint8_t report_id, uint8_t report_type, #ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI if (report_type == REPORT_TYPE_FEATURE) { *buffer_ptr = (uint8_t *)feature_report; - *buffer_size = (sizeof(uint32_t) * - CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS); + *buffer_size = + (sizeof(uint32_t) * CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS); return 0; } #endif @@ -572,8 +572,9 @@ static int hid_keyboard_iface_request(usb_uint *ep0_buf_rx, if (ret >= 0) return ret; - if (ep0_buf_rx[0] == (USB_DIR_OUT | USB_TYPE_CLASS | - USB_RECIP_INTERFACE | (USB_HID_REQ_SET_PROTOCOL << 8))) { + if (ep0_buf_rx[0] == + (USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE | + (USB_HID_REQ_SET_PROTOCOL << 8))) { uint16_t value = ep0_buf_rx[1]; if (value >= HID_PROTOCOL_COUNT) @@ -584,19 +585,21 @@ static int hid_keyboard_iface_request(usb_uint *ep0_buf_rx, /* Reload endpoint with appropriate tx_count. */ btable_ep[USB_EP_HID_KEYBOARD].tx_count = (protocol == HID_BOOT_PROTOCOL) ? - HID_KEYBOARD_BOOT_SIZE : HID_KEYBOARD_REPORT_SIZE; - STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK, - EP_TX_VALID, 0); + HID_KEYBOARD_BOOT_SIZE : + HID_KEYBOARD_REPORT_SIZE; + STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK, EP_TX_VALID, + 0); btable_ep[0].tx_count = 0; STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0); return 0; - } else if (ep0_buf_rx[0] == (USB_DIR_IN | USB_TYPE_CLASS | - USB_RECIP_INTERFACE | (USB_HID_REQ_GET_PROTOCOL << 8))) { + } else if (ep0_buf_rx[0] == + (USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE | + (USB_HID_REQ_GET_PROTOCOL << 8))) { uint8_t value = protocol; - memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx), - &value, sizeof(value)); + memcpy_to_usbram((void *)usb_sram_addr(ep0_buf_tx), &value, + sizeof(value)); btable_ep[0].tx_count = 1; STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0); return 0; @@ -615,7 +618,7 @@ void keyboard_clear_buffer(void) memset(&report, 0, sizeof(report)); #ifdef CONFIG_KEYBOARD_TABLET_MODE_SWITCH if (tablet_get_mode()) - report.extra |= 0x01 << (HID_KEYBOARD_TABLET_MODE_SWITCH - + report.extra |= 0x01 << (HID_KEYBOARD_TABLET_MODE_SWITCH - HID_KEYBOARD_EXTRA_LOW); #endif write_keyboard_report(); @@ -648,7 +651,7 @@ static uint32_t maybe_convert_function_key(int keycode) return SLEEP_KEY_MASK; if (index >= config->num_top_row_keys || - config->action_keys[index] == TK_ABSENT) + config->action_keys[index] == TK_ABSENT) return 0; /* not mapped */ return action_key[config->action_keys[index]].mask; } @@ -666,8 +669,8 @@ static void keyboard_process_queue(void) if (keyboard_debug) CPRINTF("Q%d (s%d ep%d hw%d)\n", queue_count(&key_queue), usb_is_suspended(), hid_ep_data_ready, - (STM32_USB_EP(USB_EP_HID_KEYBOARD) & EP_TX_MASK) - == EP_TX_VALID); + (STM32_USB_EP(USB_EP_HID_KEYBOARD) & EP_TX_MASK) == + EP_TX_VALID); mutex_lock(&key_queue_mutex); if (queue_count(&key_queue) == 0) { @@ -728,7 +731,7 @@ static void keyboard_process_queue(void) valid = 1; #endif } else if (ev.keycode >= HID_KEYBOARD_EXTRA_LOW && - ev.keycode <= HID_KEYBOARD_EXTRA_HIGH) { + ev.keycode <= HID_KEYBOARD_EXTRA_HIGH) { #ifdef HID_KEYBOARD_EXTRA_FIELD mask = 0x01 << (ev.keycode - HID_KEYBOARD_EXTRA_LOW); if (ev.pressed) @@ -738,7 +741,7 @@ static void keyboard_process_queue(void) valid = 1; #endif } else if (ev.keycode >= HID_KEYBOARD_MODIFIER_LOW && - ev.keycode <= HID_KEYBOARD_MODIFIER_HIGH) { + ev.keycode <= HID_KEYBOARD_MODIFIER_HIGH) { mask = 0x01 << (ev.keycode - HID_KEYBOARD_MODIFIER_LOW); if (ev.pressed) report.modifiers |= mask; @@ -805,7 +808,7 @@ static void tablet_mode_change(void) } DECLARE_HOOK(HOOK_TABLET_MODE_CHANGE, tablet_mode_change, HOOK_PRIO_DEFAULT); /* Run after tablet_mode_init. */ -DECLARE_HOOK(HOOK_INIT, tablet_mode_change, HOOK_PRIO_DEFAULT+1); +DECLARE_HOOK(HOOK_INIT, tablet_mode_change, HOOK_PRIO_DEFAULT + 1); #endif void keyboard_state_changed(int row, int col, int is_pressed) @@ -821,7 +824,8 @@ void keyboard_state_changed(int row, int col, int is_pressed) } void clear_typematic_key(void) -{ } +{ +} #ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT void usb_hid_keyboard_init(void) @@ -831,8 +835,8 @@ void usb_hid_keyboard_init(void) hid_config_kb.report_size = sizeof(report_desc_with_backlight); set_descriptor_patch(USB_DESC_KEYBOARD_BACKLIGHT, - &hid_desc_kb.desc[0].wDescriptorLength, - sizeof(report_desc_with_backlight)); + &hid_desc_kb.desc[0].wDescriptorLength, + sizeof(report_desc_with_backlight)); } } /* This needs to happen before usb_init (HOOK_PRIO_DEFAULT) */ diff --git a/chip/stm32/usb_hid_touchpad.c b/chip/stm32/usb_hid_touchpad.c index 0ead660432..15dd38756f 100644 --- a/chip/stm32/usb_hid_touchpad.c +++ b/chip/stm32/usb_hid_touchpad.c @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -24,16 +24,16 @@ #include "usb_hid_touchpad.h" /* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USB, format, ##args) static const int touchpad_debug; -static struct queue const report_queue = QUEUE_NULL(8, - struct usb_hid_touchpad_report); +static struct queue const report_queue = + QUEUE_NULL(8, struct usb_hid_touchpad_report); static struct mutex report_queue_mutex; -#define HID_TOUCHPAD_REPORT_SIZE sizeof(struct usb_hid_touchpad_report) +#define HID_TOUCHPAD_REPORT_SIZE sizeof(struct usb_hid_touchpad_report) /* * Touchpad EP interval: Make sure this value is smaller than the typical @@ -65,58 +65,63 @@ const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_TOUCHPAD, 81) = { .bInterval = HID_TOUCHPAD_EP_INTERVAL_MS /* polling interval */ }; -#define FINGER_USAGE \ - 0x05, 0x0D, /* Usage Page (Digitizer) */ \ - 0x09, 0x22, /* Usage (Finger) */ \ - 0xA1, 0x02, /* Collection (Logical) */ \ - 0x09, 0x47, /* Usage (Confidence) */ \ - 0x09, 0x42, /* Usage (Tip Switch) */ \ - 0x09, 0x32, /* Usage (In Range) */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0x01, /* Logical Maximum (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x95, 0x03, /* Report Count (3) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x09, 0x51, /* Usage (0x51) Contact identifier */ \ - 0x75, 0x04, /* Report Size (4) */ \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x25, 0x0F, /* Logical Maximum (15) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x05, 0x0D, /* Usage Page (Digitizer) */ \ - /* Logical Maximum of Pressure */ \ - 0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE & 0xFF), \ - (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE >> 8), \ - 0x75, 0x09, /* Report Size (9) */ \ - 0x09, 0x30, /* Usage (Tip pressure) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x26, 0xFF, 0x0F, /* Logical Maximum (4095) */ \ - 0x75, 0x0C, /* Report Size (12) */ \ - 0x09, 0x48, /* Usage (WIDTH) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x09, 0x49, /* Usage (HEIGHT) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x05, 0x01, /* Usage Page (Generic Desktop Ctrls) */ \ - 0x75, 0x0C, /* Report Size (12) */ \ - 0x55, 0x0E, /* Unit Exponent (-2) */ \ - 0x65, 0x11, /* Unit (System: SI Linear, Length: cm) */ \ - 0x09, 0x30, /* Usage (X) */ \ - 0x35, 0x00, /* Physical Minimum (0) */ \ - 0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X & 0xff), \ - (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X >> 8), \ - /* Logical Maximum */ \ - 0x46, (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X & 0xff), \ - (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X >> 8), \ - /* Physical Maximum (tenth of mm) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y & 0xff), \ - (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y >> 8), \ - /* Logical Maximum */ \ - 0x46, (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y & 0xff), \ - (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y >> 8), \ - /* Physical Maximum (tenth of mm) */ \ - 0x09, 0x31, /* Usage (Y) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0xC0 /* End Collection */ +#define FINGER_USAGE \ + 0x05, 0x0D, /* Usage Page (Digitizer) */ \ + 0x09, 0x22, /* Usage (Finger) */ \ + 0xA1, 0x02, /* Collection (Logical) */ \ + 0x09, 0x47, /* Usage (Confidence) */ \ + 0x09, 0x42, /* Usage (Tip Switch) */ \ + 0x09, 0x32, /* Usage (In Range) */ \ + 0x15, 0x00, /* Logical Minimum (0) */ \ + 0x25, 0x01, /* Logical Maximum (1) */ \ + 0x75, 0x01, /* Report Size (1) */ \ + 0x95, 0x03, /* Report Count (3) */ \ + 0x81, 0x02, /* Input (Data,Var,Abs) */ \ + 0x09, 0x51, /* Usage (0x51) Contact identifier */ \ + 0x75, 0x04, /* Report Size (4) */ \ + 0x95, 0x01, /* Report Count (1) */ \ + 0x25, 0x0F, /* Logical Maximum (15) */ \ + 0x81, 0x02, /* Input (Data,Var,Abs) */ \ + 0x05, 0x0D, /* Usage Page (Digitizer) */ /* Logical \ + Maximum of \ + Pressure */ \ + 0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE & 0xFF), \ + (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE >> 8), 0x75, \ + 0x09, /* Report Size (9) */ \ + 0x09, 0x30, /* Usage (Tip pressure) */ \ + 0x81, 0x02, /* Input (Data,Var,Abs) */ \ + 0x26, 0xFF, 0x0F, /* Logical Maximum (4095) */ \ + 0x75, 0x0C, /* Report Size (12) */ \ + 0x09, 0x48, /* Usage (WIDTH) */ \ + 0x81, 0x02, /* Input (Data,Var,Abs) */ \ + 0x09, 0x49, /* Usage (HEIGHT) */ \ + 0x81, 0x02, /* Input (Data,Var,Abs) */ \ + 0x05, 0x01, /* Usage Page (Generic Desktop Ctrls) */ \ + 0x75, 0x0C, /* Report Size (12) */ \ + 0x55, 0x0E, /* Unit Exponent (-2) */ \ + 0x65, 0x11, /* Unit (System: SI Linear, Length: cm) */ \ + 0x09, 0x30, /* Usage (X) */ \ + 0x35, 0x00, /* Physical Minimum (0) */ \ + 0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X & 0xff), \ + (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X >> 8), /* Logical \ + Maximum */ \ + 0x46, (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X & 0xff), \ + (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X >> 8), /* Physical \ + Maximum \ + (tenth of \ + mm) */ \ + 0x81, 0x02, /* Input (Data,Var,Abs) */ \ + 0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y & 0xff), \ + (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y >> 8), /* Logical \ + Maximum */ \ + 0x46, (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y & 0xff), \ + (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y >> 8), /* Physical \ + Maximum \ + (tenth of \ + mm) */ \ + 0x09, 0x31, /* Usage (Y) */ \ + 0x81, 0x02, /* Input (Data,Var,Abs) */ \ + 0xC0 /* End Collection */ /* * HID: Report Descriptor @@ -125,10 +130,10 @@ const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_TOUCHPAD, 81) = { */ static const uint8_t report_desc[] = { /* Touchpad Collection */ - 0x05, 0x0D, /* Usage Page (Digitizer) */ - 0x09, 0x05, /* Usage (Touch Pad) */ - 0xA1, 0x01, /* Collection (Application) */ - 0x85, REPORT_ID_TOUCHPAD, /* Report ID (1, Touch) */ + 0x05, 0x0D, /* Usage Page (Digitizer) */ + 0x09, 0x05, /* Usage (Touch Pad) */ + 0xA1, 0x01, /* Collection (Application) */ + 0x85, REPORT_ID_TOUCHPAD, /* Report ID (1, Touch) */ /* Finger 0 */ FINGER_USAGE, /* Finger 1 */ @@ -140,52 +145,52 @@ static const uint8_t report_desc[] = { /* Finger 4 */ FINGER_USAGE, /* Contact count */ - 0x05, 0x0D, /* Usage Page (Digitizer) */ - 0x09, 0x54, /* Usage (Contact count) */ - 0x25, MAX_FINGERS, /* Logical Maximum (MAX_FINGERS) */ - 0x75, 0x07, /* Report Size (7) */ - 0x95, 0x01, /* Report Count (1) */ - 0x81, 0x02, /* Input (Data,Var,Abs) */ + 0x05, 0x0D, /* Usage Page (Digitizer) */ + 0x09, 0x54, /* Usage (Contact count) */ + 0x25, MAX_FINGERS, /* Logical Maximum (MAX_FINGERS) */ + 0x75, 0x07, /* Report Size (7) */ + 0x95, 0x01, /* Report Count (1) */ + 0x81, 0x02, /* Input (Data,Var,Abs) */ /* Button */ - 0x05, 0x01, /* Usage Page(Generic Desktop Ctrls) */ - 0x05, 0x09, /* Usage (Button) */ - 0x19, 0x01, /* Usage Minimum (0x01) */ - 0x29, 0x01, /* Usage Maximum (0x01) */ - 0x15, 0x00, /* Logical Minimum (0) */ - 0x25, 0x01, /* Logical Maximum (1) */ - 0x75, 0x01, /* Report Size (1) */ - 0x95, 0x01, /* Report Count (1) */ - 0x81, 0x02, /* Input (Data,Var,Abs) */ + 0x05, 0x01, /* Usage Page(Generic Desktop Ctrls) */ + 0x05, 0x09, /* Usage (Button) */ + 0x19, 0x01, /* Usage Minimum (0x01) */ + 0x29, 0x01, /* Usage Maximum (0x01) */ + 0x15, 0x00, /* Logical Minimum (0) */ + 0x25, 0x01, /* Logical Maximum (1) */ + 0x75, 0x01, /* Report Size (1) */ + 0x95, 0x01, /* Report Count (1) */ + 0x81, 0x02, /* Input (Data,Var,Abs) */ /* Timestamp */ - 0x05, 0x0D, /* Usage Page (Digitizer) */ - 0x55, 0x0C, /* Unit Exponent (-4) */ - 0x66, 0x01, 0x10, /* Unit (Seconds) */ - 0x47, 0xFF, 0xFF, 0x00, 0x00, /* Physical Maximum (65535) */ - 0x27, 0xFF, 0xFF, 0x00, 0x00, /* Logical Maximum (65535) */ - 0x75, 0x10, /* Report Size (16) */ - 0x95, 0x01, /* Report Count (1) */ - 0x09, 0x56, /* Usage (0x56, Relative Scan Time) */ - 0x81, 0x02, /* Input (Data,Var,Abs) */ - - 0x85, REPORT_ID_DEVICE_CAPS, /* Report ID (Device Capabilities) */ - 0x09, 0x55, /* Usage (Contact Count Maximum) */ - 0x09, 0x59, /* Usage (Pad Type) */ - 0x25, 0x0F, /* Logical Maximum (15) */ - 0x75, 0x08, /* Report Size (8) */ - 0x95, 0x02, /* Report Count (2) */ - 0xB1, 0x02, /* Feature (Data,Var,Abs) */ + 0x05, 0x0D, /* Usage Page (Digitizer) */ + 0x55, 0x0C, /* Unit Exponent (-4) */ + 0x66, 0x01, 0x10, /* Unit (Seconds) */ + 0x47, 0xFF, 0xFF, 0x00, 0x00, /* Physical Maximum (65535) */ + 0x27, 0xFF, 0xFF, 0x00, 0x00, /* Logical Maximum (65535) */ + 0x75, 0x10, /* Report Size (16) */ + 0x95, 0x01, /* Report Count (1) */ + 0x09, 0x56, /* Usage (0x56, Relative Scan Time) */ + 0x81, 0x02, /* Input (Data,Var,Abs) */ + + 0x85, REPORT_ID_DEVICE_CAPS, /* Report ID (Device Capabilities) */ + 0x09, 0x55, /* Usage (Contact Count Maximum) */ + 0x09, 0x59, /* Usage (Pad Type) */ + 0x25, 0x0F, /* Logical Maximum (15) */ + 0x75, 0x08, /* Report Size (8) */ + 0x95, 0x02, /* Report Count (2) */ + 0xB1, 0x02, /* Feature (Data,Var,Abs) */ /* Page 0xFF, usage 0xC5 is device certificate. */ - 0x06, 0x00, 0xFF, /* Usage Page (Vendor Defined) */ - 0x85, REPORT_ID_DEVICE_CERT, /* Report ID (Device Certification) */ - 0x09, 0xC5, /* Usage (Vendor Usage 0xC5) */ - 0x15, 0x00, /* Logical Minimum (0) */ - 0x26, 0xFF, 0x00, /* Logical Maximum (255) */ - 0x75, 0x08, /* Report Size (8) */ - 0x96, 0x00, 0x01, /* Report Count (256) */ - 0xB1, 0x02, /* Feature (Data,Var,Abs) */ - - 0xC0, /* End Collection */ + 0x06, 0x00, 0xFF, /* Usage Page (Vendor Defined) */ + 0x85, REPORT_ID_DEVICE_CERT, /* Report ID (Device Certification) */ + 0x09, 0xC5, /* Usage (Vendor Usage 0xC5) */ + 0x15, 0x00, /* Logical Minimum (0) */ + 0x26, 0xFF, 0x00, /* Logical Maximum (255) */ + 0x75, 0x08, /* Report Size (8) */ + 0x96, 0x00, 0x01, /* Report Count (256) */ + 0xB1, 0x02, /* Feature (Data,Var,Abs) */ + + 0xC0, /* End Collection */ }; /* A 256-byte default blob for the 'device certification status' feature report. @@ -195,59 +200,281 @@ static const uint8_t report_desc[] = { static const uint8_t device_cert_response[] = { REPORT_ID_DEVICE_CERT, - 0xFC, 0x28, 0xFE, 0x84, 0x40, 0xCB, 0x9A, 0x87, - 0x0D, 0xBE, 0x57, 0x3C, 0xB6, 0x70, 0x09, 0x88, - 0x07, 0x97, 0x2D, 0x2B, 0xE3, 0x38, 0x34, 0xB6, - 0x6C, 0xED, 0xB0, 0xF7, 0xE5, 0x9C, 0xF6, 0xC2, - 0x2E, 0x84, 0x1B, 0xE8, 0xB4, 0x51, 0x78, 0x43, - 0x1F, 0x28, 0x4B, 0x7C, 0x2D, 0x53, 0xAF, 0xFC, - 0x47, 0x70, 0x1B, 0x59, 0x6F, 0x74, 0x43, 0xC4, - 0xF3, 0x47, 0x18, 0x53, 0x1A, 0xA2, 0xA1, 0x71, - 0xC7, 0x95, 0x0E, 0x31, 0x55, 0x21, 0xD3, 0xB5, - 0x1E, 0xE9, 0x0C, 0xBA, 0xEC, 0xB8, 0x89, 0x19, - 0x3E, 0xB3, 0xAF, 0x75, 0x81, 0x9D, 0x53, 0xB9, - 0x41, 0x57, 0xF4, 0x6D, 0x39, 0x25, 0x29, 0x7C, - 0x87, 0xD9, 0xB4, 0x98, 0x45, 0x7D, 0xA7, 0x26, - 0x9C, 0x65, 0x3B, 0x85, 0x68, 0x89, 0xD7, 0x3B, - 0xBD, 0xFF, 0x14, 0x67, 0xF2, 0x2B, 0xF0, 0x2A, - 0x41, 0x54, 0xF0, 0xFD, 0x2C, 0x66, 0x7C, 0xF8, - 0xC0, 0x8F, 0x33, 0x13, 0x03, 0xF1, 0xD3, 0xC1, - 0x0B, 0x89, 0xD9, 0x1B, 0x62, 0xCD, 0x51, 0xB7, - 0x80, 0xB8, 0xAF, 0x3A, 0x10, 0xC1, 0x8A, 0x5B, - 0xE8, 0x8A, 0x56, 0xF0, 0x8C, 0xAA, 0xFA, 0x35, - 0xE9, 0x42, 0xC4, 0xD8, 0x55, 0xC3, 0x38, 0xCC, - 0x2B, 0x53, 0x5C, 0x69, 0x52, 0xD5, 0xC8, 0x73, - 0x02, 0x38, 0x7C, 0x73, 0xB6, 0x41, 0xE7, 0xFF, - 0x05, 0xD8, 0x2B, 0x79, 0x9A, 0xE2, 0x34, 0x60, - 0x8F, 0xA3, 0x32, 0x1F, 0x09, 0x78, 0x62, 0xBC, - 0x80, 0xE3, 0x0F, 0xBD, 0x65, 0x20, 0x08, 0x13, - 0xC1, 0xE2, 0xEE, 0x53, 0x2D, 0x86, 0x7E, 0xA7, - 0x5A, 0xC5, 0xD3, 0x7D, 0x98, 0xBE, 0x31, 0x48, - 0x1F, 0xFB, 0xDA, 0xAF, 0xA2, 0xA8, 0x6A, 0x89, - 0xD6, 0xBF, 0xF2, 0xD3, 0x32, 0x2A, 0x9A, 0xE4, - 0xCF, 0x17, 0xB7, 0xB8, 0xF4, 0xE1, 0x33, 0x08, - 0x24, 0x8B, 0xC4, 0x43, 0xA5, 0xE5, 0x24, 0xC2, + 0xFC, + 0x28, + 0xFE, + 0x84, + 0x40, + 0xCB, + 0x9A, + 0x87, + 0x0D, + 0xBE, + 0x57, + 0x3C, + 0xB6, + 0x70, + 0x09, + 0x88, + 0x07, + 0x97, + 0x2D, + 0x2B, + 0xE3, + 0x38, + 0x34, + 0xB6, + 0x6C, + 0xED, + 0xB0, + 0xF7, + 0xE5, + 0x9C, + 0xF6, + 0xC2, + 0x2E, + 0x84, + 0x1B, + 0xE8, + 0xB4, + 0x51, + 0x78, + 0x43, + 0x1F, + 0x28, + 0x4B, + 0x7C, + 0x2D, + 0x53, + 0xAF, + 0xFC, + 0x47, + 0x70, + 0x1B, + 0x59, + 0x6F, + 0x74, + 0x43, + 0xC4, + 0xF3, + 0x47, + 0x18, + 0x53, + 0x1A, + 0xA2, + 0xA1, + 0x71, + 0xC7, + 0x95, + 0x0E, + 0x31, + 0x55, + 0x21, + 0xD3, + 0xB5, + 0x1E, + 0xE9, + 0x0C, + 0xBA, + 0xEC, + 0xB8, + 0x89, + 0x19, + 0x3E, + 0xB3, + 0xAF, + 0x75, + 0x81, + 0x9D, + 0x53, + 0xB9, + 0x41, + 0x57, + 0xF4, + 0x6D, + 0x39, + 0x25, + 0x29, + 0x7C, + 0x87, + 0xD9, + 0xB4, + 0x98, + 0x45, + 0x7D, + 0xA7, + 0x26, + 0x9C, + 0x65, + 0x3B, + 0x85, + 0x68, + 0x89, + 0xD7, + 0x3B, + 0xBD, + 0xFF, + 0x14, + 0x67, + 0xF2, + 0x2B, + 0xF0, + 0x2A, + 0x41, + 0x54, + 0xF0, + 0xFD, + 0x2C, + 0x66, + 0x7C, + 0xF8, + 0xC0, + 0x8F, + 0x33, + 0x13, + 0x03, + 0xF1, + 0xD3, + 0xC1, + 0x0B, + 0x89, + 0xD9, + 0x1B, + 0x62, + 0xCD, + 0x51, + 0xB7, + 0x80, + 0xB8, + 0xAF, + 0x3A, + 0x10, + 0xC1, + 0x8A, + 0x5B, + 0xE8, + 0x8A, + 0x56, + 0xF0, + 0x8C, + 0xAA, + 0xFA, + 0x35, + 0xE9, + 0x42, + 0xC4, + 0xD8, + 0x55, + 0xC3, + 0x38, + 0xCC, + 0x2B, + 0x53, + 0x5C, + 0x69, + 0x52, + 0xD5, + 0xC8, + 0x73, + 0x02, + 0x38, + 0x7C, + 0x73, + 0xB6, + 0x41, + 0xE7, + 0xFF, + 0x05, + 0xD8, + 0x2B, + 0x79, + 0x9A, + 0xE2, + 0x34, + 0x60, + 0x8F, + 0xA3, + 0x32, + 0x1F, + 0x09, + 0x78, + 0x62, + 0xBC, + 0x80, + 0xE3, + 0x0F, + 0xBD, + 0x65, + 0x20, + 0x08, + 0x13, + 0xC1, + 0xE2, + 0xEE, + 0x53, + 0x2D, + 0x86, + 0x7E, + 0xA7, + 0x5A, + 0xC5, + 0xD3, + 0x7D, + 0x98, + 0xBE, + 0x31, + 0x48, + 0x1F, + 0xFB, + 0xDA, + 0xAF, + 0xA2, + 0xA8, + 0x6A, + 0x89, + 0xD6, + 0xBF, + 0xF2, + 0xD3, + 0x32, + 0x2A, + 0x9A, + 0xE4, + 0xCF, + 0x17, + 0xB7, + 0xB8, + 0xF4, + 0xE1, + 0x33, + 0x08, + 0x24, + 0x8B, + 0xC4, + 0x43, + 0xA5, + 0xE5, + 0x24, + 0xC2, }; /* Device capabilities feature report. */ static const uint8_t device_caps_response[] = { REPORT_ID_DEVICE_CAPS, - MAX_FINGERS, /* Contact Count Maximum */ - 0x00, /* Pad Type: Depressible click-pad */ + MAX_FINGERS, /* Contact Count Maximum */ + 0x00, /* Pad Type: Depressible click-pad */ }; -const struct usb_hid_descriptor USB_CUSTOM_DESC_VAR(USB_IFACE_HID_TOUCHPAD, - hid, hid_desc_tp) = { +const struct usb_hid_descriptor USB_CUSTOM_DESC_VAR(USB_IFACE_HID_TOUCHPAD, hid, + hid_desc_tp) = { .bLength = 9, .bDescriptorType = USB_HID_DT_HID, .bcdHID = 0x0100, .bCountryCode = 0x00, /* Hardware target country */ .bNumDescriptors = 1, - .desc = {{ - .bDescriptorType = USB_HID_DT_REPORT, - .wDescriptorLength = sizeof(report_desc) - }} + .desc = { { .bDescriptorType = USB_HID_DT_REPORT, + .wDescriptorLength = sizeof(report_desc) } } }; static usb_uint hid_ep_buf[DIV_ROUND_UP(HID_TOUCHPAD_REPORT_SIZE, 2)] __usb_ram; @@ -258,8 +485,8 @@ static usb_uint hid_ep_buf[DIV_ROUND_UP(HID_TOUCHPAD_REPORT_SIZE, 2)] __usb_ram; */ static void write_touchpad_report(struct usb_hid_touchpad_report *report) { - memcpy_to_usbram((void *) usb_sram_addr(hid_ep_buf), - report, sizeof(*report)); + memcpy_to_usbram((void *)usb_sram_addr(hid_ep_buf), report, + sizeof(*report)); /* enable TX */ STM32_TOGGLE_EP(USB_EP_HID_TOUCHPAD, EP_TX_MASK, EP_TX_VALID, 0); @@ -289,8 +516,7 @@ static void hid_touchpad_process_queue(void) now = __hw_clock_source_read() / USB_HID_TOUCHPAD_TIMESTAMP_UNIT; if (usb_is_suspended() || - (STM32_USB_EP(USB_EP_HID_TOUCHPAD) & EP_TX_MASK) - == EP_TX_VALID) { + (STM32_USB_EP(USB_EP_HID_TOUCHPAD) & EP_TX_MASK) == EP_TX_VALID) { usb_wake(); /* Let's trim old events from the queue, if any. */ @@ -307,8 +533,8 @@ static void hid_touchpad_process_queue(void) queue_peek_units(&report_queue, &report, 0, 1); - delta = (int)((uint16_t)(now - report.timestamp)) - * USB_HID_TOUCHPAD_TIMESTAMP_UNIT; + delta = (int)((uint16_t)(now - report.timestamp)) * + USB_HID_TOUCHPAD_TIMESTAMP_UNIT; if (touchpad_debug) CPRINTS("evt t=%d d=%d", report.timestamp, delta); @@ -345,8 +571,8 @@ void set_touchpad_report(struct usb_hid_touchpad_report *report) /* USB/EP ready and nothing in queue, just write the report. */ if (!usb_is_suspended() && - (STM32_USB_EP(USB_EP_HID_TOUCHPAD) & EP_TX_MASK) != EP_TX_VALID - && queue_count(&report_queue) == 0) { + (STM32_USB_EP(USB_EP_HID_TOUCHPAD) & EP_TX_MASK) != EP_TX_VALID && + queue_count(&report_queue) == 0) { write_touchpad_report(report); mutex_unlock(&report_queue_mutex); return; @@ -385,7 +611,7 @@ static void hid_touchpad_event(enum usb_ep_event evt) hid_reset(USB_EP_HID_TOUCHPAD, hid_ep_buf, HID_TOUCHPAD_REPORT_SIZE, NULL, 0); else if (evt == USB_EVENT_DEVICE_RESUME && - queue_count(&report_queue) > 0) + queue_count(&report_queue) > 0) hook_call_deferred(&hid_touchpad_process_queue_data, 0); } @@ -393,8 +619,7 @@ USB_DECLARE_EP(USB_EP_HID_TOUCHPAD, hid_touchpad_tx, hid_touchpad_tx, hid_touchpad_event); static int get_report(uint8_t report_id, uint8_t report_type, - const uint8_t **buffer_ptr, - int *buffer_size) + const uint8_t **buffer_ptr, int *buffer_size) { switch (report_id) { case REPORT_ID_DEVICE_CAPS: diff --git a/chip/stm32/usb_hw.h b/chip/stm32/usb_hw.h index fc186ff7de..511cd9c75a 100644 --- a/chip/stm32/usb_hw.h +++ b/chip/stm32/usb_hw.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,12 +19,11 @@ enum usb_ep_event { #include "usb_dwc_hw.h" #else - /* * The STM32 has dedicated USB RAM visible on the APB1 bus (so all reads & * writes are 16-bits wide). The endpoint tables and the data buffers live in * this RAM. -*/ + */ /* Primitive to access the words in USB RAM */ typedef CONFIG_USB_RAM_ACCESS_TYPE usb_uint; @@ -87,8 +86,8 @@ enum usb_desc_patch_type { * The patches need to be setup before _before_ usb_init is executed (or, at * least, before the first call to memcpy_to_usbram_ep0_patch). */ -void set_descriptor_patch(enum usb_desc_patch_type type, - const void *address, uint16_t data); +void set_descriptor_patch(enum usb_desc_patch_type type, const void *address, + uint16_t data); /* Copy to USB ram, applying patches to src as required. */ void *memcpy_to_usbram_ep0_patch(const void *src, size_t n); @@ -106,44 +105,42 @@ void *memcpy_to_usbram_ep0_patch(const void *src, size_t n); #define _EP_RX_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _rx_typecheck) #define _EP_EVENT_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _evt_typecheck) -#define USB_DECLARE_EP(num, tx_handler, rx_handler, evt_handler) \ - void _EP_TX_HANDLER(num)(void) \ - __attribute__ ((alias(STRINGIFY(tx_handler)))); \ - void _EP_RX_HANDLER(num)(void) \ - __attribute__ ((alias(STRINGIFY(rx_handler)))); \ - void _EP_EVENT_HANDLER(num)(enum usb_ep_event evt) \ - __attribute__ ((alias(STRINGIFY(evt_handler)))); \ - static __unused void \ - (*_EP_TX_HANDLER_TYPECHECK(num))(void) = tx_handler; \ - static __unused void \ - (*_EP_RX_HANDLER_TYPECHECK(num))(void) = rx_handler; \ - static __unused void \ - (*_EP_EVENT_HANDLER_TYPECHECK(num))(enum usb_ep_event evt)\ - = evt_handler +#define USB_DECLARE_EP(num, tx_handler, rx_handler, evt_handler) \ + void _EP_TX_HANDLER(num)(void) \ + __attribute__((alias(STRINGIFY(tx_handler)))); \ + void _EP_RX_HANDLER(num)(void) \ + __attribute__((alias(STRINGIFY(rx_handler)))); \ + void _EP_EVENT_HANDLER(num)(enum usb_ep_event evt) \ + __attribute__((alias(STRINGIFY(evt_handler)))); \ + static __unused void (*_EP_TX_HANDLER_TYPECHECK(num))(void) = \ + tx_handler; \ + static __unused void (*_EP_RX_HANDLER_TYPECHECK(num))(void) = \ + rx_handler; \ + static __unused void (*_EP_EVENT_HANDLER_TYPECHECK(num))( \ + enum usb_ep_event evt) = evt_handler /* arrays with all endpoint callbacks */ -extern void (*usb_ep_tx[]) (void); -extern void (*usb_ep_rx[]) (void); -extern void (*usb_ep_event[]) (enum usb_ep_event evt); +extern void (*usb_ep_tx[])(void); +extern void (*usb_ep_rx[])(void); +extern void (*usb_ep_event[])(enum usb_ep_event evt); /* array with interface-specific control request callbacks */ -extern int (*usb_iface_request[]) (usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx); +extern int (*usb_iface_request[])(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx); /* * Interface handler returns -1 on error, 0 if it wrote the last chunk of data, * or 1 if more data needs to be transferred on the next control request. */ #define _IFACE_HANDLER(num) CONCAT3(iface_, num, _request) -#define USB_DECLARE_IFACE(num, handler) \ - int _IFACE_HANDLER(num)(usb_uint *ep0_buf_rx, \ - usb_uint *epo_buf_tx) \ - __attribute__ ((alias(STRINGIFY(handler)))); +#define USB_DECLARE_IFACE(num, handler) \ + int _IFACE_HANDLER(num)(usb_uint * ep0_buf_rx, usb_uint * epo_buf_tx) \ + __attribute__((alias(STRINGIFY(handler)))); #endif /* * In and out buffer sizes for host command over USB. */ -#define USBHC_MAX_REQUEST_SIZE 0x200 +#define USBHC_MAX_REQUEST_SIZE 0x200 #define USBHC_MAX_RESPONSE_SIZE 0x100 -#endif /* __CROS_EC_USB_HW_H */ +#endif /* __CROS_EC_USB_HW_H */ diff --git a/chip/stm32/usb_isochronous.c b/chip/stm32/usb_isochronous.c index 792507aa75..ad20b6d1ca 100644 --- a/chip/stm32/usb_isochronous.c +++ b/chip/stm32/usb_isochronous.c @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -13,10 +13,9 @@ #include "usb_hw.h" #include "usb_isochronous.h" - /* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USB, format, ##args) /* * Currently, we only support TX direction for USB isochronous transfer. @@ -65,8 +64,7 @@ static usb_uint *get_app_addr(struct usb_isochronous_config const *config, * Sets number of bytes written to application buffer. */ static void set_app_count(struct usb_isochronous_config const *config, - int dtog_value, - usb_uint count) + int dtog_value, usb_uint count) { if (dtog_value) btable_ep[config->endpoint].tx_count = count; @@ -74,13 +72,9 @@ static void set_app_count(struct usb_isochronous_config const *config, btable_ep[config->endpoint].rx_count = count; } -int usb_isochronous_write_buffer( - struct usb_isochronous_config const *config, - const uint8_t *src, - size_t n, - size_t dst_offset, - int *buffer_id, - int commit) +int usb_isochronous_write_buffer(struct usb_isochronous_config const *config, + const uint8_t *src, size_t n, + size_t dst_offset, int *buffer_id, int commit) { int dtog_value = get_tx_dtog(config); usb_uint *buffer = get_app_addr(config, dtog_value); @@ -142,15 +136,13 @@ void usb_isochronous_tx(struct usb_isochronous_config const *config) } int usb_isochronous_iface_handler(struct usb_isochronous_config const *config, - usb_uint *ep0_buf_rx, - usb_uint *ep0_buf_tx) + usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx) { int ret = -1; - if (ep0_buf_rx[0] == (USB_DIR_OUT | - USB_TYPE_STANDARD | - USB_RECIP_INTERFACE | - USB_REQ_SET_INTERFACE << 8)) { + if (ep0_buf_rx[0] == + (USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE | + USB_REQ_SET_INTERFACE << 8)) { ret = config->set_interface(ep0_buf_rx[1], ep0_buf_rx[2]); if (ret == 0) { diff --git a/chip/stm32/usb_isochronous.h b/chip/stm32/usb_isochronous.h index efa4d94ab4..a96b6db876 100644 --- a/chip/stm32/usb_isochronous.h +++ b/chip/stm32/usb_isochronous.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -75,13 +75,9 @@ struct usb_isochronous_config; * * @return -EC_ERROR_CODE on failure, or number of bytes written on success. */ -int usb_isochronous_write_buffer( - struct usb_isochronous_config const *config, - const uint8_t *src, - size_t n, - size_t dst_offset, - int *buffer_id, - int commit); +int usb_isochronous_write_buffer(struct usb_isochronous_config const *config, + const uint8_t *src, size_t n, + size_t dst_offset, int *buffer_id, int commit); struct usb_isochronous_config { int endpoint; @@ -110,21 +106,15 @@ struct usb_isochronous_config { }; /* Define an USB isochronous interface */ -#define USB_ISOCHRONOUS_CONFIG_FULL(NAME, \ - INTERFACE, \ - INTERFACE_CLASS, \ - INTERFACE_SUBCLASS, \ - INTERFACE_PROTOCOL, \ - INTERFACE_NAME, \ - ENDPOINT, \ - TX_SIZE, \ - TX_CALLBACK, \ - SET_INTERFACE, \ - NUM_EXTRA_ENDPOINTS) \ - BUILD_ASSERT(TX_SIZE > 0); \ - BUILD_ASSERT((TX_SIZE < 64 && (TX_SIZE & 0x01) == 0) || \ - (TX_SIZE < 1024 && (TX_SIZE & 0x1f) == 0)); \ - /* Declare buffer */ \ +#define USB_ISOCHRONOUS_CONFIG_FULL(NAME, INTERFACE, INTERFACE_CLASS, \ + INTERFACE_SUBCLASS, INTERFACE_PROTOCOL, \ + INTERFACE_NAME, ENDPOINT, TX_SIZE, \ + TX_CALLBACK, SET_INTERFACE, \ + NUM_EXTRA_ENDPOINTS) \ + BUILD_ASSERT(TX_SIZE > 0); \ + BUILD_ASSERT((TX_SIZE < 64 && (TX_SIZE & 0x01) == 0) || \ + (TX_SIZE < 1024 && (TX_SIZE & 0x1f) == 0)); \ + /* Declare buffer */ \ static usb_uint CONCAT2(NAME, _ep_tx_buffer_0)[TX_SIZE / 2] __usb_ram; \ static usb_uint CONCAT2(NAME, _ep_tx_buffer_1)[TX_SIZE / 2] __usb_ram; \ struct usb_isochronous_config const NAME = { \ @@ -136,62 +126,57 @@ struct usb_isochronous_config { CONCAT2(NAME, _ep_tx_buffer_0), \ CONCAT2(NAME, _ep_tx_buffer_1), \ }, \ - }; \ - const struct usb_interface_descriptor \ - USB_IFACE_DESC(INTERFACE) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 0, \ - .bNumEndpoints = 0, \ - .bInterfaceClass = INTERFACE_CLASS, \ - .bInterfaceSubClass = INTERFACE_SUBCLASS, \ - .bInterfaceProtocol = INTERFACE_PROTOCOL, \ - .iInterface = INTERFACE_NAME, \ - }; \ - const struct usb_interface_descriptor \ - USB_CONF_DESC(CONCAT3(iface, INTERFACE, _1iface)) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 1, \ - .bNumEndpoints = 1 + NUM_EXTRA_ENDPOINTS, \ - .bInterfaceClass = INTERFACE_CLASS, \ - .bInterfaceSubClass = INTERFACE_SUBCLASS, \ - .bInterfaceProtocol = INTERFACE_PROTOCOL, \ - .iInterface = INTERFACE_NAME, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 0) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = 0x80 | ENDPOINT, \ - .bmAttributes = 0x01 /* Isochronous IN */, \ - .wMaxPacketSize = TX_SIZE, \ - .bInterval = 1, \ - }; \ - static void CONCAT2(NAME, _ep_tx)(void) \ - { \ - usb_isochronous_tx(&NAME); \ - } \ - static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt) \ - { \ - usb_isochronous_event(&NAME, evt); \ - } \ - static int CONCAT2(NAME, _handler)(usb_uint *rx, usb_uint *tx) \ - { \ - return usb_isochronous_iface_handler(&NAME, rx, tx); \ - } \ - USB_DECLARE_IFACE(INTERFACE, CONCAT2(NAME, _handler)); \ - USB_DECLARE_EP(ENDPOINT, \ - CONCAT2(NAME, _ep_tx), \ - CONCAT2(NAME, _ep_tx), \ - CONCAT2(NAME, _ep_event)); \ + }; \ + const struct usb_interface_descriptor USB_IFACE_DESC(INTERFACE) = { \ + .bLength = USB_DT_INTERFACE_SIZE, \ + .bDescriptorType = USB_DT_INTERFACE, \ + .bInterfaceNumber = INTERFACE, \ + .bAlternateSetting = 0, \ + .bNumEndpoints = 0, \ + .bInterfaceClass = INTERFACE_CLASS, \ + .bInterfaceSubClass = INTERFACE_SUBCLASS, \ + .bInterfaceProtocol = INTERFACE_PROTOCOL, \ + .iInterface = INTERFACE_NAME, \ + }; \ + const struct usb_interface_descriptor USB_CONF_DESC( \ + CONCAT3(iface, INTERFACE, _1iface)) = { \ + .bLength = USB_DT_INTERFACE_SIZE, \ + .bDescriptorType = USB_DT_INTERFACE, \ + .bInterfaceNumber = INTERFACE, \ + .bAlternateSetting = 1, \ + .bNumEndpoints = 1 + NUM_EXTRA_ENDPOINTS, \ + .bInterfaceClass = INTERFACE_CLASS, \ + .bInterfaceSubClass = INTERFACE_SUBCLASS, \ + .bInterfaceProtocol = INTERFACE_PROTOCOL, \ + .iInterface = INTERFACE_NAME, \ + }; \ + const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 0) = { \ + .bLength = USB_DT_ENDPOINT_SIZE, \ + .bDescriptorType = USB_DT_ENDPOINT, \ + .bEndpointAddress = 0x80 | ENDPOINT, \ + .bmAttributes = 0x01 /* Isochronous IN */, \ + .wMaxPacketSize = TX_SIZE, \ + .bInterval = 1, \ + }; \ + static void CONCAT2(NAME, _ep_tx)(void) \ + { \ + usb_isochronous_tx(&NAME); \ + } \ + static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt) \ + { \ + usb_isochronous_event(&NAME, evt); \ + } \ + static int CONCAT2(NAME, _handler)(usb_uint * rx, usb_uint * tx) \ + { \ + return usb_isochronous_iface_handler(&NAME, rx, tx); \ + } \ + USB_DECLARE_IFACE(INTERFACE, CONCAT2(NAME, _handler)); \ + USB_DECLARE_EP(ENDPOINT, CONCAT2(NAME, _ep_tx), CONCAT2(NAME, _ep_tx), \ + CONCAT2(NAME, _ep_event)); void usb_isochronous_tx(struct usb_isochronous_config const *config); void usb_isochronous_event(struct usb_isochronous_config const *config, enum usb_ep_event event); int usb_isochronous_iface_handler(struct usb_isochronous_config const *config, - usb_uint *ep0_buf_rx, - usb_uint *ep0_buf_tx); + usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx); #endif /* __CROS_EC_USB_ISOCHRONOUS_H */ diff --git a/chip/stm32/usb_pd_phy.c b/chip/stm32/usb_pd_phy.c index 21484b1a88..9536301863 100644 --- a/chip/stm32/usb_pd_phy.c +++ b/chip/stm32/usb_pd_phy.c @@ -1,9 +1,10 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ #include "adc.h" +#include "builtin/assert.h" #include "clock.h" #include "common.h" #include "console.h" @@ -21,8 +22,8 @@ #include "usb_pd_config.h" #ifdef CONFIG_COMMON_RUNTIME -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #else #define CPRINTF(format, args...) #define CPRINTS(format, args...) @@ -38,7 +39,7 @@ */ #define PD_BIT_LEN 429 -#define PD_MAX_RAW_SIZE (PD_BIT_LEN*2) +#define PD_MAX_RAW_SIZE (PD_BIT_LEN * 2) /* maximum number of consecutive similar bits with Biphase Mark Coding */ #define MAX_BITS 2 @@ -46,12 +47,12 @@ /* alternating bit sequence used for packet preamble : 00 10 11 01 00 .. */ #define PD_PREAMBLE 0xB4B4B4B4 /* starts with 0, ends with 1 */ -#define TX_CLOCK_DIV ((clock_get_freq() / (2*PD_DATARATE))) +#define TX_CLOCK_DIV ((clock_get_freq() / (2 * PD_DATARATE))) /* threshold for 1 300-khz period */ #define PERIOD 4 -#define NB_PERIOD(from, to) ((((to) - (from) + (PERIOD/2)) & 0xFF) / PERIOD) -#define PERIOD_THRESHOLD ((PERIOD + 2*PERIOD) / 2) +#define NB_PERIOD(from, to) ((((to) - (from) + (PERIOD / 2)) & 0xFF) / PERIOD) +#define PERIOD_THRESHOLD ((PERIOD + 2 * PERIOD) / 2) static struct pd_physical { /* samples for the PD messages */ @@ -73,8 +74,8 @@ static struct pd_physical { } pd_phy[CONFIG_USB_PD_PORT_MAX_COUNT]; /* keep track of RX edge timing in order to trigger receive */ -static timestamp_t - rx_edge_ts[CONFIG_USB_PD_PORT_MAX_COUNT][PD_RX_TRANSITION_COUNT]; +static timestamp_t rx_edge_ts[CONFIG_USB_PD_PORT_MAX_COUNT] + [PD_RX_TRANSITION_COUNT]; static int rx_edge_ts_idx[CONFIG_USB_PD_PORT_MAX_COUNT]; /* keep track of transmit polarity for DMA interrupt */ @@ -95,8 +96,8 @@ static int wait_bits(int port, int nb) avail = dma_bytes_done(rx, PD_MAX_RAW_SIZE); if (avail < nb) { /* no received yet ... */ - while ((dma_bytes_done(rx, PD_MAX_RAW_SIZE) < nb) - && !(pd_phy[port].tim_rx->sr & 4)) + while ((dma_bytes_done(rx, PD_MAX_RAW_SIZE) < nb) && + !(pd_phy[port].tim_rx->sr & 4)) ; /* optimized for latency, not CPU usage ... */ if (dma_bytes_done(rx, PD_MAX_RAW_SIZE) < nb) { CPRINTS("PD TMOUT RX %d/%d", @@ -117,8 +118,8 @@ int pd_dequeue_bits(int port, int off, int len, uint32_t *val) w = wait_bits(port, off + 2); if (w < 0) goto stream_err; - cnt = samples[off] - samples[off-1]; - if (!cnt || (cnt > 3*PERIOD)) + cnt = samples[off] - samples[off - 1]; + if (!cnt || (cnt > 3 * PERIOD)) goto stream_err; off++; if (cnt <= PERIOD_THRESHOLD) { @@ -127,20 +128,22 @@ int pd_dequeue_bits(int port, int off, int len, uint32_t *val) if (w < 0) goto stream_err; */ - cnt = samples[off] - samples[off-1]; - if (cnt > PERIOD_THRESHOLD) + cnt = samples[off] - samples[off - 1]; + if (cnt > PERIOD_THRESHOLD) goto stream_err; off++; } /* enqueue the bit of the last period */ - pd_phy[port].d_last = (pd_phy[port].d_last >> 1) - | (cnt <= PERIOD_THRESHOLD ? 0x80000000 : 0); + pd_phy[port].d_last = + (pd_phy[port].d_last >> 1) | + (cnt <= PERIOD_THRESHOLD ? 0x80000000 : 0); pd_phy[port].d_lastlen++; } if (off < PD_MAX_RAW_SIZE) { - *val = (pd_phy[port].d_last << (pd_phy[port].d_lastlen - len)) - >> (32 - len); + *val = (pd_phy[port].d_last + << (pd_phy[port].d_lastlen - len)) >> + (32 - len); pd_phy[port].d_lastlen -= len; return off; } else { @@ -168,7 +171,7 @@ int pd_find_preamble(int port) /* wait if the bit is not received yet ... */ if (PD_MAX_RAW_SIZE - rx->cndtr < bit + 1) { while ((PD_MAX_RAW_SIZE - rx->cndtr < bit + 1) && - !(pd_phy[port].tim_rx->sr & 4)) + !(pd_phy[port].tim_rx->sr & 4)) ; if (pd_phy[port].tim_rx->sr & 4) { CPRINTS("PD TMOUT RX %d/%d", @@ -176,7 +179,7 @@ int pd_find_preamble(int port) return -1; } } - cnt = vals[bit] - vals[bit-1]; + cnt = vals[bit] - vals[bit - 1]; all = (all >> 1) | (cnt <= PERIOD_THRESHOLD ? BIT(31) : 0); if (all == 0x36db6db6) return bit - 1; /* should be SYNC-1 */ @@ -198,7 +201,7 @@ int pd_write_preamble(int port) msg[2] = PD_PREAMBLE; msg[3] = PD_PREAMBLE; pd_phy[port].b_toggle = 0x3FF; /* preamble ends with 1 */ - return 2*64; + return 2 * 64; } int pd_write_sym(int port, int bit_off, uint32_t val10) @@ -214,10 +217,10 @@ int pd_write_sym(int port, int bit_off, uint32_t val10) msg[word_idx] |= val << bit_idx; } else { msg[word_idx] |= val << bit_idx; - msg[word_idx+1] = val >> (32 - bit_idx); + msg[word_idx + 1] = val >> (32 - bit_idx); /* side effect: clear the new word when starting it */ } - return bit_off + 5*2; + return bit_off + 5 * 2; } int pd_write_last_edge(int port, int bit_off) @@ -239,7 +242,7 @@ int pd_write_last_edge(int port, int bit_off) } } /* ensure that the trailer is 0 */ - msg[word_idx+1] = 0; + msg[word_idx + 1] = 0; return bit_off + 3; } @@ -252,15 +255,15 @@ void pd_dump_packet(int port, const char *msg) CPRINTF("ERR %s:\n000:- ", msg); /* Packet debug output */ - for (bit = 1; bit < PD_MAX_RAW_SIZE; bit++) { - int cnt = NB_PERIOD(vals[bit-1], vals[bit]); + for (bit = 1; bit < PD_MAX_RAW_SIZE; bit++) { + int cnt = NB_PERIOD(vals[bit - 1], vals[bit]); if ((bit & 31) == 0) CPRINTF("\n%03d:", bit); CPRINTF("%1d ", cnt); } CPRINTF("><\n"); cflush(); - for (bit = 0; bit < PD_MAX_RAW_SIZE; bit++) { + for (bit = 0; bit < PD_MAX_RAW_SIZE; bit++) { if ((bit & 31) == 0) CPRINTF("\n%03d:", bit); CPRINTF("%02x ", vals[bit]); @@ -280,9 +283,9 @@ void pd_tx_spi_init(int port) spi->cr2 = STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_DATASIZE(8); /* Enable the slave SPI: LSB first, force NSS, TX only, CPHA */ - spi->cr1 = STM32_SPI_CR1_SPE | STM32_SPI_CR1_LSBFIRST - | STM32_SPI_CR1_SSM | STM32_SPI_CR1_BIDIMODE - | STM32_SPI_CR1_BIDIOE | STM32_SPI_CR1_CPHA; + spi->cr1 = STM32_SPI_CR1_SPE | STM32_SPI_CR1_LSBFIRST | + STM32_SPI_CR1_SSM | STM32_SPI_CR1_BIDIMODE | + STM32_SPI_CR1_BIDIOE | STM32_SPI_CR1_CPHA; } static void tx_dma_done(void *data) @@ -330,9 +333,8 @@ int pd_start_tx(int port, int polarity, int bit_len) pd_phy[port].tim_tx->cnt = TX_CLOCK_DIV - 1; /* update DMA configuration */ - dma_prepare_tx(&(pd_phy[port].dma_tx_option), - DIV_ROUND_UP(bit_len, 8), - pd_phy[port].raw_samples); + dma_prepare_tx(&(pd_phy[port].dma_tx_option), DIV_ROUND_UP(bit_len, 8), + pd_phy[port].raw_samples); /* Flush data in write buffer so that DMA can get the latest data */ asm volatile("dmb;"); @@ -343,8 +345,7 @@ int pd_start_tx(int port, int polarity, int bit_len) if (!(pd_phy[port].dma_tx_option.flags & STM32_DMA_CCR_CIRC)) { /* Only enable interrupt if not in circular mode */ dma_enable_tc_interrupt_callback(DMAC_SPI_TX(port), - &tx_dma_done, - (void *)port); + &tx_dma_done, (void *)port); } #endif dma_go(tx); @@ -401,9 +402,10 @@ void pd_rx_start(int port) { /* start sampling the edges on the CC line using the RX timer */ dma_start_rx(&(pd_phy[port].dma_tim_option), PD_MAX_RAW_SIZE, - pd_phy[port].raw_samples); + pd_phy[port].raw_samples); /* enable TIM2 DMA requests */ - pd_phy[port].tim_rx->egr = 0x0001; /* reset counter / reload PSC */; + pd_phy[port].tim_rx->egr = 0x0001; /* reset counter / reload PSC */ + ; pd_phy[port].tim_rx->sr = 0; /* clear overflows */ pd_phy[port].tim_rx->cr1 |= 1; } @@ -441,8 +443,8 @@ void pd_rx_disable_monitoring(int port) uint64_t get_time_since_last_edge(int port) { int prev_idx = (rx_edge_ts_idx[port] == 0) ? - PD_RX_TRANSITION_COUNT - 1 : - rx_edge_ts_idx[port] - 1; + PD_RX_TRANSITION_COUNT - 1 : + rx_edge_ts_idx[port] - 1; return get_time().val - rx_edge_ts[port][prev_idx].val; } @@ -467,11 +469,12 @@ void pd_rx_handler(void) if (pending & EXTI_COMP_MASK(i)) { rx_edge_ts[i][rx_edge_ts_idx[i]].val = get_time().val; next_idx = (rx_edge_ts_idx[i] == - PD_RX_TRANSITION_COUNT - 1) ? - 0 : rx_edge_ts_idx[i] + 1; + PD_RX_TRANSITION_COUNT - 1) ? + 0 : + rx_edge_ts_idx[i] + 1; -#if defined(CONFIG_LOW_POWER_IDLE) && \ -defined(CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED) +#if defined(CONFIG_LOW_POWER_IDLE) && \ + defined(CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED) /* * Do not deep sleep while waiting for more edges. For * most boards, sleep is already disabled due to being @@ -487,8 +490,8 @@ defined(CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED) * time, then trigger RX start. */ if ((rx_edge_ts[i][rx_edge_ts_idx[i]].val - - rx_edge_ts[i][next_idx].val) - < PD_RX_TRANSITION_WINDOW) { + rx_edge_ts[i][next_idx].val) < + PD_RX_TRANSITION_WINDOW) { /* start sampling */ pd_rx_start(i); /* @@ -535,7 +538,7 @@ void pd_hw_init_rx(int port) phy->dma_tim_option.channel = DMAC_TIM_RX(port); phy->dma_tim_option.periph = (void *)(TIM_RX_CCR_REG(port)); phy->dma_tim_option.flags = STM32_DMA_CCR_MSIZE_8_BIT | - STM32_DMA_CCR_PSIZE_16_BIT; + STM32_DMA_CCR_PSIZE_16_BIT; /* --- set counter for RX timing : 2.4Mhz rate, free-running --- */ __hw_timer_enable_clock(TIM_CLOCK_PD_RX(port), 1); @@ -561,7 +564,8 @@ void pd_hw_init_rx(int port) phy->tim_rx->ccer = 0xB << ((TIM_RX_CCR_IDX(port) - 1) * 4); /* configure DMA request on CCRx update */ - phy->tim_rx->dier |= 1 << (8 + TIM_RX_CCR_IDX(port)); /* CCxDE */; + phy->tim_rx->dier |= 1 << (8 + TIM_RX_CCR_IDX(port)); /* CCxDE */ + ; /* set prescaler to /26 (F=1.2Mhz, T=0.8us) */ phy->tim_rx->psc = (clock_get_freq() / 2400000) - 1; /* Reload the pre-scaler and reset the counter (clear CCRx) */ @@ -590,18 +594,15 @@ void pd_hw_init_rx(int port) clock_wait_bus_cycles(BUS_APB, 1); /* currently in hi-speed mode : TODO revisit later, INM = PA0(INM6) */ STM32_COMP_CSR = STM32_COMP_CMP1MODE_LSPEED | - STM32_COMP_CMP1INSEL_INM6 | - CMP1OUTSEL | - STM32_COMP_CMP1HYST_HI | - STM32_COMP_CMP2MODE_LSPEED | - STM32_COMP_CMP2INSEL_INM6 | - CMP2OUTSEL | + STM32_COMP_CMP1INSEL_INM6 | CMP1OUTSEL | + STM32_COMP_CMP1HYST_HI | STM32_COMP_CMP2MODE_LSPEED | + STM32_COMP_CMP2INSEL_INM6 | CMP2OUTSEL | STM32_COMP_CMP2HYST_HI; #elif defined(CHIP_FAMILY_STM32L) STM32_RCC_APB1ENR |= BIT(31); /* turn on COMP */ - STM32_COMP_CSR = STM32_COMP_OUTSEL_TIM2_IC4 | STM32_COMP_INSEL_DAC_OUT1 - | STM32_COMP_SPEED_FAST; + STM32_COMP_CSR = STM32_COMP_OUTSEL_TIM2_IC4 | + STM32_COMP_INSEL_DAC_OUT1 | STM32_COMP_SPEED_FAST; /* route PB4 to COMP input2 through GR6_1 bit 4 (or PB5->GR6_2 bit 5) */ STM32_RI_ASCR2 |= BIT(4); #else @@ -638,9 +639,9 @@ void pd_hw_init(int port, enum pd_power_role role) phy->dma_tx_option.channel = DMAC_SPI_TX(port); phy->dma_tx_option.periph = (void *)&SPI_REGS(port)->dr; phy->dma_tx_option.flags = STM32_DMA_CCR_MSIZE_8_BIT | - STM32_DMA_CCR_PSIZE_8_BIT; + STM32_DMA_CCR_PSIZE_8_BIT; dma_prepare_tx(&(phy->dma_tx_option), PD_MAX_RAW_SIZE, - phy->raw_samples); + phy->raw_samples); /* configure registers used for timers */ phy->tim_tx = (void *)TIM_REG_TX(port); @@ -680,5 +681,5 @@ void pd_hw_init(int port, enum pd_power_role role) void pd_set_clock(int port, int freq) { - pd_phy[port].tim_tx->arr = clock_get_freq() / (2*freq); + pd_phy[port].tim_tx->arr = clock_get_freq() / (2 * freq); } diff --git a/chip/stm32/usb_power.c b/chip/stm32/usb_power.c index 3e159d646f..589767f15c 100644 --- a/chip/stm32/usb_power.c +++ b/chip/stm32/usb_power.c @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,7 +14,7 @@ #include "usb_power.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) static int usb_power_init_inas(struct usb_power_config const *config); static int usb_power_read(struct usb_power_config const *config); @@ -42,16 +42,15 @@ void usb_power_deferred_tx(struct usb_power_config const *config) state->reports_xmit_active = state->reports_tail; /* Wait for the next command */ - usb_read_ep(config->endpoint, - config->ep->out_databuffer_max, - config->ep->out_databuffer); + usb_read_ep(config->endpoint, config->ep->out_databuffer_max, + config->ep->out_databuffer); return; } } /* Reset stream */ void usb_power_event(struct usb_power_config const *config, - enum usb_ep_event evt) + enum usb_ep_event evt) { if (evt != USB_EVENT_RESET) return; @@ -68,15 +67,15 @@ void usb_power_event(struct usb_power_config const *config, hook_call_deferred(config->ep->tx_deferred, 0); } - /* Write one or more power records to USB */ static int usb_power_write_line(struct usb_power_config const *config) { struct usb_power_state *state = config->state; - struct usb_power_report *r = (struct usb_power_report *)( - state->reports_data_area + - (USB_POWER_RECORD_SIZE(state->ina_count) - * state->reports_tail)); + struct usb_power_report *r = + (struct usb_power_report *)(state->reports_data_area + + (USB_POWER_RECORD_SIZE( + state->ina_count) * + state->reports_tail)); /* status + size + timestamps + power list */ size_t bytes = USB_POWER_RECORD_SIZE(state->ina_count); @@ -89,12 +88,12 @@ static int usb_power_write_line(struct usb_power_config const *config) recordcount = config->state->reports_head - config->state->reports_tail; else - recordcount = state->max_cached - - config->state->reports_tail; + recordcount = + state->max_cached - config->state->reports_tail; state->reports_xmit_active = state->reports_tail; - state->reports_tail = (state->reports_tail + recordcount) % - state->max_cached; + state->reports_tail = + (state->reports_tail + recordcount) % state->max_cached; usb_write_ep(config->endpoint, bytes * recordcount, r); return bytes; @@ -103,7 +102,6 @@ static int usb_power_write_line(struct usb_power_config const *config) return 0; } - static int usb_power_state_reset(struct usb_power_config const *config) { struct usb_power_state *state = config->state; @@ -117,7 +115,6 @@ static int usb_power_state_reset(struct usb_power_config const *config) return USB_POWER_SUCCESS; } - static int usb_power_state_stop(struct usb_power_config const *config) { struct usb_power_state *state = config->state; @@ -137,8 +134,6 @@ static int usb_power_state_stop(struct usb_power_config const *config) return USB_POWER_SUCCESS; } - - static int usb_power_state_start(struct usb_power_config const *config, union usb_power_command_data *cmd, int count) { @@ -182,13 +177,12 @@ static int usb_power_state_start(struct usb_power_config const *config, return USB_POWER_SUCCESS; } - static int usb_power_state_settime(struct usb_power_config const *config, - union usb_power_command_data *cmd, int count) + union usb_power_command_data *cmd, int count) { if (count != sizeof(struct usb_power_command_settime)) { - CPRINTS("[SETTIME] Error: count %d is not %d", - (int)count, sizeof(struct usb_power_command_settime)); + CPRINTS("[SETTIME] Error: count %d is not %d", (int)count, + sizeof(struct usb_power_command_settime)); return USB_POWER_ERROR_READ_SIZE; } @@ -201,9 +195,8 @@ static int usb_power_state_settime(struct usb_power_config const *config, return USB_POWER_SUCCESS; } - static int usb_power_state_addina(struct usb_power_config const *config, - union usb_power_command_data *cmd, int count) + union usb_power_command_data *cmd, int count) { struct usb_power_state *state = config->state; struct usb_power_ina_cfg *ina; @@ -217,8 +210,8 @@ static int usb_power_state_addina(struct usb_power_config const *config, } if (count != sizeof(struct usb_power_command_addina)) { - CPRINTS("[ADDINA] Error count %d is not %d", - (int)count, sizeof(struct usb_power_command_addina)); + CPRINTS("[ADDINA] Error count %d is not %d", (int)count, + sizeof(struct usb_power_command_addina)); return USB_POWER_ERROR_READ_SIZE; } @@ -286,8 +279,8 @@ static int usb_power_read(struct usb_power_config const *config) * If there is a USB packet waiting we process it and generate a * response. */ - uint8_t count = rx_ep_pending(config->endpoint); - uint8_t result = USB_POWER_SUCCESS; + uint8_t count = rx_ep_pending(config->endpoint); + uint8_t result = USB_POWER_SUCCESS; union usb_power_command_data *cmd = (union usb_power_command_data *)config->ep->out_databuffer; @@ -314,14 +307,14 @@ static int usb_power_read(struct usb_power_config const *config) result = usb_power_state_start(config, cmd, count); if (result == USB_POWER_SUCCESS) { /* Send back actual integration time. */ - ep->in_databuffer[1] = - (state->integration_us >> 0) & 0xff; - ep->in_databuffer[2] = - (state->integration_us >> 8) & 0xff; - ep->in_databuffer[3] = - (state->integration_us >> 16) & 0xff; - ep->in_databuffer[4] = - (state->integration_us >> 24) & 0xff; + ep->in_databuffer[1] = (state->integration_us >> 0) & + 0xff; + ep->in_databuffer[2] = (state->integration_us >> 8) & + 0xff; + ep->in_databuffer[3] = (state->integration_us >> 16) & + 0xff; + ep->in_databuffer[4] = (state->integration_us >> 24) & + 0xff; in_msgsize += 4; } break; @@ -363,8 +356,6 @@ static int usb_power_read(struct usb_power_config const *config) return EC_SUCCESS; } - - /****************************************************************************** * INA231 interface. * List the registers and fields here. @@ -374,20 +365,19 @@ static int usb_power_read(struct usb_power_config const *config) #define INA231_REG_CONF 0 #define INA231_REG_RSHV 1 #define INA231_REG_BUSV 2 -#define INA231_REG_PWR 3 +#define INA231_REG_PWR 3 #define INA231_REG_CURR 4 -#define INA231_REG_CAL 5 -#define INA231_REG_EN 6 - - -#define INA231_CONF_AVG(val) (((int)(val & 0x7)) << 9) -#define INA231_CONF_BUS_TIME(val) (((int)(val & 0x7)) << 6) -#define INA231_CONF_SHUNT_TIME(val) (((int)(val & 0x7)) << 3) -#define INA231_CONF_MODE(val) (((int)(val & 0x7)) << 0) -#define INA231_MODE_OFF 0x0 -#define INA231_MODE_SHUNT 0x5 -#define INA231_MODE_BUS 0x6 -#define INA231_MODE_BOTH 0x7 +#define INA231_REG_CAL 5 +#define INA231_REG_EN 6 + +#define INA231_CONF_AVG(val) (((int)(val & 0x7)) << 9) +#define INA231_CONF_BUS_TIME(val) (((int)(val & 0x7)) << 6) +#define INA231_CONF_SHUNT_TIME(val) (((int)(val & 0x7)) << 3) +#define INA231_CONF_MODE(val) (((int)(val & 0x7)) << 0) +#define INA231_MODE_OFF 0x0 +#define INA231_MODE_SHUNT 0x5 +#define INA231_MODE_BUS 0x6 +#define INA231_MODE_BOTH 0x7 int reg_type_mapping(enum usb_power_ina_type ina_type) { @@ -411,36 +401,32 @@ uint16_t ina2xx_readagain(uint8_t port, uint16_t addr_flags) int res; uint16_t val; - res = i2c_xfer(port, addr_flags, - NULL, 0, (uint8_t *)&val, sizeof(uint16_t)); + res = i2c_xfer(port, addr_flags, NULL, 0, (uint8_t *)&val, + sizeof(uint16_t)); if (res) { - CPRINTS("INA2XX I2C readagain failed p:%d a:%02x", - (int)port, (int)I2C_STRIP_FLAGS(addr_flags)); + CPRINTS("INA2XX I2C readagain failed p:%d a:%02x", (int)port, + (int)I2C_STRIP_FLAGS(addr_flags)); return 0x0bad; } return (val >> 8) | ((val & 0xff) << 8); } - -uint16_t ina2xx_read(uint8_t port, uint16_t addr_flags, - uint8_t reg) +uint16_t ina2xx_read(uint8_t port, uint16_t addr_flags, uint8_t reg) { int res; int val; res = i2c_read16(port, addr_flags, reg, &val); if (res) { - CPRINTS("INA2XX I2C read failed p:%d a:%02x, r:%02x", - (int)port, (int)I2C_STRIP_FLAGS(addr_flags), - (int)reg); + CPRINTS("INA2XX I2C read failed p:%d a:%02x, r:%02x", (int)port, + (int)I2C_STRIP_FLAGS(addr_flags), (int)reg); return 0x0bad; } return (val >> 8) | ((val & 0xff) << 8); } -int ina2xx_write(uint8_t port, uint16_t addr_flags, - uint8_t reg, uint16_t val) +int ina2xx_write(uint8_t port, uint16_t addr_flags, uint8_t reg, uint16_t val) { int res; uint16_t be_val = (val >> 8) | ((val & 0xff) << 8); @@ -451,8 +437,6 @@ int ina2xx_write(uint8_t port, uint16_t addr_flags, return res; } - - /****************************************************************************** * Background tasks * @@ -462,11 +446,10 @@ int ina2xx_write(uint8_t port, uint16_t addr_flags, */ /* INA231 integration and averaging time presets, indexed by register value */ -#define NELEMS(x) (sizeof(x) / sizeof((x)[0])) -static const int average_settings[] = { - 1, 4, 16, 64, 128, 256, 512, 1024}; -static const int conversion_time_us[] = { - 140, 204, 332, 588, 1100, 2116, 4156, 8244}; +#define NELEMS(x) (sizeof(x) / sizeof((x)[0])) +static const int average_settings[] = { 1, 4, 16, 64, 128, 256, 512, 1024 }; +static const int conversion_time_us[] = { 140, 204, 332, 588, + 1100, 2116, 4156, 8244 }; static int usb_power_init_inas(struct usb_power_config const *config) { @@ -491,8 +474,7 @@ static int usb_power_init_inas(struct usb_power_config const *config) /* Find an averaging setting from the INA presets that fits. */ while (avg < (NELEMS(average_settings) - 1)) { if ((conversion_time_us[shunt_time] * - average_settings[avg + 1]) - > target_us) + average_settings[avg + 1]) > target_us) break; avg++; } @@ -507,15 +489,15 @@ static int usb_power_init_inas(struct usb_power_config const *config) #ifdef USB_POWER_VERBOSE { - int conf, cal; - - conf = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_CONF); - cal = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_CAL); - CPRINTS("[CAP] %d (%d,0x%02x): conf:%x, cal:%x", - i, ina->port, I2C_STRIP_FLAGS(ina->addr_flags), - conf, cal); + int conf, cal; + + conf = ina2xx_read(ina->port, ina->addr_flags, + INA231_REG_CONF); + cal = ina2xx_read(ina->port, ina->addr_flags, + INA231_REG_CAL); + CPRINTS("[CAP] %d (%d,0x%02x): conf:%x, cal:%x", i, + ina->port, I2C_STRIP_FLAGS(ina->addr_flags), + conf, cal); } #endif /* @@ -536,54 +518,53 @@ static int usb_power_init_inas(struct usb_power_config const *config) if (ina->scale == 0) return -1; value = (5120000 * 100) / (ina->scale * ina->rs); - ret = ina2xx_write(ina->port, ina->addr_flags, - INA231_REG_CAL, value); + ret = ina2xx_write(ina->port, ina->addr_flags, INA231_REG_CAL, + value); if (ret != EC_SUCCESS) { CPRINTS("[CAP] usb_power_init_inas CAL FAIL: %d", ret); return ret; } #ifdef USB_POWER_VERBOSE { - int actual; + int actual; - actual = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_CAL); - CPRINTS("[CAP] scale: %d uA/div, %d uW/div, cal:%x act:%x", - ina->scale / 100, ina->scale*25/100, value, actual); + actual = ina2xx_read(ina->port, ina->addr_flags, + INA231_REG_CAL); + CPRINTS("[CAP] scale: %d uA/div, %d uW/div, cal:%x act:%x", + ina->scale / 100, ina->scale * 25 / 100, value, + actual); } #endif /* Conversion time, shunt + bus, set average. */ value = INA231_CONF_MODE(INA231_MODE_BOTH) | INA231_CONF_SHUNT_TIME(shunt_time) | - INA231_CONF_BUS_TIME(shunt_time) | - INA231_CONF_AVG(avg); - ret = ina2xx_write(ina->port, ina->addr_flags, - INA231_REG_CONF, value); + INA231_CONF_BUS_TIME(shunt_time) | INA231_CONF_AVG(avg); + ret = ina2xx_write(ina->port, ina->addr_flags, INA231_REG_CONF, + value); if (ret != EC_SUCCESS) { CPRINTS("[CAP] usb_power_init_inas CONF FAIL: %d", ret); return ret; } #ifdef USB_POWER_VERBOSE { - int actual; + int actual; - actual = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_CONF); - CPRINTS("[CAP] %d (%d,0x%02x): conf:%x, act:%x", - i, ina->port, I2C_STRIP_FLAGS(ina->addr_flags), - value, actual); + actual = ina2xx_read(ina->port, ina->addr_flags, + INA231_REG_CONF); + CPRINTS("[CAP] %d (%d,0x%02x): conf:%x, act:%x", i, + ina->port, I2C_STRIP_FLAGS(ina->addr_flags), + value, actual); } #endif #ifdef USB_POWER_VERBOSE { - int busv_mv = - (ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_BUSV) - * 125) / 100; - - CPRINTS("[CAP] %d (%d,0x%02x): busv:%dmv", - i, ina->port, I2C_STRIP_FLAGS(ina->addr_flags), - busv_mv); + int busv_mv = (ina2xx_read(ina->port, ina->addr_flags, + INA231_REG_BUSV) * + 125) / + 100; + + CPRINTS("[CAP] %d (%d,0x%02x): busv:%dmv", i, ina->port, + I2C_STRIP_FLAGS(ina->addr_flags), busv_mv); } #endif /* Initialize read from power register. This register address @@ -600,7 +581,6 @@ static int usb_power_init_inas(struct usb_power_config const *config) return EC_SUCCESS; } - /* * Read each INA's power integration measurement. * @@ -614,19 +594,20 @@ static int usb_power_get_samples(struct usb_power_config const *config) { uint64_t time = get_time().val; struct usb_power_state *state = config->state; - struct usb_power_report *r = (struct usb_power_report *)( - state->reports_data_area + - (USB_POWER_RECORD_SIZE(state->ina_count) - * state->reports_head)); + struct usb_power_report *r = + (struct usb_power_report *)(state->reports_data_area + + (USB_POWER_RECORD_SIZE( + state->ina_count) * + state->reports_head)); struct usb_power_ina_cfg *inas = state->ina_cfg; int i; /* TODO(nsanders): Would we prefer to evict oldest? */ - if (((state->reports_head + 1) % USB_POWER_MAX_CACHED(state->ina_count)) - == state->reports_xmit_active) { - CPRINTS("Overflow! h:%d a:%d t:%d (%d)", - state->reports_head, state->reports_xmit_active, - state->reports_tail, + if (((state->reports_head + 1) % + USB_POWER_MAX_CACHED(state->ina_count)) == + state->reports_xmit_active) { + CPRINTS("Overflow! h:%d a:%d t:%d (%d)", state->reports_head, + state->reports_xmit_active, state->reports_tail, USB_POWER_MAX_CACHED(state->ina_count)); return USB_POWER_ERROR_OVERFLOW; } @@ -650,47 +631,48 @@ static int usb_power_get_samples(struct usb_power_config const *config) */ if (ina->shared) regval = ina2xx_read(ina->port, ina->addr_flags, - reg_type_mapping(ina->type)); + reg_type_mapping(ina->type)); else - regval = ina2xx_readagain(ina->port, - ina->addr_flags); + regval = ina2xx_readagain(ina->port, ina->addr_flags); r->power[i] = regval; #ifdef USB_POWER_VERBOSE { - int current; - int power; - int voltage; - int bvoltage; - - voltage = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_RSHV); - bvoltage = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_BUSV); - current = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_CURR); - power = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_PWR); - { - int uV = ((int)voltage * 25) / 10; - int mV = ((int)bvoltage * 125) / 100; - int uA = (uV * 1000) / ina->rs; - int CuA = (((int)current * ina->scale) / 100); - int uW = (((int)power * ina->scale*25)/100); - - CPRINTS("[CAP] %d (%d,0x%02x): %dmV / %dmO = %dmA", - i, ina->port, I2C_STRIP_FLAGS(ina->addr_flags), - uV/1000, ina->rs, uA/1000); - CPRINTS("[CAP] %duV %dmV %duA %dCuA " - "%duW v:%04x, b:%04x, p:%04x", - uV, mV, uA, CuA, uW, voltage, bvoltage, power); - } + int current; + int power; + int voltage; + int bvoltage; + + voltage = ina2xx_read(ina->port, ina->addr_flags, + INA231_REG_RSHV); + bvoltage = ina2xx_read(ina->port, ina->addr_flags, + INA231_REG_BUSV); + current = ina2xx_read(ina->port, ina->addr_flags, + INA231_REG_CURR); + power = ina2xx_read(ina->port, ina->addr_flags, + INA231_REG_PWR); + { + int uV = ((int)voltage * 25) / 10; + int mV = ((int)bvoltage * 125) / 100; + int uA = (uV * 1000) / ina->rs; + int CuA = (((int)current * ina->scale) / 100); + int uW = (((int)power * ina->scale * 25) / 100); + + CPRINTS("[CAP] %d (%d,0x%02x): %dmV / %dmO = %dmA", + i, ina->port, + I2C_STRIP_FLAGS(ina->addr_flags), + uV / 1000, ina->rs, uA / 1000); + CPRINTS("[CAP] %duV %dmV %duA %dCuA " + "%duW v:%04x, b:%04x, p:%04x", + uV, mV, uA, CuA, uW, voltage, bvoltage, + power); + } } #endif } /* Mark this slot as used. */ state->reports_head = (state->reports_head + 1) % - USB_POWER_MAX_CACHED(state->ina_count); + USB_POWER_MAX_CACHED(state->ina_count); return EC_SUCCESS; } diff --git a/chip/stm32/usb_power.h b/chip/stm32/usb_power.h index 51220691b6..1445fcea0f 100644 --- a/chip/stm32/usb_power.h +++ b/chip/stm32/usb_power.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -38,7 +38,8 @@ * * addina: 0x0002 * +--------+--------------------------+-------------+--------------+-----------+--------+ - * | 0x0002 | 1B: 4b: extender 4b: bus | 1B:INA type | 1B: INA addr | 1B: extra | 4B: Rs | + * | 0x0002 | 1B: 4b: extender 4b: bus | 1B:INA type | 1B: INA addr | 1B: + *extra | 4B: Rs | * +--------+--------------------------+-------------+--------------+-----------+--------+ * * start: 0x0003 @@ -90,40 +91,40 @@ /* 8b status field. */ enum usb_power_error { - USB_POWER_SUCCESS = 0x00, - USB_POWER_ERROR_I2C = 0x01, - USB_POWER_ERROR_OVERFLOW = 0x02, - USB_POWER_ERROR_NOT_SETUP = 0x03, - USB_POWER_ERROR_NOT_CAPTURING = 0x04, - USB_POWER_ERROR_TIMEOUT = 0x05, - USB_POWER_ERROR_BUSY = 0x06, - USB_POWER_ERROR_READ_SIZE = 0x07, - USB_POWER_ERROR_FULL = 0x08, - USB_POWER_ERROR_INVAL = 0x09, - USB_POWER_ERROR_UNKNOWN = 0x80, + USB_POWER_SUCCESS = 0x00, + USB_POWER_ERROR_I2C = 0x01, + USB_POWER_ERROR_OVERFLOW = 0x02, + USB_POWER_ERROR_NOT_SETUP = 0x03, + USB_POWER_ERROR_NOT_CAPTURING = 0x04, + USB_POWER_ERROR_TIMEOUT = 0x05, + USB_POWER_ERROR_BUSY = 0x06, + USB_POWER_ERROR_READ_SIZE = 0x07, + USB_POWER_ERROR_FULL = 0x08, + USB_POWER_ERROR_INVAL = 0x09, + USB_POWER_ERROR_UNKNOWN = 0x80, }; /* 16b command field. */ enum usb_power_command { - USB_POWER_CMD_RESET = 0x0000, - USB_POWER_CMD_STOP = 0x0001, - USB_POWER_CMD_ADDINA = 0x0002, - USB_POWER_CMD_START = 0x0003, - USB_POWER_CMD_NEXT = 0x0004, - USB_POWER_CMD_SETTIME = 0x0005, + USB_POWER_CMD_RESET = 0x0000, + USB_POWER_CMD_STOP = 0x0001, + USB_POWER_CMD_ADDINA = 0x0002, + USB_POWER_CMD_START = 0x0003, + USB_POWER_CMD_NEXT = 0x0004, + USB_POWER_CMD_SETTIME = 0x0005, }; /* Addina "INA Type" field. */ enum usb_power_ina_type { - USBP_INA231_POWER = 0x01, - USBP_INA231_BUSV = 0x02, - USBP_INA231_CURRENT = 0x03, - USBP_INA231_SHUNTV = 0x04, + USBP_INA231_POWER = 0x01, + USBP_INA231_BUSV = 0x02, + USBP_INA231_CURRENT = 0x03, + USBP_INA231_SHUNTV = 0x04, }; /* Internal state machine values */ enum usb_power_states { - USB_POWER_STATE_OFF = 0, + USB_POWER_STATE_OFF = 0, USB_POWER_STATE_SETUP, USB_POWER_STATE_CAPTURING, }; @@ -154,8 +155,7 @@ struct usb_power_ina_cfg { int shared; }; - -struct __attribute__ ((__packed__)) usb_power_report { +struct __attribute__((__packed__)) usb_power_report { uint8_t status; uint8_t size; uint64_t timestamp; @@ -163,17 +163,19 @@ struct __attribute__ ((__packed__)) usb_power_report { }; /* Must be 4 byte aligned */ -#define USB_POWER_RECORD_SIZE(ina_count) \ - ((((sizeof(struct usb_power_report) \ - - (sizeof(uint16_t) * USB_POWER_MAX_READ_COUNT) \ - + (sizeof(uint16_t) * (ina_count))) + 3) / 4) * 4) - -#define USB_POWER_DATA_SIZE \ +#define USB_POWER_RECORD_SIZE(ina_count) \ + ((((sizeof(struct usb_power_report) - \ + (sizeof(uint16_t) * USB_POWER_MAX_READ_COUNT) + \ + (sizeof(uint16_t) * (ina_count))) + \ + 3) / \ + 4) * \ + 4) + +#define USB_POWER_DATA_SIZE \ (sizeof(struct usb_power_report) * (USB_POWER_MIN_CACHED + 1)) -#define USB_POWER_MAX_CACHED(ina_count) \ +#define USB_POWER_MAX_CACHED(ina_count) \ (USB_POWER_DATA_SIZE / USB_POWER_RECORD_SIZE(ina_count)) - struct usb_power_state { /* * The power data acquisition must be setup, then started, in order to @@ -212,7 +214,6 @@ struct usb_power_state { uint8_t tx_buf[USB_MAX_PACKET_SIZE * 4]; }; - /* * Compile time Per-USB gpio configuration stored in flash. Instances of this * structure are provided by the user of the USB gpio. This structure binds @@ -234,12 +235,12 @@ struct usb_power_config { const struct deferred_data *deferred_cap; }; -struct __attribute__ ((__packed__)) usb_power_command_start { +struct __attribute__((__packed__)) usb_power_command_start { uint16_t command; uint32_t integration_us; }; -struct __attribute__ ((__packed__)) usb_power_command_addina { +struct __attribute__((__packed__)) usb_power_command_addina { uint16_t command; uint8_t port; uint8_t type; @@ -248,7 +249,7 @@ struct __attribute__ ((__packed__)) usb_power_command_addina { uint32_t rs; }; -struct __attribute__ ((__packed__)) usb_power_command_settime { +struct __attribute__((__packed__)) usb_power_command_settime { uint16_t command; uint64_t time; }; @@ -260,7 +261,6 @@ union usb_power_command_data { struct usb_power_command_settime settime; }; - /* * Convenience macro for defining a USB INA Power driver. * @@ -273,92 +273,96 @@ union usb_power_command_data { * ENDPOINT is the index of the USB bulk endpoint used for receiving and * transmitting bytes. */ -#define USB_POWER_CONFIG(NAME, \ - INTERFACE, \ - ENDPOINT) \ - static void CONCAT2(NAME, _deferred_tx_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_tx_)); \ - static void CONCAT2(NAME, _deferred_rx_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_rx_)); \ - static void CONCAT2(NAME, _deferred_cap_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_cap_)); \ - struct usb_power_state CONCAT2(NAME, _state_) = { \ - .state = USB_POWER_STATE_OFF, \ - .ina_count = 0, \ - .integration_us = 0, \ - .reports_head = 0, \ - .reports_tail = 0, \ - .wall_offset = 0, \ - }; \ - static struct dwc_usb_ep CONCAT2(NAME, _ep_ctl) = { \ - .max_packet = USB_MAX_PACKET_SIZE, \ - .tx_fifo = ENDPOINT, \ - .out_pending = 0, \ - .out_data = 0, \ - .out_databuffer = 0, \ - .out_databuffer_max = 0, \ - .rx_deferred = &CONCAT2(NAME, _deferred_rx__data), \ - .in_packets = 0, \ - .in_pending = 0, \ - .in_data = 0, \ - .in_databuffer = 0, \ - .in_databuffer_max = 0, \ - .tx_deferred = &CONCAT2(NAME, _deferred_tx__data), \ - }; \ - struct usb_power_config const NAME = { \ - .state = &CONCAT2(NAME, _state_), \ - .ep = &CONCAT2(NAME, _ep_ctl), \ - .interface = INTERFACE, \ - .endpoint = ENDPOINT, \ - .deferred_cap = &CONCAT2(NAME, _deferred_cap__data), \ - }; \ - const struct usb_interface_descriptor \ - USB_IFACE_DESC(INTERFACE) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 0, \ - .bNumEndpoints = 2, \ - .bInterfaceClass = USB_CLASS_VENDOR_SPEC, \ - .bInterfaceSubClass = USB_SUBCLASS_GOOGLE_POWER, \ - .bInterfaceProtocol = USB_PROTOCOL_GOOGLE_POWER, \ - .iInterface = 0, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 0) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = 0x80 | ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk IN */, \ - .wMaxPacketSize = USB_MAX_PACKET_SIZE, \ - .bInterval = 1, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 1) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk OUT */, \ - .wMaxPacketSize = USB_MAX_PACKET_SIZE, \ - .bInterval = 0, \ - }; \ - static void CONCAT2(NAME, _ep_tx_) (void) { usb_epN_tx(ENDPOINT); } \ - static void CONCAT2(NAME, _ep_rx_) (void) { usb_epN_rx(ENDPOINT); } \ - static void CONCAT2(NAME, _ep_event_)(enum usb_ep_event evt) \ - { \ - usb_power_event(&NAME, evt); \ - } \ - USB_DECLARE_EP(ENDPOINT, \ - CONCAT2(NAME, _ep_tx_), \ - CONCAT2(NAME, _ep_rx_), \ - CONCAT2(NAME, _ep_event_)); \ - static void CONCAT2(NAME, _deferred_tx_)(void) \ - { usb_power_deferred_tx(&NAME); } \ - static void CONCAT2(NAME, _deferred_rx_)(void) \ - { usb_power_deferred_rx(&NAME); } \ - static void CONCAT2(NAME, _deferred_cap_)(void) \ - { usb_power_deferred_cap(&NAME); } - +#define USB_POWER_CONFIG(NAME, INTERFACE, ENDPOINT) \ + static void CONCAT2(NAME, _deferred_tx_)(void); \ + DECLARE_DEFERRED(CONCAT2(NAME, _deferred_tx_)); \ + static void CONCAT2(NAME, _deferred_rx_)(void); \ + DECLARE_DEFERRED(CONCAT2(NAME, _deferred_rx_)); \ + static void CONCAT2(NAME, _deferred_cap_)(void); \ + DECLARE_DEFERRED(CONCAT2(NAME, _deferred_cap_)); \ + struct usb_power_state CONCAT2(NAME, _state_) = { \ + .state = USB_POWER_STATE_OFF, \ + .ina_count = 0, \ + .integration_us = 0, \ + .reports_head = 0, \ + .reports_tail = 0, \ + .wall_offset = 0, \ + }; \ + static struct dwc_usb_ep CONCAT2(NAME, _ep_ctl) = { \ + .max_packet = USB_MAX_PACKET_SIZE, \ + .tx_fifo = ENDPOINT, \ + .out_pending = 0, \ + .out_data = 0, \ + .out_databuffer = 0, \ + .out_databuffer_max = 0, \ + .rx_deferred = &CONCAT2(NAME, _deferred_rx__data), \ + .in_packets = 0, \ + .in_pending = 0, \ + .in_data = 0, \ + .in_databuffer = 0, \ + .in_databuffer_max = 0, \ + .tx_deferred = &CONCAT2(NAME, _deferred_tx__data), \ + }; \ + struct usb_power_config const NAME = { \ + .state = &CONCAT2(NAME, _state_), \ + .ep = &CONCAT2(NAME, _ep_ctl), \ + .interface = INTERFACE, \ + .endpoint = ENDPOINT, \ + .deferred_cap = &CONCAT2(NAME, _deferred_cap__data), \ + }; \ + const struct usb_interface_descriptor USB_IFACE_DESC(INTERFACE) = { \ + .bLength = USB_DT_INTERFACE_SIZE, \ + .bDescriptorType = USB_DT_INTERFACE, \ + .bInterfaceNumber = INTERFACE, \ + .bAlternateSetting = 0, \ + .bNumEndpoints = 2, \ + .bInterfaceClass = USB_CLASS_VENDOR_SPEC, \ + .bInterfaceSubClass = USB_SUBCLASS_GOOGLE_POWER, \ + .bInterfaceProtocol = USB_PROTOCOL_GOOGLE_POWER, \ + .iInterface = 0, \ + }; \ + const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 0) = { \ + .bLength = USB_DT_ENDPOINT_SIZE, \ + .bDescriptorType = USB_DT_ENDPOINT, \ + .bEndpointAddress = 0x80 | ENDPOINT, \ + .bmAttributes = 0x02 /* Bulk IN */, \ + .wMaxPacketSize = USB_MAX_PACKET_SIZE, \ + .bInterval = 1, \ + }; \ + const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 1) = { \ + .bLength = USB_DT_ENDPOINT_SIZE, \ + .bDescriptorType = USB_DT_ENDPOINT, \ + .bEndpointAddress = ENDPOINT, \ + .bmAttributes = 0x02 /* Bulk OUT */, \ + .wMaxPacketSize = USB_MAX_PACKET_SIZE, \ + .bInterval = 0, \ + }; \ + static void CONCAT2(NAME, _ep_tx_)(void) \ + { \ + usb_epN_tx(ENDPOINT); \ + } \ + static void CONCAT2(NAME, _ep_rx_)(void) \ + { \ + usb_epN_rx(ENDPOINT); \ + } \ + static void CONCAT2(NAME, _ep_event_)(enum usb_ep_event evt) \ + { \ + usb_power_event(&NAME, evt); \ + } \ + USB_DECLARE_EP(ENDPOINT, CONCAT2(NAME, _ep_tx_), \ + CONCAT2(NAME, _ep_rx_), CONCAT2(NAME, _ep_event_)); \ + static void CONCAT2(NAME, _deferred_tx_)(void) \ + { \ + usb_power_deferred_tx(&NAME); \ + } \ + static void CONCAT2(NAME, _deferred_rx_)(void) \ + { \ + usb_power_deferred_rx(&NAME); \ + } \ + static void CONCAT2(NAME, _deferred_cap_)(void) \ + { \ + usb_power_deferred_cap(&NAME); \ + } /* * Handle power request in a deferred callback. @@ -374,9 +378,6 @@ void usb_power_deferred_cap(struct usb_power_config const *config); void usb_power_tx(struct usb_power_config const *config); void usb_power_rx(struct usb_power_config const *config); void usb_power_event(struct usb_power_config const *config, - enum usb_ep_event evt); - - - + enum usb_ep_event evt); #endif /* __CROS_EC_USB_DWC_POWER_H */ diff --git a/chip/stm32/usb_spi.c b/chip/stm32/usb_spi.c index e80d15b6cd..5ea813a86c 100644 --- a/chip/stm32/usb_spi.c +++ b/chip/stm32/usb_spi.c @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,9 +17,9 @@ static bool usb_spi_received_packet(struct usb_spi_config const *config); static bool usb_spi_transmitted_packet(struct usb_spi_config const *config); static void usb_spi_read_packet(struct usb_spi_config const *config, - struct usb_spi_packet_ctx *packet); + struct usb_spi_packet_ctx *packet); static void usb_spi_write_packet(struct usb_spi_config const *config, - struct usb_spi_packet_ctx *packet); + struct usb_spi_packet_ctx *packet); /* * Map EC error codes to USB_SPI error codes. @@ -31,10 +31,14 @@ static void usb_spi_write_packet(struct usb_spi_config const *config, static int16_t usb_spi_map_error(int error) { switch (error) { - case EC_SUCCESS: return USB_SPI_SUCCESS; - case EC_ERROR_TIMEOUT: return USB_SPI_TIMEOUT; - case EC_ERROR_BUSY: return USB_SPI_BUSY; - default: return USB_SPI_UNKNOWN_ERROR | (error & 0x7fff); + case EC_SUCCESS: + return USB_SPI_SUCCESS; + case EC_ERROR_TIMEOUT: + return USB_SPI_TIMEOUT; + case EC_ERROR_BUSY: + return USB_SPI_BUSY; + default: + return USB_SPI_UNKNOWN_ERROR | (error & 0x7fff); } } @@ -47,7 +51,7 @@ static int16_t usb_spi_map_error(int error) * @returns USB_SPI_RX_DATA_OVERFLOW if the source packet is too large */ static int usb_spi_read_usb_packet(struct usb_spi_transfer_ctx *dst, - const struct usb_spi_packet_ctx *src) + const struct usb_spi_packet_ctx *src) { size_t max_read_length = dst->transfer_size - dst->transfer_index; size_t bytes_in_buffer = src->packet_size - src->header_size; @@ -61,7 +65,7 @@ static int usb_spi_read_usb_packet(struct usb_spi_transfer_ctx *dst, return USB_SPI_RX_DATA_OVERFLOW; } memcpy(dst->buffer + dst->transfer_index, packet_buffer, - bytes_in_buffer); + bytes_in_buffer); dst->transfer_index += bytes_in_buffer; return USB_SPI_SUCCESS; @@ -74,7 +78,7 @@ static int usb_spi_read_usb_packet(struct usb_spi_transfer_ctx *dst, * @param src Source transmit context we are reading data from. */ static void usb_spi_fill_usb_packet(struct usb_spi_packet_ctx *dst, - struct usb_spi_transfer_ctx *src) + struct usb_spi_transfer_ctx *src) { size_t transfer_size = src->transfer_size - src->transfer_index; size_t max_buffer_size = USB_MAX_PACKET_SIZE - dst->header_size; @@ -97,7 +101,7 @@ static void usb_spi_fill_usb_packet(struct usb_spi_packet_ctx *dst, * @param read_count Number of bytes to read in the SPI transfer */ static void usb_spi_setup_transfer(struct usb_spi_config const *config, - size_t write_count, size_t read_count) + size_t write_count, size_t read_count) { /* Reset any status code. */ config->state->status_code = USB_SPI_SUCCESS; @@ -145,7 +149,7 @@ static bool usb_spi_response_in_progress(struct usb_spi_config const *config) * @param status_code status code to set for the response. */ static void setup_transfer_response(struct usb_spi_config const *config, - uint16_t status_code) + uint16_t status_code) { config->state->status_code = status_code; config->state->spi_read_ctx.transfer_index = 0; @@ -163,7 +167,7 @@ static void setup_transfer_response(struct usb_spi_config const *config, * @param packet Packet buffer we will be transmitting. */ static void create_spi_config_response(struct usb_spi_config const *config, - struct usb_spi_packet_ctx *packet) + struct usb_spi_packet_ctx *packet) { /* Construct the response packet. */ packet->rsp_config.packet_id = USB_SPI_PKT_ID_RSP_USB_SPI_CONFIG; @@ -175,8 +179,7 @@ static void create_spi_config_response(struct usb_spi_config const *config, packet->rsp_config.feature_bitmap |= USB_SPI_FEATURE_FULL_DUPLEX_SUPPORTED; #endif - packet->packet_size = - sizeof(struct usb_spi_response_configuration_v2); + packet->packet_size = sizeof(struct usb_spi_response_configuration_v2); } static void create_spi_chip_select_response(struct usb_spi_config const *config, @@ -196,16 +199,14 @@ static void create_spi_chip_select_response(struct usb_spi_config const *config, * @param config USB SPI config * @param packet Packet buffer we will be transmitting. */ -static void usb_spi_create_spi_transfer_response( - struct usb_spi_config const *config, - struct usb_spi_packet_ctx *transmit_packet) +static void +usb_spi_create_spi_transfer_response(struct usb_spi_config const *config, + struct usb_spi_packet_ctx *transmit_packet) { - if (!usb_spi_response_in_progress(config)) return; if (config->state->spi_read_ctx.transfer_index == 0) { - /* Transmit the first packet with the status code. */ transmit_packet->header_size = offsetof(struct usb_spi_response_v2, data); @@ -215,10 +216,9 @@ static void usb_spi_create_spi_transfer_response( config->state->status_code; usb_spi_fill_usb_packet(transmit_packet, - &config->state->spi_read_ctx); + &config->state->spi_read_ctx); } else if (config->state->spi_read_ctx.transfer_index < - config->state->spi_read_ctx.transfer_size) { - + config->state->spi_read_ctx.transfer_size) { /* Transmit the continue packets. */ transmit_packet->header_size = offsetof(struct usb_spi_continue_v2, data); @@ -228,10 +228,10 @@ static void usb_spi_create_spi_transfer_response( config->state->spi_read_ctx.transfer_index; usb_spi_fill_usb_packet(transmit_packet, - &config->state->spi_read_ctx); + &config->state->spi_read_ctx); } if (config->state->spi_read_ctx.transfer_index < - config->state->spi_read_ctx.transfer_size) { + config->state->spi_read_ctx.transfer_size) { config->state->mode = USB_SPI_MODE_CONTINUE_RESPONSE; } else { config->state->mode = USB_SPI_MODE_IDLE; @@ -245,7 +245,7 @@ static void usb_spi_create_spi_transfer_response( * @param packet Received packet to process. */ static void usb_spi_process_rx_packet(struct usb_spi_config const *config, - struct usb_spi_packet_ctx *packet) + struct usb_spi_packet_ctx *packet) { if (packet->packet_size < USB_SPI_MIN_PACKET_SIZE) { /* No valid packet exists smaller than the packet id. */ @@ -256,14 +256,12 @@ static void usb_spi_process_rx_packet(struct usb_spi_config const *config, config->state->mode = USB_SPI_MODE_IDLE; switch (packet->packet_id) { - case USB_SPI_PKT_ID_CMD_GET_USB_SPI_CONFIG: - { + case USB_SPI_PKT_ID_CMD_GET_USB_SPI_CONFIG: { /* The host requires the SPI configuration. */ config->state->mode = USB_SPI_MODE_SEND_CONFIGURATION; break; } - case USB_SPI_PKT_ID_CMD_RESTART_RESPONSE: - { + case USB_SPI_PKT_ID_CMD_RESTART_RESPONSE: { /* * The host has requested the device restart the last response. * This is used to recover from lost USB packets without @@ -272,8 +270,7 @@ static void usb_spi_process_rx_packet(struct usb_spi_config const *config, setup_transfer_response(config, config->state->status_code); break; } - case USB_SPI_PKT_ID_CMD_TRANSFER_START: - { + case USB_SPI_PKT_ID_CMD_TRANSFER_START: { /* The host started a new USB SPI transfer */ size_t write_count = packet->cmd_start.write_count; size_t read_count = packet->cmd_start.read_count; @@ -282,42 +279,41 @@ static void usb_spi_process_rx_packet(struct usb_spi_config const *config, setup_transfer_response(config, USB_SPI_DISABLED); } else if (write_count > USB_SPI_MAX_WRITE_COUNT) { setup_transfer_response(config, - USB_SPI_WRITE_COUNT_INVALID); + USB_SPI_WRITE_COUNT_INVALID); #ifdef CONFIG_SPI_HALFDUPLEX } else if (read_count == USB_SPI_FULL_DUPLEX_ENABLED) { /* Full duplex mode is not supported on this device. */ - setup_transfer_response(config, - USB_SPI_UNSUPPORTED_FULL_DUPLEX); + setup_transfer_response( + config, USB_SPI_UNSUPPORTED_FULL_DUPLEX); #endif } else if (read_count > USB_SPI_MAX_READ_COUNT && - read_count != USB_SPI_FULL_DUPLEX_ENABLED) { + read_count != USB_SPI_FULL_DUPLEX_ENABLED) { setup_transfer_response(config, - USB_SPI_READ_COUNT_INVALID); + USB_SPI_READ_COUNT_INVALID); } else { - usb_spi_setup_transfer(config, write_count, read_count); - packet->header_size = - offsetof(struct usb_spi_command_v2, data); - config->state->status_code = usb_spi_read_usb_packet( - &config->state->spi_write_ctx, packet); + usb_spi_setup_transfer(config, write_count, read_count); + packet->header_size = + offsetof(struct usb_spi_command_v2, data); + config->state->status_code = usb_spi_read_usb_packet( + &config->state->spi_write_ctx, packet); } /* Send responses if we encountered an error. */ if (config->state->status_code != USB_SPI_SUCCESS) { setup_transfer_response(config, - config->state->status_code); + config->state->status_code); break; } /* Start the SPI transfer when we've read all data. */ if (config->state->spi_write_ctx.transfer_index == - config->state->spi_write_ctx.transfer_size) { + config->state->spi_write_ctx.transfer_size) { config->state->mode = USB_SPI_MODE_START_SPI; } break; } - case USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE: - { + case USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE: { /* * The host has sent a continue packet for the SPI transfer * which contains additional data payload. @@ -326,26 +322,25 @@ static void usb_spi_process_rx_packet(struct usb_spi_config const *config, offsetof(struct usb_spi_continue_v2, data); if (config->state->status_code == USB_SPI_SUCCESS) { config->state->status_code = usb_spi_read_usb_packet( - &config->state->spi_write_ctx, packet); + &config->state->spi_write_ctx, packet); } /* Send responses if we encountered an error. */ if (config->state->status_code != USB_SPI_SUCCESS) { setup_transfer_response(config, - config->state->status_code); + config->state->status_code); break; } /* Start the SPI transfer when we've read all data. */ if (config->state->spi_write_ctx.transfer_index == - config->state->spi_write_ctx.transfer_size) { + config->state->spi_write_ctx.transfer_size) { config->state->mode = USB_SPI_MODE_START_SPI; } break; } - case USB_SPI_PKT_ID_CMD_CHIP_SELECT: - { + case USB_SPI_PKT_ID_CMD_CHIP_SELECT: { /* * The host is requesting the chip select line be * asserted or deasserted. @@ -362,8 +357,7 @@ static void usb_spi_process_rx_packet(struct usb_spi_config const *config, config->state->mode = USB_SPI_MODE_SEND_CHIP_SELECT_RESPONSE; break; } - default: - { + default: { /* An unknown USB packet was delivered. */ setup_transfer_response(config, USB_SPI_RX_UNEXPECTED_PACKET); break; @@ -396,8 +390,10 @@ void usb_spi_deferred(struct usb_spi_config const *config) * enable or disable routines and save our new state. */ if (enabled != config->state->enabled) { - if (enabled) usb_spi_board_enable(config); - else usb_spi_board_disable(config); + if (enabled) + usb_spi_board_enable(config); + else + usb_spi_board_disable(config); config->state->enabled = enabled; } @@ -439,11 +435,10 @@ void usb_spi_deferred(struct usb_spi_config const *config) read_count = SPI_READBACK_ALL; } #endif - status_code = spi_transaction(SPI_FLASH_DEVICE, - config->state->spi_write_ctx.buffer, + status_code = spi_transaction( + SPI_FLASH_DEVICE, config->state->spi_write_ctx.buffer, config->state->spi_write_ctx.transfer_size, - config->state->spi_read_ctx.buffer, - read_count); + config->state->spi_read_ctx.buffer, read_count); /* Cast the EC status code to USB SPI and start the response. */ status_code = usb_spi_map_error(status_code); @@ -451,7 +446,7 @@ void usb_spi_deferred(struct usb_spi_config const *config) } if (usb_spi_response_in_progress(config) && - usb_spi_transmitted_packet(config)) { + usb_spi_transmitted_packet(config)) { usb_spi_create_spi_transfer_response(config, transmit_packet); usb_spi_write_packet(config, transmit_packet); } @@ -491,7 +486,8 @@ static void usb_spi_read_packet(struct usb_spi_config const *config, /* Copy bytes from endpoint memory. */ packet_size = btable_ep[config->endpoint].rx_count & RX_COUNT_MASK; memcpy_from_usbram(packet->bytes, - (void *)usb_sram_addr(config->ep_rx_ram), packet_size); + (void *)usb_sram_addr(config->ep_rx_ram), + packet_size); packet->packet_size = packet_size; /* Set endpoint as valid for accepting new packet. */ STM32_TOGGLE_EP(config->endpoint, EP_RX_MASK, EP_RX_VALID, 0); @@ -505,14 +501,14 @@ static void usb_spi_read_packet(struct usb_spi_config const *config, * @param packet Source packet we will write to the endpoint data. */ static void usb_spi_write_packet(struct usb_spi_config const *config, - struct usb_spi_packet_ctx *packet) + struct usb_spi_packet_ctx *packet) { if (packet->packet_size == 0) return; /* Copy bytes to endpoint memory. */ memcpy_to_usbram((void *)usb_sram_addr(config->ep_tx_ram), - packet->bytes, packet->packet_size); + packet->bytes, packet->packet_size); btable_ep[config->endpoint].tx_count = packet->packet_size; /* Mark the packet as having no data. */ @@ -597,17 +593,17 @@ void usb_spi_event(struct usb_spi_config const *config, enum usb_ep_event evt) usb_spi_reset_interface(config); - btable_ep[endpoint].tx_addr = usb_sram_addr(config->ep_tx_ram); + btable_ep[endpoint].tx_addr = usb_sram_addr(config->ep_tx_ram); btable_ep[endpoint].tx_count = 0; - btable_ep[endpoint].rx_addr = usb_sram_addr(config->ep_rx_ram); - btable_ep[endpoint].rx_count = - 0x8000 | ((USB_MAX_PACKET_SIZE / 32 - 1) << 10); + btable_ep[endpoint].rx_addr = usb_sram_addr(config->ep_rx_ram); + btable_ep[endpoint].rx_count = 0x8000 | + ((USB_MAX_PACKET_SIZE / 32 - 1) << 10); - STM32_USB_EP(endpoint) = ((endpoint << 0) | /* Endpoint Addr*/ - (2 << 4) | /* TX NAK */ - (0 << 9) | /* Bulk EP */ - (3 << 12)); /* RX Valid */ + STM32_USB_EP(endpoint) = ((endpoint << 0) | /* Endpoint Addr*/ + (2 << 4) | /* TX NAK */ + (0 << 9) | /* Bulk EP */ + (3 << 12)); /* RX Valid */ } /* @@ -617,21 +613,18 @@ void usb_spi_event(struct usb_spi_config const *config, enum usb_ep_event evt) * @param rx_buf Contains setup packet * @param tx_buf unused */ -int usb_spi_interface(struct usb_spi_config const *config, - usb_uint *rx_buf, +int usb_spi_interface(struct usb_spi_config const *config, usb_uint *rx_buf, usb_uint *tx_buf) { struct usb_setup_packet setup; usb_read_setup_packet(rx_buf, &setup); - if (setup.bmRequestType != (USB_DIR_OUT | - USB_TYPE_VENDOR | - USB_RECIP_INTERFACE)) + if (setup.bmRequestType != + (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_INTERFACE)) return 1; - if (setup.wValue != 0 || - setup.wIndex != config->interface || + if (setup.wValue != 0 || setup.wIndex != config->interface || setup.wLength != 0) return 1; @@ -644,7 +637,8 @@ int usb_spi_interface(struct usb_spi_config const *config, config->state->enabled_host = 0; break; - default: return 1; + default: + return 1; } /* diff --git a/chip/stm32/usb_spi.h b/chip/stm32/usb_spi.h index fa86ba3651..3ff582dd14 100644 --- a/chip/stm32/usb_spi.h +++ b/chip/stm32/usb_spi.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -268,48 +268,48 @@ * http://libusb.sourceforge.net/api-1.0/group__misc.html */ -#define USB_SPI_FULL_DUPLEX_ENABLED (UINT16_MAX) +#define USB_SPI_FULL_DUPLEX_ENABLED (UINT16_MAX) -#define USB_SPI_PAYLOAD_SIZE_V2_START (58) +#define USB_SPI_PAYLOAD_SIZE_V2_START (58) -#define USB_SPI_PAYLOAD_SIZE_V2_RESPONSE (60) +#define USB_SPI_PAYLOAD_SIZE_V2_RESPONSE (60) -#define USB_SPI_PAYLOAD_SIZE_V2_CONTINUE (60) +#define USB_SPI_PAYLOAD_SIZE_V2_CONTINUE (60) -#define USB_SPI_PAYLOAD_SIZE_V2_ERROR (60) +#define USB_SPI_PAYLOAD_SIZE_V2_ERROR (60) -#define USB_SPI_MIN_PACKET_SIZE (2) +#define USB_SPI_MIN_PACKET_SIZE (2) enum packet_id_type { /* Request USB SPI configuration data from device. */ USB_SPI_PKT_ID_CMD_GET_USB_SPI_CONFIG = 0, /* USB SPI configuration data from device. */ - USB_SPI_PKT_ID_RSP_USB_SPI_CONFIG = 1, + USB_SPI_PKT_ID_RSP_USB_SPI_CONFIG = 1, /* * Start a USB SPI transfer specifying number of bytes to write, * read and deliver first packet of data to write. */ - USB_SPI_PKT_ID_CMD_TRANSFER_START = 2, + USB_SPI_PKT_ID_CMD_TRANSFER_START = 2, /* Additional packets containing write payload. */ - USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE = 3, + USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE = 3, /* * Request the device restart the response enabling us to recover * from packet loss without another SPI transfer. */ - USB_SPI_PKT_ID_CMD_RESTART_RESPONSE = 4, + USB_SPI_PKT_ID_CMD_RESTART_RESPONSE = 4, /* * First packet of USB SPI response with the status code * and read payload if it was successful. */ - USB_SPI_PKT_ID_RSP_TRANSFER_START = 5, + USB_SPI_PKT_ID_RSP_TRANSFER_START = 5, /* Additional packets containing read payload. */ - USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE = 6, + USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE = 6, /* * Request assertion or deassertion of chip select */ - USB_SPI_PKT_ID_CMD_CHIP_SELECT = 7, + USB_SPI_PKT_ID_CMD_CHIP_SELECT = 7, /* Response to above request. */ - USB_SPI_PKT_ID_RSP_CHIP_SELECT = 8, + USB_SPI_PKT_ID_RSP_CHIP_SELECT = 8, }; enum feature_bitmap { @@ -383,25 +383,25 @@ struct usb_spi_packet_ctx { }; enum usb_spi_error { - USB_SPI_SUCCESS = 0x0000, - USB_SPI_TIMEOUT = 0x0001, - USB_SPI_BUSY = 0x0002, - USB_SPI_WRITE_COUNT_INVALID = 0x0003, - USB_SPI_READ_COUNT_INVALID = 0x0004, - USB_SPI_DISABLED = 0x0005, + USB_SPI_SUCCESS = 0x0000, + USB_SPI_TIMEOUT = 0x0001, + USB_SPI_BUSY = 0x0002, + USB_SPI_WRITE_COUNT_INVALID = 0x0003, + USB_SPI_READ_COUNT_INVALID = 0x0004, + USB_SPI_DISABLED = 0x0005, /* The RX continue packet's data index is invalid. */ - USB_SPI_RX_BAD_DATA_INDEX = 0x0006, + USB_SPI_RX_BAD_DATA_INDEX = 0x0006, /* The RX endpoint has received more data than write count. */ - USB_SPI_RX_DATA_OVERFLOW = 0x0007, + USB_SPI_RX_DATA_OVERFLOW = 0x0007, /* An unexpected packet arrived on the device. */ - USB_SPI_RX_UNEXPECTED_PACKET = 0x0008, + USB_SPI_RX_UNEXPECTED_PACKET = 0x0008, /* The device does not support full duplex mode. */ USB_SPI_UNSUPPORTED_FULL_DUPLEX = 0x0009, - USB_SPI_UNKNOWN_ERROR = 0x8000, + USB_SPI_UNKNOWN_ERROR = 0x8000, }; enum usb_spi_request { - USB_SPI_REQ_ENABLE = 0x0000, + USB_SPI_REQ_ENABLE = 0x0000, USB_SPI_REQ_DISABLE = 0x0001, }; @@ -416,11 +416,11 @@ enum usb_spi_request { #ifdef CONFIG_USB_SPI_BUFFER_SIZE #define USB_SPI_BUFFER_SIZE CONFIG_USB_SPI_BUFFER_SIZE #else -#define USB_SPI_BUFFER_SIZE (USB_SPI_PAYLOAD_SIZE_V2_START + \ - (4 * USB_SPI_PAYLOAD_SIZE_V2_CONTINUE)) +#define USB_SPI_BUFFER_SIZE \ + (USB_SPI_PAYLOAD_SIZE_V2_START + (4 * USB_SPI_PAYLOAD_SIZE_V2_CONTINUE)) #endif -#define USB_SPI_MAX_WRITE_COUNT USB_SPI_BUFFER_SIZE -#define USB_SPI_MAX_READ_COUNT USB_SPI_BUFFER_SIZE +#define USB_SPI_MAX_WRITE_COUNT USB_SPI_BUFFER_SIZE +#define USB_SPI_MAX_READ_COUNT USB_SPI_BUFFER_SIZE /* Protocol uses two-byte length fields. Larger buffer makes no sense. */ BUILD_ASSERT(USB_SPI_BUFFER_SIZE <= 65536); @@ -541,78 +541,82 @@ struct usb_spi_config { * FLAGS encodes different run-time control parameters. See * USB_SPI_CONFIG_FLAGS_* for definitions. */ -#define USB_SPI_CONFIG(NAME, \ - INTERFACE, \ - ENDPOINT, \ - FLAGS) \ - static uint16_t CONCAT2(NAME, _buffer_)[(USB_SPI_BUFFER_SIZE + 1) / 2];\ - static usb_uint CONCAT2(NAME, _ep_rx_buffer_)[USB_MAX_PACKET_SIZE / 2] __usb_ram; \ - static usb_uint CONCAT2(NAME, _ep_tx_buffer_)[USB_MAX_PACKET_SIZE / 2] __usb_ram; \ - static void CONCAT2(NAME, _deferred_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_)); \ - struct usb_spi_state CONCAT2(NAME, _state_) = { \ - .enabled_host = 0, \ - .enabled_device = 0, \ - .enabled = 0, \ +#define USB_SPI_CONFIG(NAME, INTERFACE, ENDPOINT, FLAGS) \ + static uint16_t CONCAT2(NAME, \ + _buffer_)[(USB_SPI_BUFFER_SIZE + 1) / 2]; \ + static usb_uint CONCAT2( \ + NAME, _ep_rx_buffer_)[USB_MAX_PACKET_SIZE / 2] __usb_ram; \ + static usb_uint CONCAT2( \ + NAME, _ep_tx_buffer_)[USB_MAX_PACKET_SIZE / 2] __usb_ram; \ + static void CONCAT2(NAME, _deferred_)(void); \ + DECLARE_DEFERRED(CONCAT2(NAME, _deferred_)); \ + struct usb_spi_state CONCAT2(NAME, _state_) = { \ + .enabled_host = 0, \ + .enabled_device = 0, \ + .enabled = 0, \ .spi_write_ctx.buffer = (uint8_t *)CONCAT2(NAME, _buffer_), \ - .spi_read_ctx.buffer = (uint8_t *)CONCAT2(NAME, _buffer_), \ - }; \ - struct usb_spi_config const NAME = { \ - .state = &CONCAT2(NAME, _state_), \ - .interface = INTERFACE, \ - .endpoint = ENDPOINT, \ - .deferred = &CONCAT2(NAME, _deferred__data), \ - .ep_rx_ram = CONCAT2(NAME, _ep_rx_buffer_), \ - .ep_tx_ram = CONCAT2(NAME, _ep_tx_buffer_), \ - .flags = FLAGS, \ - }; \ - const struct usb_interface_descriptor \ - USB_IFACE_DESC(INTERFACE) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 0, \ - .bNumEndpoints = 2, \ - .bInterfaceClass = USB_CLASS_VENDOR_SPEC, \ - .bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SPI, \ - .bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SPI, \ - .iInterface = USB_STR_SPI_NAME, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 0) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = 0x80 | ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk IN */, \ - .wMaxPacketSize = USB_MAX_PACKET_SIZE, \ - .bInterval = 10, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 1) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk OUT */, \ - .wMaxPacketSize = USB_MAX_PACKET_SIZE, \ - .bInterval = 0, \ - }; \ - static void CONCAT2(NAME, _ep_tx_) (void) { usb_spi_tx (&NAME); } \ - static void CONCAT2(NAME, _ep_rx_) (void) { usb_spi_rx (&NAME); } \ - static void CONCAT2(NAME, _ep_event_)(enum usb_ep_event evt) \ - { \ - usb_spi_event(&NAME, evt); \ - } \ - USB_DECLARE_EP(ENDPOINT, \ - CONCAT2(NAME, _ep_tx_), \ - CONCAT2(NAME, _ep_rx_), \ - CONCAT2(NAME, _ep_event_)); \ - static int CONCAT2(NAME, _interface_)(usb_uint *rx_buf, \ - usb_uint *tx_buf) \ - { return usb_spi_interface(&NAME, rx_buf, tx_buf); } \ - USB_DECLARE_IFACE(INTERFACE, \ - CONCAT2(NAME, _interface_)); \ - static void CONCAT2(NAME, _deferred_)(void) \ - { usb_spi_deferred(&NAME); } + .spi_read_ctx.buffer = (uint8_t *)CONCAT2(NAME, _buffer_), \ + }; \ + struct usb_spi_config const NAME = { \ + .state = &CONCAT2(NAME, _state_), \ + .interface = INTERFACE, \ + .endpoint = ENDPOINT, \ + .deferred = &CONCAT2(NAME, _deferred__data), \ + .ep_rx_ram = CONCAT2(NAME, _ep_rx_buffer_), \ + .ep_tx_ram = CONCAT2(NAME, _ep_tx_buffer_), \ + .flags = FLAGS, \ + }; \ + const struct usb_interface_descriptor USB_IFACE_DESC(INTERFACE) = { \ + .bLength = USB_DT_INTERFACE_SIZE, \ + .bDescriptorType = USB_DT_INTERFACE, \ + .bInterfaceNumber = INTERFACE, \ + .bAlternateSetting = 0, \ + .bNumEndpoints = 2, \ + .bInterfaceClass = USB_CLASS_VENDOR_SPEC, \ + .bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SPI, \ + .bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SPI, \ + .iInterface = USB_STR_SPI_NAME, \ + }; \ + const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 0) = { \ + .bLength = USB_DT_ENDPOINT_SIZE, \ + .bDescriptorType = USB_DT_ENDPOINT, \ + .bEndpointAddress = 0x80 | ENDPOINT, \ + .bmAttributes = 0x02 /* Bulk IN */, \ + .wMaxPacketSize = USB_MAX_PACKET_SIZE, \ + .bInterval = 10, \ + }; \ + const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 1) = { \ + .bLength = USB_DT_ENDPOINT_SIZE, \ + .bDescriptorType = USB_DT_ENDPOINT, \ + .bEndpointAddress = ENDPOINT, \ + .bmAttributes = 0x02 /* Bulk OUT */, \ + .wMaxPacketSize = USB_MAX_PACKET_SIZE, \ + .bInterval = 0, \ + }; \ + static void CONCAT2(NAME, _ep_tx_)(void) \ + { \ + usb_spi_tx(&NAME); \ + } \ + static void CONCAT2(NAME, _ep_rx_)(void) \ + { \ + usb_spi_rx(&NAME); \ + } \ + static void CONCAT2(NAME, _ep_event_)(enum usb_ep_event evt) \ + { \ + usb_spi_event(&NAME, evt); \ + } \ + USB_DECLARE_EP(ENDPOINT, CONCAT2(NAME, _ep_tx_), \ + CONCAT2(NAME, _ep_rx_), CONCAT2(NAME, _ep_event_)); \ + static int CONCAT2(NAME, _interface_)(usb_uint * rx_buf, \ + usb_uint * tx_buf) \ + { \ + return usb_spi_interface(&NAME, rx_buf, tx_buf); \ + } \ + USB_DECLARE_IFACE(INTERFACE, CONCAT2(NAME, _interface_)); \ + static void CONCAT2(NAME, _deferred_)(void) \ + { \ + usb_spi_deferred(&NAME); \ + } /* * Handle SPI request in a deferred callback. @@ -636,9 +640,8 @@ void usb_spi_enable(struct usb_spi_config const *config, int enabled); void usb_spi_tx(struct usb_spi_config const *config); void usb_spi_rx(struct usb_spi_config const *config); void usb_spi_event(struct usb_spi_config const *config, enum usb_ep_event evt); -int usb_spi_interface(struct usb_spi_config const *config, - usb_uint *rx_buf, - usb_uint *tx_buf); +int usb_spi_interface(struct usb_spi_config const *config, usb_uint *rx_buf, + usb_uint *tx_buf); /* * These functions should be implemented by the board to provide any board diff --git a/chip/stm32/watchdog.c b/chip/stm32/watchdog.c index 40dfc72059..1a54d6f52d 100644 --- a/chip/stm32/watchdog.c +++ b/chip/stm32/watchdog.c @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -67,8 +67,9 @@ int watchdog_init(void) STM32_IWDG_PR = IWDG_PRESCALER & 7; /* Set the reload value of the watchdog counter */ - STM32_IWDG_RLR = MIN(STM32_IWDG_RLR_MAX, CONFIG_WATCHDOG_PERIOD_MS * - (LSI_CLOCK / IWDG_PRESCALER_DIV) / 1000); + STM32_IWDG_RLR = MIN(STM32_IWDG_RLR_MAX, + CONFIG_WATCHDOG_PERIOD_MS * + (LSI_CLOCK / IWDG_PRESCALER_DIV) / 1000); #ifdef CHIP_FAMILY_STM32L4 tickstart = get_time(); /* Wait for SR */ |