diff options
Diffstat (limited to 'driver/tcpm/raa489000.h')
| -rw-r--r-- | driver/tcpm/raa489000.h | 50 |
1 files changed, 25 insertions, 25 deletions
diff --git a/driver/tcpm/raa489000.h b/driver/tcpm/raa489000.h index 2a4c7c6b3d..41a37f94e7 100644 --- a/driver/tcpm/raa489000.h +++ b/driver/tcpm/raa489000.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -17,25 +17,25 @@ #define RAA489000_TCPC3_I2C_FLAGS 0x25 /* Vendor registers */ -#define RAA489000_TCPC_SETTING1 0x80 -#define RAA489000_VBUS_VOLTAGE_TARGET 0x90 -#define RAA489000_VBUS_CURRENT_TARGET 0x92 -#define RAA489000_VBUS_OCP_UV_THRESHOLD 0x94 -#define RAA489000_TYPEC_SETTING1 0xC0 -#define RAA489000_PD_PHYSICAL_SETTING1 0xE0 -#define RAA489000_PD_PHYSICAL_PARAMETER1 0xE8 +#define RAA489000_TCPC_SETTING1 0x80 +#define RAA489000_VBUS_VOLTAGE_TARGET 0x90 +#define RAA489000_VBUS_CURRENT_TARGET 0x92 +#define RAA489000_VBUS_OCP_UV_THRESHOLD 0x94 +#define RAA489000_TYPEC_SETTING1 0xC0 +#define RAA489000_PD_PHYSICAL_SETTING1 0xE0 +#define RAA489000_PD_PHYSICAL_PARAMETER1 0xE8 /* TCPC_SETTING_1 */ -#define RAA489000_TCPCV1_0_EN BIT(0) -#define RAA489000_TCPC_PWR_CNTRL BIT(4) +#define RAA489000_TCPCV1_0_EN BIT(0) +#define RAA489000_TCPC_PWR_CNTRL BIT(4) /* VBUS_CURRENT_TARGET */ -#define RAA489000_VBUS_CURRENT_TARGET_3A 0x66 /* 3.0A + iOvershoot */ -#define RAA489000_VBUS_CURRENT_TARGET_1_5A 0x38 /* 1.5A + iOvershoot */ +#define RAA489000_VBUS_CURRENT_TARGET_3A 0x66 /* 3.0A + iOvershoot */ +#define RAA489000_VBUS_CURRENT_TARGET_1_5A 0x38 /* 1.5A + iOvershoot */ /* VBUS_VOLTAGE_TARGET */ -#define RAA489000_VBUS_VOLTAGE_TARGET_5160MV 0x102 /* 5.16V */ -#define RAA489000_VBUS_VOLTAGE_TARGET_5220MV 0x105 /* 5.22V */ +#define RAA489000_VBUS_VOLTAGE_TARGET_5160MV 0x102 /* 5.16V */ +#define RAA489000_VBUS_VOLTAGE_TARGET_5220MV 0x105 /* 5.22V */ /* VBUS_OCP_UV_THRESHOLD */ /* Detect voltage level of overcurrent protection during Sourcing VBUS */ @@ -43,26 +43,26 @@ /* TYPEC_SETTING1 - only older silicon */ /* Enables for reverse current protection */ -#define RAA489000_SETTING1_IP2_EN BIT(9) -#define RAA489000_SETTING1_IP1_EN BIT(8) +#define RAA489000_SETTING1_IP2_EN BIT(9) +#define RAA489000_SETTING1_IP1_EN BIT(8) /* Switches from dead-battery Rd */ -#define RAA489000_SETTING1_RDOE BIT(7) +#define RAA489000_SETTING1_RDOE BIT(7) /* CC comparator enables */ -#define RAA489000_SETTING1_CC2_CMP3_EN BIT(6) -#define RAA489000_SETTING1_CC2_CMP2_EN BIT(5) -#define RAA489000_SETTING1_CC2_CMP1_EN BIT(4) -#define RAA489000_SETTING1_CC1_CMP3_EN BIT(3) -#define RAA489000_SETTING1_CC1_CMP2_EN BIT(2) -#define RAA489000_SETTING1_CC1_CMP1_EN BIT(1) +#define RAA489000_SETTING1_CC2_CMP3_EN BIT(6) +#define RAA489000_SETTING1_CC2_CMP2_EN BIT(5) +#define RAA489000_SETTING1_CC2_CMP1_EN BIT(4) +#define RAA489000_SETTING1_CC1_CMP3_EN BIT(3) +#define RAA489000_SETTING1_CC1_CMP2_EN BIT(2) +#define RAA489000_SETTING1_CC1_CMP1_EN BIT(1) /* CC debounce enable */ -#define RAA489000_SETTING1_CC_DB_EN BIT(0) +#define RAA489000_SETTING1_CC_DB_EN BIT(0) /* PD_PHYSICAL_SETTING_1 */ #define RAA489000_PD_PHY_SETTING1_RECEIVER_EN BIT(9) -#define RAA489000_PD_PHY_SETTING1_SQUELCH_EN BIT(8) +#define RAA489000_PD_PHY_SETTING1_SQUELCH_EN BIT(8) #define RAA489000_PD_PHY_SETTING1_TX_LDO11_EN BIT(0) /* PD_PHYSICAL_PARMETER_1 */ |