diff options
Diffstat (limited to 'zephyr/app/ec/chip')
| -rw-r--r-- | zephyr/app/ec/chip/CMakeLists.txt | 1 | ||||
| -rw-r--r-- | zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec | 6 | ||||
| -rw-r--r-- | zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x | 2 | ||||
| -rw-r--r-- | zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx | 6 | ||||
| -rw-r--r-- | zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 | 2 | ||||
| -rw-r--r-- | zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 | 2 | ||||
| -rw-r--r-- | zephyr/app/ec/chip/riscv/CMakeLists.txt | 1 | ||||
| -rw-r--r-- | zephyr/app/ec/chip/riscv/riscv-ite/CMakeLists.txt | 3 | ||||
| -rw-r--r-- | zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 | 2 | ||||
| -rw-r--r-- | zephyr/app/ec/chip/riscv/riscv-ite/it8xxx2-espi.c | 63 |
10 files changed, 82 insertions, 6 deletions
diff --git a/zephyr/app/ec/chip/CMakeLists.txt b/zephyr/app/ec/chip/CMakeLists.txt new file mode 100644 index 0000000000..e92dbc5d5d --- /dev/null +++ b/zephyr/app/ec/chip/CMakeLists.txt @@ -0,0 +1 @@ +add_subdirectory_ifdef(CONFIG_RISCV riscv)
\ No newline at end of file diff --git a/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec index d05ad020e7..3baca08d04 100644 --- a/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec +++ b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec @@ -1,4 +1,4 @@ -# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Copyright 2022 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. @@ -8,6 +8,10 @@ if SOC_FAMILY_MEC +# Enable MPU for ARM targets +config ARM_MPU + default y + # ADC config PLATFORM_EC_ADC_RESOLUTION default 10 diff --git a/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x index 9e37b6a534..bfcfeb8235 100644 --- a/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x +++ b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x @@ -1,4 +1,4 @@ -# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Copyright 2022 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx index 2da9252775..17936ab05d 100644 --- a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx +++ b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx @@ -1,4 +1,4 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. @@ -8,6 +8,10 @@ if SOC_FAMILY_NPCX +# Enable MPU for ARM targets +config ARM_MPU + default y + # Enable NPCX firmware header generator config NPCX_HEADER default y diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 index 37561f4dad..cb00db3345 100644 --- a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 +++ b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 @@ -1,4 +1,4 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 index aceec4f3ca..9c807a732c 100644 --- a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 +++ b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 @@ -1,4 +1,4 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/zephyr/app/ec/chip/riscv/CMakeLists.txt b/zephyr/app/ec/chip/riscv/CMakeLists.txt new file mode 100644 index 0000000000..b11c4e9a90 --- /dev/null +++ b/zephyr/app/ec/chip/riscv/CMakeLists.txt @@ -0,0 +1 @@ +add_subdirectory_ifdef(CONFIG_SOC_FAMILY_RISCV_ITE riscv-ite)
\ No newline at end of file diff --git a/zephyr/app/ec/chip/riscv/riscv-ite/CMakeLists.txt b/zephyr/app/ec/chip/riscv/riscv-ite/CMakeLists.txt new file mode 100644 index 0000000000..69608c33e3 --- /dev/null +++ b/zephyr/app/ec/chip/riscv/riscv-ite/CMakeLists.txt @@ -0,0 +1,3 @@ +if (CONFIG_ESPI_IT8XXX2) + zephyr_library_sources_ifdef(CONFIG_AP_POWER_CONTROL it8xxx2-espi.c) +endif ()
\ No newline at end of file diff --git a/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 b/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 index 809b9a6401..e0ea15c5b7 100644 --- a/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 +++ b/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 @@ -1,4 +1,4 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/zephyr/app/ec/chip/riscv/riscv-ite/it8xxx2-espi.c b/zephyr/app/ec/chip/riscv/riscv-ite/it8xxx2-espi.c new file mode 100644 index 0000000000..6109964cb9 --- /dev/null +++ b/zephyr/app/ec/chip/riscv/riscv-ite/it8xxx2-espi.c @@ -0,0 +1,63 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +#include <soc_espi.h> +#include <ap_power/ap_power.h> +#include <chipset.h> +#include <zephyr/devicetree.h> +#include <zephyr/logging/log.h> + +LOG_MODULE_REGISTER(ec_chip_it8xxx2_espi, CONFIG_ESPI_LOG_LEVEL); + +/* + * When eSPI CS# is held low, it prevents IT8xxx2 from entering deep doze. + * To allow deep doze and save power, disable the eSPI inputs while the AP is + * in G3. + */ +static const struct device *const espi_device = + DEVICE_DT_GET(DT_NODELABEL(espi0)); + +static void espi_enable_callback(struct ap_power_ev_callback *cb, + struct ap_power_ev_data data) +{ + switch (data.event) { + case AP_POWER_INITIALIZED: + /* When AP power state becomes known, sync eSPI enable */ + if (chipset_in_state(CHIPSET_STATE_HARD_OFF)) { + LOG_DBG("AP off; disabling eSPI"); + espi_it8xxx2_enable_pad_ctrl(espi_device, false); + } + break; + case AP_POWER_PRE_INIT: + case AP_POWER_HARD_OFF: { + bool enable = data.event == AP_POWER_PRE_INIT; + + LOG_DBG("%sabling eSPI in response to AP power event", + enable ? "en" : "dis"); + espi_it8xxx2_enable_pad_ctrl(espi_device, enable); + break; + } + default: + __ASSERT(false, "%s: unhandled event: %d", __func__, + data.event); + break; + } +} + +static int init_espi_enable_callback(const struct device *unused) +{ + static struct ap_power_ev_callback cb; + + if (!device_is_ready(espi_device)) + k_oops(); + + ap_power_ev_init_callback(&cb, espi_enable_callback, + AP_POWER_INITIALIZED | AP_POWER_PRE_INIT | + AP_POWER_HARD_OFF); + ap_power_ev_add_callback(&cb); + + return 0; +} +/* Should run before power sequencing init so INITIALIZED callback can fire */ +SYS_INIT(init_espi_enable_callback, APPLICATION, 0); |