1 files changed, 25 insertions, 71 deletions

diff --git a/zephyr/projects/brya/gpio.dts b/zephyr/projects/brya/gpio.dts
index 2b853f4d3b..6c6a2ac054 100644
--- a/zephyr/projects/brya/gpio.dts
+++ b/zephyr/projects/brya/gpio.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -132,10 +132,12 @@
 		gpio_pg_ec_dsw_pwrok: pg_ec_dsw_pwrok {
 			gpios = <&gpioc 7 GPIO_INPUT>;
 			enum-name = "GPIO_PG_EC_DSW_PWROK";
+			alias = "GPIO_SEQ_EC_DSW_PWROK";
 		};
 		en_s5_rails {
 			gpios = <&gpiob 6 GPIO_OUTPUT_LOW>;
 			enum-name = "GPIO_EN_S5_RAILS";
+			alias = "GPIO_TEMP_SENSOR_POWER";
 		};
 		sys_rst_odl {
 			gpios = <&gpioc 5 GPIO_ODR_HIGH>;
@@ -272,116 +274,68 @@
 		};
 		usb_c0_oc_odl {
 			gpios = <&ioex_port1 4 GPIO_ODR_HIGH>;
-			enum-name = "IOEX_USB_C0_OC_ODL";
 			no-auto-init;
 		};
-		usb_c0_frs_en {
+		usb_c0_frs_en: usb_c0_frs_en {
 			gpios = <&ioex_port1 6 GPIO_OUTPUT_LOW>;
 			enum-name = "IOEX_USB_C0_FRS_EN";
 			no-auto-init;
 		};
 		usb_c0_rt_rst_odl: usb_c0_rt_rst_odl {
 			gpios = <&ioex_port1 7 GPIO_ODR_LOW>;
-			enum-name = "IOEX_USB_C0_RT_RST_ODL";
 			no-auto-init;
 		};
 		usb_c2_rt_rst_odl: usb_c2_rt_rst_odl {
 			gpios = <&ioex_port2 2 GPIO_ODR_LOW>;
-			enum-name = "IOEX_USB_C2_RT_RST_ODL";
 			no-auto-init;
 		};
 		usb_c1_oc_odl {
 			gpios = <&ioex_port2 3 GPIO_ODR_HIGH>;
-			enum-name = "IOEX_USB_C1_OC_ODL";
 			no-auto-init;
 		};
 		usb_c2_oc_odl {
 			gpios = <&ioex_port2 4 GPIO_ODR_HIGH>;
-			enum-name = "IOEX_USB_C2_OC_ODL";
 			no-auto-init;
 		};
-		usb_c2_frs_en {
+		usb_c2_frs_en: usb_c2_frs_en {
 			gpios = <&ioex_port2 6 GPIO_OUTPUT_LOW>;
 			enum-name = "IOEX_USB_C2_FRS_EN";
 			no-auto-init;
 		};
+		/* unimplemented GPIOs */
+		entering-rw {
+			enum-name = "GPIO_ENTERING_RW";
+		};
 	};
 
 	usba-port-enable-list {
 		compatible = "cros-ec,usba-port-enable-pins";
 		enable-pins = <&gpio_en_pp5000_usba_r>;
 	};
-
-	vsby-psl-in-list {
-		/* Use PSL_IN1/2/3 as detection pins from hibernate mode */
-		psl-in-pads = <&psl_in1 &psl_in2 &psl_in3>;
-		status = "okay";
-	};
-};
-
-&i2c1_0 {
-	status = "okay";
-	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
-	pinctrl-names = "default";
-
-	nct3808_0_P1: nct3808_0_P1@70 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "nuvoton,nct38xx-gpio";
-		reg = <0x70>;
-		label = "NCT3808_0_P1";
-
-		ioex_port1: gpio@0 {
-			compatible = "nuvoton,nct38xx-gpio-port";
-			reg = <0x0>;
-			label = "NCT3808_0_P1_GPIO0";
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios = <8>;
-			pin_mask = <0xdc>;
-			pinmux_mask = <0xff>;
-		};
-	};
-
-	nct3808_0_P2: nct3808_0_P2@74 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "nuvoton,nct38xx-gpio";
-		reg = <0x74>;
-		label = "NCT3808_0_P2";
-
-		ioex_port2: gpio@0 {
-			compatible = "nuvoton,nct38xx-gpio-port";
-			reg = <0x0>;
-			label = "NCT3808_0_P2_GPIO0";
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios = <8>;
-			pin_mask = <0xdc>;
-			pinmux_mask = <0xff>;
-		};
-	};
-
-	nct3808_alert_1 {
-		compatible = "nuvoton,nct38xx-gpio-alert";
-		irq-gpios = <&gpioe 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
-		nct38xx-dev = <&nct3808_0_P1 &nct3808_0_P2>;
-		label = "NCT3808_ALERT_1";
-	};
 };
 
 /* Power switch logic input pads */
 /* LID_OPEN_OD */
-&psl_in1 {
-	flag = <NPCX_PSL_RISING_EDGE>;
+&psl_in1_gpd2 {
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
 };
 
 /* ACOK_EC_OD */
-&psl_in2 {
-	flag = <NPCX_PSL_RISING_EDGE>;
+&psl_in2_gp00 {
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
 };
 
 /* GSC_EC_PWR_BTN_ODL */
-&psl_in3 {
-	flag = <NPCX_PSL_FALLING_EDGE>;
+&psl_in3_gp01 {
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+/* Power domain device controlled by PSL (Power Switch Logic) IO pads */
+&power_ctrl_psl {
+	status = "okay";
+	pinctrl-names = "sleep";
+	pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01>;
 };