diff options
Diffstat (limited to 'zephyr/projects/intelrvp/adlrvp')
16 files changed, 209 insertions, 206 deletions
diff --git a/zephyr/projects/intelrvp/adlrvp/CMakeLists.txt b/zephyr/projects/intelrvp/adlrvp/CMakeLists.txt index bd961ff89d..71dee29552 100644 --- a/zephyr/projects/intelrvp/adlrvp/CMakeLists.txt +++ b/zephyr/projects/intelrvp/adlrvp/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Copyright 2022 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts index 418b68a8d7..79723beabd 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -20,37 +20,28 @@ named-i2c-ports { compatible = "named-i2c-ports"; - battery { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_BATTERY"; - }; i2c_charger: charger { i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_CHARGER"; - }; - eeprom { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_EEPROM"; - }; - port80 { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_PORT80"; + enum-names = "I2C_PORT_BATTERY", + "I2C_PORT_CHARGER", + "I2C_PORT_EEPROM", + "I2C_PORT_PORT80"; }; typec_0: typec-0 { i2c-port = <&i2c0_0>; - enum-name = "I2C_PORT_TYPEC_0"; + enum-names = "I2C_PORT_TYPEC_0"; }; typec_1: typec-1 { i2c-port = <&i2c2_0>; - enum-name = "I2C_PORT_TYPEC_1"; + enum-names = "I2C_PORT_TYPEC_1"; }; typec_2: typec-2 { i2c-port = <&i2c1_0>; - enum-name = "I2C_PORT_TYPEC_2"; + enum-names = "I2C_PORT_TYPEC_2"; }; typec_3: typec-3 { i2c-port = <&i2c3_0>; - enum-name = "I2C_PORT_TYPEC_3"; + enum-names = "I2C_PORT_TYPEC_3"; }; }; @@ -58,22 +49,18 @@ compatible = "named-adc-channels"; adc_ambient: ambient { - label = "ADC_TEMP_SNS_AMBIENT"; enum-name = "ADC_TEMP_SENSOR_1"; io-channels = <&adc0 3>; }; adc_ddr: ddr { - label = "ADC_TEMP_SNS_DDR"; enum-name = "ADC_TEMP_SENSOR_2"; io-channels = <&adc0 4>; }; adc_skin: skin { - label = "ADC_TEMP_SNS_SKIN"; enum-name = "ADC_TEMP_SENSOR_3"; io-channels = <&adc0 2>; }; adc_vr: vr { - label = "ADC_TEMP_SNS_VR"; enum-name = "ADC_TEMP_SENSOR_4"; io-channels = <&adc0 1>; }; @@ -130,6 +117,21 @@ reg = <0x38>; label = "MAX695X_SEVEN_SEG_DISPLAY"; }; + + charger: isl9241@9 { + compatible = "intersil,isl9241"; + status = "okay"; + reg = <0x9>; + }; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; }; &i2c_ctrl7 { @@ -142,6 +144,25 @@ clock-frequency = <I2C_BITRATE_FAST>; pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; pinctrl-names = "default"; + + tcpc_port0: fusb302@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + }; + + usb_c0_soc_side_bb_retimer: jhl8040r-c0-soc-side@54 { + compatible = "intel,jhl8040r"; + reg = <0x54>; + reset-pin = <&usb_c0_bb_retimer_rst>; + ls-en-pin = <&usb_c0_bb_retimer_ls_en>; + }; + + usb_c0_bb_retimer: jhl8040r-c0@56 { + compatible = "intel,jhl8040r"; + reg = <0x56>; + reset-pin = <&usb_c0_bb_retimer_rst>; + ls-en-pin = <&usb_c0_bb_retimer_ls_en>; + }; }; &i2c_ctrl0 { @@ -154,6 +175,25 @@ clock-frequency = <I2C_BITRATE_FAST>; pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>; pinctrl-names = "default"; + + tcpc_port1: fusb302@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + }; + + usb_c1_soc_side_bb_retimer: jhl8040r-c1-soc-side@55 { + compatible = "intel,jhl8040r"; + reg = <0x55>; + reset-pin = <&usb_c1_bb_retimer_rst>; + ls-en-pin = <&usb_c1_bb_retimer_ls_en>; + }; + + usb_c1_bb_retimer: jhl8040r-c1@57 { + compatible = "intel,jhl8040r"; + reg = <0x57>; + reset-pin = <&usb_c1_bb_retimer_rst>; + ls-en-pin = <&usb_c1_bb_retimer_ls_en>; + }; }; &i2c_ctrl2 { @@ -166,6 +206,18 @@ clock-frequency = <I2C_BITRATE_FAST>; pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; pinctrl-names = "default"; + + tcpc_port2: fusb302@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + }; + + usb_c2_bb_retimer: jhl8040r-c2@58 { + compatible = "intel,jhl8040r"; + reg = <0x58>; + reset-pin = <&usb_c2_bb_retimer_rst>; + ls-en-pin = <&usb_c2_bb_retimer_ls_en>; + }; }; &i2c_ctrl1 { @@ -178,6 +230,18 @@ clock-frequency = <I2C_BITRATE_FAST>; pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>; pinctrl-names = "default"; + + tcpc_port3: fusb302@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + }; + + usb_c3_bb_retimer: jhl8040r-c3@59 { + compatible = "intel,jhl8040r"; + reg = <0x59>; + reset-pin = <&usb_c3_bb_retimer_rst>; + ls-en-pin = <&usb_c3_bb_retimer_ls_en>; + }; }; &i2c_ctrl3 { diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/cbi_eeprom.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/cbi_eeprom.dts deleted file mode 100644 index efded14c3e..0000000000 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/cbi_eeprom.dts +++ /dev/null @@ -1,16 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -&i2c7_0 { - cbi_eeprom: eeprom@50 { - compatible = "atmel,at24"; - reg = <0x50>; - label = "EEPROM_CBI"; - size = <2048>; - pagesize = <16>; - address-width = <8>; - timeout = <5>; - }; -}; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/fan.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/fan.dts index 23f72dde94..8babe53903 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/fan.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/fan.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,7 +9,6 @@ fan_0 { pwms = <&pwm3 0 PWM_KHZ(30) PWM_POLARITY_NORMAL>; - pwm-frequency = <30000>; rpm_min = <3000>; rpm_start = <3000>; rpm_max = <10000>; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts index 7e1cb9c704..1d38fc877c 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -124,6 +124,7 @@ ec-ds3 { gpios = <&gpioc 4 GPIO_OUTPUT_LOW>; enum-name = "GPIO_EN_PP3300_A"; + alias = "GPIO_TEMP_SENSOR_POWER"; }; pch-pwrok-ec { gpios = <&gpioa 0 GPIO_INPUT>; @@ -319,11 +320,9 @@ }; usb-c2-usb-mux-cntrl-1 { gpios = <&ioex_c2_port 4 GPIO_OUTPUT_LOW>; - enum-name = "IOEX_USB_C2_USB_MUX_CNTRL_1"; }; usb-c2-usb-mux-cntrl-0 { gpios = <&ioex_c2_port 5 GPIO_OUTPUT_LOW>; - enum-name = "IOEX_USB_C2_USB_MUX_CNTRL_0"; }; usb_c3_bb_retimer_rst: usb-c3-bb-retimer-rst { gpios = <&ioex_c3_port 0 GPIO_OUTPUT_LOW>; @@ -337,5 +336,9 @@ gpios = <&ioex_c3_port 8 GPIO_OUTPUT_HIGH>; enum-name = "IOEX_USB_C2_C3_OC"; }; + /* unimplemented GPIOs */ + en-pp5000 { + enum-name = "GPIO_EN_PP5000"; + }; }; }; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts index e0992ef3b3..d7bb40fad2 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts index e735234128..81d6e82f48 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/prj.conf b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/prj.conf index 32919ea399..2c98fd9330 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/prj.conf +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/prj.conf @@ -1,4 +1,4 @@ -# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Copyright 2022 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/pwm_leds.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/pwm_leds.dts index 50a08a300e..eb1576dbff 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/pwm_leds.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/pwm_leds.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -7,10 +7,10 @@ pwmleds { compatible = "pwm-leds"; pwm_led0: pwm_led_0 { - pwms = <&pwm4 0 0 PWM_POLARITY_INVERTED>; + pwms = <&pwm4 0 PWM_HZ(4800) PWM_POLARITY_INVERTED>; }; pwm_led1: pwm_led_1 { - pwms = <&pwm5 0 0 PWM_POLARITY_INVERTED>; + pwms = <&pwm5 0 PWM_HZ(4800) PWM_POLARITY_INVERTED>; }; }; @@ -18,7 +18,6 @@ compatible = "cros-ec,pwm-leds"; leds = <&pwm_led0 &pwm_led1>; - frequency = <4800>; color-map-green = <100>; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/temp_sensor.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/temp_sensor.dts index a2fcacc1e1..93ecaa02f6 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/temp_sensor.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/temp_sensor.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -6,19 +6,36 @@ #include <cros/thermistor/thermistor.dtsi> / { + temp_ambient: ambient { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V0_22K6_47K_4050B>; + adc = <&adc_ambient>; + }; + temp_ddr: ddr { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V0_22K6_47K_4050B>; + adc = <&adc_ddr>; + }; + temp_skin: skin { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V0_22K6_47K_4050B>; + adc = <&adc_skin>; + }; + temp_vr: vr { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V0_22K6_47K_4050B>; + adc = <&adc_vr>; + }; + named-temp-sensors { + compatible = "cros-ec,temp-sensors"; ambient { - compatible = "cros-ec,temp-sensor-thermistor", - "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V0_22K6_47K_4050B>; - label = "Ambient"; - enum-name = "TEMP_SENSOR_1"; temp_fan_off = <15>; temp_fan_max = <50>; temp_host_high = <75>; temp_host_halt = <80>; temp_host_release_high = <65>; - adc = <&adc_ambient>; + sensor = <&temp_ambient>; }; /* @@ -30,7 +47,6 @@ * compatible = "cros-ec,temp-sensor-thermistor", * "cros-ec,temp-sensor"; * thermistor = < >; - * label = "Battery"; * enum-name = ""; * temp_fan_off = <15>; * temp_fan_max = <50>; @@ -42,43 +58,28 @@ */ ddr { - compatible = "cros-ec,temp-sensor-thermistor", - "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V0_22K6_47K_4050B>; - label = "DDR"; - enum-name = "TEMP_SENSOR_2"; temp_fan_off = <15>; temp_fan_max = <50>; temp_host_high = <75>; temp_host_halt = <80>; temp_host_release_high = <65>; - adc = <&adc_ddr>; + sensor = <&temp_ddr>; }; skin { - compatible = "cros-ec,temp-sensor-thermistor", - "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V0_22K6_47K_4050B>; - label = "Skin"; - enum-name = "TEMP_SENSOR_3"; temp_fan_off = <15>; temp_fan_max = <50>; temp_host_high = <75>; temp_host_halt = <80>; temp_host_release_high = <65>; - adc = <&adc_skin>; + sensor = <&temp_skin>; }; vr { - compatible = "cros-ec,temp-sensor-thermistor", - "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V0_22K6_47K_4050B>; - label = "VR"; - enum-name = "TEMP_SENSOR_4"; temp_fan_off = <15>; temp_fan_max = <50>; temp_host_high = <75>; temp_host_halt = <80>; temp_host_release_high = <65>; - adc = <&adc_vr>; + sensor = <&temp_vr>; }; }; }; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/usbc.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/usbc.dts index cd7c2b050f..471a1f52e9 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/usbc.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/usbc.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,27 +10,22 @@ usbc_port0: port0@0 { compatible = "named-usbc-port"; reg = <0>; - tcpc { - compatible = "fairchild,fusb302"; - status = "okay"; - port = <&typec_0>; - i2c-addr-flags = "FUSB302_I2C_ADDR_FLAGS"; + tcpc = <&tcpc_port0>; + chg = <&charger>; + usb_mux_chain_0: usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c0_bb_retimer + &virtual_mux_c0>; }; - chg { - compatible = "intersil,isl9241"; - status = "okay"; - port = <&i2c_charger>; + usb_mux_alt_chain_0: usb-mux-alt-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + alternative-chain; + usb-muxes = <&usb_c0_bb_retimer + &usb_c0_soc_side_bb_retimer + &virtual_mux_c0>; }; - usb-muxes = <&usb_c0_bb_retimer &virtual_mux_c0>; }; port0-muxes { - usb_c0_bb_retimer: jhl8040r-c0 { - compatible = "intel,jhl8040r"; - port = <&typec_0>; - i2c-addr-flags = <0x56>; - reset-pin = <&usb_c0_bb_retimer_rst>; - ls-en-pin = <&usb_c0_bb_retimer_ls_en>; - }; virtual_mux_c0: virtual-mux-c0 { compatible = "cros-ec,usbc-mux-virtual"; }; @@ -39,22 +34,21 @@ usbc_port1: port1@1 { compatible = "named-usbc-port"; reg = <1>; - tcpc { - compatible = "fairchild,fusb302"; - status = "okay"; - port = <&typec_1>; - i2c-addr-flags = "FUSB302_I2C_ADDR_FLAGS"; + tcpc = <&tcpc_port1>; + usb_mux_chain_1: usb-mux-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c1_bb_retimer + &virtual_mux_c1>; + }; + usb_mux_alt_chain_1: usb-mux-alt-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + alternative-chain; + usb-muxes = <&usb_c1_bb_retimer + &usb_c1_soc_side_bb_retimer + &virtual_mux_c1>; }; - usb-muxes = <&usb_c1_bb_retimer &virtual_mux_c1>; }; port1-muxes { - usb_c1_bb_retimer: jhl8040r-c1 { - compatible = "intel,jhl8040r"; - port = <&typec_1>; - i2c-addr-flags = <0x57>; - reset-pin = <&usb_c1_bb_retimer_rst>; - ls-en-pin = <&usb_c1_bb_retimer_ls_en>; - }; virtual_mux_c1: virtual-mux-c1 { compatible = "cros-ec,usbc-mux-virtual"; }; @@ -63,22 +57,14 @@ port2@2 { compatible = "named-usbc-port"; reg = <2>; - tcpc { - compatible = "fairchild,fusb302"; - status = "okay"; - port = <&typec_2>; - i2c-addr-flags = "FUSB302_I2C_ADDR_FLAGS"; + tcpc = <&tcpc_port2>; + usb_mux_chain_2: usb-mux-chain-2 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c2_bb_retimer + &virtual_mux_c2>; }; - usb-muxes = <&usb_c2_bb_retimer &virtual_mux_c2>; }; port2-muxes { - usb_c2_bb_retimer: jhl8040r-c2 { - compatible = "intel,jhl8040r"; - port = <&typec_2>; - i2c-addr-flags = <0x58>; - reset-pin = <&usb_c2_bb_retimer_rst>; - ls-en-pin = <&usb_c2_bb_retimer_ls_en>; - }; virtual_mux_c2: virtual-mux-c2 { compatible = "cros-ec,usbc-mux-virtual"; }; @@ -87,22 +73,14 @@ port3@3 { compatible = "named-usbc-port"; reg = <3>; - tcpc { - compatible = "fairchild,fusb302"; - status = "okay"; - port = <&typec_3>; - i2c-addr-flags = "FUSB302_I2C_ADDR_FLAGS"; + tcpc = <&tcpc_port3>; + usb_mux_chain_3: usb-mux-chain-3 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c3_bb_retimer + &virtual_mux_c3>; }; - usb-muxes = <&usb_c3_bb_retimer &virtual_mux_c3>; }; port3-muxes { - usb_c3_bb_retimer: jhl8040r-c3 { - compatible = "intel,jhl8040r"; - port = <&typec_3>; - i2c-addr-flags = <0x59>; - reset-pin = <&usb_c3_bb_retimer_rst>; - ls-en-pin = <&usb_c3_bb_retimer_ls_en>; - }; virtual_mux_c3: virtual-mux-c3 { compatible = "cros-ec,usbc-mux-virtual"; }; diff --git a/zephyr/projects/intelrvp/adlrvp/battery.dts b/zephyr/projects/intelrvp/adlrvp/battery.dts index 10b43d6baa..1de4111791 100644 --- a/zephyr/projects/intelrvp/adlrvp/battery.dts +++ b/zephyr/projects/intelrvp/adlrvp/battery.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h b/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h index 0061b11110..135fd4ef4f 100644 --- a/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h +++ b/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,27 +10,25 @@ #include "config.h" +#define I2C_ADDR_FUSB302_TCPC_AIC 0x22 +#define I2C_ADDR_SN5S330_TCPC_AIC_PPC 0x40 -#define I2C_ADDR_FUSB302_TCPC_AIC 0x22 -#define I2C_ADDR_SN5S330_TCPC_AIC_PPC 0x40 - -#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX 0x21 - +#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX 0x21 /* SOC side BB retimers (dual retimer config) */ -#define I2C_PORT0_BB_RETIMER_SOC_ADDR 0x54 +#define I2C_PORT0_BB_RETIMER_SOC_ADDR 0x54 #if defined(HAS_TASK_PD_C1) -#define I2C_PORT1_BB_RETIMER_SOC_ADDR 0x55 +#define I2C_PORT1_BB_RETIMER_SOC_ADDR 0x55 #endif -#define ADLM_LP4_RVP1_SKU_BOARD_ID 0x01 -#define ADLM_LP5_RVP2_SKU_BOARD_ID 0x02 -#define ADLM_LP5_RVP3_SKU_BOARD_ID 0x03 -#define ADLN_LP5_ERB_SKU_BOARD_ID 0x06 -#define ADLN_LP5_RVP_SKU_BOARD_ID 0x07 -#define ADLP_DDR5_RVP_SKU_BOARD_ID 0x12 -#define ADLP_LP5_T4_RVP_SKU_BOARD_ID 0x13 -#define ADL_RVP_BOARD_ID(id) ((id) & 0x3F) +#define ADLM_LP4_RVP1_SKU_BOARD_ID 0x01 +#define ADLM_LP5_RVP2_SKU_BOARD_ID 0x02 +#define ADLM_LP5_RVP3_SKU_BOARD_ID 0x03 +#define ADLN_LP5_ERB_SKU_BOARD_ID 0x06 +#define ADLN_LP5_RVP_SKU_BOARD_ID 0x07 +#define ADLP_DDR5_RVP_SKU_BOARD_ID 0x12 +#define ADLP_LP5_T4_RVP_SKU_BOARD_ID 0x13 +#define ADL_RVP_BOARD_ID(id) ((id)&0x3F) #define CONFIG_BATTERY_TYPE_NO_AUTO_DETECT diff --git a/zephyr/projects/intelrvp/adlrvp/ioex.dts b/zephyr/projects/intelrvp/adlrvp/ioex.dts index 93117de943..3e2227dacb 100644 --- a/zephyr/projects/intelrvp/adlrvp/ioex.dts +++ b/zephyr/projects/intelrvp/adlrvp/ioex.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/zephyr/projects/intelrvp/adlrvp/prj.conf b/zephyr/projects/intelrvp/adlrvp/prj.conf index 357b0bee66..1314277bc8 100644 --- a/zephyr/projects/intelrvp/adlrvp/prj.conf +++ b/zephyr/projects/intelrvp/adlrvp/prj.conf @@ -1,4 +1,4 @@ -# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Copyright 2022 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. @@ -71,4 +71,4 @@ CONFIG_GPIO_PCA95XX=y CONFIG_PLATFORM_EC_MAX695X_SEVEN_SEGMENT_DISPLAY=y # eSPI -CONFIG_PLATFORM_EC_ESPI_DEFAULT_VW_WIDTH_US=150 +CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US=150 diff --git a/zephyr/projects/intelrvp/adlrvp/src/adlrvp.c b/zephyr/projects/intelrvp/adlrvp/src/adlrvp.c index bcb9bba1a8..ce5196c60d 100644 --- a/zephyr/projects/intelrvp/adlrvp/src/adlrvp.c +++ b/zephyr/projects/intelrvp/adlrvp/src/adlrvp.c @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -29,9 +29,8 @@ #include "usbc_ppc.h" #include "util.h" - -#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args) -#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ##args) +#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args) /* TCPC AIC GPIO Configuration */ const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[] = { @@ -96,27 +95,6 @@ struct ppc_config_t ppc_chips[] = { BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == CONFIG_USB_PD_PORT_MAX_COUNT); unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); -/* USB Mux Configuration for Soc side BB-Retimers for Dual retimer config */ -static struct usb_mux soc_side_bb_retimer0_usb_mux = { - .usb_port = TYPE_C_PORT_0, - .next_mux = USB_MUX_NEXT_POINTER(DT_NODELABEL(usbc_port0), 0), - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_TYPEC_0, - .i2c_addr_flags = I2C_PORT0_BB_RETIMER_SOC_ADDR, -}; - -#if defined(HAS_TASK_PD_C1) -static struct usb_mux soc_side_bb_retimer1_usb_mux = { - .usb_port = TYPE_C_PORT_1, - .next_mux = USB_MUX_NEXT_POINTER(DT_NODELABEL(usbc_port1), 0), - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_TYPEC_1, - .i2c_addr_flags = I2C_PORT1_BB_RETIMER_SOC_ADDR, -}; -#endif - /* Cache BB retimer power state */ static bool cache_bb_enable[CONFIG_USB_PD_PORT_MAX_COUNT]; @@ -124,8 +102,8 @@ void board_overcurrent_event(int port, int is_overcurrented) { /* Port 0 & 1 and 2 & 3 share same line for over current indication */ #if defined(HAS_TASK_PD_C2) - enum ioex_signal oc_signal = port < TYPE_C_PORT_2 ? - IOEX_USB_C0_C1_OC : IOEX_USB_C2_C3_OC; + enum ioex_signal oc_signal = port < TYPE_C_PORT_2 ? IOEX_USB_C0_C1_OC : + IOEX_USB_C2_C3_OC; #else enum ioex_signal oc_signal = IOEX_USB_C0_C1_OC; #endif @@ -211,11 +189,11 @@ void set_charger_system_voltage(void) * on AC or AC+battery */ if (extpower_is_present() && battery_is_present()) { - bq25710_set_min_system_voltage(CHARGER_SOLO, - battery_get_info()->voltage_min); + bq25710_set_min_system_voltage( + CHARGER_SOLO, battery_get_info()->voltage_min); } else { - bq25710_set_min_system_voltage(CHARGER_SOLO, - battery_get_info()->voltage_max); + bq25710_set_min_system_voltage( + CHARGER_SOLO, battery_get_info()->voltage_max); } break; @@ -224,8 +202,7 @@ void set_charger_system_voltage(void) break; } } -DECLARE_HOOK(HOOK_AC_CHANGE, set_charger_system_voltage, - HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_AC_CHANGE, set_charger_system_voltage, HOOK_PRIO_DEFAULT); static void configure_charger(void) { @@ -246,26 +223,29 @@ static void configure_charger(void) static void configure_retimer_usbmux(void) { + struct usb_mux *mux; + switch (ADL_RVP_BOARD_ID(board_get_version())) { case ADLN_LP5_ERB_SKU_BOARD_ID: case ADLN_LP5_RVP_SKU_BOARD_ID: /* enable TUSB1044RNQR redriver on Port0 */ - usb_muxes[TYPE_C_PORT_0].i2c_addr_flags = - TUSB1064_I2C_ADDR14_FLAGS; - usb_muxes[TYPE_C_PORT_0].driver = - &tusb1064_usb_mux_driver; - usb_muxes[TYPE_C_PORT_0].hpd_update = tusb1044_hpd_update; + mux = USB_MUX_POINTER(DT_NODELABEL(usb_mux_chain_0), 0); + mux->i2c_addr_flags = TUSB1064_I2C_ADDR14_FLAGS; + mux->driver = &tusb1064_usb_mux_driver; + mux->hpd_update = tusb1044_hpd_update; #if defined(HAS_TASK_PD_C1) - usb_muxes[TYPE_C_PORT_1].driver = NULL; - usb_muxes[TYPE_C_PORT_1].hpd_update = NULL; + mux = USB_MUX_POINTER(DT_NODELABEL(usb_mux_chain_1), 0); + mux->driver = NULL; + mux->hpd_update = NULL; #endif break; case ADLP_LP5_T4_RVP_SKU_BOARD_ID: /* No retimer on Port-2 */ #if defined(HAS_TASK_PD_C2) - usb_muxes[TYPE_C_PORT_2].driver = NULL; + mux = USB_MUX_POINTER(DT_NODELABEL(usb_mux_chain_2), 0); + mux->driver = NULL; #endif break; @@ -275,15 +255,13 @@ static void configure_retimer_usbmux(void) * Change the default usb mux config on runtime to support * dual retimer topology. */ - usb_muxes[TYPE_C_PORT_0].next_mux - = &soc_side_bb_retimer0_usb_mux; + USB_MUX_ENABLE_ALTERNATIVE(usb_mux_alt_chain_0); #if defined(HAS_TASK_PD_C1) - usb_muxes[TYPE_C_PORT_1].next_mux - = &soc_side_bb_retimer1_usb_mux; + USB_MUX_ENABLE_ALTERNATIVE(usb_mux_alt_chain_1); #endif break; - /* Add additional board SKUs */ + /* Add additional board SKUs */ default: break; @@ -357,8 +335,7 @@ __override int board_get_version(void) * This loop retries to ensure rail is settled and read is successful */ for (i = 0; i < RVP_VERSION_READ_RETRY_CNT; i++) { - - rv = gpio_pin_get_dt(&bom_id_config[0]); + rv = gpio_pin_get_dt(&bom_id_config[0]); if (rv >= 0) break; @@ -374,21 +351,21 @@ __override int board_get_version(void) * BOM ID [2] : IOEX[0] * BOM ID [1:0] : IOEX[15:14] */ - bom_id = gpio_pin_get_dt(&bom_id_config[0]) << 2; + bom_id = gpio_pin_get_dt(&bom_id_config[0]) << 2; bom_id |= gpio_pin_get_dt(&bom_id_config[1]) << 1; bom_id |= gpio_pin_get_dt(&bom_id_config[2]); /* * FAB ID [1:0] : IOEX[2:1] + 1 */ - fab_id = gpio_pin_get_dt(&fab_id_config[0]) << 1; + fab_id = gpio_pin_get_dt(&fab_id_config[0]) << 1; fab_id |= gpio_pin_get_dt(&fab_id_config[1]); fab_id += 1; /* * BOARD ID[5:0] : IOEX[13:8] */ - board_id = gpio_pin_get_dt(&board_id_config[0]) << 5; + board_id = gpio_pin_get_dt(&board_id_config[0]) << 5; board_id |= gpio_pin_get_dt(&board_id_config[1]) << 4; board_id |= gpio_pin_get_dt(&board_id_config[2]) << 3; board_id |= gpio_pin_get_dt(&board_id_config[3]) << 2; @@ -450,4 +427,4 @@ static int board_pre_task_peripheral_init(const struct device *unused) return 0; } SYS_INIT(board_pre_task_peripheral_init, APPLICATION, - CONFIG_APPLICATION_INIT_PRIORITY); + CONFIG_APPLICATION_INIT_PRIORITY); |