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-rw-r--r--zephyr/projects/rex/BUILD.py45
-rw-r--r--zephyr/projects/rex/CMakeLists.txt12
-rw-r--r--zephyr/projects/rex/Kconfig11
-rw-r--r--zephyr/projects/rex/battery.dts12
-rw-r--r--zephyr/projects/rex/fan.dts39
-rw-r--r--zephyr/projects/rex/generated.dts362
-rw-r--r--zephyr/projects/rex/include/gpio_map.h9
-rw-r--r--zephyr/projects/rex/interrupts.dts65
-rw-r--r--zephyr/projects/rex/keyboard.dts34
-rw-r--r--zephyr/projects/rex/led.dts138
-rw-r--r--zephyr/projects/rex/motionsense.dts257
-rw-r--r--zephyr/projects/rex/power_signals.dts152
-rw-r--r--zephyr/projects/rex/prj.conf172
-rw-r--r--zephyr/projects/rex/prj_rex.conf9
-rw-r--r--zephyr/projects/rex/rex.dts239
-rw-r--r--zephyr/projects/rex/rex0_gpio.csv122
-rw-r--r--zephyr/projects/rex/src/board_power.c61
-rw-r--r--zephyr/projects/rex/src/usb_pd_policy.c77
-rw-r--r--zephyr/projects/rex/src/usbc_config.c288
-rw-r--r--zephyr/projects/rex/temp_sensors.dts69
-rw-r--r--zephyr/projects/rex/usbc.dts30
21 files changed, 2203 insertions, 0 deletions
diff --git a/zephyr/projects/rex/BUILD.py b/zephyr/projects/rex/BUILD.py
new file mode 100644
index 0000000000..2537f61226
--- /dev/null
+++ b/zephyr/projects/rex/BUILD.py
@@ -0,0 +1,45 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Rex Projects."""
+
+
+def register_variant(
+ project_name, extra_dts_overlays=(), extra_kconfig_files=()
+):
+ """Register a variant of rex."""
+ register_npcx_project(
+ project_name=project_name,
+ zephyr_board="npcx9m7f",
+ dts_overlays=[
+ # Common to all projects.
+ here / "rex.dts",
+ # Project-specific DTS customization.
+ *extra_dts_overlays,
+ ],
+ kconfig_files=[
+ # Common to all projects.
+ here / "prj.conf",
+ # Project-specific KConfig customization.
+ *extra_kconfig_files,
+ ],
+ )
+
+
+register_variant(
+ project_name="rex",
+ extra_dts_overlays=[
+ here / "generated.dts",
+ here / "interrupts.dts",
+ here / "power_signals.dts",
+ here / "battery.dts",
+ here / "usbc.dts",
+ here / "keyboard.dts",
+ here / "led.dts",
+ here / "fan.dts",
+ here / "temp_sensors.dts",
+ here / "motionsense.dts",
+ ],
+ extra_kconfig_files=[here / "prj_rex.conf"],
+)
diff --git a/zephyr/projects/rex/CMakeLists.txt b/zephyr/projects/rex/CMakeLists.txt
new file mode 100644
index 0000000000..27d7dff068
--- /dev/null
+++ b/zephyr/projects/rex/CMakeLists.txt
@@ -0,0 +1,12 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.20.5)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(rex)
+
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include")
+zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ "src/board_power.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/usbc_config.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/usb_pd_policy.c")
diff --git a/zephyr/projects/rex/Kconfig b/zephyr/projects/rex/Kconfig
new file mode 100644
index 0000000000..7d17c27815
--- /dev/null
+++ b/zephyr/projects/rex/Kconfig
@@ -0,0 +1,11 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config BOARD_REX
+ bool "Google Rex Baseboard"
+ help
+ Build Google Rex reference board. The board uses Nuvoton
+ NPCX9 chip as the EC.
+
+source "Kconfig.zephyr"
diff --git a/zephyr/projects/rex/battery.dts b/zephyr/projects/rex/battery.dts
new file mode 100644
index 0000000000..e11346f48d
--- /dev/null
+++ b/zephyr/projects/rex/battery.dts
@@ -0,0 +1,12 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+ batteries {
+ default_battery: batgqa05l22 {
+ compatible = "powertech,batgqa05l22", "battery-smart";
+ };
+ };
+};
diff --git a/zephyr/projects/rex/fan.dts b/zephyr/projects/rex/fan.dts
new file mode 100644
index 0000000000..aa6dcfde7d
--- /dev/null
+++ b/zephyr/projects/rex/fan.dts
@@ -0,0 +1,39 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+ fans {
+ compatible = "cros-ec,fans";
+
+ fan_0 {
+ pwms = <&pwm5 0 PWM_KHZ(1) PWM_POLARITY_NORMAL>;
+ rpm_min = <2200>;
+ rpm_start = <2200>;
+ rpm_max = <4200>;
+ tach = <&tach1>;
+ enable_gpio = <&gpio_en_pp5000_fan>;
+ };
+ };
+};
+
+/* Tachemeter for fan speed measurement */
+&tach1 {
+ status = "okay";
+ pinctrl-0 = <&ta1_1_in_gp40>;
+ pinctrl-names = "default";
+ port = <NPCX_TACH_PORT_A>; /* port-A is selected */
+ sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
+ pulses-per-round = <2>; /* number of pulses per round of encoder */
+};
+
+&pwm5_gpb7 {
+ drive-open-drain;
+};
+
+&pwm5 {
+ status = "okay";
+ pinctrl-0 = <&pwm5_gpb7>;
+ pinctrl-names = "default";
+};
diff --git a/zephyr/projects/rex/generated.dts b/zephyr/projects/rex/generated.dts
new file mode 100644
index 0000000000..549f0e5fde
--- /dev/null
+++ b/zephyr/projects/rex/generated.dts
@@ -0,0 +1,362 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * This file is auto-generated - do not edit!
+ *
+ * TODO(b:/244441996): There are some errors in the main Rex EC GPIO spreadsheet
+ * which is used as input to create this device tree file. Until that issue is
+ * resolved, there are some edits required to this file to support EC
+ * functionality.
+ */
+
+/ {
+
+ named-adc-channels {
+ compatible = "named-adc-channels";
+
+ adc_ddr_soc: ddr_soc {
+ enum-name = "ADC_TEMP_SENSOR_1_DDR_SOC";
+ io-channels = <&adc0 0>;
+ };
+ adc_ambient: ambient {
+ enum-name = "ADC_TEMP_SENSOR_2";
+ io-channels = <&adc0 1>;
+ };
+ adc_charger: charger {
+ enum-name = "ADC_TEMP_SENSOR_3";
+ io-channels = <&adc0 8>;
+ };
+ adc_wwan: wwan {
+ enum-name = "ADC_TEMP_SENSOR_4";
+ io-channels = <&adc0 7>;
+ };
+ };
+
+ named-gpios {
+ compatible = "named-gpios";
+
+ gpio_acok_od: acok_od {
+ gpios = <&gpio0 0 GPIO_INPUT>;
+ enum-name = "GPIO_AC_PRESENT";
+ };
+ gpio_ccd_mode_odl: ccd_mode_odl {
+ gpios = <&gpioe 5 GPIO_ODR_LOW>;
+ enum-name = "GPIO_CCD_MODE_ODL";
+ };
+ gpio_cpu_c10_gate_l: cpu_c10_gate_l {
+ gpios = <&gpioa 7 GPIO_INPUT>;
+ };
+ gpio_ec_accel_int_r_l: ec_accel_int_r_l {
+ gpios = <&gpio8 1 GPIO_INPUT>;
+ };
+ gpio_ec_als_rgb_int_r_l: ec_als_rgb_int_r_l {
+ gpios = <&gpiod 4 GPIO_INPUT_PULL_UP>;
+ };
+ gpio_ec_batt_pres_odl: ec_batt_pres_odl {
+ gpios = <&gpioa 3 GPIO_INPUT>;
+ enum-name = "GPIO_BATT_PRES_ODL";
+ };
+ gpio_ec_cbi_wp: ec_cbi_wp {
+ gpios = <&gpio7 3 GPIO_OUTPUT>;
+ };
+ gpio_ec_edp_bl_en: ec_edp_bl_en {
+ gpios = <&gpiod 3 GPIO_OUTPUT_LOW>;
+ enum-name = "GPIO_ENABLE_BACKLIGHT";
+ };
+ gpio_ec_gsc_packet_mode: ec_gsc_packet_mode {
+ gpios = <&gpio7 5 GPIO_ODR_HIGH>;
+ enum-name = "GPIO_PACKET_MODE_EN";
+ };
+ gpio_ec_imu_int_r_l: ec_imu_int_r_l {
+ gpios = <&gpio5 6 GPIO_INPUT_PULL_UP>;
+ };
+ gpio_ec_imvp92_en_smb: ec_imvp92_en_smb {
+ gpios = <&gpiob 1 GPIO_OUTPUT>;
+ };
+ gpio_ec_kb_bl_en_l: ec_kb_bl_en_l {
+ gpios = <&gpio8 6 GPIO_OUTPUT>;
+ };
+ gpio_ec_kso_02_inv: ec_kso_02_inv {
+ gpios = <&gpio1 7 (GPIO_OUTPUT | GPIO_ACTIVE_LOW)>;
+ };
+ gpio_ec_prochot_in_l: ec_prochot_in_l {
+ gpios = <&gpiof 0 GPIO_INPUT>;
+ };
+ gpio_ec_prochot_odl: ec_prochot_odl {
+ gpios = <&gpio6 3 GPIO_ODR_HIGH>;
+ };
+ gpio_ec_rst_r_odl: ec_rst_r_odl {
+ gpios = <&gpio7 7 GPIO_INPUT>;
+ };
+ gpio_ec_soc_int_odl: ec_soc_int_odl {
+ gpios = <&gpio7 0 GPIO_ODR_LOW>;
+ enum-name = "GPIO_EC_INT_L";
+ };
+ gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl {
+ gpios = <&gpioc 1 GPIO_ODR_LOW>;
+ enum-name = "GPIO_PCH_PWRBTN_L";
+ };
+ gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+ gpios = <&gpioa 6 GPIO_OUTPUT>;
+ };
+ gpio_ec_soc_rtcrst: ec_soc_rtcrst {
+ gpios = <&gpio7 6 GPIO_ODR_HIGH>;
+ };
+ gpio_ec_soc_wake_r_odl: ec_soc_wake_r_odl {
+ gpios = <&gpioc 0 GPIO_ODR_LOW>;
+ };
+ gpio_ec_spare_gpio42: ec_spare_gpio42 {
+ gpios = <&gpio4 2 GPIO_OUTPUT>;
+ };
+ gpio_ec_spare_gpio66: ec_spare_gpio66 {
+ gpios = <&gpio6 6 GPIO_OUTPUT>;
+ };
+ gpio_ec_spare_gpio94: ec_spare_gpio94 {
+ gpios = <&gpio9 4 GPIO_OUTPUT>;
+ };
+ gpio_ec_spare_gpioa2: ec_spare_gpioa2 {
+ gpios = <&gpioa 2 GPIO_OUTPUT>;
+ };
+ gpio_ec_spare_gpioa4: ec_spare_gpioa4 {
+ gpios = <&gpioa 4 GPIO_OUTPUT>;
+ };
+ gpio_ec_spare_gpioc7: ec_spare_gpioc7 {
+ gpios = <&gpioc 7 GPIO_OUTPUT>;
+ };
+ gpio_ec_spare_gpo32: ec_spare_gpo32 {
+ gpios = <&gpio3 2 GPIO_OUTPUT>;
+ };
+ gpio_ec_spare_gpo35: ec_spare_gpo35 {
+ gpios = <&gpio3 5 GPIO_OUTPUT>;
+ };
+ gpio_ec_voldn_btn_odl: ec_voldn_btn_odl {
+ gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>;
+ enum-name = "GPIO_VOLUME_DOWN_L";
+ };
+ gpio_ec_volup_btn_odl: ec_volup_btn_odl {
+ gpios = <&gpio9 7 GPIO_INPUT_PULL_UP>;
+ enum-name = "GPIO_VOLUME_UP_L";
+ };
+ gpio_ec_wp_l: ec_wp_l {
+ gpios = <&gpioa 1 GPIO_INPUT>;
+ };
+ gpio_en_pp5000_fan: en_pp5000_fan {
+ gpios = <&gpio6 1 GPIO_OUTPUT_LOW>;
+ };
+ gpio_en_pp5000_usba_r: en_pp5000_usba_r {
+ gpios = <&gpiod 7 GPIO_OUTPUT>;
+ };
+ gpio_en_s5_rails: en_s5_rails {
+ gpios = <&gpiob 6 GPIO_ODR_HIGH>;
+ enum-name = "GPIO_TEMP_SENSOR_POWER";
+ };
+ gpio_en_z1_rails: en_z1_rails {
+ gpios = <&gpio8 5 GPIO_OUTPUT>;
+ };
+ gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl {
+ gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>;
+ };
+ gpio_imvp92_vrrdy_od: imvp92_vrrdy_od {
+ gpios = <&gpio4 3 GPIO_INPUT>;
+ };
+ gpio_led_1_l: led_1_l {
+ gpios = <&gpioc 4 GPIO_OUTPUT>;
+ };
+ gpio_led_2_l: led_2_l {
+ gpios = <&gpioc 3 GPIO_OUTPUT>;
+ };
+ gpio_led_3_l: led_3_l {
+ gpios = <&gpioc 2 GPIO_OUTPUT>;
+ };
+ gpio_led_4_l: led_4_l {
+ gpios = <&gpio6 0 GPIO_OUTPUT>;
+ };
+ gpio_lid_open: lid_open {
+ gpios = <&gpiod 2 GPIO_INPUT_PULL_UP>;
+ enum-name = "GPIO_LID_OPEN";
+ };
+ gpio_mech_pwr_btn_odl: mech_pwr_btn_odl {
+ gpios = <&gpio0 2 GPIO_INPUT>;
+ enum-name = "GPIO_POWER_BUTTON_L";
+ };
+ gpio_seq_ec_all_sys_pg: seq_ec_all_sys_pg {
+ gpios = <&gpiof 4 GPIO_INPUT>;
+ };
+ gpio_seq_ec_rsmrst_odl: seq_ec_rsmrst_odl {
+ gpios = <&gpioe 2 GPIO_INPUT>;
+ };
+ gpio_slp_s3_ls_l: slp_s3_ls_l {
+ gpios = <&gpio4 1 GPIO_INPUT>;
+ };
+ gpio_sochot_odl: sochot_odl {
+ gpios = <&gpio9 6 GPIO_INPUT>;
+ };
+ gpio_soc_pwrok: soc_pwrok {
+ gpios = <&gpioa 5 GPIO_OUTPUT>;
+ };
+ gpio_sys_pwrok: sys_pwrok {
+ gpios = <&gpiob 0 GPIO_OUTPUT>;
+ };
+ gpio_sys_rst_odl: sys_rst_odl {
+ gpios = <&gpioc 5 GPIO_INPUT>;
+ };
+ gpio_sys_slp_s0ix_3v3_l: sys_slp_s0ix_3v3_l {
+ gpios = <&gpiod 5 GPIO_INPUT>;
+ };
+ gpio_tablet_mode_l: tablet_mode_l {
+ gpios = <&gpio9 5 GPIO_INPUT_PULL_UP>;
+ enum-name = "GPIO_TABLET_MODE_L";
+ };
+ gpio_usb_c0_bc12_int_odl: usb_c0_bc12_int_odl {
+ gpios = <&gpioc 6 GPIO_INPUT>;
+ enum-name = "GPIO_USB_C0_BC12_INT_ODL";
+ };
+ gpio_usb_c0_ppc_int_odl: usb_c0_ppc_int_odl {
+ gpios = <&gpio6 2 GPIO_INPUT>;
+ enum-name = "GPIO_USB_C0_PPC_INT_ODL";
+ };
+ gpio_usb_c0_rt_3p3_sx_en: usb_c0_rt_3p3_sx_en {
+ gpios = <&gpio0 3 GPIO_OUTPUT_LOW>;
+ };
+ gpio_usb_c0_rt_int_odl: usb_c0_rt_int_odl {
+ gpios = <&gpioa 0 GPIO_INPUT>;
+ };
+ gpio_usb_c0_tcpc_int_odl: usb_c0_tcpc_int_odl {
+ gpios = <&gpioe 0 GPIO_INPUT>;
+ enum-name = "GPIO_USB_C0_TCPC_INT_ODL";
+ };
+ gpio_usb_c0_tcpc_rst_odl: usb_c0_tcpc_rst_odl {
+ gpios = <&gpio6 7 GPIO_ODR_HIGH>;
+ };
+ gpio_usb_c1_bc12_int_odl: usb_c1_bc12_int_odl {
+ gpios = <&gpio5 0 GPIO_INPUT>;
+ enum-name = "GPIO_USB_C1_BC12_INT_ODL";
+ };
+ gpio_usb_c1_frs_en: usb_c1_frs_en {
+ gpios = <&gpio8 3 GPIO_ODR_HIGH>;
+ };
+ gpio_usb_c1_ppc_int_odl: usb_c1_ppc_int_odl {
+ gpios = <&gpiof 5 GPIO_INPUT>;
+ enum-name = "GPIO_USB_C1_PPC_INT_ODL";
+ };
+ gpio_usb_c1_rst_odl: usb_c1_rst_odl {
+ gpios = <&gpio3 7 GPIO_ODR_LOW>;
+ };
+ gpio_usb_c1_rt_int_odl: usb_c1_rt_int_odl {
+ gpios = <&gpio7 2 GPIO_INPUT_PULL_UP>;
+ };
+ gpio_usb_c1_rt_rst_r_odl: usb_c1_rt_rst_r_odl {
+ gpios = <&gpio7 4 GPIO_ODR_HIGH>;
+ };
+ gpio_usb_c1_tcpc_int_odl: usb_c1_tcpc_int_odl {
+ gpios = <&gpio3 4 GPIO_INPUT>;
+ enum-name = "GPIO_USB_C1_TCPC_INT_ODL";
+ };
+ };
+
+ named-i2c-ports {
+ compatible = "named-i2c-ports";
+
+ i2c_ec_i2c_sensor: ec_i2c_sensor {
+ i2c-port = <&i2c0_0>;
+ enum-names = "I2C_PORT_SENSOR";
+ };
+ i2c_ec_i2c_usb_c0_tcp: ec_i2c_usb_c0_tcp {
+ i2c-port = <&i2c1_0>;
+ enum-names = "I2C_PORT_USB_C0_TCPC";
+ };
+ i2c_ec_i2c_usb_c0_ppc_b: ec_i2c_usb_c0_ppc_b {
+ i2c-port = <&i2c2_0>;
+ enum-names = "I2C_PORT_PPC0";
+ };
+ i2c_ec_i2c_usb_c0_rt: ec_i2c_usb_c0_rt {
+ i2c-port = <&i2c3_0>;
+ enum-names = "I2C_PORT_USB_C0_RT";
+ };
+ i2c_ec_i2c_usb_c1_tcp: ec_i2c_usb_c1_tcp {
+ i2c-port = <&i2c4_1>;
+ enum-names = "I2C_PORT_USB_C1_TCPC";
+ };
+ i2c_ec_i2c_bat: ec_i2c_bat {
+ i2c-port = <&i2c5_0>;
+ enum-names = "I2C_PORT_BATTERY";
+ };
+ i2c_ec_i2c_usb_c1_mix: ec_i2c_usb_c1_mix {
+ i2c-port = <&i2c6_1>;
+ enum-names = "I2C_PORT_USB_1_MIX";
+ };
+ i2c_ec_i2c_mi: ec_i2c_mi {
+ i2c-port = <&i2c7_0>;
+ enum-names = "I2C_PORT_EEPROM";
+ };
+ };
+};
+
+&adc0 {
+ status = "okay";
+};
+
+&i2c0_0 {
+ status = "okay";
+};
+
+&i2c1_0 {
+ status = "okay";
+};
+
+&i2c2_0 {
+ status = "okay";
+};
+
+&i2c3_0 {
+ status = "okay";
+};
+
+&i2c4_1 {
+ status = "okay";
+};
+
+&i2c5_0 {
+ status = "okay";
+};
+
+&i2c6_1 {
+ status = "okay";
+};
+
+&i2c7_0 {
+ status = "okay";
+};
+
+&i2c_ctrl0 {
+ status = "okay";
+};
+
+&i2c_ctrl1 {
+ status = "okay";
+};
+
+&i2c_ctrl2 {
+ status = "okay";
+};
+
+&i2c_ctrl3 {
+ status = "okay";
+};
+
+&i2c_ctrl4 {
+ status = "okay";
+};
+
+&i2c_ctrl5 {
+ status = "okay";
+};
+
+&i2c_ctrl6 {
+ status = "okay";
+};
+
+&i2c_ctrl7 {
+ status = "okay";
+};
diff --git a/zephyr/projects/rex/include/gpio_map.h b/zephyr/projects/rex/include/gpio_map.h
new file mode 100644
index 0000000000..01cbc44396
--- /dev/null
+++ b/zephyr/projects/rex/include/gpio_map.h
@@ -0,0 +1,9 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_GPIO_MAP_H
+#define __ZEPHYR_GPIO_MAP_H
+
+#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/rex/interrupts.dts b/zephyr/projects/rex/interrupts.dts
new file mode 100644
index 0000000000..7c4e6bca58
--- /dev/null
+++ b/zephyr/projects/rex/interrupts.dts
@@ -0,0 +1,65 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+ gpio-interrupts {
+ compatible = "cros-ec,gpio-interrupts";
+
+ int_ac_present: ac_present {
+ irq-pin = <&gpio_acok_od>;
+ flags = <GPIO_INT_EDGE_BOTH>;
+ handler = "extpower_interrupt";
+ };
+ int_power_button: power_button {
+ irq-pin = <&gpio_mech_pwr_btn_odl>;
+ flags = <GPIO_INT_EDGE_BOTH>;
+ handler = "power_button_interrupt";
+ };
+ int_lid_open: lid_open {
+ irq-pin = <&gpio_lid_open>;
+ flags = <GPIO_INT_EDGE_BOTH>;
+ handler = "lid_interrupt";
+ };
+ int_usb_c0_sbu_fault: c0_sbu_fault {
+ irq-pin = <&ioex_usb_c0_sbu_fault_odl>;
+ flags = <GPIO_INT_EDGE_FALLING>;
+ handler = "sbu_fault_interrupt";
+ };
+ int_usb_c0_tcpc: usb_c0_tcpc {
+ irq-pin = <&gpio_usb_c0_tcpc_int_odl>;
+ flags = <GPIO_INT_EDGE_FALLING>;
+ handler = "tcpc_alert_event";
+ };
+ int_usb_c0_ppc: usb_c0_ppc {
+ irq-pin = <&gpio_usb_c0_ppc_int_odl>;
+ flags = <GPIO_INT_EDGE_FALLING>;
+ handler = "ppc_interrupt";
+ };
+ int_usb_c0_bc12: usb_c0_bc12 {
+ irq-pin = <&gpio_usb_c0_bc12_int_odl>;
+ flags = <GPIO_INT_EDGE_FALLING>;
+ handler = "bc12_interrupt";
+ };
+ int_imu: ec_imu {
+ irq-pin = <&gpio_ec_imu_int_r_l>;
+ flags = <GPIO_INT_EDGE_FALLING>;
+ handler = "lsm6dso_interrupt";
+ };
+ int_als_rgb: ec_als_rgb {
+ irq-pin = <&gpio_ec_als_rgb_int_r_l>;
+ flags = <GPIO_INT_EDGE_FALLING>;
+ handler = "tcs3400_interrupt";
+ };
+ int_accel: ec_accel {
+ irq-pin = <&gpio_ec_accel_int_r_l>;
+ flags = <GPIO_INT_EDGE_FALLING>;
+ handler = "lis2dw12_interrupt";
+ };
+ };
+};
+
+/* Required node label that doesn't is named differently on Rex */
+gpio_ec_pch_wake_odl: &gpio_ec_soc_wake_r_odl {};
+
diff --git a/zephyr/projects/rex/keyboard.dts b/zephyr/projects/rex/keyboard.dts
new file mode 100644
index 0000000000..5248c4aaff
--- /dev/null
+++ b/zephyr/projects/rex/keyboard.dts
@@ -0,0 +1,34 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+&cros_kb_raw {
+ status = "okay";
+ /* No KSO2 (it's inverted and implemented by GPIO) */
+ pinctrl-0 = <
+ &ksi0_gp31
+ &ksi1_gp30
+ &ksi2_gp27
+ &ksi3_gp26
+ &ksi4_gp25
+ &ksi5_gp24
+ &ksi6_gp23
+ &ksi7_gp22
+ &kso00_gp21
+ &kso01_gp20
+ &kso03_gp16
+ &kso04_gp15
+ &kso05_gp14
+ &kso06_gp13
+ &kso07_gp12
+ &kso08_gp11
+ &kso09_gp10
+ &kso10_gp07
+ &kso11_gp06
+ &kso12_gp05
+ &kso13_gp04
+ &kso14_gp82
+ >;
+ pinctrl-names = "default";
+};
diff --git a/zephyr/projects/rex/led.dts b/zephyr/projects/rex/led.dts
new file mode 100644
index 0000000000..94acb6da5c
--- /dev/null
+++ b/zephyr/projects/rex/led.dts
@@ -0,0 +1,138 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+ gpio-led-pins {
+ compatible = "cros-ec,gpio-led-pins";
+
+ color_off: color-off {
+ led-color = "LED_OFF";
+ led-id = "EC_LED_ID_BATTERY_LED";
+ led-pins = <&gpio_led_1_l 1>,
+ <&gpio_led_2_l 1>;
+ };
+
+ color_white: color-white {
+ led-color = "LED_WHITE";
+ led-id = "EC_LED_ID_BATTERY_LED";
+ br-color = "EC_LED_COLOR_WHITE";
+ led-pins = <&gpio_led_1_l 1>,
+ <&gpio_led_2_l 0>;
+ };
+
+ color_amber: color-amber {
+ led-color = "LED_AMBER";
+ led-id = "EC_LED_ID_BATTERY_LED";
+ br-color = "EC_LED_COLOR_AMBER";
+ led-pins = <&gpio_led_1_l 0>,
+ <&gpio_led_2_l 1>;
+ };
+ };
+
+ led-colors {
+ compatible = "cros-ec,led-policy";
+
+ power-state-charge {
+ charge-state = "PWR_STATE_CHARGE";
+
+ color-0 {
+ led-color = <&color_amber>;
+ };
+ };
+
+ power-state-discharge-s0 {
+ charge-state = "PWR_STATE_DISCHARGE";
+ chipset-state = "POWER_S0";
+
+ color-0 {
+ led-color = <&color_off>;
+ };
+ };
+
+ power-state-discharge-s3 {
+ charge-state = "PWR_STATE_DISCHARGE";
+ chipset-state = "POWER_S3";
+
+ /* Blue 1 sec, off 3 sec */
+ color-0 {
+ led-color = <&color_white>;
+ period-ms = <1000>;
+ };
+ color-1 {
+ led-color = <&color_off>;
+ period-ms = <3000>;
+ };
+ };
+
+ power-state-discharge-s5 {
+ charge-state = "PWR_STATE_DISCHARGE";
+ chipset-state = "POWER_S5";
+
+ color-0 {
+ led-color = <&color_off>;
+ };
+ };
+
+ power-state-error {
+ charge-state = "PWR_STATE_ERROR";
+
+ /* Red 1 sec, off 1 sec */
+ color-0 {
+ led-color = <&color_white>;
+ period-ms = <1000>;
+ };
+ color-1 {
+ led-color = <&color_off>;
+ period-ms = <1000>;
+ };
+ };
+
+ power-state-near-full {
+ charge-state = "PWR_STATE_CHARGE_NEAR_FULL";
+
+ color-0 {
+ led-color = <&color_amber>;
+ };
+ };
+
+ power-state-forced-idle {
+ charge-state = "PWR_STATE_FORCED_IDLE";
+
+ /* White 2 sec, Amber 2 sec */
+ color-0 {
+ led-color = <&color_white>;
+ period-ms = <2000>;
+ };
+ color-1 {
+ led-color = <&color_amber>;
+ period-ms = <2000>;
+ };
+ };
+
+ power-state-idle-default {
+ charge-state = "PWR_STATE_IDLE";
+
+ color-0 {
+ led-color = <&color_white>;
+ };
+ };
+ };
+};
+
+&gpio_led_1_l {
+ #led-pin-cells = <1>;
+};
+
+&gpio_led_2_l {
+ #led-pin-cells = <1>;
+};
+
+&gpio_led_3_l {
+ #led-pin-cells = <1>;
+};
+
+&gpio_led_4_l {
+ #led-pin-cells = <1>;
+};
diff --git a/zephyr/projects/rex/motionsense.dts b/zephyr/projects/rex/motionsense.dts
new file mode 100644
index 0000000000..8b1c80921b
--- /dev/null
+++ b/zephyr/projects/rex/motionsense.dts
@@ -0,0 +1,257 @@
+/*
+ * Copyright 2022 The ChromiumOS Authors
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+ aliases {
+ /*
+ * motion sense's <>_INT_EVENT is handled
+ * by alias. Using the alias, each driver creates
+ * its own <>_INT_EVENT.
+ */
+ lsm6dso-int = &base_accel;
+ lis2dw12-int = &lid_accel;
+ tcs3400-int = &als_clear;
+ };
+
+ /*
+ * Declare mutexes used by sensor drivers.
+ * A mutex node is used to create an instance of mutex_t.
+ * A mutex node is referenced by a sensor node if the
+ * corresponding sensor driver needs to use the
+ * instance of the mutex.
+ */
+ motionsense-mutex {
+ compatible = "cros-ec,motionsense-mutex";
+ mutex_lis2dw12: lis2dw12-mutex {
+ };
+
+ mutex_lsm6dso: lsm6dso-mutex {
+ };
+ };
+
+ /* Rotation matrix used by drivers. */
+ motionsense-rotation-ref {
+ compatible = "cros-ec,motionsense-rotation-ref";
+ lid_rot_ref: lid-rotation-ref {
+ mat33 = <0 1 0
+ 1 0 0
+ 0 0 (-1)>;
+ };
+ base_rot_ref: base-rotation-ref {
+ mat33 = <1 0 0
+ 0 (-1) 0
+ 0 0 (-1)>;
+ };
+ };
+
+ /*
+ * Driver specific data. A driver-specific data can be shared with
+ * different motion sensors while they are using the same driver.
+ *
+ * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+ * a common structure defined in accelgyro.h.
+ * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+ * "struct als_drv_data_t" in accelgyro.h
+ */
+ motionsense-sensor-data {
+ lis2dw12_data: lis2dw12-drv-data {
+ compatible = "cros-ec,drvdata-lis2dw12";
+ status = "okay";
+ };
+
+ lsm6dso_accel_data: lsm6dso-drv-data {
+ compatible = "cros-ec,drvdata-lsm6dso";
+ status = "okay";
+ };
+
+ lsm6dso_gyro_data: lsm6dso-drv-data {
+ compatible = "cros-ec,drvdata-lsm6dso";
+ status = "okay";
+ };
+
+ tcs_clear_data: tcs3400-clear-drv-data {
+ compatible = "cros-ec,drvdata-tcs3400-clear";
+ status = "okay";
+
+ als-drv-data {
+ compatible = "cros-ec,accelgyro-als-drv-data";
+ als-cal {
+ scale = <1>;
+ uscale = <0>;
+ offset = <0>;
+ als-channel-scale {
+ compatible =
+ "cros-ec,accelgyro-als-channel-scale";
+ k-channel-scale = <1>;
+ cover-scale = <1>;
+ };
+ };
+ };
+ };
+
+ tcs_rgb_data: tcs3400-rgb-drv-data {
+ compatible = "cros-ec,drvdata-tcs3400-rgb";
+ status = "okay";
+
+ /* node for rgb_calibration_t defined in accelgyro.h */
+ rgb_calibration {
+ compatible =
+ "cros-ec,accelgyro-rgb-calibration";
+
+ irt = <1>;
+
+ rgb-cal-x {
+ offset = <0>;
+ coeff = <0 0 0 1>;
+ als-channel-scale {
+ compatible =
+ "cros-ec,accelgyro-als-channel-scale";
+ k-channel-scale = <1>;
+ cover-scale = <1>;
+ };
+ };
+ rgb-cal-y {
+ offset = <0>;
+ coeff = <0 0 0 1>;
+ als-channel-scale {
+ compatible =
+ "cros-ec,accelgyro-als-channel-scale";
+ k-channel-scale = <1>;
+ cover-scale = <1>;
+ };
+ };
+ rgb-cal-z {
+ offset = <0>;
+ coeff = <0 0 0 1>;
+ als-channel-scale {
+ compatible =
+ "cros-ec,accelgyro-als-channel-scale";
+ k-channel-scale = <1>;
+ cover-scale = <1>;
+ };
+ };
+ };
+ };
+ };
+
+ /*
+ * List of motion sensors that creates motion_sensors array.
+ * The nodelabel "lid_accel" and "base_accel" are used to indicate
+ * motion sensor IDs for lid angle calculation.
+ */
+ motionsense-sensor {
+ lid_accel: lid-accel {
+ compatible = "cros-ec,lis2dw12";
+ status = "okay";
+
+ active-mask = "SENSOR_ACTIVE_S0_S3";
+ location = "MOTIONSENSE_LOC_LID";
+ mutex = <&mutex_lis2dw12>;
+ port = <&i2c_ec_i2c_sensor>;
+ rot-standard-ref = <&lid_rot_ref>;
+ default-range = <2>;
+ drv-data = <&lis2dw12_data>;
+ i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS";
+ configs {
+ compatible =
+ "cros-ec,motionsense-sensor-config";
+ ec-s0 {
+ odr = <(10000 | ROUND_UP_FLAG)>;
+ };
+ ec-s3 {
+ odr = <(10000 | ROUND_UP_FLAG)>;
+ };
+ };
+ };
+
+ base_accel: base-accel {
+ compatible = "cros-ec,lsm6dso-accel";
+ status = "okay";
+
+ active-mask = "SENSOR_ACTIVE_S0_S3";
+ location = "MOTIONSENSE_LOC_BASE";
+ mutex = <&mutex_lsm6dso>;
+ port = <&i2c_ec_i2c_sensor>;
+ rot-standard-ref = <&base_rot_ref>;
+ default-range = <4>;
+ drv-data = <&lsm6dso_accel_data>;
+ i2c-spi-addr-flags = "LSM6DSO_ADDR0_FLAGS";
+ configs {
+ compatible =
+ "cros-ec,motionsense-sensor-config";
+ ec-s0 {
+ odr = <(10000 | ROUND_UP_FLAG)>;
+ ec-rate = <(100 * USEC_PER_MSEC)>;
+ };
+ ec-s3 {
+ odr = <(10000 | ROUND_UP_FLAG)>;
+ ec-rate = <(100 * USEC_PER_MSEC)>;
+ };
+ };
+ };
+
+ base-gyro {
+ compatible = "cros-ec,lsm6dso-gyro";
+ status = "okay";
+
+ active-mask = "SENSOR_ACTIVE_S0_S3";
+ location = "MOTIONSENSE_LOC_BASE";
+ mutex = <&mutex_lsm6dso>;
+ port = <&i2c_ec_i2c_sensor>;
+ rot-standard-ref = <&base_rot_ref>;
+ default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */
+ drv-data = <&lsm6dso_gyro_data>;
+ i2c-spi-addr-flags = "LSM6DSO_ADDR0_FLAGS";
+ };
+
+ als_clear: base-als-clear {
+ compatible = "cros-ec,tcs3400-clear";
+ status = "okay";
+
+ active-mask = "SENSOR_ACTIVE_S0_S3";
+ location = "MOTIONSENSE_LOC_CAMERA";
+ port = <&i2c_ec_i2c_sensor>;
+ default-range = <0x10000>;
+ drv-data = <&tcs_clear_data>;
+ i2c-spi-addr-flags = "TCS3400_I2C_ADDR_FLAGS";
+ configs {
+ compatible =
+ "cros-ec,motionsense-sensor-config";
+ ec-s0 {
+ /* Run ALS sensor in S0 */
+ odr = <1000>;
+ };
+ };
+ };
+
+ base-als-rgb {
+ compatible = "cros-ec,tcs3400-rgb";
+ status = "okay";
+
+ active-mask = "SENSOR_ACTIVE_S0_S3";
+ location = "MOTIONSENSE_LOC_CAMERA";
+ default-range = <0x10000>; /* scale = 1x, uscale = 0 */
+ drv-data = <&tcs_rgb_data>;
+ };
+ };
+
+ motionsense-sensor-info {
+ compatible = "cros-ec,motionsense-sensor-info";
+
+ /* list of entries for motion_als_sensors */
+ als-sensors = <&als_clear>;
+ /*
+ * list of GPIO interrupts that have to
+ * be enabled at initial stage
+ */
+ sensor-irqs = <&int_imu &int_als_rgb &int_accel>;
+ /* list of sensors in force mode */
+ accel-force-mode-sensors = <&lid_accel &als_clear>;
+ };
+};
diff --git a/zephyr/projects/rex/power_signals.dts b/zephyr/projects/rex/power_signals.dts
new file mode 100644
index 0000000000..860c316795
--- /dev/null
+++ b/zephyr/projects/rex/power_signals.dts
@@ -0,0 +1,152 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+ chosen {
+ intel-ap-pwrseq,espi = &espi0;
+ };
+
+ common-pwrseq {
+ compatible = "intel,ap-pwrseq";
+
+ sys-pwrok-delay = <3>;
+ all-sys-pwrgd-timeout = <20>;
+ };
+
+ pwr-en-pp3300-s5 {
+ compatible = "intel,ap-pwrseq-gpio";
+ dbg-label = "PP1800_S5/PP3300_S5 enable output to LS";
+ enum-name = "PWR_EN_PP3300_A";
+ gpios = <&gpiob 6 GPIO_ACTIVE_HIGH>;
+ output;
+ };
+ pwr-pg-ec-rsmrst-od {
+ compatible = "intel,ap-pwrseq-gpio";
+ dbg-label = "RSMRST power good from regulator";
+ enum-name = "PWR_RSMRST";
+ gpios = <&gpioe 2 GPIO_ACTIVE_HIGH>;
+ interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+ };
+ pwr-ec-pch-rsmrst-odl {
+ compatible = "intel,ap-pwrseq-gpio";
+ dbg-label = "RSMRST output to PCH";
+ enum-name = "PWR_EC_PCH_RSMRST";
+ gpios = <&gpioa 6 GPIO_ACTIVE_HIGH>;
+ output;
+ };
+ pwr-pch-pwrok {
+ compatible = "intel,ap-pwrseq-gpio";
+ dbg-label = "PCH_PWROK output to PCH";
+ enum-name = "PWR_PCH_PWROK";
+ gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>;
+ output;
+ };
+ pwr-ec-pch-sys-pwrok {
+ compatible = "intel,ap-pwrseq-gpio";
+ dbg-label = "SYS_PWROK output to PCH";
+ enum-name = "PWR_EC_PCH_SYS_PWROK";
+ gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>;
+ output;
+ };
+ pwr-sys-rst-l {
+ compatible = "intel,ap-pwrseq-gpio";
+ dbg-label = "SYS_RESET# output to PCH";
+ enum-name = "PWR_SYS_RST";
+ gpios = <&gpioc 5 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+ output;
+ };
+ pwr-slp-s0-l {
+ compatible = "intel,ap-pwrseq-gpio";
+ dbg-label = "SLP_S0_L input from PCH";
+ enum-name = "PWR_SLP_S0";
+ gpios = <&gpiod 5 GPIO_ACTIVE_LOW>;
+ interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+ };
+ pwr-slp-s3-l {
+ compatible = "intel,ap-pwrseq-vw";
+ dbg-label = "SLP_S3_L input from PCH";
+ enum-name = "PWR_SLP_S3";
+ virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
+ vw-invert;
+/*
+ * TODO: Initially, use virtual wire for sleep S3 signal instead of
+ * of the GPIO signal which also exists.
+ * compatible = "intel,ap-pwrseq-gpio";
+ * gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
+ * interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+ */
+ };
+ pwr-slp-s4 {
+ compatible = "intel,ap-pwrseq-vw";
+ dbg-label = "SLP_S4 virtual wire input from PCH";
+ enum-name = "PWR_SLP_S4";
+ virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
+ vw-invert;
+ };
+ pwr-slp-s5 {
+ compatible = "intel,ap-pwrseq-vw";
+ dbg-label = "SLP_S5 virtual wire input from PCH";
+ enum-name = "PWR_SLP_S5";
+ virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
+ vw-invert;
+ };
+ pwr-all-sys-pwrgd {
+ compatible = "intel,ap-pwrseq-gpio";
+ dbg-label = "all power good";
+ enum-name = "PWR_ALL_SYS_PWRGD";
+ gpios = <&gpiof 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>;
+ interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+ };
+};
+
+/*
+ * Because the power signals directly reference the GPIOs,
+ * the corresponding named-gpios need to have no-auto-init set.
+ */
+ /* pwr-en-pp3300-s5 */
+&gpio_en_s5_rails {
+ no-auto-init;
+};
+
+/* pwr-pg-ec-rsmrst-od */
+&gpio_seq_ec_rsmrst_odl{
+ no-auto-init;
+};
+
+/* pwr-ec-pch-rsmrst-odl */
+&gpio_ec_soc_rsmrst_l{
+ no-auto-init;
+};
+
+/* pwr-pch-pwrok */
+&gpio_soc_pwrok{
+ no-auto-init;
+};
+
+/* pwr-ec-pch-sys-pwrok */
+&gpio_sys_pwrok{
+ no-auto-init;
+};
+
+/* pwr-sys-rst-l */
+&gpio_sys_rst_odl{
+ no-auto-init;
+};
+
+/* pwr-slp-s0-l */
+&gpio_sys_slp_s0ix_3v3_l{
+ no-auto-init;
+};
+
+/* pwr-slp-s3-l */
+&gpio_slp_s3_ls_l{
+ no-auto-init;
+};
+
+/* pwr-all-sys-pwrgd */
+&gpio_seq_ec_all_sys_pg{
+ no-auto-init;
+};
+
diff --git a/zephyr/projects/rex/prj.conf b/zephyr/projects/rex/prj.conf
new file mode 100644
index 0000000000..96f407b903
--- /dev/null
+++ b/zephyr/projects/rex/prj.conf
@@ -0,0 +1,172 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC=y
+CONFIG_CROS_EC=y
+CONFIG_SHIMMED_TASKS=y
+CONFIG_SYSCON=y
+# Enable during development
+CONFIG_LTO=n
+CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y
+
+# Shell Commands
+CONFIG_SHELL_HELP=y
+CONFIG_SHELL_HISTORY=y
+CONFIG_SHELL_TAB=y
+CONFIG_SHELL_TAB_AUTOCOMPLETION=y
+CONFIG_KERNEL_SHELL=y
+
+# Logging
+CONFIG_LOG=y
+CONFIG_LOG_MODE_MINIMAL=y
+
+# Disable default features we don't want in a minimal example.
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=y
+CONFIG_PLATFORM_EC_SWITCH=y
+CONFIG_PLATFORM_EC_VBOOT_EFS2=n
+
+# Application processor; communicates with EC via eSPI
+CONFIG_AP=y
+CONFIG_ESPI=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5=y
+CONFIG_PLATFORM_EC_HOSTCMD=y
+# Disabling this until temp sensor support is in
+CONFIG_PLATFORM_EC_THROTTLE_AP=n
+CONFIG_PLATFORM_EC_PORT80=y
+
+# Power Sequecing
+CONFIG_AP_X86_INTEL_MTL=y
+CONFIG_X86_NON_DSX_PWRSEQ_MTL=y
+CONFIG_X86_NON_DSX_PWRSEQ_HOST_CMD=y
+# TODO (b/240434243): This may be needed, but using eSPI VW for now
+CONFIG_PLATFORM_EC_POWERSEQ_SLP_S3_L_OVERRIDE=n
+CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n
+
+# Zephyr Inbuilt AP Power Sequencing Config
+CONFIG_AP_PWRSEQ=y
+CONFIG_X86_NON_DSX_PWRSEQ_CONSOLE=y
+CONFIG_AP_PWRSEQ_S0IX=y
+
+# ADC
+CONFIG_ADC=y
+
+# I2C
+CONFIG_I2C=y
+
+# PWM
+CONFIG_PWM=y
+
+# Fan
+CONFIG_TACH_NPCX=y
+
+# Temperature sensors
+CONFIG_SENSOR=y
+CONFIG_PLATFORM_EC_TEMP_SENSOR=y
+CONFIG_PLATFORM_EC_THERMISTOR=y
+CONFIG_PLATFORM_EC_TEMP_SENSOR_POWER=y
+
+# CBI EEPROM support
+CONFIG_EEPROM=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_SHELL=n
+CONFIG_PLATFORM_EC_CBI_EEPROM=y
+CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y
+CONFIG_PLATFORM_EC_BYPASS_CBI_EEPROM_WP_CHECK=y
+
+# LED
+CONFIG_PLATFORM_EC_LED_DT=y
+
+# Battery
+CONFIG_PLATFORM_EC_BATTERY=y
+CONFIG_PLATFORM_EC_BATTERY_SMART=y
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
+CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y
+CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y
+
+# Charger
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
+CONFIG_PLATFORM_EC_CHARGER_INPUT_CURRENT=512
+CONFIG_PLATFORM_EC_CHARGER_ISL9241=y
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=5
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=10
+CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=30000
+CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT=15000
+
+# USB-A
+CONFIG_PLATFORM_EC_USBA=y
+
+# USBC
+CONFIG_PLATFORM_EC_USBC_PPC=y
+CONFIG_PLATFORM_EC_USBC_PPC_SYV682X=y
+CONFIG_PLATFORM_EC_USBC_PPC_SYV682C=y
+CONFIG_PLATFORM_EC_USBC_PPC_SYV682X_SMART_DISCHARGE=y
+
+CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_FRS=y
+CONFIG_PLATFORM_EC_USB_PD_FRS_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_TCPCI=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_NCT38XX=y
+CONFIG_PLATFORM_EC_USB_PD_TRY_SRC=y
+CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE=y
+CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_HB=y
+CONFIG_PLATFORM_EC_USBC_VCONN=y
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER=y
+CONFIG_PLATFORM_EC_USB_PID=0x504D
+
+# IOEX
+CONFIG_GPIO_NCT38XX=y
+
+# BC 1.2
+CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y
+
+#USB Mux
+CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y
+CONFIG_PLATFORM_EC_USB_MUX_TASK=y
+
+# External power
+CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
+
+# Standard shimmed features
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+
+# Keyboard support
+CONFIG_PLATFORM_EC_KEYBOARD=y
+CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_8042=y
+# Column 2 is driven through the GSC, which inverts the signal going through it
+CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y
+
+# MKBP event
+CONFIG_PLATFORM_EC_MKBP_EVENT=y
+CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y
+CONFIG_PLATFORM_EC_MKBP_USE_GPIO_AND_HOST_EVENT=y
+
+# Sensors console command
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y
+
+# Sensors
+CONFIG_SENSOR=y
+CONFIG_SENSOR_SHELL=n
+CONFIG_PLATFORM_EC_MOTIONSENSE=y
+CONFIG_PLATFORM_EC_ACCEL_FIFO=y
+CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y
+CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
+CONFIG_PLATFORM_EC_LID_ANGLE=y
+CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
+CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y
+CONFIG_PLATFORM_EC_TABLET_MODE=y
+CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y
+
+# Sensor Drivers
+CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y
+CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y
+CONFIG_PLATFORM_EC_ALS_TCS3400=y
diff --git a/zephyr/projects/rex/prj_rex.conf b/zephyr/projects/rex/prj_rex.conf
new file mode 100644
index 0000000000..0f204b9669
--- /dev/null
+++ b/zephyr/projects/rex/prj_rex.conf
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Rex reference-board-specific Kconfig settings.
+CONFIG_BOARD_REX=y
+
+# Keyboard
+CONFIG_CROS_KB_RAW_NPCX=y
diff --git a/zephyr/projects/rex/rex.dts b/zephyr/projects/rex/rex.dts
new file mode 100644
index 0000000000..259cd6ff4c
--- /dev/null
+++ b/zephyr/projects/rex/rex.dts
@@ -0,0 +1,239 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+ #include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+ aliases {
+ gpio-wp = &ec_wp_l;
+ gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+ };
+
+ named-gpios {
+ compatible = "named-gpios";
+
+ ec_wp_l: write-protect {
+ gpios = <&gpioa 0 GPIO_INPUT>;
+ };
+ gpio_ec_entering_rw: ec_entering_rw {
+ enum-name = "GPIO_ENTERING_RW";
+ };
+
+ ioex_usb_c0_sbu_fault_odl: usb_c0_sbu_fault_odl {
+ gpios = <&ioex_c0_port1 2 GPIO_INPUT>;
+ };
+ ioex_usb_c0_rt_rst_ls_l: usb_c0_rt_rst_ls_l {
+ gpios = <&ioex_c0_port0 7 GPIO_OUTPUT>;
+ };
+
+ ioex_usb_c0_frs_en: usb_c0_frs_en {
+ gpios = <&ioex_c0_port0 6 GPIO_OUTPUT_LOW>;
+ };
+
+ /* Need to designate 1.8V for I2C buses on the 1800mV rail */
+ ec-i2c-sensor-scl {
+ gpios = <&gpiob 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+ };
+ ec-i2c-sensor-sda {
+ gpios = <&gpiob 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+ };
+ ec-i2c-c0-rt-scl {
+ gpios = <&gpiod 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+ };
+ ec-i2c-c0-rt-sda {
+ gpios = <&gpiod 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+ };
+ };
+
+ usba-port-enable-list {
+ compatible = "cros-ec,usba-port-enable-pins";
+ enable-pins = <&gpio_en_pp5000_usba_r>;
+ };
+};
+
+/* host interface */
+&espi0 {
+ status = "okay";
+ pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
+ pinctrl-names = "default";
+};
+
+/* Power switch logic input pads */
+&psl_in1_gpd2 {
+ /* LID_OPEN */
+ psl-in-mode = "edge";
+ psl-in-pol = "high-rising";
+};
+
+&psl_in2_gp00 {
+ /* ACOK_OD */
+ psl-in-mode = "edge";
+ psl-in-pol = "high-rising";
+};
+
+&psl_in4_gp02 {
+ /* MECH_PWR_BTN_ODL */
+ psl-in-mode = "edge";
+ psl-in-pol = "low-falling";
+};
+
+/* Power domain device controlled by PSL (Power Switch Logic) IO pads */
+&power_ctrl_psl {
+ status = "okay";
+ pinctrl-names = "sleep";
+ pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01 &psl_in4_gp02>;
+};
+
+/* ADC and GPIO alt-function specifications */
+&adc0 {
+ pinctrl-0 = <&adc0_chan0_gp45
+ &adc0_chan1_gp44
+ &adc0_chan8_gpf1
+ &adc0_chan7_gpe1>;
+ pinctrl-names = "default";
+};
+
+&i2c0_0 {
+ label = "I2C_SENSOR";
+ clock-frequency = <I2C_BITRATE_FAST>;
+
+ pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
+ pinctrl-names = "default";
+};
+
+&i2c1_0 {
+ label = "I2C_USB_C0_TCPC";
+ clock-frequency = <I2C_BITRATE_FAST>;
+
+ pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
+ pinctrl-names = "default";
+
+ tcpc_port0: nct38xx@70 {
+ compatible = "nuvoton,nct38xx";
+ gpio-dev = <&nct3807_C0>;
+ reg = <0x70>;
+ tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>;
+ };
+
+ nct3807_C0:nct3807_C0@70 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nuvoton,nct38xx-gpio";
+ reg = <0x70>;
+ label = "NCT3807_C0";
+
+ ioex_c0_port0:gpio@0 {
+ compatible = "nuvoton,nct38xx-gpio-port";
+ reg = <0x0>;
+ label = "NCT3807_C0_GPIO0";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <8>;
+ pin_mask = <0xff>;
+ pinmux_mask = <0xf7>;
+ };
+ ioex_c0_port1:gpio@1 {
+ compatible = "nuvoton,nct38xx-gpio-port";
+ reg = <0x1>;
+ label = "NCT3807_C0_GPIO1";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <8>;
+ pin_mask = <0xff>;
+ };
+ };
+
+ nct3808_alert_0 {
+ compatible = "nuvoton,nct38xx-gpio-alert";
+ irq-gpios = <&gpioe 0 GPIO_ACTIVE_LOW>;
+ nct38xx-dev = <&nct3807_C0>;
+ label = "NCT3807_ALERT_0";
+ };
+};
+
+&i2c2_0 {
+ label = "I2C_PPC0";
+ clock-frequency = <I2C_BITRATE_FAST>;
+
+ pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>;
+ pinctrl-names = "default";
+
+ bc12_port0: pi3usb9201@5f {
+ compatible = "pericom,pi3usb9201";
+ status = "okay";
+ reg = <0x5f>;
+ irq = <&int_usb_c0_bc12>;
+ };
+
+ ppc_port0_syv: ppc_syv@40 {
+ compatible = "silergy,syv682x";
+ status = "okay";
+ reg = <0x40>;
+ frs_en_gpio = <&ioex_usb_c0_frs_en>;
+ };
+};
+
+&i2c3_0 {
+ label = "I2C_USB_C0_RT";
+ clock-frequency = <I2C_BITRATE_FAST>;
+
+ pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
+ pinctrl-names = "default";
+
+ usb_c0_hb_retimer: jhl8040r-c0@56 {
+ compatible = "intel,jhl8040r";
+ reg = <0x56>;
+ ls-en-pin = <&gpio_usb_c0_rt_3p3_sx_en>;
+ int-pin = <&gpio_usb_c0_rt_int_odl>;
+ reset-pin = <&ioex_usb_c0_rt_rst_ls_l>;
+ };
+};
+
+&i2c4_1 {
+ label = "I2_USB_C1_TCPC";
+ clock-frequency = <I2C_BITRATE_FAST>;
+
+ pinctrl-0 = <&i2c4_1_sda_scl_gpf2_f3>;
+ pinctrl-names = "default";
+};
+
+&i2c5_0 {
+ label = "I2C__BATTERY";
+ clock-frequency = <I2C_BITRATE_STANDARD>;
+
+ pinctrl-0 = <&i2c5_0_sda_scl_gp33_36>;
+ pinctrl-names = "default";
+};
+
+&i2c6_1 {
+ label = "I2C_USB_1_MIX";
+ clock-frequency = <I2C_BITRATE_FAST>;
+
+ pinctrl-0 = <&i2c6_1_sda_scl_gpe3_e4>;
+ pinctrl-names = "default";
+};
+
+&i2c7_0 {
+ label = "I2C_CHARGER";
+ clock-frequency = <I2C_BITRATE_FAST>;
+
+ pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>;
+ pinctrl-names = "default";
+
+ cbi_eeprom: eeprom@50 {
+ compatible = "atmel,at24";
+ reg = <0x50>;
+ size = <2048>;
+ pagesize = <16>;
+ address-width = <8>;
+ timeout = <5>;
+ };
+
+ charger: isl9241@9 {
+ compatible = "intersil,isl9241";
+ status = "okay";
+ reg = <0x09>;
+ };
+};
diff --git a/zephyr/projects/rex/rex0_gpio.csv b/zephyr/projects/rex/rex0_gpio.csv
new file mode 100644
index 0000000000..5c20f6fb00
--- /dev/null
+++ b/zephyr/projects/rex/rex0_gpio.csv
@@ -0,0 +1,122 @@
+Signal Name,Pin Number,Type,Enum
+USB_C1_BC12_INT_ODL,G10,INPUT,GPIO_USB_C1_BC12_INT_ODL
+ESPI_SOC_CS0_L,L2,OTHER,
+ESPI_SOC_RESET_L,K3,OTHER,
+ESPI_SOC_CLK,M1,OTHER,
+EC_IMU_INT_R_L,M2,INPUT_PU,
+ESPI_SOC_IO0,H1,OTHER,
+ESPI_SOC_IO1,J1,OTHER,
+ESPI_SOC_IO2,K1,OTHER,
+ESPI_SOC_IO3,L1,OTHER,
+ESPI_SOC_ALERT_L_R,L3,OTHER,
+EC_VOLDN_BTN_ODL,E11,INPUT_PU,GPIO_VOLUME_DOWN_L
+TABLET_MODE_L,M12,INPUT_PU,GPIO_TABLET_MODE_L
+SOCHOT_ODL,G12,INPUT,
+EC_VOLUP_BTN_ODL,L10,INPUT_PU,GPIO_VOLUME_UP_L
+USB_C0_RT_INT_ODL,G11,INPUT,
+EC_WP_L,L12,INPUT,
+EC_BATT_PRES_ODL,K12,INPUT,GPIO_BATT_PRES_ODL
+CPU_C10_GATE_L,J11,INPUT,
+SOC_PWROK,K11,OUTPUT,
+EC_SOC_RSMRST_L,F11,OUTPUT,
+SYS_PWROK,L11,OUTPUT,
+EC_SPARE_GPIO94,M11,OUTPUT,
+EC_SPARE_GPIOA2,F12,OUTPUT,
+EC_SPARE_GPIOA4,H11,OUTPUT,
+EC_ACCEL_INT_R_L,M7,INPUT,
+SLP_S3_LS_L,C2,INPUT,
+IMVP92_VRRDY_OD,E2,INPUT,
+EC_PROCHOT_IN_L,D2,INPUT,
+EC_SPARE_GPIO42,D3,OUTPUT,
+TEMP_SENSOR_2,E3,ADC,ADC_TEMP_SENSOR_2
+TEMP_SENSOR_1,F2,ADC,ADC_TEMP_SENSOR_1
+TEMP_SENSOR_4,F3,ADC,ADC_TEMP_SENSOR_4
+TEMP_SENSOR_3,G3,ADC,ADC_TEMP_SENSOR_3
+SYS_RST_ODL,H7,INPUT,
+EC_SOC_WAKE_R_ODL,H8,OUTPUT_ODL,
+EC_PROCHOT_ODL,J2,OUTPUT_ODR,
+EC_SOC_INT_ODL,J4,OUTPUT_ODL,GPIO_EC_INT_L
+EC_SOC_RTCRST,J5,OUTPUT_ODR,
+EC_SOC_PWR_BTN_ODL,H9,OUTPUT_ODL,GPIO_PCH_PWRBTN_L
+USB_C0_RT_3P3_SX_EN,D9,OUTPUT_ODR,
+KSO_13,D11,OTHER,
+KSO_12,C11,OTHER,
+KSO_11,B10,OTHER,
+KSO_10,B11,OTHER,
+KSO_09,C10,OTHER,
+KSO_08,C9,OTHER,
+KSO_05,C6,OTHER,
+KSO_04,C7,OTHER,
+KSO_03,B8,OTHER,
+EC_KSO_02_INV,B7,OUTPUT_L,
+KSO_01,B6,OTHER,
+KSO_00,B5,OTHER,
+KSI_07,C5,OTHER,
+KSI_06,C4,OTHER,
+KSI_05,C3,OTHER,
+KSI_04,B4,OTHER,
+EC_KSI_03,B3,OTHER,
+EC_KSI_02,A4,OTHER,
+KSI_01,A3,OTHER,
+EC_KSI_00,A2,OTHER,
+EC_I2C_BAT_SCL,D5,I2C_CLOCK,I2C_PORT_BATTERY
+USB_C1_TCPC_INT_ODL,B2,INPUT,GPIO_USB_C1_TCPC_INT_ODL
+EC_I2C_BAT_SDA,D4,I2C_DATA,
+USB_C1_RST_ODL,C1,OUTPUT_ODL,
+EC_FAN_TACH,E5,TACH,
+LED_4_L,G6,OUTPUT,
+EN_PP5000_FAN,K4,OUTPUT_ODR,
+USB_C0_PPC_INT_ODL,H2,INPUT,GPIO_USB_C0_PPC_INT_ODL
+UART_GSC_DBG_TX_EC_RX_R,G4,OTHER,
+EC_SPARE_GPIO66,G2,OUTPUT,
+USB_C0_TCPC_RST_ODL,J3,OUTPUT_ODL,
+USB_C1_RT_INT_ODL,M4,INPUT_PU,
+EC_CBI_WP,G5,OUTPUT,
+USB_C1_RT_RST_R_ODL,H5,OUTPUT_ODL,
+EC_GSC_PACKET_MODE,J6,OUTPUT_ODR,GPIO_PACKET_MODE_EN
+EC_KB_BL_PWM,K5,PWM,GPIO_EN_KEYBOARD_BACKLIGHT
+KSO_14,D6,OTHER,
+USB_C1_FRS_EN,D7,OUTPUT_ODR,
+EC_I2C_USB_C0_TCPC_SDA,K7,I2C_DATA,
+EC_I2C_USB_C0_TCPC_SCL,K8,I2C_CLOCK,I2C_PORT_USB_C0_TCPC
+EC_I2C_USB_C0_PPC_BC_SDA,K9,I2C_DATA,
+EC_I2C_USB_C0_PPC_BC_SCL,L8,I2C_CLOCK,I2C_PORT_PPC0
+EC_IMVP92_EN_SMB,D8,OUTPUT,
+EC_I2C_MISC_SDA,K10,I2C_DATA,
+EC_I2C_MISC_SCL,J10,I2C_CLOCK,I2C_PORT_EEPROM
+EC_I2C_SENSOR_SDA,B12,I2C_DATA,
+EC_I2C_SENSOR_SCL,C12,I2C_CLOCK,I2C_PORT_SENSOR
+EN_S5_RAILS,L9,OUTPUT_ODR,
+FAN_PWM,J7,PWM,
+LED_3_L,H10,OUTPUT,
+LED_2_L,G9,OUTPUT,
+LED_1_L,G8,OUTPUT,
+USB_C0_BC12_INT_ODL,D10,INPUT,GPIO_USB_C0_BC12_INT_ODL
+EC_SPARE_GPIOC7,F10,OUTPUT,
+EC_I2C_USB_C0_RT_SDA,F9,I2C_DATA,
+EC_I2C_USB_C0_RT_SCL,F8,I2C_CLOCK,I2C_PORT_USB_C0_RT
+EC_EDP_BL_EN,E10,OUTPUT_ODR,GPIO_ENABLE_BACKLIGHT
+EC_ALS_RGB_INT_R_L,A9,INPUT_PU,
+SYS_SLP_S0IX_3V3_L,A10,INPUT,
+USB_C0_TCPC_INT_ODL,F4,INPUT,GPIO_USB_C0_TCPC_INT_ODL
+SEQ_EC_RSMRST_ODL,A11,INPUT,
+EC_I2C_USB_C1_MIX_SDA,L7,I2C_DATA,
+EC_I2C_USB_C1_MIX_SCL,L6,I2C_CLOCK,I2C_PORT_USB_1_MIX
+CCD_MODE_ODL,A12,OUTPUT_ODL,GPIO_CCD_MODE_ODL
+EC_I2C_USB_C1_TCPC_SDA,F6,I2C_DATA,
+EC_I2C_USB_C1_TCPC_SCL,F5,I2C_CLOCK,I2C_PORT_USB_C1_TCPC
+SEQ_EC_ALL_SYS_PG,E9,INPUT,
+USB_C1_PPC_INT_ODL,E8,INPUT,GPIO_USB_C1_PPC_INT_ODL
+EC_KSO_07_JEN_L,B9,OTHER,
+EC_KSO_06_GP_SEL_L,C8,OTHER,
+EC_SPARE_GPO32,E4,OUTPUT,
+EC_SPARE_GPO35,K2,OUTPUT,
+UART_GSC_DBG_RX_EC_TX_R,H4,OTHER,
+EC_RST_R_ODL,K6,INPUT,
+EC_KB_BL_EN_L,J9,OUTPUT,
+ACOK_OD,E7,INPUT,GPIO_AC_PRESENT
+GSC_EC_PWR_BTN_ODL,E6,INPUT_PU,GPIO_POWER_BUTTON_L
+MECH_PWR_BTN_ODL,F7,INPUT,
+LID_OPEN,G7,INPUT_PU,GPIO_LID_OPEN
+EN_Z1_RAILS,J8,OUTPUT,
+EN_PP5000_USBA_R,H6,OUTPUT,
diff --git a/zephyr/projects/rex/src/board_power.c b/zephyr/projects/rex/src/board_power.c
new file mode 100644
index 0000000000..c7f12d024e
--- /dev/null
+++ b/zephyr/projects/rex/src/board_power.c
@@ -0,0 +1,61 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/logging/log.h>
+#include <zephyr/drivers/gpio.h>
+
+#include <ap_power/ap_power.h>
+#include <ap_power/ap_power_events.h>
+#include <ap_power/ap_power_interface.h>
+#include <ap_power_override_functions.h>
+#include <power_signals.h>
+#include <x86_power_signals.h>
+
+#include "gpio_signal.h"
+#include "gpio/gpio.h"
+
+LOG_MODULE_DECLARE(ap_pwrseq, LOG_LEVEL_INF);
+
+#if CONFIG_X86_NON_DSX_PWRSEQ_MTL
+#define X86_NON_DSX_MTL_FORCE_SHUTDOWN_TO_MS 50
+
+void board_ap_power_force_shutdown(void)
+{
+ int timeout_ms = X86_NON_DSX_MTL_FORCE_SHUTDOWN_TO_MS;
+
+ /* Turn off PCH_RMSRST to meet tPCH12 */
+ power_signal_set(PWR_EC_PCH_RSMRST, 0);
+
+ /* Turn off PRIM load switch. */
+ power_signal_set(PWR_EN_PP3300_A, 0);
+
+ /* Wait RSMRST to be off. */
+ while (power_signal_get(PWR_RSMRST) && (timeout_ms > 0)) {
+ k_msleep(1);
+ timeout_ms--;
+ };
+
+ if (power_signal_get(PWR_RSMRST)) {
+ LOG_WRN("RSMRST_ODL didn't go low! Assuming G3.");
+ }
+}
+
+void board_ap_power_action_g3_s5(void)
+{
+ /* Turn on the PP3300_PRIM rail. */
+ power_signal_set(PWR_EN_PP3300_A, 1);
+
+ if (!power_wait_signals_timeout(
+ IN_PGOOD_ALL_CORE,
+ AP_PWRSEQ_DT_VALUE(wait_signal_timeout))) {
+ ap_power_ev_send_callbacks(AP_POWER_PRE_INIT);
+ }
+}
+
+bool board_ap_power_check_power_rails_enabled(void)
+{
+ return power_signal_get(PWR_EN_PP3300_A);
+}
+#endif /* CONFIG_X86_NON_DSX_PWRSEQ_MTL */
diff --git a/zephyr/projects/rex/src/usb_pd_policy.c b/zephyr/projects/rex/src/usb_pd_policy.c
new file mode 100644
index 0000000000..7e9876f9c1
--- /dev/null
+++ b/zephyr/projects/rex/src/usb_pd_policy.c
@@ -0,0 +1,77 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Shared USB-C policy for Rex boards */
+
+#include <zephyr/drivers/gpio.h>
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+int pd_check_vconn_swap(int port)
+{
+ /* Allow VCONN swaps if the AP is on. */
+ return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+ /* Disable VBUS. */
+ ppc_vbus_source_enable(port, 0);
+
+ /* Enable discharge if we were previously sourcing 5V */
+ if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE))
+ pd_set_vbus_discharge(port, 1);
+
+ /* Notify host of power info change. */
+ pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+ int rv;
+
+ /* Disable charging. */
+ rv = ppc_vbus_sink_enable(port, 0);
+ if (rv)
+ return rv;
+
+ if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE)) {
+ pd_set_vbus_discharge(port, 0);
+ }
+
+ /* Provide Vbus. */
+ rv = ppc_vbus_source_enable(port, 1);
+ if (rv) {
+ return rv;
+ }
+
+ /* Notify host of power info change. */
+ pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+ return EC_SUCCESS;
+}
+
+/* Used by Vbus discharge common code with CONFIG_USB_PD_DISCHARGE */
+int board_vbus_source_enabled(int port)
+{
+ return tcpm_get_src_ctrl(port);
+}
+
+/* Used by USB charger task with CONFIG_USB_PD_5V_EN_CUSTOM */
+int board_is_sourcing_vbus(int port)
+{
+ return board_vbus_source_enabled(port);
+}
diff --git a/zephyr/projects/rex/src/usbc_config.c b/zephyr/projects/rex/src/usbc_config.c
new file mode 100644
index 0000000000..3aeaac8977
--- /dev/null
+++ b/zephyr/projects/rex/src/usbc_config.c
@@ -0,0 +1,288 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/drivers/gpio.h>
+
+#include "battery_fuel_gauge.h"
+#include "charger.h"
+#include "charge_manager.h"
+#include "charge_ramp.h"
+#include "charge_state_v2.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "driver/charger/isl9241.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/tcpci.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "ioexpander.h"
+#include "ppc/syv682x_public.h"
+#include "system.h"
+#include "task.h"
+#include "usb_mux.h"
+#include "usbc_ppc.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/*******************************************************************/
+/* USB-C Configuration Start */
+
+/* USB-C ports */
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_COUNT };
+BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+static void usbc_interrupt_init(void)
+{
+ /* Enable PPC interrupts. */
+ gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc));
+
+ /* Enable TCPC interrupts. */
+ gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_tcpc));
+
+ /* Enable BC 1.2 interrupts */
+ gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_bc12));
+
+ /* Enable SBU fault interrupts */
+ gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_sbu_fault));
+}
+DECLARE_HOOK(HOOK_INIT, usbc_interrupt_init, HOOK_PRIO_POST_I2C);
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+ /*
+ * TODO: Meteorlake PCH does not use Physical GPIO for over current
+ * error, hence Send 'Over Current Virtual Wire' eSPI signal.
+ */
+}
+
+void sbu_fault_interrupt(enum gpio_signal signal)
+{
+ int port = USBC_PORT_C0;
+
+ CPRINTSUSB("C%d: SBU fault", port);
+ pd_handle_overcurrent(port);
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+ int port;
+
+ switch (signal) {
+ case GPIO_USB_C0_TCPC_INT_ODL:
+ port = 0;
+ break;
+ default:
+ return;
+ }
+
+ schedule_deferred_pd_interrupt(port);
+}
+
+static void reset_nct38xx_port(int port)
+{
+ const struct gpio_dt_spec *reset_gpio_l;
+ const struct device *ioex_port0, *ioex_port1;
+
+ /* TODO(b/225189538): Save and restore ioex signals */
+ if (port == USBC_PORT_C0) {
+ reset_gpio_l = GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_rst_odl);
+ ioex_port0 = DEVICE_DT_GET(DT_NODELABEL(ioex_c0_port0));
+ ioex_port1 = DEVICE_DT_GET(DT_NODELABEL(ioex_c0_port1));
+ } else {
+ /* Invalid port: do nothing */
+ return;
+ }
+
+ gpio_pin_set_dt(reset_gpio_l, 0);
+ msleep(NCT38XX_RESET_HOLD_DELAY_MS);
+ gpio_pin_set_dt(reset_gpio_l, 1);
+ nct38xx_reset_notify(port);
+ if (NCT3807_RESET_POST_DELAY_MS != 0) {
+ msleep(NCT3807_RESET_POST_DELAY_MS);
+ }
+
+ /* Re-enable the IO expander pins */
+ gpio_reset_port(ioex_port0);
+ gpio_reset_port(ioex_port1);
+}
+
+void board_reset_pd_mcu(void)
+{
+ /* Reset TCPC0 */
+ reset_nct38xx_port(USBC_PORT_C0);
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+ uint16_t status = 0;
+ const struct gpio_dt_spec *tcpc_c0_rst_l;
+ const struct gpio_dt_spec *tcpc_c0_int_l;
+
+ tcpc_c0_rst_l = GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_rst_odl);
+ tcpc_c0_int_l = GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_int_odl);
+
+ /*
+ * Check which port has the ALERT line set and ignore if that TCPC has
+ * its reset line active.
+ */
+ if (!gpio_pin_get_dt(tcpc_c0_int_l) && gpio_pin_get_dt(tcpc_c0_rst_l)) {
+ status |= PD_STATUS_TCPC_ALERT_0;
+ }
+
+ return status;
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+ switch (signal) {
+ case GPIO_USB_C0_PPC_INT_ODL:
+ syv682x_interrupt(USBC_PORT_C0);
+ break;
+
+ default:
+ break;
+ }
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+ switch (signal) {
+ case GPIO_USB_C0_BC12_INT_ODL:
+ usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+ break;
+
+ default:
+ break;
+ }
+}
+
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+ int charge_mv)
+{
+ charge_set_input_current_limit(
+ MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+}
+
+static void board_disable_charger_ports(void)
+{
+ int i;
+
+ CPRINTSUSB("Disabling all charger ports");
+
+ /* Disable all ports. */
+ for (i = 0; i < ppc_cnt; i++) {
+ /*
+ * If this port had booted in dead battery mode, go
+ * ahead and reset it so EN_SNK responds properly.
+ */
+ if (nct38xx_get_boot_type(i) == NCT38XX_BOOT_DEAD_BATTERY) {
+ reset_nct38xx_port(i);
+ pd_set_error_recovery(i);
+ }
+
+ /*
+ * Do not return early if one fails otherwise we can
+ * get into a boot loop assertion failure.
+ */
+ if (ppc_vbus_sink_enable(i, 0)) {
+ CPRINTSUSB("Disabling C%d as sink failed.", i);
+ }
+ }
+}
+
+int board_set_active_charge_port(int port)
+{
+ int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+ int i;
+ int rv;
+
+ if (port == CHARGE_PORT_NONE) {
+ board_disable_charger_ports();
+ return EC_SUCCESS;
+ } else if (!is_valid_port) {
+ return EC_ERROR_INVAL;
+ }
+
+ /*
+ * Check if we can reset any ports in dead battery mode
+ *
+ * The NCT3807 may continue to keep EN_SNK low on the dead battery port
+ * and allow a dangerous level of voltage to pass through to the initial
+ * charge port (see b/183660105). We must reset the ports if we have
+ * sufficient battery to do so, which will bring EN_SNK back under
+ * normal control.
+ */
+ rv = EC_SUCCESS;
+ for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+ if (nct38xx_get_boot_type(i) != NCT38XX_BOOT_DEAD_BATTERY) {
+ continue;
+ }
+
+ /* Handle dead battery boot case */
+ CPRINTSUSB("Found dead battery on %d", i);
+ /*
+ * If we have battery, get this port reset ASAP.
+ * This means temporarily rejecting charge manager
+ * sets to it.
+ */
+ if (pd_is_battery_capable()) {
+ reset_nct38xx_port(i);
+ pd_set_error_recovery(i);
+
+ if (port == i) {
+ rv = EC_ERROR_INVAL;
+ }
+ } else if (port != i) {
+ /*
+ * If other port is selected and in dead battery
+ * mode, reset this port. Otherwise, reject
+ * change because we'll brown out.
+ */
+ if (nct38xx_get_boot_type(port) ==
+ NCT38XX_BOOT_DEAD_BATTERY) {
+ reset_nct38xx_port(i);
+ pd_set_error_recovery(i);
+ } else {
+ rv = EC_ERROR_INVAL;
+ }
+ }
+ }
+
+ if (rv != EC_SUCCESS) {
+ return rv;
+ }
+
+ /* Check if the port is sourcing VBUS. */
+ if (tcpm_get_src_ctrl(port)) {
+ CPRINTSUSB("Skip enable C%d", port);
+ return EC_ERROR_INVAL;
+ }
+
+ CPRINTSUSB("New charge port: C%d", port);
+
+ /*
+ * Turn off the other ports' sink path FETs, before enabling the
+ * requested charge port.
+ */
+ for (i = 0; i < ppc_cnt; i++) {
+ if (i == port) {
+ continue;
+ }
+ if (ppc_vbus_sink_enable(i, 0)) {
+ CPRINTSUSB("C%d: sink path disable failed.", i);
+ }
+ }
+
+ /* Enable requested charge port. */
+ if (ppc_vbus_sink_enable(port, 1)) {
+ CPRINTSUSB("C%d: sink path enable failed.", port);
+ return EC_ERROR_UNKNOWN;
+ }
+
+ return EC_SUCCESS;
+}
diff --git a/zephyr/projects/rex/temp_sensors.dts b/zephyr/projects/rex/temp_sensors.dts
new file mode 100644
index 0000000000..680ebc8954
--- /dev/null
+++ b/zephyr/projects/rex/temp_sensors.dts
@@ -0,0 +1,69 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+
+/ {
+ temp_ddr_soc: ddr_soc {
+ compatible = "cros-ec,temp-sensor-thermistor";
+ thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+ adc = <&adc_ddr_soc>;
+ };
+ temp_ambient: ambient {
+ compatible = "cros-ec,temp-sensor-thermistor";
+ thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+ adc = <&adc_ambient>;
+ };
+ temp_charger: charger {
+ compatible = "cros-ec,temp-sensor-thermistor";
+ thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+ adc = <&adc_charger>;
+ };
+ temp_wwan: wwan {
+ compatible = "cros-ec,temp-sensor-thermistor";
+ thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+ adc = <&adc_wwan>;
+ };
+
+ named-temp-sensors {
+ compatible = "cros-ec,temp-sensors";
+ ddr_soc {
+ temp_fan_off = <35>;
+ temp_fan_max = <60>;
+ temp_host_high = <85>;
+ temp_host_halt = <90>;
+ temp_host_release_high = <80>;
+ sensor = <&temp_ddr_soc>;
+ };
+ ambient {
+ temp_fan_off = <35>;
+ temp_fan_max = <60>;
+ temp_host_high = <85>;
+ temp_host_halt = <90>;
+ temp_host_release_high = <80>;
+ sensor = <&temp_ambient>;
+ };
+ charger {
+ temp_fan_off = <35>;
+ temp_fan_max = <65>;
+ temp_host_high = <105>;
+ temp_host_halt = <120>;
+ temp_host_release_high = <90>;
+ sensor = <&temp_charger>;
+ };
+ wwan {
+ temp_fan_off = <35>;
+ temp_fan_max = <60>;
+ temp_host_high = <130>;
+ temp_host_halt = <130>;
+ temp_host_release_high = <100>;
+ sensor = <&temp_wwan>;
+ };
+ };
+};
+
+&thermistor_3V3_30K9_47K_4050B {
+ status = "okay";
+};
diff --git a/zephyr/projects/rex/usbc.dts b/zephyr/projects/rex/usbc.dts
new file mode 100644
index 0000000000..8b3d0aa316
--- /dev/null
+++ b/zephyr/projects/rex/usbc.dts
@@ -0,0 +1,30 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+ usbc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usbc_port0: port0@0 {
+ compatible = "named-usbc-port";
+ reg = <0>;
+ bc12 = <&i2c_ec_i2c_usb_c0_ppc_b>;
+ ppc = <&ppc_port0_syv>;
+ tcpc = <&tcpc_port0>;
+ chg = <&charger>;
+ usb-mux-chain-0 {
+ compatible = "cros-ec,usb-mux-chain";
+ usb-muxes = <&usb_c0_hb_retimer
+ &virtual_mux_c0>;
+ };
+ };
+ port0-muxes {
+ virtual_mux_c0: virtual-mux-c0 {
+ compatible = "cros-ec,usbc-mux-virtual";
+ };
+ };
+ };
+};
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