diff options
Diffstat (limited to 'zephyr/projects/skyrim')
48 files changed, 2332 insertions, 1809 deletions
diff --git a/zephyr/projects/skyrim/BUILD.py b/zephyr/projects/skyrim/BUILD.py index 3d43b3676b..ff53aeefda 100644 --- a/zephyr/projects/skyrim/BUILD.py +++ b/zephyr/projects/skyrim/BUILD.py @@ -1,11 +1,15 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. """Define zmake projects for skyrim.""" -def register_variant(project_name): +def register_skyrim_project( + project_name, + extra_dts_overlays=(), + extra_kconfig_files=(), +): """Register a variant of skyrim.""" register_npcx_project( project_name=project_name, @@ -13,26 +17,56 @@ def register_variant(project_name): dts_overlays=[ # Common to all projects. here / "adc.dts", - here / "battery.dts", here / "fan.dts", here / "gpio.dts", - here / "i2c.dts", here / "interrupts.dts", here / "keyboard.dts", - here / "led_pins_skyrim.dts", - here / "led_policy_skyrim.dts", here / "motionsense.dts", here / "usbc.dts", # Project-specific DTS customizations. - here / f"{project_name}.dts", - ], - kconfig_files=[ - here / f"prj_{project_name}.conf", + *extra_dts_overlays, ], + kconfig_files=[here / "prj.conf", *extra_kconfig_files], ) -register_variant(project_name="skyrim") +register_skyrim_project( + project_name="morthal", + extra_dts_overlays=[ + here / "morthal.dts", + here / "battery_morthal.dts", + here / "led_pins_morthal.dts", + here / "led_policy_morthal.dts", + ], + extra_kconfig_files=[ + here / "prj_morthal.conf", + ], +) + + +register_skyrim_project( + project_name="skyrim", + extra_dts_overlays=[ + here / "skyrim.dts", + here / "battery_skyrim.dts", + here / "led_pins_skyrim.dts", + here / "led_policy_skyrim.dts", + ], + extra_kconfig_files=[ + here / "prj_skyrim.conf", + ], +) + -# TODO: Deprecate guybrush build after skyrim hardware is readily available. -# register_variant(project_name="guybrush") +register_skyrim_project( + project_name="winterhold", + extra_dts_overlays=[ + here / "winterhold.dts", + here / "battery_winterhold.dts", + here / "led_pins_winterhold.dts", + here / "led_policy_winterhold.dts", + ], + extra_kconfig_files=[ + here / "prj_winterhold.conf", + ], +) diff --git a/zephyr/projects/skyrim/CMakeLists.txt b/zephyr/projects/skyrim/CMakeLists.txt index b364421eb4..5c466e87e8 100644 --- a/zephyr/projects/skyrim/CMakeLists.txt +++ b/zephyr/projects/skyrim/CMakeLists.txt @@ -1,23 +1,46 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. cmake_minimum_required(VERSION 3.13.1) -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(guybrush) +find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}") -cros_ec_library_include_directories_ifdef(CONFIG_BOARD_SKYRIM include) -cros_ec_library_include_directories_ifdef(CONFIG_BOARD_GUYBRUSH include_guybrush) +zephyr_library_sources("src/common.c") +zephyr_library_sources("src/power_signals.c") -zephyr_library_sources_ifdef(CONFIG_BOARD_SKYRIM "power_signals.c") -zephyr_library_sources_ifdef(CONFIG_BOARD_GUYBRUSH "power_signals_guybrush.c") +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC + "src/usb_pd_policy.c" + "src/usbc_config.c") +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON + "src/led.c") +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_AMD_STT + "src/stt.c") -zephyr_library_sources_ifdef(CONFIG_BOARD_SKYRIM "usbc_config.c") -zephyr_library_sources_ifdef(CONFIG_BOARD_GUYBRUSH "usbc_config_guybrush.c") +if(DEFINED CONFIG_BOARD_MORTHAL) + project(morthal) + zephyr_library_sources( + "src/morthal/ppc_config.c" + "src/morthal/usb_mux_config.c" +) +endif() -zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC - "usb_pd_policy.c") +if(DEFINED CONFIG_BOARD_SKYRIM) + project(skyrim) + cros_ec_library_include_directories_ifdef(CONFIG_BOARD_SKYRIM include) + zephyr_library_sources( + "src/skyrim/usb_mux_config.c" + "src/skyrim/ppc_config.c" + "src/skyrim/form_factor.c" + "src/skyrim/alt_charger.c" + ) + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "src/skyrim/fan.c") +endif() -zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON - "led.c") +if(DEFINED CONFIG_BOARD_WINTERHOLD) + project(winterhold) + zephyr_library_sources( + "src/winterhold/usb_mux_config.c" + "src/winterhold/ppc_config.c" + ) +endif() diff --git a/zephyr/projects/skyrim/Kconfig b/zephyr/projects/skyrim/Kconfig index ea68baf71b..d2ef60fa52 100644 --- a/zephyr/projects/skyrim/Kconfig +++ b/zephyr/projects/skyrim/Kconfig @@ -1,12 +1,12 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -config BOARD_GUYBRUSH - bool "Google Guybrush Board" +config BOARD_MORTHAL + bool "Google Morthal Board" help - Build Google Guybrush reference board. This board build is a - prototype rather than a releasing product. + Build Google Morthal reference board. This board uses an AMD SoC + and NPCX9 EC config BOARD_SKYRIM bool "Google Skyrim Board" @@ -14,4 +14,14 @@ config BOARD_SKYRIM Build Google Skyrim reference board. This board uses an AMD SoC and NPCX9 EC +config BOARD_WINTERHOLD + bool "Google Winterhold Board" + help + Build Google Winterhold reference board. This board uses an AMD SoC + and NPCX9 EC + +module = SKYRIM +module-str = Skyrim board-specific code +source "subsys/logging/Kconfig.template.log_config" + source "Kconfig.zephyr" diff --git a/zephyr/projects/skyrim/adc.dts b/zephyr/projects/skyrim/adc.dts index 40fe146a06..0f2ffd6436 100644 --- a/zephyr/projects/skyrim/adc.dts +++ b/zephyr/projects/skyrim/adc.dts @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,63 +10,60 @@ compatible = "named-adc-channels"; adc_temp_charger: temp-charger { - label = "CHARGER"; enum-name = "ADC_TEMP_SENSOR_CHARGER"; io-channels = <&adc0 1>; }; adc_temp_memory: temp-memory { - label = "MEMORY"; enum-name = "ADC_TEMP_SENSOR_MEMORY"; io-channels = <&adc0 2>; }; adc_core_imon1: core-imon1 { - label = "CORE_I"; enum-name = "ADC_CORE_IMON1"; io-channels = <&adc0 3>; }; adc_core_imon2: core-imon2 { - label = "SOC_I"; enum-name = "ADC_SOC_IMON2"; io-channels = <&adc0 4>; }; }; + temp_charger_thermistor: charger-thermistor { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_30K9_47K_4050B>; + adc = <&adc_temp_charger>; + }; + + temp_memory_thermistor: memory-thermistor { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_30K9_47K_4050B>; + adc = <&adc_temp_memory>; + }; + named-temp-sensors { + compatible = "cros-ec,temp-sensors"; charger-thermistor { - compatible = "cros-ec,temp-sensor-thermistor", - "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V3_30K9_47K_4050B>; - label = "Charger"; - enum-name = "TEMP_SENSOR_CHARGER"; temp_host_high = <100>; temp_host_halt = <105>; temp_host_release_high = <80>; - adc = <&adc_temp_charger>; + sensor = <&temp_charger_thermistor>; }; + memory-thermistor { - compatible = "cros-ec,temp-sensor-thermistor", - "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V3_30K9_47K_4050B>; - label = "Memory"; - enum-name = "TEMP_SENSOR_MEMORY"; temp_host_high = <100>; temp_host_halt = <105>; temp_host_release_high = <80>; - adc = <&adc_temp_memory>; power-good-pin = <&gpio_pg_pwr_s5>; + sensor = <&temp_memory_thermistor>; }; - sb-tsi-sensor { - compatible = "cros-ec,temp-sensor-sb-tsi", - "cros-ec,temp-sensor"; - label = "CPU"; - enum-name = "TEMP_SENSOR_CPU"; - port = <&i2c_soc_thermal>; + + cpu { temp_host_high = <100>; temp_host_halt = <105>; temp_host_release_high = <80>; temp_fan_off = <60>; temp_fan_max = <90>; power-good-pin = <&gpio_s0_pgood>; + sensor = <&temp_cpu>; }; }; }; diff --git a/zephyr/projects/skyrim/battery.dts b/zephyr/projects/skyrim/battery_morthal.dts index b9fc0d1090..8c87cef7f9 100644 --- a/zephyr/projects/skyrim/battery.dts +++ b/zephyr/projects/skyrim/battery_morthal.dts @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/zephyr/projects/skyrim/battery_skyrim.dts b/zephyr/projects/skyrim/battery_skyrim.dts new file mode 100644 index 0000000000..8c87cef7f9 --- /dev/null +++ b/zephyr/projects/skyrim/battery_skyrim.dts @@ -0,0 +1,15 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + batteries { + default_battery: aec_5477109 { + compatible = "aec,5477109", "battery-smart"; + }; + smp_l20m3pg1 { + compatible = "smp,l20m3pg1", "battery-smart"; + }; + }; +}; diff --git a/zephyr/projects/skyrim/battery_winterhold.dts b/zephyr/projects/skyrim/battery_winterhold.dts new file mode 100644 index 0000000000..776d74cdff --- /dev/null +++ b/zephyr/projects/skyrim/battery_winterhold.dts @@ -0,0 +1,33 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + batteries { + default_battery: lgc_xphx8 { + compatible = "lgc,xphx8", "battery-smart"; + }; + smp_atlxdy9k { + compatible = "smp,atlxdy9k", "battery-smart"; + }; + smp_cosxdy9k{ + compatible = "smp,cosxdy9k", "battery-smart"; + }; + byd_wv3k8{ + compatible = "byd,wv3k8", "battery-smart"; + }; + cosmx_mvk11{ + compatible = "cosmx,mvk11", "battery-smart"; + }; + sunwoda_atl3rr09{ + compatible = "sunwoda,atl3rr09", "battery-smart"; + }; + sunwoda_cos3rr09{ + compatible = "sunwoda,cos3rr09", "battery-smart"; + }; + atl_cfd72{ + compatible = "atl,cfd72", "battery-smart"; + }; + }; +}; diff --git a/zephyr/projects/skyrim/fan.dts b/zephyr/projects/skyrim/fan.dts index 042b9399dc..f0bc28cb7e 100644 --- a/zephyr/projects/skyrim/fan.dts +++ b/zephyr/projects/skyrim/fan.dts @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,7 +9,6 @@ fan_0 { pwms = <&pwm0 0 PWM_KHZ(25) PWM_POLARITY_NORMAL>; - pwm-frequency = <25000>; rpm_min = <3100>; rpm_start = <3100>; rpm_max = <8000>; diff --git a/zephyr/projects/skyrim/gpio.dts b/zephyr/projects/skyrim/gpio.dts index a06bb070ab..4c935320b2 100644 --- a/zephyr/projects/skyrim/gpio.dts +++ b/zephyr/projects/skyrim/gpio.dts @@ -1,9 +1,15 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ / { + aliases { + gpio-wp = &gpio_wp; + gpio-cbi-wp = &gpio_cbi_wp; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + /* GPIOs shared by all boards */ named-gpios { compatible = "named-gpios"; @@ -22,6 +28,7 @@ gpio_slp_s3_l: slp_s3_l { gpios = <&gpio6 1 GPIO_INPUT>; enum-name = "GPIO_PCH_SLP_S3_L"; + alias = "GPIO_PCH_SLP_S0_L"; }; gpio_slp_s5_l: slp_s5_l { gpios = <&gpio7 2 GPIO_INPUT>; @@ -119,6 +126,81 @@ gpios = <&gpioa 6 GPIO_OUTPUT_HIGH>; enum-name = "GPIO_ENABLE_BACKLIGHT_L"; }; + gpio_usb_fault_odl: usb_fault_odl { + gpios = <&gpio5 0 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; + }; + gpio_en_pwr_s3: en_pwr_s3 { + gpios = <&gpio7 4 GPIO_OUTPUT_LOW>; + }; + gpio_pg_groupc_s0_od: pg_groupc_s0_od { + gpios = <&gpiof 0 GPIO_INPUT>; + }; + gpio_ec_i2c_usbc_pd_int: ec_i2c_usbc_pd_int { + gpios = <&gpioa 3 GPIO_INPUT>; + }; + gpio_soc_thermtrip_odl: soc_thermtrip_odl { + gpios = <&gpio9 5 GPIO_INPUT>; + }; + gpio_hub_rst: hub_rst { + gpios = <&gpio6 6 GPIO_OUTPUT_HIGH>; + }; + ec_soc_int_l { + gpios = <&gpioa 1 GPIO_OUTPUT_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_ec_soc_pwr_good: ec_soc_pwr_good { + gpios = <&gpiod 3 GPIO_OUTPUT_LOW>; + }; + /* TODO: Add interrupt handler to shut down */ + pcore_ocp_r_l { + gpios = <&gpioa 5 GPIO_INPUT>; + }; + gpio_usb_hub_fault_q_odl: usb_hub_fault_q_odl { + gpios = <&gpioe 5 GPIO_INPUT_PULL_UP>; + }; + gpio_pg_lpddr5_s3_od: pg_lpddr5_s3_od { + gpios = <&gpio7 3 GPIO_INPUT>; + }; + 3axis_int_l { + gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>; + }; + gpio_ec_soc_pwr_btn_l: ec_soc_pwr_btn_l { + gpios = <&gpioa 7 GPIO_OUTPUT_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + gpio_volup_btn_odl: volup_btn_odl { + gpios = <&gpio6 7 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + gpio_voldn_btn_odl: voldn_btn_odl { + gpios = <&gpio7 0 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + ec_sc_rst { + gpios = <&gpiob 0 GPIO_OUTPUT_LOW>; + }; + gpio_cbi_wp: ec_cbi_wp { + gpios = <&gpio8 1 GPIO_OUTPUT_LOW>; + }; + gpio_wp: ec_wp_l { + gpios = <&gpiod 7 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_pg_lpddr5_s0_od: pg_lpddr5_s0_od { + gpios = <&gpio6 0 GPIO_INPUT>; + }; + ec_espi_rst_l { + gpios = <&gpio5 4 GPIO_PULL_DOWN>; + }; + gpio_accel_gyro_int_l: accel_gyro_int_l { + gpios = <&gpioa 0 GPIO_INPUT>; + }; + /* unimplemented GPIOs */ + entering-rw { + enum-name = "GPIO_ENTERING_RW"; + }; + pch-sys-prwok { + enum-name = "GPIO_PCH_SYS_PWROK"; + }; ec_i2c_usb_a0_c0_scl { gpios = <&gpiob 5 GPIO_INPUT>; }; @@ -132,10 +214,10 @@ gpios = <&gpio8 7 GPIO_INPUT>; }; ec_i2c_batt_scl { - gpios = <&gpio9 2 GPIO_INPUT>; + gpios = <&gpio9 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; }; ec_i2c_batt_sda { - gpios = <&gpio9 1 GPIO_INPUT>; + gpios = <&gpio9 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; }; ec_i2c_usbc_mux_scl { gpios = <&gpiod 1 GPIO_INPUT>; @@ -156,16 +238,16 @@ gpios = <&gpio3 6 GPIO_INPUT>; }; ec_i2c_sensor_scl { - gpios = <&gpioe 4 GPIO_INPUT>; + gpios = <&gpioe 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; }; ec_i2c_sensor_sda { - gpios = <&gpioe 3 GPIO_INPUT>; + gpios = <&gpioe 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; }; ec_i2c_soc_sic { - gpios = <&gpiob 3 GPIO_INPUT>; + gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; }; ec_i2c_soc_sid { - gpios = <&gpiob 2 GPIO_INPUT>; + gpios = <&gpiob 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; }; en_kb_bl { gpios = <&gpio9 7 GPIO_OUTPUT_HIGH>; @@ -191,27 +273,21 @@ }; usb_c0_ppc_en_l { gpios = <&ioex_c0_port1 0 GPIO_OUTPUT_LOW>; - enum-name = "IOEX_USB_C0_PPC_EN_L"; }; - usb_c0_ppc_ilim_3a_en { + ioex_usb_c0_ilim_3a_en: usb_c0_ppc_ilim_3a_en { gpios = <&ioex_c0_port1 1 GPIO_OUTPUT_LOW>; enum-name = "IOEX_USB_C0_PPC_ILIM_3A_EN"; }; - /* TODO: figure out interrupts */ - usb_c0_sbu_fault_odl { + ioex_usb_c0_sbu_fault_odl: usb_c0_sbu_fault_odl { gpios = <&ioex_c0_port1 2 GPIO_INPUT>; - enum-name = "IOEX_USB_C0_FAULT_ODL"; }; ioex_en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus { gpios = <&ioex_c0_port1 5 GPIO_OUTPUT_LOW>; - enum-name = "IOEX_EN_PP5000_USB_A0_VBUS"; }; - /* TODO: figure out interrupts */ - usb_a0_fault_odl { + ioex_usb_a0_fault_odl: usb_a0_fault_odl { gpios = <&ioex_c0_port1 6 GPIO_INPUT>; - enum-name = "IOEX_USB3_A0_FAULT_L"; }; - usb_c0_sbu_flip { + ioex_usb_c0_sbu_flip: usb_c0_sbu_flip { gpios = <&ioex_c0_port1 7 GPIO_OUTPUT_LOW>; enum-name = "IOEX_USB_C0_SBU_FLIP"; }; @@ -222,7 +298,6 @@ }; usb_a1_retimer_rst { gpios = <&ioex_c1_port0 1 GPIO_OUTPUT_LOW>; - enum-name = "IOEX_USB_A1_RETIMER_RST"; }; usb_c1_in_hpd { gpios = <&ioex_c1_port0 3 GPIO_OUTPUT_LOW>; @@ -234,27 +309,22 @@ }; usb_c1_ppc_en_l { gpios = <&ioex_c1_port1 0 GPIO_OUTPUT_LOW>; - enum-name = "IOEX_USB_C1_PPC_EN_L"; }; usb_c1_ppc_ilim_3a_en { gpios = <&ioex_c1_port1 1 GPIO_OUTPUT_LOW>; enum-name = "IOEX_USB_C1_PPC_ILIM_3A_EN"; }; - /* TODO: figure out interrupts */ - usb_c1_sbu_fault_odl { + ioex_usb_c1_sbu_fault_odl: usb_c1_sbu_fault_odl { gpios = <&ioex_c1_port1 2 GPIO_INPUT>; enum-name = "IOEX_USB_C1_FAULT_ODL"; }; ioex_en_pp5000_usb_a1_vbus: en_pp5000_usb_a1_vbus { gpios = <&ioex_c1_port1 5 GPIO_OUTPUT_LOW>; - enum-name = "IOEX_EN_PP5000_USB_A1_VBUS_DB"; }; - /* TODO: figure out interrupts */ - usb_a1_fault_db_odl { + ioex_usb_a1_fault_db_odl: usb_a1_fault_db_odl { gpios = <&ioex_c1_port1 6 GPIO_INPUT>; - enum-name = "IOEX_USB_A1_FAULT_DB_ODL"; }; - usb_c1_sbu_flip { + ioex_usb_c1_sbu_flip: usb_c1_sbu_flip { gpios = <&ioex_c1_port1 7 GPIO_OUTPUT_LOW>; enum-name = "IOEX_USB_C1_SBU_FLIP"; }; @@ -265,100 +335,37 @@ enable-pins = <&ioex_en_pp5000_usb_a0_vbus &ioex_en_pp5000_usb_a1_vbus>; }; - - vsby-psl-in-list { - /* PSL_IN1/2/4 are used to wake */ - psl-in-pads = <&psl_in1 &psl_in2 &psl_in4>; - status = "okay"; - }; }; /* PSL input pads*/ -&psl_in1 { +&psl_in1_gpd2 { /* MECH_PWR_BTN_ODL */ - flag = <NPCX_PSL_FALLING_EDGE>; + psl-in-mode = "edge"; + psl-in-pol = "low-falling"; }; -&psl_in2 { +&psl_in2_gp00 { /* ACOK_OD */ - flag = <NPCX_PSL_RISING_EDGE>; + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; }; -&psl_in4 { +&psl_in4_gp02 { /* LID_OPEN */ - flag = <NPCX_PSL_RISING_EDGE>; + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; }; -&i2c0_0 { - nct3807_C0:nct3807_C0@70 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "nuvoton,nct38xx-gpio"; - reg = <0x70>; - label = "NCT3807_C0"; - - ioex_c0_port0:gpio@0 { - compatible = "nuvoton,nct38xx-gpio-port"; - reg = <0x0>; - label = "NCT3807_C0_GPIO0"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - pin_mask = <0xff>; - pinmux_mask = <0xf7>; - }; - ioex_c0_port1:gpio@1 { - compatible = "nuvoton,nct38xx-gpio-port"; - reg = <0x1>; - label = "NCT3807_C0_GPIO1"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - pin_mask = <0xff>; - }; - }; - - nct3808_alert_0 { - compatible = "nuvoton,nct38xx-gpio-alert"; - irq-gpios = <&gpioe 0 GPIO_ACTIVE_LOW>; - nct38xx-dev = <&nct3807_C0>; - label = "NCT3807_ALERT_0"; - }; +/* Power domain device controlled by PSL (Power Switch Logic) IO pads */ +&power_ctrl_psl { + status = "okay"; + pinctrl-names = "sleep"; + pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in4_gp02>; }; -&i2c1_0 { - nct3807_C1:nct3807_C1@70 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "nuvoton,nct38xx-gpio"; - reg = <0x70>; - label = "NCT3807_C1"; - - ioex_c1_port0:gpio@0 { - compatible = "nuvoton,nct38xx-gpio-port"; - reg = <0x0>; - label = "NCT3807_C1_GPIO0"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - pin_mask = <0xff>; - pinmux_mask = <0xf7>; - }; - ioex_c1_port1:gpio@1 { - compatible = "nuvoton,nct38xx-gpio-port"; - reg = <0x1>; - label = "NCT3807_C1_GPIO1"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - pin_mask = <0xff>; - }; - }; - - nct3808_alert_1 { - compatible = "nuvoton,nct38xx-gpio-alert"; - irq-gpios = <&gpioc 7 GPIO_ACTIVE_LOW>; - nct38xx-dev = <&nct3807_C1>; - label = "NCT3807_ALERT_1"; - }; +/* host interface */ +&espi0 { + status = "okay"; + pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; + pinctrl-names = "default"; }; diff --git a/zephyr/projects/skyrim/guybrush.dts b/zephyr/projects/skyrim/guybrush.dts deleted file mode 100644 index 6c5c72d061..0000000000 --- a/zephyr/projects/skyrim/guybrush.dts +++ /dev/null @@ -1,198 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/ { - aliases { - gpio-wp = &gpio_wp; - gpio-kbd-kso2 = &gpio_ec_kso_02_inv; - }; - - named-gpios { - /* Guybrush-specific GPIO customizations */ - gpio_wp: ec_wp_l { - gpios = <&gpio5 0 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; - }; - gpio_ec_pwr_btn_odl: ec_pwr_btn_odl { - gpios = <&gpio0 1 GPIO_INPUT>; - }; - gpio_slp_s3_s0i3_l: slp_s3_s0i3_l { - gpios = <&gpio7 4 GPIO_INPUT>; - enum-name = "GPIO_PCH_SLP_S0_L"; - }; - gpio_ec_pcore_int_odl: ec_pcore_int_odl { - gpios = <&gpiof 0 GPIO_INPUT_PULL_UP>; - }; - gpio_pg_groupc_s0_od: pg_groupc_s0_od { - gpios = <&gpioa 3 GPIO_INPUT>; - }; - gpio_pg_lpddr4x_s3_od: pg_lpddr4x_s3_od { - gpios = <&gpio9 5 GPIO_INPUT>; - }; - ec_soc_pwr_good { - gpios = <&gpiod 3 GPIO_OUTPUT_LOW>; - enum-name = "GPIO_PCH_SYS_PWROK"; - }; - ec_entering_rw { - gpios = <&gpio6 6 GPIO_OUTPUT_LOW>; - enum-name = "GPIO_ENTERING_RW"; - }; - ec_clr_cmos { - gpios = <&gpioa 1 GPIO_OUTPUT_LOW>; - }; - ec_mem_event { - gpios = <&gpioa 5 GPIO_OUTPUT_LOW>; - }; - gpio_ec_soc_pwr_btn_l: ec_soc_pwr_btn_l { - gpios = <&gpio6 3 GPIO_OUTPUT_HIGH>; - enum-name = "GPIO_PCH_PWRBTN_L"; - }; - ec_soc_int_l { - gpios = <&gpio8 3 GPIO_OUTPUT_HIGH>; - enum-name = "GPIO_EC_INT_L"; - }; - soc_thermtrip_odl { - gpios = <&gpioe 5 GPIO_INPUT>; - }; - gpio_usb_c0_c1_fault_odl: usb_c0_c1_fault_odl { - gpios = <&gpio7 3 GPIO_ODR_HIGH>; - }; - 3axis_int_l { - gpios = <&gpioa 2 GPIO_INPUT_PULL_DOWN>; - }; - gpio_voldn_btn_odl: voldn_btn_odl { - gpios = <&gpioa 7 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_VOLUME_DOWN_L"; - }; - gpio_volup_btn_odl: volup_btn_odl { - gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_VOLUME_UP_L"; - }; - ec_ps2_clk { - gpios = <&gpio6 7 GPIO_INPUT_PULL_UP>; - }; - ec_ps2_dat { - gpios = <&gpio7 0 GPIO_INPUT_PULL_UP>; - }; - ec_ps2_rst { - gpios = <&gpio6 2 GPIO_INPUT_PULL_UP>; - }; - ec_gpiob0 { - gpios = <&gpiob 0 GPIO_INPUT_PULL_UP>; - }; - ec_gpio81 { - gpios = <&gpio8 1 GPIO_INPUT_PULL_UP>; - }; - ec_psl_gpo { - gpios = <&gpiod 7 GPIO_INPUT_PULL_UP>; - }; - ec_pwm7 { - gpios = <&gpio6 0 GPIO_INPUT_PULL_UP>; - }; - gpio_accel_gyro_int_l: accel_gyro_int_l { - gpios = <&gpioa 0 GPIO_INPUT_PULL_UP>; - }; - }; - - def-lvol-io-list { - compatible = "nuvoton,npcx-lvolctrl-def"; - - /* Low voltage on I2C6_1 */ - lvol-io-pads = <&lvol_ioe4 &lvol_ioe3>; - }; - - named-adc-channels { - compatible = "named-adc-channels"; - - adc_temp_soc: temp-soc { - label = "SOC"; - enum-name = "ADC_TEMP_SENSOR_SOC"; - io-channels = <&adc0 0>; - }; - }; - - named-temp-sensors { - soc-tmp112 { - compatible = "cros-ec,temp-sensor-tmp112", - "cros-ec,temp-sensor"; - label = "SOC"; - enum-name = "TEMP_SENSOR_SOC"; - tmp112-name = "TMP112_SOC"; - port = <&i2c_sensor>; - i2c-addr-flags = "TMP112_I2C_ADDR_FLAGS0"; - temp_host_high = <100>; - temp_host_halt = <105>; - temp_host_release_high = <80>; - temp_fan_off = <0>; - temp_fan_max = <70>; - }; - amb-tmp112 { - compatible = "cros-ec,temp-sensor-tmp112", - "cros-ec,temp-sensor"; - label = "Ambient"; - enum-name = "TEMP_SENSOR_AMB"; - tmp112-name = "TMP112_AMB"; - port = <&i2c_sensor>; - i2c-addr-flags = "TMP112_I2C_ADDR_FLAGS1"; - }; - }; - - gpio-interrupts { - compatible = "cros-ec,gpio-interrupts"; - - int_pg_lpddr4x_s3: pg_lpddr4x_s3 { - irq-pin = <&gpio_pg_lpddr4x_s3_od>; - flags = <GPIO_INT_EDGE_BOTH>; - handler = "baseboard_en_pwr_pcore_s0"; - }; - int_slp_s3_s0i3: slp_s3_s0i3 { - irq-pin = <&gpio_slp_s3_s0i3_l>; - flags = <GPIO_INT_EDGE_BOTH>; - handler = "power_signal_interrupt"; - }; - int_ec_pwr_btn: ec_pwr_btn { - irq-pin = <&gpio_ec_pwr_btn_odl>; - flags = <GPIO_INT_EDGE_BOTH>; - handler = "power_signal_interrupt"; - }; - int_ec_pcore: ec_pcore { - irq-pin = <&gpio_ec_pcore_int_odl>; - flags = <GPIO_INT_EDGE_BOTH>; - handler = "power_signal_interrupt"; - }; - int_pg_groupc_s0: pg_groupc_s0 { - irq-pin = <&gpio_pg_groupc_s0_od>; - flags = <GPIO_INT_EDGE_BOTH>; - handler = "baseboard_en_pwr_pcore_s0"; - }; - int_s0_pgood: s0_pgood { - irq-pin = <&gpio_s0_pgood>; - flags = <GPIO_INT_EDGE_BOTH>; - handler = "power_signal_interrupt"; - }; - }; - - /* Rotation matrices for motion sensors. */ - motionsense-rotation-ref { - compatible = "cros-ec,motionsense-rotation-ref"; - lid_rot_ref: lid-rotation-ref { - mat33 = <0 (-1) 0 - (-1) 0 0 - 0 0 (-1)>; - }; - - base_rot_ref: base-rotation-ref { - mat33 = <(-1) 0 0 - 0 1 0 - 0 0 (-1)>; - }; - }; -}; - -/* host interface */ -&espi0 { - status = "okay"; - pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; - pinctrl-names = "default"; -}; diff --git a/zephyr/projects/skyrim/i2c.dts b/zephyr/projects/skyrim/i2c.dts deleted file mode 100644 index 3ac516eb46..0000000000 --- a/zephyr/projects/skyrim/i2c.dts +++ /dev/null @@ -1,169 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/ { - aliases { - i2c-0 = &i2c0_0; - i2c-1 = &i2c1_0; - i2c-2 = &i2c2_0; - i2c-3 = &i2c3_0; - i2c-4 = &i2c4_1; - i2c-5 = &i2c5_0; - i2c-7 = &i2c7_0; - }; - - named-i2c-ports { - compatible = "named-i2c-ports"; - - i2c_tcpc0: tcpc0 { - i2c-port = <&i2c0_0>; - enum-name = "I2C_PORT_TCPC0"; - }; - - i2c_tcpc1: tcpc1 { - i2c-port = <&i2c1_0>; - enum-name = "I2C_PORT_TCPC1"; - }; - - battery { - i2c-port = <&i2c2_0>; - remote-port = <0>; - enum-name = "I2C_PORT_BATTERY"; - }; - - usb-mux { - i2c-port = <&i2c3_0>; - enum-name = "I2C_PORT_USB_MUX"; - }; - - i2c_charger: charger { - i2c-port = <&i2c4_1>; - enum-name = "I2C_PORT_CHARGER"; - }; - - eeprom { - i2c-port = <&i2c5_0>; - enum-name = "I2C_PORT_EEPROM"; - }; - - i2c_sensor: sensor { - i2c-port = <&i2c6_1>; - enum-name = "I2C_PORT_SENSOR"; - }; - - i2c_soc_thermal: soc-thermal { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_THERMAL_AP"; - }; - }; - - -}; - -&i2c0_0 { - status = "okay"; - label = "I2C_TCPC0"; - clock-frequency = <I2C_BITRATE_FAST>; - pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; - pinctrl-names = "default"; -}; - -&i2c_ctrl0 { - status = "okay"; -}; - -&i2c1_0 { - status = "okay"; - label = "I2C_TCPC1"; - clock-frequency = <I2C_BITRATE_FAST>; - pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; - pinctrl-names = "default"; -}; - -&i2c_ctrl1 { - status = "okay"; -}; - -&i2c2_0 { - status = "okay"; - label = "I2C_BATTERY"; - clock-frequency = <I2C_BITRATE_STANDARD>; - pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>; - pinctrl-names = "default"; -}; - -&i2c_ctrl2 { - status = "okay"; -}; - -&i2c3_0 { - status = "okay"; - label = "I2C_USB_MUX"; - clock-frequency = <I2C_BITRATE_FAST>; - pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>; - pinctrl-names = "default"; -}; - -&i2c_ctrl3 { - status = "okay"; -}; - -&i2c4_1 { - status = "okay"; - label = "I2C_CHARGER"; - clock-frequency = <I2C_BITRATE_FAST>; - pinctrl-0 = <&i2c4_1_sda_scl_gpf2_f3>; - pinctrl-names = "default"; -}; - -&i2c_ctrl4 { - status = "okay"; -}; - -&i2c5_0 { - status = "okay"; - label = "I2C_EEPROM"; - clock-frequency = <I2C_BITRATE_FAST>; - pinctrl-0 = <&i2c5_0_sda_scl_gp33_36>; - pinctrl-names = "default"; - - cbi_eeprom: eeprom@50 { - compatible = "atmel,at24"; - reg = <0x50>; - label = "EEPROM_CBI"; - size = <2048>; - pagesize = <16>; - address-width = <8>; - timeout = <5>; - }; -}; - -&i2c_ctrl5 { - status = "okay"; -}; - -&i2c6_1 { - status = "okay"; - label = "I2C_SENSOR"; - clock-frequency = <I2C_BITRATE_FAST>; - pinctrl-0 = <&i2c6_1_sda_scl_gpe3_e4>; - pinctrl-names = "default"; -}; - -&i2c_ctrl6 { - status = "okay"; -}; - -&i2c7_0 { - status = "okay"; - label = "I2C_THERMAL_AP"; - clock-frequency = <I2C_BITRATE_FAST>; - pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>; - pinctrl-names = "default"; -}; - -&i2c_ctrl7 { - status = "okay"; -}; diff --git a/zephyr/projects/skyrim/i2c_common.dtsi b/zephyr/projects/skyrim/i2c_common.dtsi new file mode 100644 index 0000000000..8358b1c296 --- /dev/null +++ b/zephyr/projects/skyrim/i2c_common.dtsi @@ -0,0 +1,300 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + + #include <dt-bindings/usb_pd_tcpm.h> + +/ { + aliases { + i2c-0 = &i2c0_0; + i2c-1 = &i2c1_0; + i2c-2 = &i2c2_0; + i2c-3 = &i2c3_0; + i2c-4 = &i2c4_1; + i2c-5 = &i2c5_0; + i2c-7 = &i2c7_0; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_tcpc0: tcpc0 { + i2c-port = <&i2c0_0>; + enum-names = "I2C_PORT_TCPC0"; + }; + + i2c_tcpc1: tcpc1 { + i2c-port = <&i2c1_0>; + enum-names = "I2C_PORT_TCPC1"; + }; + + battery { + i2c-port = <&i2c2_0>; + remote-port = <0>; + enum-names = "I2C_PORT_BATTERY"; + }; + + usb-mux { + i2c-port = <&i2c3_0>; + enum-names = "I2C_PORT_USB_MUX"; + }; + + i2c_charger: charger { + i2c-port = <&i2c4_1>; + enum-names = "I2C_PORT_CHARGER"; + }; + + eeprom { + i2c-port = <&i2c5_0>; + enum-names = "I2C_PORT_EEPROM"; + }; + + i2c_sensor: sensor { + i2c-port = <&i2c6_1>; + enum-names = "I2C_PORT_SENSOR"; + }; + + i2c_soc_thermal: soc-thermal { + i2c-port = <&i2c7_0>; + enum-names = "I2C_PORT_THERMAL_AP"; + }; + }; + + +}; + +&i2c0_0 { + status = "okay"; + label = "I2C_TCPC0"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; + pinctrl-names = "default"; + + bc12_port0: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + irq = <&int_usb_c0_bc12>; + }; + + tcpc_port0: nct38xx@70 { + compatible = "nuvoton,nct38xx"; + reg = <0x70>; + gpio-dev = <&nct3807_C0>; + tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>; + }; + + nct3807_C0:nct3807_C0@70 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nuvoton,nct38xx-gpio"; + reg = <0x70>; + label = "NCT3807_C0"; + + ioex_c0_port0:gpio@0 { + compatible = "nuvoton,nct38xx-gpio-port"; + reg = <0x0>; + label = "NCT3807_C0_GPIO0"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + pin_mask = <0xff>; + pinmux_mask = <0xf7>; + }; + ioex_c0_port1:gpio@1 { + compatible = "nuvoton,nct38xx-gpio-port"; + reg = <0x1>; + label = "NCT3807_C0_GPIO1"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + pin_mask = <0xff>; + }; + }; + + nct3808_alert_0 { + compatible = "nuvoton,nct38xx-gpio-alert"; + irq-gpios = <&gpioe 0 GPIO_ACTIVE_LOW>; + nct38xx-dev = <&nct3807_C0>; + label = "NCT3807_ALERT_0"; + }; +}; + +&i2c_ctrl0 { + status = "okay"; +}; + +&i2c1_0 { + status = "okay"; + label = "I2C_TCPC1"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; + pinctrl-names = "default"; + + bc12_port1: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + irq = <&int_usb_c1_bc12>; + }; + + tcpc_port1: nct38xx@70 { + compatible = "nuvoton,nct38xx"; + reg = <0x70>; + gpio-dev = <&nct3807_C1>; + tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>; + }; + + nct3807_C1:nct3807_C1@70 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nuvoton,nct38xx-gpio"; + reg = <0x70>; + label = "NCT3807_C1"; + + ioex_c1_port0:gpio@0 { + compatible = "nuvoton,nct38xx-gpio-port"; + reg = <0x0>; + label = "NCT3807_C1_GPIO0"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + pin_mask = <0xff>; + pinmux_mask = <0xf7>; + }; + ioex_c1_port1:gpio@1 { + compatible = "nuvoton,nct38xx-gpio-port"; + reg = <0x1>; + label = "NCT3807_C1_GPIO1"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + pin_mask = <0xff>; + }; + }; + + nct3808_alert_1 { + compatible = "nuvoton,nct38xx-gpio-alert"; + irq-gpios = <&gpioc 7 GPIO_ACTIVE_LOW>; + nct38xx-dev = <&nct3807_C1>; + label = "NCT3807_ALERT_1"; + }; +}; + +&i2c_ctrl1 { + status = "okay"; +}; + +&i2c2_0 { + status = "okay"; + label = "I2C_BATTERY"; + clock-frequency = <I2C_BITRATE_STANDARD>; + pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>; + pinctrl-names = "default"; +}; + +&i2c_ctrl2 { + status = "okay"; +}; + +&i2c3_0 { + status = "okay"; + label = "I2C_USB_MUX"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>; + pinctrl-names = "default"; + + amd_fp6_port0: amd_fp6@5c { + compatible = "amd,usbc-mux-amd-fp6"; + status = "okay"; + reg = <0x5c>; + }; + amd_fp6_port1: amd_fp6@52 { + compatible = "amd,usbc-mux-amd-fp6"; + status = "okay"; + reg = <0x52>; + }; +}; + +&i2c_ctrl3 { + status = "okay"; +}; + +&i2c4_1 { + status = "okay"; + label = "I2C_CHARGER"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c4_1_sda_scl_gpf2_f3>; + pinctrl-names = "default"; + + charger: isl9241@9 { + compatible = "intersil,isl9241"; + status = "okay"; + reg = <0x9>; + }; +}; + +&i2c_ctrl4 { + status = "okay"; +}; + +&i2c5_0 { + status = "okay"; + label = "I2C_EEPROM"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c5_0_sda_scl_gp33_36>; + pinctrl-names = "default"; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; +}; + +&i2c_ctrl5 { + status = "okay"; +}; + +&i2c6_1 { + status = "okay"; + label = "I2C_SENSOR"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c6_1_sda_scl_gpe3_e4>; + pinctrl-names = "default"; + + soc_pct2075: soc-pct2075@48 { + compatible = "nxp,pct2075"; + reg = <0x48>; + }; + + amb_pct2075: amb-pct2075@4f { + compatible = "nxp,pct2075"; + reg = <0x4f>; + }; +}; + +&i2c_ctrl6 { + status = "okay"; +}; + +&i2c7_0 { + status = "okay"; + label = "I2C_THERMAL_AP"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>; + pinctrl-names = "default"; + + temp_cpu: cpu@4c { + compatible = "amd,sb-tsi"; + reg = <0x4c>; + }; +}; + +&i2c_ctrl7 { + status = "okay"; +}; diff --git a/zephyr/projects/skyrim/include/gpio_map.h b/zephyr/projects/skyrim/include/gpio_map.h deleted file mode 100644 index ca1272a9ed..0000000000 --- a/zephyr/projects/skyrim/include/gpio_map.h +++ /dev/null @@ -1,28 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __ZEPHYR_GPIO_MAP_H -#define __ZEPHYR_GPIO_MAP_H - -#include <zephyr/devicetree.h> -#include <gpio_signal.h> - -/* Power input signals */ -enum power_signal { - X86_SLP_S3_N, /* SOC -> SLP_S3_L */ - X86_SLP_S5_N, /* SOC -> SLP_S5_L */ - - X86_S0_PGOOD, /* PMIC -> S0_PWROK_OD */ - X86_S5_PGOOD, /* PMIC -> S5_PWROK */ - - /* Number of X86 signals */ - POWER_SIGNAL_COUNT, -}; - -#define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED -#define GPIO_PCH_SYS_PWROK GPIO_UNIMPLEMENTED -#define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S3_L - -#endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/skyrim/include_guybrush/gpio_map.h b/zephyr/projects/skyrim/include_guybrush/gpio_map.h deleted file mode 100644 index 22d0eb602e..0000000000 --- a/zephyr/projects/skyrim/include_guybrush/gpio_map.h +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __ZEPHYR_GPIO_MAP_H -#define __ZEPHYR_GPIO_MAP_H - -#include <zephyr/devicetree.h> -#include <gpio_signal.h> - -/* Power input signals */ -enum power_signal { - X86_SLP_S0_N, /* SOC -> SLP_S3_S0I3_L */ - X86_SLP_S3_N, /* SOC -> SLP_S3_L */ - X86_SLP_S5_N, /* SOC -> SLP_S5_L */ - - X86_S0_PGOOD, /* PMIC -> S0_PWROK_OD */ - X86_S5_PGOOD, /* PMIC -> S5_PWROK */ - - /* Number of X86 signals */ - POWER_SIGNAL_COUNT, -}; - -#endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/skyrim/interrupts.dts b/zephyr/projects/skyrim/interrupts.dts index 59507f8081..0749b72078 100644 --- a/zephyr/projects/skyrim/interrupts.dts +++ b/zephyr/projects/skyrim/interrupts.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -42,6 +42,26 @@ flags = <GPIO_INT_EDGE_BOTH>; handler = "baseboard_set_en_pwr_pcore"; }; + int_pg_lpddr_s3: pg_lpddr_s3 { + irq-pin = <&gpio_pg_lpddr5_s3_od>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "baseboard_set_en_pwr_pcore"; + }; + int_pg_lpddr_s0: pg_lpddr_s0 { + irq-pin = <&gpio_pg_lpddr5_s0_od>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "baseboard_set_soc_pwr_pgood"; + }; + int_s0_pgood: s0_pgood { + irq-pin = <&gpio_s0_pgood>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "baseboard_s0_pgood"; + }; + int_soc_thermtrip: soc_thermtrip { + irq-pin = <&gpio_soc_thermtrip_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "baseboard_soc_thermtrip"; + }; int_volume_up: volume_up { irq-pin = <&gpio_volup_btn_odl>; flags = <GPIO_INT_EDGE_BOTH>; @@ -52,6 +72,26 @@ flags = <GPIO_INT_EDGE_BOTH>; handler = "button_interrupt"; }; + int_usb_a0_fault: a0_fault { + irq-pin = <&ioex_usb_a0_fault_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "usb_fault_interrupt"; + }; + int_usb_a1_fault: a1_fault { + irq-pin = <&ioex_usb_a1_fault_db_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "usb_fault_interrupt"; + }; + int_usb_c0_sbu_fault: c0_sbu_fault { + irq-pin = <&ioex_usb_c0_sbu_fault_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "sbu_fault_interrupt"; + }; + int_usb_c1_sbu_fault: c1_sbu_fault { + irq-pin = <&ioex_usb_c1_sbu_fault_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "sbu_fault_interrupt"; + }; int_usb_c0_tcpc: usb_c0_tcpc { irq-pin = <&gpio_usb_c0_tcpc_int_odl>; flags = <GPIO_INT_EDGE_FALLING>; @@ -82,6 +122,16 @@ flags = <GPIO_INT_EDGE_FALLING>; handler = "bc12_interrupt"; }; + int_usb_hub_fault: hub_fault { + irq-pin = <&gpio_usb_hub_fault_q_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "usb_fault_interrupt"; + }; + int_usb_pd_soc: usb_pd_soc { + irq-pin = <&gpio_ec_i2c_usbc_pd_int>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "usb_pd_soc_interrupt"; + }; int_accel_gyro: accel_gyro { irq-pin = <&gpio_accel_gyro_int_l>; flags = <GPIO_INT_EDGE_FALLING>; diff --git a/zephyr/projects/skyrim/keyboard.dts b/zephyr/projects/skyrim/keyboard.dts index 216ea97045..df334ba54c 100644 --- a/zephyr/projects/skyrim/keyboard.dts +++ b/zephyr/projects/skyrim/keyboard.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -7,7 +7,6 @@ kblight { compatible = "cros-ec,kblight-pwm"; pwms = <&pwm1 0 PWM_HZ(100) PWM_POLARITY_NORMAL>; - frequency = <100>; }; }; diff --git a/zephyr/projects/skyrim/led_pins_morthal.dts b/zephyr/projects/skyrim/led_pins_morthal.dts new file mode 100644 index 0000000000..33a66c0756 --- /dev/null +++ b/zephyr/projects/skyrim/led_pins_morthal.dts @@ -0,0 +1,63 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwm_pins { + compatible = "cros-ec,pwm-pin-config"; + + pwm_y: pwm_y { + #led-pin-cells = <1>; + pwms = <&pwm2 0 PWM_HZ(100) PWM_POLARITY_INVERTED>; + }; + + pwm_w: pwm_w { + #led-pin-cells = <1>; + pwms = <&pwm3 0 PWM_HZ(100) PWM_POLARITY_INVERTED>; + }; + }; + + pwm-led-pins { + compatible = "cros-ec,pwm-led-pins"; + + color_off: color-off { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&pwm_y 0>, + <&pwm_w 0>; + }; + + color_amber: color-amber { + led-color = "LED_AMBER"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_AMBER"; + led-pins = <&pwm_y 100>, + <&pwm_w 0>; + }; + + color_white: color-white { + led-color = "LED_WHITE"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_BLUE"; + led-pins = <&pwm_y 0>, + <&pwm_w 100>; + }; + }; +}; + +/* Amber "battery charging" LED */ +&pwm2 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm2_gpc4>; + pinctrl-names = "default"; +}; + +/* White "battery full" LED */ +&pwm3 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm3_gp80>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/skyrim/led_pins_skyrim.dts b/zephyr/projects/skyrim/led_pins_skyrim.dts index 3ff966bcf6..33a66c0756 100644 --- a/zephyr/projects/skyrim/led_pins_skyrim.dts +++ b/zephyr/projects/skyrim/led_pins_skyrim.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -20,7 +20,6 @@ pwm-led-pins { compatible = "cros-ec,pwm-led-pins"; - pwm-frequency = <100>; color_off: color-off { led-color = "LED_OFF"; diff --git a/zephyr/projects/skyrim/led_pins_winterhold.dts b/zephyr/projects/skyrim/led_pins_winterhold.dts new file mode 100644 index 0000000000..33a66c0756 --- /dev/null +++ b/zephyr/projects/skyrim/led_pins_winterhold.dts @@ -0,0 +1,63 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwm_pins { + compatible = "cros-ec,pwm-pin-config"; + + pwm_y: pwm_y { + #led-pin-cells = <1>; + pwms = <&pwm2 0 PWM_HZ(100) PWM_POLARITY_INVERTED>; + }; + + pwm_w: pwm_w { + #led-pin-cells = <1>; + pwms = <&pwm3 0 PWM_HZ(100) PWM_POLARITY_INVERTED>; + }; + }; + + pwm-led-pins { + compatible = "cros-ec,pwm-led-pins"; + + color_off: color-off { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&pwm_y 0>, + <&pwm_w 0>; + }; + + color_amber: color-amber { + led-color = "LED_AMBER"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_AMBER"; + led-pins = <&pwm_y 100>, + <&pwm_w 0>; + }; + + color_white: color-white { + led-color = "LED_WHITE"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_BLUE"; + led-pins = <&pwm_y 0>, + <&pwm_w 100>; + }; + }; +}; + +/* Amber "battery charging" LED */ +&pwm2 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm2_gpc4>; + pinctrl-names = "default"; +}; + +/* White "battery full" LED */ +&pwm3 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm3_gp80>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/skyrim/led_policy_morthal.dts b/zephyr/projects/skyrim/led_policy_morthal.dts new file mode 100644 index 0000000000..a075c6b0d2 --- /dev/null +++ b/zephyr/projects/skyrim/led_policy_morthal.dts @@ -0,0 +1,103 @@ +#include <dt-bindings/battery.h> + +/ { + led-colors { + compatible = "cros-ec,led-policy"; + + power-state-charge { + charge-state = "PWR_STATE_CHARGE"; + + color-0 { + led-color = <&color_amber>; + }; + }; + + power-state-discharge-s0 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + /* Battery percent range (> Low, <= Full) */ + batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>; + + color-0 { + led-color = <&color_white>; + }; + }; + + power-state-discharge-s0-batt-low { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + /* Battery percent range (>= Empty, <= Low) */ + batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>; + + /* White 2 sec, off 1 sec */ + color-0 { + led-color = <&color_white>; + period-ms = <2000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <1000>; + }; + }; + + power-state-discharge-s3 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S3"; + + /* White 1 sec, off 1 sec */ + color-0 { + led-color = <&color_white>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <1000>; + }; + }; + + power-state-discharge-s5 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-error { + charge-state = "PWR_STATE_ERROR"; + + /* Amber 1 sec, off 1 sec */ + color-0 { + led-color = <&color_amber>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <1000>; + }; + }; + + power-state-near-full { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + + color-0 { + led-color = <&color_white>; + }; + }; + + power-state-forced-idle { + charge-state = "PWR_STATE_FORCED_IDLE"; + + /* Amber 2 sec, White 2 sec */ + color-0 { + led-color = <&color_amber>; + period-ms = <2000>; + }; + color-1 { + led-color = <&color_white>; + period-ms = <2000>; + }; + }; + }; +}; diff --git a/zephyr/projects/skyrim/led_policy_skyrim.dts b/zephyr/projects/skyrim/led_policy_skyrim.dts index da3d817925..a075c6b0d2 100644 --- a/zephyr/projects/skyrim/led_policy_skyrim.dts +++ b/zephyr/projects/skyrim/led_policy_skyrim.dts @@ -2,7 +2,7 @@ / { led-colors { - compatible = "cros-ec,led-colors"; + compatible = "cros-ec,led-policy"; power-state-charge { charge-state = "PWR_STATE_CHARGE"; @@ -86,9 +86,8 @@ }; }; - power-state-idle-forced { - charge-state = "PWR_STATE_IDLE"; - extra-flag = "LED_CHFLAG_FORCE_IDLE"; + power-state-forced-idle { + charge-state = "PWR_STATE_FORCED_IDLE"; /* Amber 2 sec, White 2 sec */ color-0 { diff --git a/zephyr/projects/skyrim/led_policy_winterhold.dts b/zephyr/projects/skyrim/led_policy_winterhold.dts new file mode 100644 index 0000000000..f1f8aa31ed --- /dev/null +++ b/zephyr/projects/skyrim/led_policy_winterhold.dts @@ -0,0 +1,103 @@ +#include <dt-bindings/battery.h> + +/ { + led-colors { + compatible = "cros-ec,led-policy"; + + power-state-charge { + charge-state = "PWR_STATE_CHARGE"; + color-0 { + led-color = <&color_white>; + }; + }; + + power-state-discharge-s0 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + /* Battery percent range (> Low, <= Full) */ + batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-discharge-s0-batt-low { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + /* Battery percent range (>= Empty, <= Low) */ + batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>; + + color-0 { + led-color = <&color_amber>; + }; + }; + + power-state-discharge-s3 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S3"; + /* Battery percent range (> Low, <= Full) */ + batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-discharge-s3-batt-low { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S3"; + /* Battery percent range (>= Empty, <= Low) */ + batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>; + + color-0 { + led-color = <&color_amber>; + }; + }; + + power-state-discharge-s5 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-error { + charge-state = "PWR_STATE_ERROR"; + + /* Amber 1 sec, off 1 sec */ + color-0 { + led-color = <&color_amber>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <1000>; + }; + }; + + power-state-near-full { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-forced-idle { + charge-state = "PWR_STATE_FORCED_IDLE"; + + /* Amber 2 sec, White 2 sec */ + color-0 { + led-color = <&color_amber>; + period-ms = <2000>; + }; + color-1 { + led-color = <&color_white>; + period-ms = <2000>; + }; + }; + }; +}; diff --git a/zephyr/projects/skyrim/morthal.dts b/zephyr/projects/skyrim/morthal.dts new file mode 100644 index 0000000000..bb1e45aa87 --- /dev/null +++ b/zephyr/projects/skyrim/morthal.dts @@ -0,0 +1,175 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/usbc_mux.h> + +#include "i2c_common.dtsi" + +/ { + named-gpios { + /* Morthal-specific GPIO customizations */ + }; + + named-temp-sensors { + compatible = "cros-ec,temp-sensors"; + soc-pct2075 { + temp_host_high = <100>; + temp_host_halt = <105>; + temp_host_release_high = <80>; + temp_host_release_halt = <80>; + temp_fan_off = <0>; + temp_fan_max = <70>; + power-good-pin = <&gpio_pg_pwr_s5>; + sensor = <&soc_pct2075>; + }; + amb-pct2075 { + power-good-pin = <&gpio_pg_pwr_s5>; + sensor = <&amb_pct2075>; + }; + }; + + /* + * Note this is expected to vary per-board, so we keep it in the board + * dts files. + */ + morthal-fw-config { + compatible = "cros-ec,cbi-fw-config"; + + form-factor { + enum-name = "FW_FORM_FACTOR"; + start = <0>; + size = <1>; + + ff-clamshell { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_FF_CLAMSHELL"; + value = <0>; + }; + ff-convertible { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_FF_CONVERTIBLE"; + value = <1>; + default; + }; + }; + io-db { + enum-name = "FW_IO_DB"; + start = <6>; + size = <2>; + + io-db-ps8811-ps8818 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_IO_DB_PS8811_PS8818"; + value = <0>; + }; + io-db-none-anx7483 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_IO_DB_NONE_ANX7483"; + value = <1>; + default; + }; + }; + + /* + * FW_CONFIG field to enable fan or not. + */ + fan { + enum-name = "FW_FAN"; + start = <10>; + size = <1>; + + no-fan { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_FAN_NOT_PRESENT"; + value = <0>; + }; + fan-present { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_FAN_PRESENT"; + value = <1>; + /* + * Set as default so that unprovisioned + * configs will run the fan regardless. + */ + default; + }; + }; + }; + + /* Rotation matrices for motion sensors. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <0 (-1) 0 + 1 0 0 + 0 0 1>; + }; + + lid_rot_ref1: lid-rotation-ref1 { + mat33 = <0 1 0 + (-1) 0 0 + 0 0 1>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <0 1 0 + (-1) 0 0 + 0 0 1>; + }; + }; + + ppc_port0: aoz1380 { + compatible = "aoz,aoz1380"; + status = "okay"; + }; +}; + +&i2c0_0 { + anx7483_port0: anx7483@3e { + compatible = "analogix,anx7483"; + reg = <0x3e>; + board-set = "board_anx7483_c0_mux_set"; + }; +}; + +&i2c1_0 { + anx7483_port1: anx7483@3e { + compatible = "analogix,anx7483"; + reg = <0x3e>; + board-set = "board_anx7483_c1_mux_set"; + }; + ppc_port1: nx20p348x@71 { + compatible = "nxp,nx20p348x"; + status = "okay"; + reg = <0x71>; + }; + ps8818_port1: ps8818@28 { + compatible = "parade,ps8818"; + reg = <0x28>; + flags = <(USB_MUX_FLAG_RESETS_IN_G3)>; + board-set = "board_c1_ps8818_mux_set"; + }; +}; + +&usbc_port0 { + ppc = <&ppc_port0>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&amd_fp6_port0 &anx7483_port0>; + }; +}; + +&usbc_port1 { + ppc = <&ppc_port1>; + usb-mux-chain-1-anx { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&amd_fp6_port1 &anx7483_port1>; + }; + usb_mux_chain_ps8818_port1: usb-mux-chain-1-ps { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&amd_fp6_port1 &ps8818_port1>; + alternative-chain; + }; +}; diff --git a/zephyr/projects/skyrim/motionsense.dts b/zephyr/projects/skyrim/motionsense.dts index 642a1cddf8..f943bea4c8 100644 --- a/zephyr/projects/skyrim/motionsense.dts +++ b/zephyr/projects/skyrim/motionsense.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -26,11 +26,9 @@ motionsense-mutex { compatible = "cros-ec,motionsense-mutex"; lid_mutex: lid-mutex { - label = "LID_MUTEX"; }; mutex_bmi3xx: bmi3xx-mutex { - label = "BMI3XX_MUTEX"; }; }; @@ -57,7 +55,7 @@ /* * List of motion sensors that creates motion_sensors array. - * The label "lid_accel" and "base_accel" are used to indicate + * The nodelabel "lid_accel" and "base_accel" are used to indicate * motion sensor IDs for lid angle calculation. */ motionsense-sensor { @@ -65,7 +63,6 @@ compatible = "cros-ec,bma4xx"; status = "okay"; - label = "Lid Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_LID"; mutex = <&lid_mutex>; @@ -77,12 +74,10 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(12500 | ROUND_UP_FLAG)>; ec-rate = <100>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(12500 | ROUND_UP_FLAG)>; }; }; @@ -92,7 +87,6 @@ compatible = "cros-ec,bmi3xx-accel"; status = "okay"; - label = "Base Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&mutex_bmi3xx>; @@ -104,12 +98,10 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(12500 | ROUND_UP_FLAG)>; ec-rate = <100>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(12500 | ROUND_UP_FLAG)>; }; }; @@ -119,7 +111,6 @@ compatible = "cros-ec,bmi3xx-gyro"; status = "okay"; - label = "Base Gyro"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&mutex_bmi3xx>; diff --git a/zephyr/projects/skyrim/power_signals_guybrush.c b/zephyr/projects/skyrim/power_signals_guybrush.c deleted file mode 100644 index 11110886f2..0000000000 --- a/zephyr/projects/skyrim/power_signals_guybrush.c +++ /dev/null @@ -1,125 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include <zephyr/drivers/gpio.h> - -#include "chipset.h" -#include "config.h" -#include "gpio_signal.h" -#include "gpio/gpio_int.h" -#include "hooks.h" -#include "power.h" -#include "timer.h" - -/* Wake Sources */ -/* TODO: b/218904113: Convert to using Zephyr GPIOs */ -const enum gpio_signal hibernate_wake_pins[] = { - GPIO_LID_OPEN, - GPIO_AC_PRESENT, - GPIO_POWER_BUTTON_L, -}; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); - -/* Power Signal Input List */ -/* TODO: b/218904113: Convert to using Zephyr GPIOs */ -const struct power_signal_info power_signal_list[] = { - [X86_SLP_S0_N] = { - .gpio = GPIO_PCH_SLP_S0_L, - .flags = POWER_SIGNAL_ACTIVE_HIGH, - .name = "SLP_S0_DEASSERTED", - }, - [X86_SLP_S3_N] = { - .gpio = GPIO_PCH_SLP_S3_L, - .flags = POWER_SIGNAL_ACTIVE_HIGH, - .name = "SLP_S3_DEASSERTED", - }, - [X86_SLP_S5_N] = { - .gpio = GPIO_PCH_SLP_S5_L, - .flags = POWER_SIGNAL_ACTIVE_HIGH, - .name = "SLP_S5_DEASSERTED", - }, - [X86_S0_PGOOD] = { - .gpio = GPIO_S0_PGOOD, - .flags = POWER_SIGNAL_ACTIVE_HIGH, - .name = "S0_PGOOD", - }, - [X86_S5_PGOOD] = { - .gpio = GPIO_S5_PGOOD, - .flags = POWER_SIGNAL_ACTIVE_HIGH, - .name = "S5_PGOOD", - }, -}; -BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); - -static void baseboard_interrupt_init(void) -{ - /* Enable Power Group interrupts. */ - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_groupc_s0)); - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_lpddr4x_s3)); -} -DECLARE_HOOK(HOOK_INIT, baseboard_interrupt_init, HOOK_PRIO_POST_I2C); - -/** - * b/175324615: On G3->S5, wait for RSMRST_L to be deasserted before asserting - * PCH_PWRBTN_L. - */ -void board_pwrbtn_to_pch(int level) -{ - timestamp_t start; - const uint32_t timeout_rsmrst_rise_us = 30 * MSEC; - - /* Add delay for G3 exit if asserting PWRBTN_L and RSMRST_L is low. */ - if (!level && - !gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l))) { - start = get_time(); - do { - usleep(200); - if (gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l))) - break; - } while (time_since32(start) < timeout_rsmrst_rise_us); - - if (!gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l))) - ccprints("Error pwrbtn: RSMRST_L still low"); - - msleep(16); - } - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_pwr_btn_l), level); -} - -void baseboard_en_pwr_pcore_s0(enum gpio_signal signal) -{ - - /* EC must AND signals PG_LPDDR4X_S3_OD and PG_GROUPC_S0_OD */ - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r), - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr4x_s3_od)) && - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_groupc_s0_od))); -} - -void baseboard_en_pwr_s0(enum gpio_signal signal) -{ - - /* EC must AND signals SLP_S3_L and PG_PWR_S5 */ - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r), - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s3_l)) && - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5))); - - /* Now chain off to the normal power signal interrupt handler. */ - power_signal_interrupt(signal); -} - -void baseboard_s5_pgood(enum gpio_signal signal) -{ - baseboard_en_pwr_s0(signal); -} - -void baseboard_set_en_pwr_s3(enum gpio_signal signal) -{ - /* EC has no EN_PWR_S3 on this board */ - - /* Chain off the normal power signal interrupt handler */ - power_signal_interrupt(signal); -} diff --git a/zephyr/projects/skyrim/prj.conf b/zephyr/projects/skyrim/prj.conf index 47e9c1d096..135b5713e4 100644 --- a/zephyr/projects/skyrim/prj.conf +++ b/zephyr/projects/skyrim/prj.conf @@ -1,4 +1,4 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. @@ -28,7 +28,7 @@ CONFIG_PLATFORM_EC_PORT80=y CONFIG_PLATFORM_EC_POWER_BUTTON=y # ADC -CONFIG_PLATFORM_EC_ADC=y +CONFIG_ADC=y # I2C CONFIG_I2C=y @@ -41,6 +41,8 @@ CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y CONFIG_PLATFORM_EC_CBI_EEPROM=y # Temperature Sensors +CONFIG_PLATFORM_EC_AMD_SB_RMI=y +CONFIG_PLATFORM_EC_AMD_STT=y CONFIG_PLATFORM_EC_TEMP_SENSOR=y CONFIG_PLATFORM_EC_TEMP_SENSOR_SB_TSI=y CONFIG_PLATFORM_EC_THERMISTOR=y @@ -59,11 +61,6 @@ CONFIG_SENSOR_SHELL=n # Fan CONFIG_TACH_NPCX=y -# LEDs -CONFIG_PLATFORM_EC_LED_COMMON=y -CONFIG_PLATFORM_EC_LED_ONOFF_STATES=y -CONFIG_PLATFORM_EC_LED_PWM=y - # Lid switch CONFIG_PLATFORM_EC_LID_ANGLE=y CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y @@ -74,6 +71,8 @@ CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=y CONFIG_PLATFORM_EC_KEYBOARD=y CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y +CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y +CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y # PWM CONFIG_PWM=y @@ -133,7 +132,6 @@ CONFIG_GPIO_NCT38XX=y # Hibernate and wake CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=y -CONFIG_PLATFORM_EC_HIBERNATE_PSL=y # Motion sense CONFIG_PLATFORM_EC_MOTIONSENSE=y @@ -159,3 +157,13 @@ CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y # Misc. CONFIG_PLATFORM_EC_I2C_DEBUG=y CONFIG_PLATFORM_EC_PORT80_4_BYTE=y + +# These are debug options that happen to be expensive in terms of flash space. +# Turn on as needed based on demand. +CONFIG_FLASH_PAGE_LAYOUT=n # 1876 bytes +CONFIG_FLASH_SHELL=n # 1852 bytes +CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=n # 656 bytes +CONFIG_PLATFORM_EC_CONSOLE_CMD_MEM=n # 896 bytes +# CONFIG_PLATFORM_EC_CONSOLE_CMD_TCPC_DUMP=n # 1180 bytes +CONFIG_PLATFORM_EC_CONSOLE_CMD_USB_PD_CABLE=n # 1104 bytes +CONFIG_THREAD_MONITOR=n # 1548 bytes diff --git a/zephyr/projects/skyrim/prj_guybrush.conf b/zephyr/projects/skyrim/prj_guybrush.conf deleted file mode 100644 index 0ca57174a4..0000000000 --- a/zephyr/projects/skyrim/prj_guybrush.conf +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Guybrush board-specific Kconfig settings. -CONFIG_BOARD_GUYBRUSH=y - -# Only Guybrush has TMP112 -CONFIG_PLATFORM_EC_TEMP_SENSOR_TMP112=y
\ No newline at end of file diff --git a/zephyr/projects/skyrim/prj_morthal.conf b/zephyr/projects/skyrim/prj_morthal.conf new file mode 100644 index 0000000000..3d2b3fddb7 --- /dev/null +++ b/zephyr/projects/skyrim/prj_morthal.conf @@ -0,0 +1,23 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Morthal reference-board-specific Kconfig settings. +CONFIG_BOARD_MORTHAL=y + +# TODO(b/215404321): Remove later in board development +CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y +CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y + +# LED +CONFIG_PLATFORM_EC_LED_DT=y + +# Morthal is capable of sinking 100W +CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=100000 +CONFIG_PLATFORM_EC_PD_MAX_CURRENT_MA=5000 +CONFIG_PLATFORM_EC_PD_MAX_VOLTAGE_MV=20000 + +# Only Morthal has the PCT2075 +CONFIG_PLATFORM_EC_TEMP_SENSOR_PCT2075=y + +CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y diff --git a/zephyr/projects/skyrim/prj_skyrim.conf b/zephyr/projects/skyrim/prj_skyrim.conf index 2a524cf442..6a0ced86dd 100644 --- a/zephyr/projects/skyrim/prj_skyrim.conf +++ b/zephyr/projects/skyrim/prj_skyrim.conf @@ -1,4 +1,4 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. @@ -8,14 +8,20 @@ CONFIG_BOARD_SKYRIM=y # TODO(b/215404321): Remove later in board development CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y -CONFIG_PLATFORM_EC_KEYBOARD_DEBUG=y -CONFIG_PLATFORM_EC_POWERSEQ_FAKE_CONTROL=y # LED -CONFIG_PLATFORM_EC_LED_COMMON=n CONFIG_PLATFORM_EC_LED_DT=y +# Skyrim is capable of sinking 100W +CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=100000 +CONFIG_PLATFORM_EC_PD_MAX_CURRENT_MA=5000 +CONFIG_PLATFORM_EC_PD_MAX_VOLTAGE_MV=20000 + # Only Skyrim has the PCT2075 CONFIG_PLATFORM_EC_TEMP_SENSOR_PCT2075=y CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y + +# Enable alternative charger chip +CONFIG_PLATFORM_EC_CHARGER_RUNTIME_CONFIG=y +CONFIG_PLATFORM_EC_CHARGER_ISL9238C=y diff --git a/zephyr/projects/skyrim/prj_winterhold.conf b/zephyr/projects/skyrim/prj_winterhold.conf new file mode 100644 index 0000000000..3e6c967c6d --- /dev/null +++ b/zephyr/projects/skyrim/prj_winterhold.conf @@ -0,0 +1,18 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Winterhold reference-board-specific Kconfig settings. +CONFIG_BOARD_WINTERHOLD=y + +# TODO(b/215404321): Remove later in board development +CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y +CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y + +# LED +CONFIG_PLATFORM_EC_LED_DT=y + +# Only Winterhold has the PCT2075 +CONFIG_PLATFORM_EC_TEMP_SENSOR_PCT2075=y + +CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y diff --git a/zephyr/projects/skyrim/skyrim.dts b/zephyr/projects/skyrim/skyrim.dts index 8b4b5505ad..02308e4390 100644 --- a/zephyr/projects/skyrim/skyrim.dts +++ b/zephyr/projects/skyrim/skyrim.dts @@ -1,150 +1,32 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ -/ { - aliases { - gpio-wp = &gpio_wp; - gpio-cbi-wp = &gpio_cbi_wp; - gpio-kbd-kso2 = &gpio_ec_kso_02_inv; - }; +#include <dt-bindings/usbc_mux.h> + +#include "i2c_common.dtsi" +/ { named-gpios { /* Skyrim-specific GPIO customizations */ - usb_fault_odl { - gpios = <&gpio5 0 GPIO_ODR_HIGH>; - }; - gpio_en_pwr_s3: en_pwr_s3 { - gpios = <&gpio7 4 GPIO_OUTPUT_LOW>; - }; - gpio_pg_groupc_s0_od: pg_groupc_s0_od { - gpios = <&gpiof 0 GPIO_INPUT>; - }; - /* TODO: Add interrupt handler */ - ec_i2c_usbc_pd_int { - gpios = <&gpioa 3 GPIO_INPUT>; - }; - /* TODO: Add interrupt handler */ - soc_thermtrip_odl { - gpios = <&gpio9 5 GPIO_INPUT>; - }; - gpio_hub_rst: hub_rst { - gpios = <&gpio6 6 GPIO_OUTPUT_HIGH>; - }; - ec_soc_int_l { - gpios = <&gpioa 1 GPIO_OUTPUT_HIGH>; - enum-name = "GPIO_EC_INT_L"; - }; - gpio_ec_soc_pwr_good: ec_soc_pwr_good { - gpios = <&gpiod 3 GPIO_OUTPUT_LOW>; - }; - /* TODO: Add interrupt handler to shut down */ - pcore_ocp_r_l { - gpios = <&gpioa 5 GPIO_INPUT>; - }; - /* TODO: Add interrupt handler */ - sc_0_int_l { - gpios = <&gpio6 3 GPIO_INPUT_PULL_UP>; - }; - /* TODO: Add interrupt handler */ - usb_hub_fault_q_odl { - gpios = <&gpioe 5 GPIO_INPUT_PULL_UP>; - }; - gpio_pg_lpddr5_s3_od: pg_lpddr5_s3_od { - gpios = <&gpio7 3 GPIO_INPUT>; - }; - 3axis_int_l { - gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>; - }; - gpio_ec_soc_pwr_btn_l: ec_soc_pwr_btn_l { - gpios = <&gpioa 7 GPIO_OUTPUT_HIGH>; - enum-name = "GPIO_PCH_PWRBTN_L"; - }; - gpio_volup_btn_odl: volup_btn_odl { - gpios = <&gpio6 7 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_VOLUME_UP_L"; - }; - gpio_voldn_btn_odl: voldn_btn_odl { - gpios = <&gpio7 0 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_VOLUME_DOWN_L"; - }; - ec_sc_rst { - gpios = <&gpiob 0 GPIO_OUTPUT_LOW>; - }; - gpio_cbi_wp: ec_cbi_wp { - gpios = <&gpio8 1 GPIO_OUTPUT_LOW>; - }; - gpio_wp: ec_wp_l { - gpios = <&gpiod 7 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; - }; - gpio_pg_lpddr5_s0_od: pg_lpddr5_s0_od { - gpios = <&gpio6 0 GPIO_INPUT>; - }; - ec_espi_rst_l { - gpios = <&gpio5 4 GPIO_PULL_DOWN>; - }; - gpio_accel_gyro_int_l: accel_gyro_int_l { - gpios = <&gpioa 0 GPIO_INPUT>; - }; - }; - - def-lvol-io-list { - compatible = "nuvoton,npcx-lvolctrl-def"; - - /* - * Low voltage on I2C2_0, I2C6_1, I2C7_0, USB_FAUT_ODL - */ - lvol-io-pads = <&lvol_io92 &lvol_io91 &lvol_ioe4 &lvol_ioe3 - &lvol_iob3 &lvol_iob2 &lvol_io50>; }; named-temp-sensors { + compatible = "cros-ec,temp-sensors"; soc-pct2075 { - compatible = "cros-ec,temp-sensor-pct2075", - "cros-ec,temp-sensor"; - label = "SOC"; - enum-name = "TEMP_SENSOR_SOC"; - pct2075-name = "PCT2075_SOC"; - port = <&i2c_sensor>; - i2c-addr-flags = "PCT2075_I2C_ADDR_FLAGS0"; temp_host_high = <100>; temp_host_halt = <105>; temp_host_release_high = <80>; temp_host_release_halt = <80>; - temp_fan_off = <0>; + temp_fan_off = <35>; temp_fan_max = <70>; power-good-pin = <&gpio_pg_pwr_s5>; + sensor = <&soc_pct2075>; }; amb-pct2075 { - compatible = "cros-ec,temp-sensor-pct2075", - "cros-ec,temp-sensor"; - label = "Ambient"; - enum-name = "TEMP_SENSOR_AMB"; - pct2075-name = "PCT2075_AMB"; - port = <&i2c_sensor>; - i2c-addr-flags = "PCT2075_I2C_ADDR_FLAGS7"; power-good-pin = <&gpio_pg_pwr_s5>; - }; - }; - - gpio-interrupts { - compatible = "cros-ec,gpio-interrupts"; - - int_pg_lpddr_s3: pg_lpddr_s3 { - irq-pin = <&gpio_pg_lpddr5_s3_od>; - flags = <GPIO_INT_EDGE_BOTH>; - handler = "baseboard_set_en_pwr_pcore"; - }; - int_pg_lpddr_s0: pg_lpddr_s0 { - irq-pin = <&gpio_pg_lpddr5_s0_od>; - flags = <GPIO_INT_EDGE_BOTH>; - handler = "baseboard_set_soc_pwr_pgood"; - }; - int_s0_pgood: s0_pgood { - irq-pin = <&gpio_s0_pgood>; - flags = <GPIO_INT_EDGE_BOTH>; - handler = "baseboard_s0_pgood"; + sensor = <&amb_pct2075>; }; }; @@ -189,6 +71,49 @@ default; }; }; + + /* + * FW_CONFIG field to enable fan or not. + */ + fan { + enum-name = "FW_FAN"; + start = <10>; + size = <1>; + + no-fan { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_FAN_NOT_PRESENT"; + value = <0>; + }; + fan-present { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_FAN_PRESENT"; + value = <1>; + /* + * Set as default so that unprovisioned + * configs will run the fan regardless. + */ + default; + }; + }; + + charger-option { + enum-name = "FW_CHARGER"; + start = <11>; + size = <2>; + + charger-option-isl9241 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_CHARGER_ISL9241"; + value = <0>; + default; + }; + charger-option-isl9538 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_CHARGER_ISL9538"; + value = <1>; + }; + }; }; /* Rotation matrices for motion sensors. */ @@ -200,17 +125,78 @@ 0 0 1>; }; + lid_rot_ref1: lid-rotation-ref1 { + mat33 = <0 1 0 + (-1) 0 0 + 0 0 1>; + }; + base_rot_ref: base-rotation-ref { mat33 = <0 1 0 (-1) 0 0 0 0 1>; }; }; + + ppc_port0: aoz1380 { + compatible = "aoz,aoz1380"; + status = "okay"; + }; }; -/* host interface */ -&espi0 { - status = "okay"; - pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; - pinctrl-names = "default"; +&i2c0_0 { + anx7483_port0: anx7483@3e { + compatible = "analogix,anx7483"; + reg = <0x3e>; + board-set = "board_anx7483_c0_mux_set"; + }; +}; + +&i2c1_0 { + anx7483_port1: anx7483@3e { + compatible = "analogix,anx7483"; + reg = <0x3e>; + board-set = "board_anx7483_c1_mux_set"; + }; + ppc_port1: nx20p348x@71 { + compatible = "nxp,nx20p348x"; + status = "okay"; + reg = <0x71>; + }; + ps8818_port1: ps8818@28 { + compatible = "parade,ps8818"; + reg = <0x28>; + flags = <(USB_MUX_FLAG_RESETS_IN_G3)>; + board-set = "board_c1_ps8818_mux_set"; + }; +}; + +&i2c4_1 { + alt_charger: isl9538@9 { + compatible = "intersil,isl923x"; + status = "okay"; + reg = <0x9>; + }; +}; + +&usbc_port0 { + chg_alt = <&alt_charger>; + ppc = <&ppc_port0>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&amd_fp6_port0 &anx7483_port0>; + }; +}; + +&usbc_port1 { + ppc = <&ppc_port1>; + usb-mux-chain-1-anx { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&amd_fp6_port1 &anx7483_port1>; + }; + usb_mux_chain_ps8818_port1: usb-mux-chain-1-ps { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&amd_fp6_port1 &ps8818_port1>; + alternative-chain; + }; }; diff --git a/zephyr/projects/skyrim/src/common.c b/zephyr/projects/skyrim/src/common.c new file mode 100644 index 0000000000..af82139c1b --- /dev/null +++ b/zephyr/projects/skyrim/src/common.c @@ -0,0 +1,8 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/logging/log.h> + +LOG_MODULE_REGISTER(skyrim, CONFIG_SKYRIM_LOG_LEVEL); diff --git a/zephyr/projects/skyrim/src/morthal/ppc_config.c b/zephyr/projects/skyrim/src/morthal/ppc_config.c new file mode 100644 index 0000000000..f3ec1d312e --- /dev/null +++ b/zephyr/projects/skyrim/src/morthal/ppc_config.c @@ -0,0 +1,46 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Morthal board-specific PPC code */ + +#include <zephyr/drivers/gpio.h> + +#include "driver/ppc/nx20p348x.h" +#include "driver/ppc/aoz1380_public.h" +#include "usbc_ppc.h" + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +/* + * In the AOZ1380 PPC, there are no programmable features. We use + * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0 + * current limits. + */ +int board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp) +{ + int rv = EC_SUCCESS; + + rv = gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(ioex_usb_c0_ilim_3a_en), + (rp == TYPEC_RP_3A0) ? 1 : 0); + + return rv; +} + +void ppc_interrupt(enum gpio_signal signal) +{ + switch (signal) { + case GPIO_USB_C0_PPC_INT_ODL: + aoz1380_interrupt(0); + break; + + case GPIO_USB_C1_PPC_INT_ODL: + nx20p348x_interrupt(1); + break; + + default: + break; + } +} diff --git a/zephyr/projects/skyrim/src/morthal/usb_mux_config.c b/zephyr/projects/skyrim/src/morthal/usb_mux_config.c new file mode 100644 index 0000000000..8fe76233e2 --- /dev/null +++ b/zephyr/projects/skyrim/src/morthal/usb_mux_config.c @@ -0,0 +1,142 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Morthal board-specific USB-C mux configuration */ + +#include <zephyr/drivers/gpio.h> + +#include "console.h" +#include "cros_board_info.h" +#include "cros_cbi.h" +#include "driver/retimer/anx7483_public.h" +#include "hooks.h" +#include "ioexpander.h" +#include "usb_mux.h" +#include "usbc/usb_muxes.h" + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +/* + * USB C0 (general) and C1 (just ANX DB) use IOEX pins to + * indicate flipped polarity to a protection switch. + */ +static int ioex_set_flip(int port, mux_state_t mux_state) +{ + if (port == 0) { + if (mux_state & USB_PD_MUX_POLARITY_INVERTED) + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip), + 1); + else + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip), + 0); + } else { + if (mux_state & USB_PD_MUX_POLARITY_INVERTED) + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip), + 1); + else + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip), + 0); + } + + return EC_SUCCESS; +} + +int board_anx7483_c0_mux_set(const struct usb_mux *me, mux_state_t mux_state) +{ + /* Set the SBU polarity mux */ + RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state)); + + return anx7483_set_default_tuning(me, mux_state); +} + +int board_anx7483_c1_mux_set(const struct usb_mux *me, mux_state_t mux_state) +{ + bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED; + + /* Set the SBU polarity mux */ + RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state)); + + /* Remove flipped from the state for easier compraisons */ + mux_state = mux_state & ~USB_PD_MUX_POLARITY_INVERTED; + + RETURN_ERROR(anx7483_set_default_tuning(me, mux_state)); + + if (mux_state == USB_PD_MUX_USB_ENABLED) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DP_ENABLED) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DOCK && !flipped) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DOCK && flipped) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2, + ANX7483_EQ_SETTING_12_5DB)); + } + + return EC_SUCCESS; +} + +int board_c1_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state) +{ + CPRINTSUSB("C1: PS8818 mux using default tuning"); + + /* Once a DP connection is established, we need to set IN_HPD */ + if (mux_state & USB_PD_MUX_DP_ENABLED) + ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 1); + else + ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 0); + + return 0; +} + +static void setup_mux(void) +{ + uint32_t val; + + if (cros_cbi_get_fw_config(FW_IO_DB, &val) != 0) + CPRINTSUSB("Error finding FW_DB_IO in CBI FW_CONFIG"); + /* Val will have our dts default on error, so continue setup */ + + if (val == FW_IO_DB_PS8811_PS8818) { + CPRINTSUSB("C1: Setting PS8818 mux"); + USB_MUX_ENABLE_ALTERNATIVE(usb_mux_chain_ps8818_port1); + } else if (val == FW_IO_DB_NONE_ANX7483) { + CPRINTSUSB("C1: Setting ANX7483 mux"); + } else { + CPRINTSUSB("Unexpected DB_IO board: %d", val); + } +} +DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C); diff --git a/zephyr/projects/skyrim/power_signals.c b/zephyr/projects/skyrim/src/power_signals.c index e85cea1f04..3c56e51ddc 100644 --- a/zephyr/projects/skyrim/power_signals.c +++ b/zephyr/projects/skyrim/src/power_signals.c @@ -1,16 +1,20 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ #include "ap_power/ap_power.h" +#include "charger.h" #include "chipset.h" #include "config.h" +#include "cros_board_info.h" #include "gpio_signal.h" #include "gpio/gpio_int.h" #include "hooks.h" +#include "i2c.h" #include "ioexpander.h" #include "power.h" +#include "power/amd_x86.h" #include "timer.h" /* Power Signal Input List */ @@ -49,15 +53,15 @@ static void baseboard_suspend_change(struct ap_power_ev_callback *cb, case AP_POWER_SUSPEND: /* Disable display backlight and retimer */ - gpio_pin_set_dt( - GPIO_DT_FROM_NODELABEL(gpio_ec_disable_disp_bl), 1); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_disable_disp_bl), + 1); ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0); break; case AP_POWER_RESUME: /* Enable retimer and display backlight */ - gpio_pin_set_dt( - GPIO_DT_FROM_NODELABEL(gpio_ec_disable_disp_bl), 0); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_disable_disp_bl), + 0); ioex_set_level(IOEX_USB_A1_RETIMER_EN, 1); /* Any retimer tuning can be done after the retimer turns on */ break; @@ -76,6 +80,9 @@ static void baseboard_init(void) gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_groupc_s0)); gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_lpddr_s0)); gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_lpddr_s3)); + + /* Enable thermtrip interrupt */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_soc_thermtrip)); } DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_POST_I2C); @@ -84,7 +91,7 @@ DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_POST_I2C); * PCH_PWRBTN_L. This can be as long as ~65ms after cold boot. Then wait an * additional delay of T1a defined in the EDS before changing the power button. */ -#define RSMRST_WAIT_DELAY 70 +#define RSMRST_WAIT_DELAY 70 #define EDS_PWR_BTN_RSMRST_T1A_DELAY 16 void board_pwrbtn_to_pch(int level) { @@ -96,13 +103,13 @@ void board_pwrbtn_to_pch(int level) start = get_time(); do { usleep(500); - if (gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l))) + if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( + gpio_ec_soc_rsmrst_l))) break; } while (time_since32(start) < (RSMRST_WAIT_DELAY * MSEC)); if (!gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l))) + GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l))) ccprints("Error pwrbtn: RSMRST_L still low"); msleep(EDS_PWR_BTN_RSMRST_T1A_DELAY); @@ -113,11 +120,34 @@ void board_pwrbtn_to_pch(int level) /* Note: signal parameter unused */ void baseboard_set_soc_pwr_pgood(enum gpio_signal unused) { - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_pwr_good), - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r)) && - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr5_s0_od)) && - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_s0_pgood))); + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_ec_soc_pwr_good), + gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r)) && + gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr5_s0_od)) && + gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_s0_pgood))); +} + +/* TODO: Remove when board versions are no longer supported */ +#define MP2845A_I2C_ADDR_FLAGS 0x20 +#define MP2854A_MFR_VOUT_CMPS_MAX_REG 0x69 +#define MP2854A_MFR_LOW_PWR_SEL BIT(12) + +static void setup_mp2845(void) +{ + int version; + + /* TODO: Remove when board versions are no longer supported */ + if ((cbi_get_board_version(&version) == EC_SUCCESS) && version > 3) + return; + + if (i2c_update16(chg_chips[CHARGER_SOLO].i2c_port, + MP2845A_I2C_ADDR_FLAGS, MP2854A_MFR_VOUT_CMPS_MAX_REG, + MP2854A_MFR_LOW_PWR_SEL, MASK_CLR)) + ccprints("Failed to send mp2845 workaround"); } +DECLARE_DEFERRED(setup_mp2845); void baseboard_s0_pgood(enum gpio_signal signal) { @@ -125,6 +155,10 @@ void baseboard_s0_pgood(enum gpio_signal signal) /* Chain off power signal interrupt handler for PG_PCORE_S0_R_OD */ power_signal_interrupt(signal); + + /* Set up the MP2845, which is powered in S0 */ + if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_s0_pgood))) + hook_call_deferred(&setup_mp2845_data, 50 * MSEC); } /* Note: signal parameter unused */ @@ -134,10 +168,13 @@ void baseboard_set_en_pwr_pcore(enum gpio_signal unused) * EC must AND signals PG_LPDDR5_S3_OD, PG_GROUPC_S0_OD, and * EN_PWR_S0_R */ - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r), - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr5_s3_od)) && - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_groupc_s0_od)) && - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r))); + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r), + gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr5_s3_od)) && + gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_pg_groupc_s0_od)) && + gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r))); /* Update EC_SOC_PWR_GOOD based on our results */ baseboard_set_soc_pwr_pgood(unused); @@ -146,9 +183,11 @@ void baseboard_set_en_pwr_pcore(enum gpio_signal unused) void baseboard_en_pwr_s0(enum gpio_signal signal) { /* EC must AND signals SLP_S3_L and PG_PWR_S5 */ - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r), - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s3_l)) && - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5))); + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r), + gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s3_l)) && + gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5))); /* Change EN_PWR_PCORE_S0_R if needed*/ baseboard_set_en_pwr_pcore(signal); @@ -179,8 +218,14 @@ void baseboard_set_en_pwr_s3(enum gpio_signal signal) { /* EC must enable PWR_S3 when SLP_S5_L goes high, disable on low */ gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s3), - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s5_l))); + gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s5_l))); /* Chain off the normal power signal interrupt handler */ power_signal_interrupt(signal); } + +void baseboard_soc_thermtrip(enum gpio_signal signal) +{ + ccprints("SoC thermtrip reported, shutting down"); + chipset_force_shutdown(CHIPSET_SHUTDOWN_THERMAL); +} diff --git a/zephyr/projects/skyrim/src/skyrim/alt_charger.c b/zephyr/projects/skyrim/src/skyrim/alt_charger.c new file mode 100644 index 0000000000..4b717901cd --- /dev/null +++ b/zephyr/projects/skyrim/src/skyrim/alt_charger.c @@ -0,0 +1,31 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/devicetree.h> +#include <zephyr/logging/log.h> + +#include "charger_chips.h" +#include "common.h" +#include "cros_board_info.h" +#include "cros_cbi.h" +#include "hooks.h" + +LOG_MODULE_DECLARE(skyrim, CONFIG_SKYRIM_LOG_LEVEL); + +static void alt_charger_init(void) +{ + int ret; + uint32_t val; + + ret = cros_cbi_get_fw_config(FW_CHARGER, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_CHARGER); + return; + } + + if (val == FW_CHARGER_ISL9538) + CHG_ENABLE_ALTERNATE(0); +} +DECLARE_HOOK(HOOK_INIT, alt_charger_init, HOOK_PRIO_POST_FIRST); diff --git a/zephyr/projects/skyrim/src/skyrim/fan.c b/zephyr/projects/skyrim/src/skyrim/fan.c new file mode 100644 index 0000000000..70d512bb78 --- /dev/null +++ b/zephyr/projects/skyrim/src/skyrim/fan.c @@ -0,0 +1,46 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/devicetree.h> +#include <zephyr/drivers/gpio.h> +#include <zephyr/logging/log.h> + +#include "cros_board_info.h" +#include "cros_cbi.h" +#include "fan.h" +#include "gpio/gpio.h" +#include "hooks.h" + +LOG_MODULE_DECLARE(skyrim, CONFIG_SKYRIM_LOG_LEVEL); + +/* + * Skyrim fan support + */ +static void fan_init(void) +{ + int ret; + uint32_t val; + uint32_t board_version; + /* + * Retrieve the fan config. + */ + ret = cros_cbi_get_fw_config(FW_FAN, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN); + return; + } + + ret = cbi_get_board_version(&board_version); + if (ret != EC_SUCCESS) { + LOG_ERR("Error retrieving CBI board version"); + return; + } + + if ((board_version >= 3) && (val != FW_FAN_PRESENT)) { + /* Disable the fan */ + fan_set_count(0); + } +} +DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST); diff --git a/zephyr/projects/skyrim/src/skyrim/form_factor.c b/zephyr/projects/skyrim/src/skyrim/form_factor.c new file mode 100644 index 0000000000..f137c6db31 --- /dev/null +++ b/zephyr/projects/skyrim/src/skyrim/form_factor.c @@ -0,0 +1,37 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/devicetree.h> +#include <zephyr/logging/log.h> +#include "common.h" +#include "accelgyro.h" +#include "cros_board_info.h" +#include "hooks.h" +#include "motionsense_sensors.h" + +LOG_MODULE_DECLARE(skyrim, CONFIG_SKYRIM_LOG_LEVEL); + +/* + * Mainboard orientation support. + */ + +#define ALT_MAT SENSOR_ROT_STD_REF_NAME(DT_NODELABEL(lid_rot_ref1)) +#define LID_ACCEL SENSOR_ID(DT_NODELABEL(lid_accel)) + +static void form_factor_init(void) +{ + int ret; + uint32_t val; + /* + * If the board version >=4 + * use ver1 rotation matrix. + */ + ret = cbi_get_board_version(&val); + if (ret == EC_SUCCESS && val >= 4) { + LOG_INF("Switching to ver1 lid"); + motion_sensors[LID_ACCEL].rot_standard_ref = &ALT_MAT; + } +} +DECLARE_HOOK(HOOK_INIT, form_factor_init, HOOK_PRIO_POST_I2C); diff --git a/zephyr/projects/skyrim/src/skyrim/ppc_config.c b/zephyr/projects/skyrim/src/skyrim/ppc_config.c new file mode 100644 index 0000000000..bebc8adcc7 --- /dev/null +++ b/zephyr/projects/skyrim/src/skyrim/ppc_config.c @@ -0,0 +1,46 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Skyrim board-specific PPC code */ + +#include <zephyr/drivers/gpio.h> + +#include "driver/ppc/nx20p348x.h" +#include "driver/ppc/aoz1380_public.h" +#include "usbc_ppc.h" + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +/* + * In the AOZ1380 PPC, there are no programmable features. We use + * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0 + * current limits. + */ +int board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp) +{ + int rv = EC_SUCCESS; + + rv = gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(ioex_usb_c0_ilim_3a_en), + (rp == TYPEC_RP_3A0) ? 1 : 0); + + return rv; +} + +void ppc_interrupt(enum gpio_signal signal) +{ + switch (signal) { + case GPIO_USB_C0_PPC_INT_ODL: + aoz1380_interrupt(0); + break; + + case GPIO_USB_C1_PPC_INT_ODL: + nx20p348x_interrupt(1); + break; + + default: + break; + } +} diff --git a/zephyr/projects/skyrim/src/skyrim/usb_mux_config.c b/zephyr/projects/skyrim/src/skyrim/usb_mux_config.c new file mode 100644 index 0000000000..6c65e56d9e --- /dev/null +++ b/zephyr/projects/skyrim/src/skyrim/usb_mux_config.c @@ -0,0 +1,142 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Skyrim board-specific USB-C mux configuration */ + +#include <zephyr/drivers/gpio.h> + +#include "console.h" +#include "cros_board_info.h" +#include "cros_cbi.h" +#include "driver/retimer/anx7483_public.h" +#include "hooks.h" +#include "ioexpander.h" +#include "usb_mux.h" +#include "usbc/usb_muxes.h" + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +/* + * USB C0 (general) and C1 (just ANX DB) use IOEX pins to + * indicate flipped polarity to a protection switch. + */ +static int ioex_set_flip(int port, mux_state_t mux_state) +{ + if (port == 0) { + if (mux_state & USB_PD_MUX_POLARITY_INVERTED) + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip), + 1); + else + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip), + 0); + } else { + if (mux_state & USB_PD_MUX_POLARITY_INVERTED) + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip), + 1); + else + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip), + 0); + } + + return EC_SUCCESS; +} + +int board_anx7483_c0_mux_set(const struct usb_mux *me, mux_state_t mux_state) +{ + /* Set the SBU polarity mux */ + RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state)); + + return anx7483_set_default_tuning(me, mux_state); +} + +int board_anx7483_c1_mux_set(const struct usb_mux *me, mux_state_t mux_state) +{ + bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED; + + /* Set the SBU polarity mux */ + RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state)); + + /* Remove flipped from the state for easier compraisons */ + mux_state = mux_state & ~USB_PD_MUX_POLARITY_INVERTED; + + RETURN_ERROR(anx7483_set_default_tuning(me, mux_state)); + + if (mux_state == USB_PD_MUX_USB_ENABLED) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DP_ENABLED) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DOCK && !flipped) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DOCK && flipped) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2, + ANX7483_EQ_SETTING_12_5DB)); + } + + return EC_SUCCESS; +} + +int board_c1_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state) +{ + CPRINTSUSB("C1: PS8818 mux using default tuning"); + + /* Once a DP connection is established, we need to set IN_HPD */ + if (mux_state & USB_PD_MUX_DP_ENABLED) + ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 1); + else + ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 0); + + return 0; +} + +static void setup_mux(void) +{ + uint32_t val; + + if (cros_cbi_get_fw_config(FW_IO_DB, &val) != 0) + CPRINTSUSB("Error finding FW_DB_IO in CBI FW_CONFIG"); + /* Val will have our dts default on error, so continue setup */ + + if (val == FW_IO_DB_PS8811_PS8818) { + CPRINTSUSB("C1: Setting PS8818 mux"); + USB_MUX_ENABLE_ALTERNATIVE(usb_mux_chain_ps8818_port1); + } else if (val == FW_IO_DB_NONE_ANX7483) { + CPRINTSUSB("C1: Setting ANX7483 mux"); + } else { + CPRINTSUSB("Unexpected DB_IO board: %d", val); + } +} +DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C); diff --git a/zephyr/projects/skyrim/src/stt.c b/zephyr/projects/skyrim/src/stt.c new file mode 100644 index 0000000000..40743fbc68 --- /dev/null +++ b/zephyr/projects/skyrim/src/stt.c @@ -0,0 +1,28 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Support code for STT temperature reporting */ + +#include "chipset.h" +#include "temp_sensor/pct2075.h" +#include "temp_sensor/temp_sensor.h" + +int board_get_soc_temp_mk(int *temp_mk) +{ + if (chipset_in_state(CHIPSET_STATE_HARD_OFF)) + return EC_ERROR_NOT_POWERED; + + return pct2075_get_val_mk(PCT2075_SENSOR_ID(DT_NODELABEL(soc_pct2075)), + temp_mk); +} + +int board_get_ambient_temp_mk(int *temp_mk) +{ + if (chipset_in_state(CHIPSET_STATE_HARD_OFF)) + return EC_ERROR_NOT_POWERED; + + return pct2075_get_val_mk(PCT2075_SENSOR_ID(DT_NODELABEL(amb_pct2075)), + temp_mk); +} diff --git a/zephyr/projects/skyrim/usb_pd_policy.c b/zephyr/projects/skyrim/src/usb_pd_policy.c index 1d6457278a..ec9f873863 100644 --- a/zephyr/projects/skyrim/usb_pd_policy.c +++ b/zephyr/projects/skyrim/src/usb_pd_policy.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/zephyr/projects/skyrim/usbc_config.c b/zephyr/projects/skyrim/src/usbc_config.c index fe60db2a69..0ca421deca 100644 --- a/zephyr/projects/skyrim/usbc_config.c +++ b/zephyr/projects/skyrim/src/usbc_config.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,11 +17,10 @@ #include "charger.h" #include "driver/bc12/pi3usb9201.h" #include "driver/charger/isl9241.h" -#include "driver/ppc/aoz1380.h" #include "driver/ppc/nx20p348x.h" #include "driver/retimer/anx7483_public.h" #include "driver/retimer/ps8811.h" -#include "driver/retimer/ps8818.h" +#include "driver/retimer/ps8818_public.h" #include "driver/tcpm/nct38xx.h" #include "driver/usb_mux/amd_fp6.h" #include "gpio/gpio_int.h" @@ -31,23 +30,16 @@ #include "usb_mux.h" #include "usb_pd_tcpm.h" #include "usbc_ppc.h" +#include "usbc/usb_muxes.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* USB-A ports */ -enum usba_port { - USBA_PORT_A0 = 0, - USBA_PORT_A1, - USBA_PORT_COUNT -}; +enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT }; /* USB-C ports */ -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT); static void reset_nct38xx_port(int port); @@ -66,215 +58,34 @@ static void usbc_interrupt_init(void) gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_bc12)); gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_bc12)); - /* TODO: Enable SBU fault interrupts (io expander )*/ + /* Enable SBU fault interrupts */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_sbu_fault)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_sbu_fault)); } DECLARE_HOOK(HOOK_INIT, usbc_interrupt_init, HOOK_PRIO_POST_I2C); -struct ppc_config_t ppc_chips[] = { - [USBC_PORT_C0] = { - /* Device does not talk I2C */ - .drv = &aoz1380_drv - }, - - [USBC_PORT_C1] = { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = NX20P3483_ADDR1_FLAGS, - .drv = &nx20p348x_drv - }, -}; -BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == CONFIG_USB_PD_PORT_MAX_COUNT); -unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); - -/* - * .init is not necessary here because it has nothing - * to do. Primary mux will handle mux state so .get is - * not needed as well. usb_mux.c can handle the situation - * properly. - */ -static int ioex_set_flip(const struct usb_mux*, mux_state_t, bool *); -struct usb_mux_driver ioex_sbu_mux_driver = { - .set = ioex_set_flip, -}; - -/* - * Since NX3DV221GM is not a i2c device, .i2c_port and - * .i2c_addr_flags are not required here. - */ -struct usb_mux usbc0_sbu_mux = { - .usb_port = USBC_PORT_C0, - .driver = &ioex_sbu_mux_driver, -}; - -struct usb_mux usbc1_sbu_mux = { - .usb_port = USBC_PORT_C1, - .driver = &ioex_sbu_mux_driver, -}; - -int baseboard_anx7483_c0_mux_set(const struct usb_mux *me, - mux_state_t mux_state) -{ - return anx7483_set_default_tuning(me, mux_state); -} - -int baseboard_anx7483_c1_mux_set(const struct usb_mux *me, - mux_state_t mux_state) -{ - bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED; - - /* Remove flipped from the state for easier compraisons */ - mux_state = mux_state & ~USB_PD_MUX_POLARITY_INVERTED; - - RETURN_ERROR(anx7483_set_default_tuning(me, mux_state)); - - if (mux_state == USB_PD_MUX_USB_ENABLED) { - RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, - ANX7483_EQ_SETTING_12_5DB)); - RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, - ANX7483_EQ_SETTING_12_5DB)); - RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1, - ANX7483_EQ_SETTING_12_5DB)); - RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2, - ANX7483_EQ_SETTING_12_5DB)); - } else if (mux_state == USB_PD_MUX_DP_ENABLED) { - RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, - ANX7483_EQ_SETTING_12_5DB)); - RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, - ANX7483_EQ_SETTING_12_5DB)); - RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1, - ANX7483_EQ_SETTING_12_5DB)); - RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2, - ANX7483_EQ_SETTING_12_5DB)); - } else if (mux_state == USB_PD_MUX_DOCK && !flipped) { - RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, - ANX7483_EQ_SETTING_12_5DB)); - RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, - ANX7483_EQ_SETTING_12_5DB)); - RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1, - ANX7483_EQ_SETTING_12_5DB)); - RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2, - ANX7483_EQ_SETTING_12_5DB)); - } else if (mux_state == USB_PD_MUX_DOCK && flipped) { - RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, - ANX7483_EQ_SETTING_12_5DB)); - RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, - ANX7483_EQ_SETTING_12_5DB)); - RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1, - ANX7483_EQ_SETTING_12_5DB)); - RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2, - ANX7483_EQ_SETTING_12_5DB)); - } - - return EC_SUCCESS; -} - -struct usb_mux usbc0_anx7483 = { - .usb_port = USBC_PORT_C0, - .i2c_port = I2C_PORT_TCPC0, - .i2c_addr_flags = ANX7483_I2C_ADDR0_FLAGS, - .driver = &anx7483_usb_retimer_driver, - .board_set = &baseboard_anx7483_c0_mux_set, - .next_mux = &usbc0_sbu_mux, -}; - -__overridable int board_c1_ps8818_mux_set(const struct usb_mux *me, - mux_state_t mux_state) +static void usb_fault_interrupt_init(void) { - CPRINTSUSB("C1: PS8818 mux using default tuning"); - - /* Once a DP connection is established, we need to set IN_HPD */ - if (mux_state & USB_PD_MUX_DP_ENABLED) - ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 1); - else - ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 0); - - return 0; -} - -struct usb_mux usbc1_ps8818 = { - .usb_port = USBC_PORT_C1, - .i2c_port = I2C_PORT_TCPC1, - .flags = USB_MUX_FLAG_RESETS_IN_G3, - .i2c_addr_flags = PS8818_I2C_ADDR_FLAGS, - .driver = &ps8818_usb_retimer_driver, - .board_set = &board_c1_ps8818_mux_set, -}; - -struct usb_mux usbc1_anx7483 = { - .usb_port = USBC_PORT_C1, - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = ANX7483_I2C_ADDR0_FLAGS, - .driver = &anx7483_usb_retimer_driver, - .board_set = &baseboard_anx7483_c1_mux_set, - .next_mux = &usbc1_sbu_mux, -}; - -struct usb_mux usb_muxes[] = { - [USBC_PORT_C0] = { - .usb_port = USBC_PORT_C0, - .i2c_port = I2C_PORT_USB_MUX, - .i2c_addr_flags = AMD_FP6_C0_MUX_I2C_ADDR, - .driver = &amd_fp6_usb_mux_driver, - .next_mux = &usbc0_anx7483, - }, - [USBC_PORT_C1] = { - .usb_port = USBC_PORT_C1, - .i2c_port = I2C_PORT_USB_MUX, - .i2c_addr_flags = AMD_FP6_C4_MUX_I2C_ADDR, - .driver = &amd_fp6_usb_mux_driver, - /* .next_mux = filled in by setup_mux based on fw_config */ - } -}; -BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT); - -/* - * USB C0 (general) and C1 (just ANX DB) use IOEX pins to - * indicate flipped polarity to a protection switch. - */ -static int ioex_set_flip(const struct usb_mux *me, mux_state_t mux_state, - bool *ack_required) -{ - /* This driver does not use host command ACKs */ - *ack_required = false; - - if (me->usb_port == USBC_PORT_C0) { - if (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ioex_set_level(IOEX_USB_C0_SBU_FLIP, 1); - else - ioex_set_level(IOEX_USB_C0_SBU_FLIP, 0); - } else { - if (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ioex_set_level(IOEX_USB_C1_SBU_FLIP, 1); - else - ioex_set_level(IOEX_USB_C1_SBU_FLIP, 0); - } - - return EC_SUCCESS; + /* Enable USB fault interrupts when we hit S5 */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_hub_fault)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_a0_fault)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_a1_fault)); } +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, usb_fault_interrupt_init, HOOK_PRIO_DEFAULT); -static void setup_mux(void) +static void usb_fault_interrupt_disable(void) { - uint32_t val; - - if (cros_cbi_get_fw_config(FW_IO_DB, &val) != 0) - CPRINTSUSB("Error finding FW_DB_IO in CBI FW_CONFIG"); - /* Val will have our dts default on error, so continue setup */ - - if (val == FW_IO_DB_PS8811_PS8818) { - CPRINTSUSB("C1: Setting PS8818 mux"); - usb_muxes[USBC_PORT_C1].next_mux = &usbc1_ps8818; - } else if (val == FW_IO_DB_NONE_ANX7483) { - CPRINTSUSB("C1: Setting ANX7483 mux"); - usb_muxes[USBC_PORT_C1].next_mux = &usbc1_anx7483; - } else { - CPRINTSUSB("Unexpected DB_IO board: %d", val); - } + /* Disable USB fault interrupts leaving S5 */ + gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_hub_fault)); + gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_a0_fault)); + gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_a1_fault)); } -DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C); +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, usb_fault_interrupt_disable, + HOOK_PRIO_DEFAULT); int board_set_active_charge_port(int port) { - int is_valid_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; int rv; @@ -288,7 +99,7 @@ int board_set_active_charge_port(int port) * ahead and reset it so EN_SNK responds properly. */ if (nct38xx_get_boot_type(i) == - NCT38XX_BOOT_DEAD_BATTERY) { + NCT38XX_BOOT_DEAD_BATTERY) { reset_nct38xx_port(i); pd_set_error_recovery(i); } @@ -337,7 +148,7 @@ int board_set_active_charge_port(int port) * change because we'll brown out. */ if (nct38xx_get_boot_type(port) == - NCT38XX_BOOT_DEAD_BATTERY) { + NCT38XX_BOOT_DEAD_BATTERY) { reset_nct38xx_port(i); pd_set_error_recovery(i); } else { @@ -379,31 +190,42 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -/* - * In the AOZ1380 PPC, there are no programmable features. We use - * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0 - * current limits. - */ -int board_aoz1380_set_vbus_source_current_limit(int port, - enum tcpc_rp_value rp) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { - int rv = EC_SUCCESS; + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); +} - rv = ioex_set_level(IOEX_USB_C0_PPC_ILIM_3A_EN, - (rp == TYPEC_RP_3A0) ? 1 : 0); +void sbu_fault_interrupt(enum gpio_signal signal) +{ + int port = signal == IOEX_USB_C1_FAULT_ODL ? 1 : 0; - return rv; + CPRINTSUSB("C%d: SBU fault", port); + pd_handle_overcurrent(port); } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void usb_fault_interrupt(enum gpio_signal signal) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + int out; + + CPRINTSUSB("USB fault(%d), alerting the SoC", signal); + out = gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_usb_hub_fault_q_odl)) && + gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(ioex_usb_a0_fault_odl)) && + gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(ioex_usb_a1_fault_db_odl)); + + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_fault_odl), out); } -/* TODO: sbu_fault_interrupt from io expander */ +void usb_pd_soc_interrupt(enum gpio_signal signal) +{ + /* + * This interrupt is unexpected with our use of the SoC mux, so just log + * it as a point of interest. + */ + CPRINTSUSB("SOC PD Interrupt"); +} /* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */ #define SKYRIM_AC_PROCHOT_CURRENT_MA 3328 @@ -462,7 +284,6 @@ static void reset_nct38xx_port(int port) gpio_reset_port(ioex_port1); } - void board_reset_pd_mcu(void) { /* Reset TCPC0 */ @@ -481,38 +302,22 @@ uint16_t tcpc_get_alert_status(void) * its reset line active. */ if (!gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_int_odl))) { - if (gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_rst_l)) != 0) + GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_int_odl))) { + if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( + gpio_usb_c0_tcpc_rst_l)) != 0) status |= PD_STATUS_TCPC_ALERT_0; } if (!gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_int_odl))) { - if (gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_rst_l)) != 0) + GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_int_odl))) { + if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( + gpio_usb_c1_tcpc_rst_l)) != 0) status |= PD_STATUS_TCPC_ALERT_1; } return status; } -void ppc_interrupt(enum gpio_signal signal) -{ - switch (signal) { - case GPIO_USB_C0_PPC_INT_ODL: - aoz1380_interrupt(USBC_PORT_C0); - break; - - case GPIO_USB_C1_PPC_INT_ODL: - nx20p348x_interrupt(USBC_PORT_C1); - break; - - default: - break; - } -} - void bc12_interrupt(enum gpio_signal signal) { switch (signal) { diff --git a/zephyr/projects/skyrim/src/winterhold/ppc_config.c b/zephyr/projects/skyrim/src/winterhold/ppc_config.c new file mode 100644 index 0000000000..72ddb6ce6c --- /dev/null +++ b/zephyr/projects/skyrim/src/winterhold/ppc_config.c @@ -0,0 +1,27 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Winterhold board-specific PPC code */ + +#include <zephyr/drivers/gpio.h> + +#include "driver/ppc/nx20p348x.h" +#include "usbc_ppc.h" + +void ppc_interrupt(enum gpio_signal signal) +{ + switch (signal) { + case GPIO_USB_C0_PPC_INT_ODL: + nx20p348x_interrupt(0); + break; + + case GPIO_USB_C1_PPC_INT_ODL: + nx20p348x_interrupt(1); + break; + + default: + break; + } +} diff --git a/zephyr/projects/skyrim/src/winterhold/usb_mux_config.c b/zephyr/projects/skyrim/src/winterhold/usb_mux_config.c new file mode 100644 index 0000000000..ca7b604d10 --- /dev/null +++ b/zephyr/projects/skyrim/src/winterhold/usb_mux_config.c @@ -0,0 +1,142 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Winterhold board-specific USB-C mux configuration */ + +#include <zephyr/drivers/gpio.h> + +#include "console.h" +#include "cros_board_info.h" +#include "cros_cbi.h" +#include "driver/retimer/anx7483_public.h" +#include "hooks.h" +#include "ioexpander.h" +#include "usb_mux.h" +#include "usbc/usb_muxes.h" + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +/* + * USB C0 (general) and C1 (just ANX DB) use IOEX pins to + * indicate flipped polarity to a protection switch. + */ +static int ioex_set_flip(int port, mux_state_t mux_state) +{ + if (port == 0) { + if (mux_state & USB_PD_MUX_POLARITY_INVERTED) + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip), + 1); + else + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip), + 0); + } else { + if (mux_state & USB_PD_MUX_POLARITY_INVERTED) + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip), + 1); + else + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip), + 0); + } + + return EC_SUCCESS; +} + +int board_anx7483_c0_mux_set(const struct usb_mux *me, mux_state_t mux_state) +{ + /* Set the SBU polarity mux */ + RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state)); + + return anx7483_set_default_tuning(me, mux_state); +} + +int board_anx7483_c1_mux_set(const struct usb_mux *me, mux_state_t mux_state) +{ + bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED; + + /* Set the SBU polarity mux */ + RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state)); + + /* Remove flipped from the state for easier compraisons */ + mux_state = mux_state & ~USB_PD_MUX_POLARITY_INVERTED; + + RETURN_ERROR(anx7483_set_default_tuning(me, mux_state)); + + if (mux_state == USB_PD_MUX_USB_ENABLED) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DP_ENABLED) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DOCK && !flipped) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DOCK && flipped) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2, + ANX7483_EQ_SETTING_12_5DB)); + } + + return EC_SUCCESS; +} + +int board_c1_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state) +{ + CPRINTSUSB("C1: PS8818 mux using default tuning"); + + /* Once a DP connection is established, we need to set IN_HPD */ + if (mux_state & USB_PD_MUX_DP_ENABLED) + ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 1); + else + ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 0); + + return 0; +} + +static void setup_mux(void) +{ + uint32_t val; + + if (cros_cbi_get_fw_config(FW_IO_DB, &val) != 0) + CPRINTSUSB("Error finding FW_DB_IO in CBI FW_CONFIG"); + /* Val will have our dts default on error, so continue setup */ + + if (val == FW_IO_DB_PS8811_PS8818) { + CPRINTSUSB("C1: Setting PS8818 mux"); + USB_MUX_ENABLE_ALTERNATIVE(usb_mux_chain_ps8818_port1); + } else if (val == FW_IO_DB_NONE_ANX7483) { + CPRINTSUSB("C1: Setting ANX7483 mux"); + } else { + CPRINTSUSB("Unexpected DB_IO board: %d", val); + } +} +DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C); diff --git a/zephyr/projects/skyrim/usbc.dts b/zephyr/projects/skyrim/usbc.dts index c7e85ceb5f..8486927e8d 100644 --- a/zephyr/projects/skyrim/usbc.dts +++ b/zephyr/projects/skyrim/usbc.dts @@ -1,56 +1,26 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ - #include <dt-bindings/usb_pd_tcpm.h> - / { usbc { #address-cells = <1>; #size-cells = <0>; - port0@0 { + usbc_port0: port0@0 { compatible = "named-usbc-port"; reg = <0>; - bc12 { - compatible = "pericom,pi3usb9201"; - status = "okay"; - irq = <&int_usb_c0_bc12>; - port = <&i2c_tcpc0>; - i2c-addr-flags = "PI3USB9201_I2C_ADDR_3_FLAGS"; - }; - tcpc { - compatible = "nuvoton,nct38xx"; - gpio-dev = <&nct3807_C0>; - port = <&i2c_tcpc0>; - i2c-addr-flags = "NCT38XX_I2C_ADDR1_1_FLAGS"; - tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>; - }; - chg { - compatible = "intersil,isl9241"; - status = "okay"; - port = <&i2c_charger>; - }; + bc12 = <&bc12_port0>; + tcpc = <&tcpc_port0>; + chg = <&charger>; }; - port1@1 { + usbc_port1: port1@1 { compatible = "named-usbc-port"; reg = <1>; - bc12 { - compatible = "pericom,pi3usb9201"; - status = "okay"; - irq = <&int_usb_c1_bc12>; - port = <&i2c_tcpc1>; - i2c-addr-flags = "PI3USB9201_I2C_ADDR_3_FLAGS"; - }; - tcpc { - compatible = "nuvoton,nct38xx"; - gpio-dev = <&nct3807_C1>; - port = <&i2c_tcpc1>; - i2c-addr-flags = "NCT38XX_I2C_ADDR1_1_FLAGS"; - tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>; - }; + bc12 = <&bc12_port1>; + tcpc = <&tcpc_port1>; }; }; }; diff --git a/zephyr/projects/skyrim/usbc_config_guybrush.c b/zephyr/projects/skyrim/usbc_config_guybrush.c deleted file mode 100644 index 1d7afcbbb4..0000000000 --- a/zephyr/projects/skyrim/usbc_config_guybrush.c +++ /dev/null @@ -1,611 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Guybrush family-specific USB-C configuration */ - -#include "cros_board_info.h" -#include "battery_fuel_gauge.h" -#include "charge_manager.h" -#include "charge_ramp.h" -#include "charge_state_v2.h" -#include "charge_state.h" -#include "charger.h" -#include "driver/bc12/pi3usb9201.h" -#include "driver/charger/isl9241.h" -#include "driver/ppc/aoz1380.h" -#include "driver/ppc/nx20p348x.h" -#include "driver/retimer/anx7491.h" -#include "driver/retimer/ps8811.h" -#include "driver/retimer/ps8818.h" -#include "driver/tcpm/nct38xx.h" -#include "driver/usb_mux/anx7451.h" -#include "driver/usb_mux/amd_fp6.h" -#include "gpio.h" -#include "gpio/gpio_int.h" -#include "hooks.h" -#include "ioexpander.h" -#include "power.h" -#include "usb_mux.h" -#include "usb_pd_tcpm.h" -#include "usbc_ppc.h" - -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) - -/* USB-A ports */ -enum usba_port { - USBA_PORT_A0 = 0, - USBA_PORT_A1, - USBA_PORT_COUNT -}; - -/* USB-C ports */ -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; -BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT); - -static void reset_nct38xx_port(int port); - -static void usbc_interrupt_init(void) -{ - /* Enable PPC interrupts. */ - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc)); - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_ppc)); - - /* Enable TCPC interrupts. */ - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_tcpc)); - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_tcpc)); - - /* Enable BC 1.2 interrupts */ - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_bc12)); - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_bc12)); - - /* TODO: Enable SBU fault interrupts (io expander )*/ -} -DECLARE_HOOK(HOOK_INIT, usbc_interrupt_init, HOOK_PRIO_POST_I2C); - -struct ppc_config_t ppc_chips[] = { - [USBC_PORT_C0] = { - /* Device does not talk I2C */ - .drv = &aoz1380_drv - }, - - [USBC_PORT_C1] = { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = NX20P3483_ADDR1_FLAGS, - .drv = &nx20p348x_drv - }, -}; -BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == CONFIG_USB_PD_PORT_MAX_COUNT); -unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); - -/* - * .init is not necessary here because it has nothing - * to do. Primary mux will handle mux state so .get is - * not needed as well. usb_mux.c can handle the situation - * properly. - */ -static int fsusb42umx_set_mux(const struct usb_mux*, mux_state_t, bool *); -struct usb_mux_driver usbc0_sbu_mux_driver = { - .set = fsusb42umx_set_mux, -}; - -/* - * Since FSUSB42UMX is not a i2c device, .i2c_port and - * .i2c_addr_flags are not required here. - */ -struct usb_mux usbc0_sbu_mux = { - .usb_port = USBC_PORT_C0, - .driver = &usbc0_sbu_mux_driver, -}; - -__overridable int board_c1_ps8818_mux_set(const struct usb_mux *me, - mux_state_t mux_state) -{ - CPRINTSUSB("C1: PS8818 mux using default tuning"); - return 0; -} - -struct usb_mux usbc1_ps8818 = { - .usb_port = USBC_PORT_C1, - .i2c_port = I2C_PORT_TCPC1, - .flags = USB_MUX_FLAG_RESETS_IN_G3, - .i2c_addr_flags = PS8818_I2C_ADDR_FLAGS, - .driver = &ps8818_usb_retimer_driver, - .board_set = &board_c1_ps8818_mux_set, -}; - -/* - * ANX7491(A1) and ANX7451(C1) are on the same i2c bus. Both default - * to 0x29 for the USB i2c address. This moves ANX7451(C1) USB i2c - * address to 0x2A. ANX7491(A1) will stay at the default 0x29. - */ -uint16_t board_anx7451_get_usb_i2c_addr(const struct usb_mux *me) -{ - ASSERT(me->usb_port == USBC_PORT_C1); - return 0x2a; -} - -__overridable int board_c1_anx7451_mux_set(const struct usb_mux *me, - mux_state_t mux_state) -{ - CPRINTSUSB("C1: ANX7451 mux using default tuning"); - return 0; -} - -struct usb_mux usbc1_anx7451 = { - .usb_port = USBC_PORT_C1, - .i2c_port = I2C_PORT_TCPC1, - .flags = USB_MUX_FLAG_RESETS_IN_G3, - .i2c_addr_flags = ANX7491_I2C_ADDR3_FLAGS, - .driver = &anx7451_usb_mux_driver, - .board_set = &board_c1_anx7451_mux_set, -}; - -struct usb_mux usb_muxes[] = { - [USBC_PORT_C0] = { - .usb_port = USBC_PORT_C0, - .i2c_port = I2C_PORT_USB_MUX, - .i2c_addr_flags = AMD_FP6_C0_MUX_I2C_ADDR, - .driver = &amd_fp6_usb_mux_driver, - .next_mux = &usbc0_sbu_mux, - }, - [USBC_PORT_C1] = { - .usb_port = USBC_PORT_C1, - .i2c_port = I2C_PORT_USB_MUX, - .i2c_addr_flags = AMD_FP6_C4_MUX_I2C_ADDR, - .driver = &amd_fp6_usb_mux_driver, - /* .next_mux = filled in by setup_mux based on fw_config */ - } -}; -BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT); - -/* - * USB C0 port SBU mux use standalone FSUSB42UMX - * chip and it needs a board specific driver. - * Overall, it will use chained mux framework. - */ -static int fsusb42umx_set_mux(const struct usb_mux *me, mux_state_t mux_state, - bool *ack_required) -{ - /* This driver does not use host command ACKs */ - *ack_required = false; - - if (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ioex_set_level(IOEX_USB_C0_SBU_FLIP, 1); - else - ioex_set_level(IOEX_USB_C0_SBU_FLIP, 0); - - return EC_SUCCESS; -} - -static void setup_mux(void) -{ - /* TODO: Fill in C1 mux based on CBI */ - CPRINTSUSB("C1: Setting ANX7451 mux"); - usb_muxes[USBC_PORT_C1].next_mux = &usbc1_anx7451; -} -DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C); - -int board_set_active_charge_port(int port) -{ - int is_valid_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); - int i; - int rv; - - if (port == CHARGE_PORT_NONE) { - CPRINTSUSB("Disabling all charger ports"); - - /* Disable all ports. */ - for (i = 0; i < ppc_cnt; i++) { - /* - * If this port had booted in dead battery mode, go - * ahead and reset it so EN_SNK responds properly. - */ - if (nct38xx_get_boot_type(i) == - NCT38XX_BOOT_DEAD_BATTERY) { - reset_nct38xx_port(i); - pd_set_error_recovery(i); - } - - /* - * Do not return early if one fails otherwise we can - * get into a boot loop assertion failure. - */ - if (ppc_vbus_sink_enable(i, 0)) - CPRINTSUSB("Disabling C%d as sink failed.", i); - } - - return EC_SUCCESS; - } else if (!is_valid_port) { - return EC_ERROR_INVAL; - } - - /* - * Check if we can reset any ports in dead battery mode - * - * The NCT3807 may continue to keep EN_SNK low on the dead battery port - * and allow a dangerous level of voltage to pass through to the initial - * charge port (see b/183660105). We must reset the ports if we have - * sufficient battery to do so, which will bring EN_SNK back under - * normal control. - */ - rv = EC_SUCCESS; - for (i = 0; i < board_get_usb_pd_port_count(); i++) { - if (nct38xx_get_boot_type(i) == NCT38XX_BOOT_DEAD_BATTERY) { - CPRINTSUSB("Found dead battery on %d", i); - /* - * If we have battery, get this port reset ASAP. - * This means temporarily rejecting charge manager - * sets to it. - */ - if (pd_is_battery_capable()) { - reset_nct38xx_port(i); - pd_set_error_recovery(i); - - if (port == i) - rv = EC_ERROR_INVAL; - } else if (port != i) { - /* - * If other port is selected and in dead battery - * mode, reset this port. Otherwise, reject - * change because we'll brown out. - */ - if (nct38xx_get_boot_type(port) == - NCT38XX_BOOT_DEAD_BATTERY) { - reset_nct38xx_port(i); - pd_set_error_recovery(i); - } else { - rv = EC_ERROR_INVAL; - } - } - } - } - - if (rv != EC_SUCCESS) - return rv; - - /* Check if the port is sourcing VBUS. */ - if (tcpm_get_src_ctrl(port)) { - CPRINTSUSB("Skip enable C%d", port); - return EC_ERROR_INVAL; - } - - CPRINTSUSB("New charge port: C%d", port); - - /* - * Turn off the other ports' sink path FETs, before enabling the - * requested charge port. - */ - for (i = 0; i < ppc_cnt; i++) { - if (i == port) - continue; - - if (ppc_vbus_sink_enable(i, 0)) - CPRINTSUSB("C%d: sink path disable failed.", i); - } - - /* Enable requested charge port. */ - if (ppc_vbus_sink_enable(port, 1)) { - CPRINTSUSB("C%d: sink path enable failed.", port); - return EC_ERROR_UNKNOWN; - } - - return EC_SUCCESS; -} - -/* - * In the AOZ1380 PPC, there are no programmable features. We use - * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0 - * current limits. - */ -int board_aoz1380_set_vbus_source_current_limit(int port, - enum tcpc_rp_value rp) -{ - int rv = EC_SUCCESS; - - rv = ioex_set_level(IOEX_USB_C0_PPC_ILIM_3A_EN, - (rp == TYPEC_RP_3A0) ? 1 : 0); - - return rv; -} - -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) -{ - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); -} - -/* TODO: sbu_fault_interrupt from io expander */ - -/* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */ -#define GUYBRUSH_AC_PROCHOT_CURRENT_MA 3328 -static void set_ac_prochot(void) -{ - isl9241_set_ac_prochot(CHARGER_SOLO, GUYBRUSH_AC_PROCHOT_CURRENT_MA); -} -DECLARE_HOOK(HOOK_INIT, set_ac_prochot, HOOK_PRIO_DEFAULT); - -void tcpc_alert_event(enum gpio_signal signal) -{ - int port; - - switch (signal) { - case GPIO_USB_C0_TCPC_INT_ODL: - port = 0; - break; - case GPIO_USB_C1_TCPC_INT_ODL: - port = 1; - break; - default: - return; - } - - schedule_deferred_pd_interrupt(port); -} - -static void reset_nct38xx_port(int port) -{ - const struct gpio_dt_spec *reset_gpio_l; - - /* TODO: Save and restore ioex signals */ - if (port == USBC_PORT_C0) - reset_gpio_l = GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_rst_l); - else if (port == USBC_PORT_C1) - reset_gpio_l = GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_rst_l); - else - /* Invalid port: do nothing */ - return; - - gpio_pin_set_dt(reset_gpio_l, 0); - msleep(NCT38XX_RESET_HOLD_DELAY_MS); - gpio_pin_set_dt(reset_gpio_l, 1); - nct38xx_reset_notify(port); - if (NCT3807_RESET_POST_DELAY_MS != 0) - msleep(NCT3807_RESET_POST_DELAY_MS); -} - - -void board_reset_pd_mcu(void) -{ - /* Reset TCPC0 */ - reset_nct38xx_port(USBC_PORT_C0); - - /* Reset TCPC1 */ - reset_nct38xx_port(USBC_PORT_C1); -} - -uint16_t tcpc_get_alert_status(void) -{ - uint16_t status = 0; - - /* - * Check which port has the ALERT line set and ignore if that TCPC has - * its reset line active. - */ - if (!gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_int_odl))) { - if (gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_rst_l)) != 0) - status |= PD_STATUS_TCPC_ALERT_0; - } - - if (!gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_int_odl))) { - if (gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_rst_l)) != 0) - status |= PD_STATUS_TCPC_ALERT_1; - } - - return status; -} - -void ppc_interrupt(enum gpio_signal signal) -{ - switch (signal) { - case GPIO_USB_C0_PPC_INT_ODL: - aoz1380_interrupt(USBC_PORT_C0); - break; - - case GPIO_USB_C1_PPC_INT_ODL: - nx20p348x_interrupt(USBC_PORT_C1); - break; - - default: - break; - } -} - -void bc12_interrupt(enum gpio_signal signal) -{ - switch (signal) { - case GPIO_USB_C0_BC12_INT_ODL: - usb_charger_task_set_event(0, USB_CHG_EVENT_BC12); - break; - - case GPIO_USB_C1_BC12_INT_ODL: - usb_charger_task_set_event(1, USB_CHG_EVENT_BC12); - break; - - default: - break; - } -} - -/** - * Return if VBUS is sagging too low - * - * For legacy BC1.2 charging with CONFIG_CHARGE_RAMP_SW, ramp up input current - * until voltage drops to 4.5V. Don't go lower than this to be kind to the - * charger (see b/67964166). - */ -#define BC12_MIN_VOLTAGE 4500 -int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) -{ - int voltage = 0; - int rv; - - rv = charger_get_vbus_voltage(port, &voltage); - - if (rv) { - CPRINTSUSB("%s rv=%d", __func__, rv); - return 0; - } - - /* - * b/168569046: The ISL9241 sometimes incorrectly reports 0 for unknown - * reason, causing ramp to stop at 0.5A. Workaround this by ignoring 0. - * This partly defeats the point of ramping, but will still catch - * VBUS below 4.5V and above 0V. - */ - if (voltage == 0) { - CPRINTSUSB("%s vbus=0", __func__); - return 0; - } - - if (voltage < BC12_MIN_VOLTAGE) - CPRINTSUSB("%s vbus=%d", __func__, voltage); - - return voltage < BC12_MIN_VOLTAGE; -} - -#define SAFE_RESET_VBUS_DELAY_MS 900 -#define SAFE_RESET_VBUS_MV 5000 -void board_hibernate(void) -{ - int port; - enum ec_error_list ret; - - /* - * If we are charging, then drop the Vbus level down to 5V to ensure - * that we don't get locked out of the 6.8V OVLO for our PPCs in - * dead-battery mode. This is needed when the TCPC/PPC rails go away. - * (b/79218851, b/143778351, b/147007265) - */ - port = charge_manager_get_active_charge_port(); - if (port != CHARGE_PORT_NONE) { - pd_request_source_voltage(port, SAFE_RESET_VBUS_MV); - - /* Give PD task and PPC chip time to get to 5V */ - msleep(SAFE_RESET_VBUS_DELAY_MS); - } - - /* Try to put our battery fuel gauge into sleep mode */ - ret = battery_sleep_fuel_gauge(); - if ((ret != EC_SUCCESS) && (ret != EC_ERROR_UNIMPLEMENTED)) - cprints(CC_SYSTEM, "Failed to send battery sleep command"); -} - -__overridable enum ec_error_list -board_a1_ps8811_retimer_init(const struct usb_mux *me) -{ - return EC_SUCCESS; -} - -static int baseboard_a1_ps8811_retimer_init(const struct usb_mux *me) -{ - int rv; - int tries = 2; - - do { - int val; - - rv = ps8811_i2c_read(me, PS8811_REG_PAGE1, - PS8811_REG1_USB_BEQ_LEVEL, &val); - } while (rv && --tries); - - if (rv) { - CPRINTSUSB("A1: PS8811 retimer not detected!"); - return rv; - } - CPRINTSUSB("A1: PS8811 retimer detected"); - rv = board_a1_ps8811_retimer_init(me); - if (rv) - CPRINTSUSB("A1: Error during PS8811 setup rv:%d", rv); - return rv; -} - -/* - * PS8811 is just a type-A USB retimer, reusing mux structure for - * convenience. - */ -const struct usb_mux usba1_ps8811 = { - .usb_port = USBA_PORT_A1, - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = PS8811_I2C_ADDR_FLAGS3, - .board_init = &baseboard_a1_ps8811_retimer_init, -}; - -__overridable enum ec_error_list -board_a1_anx7491_retimer_init(const struct usb_mux *me) -{ - return EC_SUCCESS; -} - -static int baseboard_a1_anx7491_retimer_init(const struct usb_mux *me) -{ - int rv; - int tries = 2; - - do { - int val; - - rv = i2c_read8(me->i2c_port, me->i2c_addr_flags, 0, &val); - } while (rv && --tries); - if (rv) { - CPRINTSUSB("A1: ANX7491 retimer not detected!"); - return rv; - } - CPRINTSUSB("A1: ANX7491 retimer detected"); - rv = board_a1_anx7491_retimer_init(me); - if (rv) - CPRINTSUSB("A1: Error during ANX7491 setup rv:%d", rv); - return rv; -} - -/* - * ANX7491 is just a type-A USB retimer, reusing mux structure for - * convenience. - */ -const struct usb_mux usba1_anx7491 = { - .usb_port = USBA_PORT_A1, - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = ANX7491_I2C_ADDR0_FLAGS, - .board_init = &baseboard_a1_anx7491_retimer_init, -}; - -void baseboard_a1_retimer_setup(void) -{ - struct usb_mux a1_retimer; - - /* TODO: Support PS8811 retimer through CBI */ - a1_retimer = usba1_anx7491; - a1_retimer.board_init(&a1_retimer); -} -DECLARE_DEFERRED(baseboard_a1_retimer_setup); - -/* TODO: Remove when guybrush is no longer supported */ -#ifdef CONFIG_BOARD_GUYBRUSH -void board_overcurrent_event(int port, int is_overcurrented) -{ - switch (port) { - case USBC_PORT_C0: - case USBC_PORT_C1: - gpio_pin_set_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c0_c1_fault_odl), - !is_overcurrented); - break; - - default: - break; - } -} -#endif diff --git a/zephyr/projects/skyrim/winterhold.dts b/zephyr/projects/skyrim/winterhold.dts new file mode 100644 index 0000000000..1b2a89999f --- /dev/null +++ b/zephyr/projects/skyrim/winterhold.dts @@ -0,0 +1,169 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/usbc_mux.h> + +#include "i2c_common.dtsi" + +/ { + named-gpios { + /* Winterhold-specific GPIO customizations */ + }; + + named-temp-sensors { + compatible = "cros-ec,temp-sensors"; + soc-pct2075 { + temp_host_high = <100>; + temp_host_halt = <105>; + temp_host_release_high = <80>; + temp_host_release_halt = <80>; + temp_fan_off = <0>; + temp_fan_max = <70>; + power-good-pin = <&gpio_pg_pwr_s5>; + sensor = <&soc_pct2075>; + }; + amb-pct2075 { + power-good-pin = <&gpio_pg_pwr_s5>; + sensor = <&amb_pct2075>; + }; + }; + + /* + * Note this is expected to vary per-board, so we keep it in the board + * dts files. + */ + Winterhold-fw-config { + compatible = "cros-ec,cbi-fw-config"; + + form-factor { + enum-name = "FW_FORM_FACTOR"; + start = <0>; + size = <1>; + + ff-clamshell { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_FF_CLAMSHELL"; + value = <0>; + }; + ff-convertible { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_FF_CONVERTIBLE"; + value = <1>; + default; + }; + }; + io-db { + enum-name = "FW_IO_DB"; + start = <6>; + size = <2>; + + io-db-ps8811-ps8818 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_IO_DB_PS8811_PS8818"; + value = <0>; + }; + io-db-none-anx7483 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_IO_DB_NONE_ANX7483"; + value = <1>; + default; + }; + }; + + /* + * FW_CONFIG field to enable fan or not. + */ + fan { + enum-name = "FW_FAN"; + start = <10>; + size = <1>; + + no-fan { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_FAN_NOT_PRESENT"; + value = <0>; + }; + fan-present { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_FAN_PRESENT"; + value = <1>; + /* + * Set as default so that unprovisioned + * configs will run the fan regardless. + */ + default; + }; + }; + }; + + /* Rotation matrices for motion sensors. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <0 (-1) 0 + 1 0 0 + 0 0 1>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <0 1 0 + (-1) 0 0 + 0 0 1>; + }; + }; +}; + +&i2c0_0 { + anx7483_port0: anx7483@3e { + compatible = "analogix,anx7483"; + reg = <0x3e>; + board-set = "board_anx7483_c0_mux_set"; + }; + ppc_port0: nx20p348x@71 { + compatible = "nxp,nx20p348x"; + status = "okay"; + reg = <0x71>; + }; +}; + +&i2c1_0 { + anx7483_port1: anx7483@3e { + compatible = "analogix,anx7483"; + reg = <0x3e>; + board-set = "board_anx7483_c1_mux_set"; + }; + ppc_port1: nx20p348x@71 { + compatible = "nxp,nx20p348x"; + status = "okay"; + reg = <0x71>; + }; + ps8818_port1: ps8818@28 { + compatible = "parade,ps8818"; + reg = <0x28>; + flags = <(USB_MUX_FLAG_RESETS_IN_G3)>; + board-set = "board_c1_ps8818_mux_set"; + }; +}; + +&usbc_port0 { + ppc = <&ppc_port0>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&amd_fp6_port0 &anx7483_port0>; + }; +}; + +&usbc_port1 { + ppc = <&ppc_port1>; + usb-mux-chain-1-anx { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&amd_fp6_port1 &anx7483_port1>; + }; + usb_mux_chain_ps8818_port1: usb-mux-chain-1-ps { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&amd_fp6_port1 &ps8818_port1>; + alternative-chain; + }; +}; |