diff options
Diffstat (limited to 'zephyr/shim/chip/mchp/include/flash_chip.h')
| -rw-r--r-- | zephyr/shim/chip/mchp/include/flash_chip.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/zephyr/shim/chip/mchp/include/flash_chip.h b/zephyr/shim/chip/mchp/include/flash_chip.h index b3677fb45c..de8138614c 100644 --- a/zephyr/shim/chip/mchp/include/flash_chip.h +++ b/zephyr/shim/chip/mchp/include/flash_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,10 +11,10 @@ * Similar to W25X40, both only have one status reg */ #define CONFIG_SPI_FLASH_W25X40 /* Internal SPI flash type. */ -#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ -#define CONFIG_FLASH_ERASE_SIZE 0x1000 -#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE +#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ +#define CONFIG_FLASH_ERASE_SIZE 0x1000 +#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE /* RO image resides at 4KB offset in protected region * The first 4KB in the protected region starting at offset 0 contains @@ -23,7 +23,7 @@ * RW image is never loaded by the Boot-ROM therefore no TAG or Header * is needed. RW starts at offset 0 in RW storage region. */ -#define CONFIG_RO_STORAGE_OFF 0x1000 -#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0x1000 +#define CONFIG_RW_STORAGE_OFF 0 #endif /* __CROS_EC_FLASH_CHIP_H */ |