diff options
Diffstat (limited to 'zephyr/shim/chip/mchp/include')
-rw-r--r-- | zephyr/shim/chip/mchp/include/clock_chip.h | 2 | ||||
-rw-r--r-- | zephyr/shim/chip/mchp/include/flash_chip.h | 14 | ||||
-rw-r--r-- | zephyr/shim/chip/mchp/include/system_chip.h | 16 |
3 files changed, 16 insertions, 16 deletions
diff --git a/zephyr/shim/chip/mchp/include/clock_chip.h b/zephyr/shim/chip/mchp/include/clock_chip.h index c317ccb415..4c14d60ff9 100644 --- a/zephyr/shim/chip/mchp/include/clock_chip.h +++ b/zephyr/shim/chip/mchp/include/clock_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/zephyr/shim/chip/mchp/include/flash_chip.h b/zephyr/shim/chip/mchp/include/flash_chip.h index b3677fb45c..de8138614c 100644 --- a/zephyr/shim/chip/mchp/include/flash_chip.h +++ b/zephyr/shim/chip/mchp/include/flash_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,10 +11,10 @@ * Similar to W25X40, both only have one status reg */ #define CONFIG_SPI_FLASH_W25X40 /* Internal SPI flash type. */ -#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ -#define CONFIG_FLASH_ERASE_SIZE 0x1000 -#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE +#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ +#define CONFIG_FLASH_ERASE_SIZE 0x1000 +#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE /* RO image resides at 4KB offset in protected region * The first 4KB in the protected region starting at offset 0 contains @@ -23,7 +23,7 @@ * RW image is never loaded by the Boot-ROM therefore no TAG or Header * is needed. RW starts at offset 0 in RW storage region. */ -#define CONFIG_RO_STORAGE_OFF 0x1000 -#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0x1000 +#define CONFIG_RW_STORAGE_OFF 0 #endif /* __CROS_EC_FLASH_CHIP_H */ diff --git a/zephyr/shim/chip/mchp/include/system_chip.h b/zephyr/shim/chip/mchp/include/system_chip.h index a62ea4a525..01cd1e7391 100644 --- a/zephyr/shim/chip/mchp/include/system_chip.h +++ b/zephyr/shim/chip/mchp/include/system_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -6,18 +6,18 @@ #ifndef __CROS_EC_SYSTEM_CHIP_H_ #define __CROS_EC_SYSTEM_CHIP_H_ -#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit))) -#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit)))) +#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit))) +#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit)))) #undef IS_BIT_SET -#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1)) +#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1)) /******************************************************************************/ /* Optional M4 Registers */ -#define CPU_MPU_CTRL REG32(0xE000ED94) -#define CPU_MPU_RNR REG32(0xE000ED98) -#define CPU_MPU_RBAR REG32(0xE000ED9C) -#define CPU_MPU_RASR REG32(0xE000EDA0) +#define CPU_MPU_CTRL REG32(0xE000ED94) +#define CPU_MPU_RNR REG32(0xE000ED98) +#define CPU_MPU_RBAR REG32(0xE000ED9C) +#define CPU_MPU_RASR REG32(0xE000EDA0) void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, uint32_t size, uint32_t exeAddr); |