diff options
Diffstat (limited to 'zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h')
| -rw-r--r-- | zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h b/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h index f874879f04..2320e61965 100644 --- a/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h +++ b/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -15,7 +15,7 @@ #include <ap_power_host_sleep.h> #include <x86_common_pwrseq.h> -#define DT_DRV_COMPAT intel_ap_pwrseq +#define DT_DRV_COMPAT intel_ap_pwrseq /* The wait time is ~150 msec, allow for safety margin. */ #define IN_PCH_SLP_SUS_WAIT_TIME_MS 250 @@ -23,11 +23,11 @@ enum power_states_ndsx chipset_pwr_sm_run(enum power_states_ndsx curr_state); void init_chipset_pwr_seq_state(void); enum power_states_ndsx chipset_pwr_seq_get_state(void); -void request_exit_hardoff(bool should_exit); +void request_start_from_g3(void); enum power_states_ndsx pwr_sm_get_state(void); -const char * const pwr_sm_get_state_name(enum power_states_ndsx state); +const char *const pwr_sm_get_state_name(enum power_states_ndsx state); void apshutdown(void); void ap_pwrseq_handle_chipset_reset(void); -void set_reboot_ap_at_g3_delay_seconds(uint32_t d_time); +void set_start_from_g3_delay_seconds(uint32_t d_time); #endif /* __X86_NON_DSX_COMMON_PWRSEQ_SM_HANDLER_H__ */ |