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| author | Martin Roth <gaumless@gmail.com> | 2023-02-02 17:23:46 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-02-04 03:23:24 +0000 |
| commit | 7c66d39a0b94e894a56453e0624e976bbbec8850 (patch) | |
| tree | bccf0d4befc805b8360b3cdc1e88ef6385074e2e /src/soc/amd/picasso/Kconfig | |
| parent | 10c43a2c2e0a68a80bd4fc92732cde037b1d4a34 (diff) | |
| download | coreboot-7c66d39a0b94e894a56453e0624e976bbbec8850.tar.gz | |
soc/amd: Use common reset code for PCO SoC
This switches the Picasso SoC to use the common reset code.
Picasso supports warm resets, so set the SOC_AMD_SUPPORTS_WARM_RESET
flag.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I52515b20ef6c70b137f176d95480757b16bd8735
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72755
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso/Kconfig')
| -rw-r--r-- | src/soc/amd/picasso/Kconfig | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index a0254e98d3..d34b2ab444 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -50,6 +50,7 @@ config SOC_AMD_PICASSO select SOC_AMD_COMMON_BLOCK_PM select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE select SOC_AMD_COMMON_BLOCK_PSP_GEN2 + select SOC_AMD_COMMON_BLOCK_RESET select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI @@ -61,6 +62,7 @@ config SOC_AMD_PICASSO select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE select SOC_AMD_COMMON_FSP_DMI_TABLES + select SOC_AMD_SUPPORTS_WARM_RESET select SSE2 select UDK_2017_BINDING select USE_DDR4 |