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* console: Add format-checking __printf() to die()Nico Huber2023-05-171-1/+1
| | | | | | | | | | | | | Code changes are necessary because `-Wformat` warns about empty format strings by default. Change-Id: Ic8021b70f4cd4875b06f196f88b84940c9a79fe0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75147 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* acpigen: Add printf-like function for debug stringCliff Huang2023-05-161-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Generate formatted string and ACPI code to print debug string. For example (with pcie_rp = 1): acpigen_write_debug_sprintf("calling _ON for RP: %u", pcie_rp); generates the following ACPI code: Debug = "calling _ON for RP: 1" With this new function, the following functions are not needed anymore and therefore are removed by this patch. - acpigen_concatenate_string_string() - acpigen_concatenate_string_int() - acpigen_write_debug_concatenate_string_string() - acpigen_write_debug_concatenate_string_int() BRANCH=firmware-brya-14505.B TEST=Add above functions in the acpigen code and check the generated SSDT table after OS boot. Check the debug messages is in the kernel log when /sys/modules/acpi/parameters/aml_debug_output is set to '1'. Change-Id: Id4a42e5854516a22b7bc4559c2ed08680722c5ba Signed-off-by: Cliff Huang <cliff.huang@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Zhixing Ma <zhixing.ma@intel.com> Reviewed-by: Musse Abdullahi <musse.abdullahi@intel.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* acpi/acpigen: add acpigen_resource_io to generate I/O resourceFelix Held2023-05-111-0/+1
| | | | | | | | | | | | Add the acpigen_resource_io helper function to generate an I/O range resource. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I177f59b52d4dbbff0a3ceeef5fc8c7455cef9ff8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
* acpi/acpigen: add acpigen_resource_bus_number to generate bus numberFelix Held2023-05-111-0/+2
| | | | | | | | | | | | Add the acpigen_resource_bus_number helper function to generate a bus number range resource. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ib1f1da3dbe823c6bc4fc30c0622653410cfbf301 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
* drivers/pc80/rtc/mc146818rtc.c: Add Kconfig for RTC CMOS base addressesJonathon Hall2023-05-081-10/+11
| | | | | | | | | | | | Configure the CMOS bank I/O base addresses with PC_CMOS_BASE_PORT_BANK* rather than hard-coding as 0x70, 0x72. The defaults remain the same. Change-Id: Ie44e5f5191c66f44e2df8ea0ff58a860be88bfcf Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74903 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* acpi/acpigen: add acpigen_write_BBN to generate base bus number methodFelix Held2023-05-081-0/+1
| | | | | | | | | | | | | Introduce acpigen_write_BBN to generate the ACPI method object that returns the base bus number for a PCI(e) host bridge. When called, the base_bus_number argument must be the first PCI bus number that got assigned to the corresponding host bridge. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib67bf42b9c77c262d8a02d8f28ac5cb8482136b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
* acpigen: Add a runtime method to override exposed _Sx sleep statesArthur Heymans2023-05-011-0/+4
| | | | | | | | | | | | | | | This allows mainboards to override available sleep states at runtime. This is done by adding a IntObj in SSDT that DSDT consumes to override the available _Sx states. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic21830c1ef9c183b1e3005cc1f8b7daf7e9ea998 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74762 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* ACPI: Make FADT entries for RTC/CMOS architecturalKyösti Mälkki2023-04-291-0/+3
| | | | | | | | | | | | | | | | For AMD, replace name RTC_ALT_CENTURY with RTC_CLK_ALTCENTURY that points to same offset. Since the century field inside RTC falls within the NVRAM space, and could interfere with OPTION_TABLE, it is now guarded with config USE_PC_CMOS_ALTCENTURY. There were no reference for the use of offset 0x48 for century. Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74601 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* vga: Change the arguments of vga_write_text to support extended ASCIIHsuan Ting Chen2023-04-281-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | VGA defined the extended ASCII set based on CP437, but the function vga_write_text() accepts a signed char array. This will cause unnecessary confusion that if we want to print u with umlaut (code=129 in CP437), we need to explicitly cast it to -127 in signed char. Since we still want to leverage the built-in string utilities which only accepts const char*, we still need to cast it to signed char while processing, and cast it back to unsigned once we write into the frame buffer. BRANCH=brya BUG=b:264666392 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: If555bbc05f40ce3f02339c0468afff6dda8b7ded Reviewed-on: https://review.coreboot.org/c/coreboot/+/73099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* arch/x86/ioapic: Promote ioapic_get_sci_pin()Kyösti Mälkki2023-04-261-2/+0
| | | | | | | | | | | Platform needs to implement this to provide information about SCI IRQ pin and polarity, to be used for filling in ACPI FADT and MADT entries. Change-Id: Icea7e9ca4abf3997c01617d2f78f25036d85a52f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel: Introduce ioapic_get_sci_pin()Kyösti Mälkki2023-04-261-0/+3
| | | | | | | | | | | | | | | | | | | | | | | According to ACPI Release 6.5 systems supporting PIC (i8259) interrupt mechanism need to report IRQ vector for the SCI_INT field. In PIC mode only IRQ0..15 are allowed hardware vectors. This change should cover section 5.2.9 to not pass SCI_INT larger than IRQ15. Section 5.2.15.5 needs follow-up work. Care should be taken that ioapic_get_sci_pin() is called after platform code has potentially changed the routing from the default. It appears touched all platforms except siemens/mc_aplX currently program SCI as IRQ9. Change-Id: I723c207f1dcbba5e6fc0452fe1dbd087fad290ee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* ACPI: Add acpigen_write_PTC()Kyösti Mälkki2023-04-261-0/+1
| | | | | | | | Change-Id: Ibaf2d7105e7a5da8a50ef32b682978ff55fe31e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* acpi/acpi.c: Reduce scope of some functionsArthur Heymans2023-04-261-16/+0
| | | | | | | | | | | | | | | These functions are only used in one compilation unit. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I6f8282f308506a68b14ce3101f11078cb13709f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74756 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* include/cpu/amd/mtrr: fix typo in get_top_of_mem_above_4gbFelix Held2023-04-231-1/+1
| | | | | | | | | | | Add the missing 'b' to the 4gb so that get_top_of_mem_above_4gb is in line with get_top_of_mem_below_4gb. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic9170372d8b0c27d7de3bd04d822c95e2015cb10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* lib/version: Move board identification stringsKyösti Mälkki2023-04-223-6/+11
| | | | | | | | | | | | | | | These strings are now only expanded in lib/identity.c. This improves ccache hit rates slightly, as one built object file lib/version.o is used for all variants of a board. Also one built object file lib/identity.o can become a ccache hit for successive builds of a variant, while the commit hash changes. Change-Id: Ia7d5454d95c8698ab1c1744e63ea4c04d615bb3b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* include/cpu/amd/mtrr: return uint32_t from get_top_of_mem_below_4gbFelix Held2023-04-211-1/+1
| | | | | | | | | | | The top of memory below 4GB will always fit into 32 bits, so change the return type accordingly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b463a17f2db3b7a99ff3572f318c9c22aac7431 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* include/cpu/amd/mtrr: rename functions to get top of memory regionsFelix Held2023-04-211-2/+2
| | | | | | | | | | | Rename amd_topmem and amd_topmem2 to get_top_of_mem_below_4gb and get_top_of_mem_above_4g to make it clearer what those functions return. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic6e98d94c731af74aea0ce276a9a7e4867e3986f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* src/cpu/power9: move part of scom.h to scom.cSergii Dmytruk2023-04-181-5/+0
| | | | | | | | | | | Reset function, constants and include are not used outside of scom.c and not going to be. Change-Id: Iff4e98ae52c7099954f0c20fcb639eb87af15534 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
* soc/intel/meteorlake: Add B0 stepping CPU IDMusse Abdullahi2023-04-151-0/+1
| | | | | | | | | | | | | | | | This patch adds CPU ID for B0 stepping (aka ES2). DOC=#723567 TEST=Able to boot on B0 rvp and get correct CPU Name in coreboot log. Signed-off-by: Musse Abdullahi <musse.abdullahi@intel.com> Change-Id: I8b939ccc8b05e3648c55f8f2a0a391cb08f04184 Signed-off-by: Musse Abdullahi <musse.abdullahi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74300 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Reland "drivers/intel/dptf: Add multiple fan support under dptf"Sumeet Pawnikar2023-04-121-2/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 4dba71fd25c91a9e610287c61238a8fe24452e4e. Add multiple fan support for dptf policies. This also fixes the Google Meet resolution drop issue as per b:246535768 comment#12. When system starts Google Meet video call, it uses the hardware accelerated encoder as expected. But, as soon as another system connects to the call, an immediate fallback is observed from hardware to software encoder. Due to this, Google Meet resolution dropped from 720p to 180p. This issue is observed on Alder Lake-N SoC based fanless platforms. This same issue was not seen on fan based systems. With the fix in dptf driver where fan configures appropriate setting for only fan participant, not for other device participants, able to see consistent 720p resolution. BUG=b:246535768,b:235254828 BRANCH=None TEST=Built and tested on Alder Lake-P Redrix system for two fans support and on Alder Lake-N fanless systems. With this code change Google Meet resolution drop not observed. Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: Id07d279ff962253c22be9d395ed7be0d732aeaa7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73249 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ACPI: Add helper for MADT LAPICsKyösti Mälkki2023-04-111-3/+3
| | | | | | | | | | This avoids some code duplication related to X2APIC mode. Change-Id: I592c69e0f52687924fe41189b082c86913999136 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
* ACPI: Add helper for MADT LAPIC NMIsKyösti Mälkki2023-04-111-4/+5
| | | | | | | | | | | This avoids some code duplication related to X2APIC mode. Change-Id: I2cb8676efc1aba1b154fd04c49e53b2530239b4c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
* binaryPI: Use common code for LAPIC NMIsKyösti Mälkki2023-04-111-1/+1
| | | | | | | | Change-Id: I1a39f355733d10ecd43a1da541ab2e66ba13db15 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
* util/sconfig: Remove unused ioapic and irq keywordsArthur Heymans2023-04-111-8/+0
| | | | | | | | | | | | | | | Ioapic information in the devicetree was only used to set up mptables but this generic driver was removed (ca5a793 drivers/generic/ioapic: Drop poor implementation). This removes the unused remainders from mainboard devicetrees. Remove ioapic setup from sconfig. Change-Id: Ib3fef0bf923ab3f02f3aeed2e55cf662a3dc3a1b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* cpu/x86/topology: Add code to fill in topology on struct pathArthur Heymans2023-04-062-9/+14
| | | | | | | | | | | | | This is needed to generate MADT and SRAT where lapicid for threads need to be added last. When CPUID leaf '0xB' is not present assume some defaults that would result in identical ACPI code generation. Change-Id: I2210eb9b663dd90941a64132aa7154440dc7e5a9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69222 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/smm_module_loader.c: Fix up CPU index locallyArthur Heymans2023-04-061-2/+0
| | | | | | | | | | Don't pass the stub params to the mp_init code. Change-Id: I070bc00ae5e5bceb6c5b90ea833cc057dd41f6cc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64802 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86/mp_init.c: Generate a C header to get start32 offsetArthur Heymans2023-04-061-2/+0
| | | | | | | | | | | | | | | | | In the current design the relocatable parameters are used to know the offset of the 32bit startpoint. This requires back and forward interaction between the stub, the loader and the mp init code. This makes the code hard to read. This is static information known at buildtime, so a better way to deal with this is to generate a header that contains this offset. Change-Id: Ic01badd2af11a6e1dbc27c8e928916fedf104b5b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64625 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86/mp_init.c: Keep track of initial lapic ID inside device_pathArthur Heymans2023-04-062-4/+1
| | | | | | | | | | | | It's quite confusing to keep track of lapic ID inside the device struct and initial lapic ID inside an array. Change-Id: I4d9f8d23c0b0e5c142f6907593428d8509e4e7bb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64342 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common: Add core_type member to 'struct apic_path'Sridhar Siricilla2023-03-311-0/+1
| | | | | | | | | | | | | | The patch adds new member 'core_type' to the 'struct apic_path' and updates core type information. TEST=Build the code for MTL Change-Id: I1d34068fd5ef43f8408301bf3effa9febf85f683 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74088 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/common: Add Intel Trace Hub driverPratikkumar Prajapati2023-03-291-0/+3
| | | | | | | | | | | | | | | | | | From Meteor Lake onwards Intel FSP will generate the Trace Hub related HOB if the Trace Hub is configured to save data in DRAM. This memory region is used by Trace Hub to store the traces for debugging purpose. This driver locates the HOB and marks the memory region reserved so that OS does not use it. Intel Trace Hub developer manual can be found via document #671536 on Intel's website. Change-Id: Ie5a348071b6c6a35e8be3efd1b2b658a991aed0e Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* cpu/intel: Remove redefined SAPPHIRERAPIDS_SP CPUID to fix build errorJohnny Lin2023-03-241-6/+0
| | | | | | | | | | | | | | | | This reverts pieces of commit 08135332dd "soc/intel/xeon_sp: Report platform cpu info" Reason for revert: Due to duplicated definitions this breaks the tree. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I7bcffe99e4f049e38d9a13c82d38464c64250ee1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74002 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* soc/amd/common/block/acpi/cpu_power_state: use pstate_msr unionFelix Held2023-03-231-2/+0
| | | | | | | | | | | | | Use the pstate_msr union in get_pstate_info to check if the P state enable bit is set. Also drop the now unused PSTATE_DEF_HI_ENABLE_SHIFT and PSTATE_DEF_HI_ENABLE_MASK definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I79119e09af79a4bb680a18e93b4a61a049f0080e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* soc/intel/xeon_sp: Report platform cpu infoNaresh Solanki2023-03-231-0/+9
| | | | | | | | | | | | | | | Add platform cpu info for known microcode, print cpuid & processor branding string. This will print as in the following example: CPU: Intel(R) Xeon(R) Platinum 8468H CPU: ID 806f6, Sapphire Rapids E3, ucode: 2b000130 CPU: AES supported, TXT supported, VT supported Change-Id: I9c08fb924aad81608f554523432ab6a549b1b75f Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/xeon_sp/spr: Add header files and romstage codeJonathan Zhang2023-03-191-0/+6
| | | | | | | | | | | | | | Several FSP HOBs processing codes are similar to Intel Cooperlake-SP codes in soc/intel/xeon_sp/cpx. Register datasheet please reference Sapphire Rapids EDS Vol2 Doc#612246 and Emmitsburg PCH EDS Doc#606161. Change-Id: Ia022534e5206dbeec946d3e5f3c66bcb5628748f Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* cpu/x86/cache: CLFLUSH programs to memory before runningArthur Heymans2023-03-131-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | When cbmem is initialized in romstage and postcar placed in the stage cache + cbmem where it is run, the assumption is made that these are all in UC memory such that calling INVD in postcar is OK. For performance reasons (e.g. postcar decompression) it is desirable to cache cbmem and the stage cache during romstage. Another reason is that AGESA sets up MTRR during romstage to cache all dram, which is currently worked around by using additional MTRR's to make that UC. TESTED on asus/p5ql-em, up/squared on both regular and S3 resume bootpath. Sometimes there are minimal performance improvements when cbmem is cached (few ms). Change-Id: I7ff2a57aee620908b71829457ea0f5a0c410ec5b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37196 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/include/msr: factor out P state MSR enable bit to cpu/amd/msr.hFelix Held2023-03-081-0/+3
| | | | | | | | | | | | | | The bit position of the P state enable bit in the 8 P state MSRs is identical for all AMD chips including the family 16h model 30h APU that lives outside of soc/amd. The other bits in those 8 MSRs are more or less family- and model-specific. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia69c33e28e2a91ff9a9bfe95859c1fd454921b77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* device/xhci: Add struct for capability registersRobert Zieba2023-03-071-0/+13
| | | | | | | | | | | | | | | | | The XHCI code does not currently contain a structure that corresponds to the XHCI capability registers. These registers contain various useful information about the controller. Create a`xhci_capability_regs` struct to address this. BRANCH=guybrush BUG=b:186792595 TEST=builds Change-Id: If38bfde726bd4e5dd314456f25a2b08acd3cd20c Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* device/xhci: Add functions to work with resource pointersRobert Zieba2023-03-051-0/+6
| | | | | | | | | | | | | | | | | | | | The XHCI device functions currently use functions that require a access to the device tree. Create variant of these functions that can operate with a resource* as an argument and refactor the existing device*-based functions to operate by calling the resource*-based variants. This is useful for stages like SMM that may not have access to the device tree. BRANCH=guybrush BUG=b:186792595 TEST=Ran on skyrim device, verified that XHCI ACPI tables are still generated correctly. Change-Id: If5a74f9529d5dc6031ec968ef5f40a9cad5ffbc4 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* cpu/x86/smm: Add PCI resource store functionalityRobert Zieba2023-03-052-0/+30
| | | | | | | | | | | | | | | | | In certain cases data within protected memmory areas like SMRAM could be leaked or modified if an attacker remaps PCI BARs to point within that area. Add support to the existing SMM runtime to allow storing PCI resources in SMRAM and then later retrieving them. BRANCH=guybrush BUG=b:186792595 TEST=builds Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I23fb1e935dd1b89f1cc5c834cc2025f0fe5fda37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* acpi: Add SRAT x2APIC table supportNaresh Solanki2023-03-031-0/+13
| | | | | | | | | | | For platforms using X2APIC mode add SRAT x2APIC table generation. This allows to setup proper SRAT tables. Change-Id: If78c423884b7ce9330f0f46998ac83da334ee26d Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* lib: set up specific purpose memory as LB_MEM_SOFT_RESERVEDJonathan Zhang2023-03-033-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CXL (Compute Express Link) [1] is a cache-coherent interconnect standard for processors, memory expansion and accelerators. CXL memory is provided through CXL device which is connected through CXL/PCIe link, while regular system memory is provided through DIMMs plugged into DIMM slots which are connected to memory controllers of processor. With CXL memory, the server's memory capacity is increased. CXL memory is in its own NUMA domain, with longer latency and added bandwidth, comparing to regular system memory. Host firmware may present CXL memory as specific purpose memory. Linux kernel dax driver provides direct access to such differentiated memory. In particular, hmem dax driver provides direct access to specific purpose memory. Specific purpose memory needs to be represented in e820 table as soft reserved, as described in [2]. Add IORESOURCE_SOFT_RESERVE resource property to indicate (memory) resource that needs to be soft reserved. Add soft_reserved_ram_resource macro to allow soc/mb code to add memory resource as soft reserved. [1] https://www.computeexpresslink.org/ [2] https://web.archive.org/web/20230130233752/https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.32&id=262b45ae3ab4bf8e2caf1fcfd0d8307897519630 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ie70795bcb8c97e9dd5fb772adc060e1606f9bab0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52585 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* soc/amd: introduce and use PSTATE_MSR macroFelix Held2023-02-281-4/+1
| | | | | | | | | | | | | | | | Instead of adding the P-state number to the PSTATE_0_MSR number to get the P-state MSR number for the rdmsr call, provide a macro that directly calculates the MSR number for a given power state. Also drop the unused PSTATE_[1..4]_MSR definitions which also didn't cover all P-state MSRs available in the hardware. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If85acf556efe82c209e1608e56c05f7a2a748403 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* include/device/pci_def.h: Fix typo in commentWerner Zeh2023-02-281-1/+1
| | | | | | | | | | | Fix typo in the comment for Common Clock Configuration. Change-Id: Idd01e787458a9090d53b9a57547b8158480dcc16 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
* cpu/x86/smm: Enable setting SMM console log level from mainboardJohnny Lin2023-02-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a Kconfig RUNTIME_CONFIGURABLE_SMM_LOGLEVEL that enables mainboard to override mainboard_set_smm_log_level for SMM log level. This can let SMM have different log level than other stages for more flexibility. Another reason is that getting certain data that requires searching from flash VPD or CMOS is not very ideal to be done in SMM, so in this change the value can be passed via the member variable in struct smm_runtime and be referenced directly in SMM. One example is that mainboard can get the desired SMM log level from VPD/CMOS, and pass SMM console log level via the variable and in SMM it can be referenced in get_console_loglevel() override function directly. Tested=On OCP Delta Lake, verified SMM log level can be overridden. Change-Id: I81722a4f1bf75ec942cc06e403ad702dfe938e71 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49460 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
* pc80/i8254: Add speaker beep functionMichał Żygowski2023-02-151-0/+1
| | | | | | | | | | | | | Some platforms have an onboard speaker which could be used as an indicator of successful boot or critical error, e.g. in die_notify function. The function assumes that SPKR GPIO is properly configured by the platform code. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I8189b3462bb5140af352fa786db3a6a2a45076f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
* drivers/smmstore: Expose region devicePatrick Rudolph2023-02-121-0/+2
| | | | | | | | | | Allow other drivers to use the SMMSTORE region device. Change-Id: I6316b703829590bd6f41c3d4013b4a4660b9cbab Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* acpi/acpigen: add acpigen_write_store_namestr_to_namestrFelix Held2023-02-101-0/+1
| | | | | | | | | | | | acpigen_write_rom open-codes this functionality, so add a function for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ief25dd854d1639a295c021e9d02c05b4cc61109c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* soc/intel/{common, meteorlake}: Add support for new MCHSridhar Siricilla2023-02-101-0/+1
| | | | | | | | | | | | The patch adds support for new Meteor Lake MCH (ID:0x7d16). TEST=Build and boot the system having MCH ID:0x7d16. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ib0c9ce5c58e4bdec5e7245840f0892d651922cd9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com>
* sb/intel/lynxpoint: Add PCI DIDs for 9 series PCHsAngel Pons2023-02-091-0/+23
| | | | | | | | | | | The desktop 9 series PCHs should be the same as the 8 series PCHs. Change-Id: Iee93fee4f28b88a72c537944159fb7cbb2796235 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* src/acpi: add function gen: if_lgreater_ and namestr assignmentCliff Huang2023-02-091-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | 1. add functions to generate if greater than conditions: acpigen_write_if_lgreater_op_op: if (op1 > op2) acpigen_write_if_lgreater_op_int: if (op > val) acpigen_write_if_lgreater_namestr_int: if (namestr > val) 2. add function to assignal value to a namestr acpigen_write_store_namestr_to_op: namestr = val TEST=Use above functions and check the generated SSDT table after OS boot. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Iffe1b23362a7ab58bdc2aa8daf45cd6f086ee818 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72825 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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