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* util/docker: Add Dockerfile for Arch LinuxHEADmasterFelix Singer2023-05-171-0/+19
| | | | | | | | | | | Add a minimal Dockerfile that pre-installs necessary software which is needed to work with coreboot. Change-Id: I85f3dc7b28b77989f0f1400d1282ed4b17082f65 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* nb/intel/i440bx: Clear memory errors before ending raminitKeith Hui2023-05-171-0/+5
| | | | | | | | | | | | i440BX datasheet says all memory errors reported during RAM init should be ignored. Do as it says. Change-Id: Iaf85fde813aa083ae62218a2df5aec303e3c9f8c Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73952 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/i440bx, mb/asus/p3b-f: Abolish disable_spd()Keith Hui2023-05-173-12/+0
| | | | | | | | | | | | | This hook is specifically for asus/p3b-f so its mainboard code has a chance to put SPD away after RAM init completes. What it intends to do is done when GPO gets programmed in ramstage (and it's safe to do so), and no other board needs this hook, so drop it. Change-Id: Ib7874b4d2b69fdaa5f3c5a3421a62a629c4154a4 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* acpi: Warn on timeout in write_delay_until()Cliff Huang2023-05-171-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make ACPI code print a debug warning message when a timeout is detected in a loop waiting for a condition. This timeout message won't be displayed when this function is used as delay loop (ie. without checking variable condition). The following is required to get this log in kernel log buffer: echo 1 > /sys/module/acpi/parameters/aml_debug_output Here is an example of generated code when waiting for variable L23E to be 0. Local7 = 0x08 While ((Local7 > Zero)) { If ((L23E == Zero)) { Break } Sleep (0x10) Local7-- If ((Local7 == Zero)) { Debug = "WARN: Wait loop timeout for variable L23E" } } BRANCH=firmware-brya-14505.B TEST=Boot to OS and check that the Debug print is added to the function. Change-Id: I3843e51988527e99822017d1b5f653ff2eaa7958 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73348 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* mb/google/nissa/var/pujjo: Add GPIO setting for WWAN_5GLeo Chou2023-05-171-4/+80
| | | | | | | | | | | | | Pujjoteen5 support WWAN 5G device, add GPIO setting for WWAN 5G device BUG=b:281943398 TEST=Build and check serial log Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Ie2e0ea34c54a453645d626f892f50654ef5064ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/75195 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/nissa/var/pujjo: Enable PCIe port 3 for WWAN_5GLeo Chou2023-05-174-1/+48
| | | | | | | | | | | | | Pujjoteen5 support WWAN 5G device, enable PCIe port 3 for WWAN 5G device BUG=b:281943398 TEST=Build and boot on pujjo Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I6d2e8eaecae968ed51095d9497beab492ba7e0c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
* mb/google/brya/variants/hades: Set up internal pull-up for GPIOsEran Mitrani2023-05-171-1/+1
| | | | | | | | | | | BUG=b:280843816 TEST=builds Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I55a85335a34eee227abb6ff355719f7ca2cbf04a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* console: Add format-checking __printf() to die()Nico Huber2023-05-174-13/+6
| | | | | | | | | | | | | Code changes are necessary because `-Wformat` warns about empty format strings by default. Change-Id: Ic8021b70f4cd4875b06f196f88b84940c9a79fe0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75147 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/xeon_sp/spr: Fix format specifier for __LINE__ (%d)Nico Huber2023-05-171-3/+3
| | | | | | | | | Change-Id: I1384a02fa2931002ddd629acef0a4368435cfeb5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* ec/google/chromeec/ACPI: Set TBMC status based on motion sensor presenceMatt DeVillier2023-05-171-1/+5
| | | | | | | | | | | | | | | Use ECRAM field MTNS to determine if motion sensor present, and set TBMC device status accordingly. TEST=build/boot google/{jinlon,drobit}, verify ACPI status for TMBC correct for both devices with and without tablet mode. Change-Id: Ic06ab6d721f0a3435e6dfd7b5e130f378096afec Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/volteer: Use FW_CONFIG to determine correct SOF audio profileMatt DeVillier2023-05-172-7/+28
| | | | | | | | | | | | | | | Use AUDIO PROBE to determine speaker amp config, set SOF driver profile accordingly. TEST=build/boot Win11 on Delbin and Drobit, verify correct audio profile selected, drivers loaded and functional. Change-Id: I13d787cb5ccb74d2774151ccd5deeb45b3364319 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* drivers/sof: Add support for max98373a using port SSP2Matt DeVillier2023-05-172-1/+3
| | | | | | | | | | | | | | Some devices using the MAX98373a smart amp have the speakers connected to port SSP2 vs the default SSP1, so add a configuration item to be able to specify that. TEST=tested with rest of patch train Change-Id: I11d8011c54946aa72a83c73fa88456b4bb5d7d95 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75231 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/sof: Use topology enums where appropriateMatt DeVillier2023-05-172-29/+27
| | | | | | | | | | | Also correct switch intendation, remove excess empty lines. Change-Id: I86026e7f6c0c1c7f3dc6a473bb3afe2f6d32a247 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75230 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/common: Don't hardcode ramtop offsetSean Rhodes2023-05-171-8/+11
| | | | | | | | | | | | | | The `ramtop` can be obtained from the `option.h`, so remove the hardcoded value. Keep the check for the value being byte aligned. Change-Id: I5327b5d4e78b715a85072e5d9a62cf8fd2ae92c0 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74511 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/alderlake: Handle FSP logo paramsSubrata Banik2023-05-171-0/+7
| | | | | | | | | | | | | | This patch overrides FSP-S UPD `LogoPtr/LogoSize` with a valid logo.bmp file if `BMP_LOGO` config is enabled. TEST=Able to see splash screen while booting google/marasov with BMP_LOGO config enable. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I421da2b4dadb892f17a859ce0ec586a2880469eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/75294 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/meteorlake: Handle FSP logo paramsSubrata Banik2023-05-171-0/+7
| | | | | | | | | | | | | | | This patch overrides FSP-S UPD `LogoPtr/LogoSize` with a valid logo.bmp file if `BMP_LOGO` config is enabled. TEST=Able to see splash screen while booting Intel Meteor Lake RVP with BMP_LOGO config enable. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iaba187456dd4dfb2f69d3532e83a3850f31783ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/75198 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* cpu/amd/pi/00730f01/Kconfig: use hexadecimal CPU number in ACPIFelix Held2023-05-161-1/+1
| | | | | | | | | | | | | | | To match the rest of coreboot, also change this ACPI_CPU_STRING Kconfig setting to use hexadecimal CPU numbers for the ACPI CPU objects. Since this SoC has a maximum of 4 cores, this change will make no difference in the runtime behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I58f9c4672f34de0defafc300d2d291f4ad6196ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/75251 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/*/Kconfig: change ACPI_CPU_STRING to use hexadecimal CPU numbersFelix Held2023-05-162-2/+2
| | | | | | | | | | | | | | | | | | | Both the AMD AGESA reference code and the default coreboot ACPI_CPU_STRING use hexadecimal numbers in the ACPI CPU object names, so change the ACPI_CPU_STRING format string in the both the Stoneyridge Kconfig and the common non-CAR AMD SoC config Kconfig which covers all other AMD SoCs in soc/amd. All platforms where the P state and C state SSDT from binaryPI (Stoneyridge) or FSP (Picasso) was used in coreboot before it got replaced by native code, had at most 8 cores/threads, so the mismatch never became apparent. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9d6822c5df01786ee541ce90734b75ed1a761fca Reviewed-on: https://review.coreboot.org/c/coreboot/+/75250 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/google/chromeec: Use host command APICaveh Jalali2023-05-161-430/+88
| | | | | | | | | | | | | | | | Update the chromeec driver to use the EC host command API. Large blocks of repetitive code to set up EC calls are replaced with single function calls to perform the same operation. BUG=b:258126464 BRANCH=none TEST=booted on rex Change-Id: I0317405b1ed0c58568078133c17c8cfbc7c21d80 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73325 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/google/chromeec: Add ec_cmd_api.h, update ec_commands.hCaveh Jalali2023-05-162-96/+558
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The new util/chromeos/update_ec_headers.sh utility is used to update ec_commands.h and introduce ec_cmd_api.h from the chrome EC repo. ec_cmd_api.h is a new file from the chrome EC repo which defines the API for communicating with the EC. It is a companion to the existing ec_commands.h by defining functions corresponding to EC host command opcodes and request/response struct definitions. See $EC/docs/ec-host-command-api.md for details. Generated using update_ec_headers.sh [EC-DIR]. The original include/ec_commands.h version in the EC repo is: 3e35858003 ec: Add another #line directive The original include/ec_cmd_api.h version in the EC repo is: 59de61f2db zephyr: Add support for RNG devices BUG=b:258126464 BRANCH=none TEST=none Change-Id: I30f20e34d31b7e19cf03f65fefd58ae64eef1d41 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73324 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/chromeos: Add EC header update utilityCaveh Jalali2023-05-161-0/+118
| | | | | | | | | | | | | | | | | | | | | | | | | This adds a new utility for copying ec_commands.h and ec_cmd_api.h from the chrome EC repo with the appropriate copyright header adjustment. It is invoked as: util/chromeos/update_ec_headers.sh [EC-repo] where EC-repo is the top of the EC repo from which header files are to be obtained. The corresponding files in src/ec/google/chromeec are updated but not committed. Also, a commit message is suggested with the original git versions for reference. BUG=b:258126464 Change-Id: Ib43c75d807dd925b2c4bff425c07a36b4b4582c4 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Boris Mittelberg <bmbm@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* lib: Perform display init in normal boot mode if BMP_LOGO is setSubrata Banik2023-05-161-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Traditionally, display init during vboot "verified/secure/normal boot mode" relies on the VB2_CONTEXT_DISPLAY_INIT. This is the default behavior for vboot, meaning skip display init during verified boot mode. However, if the intention is to show the OEM splash screen (using BMP_LOGO config) during boot, then the policy enforced by vboot needs to be overridden. This can be done by setting the BMP_LOGO config flag. If BMP_LOGO is not enabled, then the vboot policy will be followed and display init will be skipped. This change was made to allow OEMs to show their splash screen during boot, even if the system is in verified/secure/normal mode. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ice1f02ad5c02a6a7e74a97ed23c5f11c7ecfb594 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75197 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* acpigen: Add printf-like function for debug stringCliff Huang2023-05-162-39/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Generate formatted string and ACPI code to print debug string. For example (with pcie_rp = 1): acpigen_write_debug_sprintf("calling _ON for RP: %u", pcie_rp); generates the following ACPI code: Debug = "calling _ON for RP: 1" With this new function, the following functions are not needed anymore and therefore are removed by this patch. - acpigen_concatenate_string_string() - acpigen_concatenate_string_int() - acpigen_write_debug_concatenate_string_string() - acpigen_write_debug_concatenate_string_int() BRANCH=firmware-brya-14505.B TEST=Add above functions in the acpigen code and check the generated SSDT table after OS boot. Check the debug messages is in the kernel log when /sys/modules/acpi/parameters/aml_debug_output is set to '1'. Change-Id: Id4a42e5854516a22b7bc4559c2ed08680722c5ba Signed-off-by: Cliff Huang <cliff.huang@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Zhixing Ma <zhixing.ma@intel.com> Reviewed-by: Musse Abdullahi <musse.abdullahi@intel.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* x86: pci_io_cfg: Make constant unsigned to fix out of bounds shiftPaul Menzel2023-05-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the error below when running a coreboot image built with `CONFIG_UBSAN=y`. PCI: pci_scan_bus for bus 00 shift out of bounds src/arch/x86/include/arch/pci_io_cfg.h:13:20 ubsan: unrecoverable error. GCC with `-fsanitize=shift` also flags this: runtime error: left shift of 1 by 31 places cannot be represented in type 'int' So, make the constant unsigned. TEST=emulation/qemu-i440fx with `CONFIG_UBSAN=y` stops later with [ERROR] unaligned access src/lib/rmodule.c:152:27 [EMERG] ubsan: unrecoverable error. Change-Id: Ib05d225ab9f22078d765009b4ee6ef0c63231eed Found-by: UBSAN Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/xeon_sp: Drop dummy FADT entryKyösti Mälkki2023-05-161-3/+0
| | | | | | | | | | | Specifying types without addresses for PM1B events is not useful. Change-Id: I839208eaecf689a32484b9154647fc66633e5eef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* device/allocator: Fix format string for resource flags (%lu)Nico Huber2023-05-151-1/+1
| | | | | | | | | | Change-Id: I56ffb82ec417530527ea1ea7e97a593e5bf6b756 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/brya/var/taniks: Update SOF speaker topologyMatt DeVillier2023-05-151-1/+1
| | | | | | | | | | | | | | Taniks uses a 4-channel output config, rather than 2-channel. Update the SOF speaker topology accordingly. TEST=build/boot Win11 on taniks, verify speaker output functional. Change-Id: I3c08b12b11464dcada014289174e0cc468d1c39d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* drivers/sof: Add support for max98357a with 4-ch outputMatt DeVillier2023-05-152-3/+5
| | | | | | | | | | | | | | Will allow boards using this speaker configuration to correctly specify their output type. TEST=tested with rest of patch train Change-Id: Iefcfc928e2611f533af1a2962ec2761ec1b7bf3a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* commonlib: compiler.h: Add __printf macroJeremy Compostella2023-05-151-0/+4
| | | | | | | | | | | | | | | | | | | | This patch adds the `__printf' macro to comply with checkpatch following warning: Prefer __printf(1, 2) over __attribute__((format(printf, 1, 2))) BRANCH=firmware-brya-14505.B TEST=Successful compilation with `__printf(1, 2)' instead of `__attribute__((format(printf, 1, 2)))' Change-Id: Ic2d90478ab0955c2ad0955e8cff5be76bfb2e741 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75159 Reviewed-by: Cliff Huang <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* 3rdparty/blobs: Advance submodule pointerSean Rhodes2023-05-151-0/+0
| | | | | | | | | | | | | | | | | | | | | | This contains the following commits: * 9df5910: mb/starlabs/starbook/adl: Update EC binary to 1.13 * 65c8e9a: soc/mediatek/mt8188: Add scramble switch and fix 1RK register bit * 1a4c51c: soc/mediatek/mt8188: Add scramble switch for dpm version 0.2 * 076cdd1: soc/mediatek/mt8188: Update MCUPM firmware from v1.01.03 to v1.01.04 * 2be5f15: soc/mediatek/mt8186: Update SSPM firmware from v2.0.0 to v2.0.1 * 01ba156: mb/google/skyrim: Add RO SPL table * ce5566f: soc/mediatek/mt8186: Update SSPM firmware from v1.0.0 to v2.0.0 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iee7b479f305b77f4e6ab5e53a0b74cebdc653599 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* mb/google/myst: Re-organize the FMAP layoutKarthikeyan Ramasubramanian2023-05-151-5/+5
| | | | | | | | | | | | | | | | | | By moving certain FW UI assets from RO to RW sections, 4 MiB is sufficient for RO section. Split the resultant available 4 MiB equally between 2 RW sections. This will help in getting to 16 MiB SPI flash for the mainboard. BUG=b:281567816 TEST=Build Myst BIOS image with the updated layout. Cq-Depend: chromium:4519688 Change-Id: I09948ceac0a6a1cb109322fc4856b8b486318664 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75184 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
* mb/msi/ms7d25: Update USB port macrosMichał Żygowski2023-05-151-9/+11
| | | | | | | | | | | | | | | | Update USB port macros: - change onboard ports to SHORT: MYSTIC LIGHT, LAN_USB1, PS2_USB1, HUB to USB 2.0 headers, HUB to rear USB 2.0 - change USB type C header to LONG which caused hard lockups on the port making it unable to enumerate in UEFI Payload and Linux - add empty definitions for USBr ports Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I91198aa713e9084ff3906c267ee1b37b10c71843 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69820 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/dedede/var/taranza: Copy devicetree and GPIO from var/dibbi4.20Sheng-Liang Pan2023-05-154-18/+334
| | | | | | | | | | | | | | | copy from dibbi since taranza base on dibbi,this is only for first initial configuration, will update the more setting afterward. BUG=b:277664211 BRANCH=dedede TEST=build Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ia319f65897c0fea2f0558c20a5bc36bb6fbaea96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
* mb/google/dedede/var/taranza: Generate SPD ID for supported partsSheng-Liang Pan2023-05-153-2/+11
| | | | | | | | | | | | | | | Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. BUG=b:277664211 BRANCH=dedede TEST=build Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I6bbb67ccdd8ebc21719921d00320907f8dbb285f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74933 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* docs/releases/4.20: Update release notesFelix Singer2023-05-152-43/+180
| | | | | | | | | | | Change-Id: If5627cef5293c160e91ff85297abe695064f1bd1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74981 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* docs/releases: Add 4.21 release notes templateFelix Singer2023-05-142-1/+52
| | | | | | | | | | | Change-Id: Ibb4eaba6be088e20c76a8329847148c1d4ff8c04 Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75187 Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* docs/vboot: Update list of boards supported by vbootFelix Singer2023-05-141-8/+21
| | | | | | | | | | Change-Id: Ib797c17183ca48131713288c618c4c20496583fb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75215 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
* acpi/acpigen: add comment about byte 0 in acpigen_resource_*wordFelix Held2023-05-141-0/+3
| | | | | | | | | | | | | | | | | | | | | Since it's not obvious, add comments to acpigen_resource_word, acpigen_resource_dword and acpigen_resource_qword to clarify out what the magic number in byte 0 means. The most significant bit of byte 0 indicates if it is a small or large resource data type. In the case of the MSB being 0, it's a small resource data type (aka type 0), and the other bits encode bit the type and size of the item; if the MSB is 1, it's a large resource data type (aka type 1), and the other bits just encode the type and there are two separate bytes to encode the size. Beware that the large resource's data type values in the ACPI specification don't include the MSB that's set, but only the 7 lower bits. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia6a6c9fb1bcde232122bb5899b9a0983ef48e12b Reviewed-on: https://review.coreboot.org/c/coreboot/+/75158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* arch/x86/ioapic.c: Increase the number of bits for ioapic IDArthur Heymans2023-05-141-1/+6
| | | | | | | | | | | In practice hardware can use larger numbers. Change-Id: I6e9ddd1ebd396c37e25eb3019f981d45d9c5e062 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki.2011@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* mb/google/rex: Add variant specific SOC chip config update functionAnil Kumar2023-05-142-0/+13
| | | | | | | | | | | | | This patch adds support for variant specific chip config update similar to commit 061a93f93d2 ("mb/google/brya: Add variant specific soc chip config update"). Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I60a4042cba608fd527527af9340ec0215f3086ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/75046 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/rex/var/screebo: Add initial devicetree configKun Liu2023-05-142-3/+343
| | | | | | | | | | | | | add initial devicetree config for screebo BUG=b:276814951 TEST=emerge-rex coreboot Change-Id: Ie64d0e50ec22b3e363597af64eb723ef1f86dfa8 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/corsola: Add support for MIPI panelRuihai Zhou2023-05-146-120/+314
| | | | | | | | | | | | | | | | | | | | | The detachable Starmie will use MIPI panels, which require reading serializable data from the CBFS. So we add MIPI panel support to the display configuration and align the configuration sequence with the panels that use MIPI bridges. The PMIC Datasheet: TPS65132-Single-Inductor-Dual-Output-Power-Supply.pdf BUG=b:275470328 BRANCH=corsola TEST=emerge-corsola coreboot chromeos-bootimage and display normally Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I6f079e54f0317ff2f685f0e3834ebd1ceb8e9fcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/74051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/facebook/fbg1701/board_mboot.h: Remove config from mb_log_listFrans Hendriks2023-05-141-1/+0
| | | | | | | | | | | | | | | | | | Error message ´Cannot map compressed file config without cbfs_cache' is reported. Compressed parts of CBFS can not be used during bootblock stage. Remove config from mb_log_list. Will be added to verified items by CB:74752. BUG=NA TEST=booting and verify log on facebook FBG1701 Change-Id: Iacf023bc8b9c2ebc66137c4ea683589751a30d2f Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/nissa/var/uldren: Add wifi sar tableDtrain Hsu2023-05-143-0/+10
| | | | | | | | | | | | | | | Add wifi sar table for uldren BUG=b:279679700 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I9e3d7a06beb673b204f2dfe8e7beb919730aa885 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
* screebo: fix the lp5ccc config from 0x55 to 0xaaSimon Zhou2023-05-141-1/+1
| | | | | | | | | | | BUG=b:278022971 TEST=verified on screebo Change-Id: I16f1d66ca7f885120358eb2a2d3c6fb111319f11 Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75173 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/phoenix/Kconfig: Update default soft fuse bitsFred Reitberger2023-05-141-1/+1
| | | | | | | | | | | Set the default soft fuse bits to the recommended values Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I2354aefe90a08eaef95a68926806d11a9118c3de Reviewed-on: https://review.coreboot.org/c/coreboot/+/75183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/myst/Kconfig: Select SPI_FLASH_EXIT_4_BYTE_ADDR_MODEFred Reitberger2023-05-141-0/+1
| | | | | | | | | | | | When using a 32-MiB ROM chip, the ABL leaves the SPI flash in 4-byte addressing mode, so ensure the driver exits that mode for regular operation. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9a846be743a65ffe5b3ef94e20e0b5fc5e273961 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* sb/intel/bd82x6x,ibexpeak: Move UPRWC definitionKyösti Mälkki2023-05-142-8/+10
| | | | | | | | | | Locate it with all the other PM IO registers. Change-Id: I779b2e313c9d8370c66c4adb4f6f4d4cf5b4e7dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* sb/intel/lynxpoint: Remove GPE0_{EN,STS}_2 definesKyösti Mälkki2023-05-143-8/+6
| | | | | | | | | | | By ACPI specification, those follow GPE0_EN bits in the register space. Use sizeof() to replace the 2/4 offset previously used. Change-Id: I27ada0b19b2cf5e8eca71f48bf103dcab1b3cc11 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Makefile.inc: Warn about set but unused variables with GCCArthur Heymans2023-05-141-2/+0
| | | | | | | | | | | | | Clang was already warning about this. Synchronize the behaviour between both compilers. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I3331a7437b17ab5ac97cef94511bb29c020bdff0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75032 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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