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* mb/google/dedede/var/taranza: Copy devicetree and GPIO from var/dibbi4.20Sheng-Liang Pan2023-05-154-18/+334
| | | | | | | | | | | | | | | copy from dibbi since taranza base on dibbi,this is only for first initial configuration, will update the more setting afterward. BUG=b:277664211 BRANCH=dedede TEST=build Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ia319f65897c0fea2f0558c20a5bc36bb6fbaea96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
* mb/google/dedede/var/taranza: Generate SPD ID for supported partsSheng-Liang Pan2023-05-153-2/+11
| | | | | | | | | | | | | | | Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. BUG=b:277664211 BRANCH=dedede TEST=build Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I6bbb67ccdd8ebc21719921d00320907f8dbb285f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74933 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/boxy: Disable EXT_VRKevin Yang2023-05-111-0/+3
| | | | | | | | | | | | | | The boxy removed the APW8738BQBI-TRG and "disable_external_bypass_vr" should be set to "1" to disable BUG=b:271407334 TEST=emerge-dedede coreboot Signed-off-by: Kevin Yang <kevin3.yang@lcfc.corp-partner.google.com> Change-Id: Ic6667e93de41e84f67363ab7554fe755fe50684a Reviewed-on: https://review.coreboot.org/c/coreboot/+/74889 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/boxy: Update devicetree and GPIO tableKevin Yang2023-05-113-18/+270
| | | | | | | | | | | | | | | | | | | | | | Create overridetree and GPIO config based on latest schematic: 1. Update PCIe ports 2. Update USB ports 3. Remove unused I2Cs 4. Remove unused peripherals (SD card, eDP, speakers) 5. Add LAN 6. Thermal policy for updated temp sensors BUG=b:277529068 BRANCH=dedede TEST=build Signed-off-by: Kevin Yang <kevin3.yang@lcfc.corp-partner.google.com> Change-Id: I5a155ebca50dbd5bdb046713ebabbee395361273 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74626 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
* mb/google/dedede: Add SOF chip driverMatt DeVillier2023-05-042-1/+28
| | | | | | | | | | | | | | | | Add all SOF chip drivers to baseboard and use FW_CONFIG to determine the correct option, to ensure the correct audio config is passed to the SOF OS drivers. TEST=build, boot Windows on several dedede variants, verify audio functional under Windows using coolstar's SOF drivers. Change-Id: I9452b11af614d8727aa8dd448e37f7a06faa450d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74818 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* mb/google/dedede/var/boxy: Generate SPD ID for supported memory partkevin3.yang2023-04-223-2/+15
| | | | | | | | | | | | | | | | | | | Add boxy supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K4U6E3S4AB-MGCL 2. Hynix H54G46CYRBX267 3. Micron MT53E512M32D1NP-046 WT:B BUG=b:278983561 TEST=Use part_id_gen to generate related settings Signed-off-by: kevin3.yang <kevin3.yang@lcfc.corp-partner.google.com> Change-Id: I317f2b31774627706babdea10776af05ab692d1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
* mb/google/dedede: Create boxy variantkevin3.yang2023-04-218-0/+84
| | | | | | | | | | | | | | | | | | | Create the boxy variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:277529068 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_BOXY Change-ID: Ief22eb000421c23abf6de3f99eb860bdae1e7919 Signed-off-by: kevin3.yang <kevin3.yang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* Makefiles: Drop redundant VARIANT_DIR definitionsKyösti Mälkki2023-04-171-1/+0
| | | | | | | | Change-Id: Ie75ce1eee3179a623da812a6b76c7ec457684177 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/dedede/var/boten: Generate SPD ID for supported memory partkevin3.yang2023-04-173-1/+3
| | | | | | | | | | | | | | | | Add boten supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K4U6E3S4AB-MGCL BUG=b:278138388 TEST=Use part_id_gen to generate related settings Signed-off-by: kevin3.yang <kevin3.yang@lcfc.corp-partner.google.com> Change-Id: I5f910393847c6494f77c009cb11f50b31bebffb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/dedede/var/kracko: Add G2touch touchscreen supportRobert Chen2023-04-141-0/+14
| | | | | | | | | | | | | | | | Add G2touch touchscreen support for kracko. BOE NV116WHM-T04 V8.0 with G7500 touch panel sensor IC BUG=b:277852921 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot & test on DUT Change-Id: Ic065d5dc2900c6ccfee09031f7a80cefc391f5dd Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74307 Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede: Create taranza variantDavid Wu2023-04-138-0/+81
| | | | | | | | | | | | | | | | | | Create the taranza variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:277664211 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_TARANZA Change-Id: Id64e48ff2acd6e827fe586a00376183930ddc7e1 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74295 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/kracko: Add fw_config probe for ALC5682-VD/ALC5682-VSRobert Chen2023-03-311-1/+25
| | | | | | | | | | | | | | | | | | ALC5682-VD/ALC5682-VS use different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:275644832 TEST=emerge-dedede coreboot BRANCH=firmware-dedede-13606.B Change-Id: I644f3aa3187e08146d78abb70a568833bc9b9211 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/dedede/var/magolor: Add FW_CONFIG probe for EXT_VRMorris Hsu2023-03-222-0/+15
| | | | | | | | | | | | | Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on magolor. BUG=b:223687184 TEST=emerge-dedede coreboot chromeos-bootimage and pass suspend_test and firmware_ConsecutiveBoot test Change-Id: I47ad313c4a14edb687913698986df9ece6cd721d Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73833 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede: Add EC_HOST_EVENT_PANIC to SCI maskRob Barnes2023-03-151-1/+2
| | | | | | | | | | | | | | | | | | Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the Kernel when an EC panic occurs. If system safe mode is also enabled on the EC, the kernel will have a short period to extract and save info about the EC panic. BUG=b:268377440 BRANCH=firmware-dedede-13606.B TEST=Observe kernel ec panic handler run when ec panics Change-Id: I24f929ae60a406d0091956dc6cab3e2876ca23e9 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/dedede/var/dibbi: Configure I2C times for audioAmanda Huang2023-03-141-1/+6
| | | | | | | | | | | | | | | | Configure the I2C bus high and low time for audio. BUG=b:271804915 BRANCH=dedede TEST=Build and confirm I2C clock for audio is between 380 kHz and 400 kHz Change-Id: I2987a39abc5527844424edfa1cf70d5c5cea5357 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/dedede/var/kracko: Generate new SPD ID for new memory partsRobert Chen2023-03-093-1/+5
| | | | | | | | | | | | | | | Add new memory parts in memory_parts_used.txt and generate SPD id for these parts: Hynix H54G46CYRBX267 Samsung K4U6E3S4AB-MGCL BUG=b:272173189 TEST=run part_id_gen to generate SPD id Change-Id: I141bda6eda3f658ca608c86ad0b320d018598514 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73554 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/dibbi: Improve USB2 strengthAmanda Huang2023-02-271-4/+40
| | | | | | | | | | | | BUG=b:269786649 TEST=build and test USB2 port function works fine BRANCH=dedede Change-Id: I63928a0d8ce6b2365250fd96572f4a2db948c19d Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* mb/google/dedede/var/dibbi: Enable USB2 port 6Sam McNally2023-02-221-0/+1
| | | | | | | | | | | | | | | | | USB2 port 6 may be used for a PL2303 USB to UART bridge, so enable the port. BUG=b:269690930 TEST=kernel can detect a PL2303 USB device BRANCH=dedede Change-Id: I0ba421c3a502e69d101de40bbd31122211d3fb05 Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
* mb/google/dedede/var/dibbi: Update devicetree for enabling audioSam McNally2023-02-171-1/+2
| | | | | | | | | | | | | | | | Enable HDA device and update jack codec HID from ALC5682I-VD to ALC5682I-VS. BUG=b:268309238 TEST=kernel detects audio DSP and rt5682s BRANCH=dedede Change-Id: Icd17d5009ab8ef4711bb6c5fa414a8188fc0912f Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/dedede/var/dibbi: Update gpio tableAmanda Huang2023-02-091-0/+3
| | | | | | | | | | | | | | | | Config GPP_B9 as LAN_CLKREQ_ODL based on latest schematic BUG=265021899 BRANCH=dedede TEST=emerge-dedede coreboot Change-Id: Ia099bd64364b46240e0426aa57dfe8d230e7494d Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Liam Flaherty <liamflaherty@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* tree: Drop repeated wordsAlexander Goncharov2023-02-071-1/+1
| | | | | | | | | | | | | Found-by: linter Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/dibbi: Update devicetree and GPIO tableLiam Flaherty2023-02-024-17/+287
| | | | | | | | | | | | | | | | | | | | | | Create overridetree and GPIO config based on latest schematic: 1. Update PCIe ports 2. Update USB ports 3. Remove unused I2Cs 4. Remove unused peripherals (SD card, eDP, speakers) 5. Add LAN 6. Thermal policy for updated temp sensors BUG=b:260934185, b:260934719 BRANCH=dedede TEST=build Change-Id: I4789be2eee1d01288031bc1e8ee5c9d6df71f9fe Signed-off-by: Liam Flaherty <liamflaherty@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71882 Reviewed-by: Adam Mills <adamjmills@google.com> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/i2c/generic: Drop 'disable_gpio_export_in_crs' flagMatt DeVillier2023-01-158-16/+0
| | | | | | | | | | | | | | | | | | | | | | | Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the OS driver and ACPI thinking they own the GPIO. This can cause timing problems because it's not clear which system should be controlling the GPIO. Previously, we flagged as an error any device which set the 'has_power_resource' flag but did not set 'disable_gpio_export_in_crs.' There's no reason to require explicit disablement however, so drop the superfluous 'disable' flag, and change the _CRS generation to check if the GPIOs will be exported via the 'has_power_resource' flag instead. BUG=b:265055477 TEST=build/boot skyrim, dump SSDT and verify touchscreen GPIOs only listed under PRx, not under _CRS. Change-Id: I837ae6c6fe4b8e1c4e10686406cba06bdb7759d2 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* mb/google/dedede/var/dibbi: Generate SPD ID for supported partsLiam Flaherty2023-01-103-2/+11
| | | | | | | | | | | | | | | | | Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. BUG=b:260934724, b:255447299 BRANCH=dedede TEST=build Change-Id: I8c95ced79e14bb4a99aa1fa5f4fc3bc0681cc1cc Signed-off-by: Liam Flaherty <liamflaherty@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71710 Reviewed-by: Adam Mills <adamjmills@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede: Use runtime detection for touchscreensMatt DeVillier2023-01-0919-49/+49
| | | | | | | | | | | | | | | | | | Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. BUG=b:121309055 TEST=build/boot Windows/linux on multiple dedede variants, verify all touchscreens functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I91e03bd1d96a6b2f0c3813665910133db0d6c308 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/google/dedede: Set touchscreen IRQs to LEVEL vs EDGEMatt DeVillier2023-01-095-7/+7
| | | | | | | | | | | | | The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: I212533ffdfb05f841e722c130b52c2976272e670 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/google/dedede: Implement touchscreen power sequencingMatt DeVillier2023-01-094-4/+62
| | | | | | | | | | | | | | | | | | | | | For touchscreens on dedede variants, drive the enable GPIO high starting in romstage, then disable the reset GPIO in ramstage. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). Since the fast majority of dedede variants have a touchscreen option, and those that do use the same GPIOs for enable/reset, set the GPIOs for touchscreen operation in the baseboard and then override for the few (3) variants that do not have a touchscreen. BUG=b:121309055 TEST=tested with rest of patch train Change-Id: Ib95e23545cc3e8589ddbd9e18cd0533bec9333e0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/google/dedede: Add method to set GPIOs in romstageMatt DeVillier2023-01-094-0/+13
| | | | | | | | | | | | | | | Add method variant_romstage_gpio_table() with empty weak implementation to allow variants to override as needed for touchscreen power sequencing (to be implemented in a subsequent commit). Call method in romstage to program any GPIOs the variant may need to set. TEST=tested with rest of patch train Change-Id: Ic216827a4b53d1d35913efca63a43d4672791c54 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/google/dedede: Create dibbi variantLiam Flaherty2023-01-088-0/+81
| | | | | | | | | | | | | | | | | Create the dibbi variant of the waddledee reference board by copying the template files to a new directory. BUG=b:260934018 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a includes GOOGLE_DIBBI Change-Id: I3b8d4e7f8a53323f56567cbbc03bab7f8804f286 Signed-off-by: Liam Flaherty <liamflaherty@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71709 Reviewed-by: Adam Mills <adamjmills@google.com> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede: update ACPI HID/CID for Synaptics touchpadsMatt DeVillier2022-12-229-9/+18
| | | | | | | | | | | | | | | | The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=boot Linux 5.1x, Windows 10 on drawcia, verify all touchpad functions work correctly. Change-Id: I43eb5bc394a3fbfd4109f2e6c274ec66fc01d46d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* treewide: Include <device/mmio.h> instead of <arch/mmio.h>Elyes Haouas2022-12-102-4/+4
| | | | | | | | | | | | | <device/mmio.h>` chain-include `<arch/mmio.h>: https://doc.coreboot.org/contributing/coding_style.html#headers-and-includes Also sort includes while on it. Change-Id: Ie62e4295ce735a6ca74fbe2499b41aab2e76d506 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/dedede/variants/sasukette: Disable PCIE RP8 and CLKSRC4zhourui2022-11-301-0/+4
| | | | | | | | | | | | | | | | | | This change disables unused PCIE RP8 and CLKSRC4. Without this change sasukette cannot enter into s0ix properly. BUG=b:259891452 TEST=Build and verified in sasukette Change-Id: I61bcefa128d4f39613a760b647048f9e19e262c2 Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* ec/google/chromeec: Remove EC_HOST_EVENT_USB_CHARGERCaveh Jalali2022-11-192-2/+0
| | | | | | | | | | | | | | | | | EC_HOST_EVENT_USB_CHARGER is no longer defined by the EC, so remove all references. BUG=b:216485035,b:258126464 BRANCH=none TEST=none Change-Id: I9e3e0e9b45385766343489ae2d8fc43fb0954923 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* drivers/i2c/sx9324: Add support for Linux's SX9324 driverVictor Ding2022-11-091-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SX9324 driver is updated per Linux's documentation found at https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml Supporting logic for the deprecated SX932x driver is hence guarded by DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER This patch by itself does not introduce functional changes to any board. The legacy SX932x Linux driver never reached upstream Linux and is only available in ChromeOS kernel fork of 4.4 and 5.4. Linux later accepted a different implementation named SX9324 and has been available since 5.4. Ideally all variants should adopt the new driver; however, during the transition phase, coreboot must support both drivers. It is better to have a single firmware build that can work with both Linux kernel drivers by specifying both sets of properties. Legacy driver support should be deleted once all variants finish migration. BUG=b:242662878 TEST=Dump ACPI SSDT then verify _DSD entries related to the legacy SX932x driver are identical w/ and w/o this patch (Tested on Craask and Nivviks) Change-Id: I42cd6841c3a270c242ed2e739db245e858eadb3b Signed-off-by: Victor Ding <victording@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69192 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google: Probe p-sensor only for selected variantsVictor Ding2022-11-072-2/+6
| | | | | | | | | | | | | | | | | Only a subset of variants has proximity sensors. This patch by itself does not introduce functional changes to any board. It is mainly to ease migrating SX9324 from the legacy driver to the linux one - allowing gradual migration variant by variant. BUG=b:242662878 TEST=Dump ACPI SSDT then verify they are identical w/ and w/o this patch Change-Id: Ic00e0d9eafcef2c9eaf32571fecf6190777cec36 Signed-off-by: Victor Ding <victording@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69191 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede: add VBTs for drawcia, mangolor variantsMatt DeVillier2022-10-207-0/+6
| | | | | | | | | | | | | | | Add VBT data files, ensure secondary VBTs compiled in as needed, select INTEL_GMA_HAVE_VBT. TEST=build/boot drawcia, mangolor variants with FSP/GOP display init and edk2 payload Change-Id: I58a2ed59bd858ce772e92f6659d341036823b11a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/dedede/var/storo: Disable PCIE RP8 and CLKSRC4Zanxi Chen2022-10-181-0/+4
| | | | | | | | | | | | | | | | | | This change disables unused PCIE RP8 and CLKSRC4. Without this change storo cannot enter into s0ix properly. BUG=b:219376808 TEST=Built and verified in storo Change-Id: I9867825ce53de72ef73920c153002bc3be4dbd2d Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-by: Jamie Chen <jamie.chen@intel.corp-partner.google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Reviewed-by: Aamir Bohra <aamirbohra@google.com>
* mainboard/google: Remove ACPI ALS deviceGwendal Grignou2022-10-181-3/+0
| | | | | | | | | | | | | | | | | | | Remove the ACPI ALS device from the EC configuration for newer devices, because some do not have light sensors, and those who do have their ALS presented through the new EC sensor interface already. Inspired from commit ("f13e2501525f ("UPSTREAM: mainboard/google/eve: Remove ACPI ALS device") BUG=b:253967865 BRANCH=none TEST=Boot a device and ensure that 'acpi-als' device is not present in /sys/bus/iio/devices. Change-Id: Ibcfa9e8c5a4679d557150998fd255789d3f8a272 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68493 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/beadrix: Update SoC gpio pin of USB cameraTeddy Shih2022-10-181-2/+2
| | | | | | | | | | | | | | | | | | | Update SoC GPIO setting of camera according to beadrix schematics. GPP_D13 : NC -> PLTRST (EN_PP2800_CAMERA) BRANCH=dedede BUG=b:247178737,b:244120730 TEST=on beadrix, validated by beadrix seconds_system_resume < 500 ms. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Id00cb85cdad900c03842ad69707966aa62410efd Reviewed-on: https://review.coreboot.org/c/coreboot/+/68129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Simon Yang <simon1.yang@intel.com> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
* mb/google/dedede: Guard FMD selection with CHROMEOSMatt DeVillier2022-10-171-2/+2
| | | | | | | | | | | | | Allows dedede boards to use coreboot-generated FMAP layout when building for non-ChromeOS target. TEST=build/boot dedede with edk2 payload, non-ChromeOS build Change-Id: Icb975455cde0d75a5af9130ba3e82a4fb0df5613 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/dedede/var/pirika: Add fw_config probe for ALC5682-VD & VSFrankChu2022-10-171-1/+26
| | | | | | | | | | | | | | | | | | | | ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:244620955 TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ia6cb56e76bc4e245a32f29b19226fa4fae330c92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
* mb/google/dedede: rename baseboard GPIO table getter for clarityMatt DeVillier2022-09-273-3/+3
| | | | | | | | | | | | | | Rename variant_base_gpio_table() to baseboard_gpio_table(), since the GPIO table comes from the baseboard, and is overridden by a separate table from the variant. Drop the __weak qualifier as this function is not overridden. Change-Id: I11814016d654bc2c2e6d24b3d18fb30d5b843fe9 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/{google,intel}/*/ec: Decrease loglevel of init messages to BIOS_INFOElyes Haouas2022-09-231-1/+1
| | | | | | | | | | | | | BIOS_ERR is inappropriate since the init message is informational. Use BIOS_INFO instead. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I6fc15291a6d177a1b9e258d08e165224e5e10b32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67733 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/dedede: Resume from suspend on critical batteryIvan Chen2022-09-201-1/+5
| | | | | | | | | | | | | | | | | | | | | | This patch makes dedede EC wake up AP from s0ix when the state of charge drops to low_battery_shutdown_percent. Demonstrated as follows: 1. Boot OS. 2. Run powerd_dbus_suspend. 3. On EC, run battfake 4. 4. System resumes. BUG=b:244253629 TEST=Verified on dedede Change-Id: I39234d2b9e739383b5f96be49077f8c9831fa0fa Signed-off-by: Ivan Chen <yulunchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/dedede/var/boten: Turn off camera during S0ixKarthikeyan Ramasubramanian2022-09-201-0/+9
| | | | | | | | | | | | | | | | | | Add a variant specific S0ix hook to fill the SSDT table to disable and enable camera during suspend and resume respectively. BUG=b:206911455 TEST=Build Boten BIOS image. Ensure that camera is disabled during suspend and enabled during resume. Change-Id: I3229b22b8d8651bf2d9df25b10ce6749efde7cf6 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
* mb/google/dedede/variants/shotzo: Turn off LAN power in S0ixTony Huang2022-09-142-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Turn off the LAN power which is controlled by GPP_A10 in S0ix states. For an USB device, the S0ix hook is needed for the on/off operationas to take place. BUG=b:245426120 BRANCH=firmware-dedede-13606.B TEST=emerge-shotzo coreboot check LAN LED off in S0ix states check LAN function ok after suspending 500 loops check SSDT table has MS0X entry Scope (\_SB) { Method (MS0X, 1, Serialized) { If ((Arg0 == One)) { \_SB.PCI0.CTXS (0x41) } Else { \_SB.PCI0.STXS (0x41) } } } Change-Id: I3fcab4a73239b4f006839c0c81e9b4cc74047b77 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/dedede: Generate MS0X entry and provide variant hookTony Huang2022-09-132-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | BUG=b:245426120 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot check SSDT table has MS0X entry Scope (\_SB) { Method (MS0X, 1, Serialized) { If ((Arg0 == One)) {} Else { } } } Change-Id: Id01089531503e62231c5ab19e4cd8056198b9acb Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/dedede/var/shotzo: Config I2C times for touchscreen/audioTony Huang2022-09-091-0/+10
| | | | | | | | | | | | | | | | | Config I2C high / low time in device tree to ensure I2C CLK runs accurately at I2C_SPEED_FAST (400 kHz). EE measured touchscreen/audio runs at 385.5/397.9kHz after tuning. BUG=b:244403643 BRANCH=firmware-dedede-13606.B TEST=Build and check after tuning I2C clock is under 400kHz Change-Id: I7d9503e5f92295432e31f09ae791eaa18eac9d4d Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
* mb/*/{device,override}tree: Set touchpads to use detect (vs probed) flagMatt DeVillier2022-09-0924-45/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | Historically, ChromeOS devices have worked around the problem of OEMs using several different parts for touchpads/touchscreens by using a ChromeOS kernel-specific 'probed' flag (rejected by the upstream kernel) to indicate that the device may or may not be present, and that the driver should probe to confirm device presence. Since c636142b, coreboot now supports detection for i2c devices at runtime when creating the device entries for the ACPI/SSDT tables, rendering the 'probed' flag obsolete for touchpads. Switch all touchpads in the tree from using the 'probed' flag to the 'detect' flag. Touchscreens require more involved power sequencing, which will be done at some future time, after which they will switch over as well. TEST: build/boot at least one variant for each baseboard in the tree. Verify touchpad works under Linux and Windows. Verify only a single touchpad device is present in the ACPI tables. Change-Id: I47c6eed37eb34c044e27963532e544d3940a7c15 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67305 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/dedede/var/shotzo: Update DPTF parametersTony Huang2022-09-041-0/+52
| | | | | | | | | | | | | | Update DPTF parameters from internal thermal team. BUG=b:244373677 BRANCH=firmware-dedede-13606.B TEST=Build image and verified by thermal team. Change-Id: I8415e0d25a79764f0c1d11688728b7caa3b3d6a4 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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