diff options
Diffstat (limited to 'libc/sysdeps/sparc/sparc32/sparcv9')
35 files changed, 1252 insertions, 120 deletions
diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/addmul_1.S b/libc/sysdeps/sparc/sparc32/sparcv9/addmul_1.S index 563bfb1c0..7ba81d8a6 100644 --- a/libc/sysdeps/sparc/sparc32/sparcv9/addmul_1.S +++ b/libc/sysdeps/sparc/sparc32/sparcv9/addmul_1.S @@ -1 +1,81 @@ -#include <sparcv8/addmul_1.S> +! SPARC v9 32-bit __mpn_addmul_1 -- Multiply a limb vector with a limb +! and add the result to a second limb vector. +! +! Copyright (C) 2013 Free Software Foundation, Inc. +! This file is part of the GNU C Library. +! Contributed by David S. Miller <davem@davemloft.net> +! +! The GNU C Library is free software; you can redistribute it and/or +! modify it under the terms of the GNU Lesser General Public +! License as published by the Free Software Foundation; either +! version 2.1 of the License, or (at your option) any later version. +! +! The GNU C Library is distributed in the hope that it will be useful, +! but WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! Lesser General Public License for more details. +! +! You should have received a copy of the GNU Lesser General Public +! License along with the GNU C Library; if not, see +! <http://www.gnu.org/licenses/>. + +#include <sysdep.h> + +#define res_ptr %i0 +#define s1_ptr %i1 +#define sz_arg %i2 +#define s2l_arg %i3 +#define sz %o4 +#define carry %o5 +#define s2_limb %g1 +#define tmp1 %l0 +#define tmp2 %l1 +#define tmp3 %l2 +#define tmp4 %l3 +#define tmp64_1 %g3 +#define tmp64_2 %o3 + +ENTRY(__mpn_addmul_1) + save %sp, -96, %sp + srl sz_arg, 0, sz + srl s2l_arg, 0, s2_limb + subcc sz, 1, sz + be,pn %icc, .Lfinal_limb + clr carry + +.Lloop: + lduw [s1_ptr + 0x00], tmp1 + lduw [res_ptr + 0x00], tmp3 + lduw [s1_ptr + 0x04], tmp2 + lduw [res_ptr + 0x04], tmp4 + mulx tmp1, s2_limb, tmp64_1 + add s1_ptr, 8, s1_ptr + mulx tmp2, s2_limb, tmp64_2 + sub sz, 2, sz + add res_ptr, 8, res_ptr + add tmp3, tmp64_1, tmp64_1 + add carry, tmp64_1, tmp64_1 + stw tmp64_1, [res_ptr - 0x08] + srlx tmp64_1, 32, carry + add tmp4, tmp64_2, tmp64_2 + add carry, tmp64_2, tmp64_2 + stw tmp64_2, [res_ptr - 0x04] + brgz sz, .Lloop + srlx tmp64_2, 32, carry + + brlz,pt sz, .Lfinish + nop + +.Lfinal_limb: + lduw [s1_ptr + 0x00], tmp1 + lduw [res_ptr + 0x00], tmp3 + mulx tmp1, s2_limb, tmp64_1 + add tmp3, tmp64_1, tmp64_1 + add carry, tmp64_1, tmp64_1 + stw tmp64_1, [res_ptr + 0x00] + srlx tmp64_1, 32, carry + +.Lfinish: + jmpl %i7 + 0x8, %g0 + restore carry, 0, %o0 +END(__mpn_addmul_1) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile index ee9f6ffce..0d92813d7 100644 --- a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile @@ -1,11 +1,15 @@ ifeq ($(subdir),math) +libm-sysdep_routines += s_ceil-vis2 s_ceilf-vis2 \ + s_floor-vis2 s_floorf-vis2 ifeq ($(have-as-vis3),yes) libm-sysdep_routines += m_copysignf-vis3 m_copysign-vis3 s_ceilf-vis3 \ s_ceil-vis3 s_fabs-vis3 s_fabsf-vis3 s_floor-vis3 \ s_floorf-vis3 s_llrintf-vis3 s_llrint-vis3 \ s_rintf-vis3 s_rint-vis3 w_sqrt-vis3 w_sqrtf-vis3 \ s_fminf-vis3 s_fmin-vis3 s_fmaxf-vis3 s_fmax-vis3 \ - s_fmaf-vis3 s_fma-vis3 + s_fmaf-vis3 s_fma-vis3 s_fdimf-vis3 s_fdim-vis3 \ + s_nearbyint-vis3 s_nearbyintf-vis3 s_truncf-vis3 \ + s_trunc-vis3 sysdep_routines += s_copysignf-vis3 s_copysign-vis3 endif endif diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis2.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis2.S new file mode 100644 index 000000000..94388003d --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis2.S @@ -0,0 +1,61 @@ +/* ceil function, sparc32 v9 vis2 version. + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* 'siam' (Set Interval Arithmetic Mode) is used to quickly override + the rounding mode during this routine. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value and, + with suitable 'siam' initiated rouding mode settings, round + the final result in the proper direction. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__ceil_vis2) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o0, 32, %o0 + or %o0, %o1, %o0 + stx %o0, [%sp + 72] + sllx %o2, 32, %o2 + fzero ZERO + ldd [%sp + 72], %f0 + fnegd ZERO, SIGN_BIT + stx %o2, [%sp + 72] + fabsd %f0, %f14 + ldd [%sp + 72], %f16 + fcmpd %fcc3, %f14, %f16 + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + for %f16, SIGN_BIT, %f16 + siam (1 << 2) | 2 + faddd %f0, %f16, %f18 + siam (1 << 2) | 0 + fsubd %f18, %f16, %f18 + siam (0 << 2) + retl + for %f18, SIGN_BIT, %f0 +END (__ceil_vis2) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S index 0c2140d95..aebff5cae 100644 --- a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S @@ -19,27 +19,21 @@ #include <sysdep.h> - /* Since changing the rounding mode is extremely expensive, we - try to round up using a method that is rounding mode - agnostic. + /* 'siam' (Set Interval Arithmetic Mode) is used to quickly override + the rounding mode during this routine. We add then subtract (or subtract than add if the initial value was negative) 2**23 to the value, then subtract it back out. - This will clear out the fractional portion of the value. - One of two things will happen for non-whole initial values. - Either the rounding mode will round it up, or it will be - rounded down. If the value started out whole, it will be - equal after the addition and subtraction. This means we - can accurately detect with one test whether we need to add - another 1.0 to round it up properly. + This will clear out the fractional portion of the value and, + with suitable 'siam' initiated rouding mode settings, round + the final result in the proper direction. - VIS instructions are used to facilitate the formation of - easier constants, and the propagation of the sign bit. */ + We also use VIS3 moves to avoid using the stack to transfer + values between float and integer registers. */ #define TWO_FIFTYTWO 0x43300000 /* 2**52 */ -#define ONE_DOT_ZERO 0x3ff00000 /* 1.0 */ #define ZERO %f10 /* 0.0 */ #define SIGN_BIT %f12 /* -0.0 */ @@ -47,32 +41,22 @@ ENTRY (__ceil_vis3) sethi %hi(TWO_FIFTYTWO), %o2 sllx %o0, 32, %o0 - sethi %hi(ONE_DOT_ZERO), %o3 + sllx %o2, 32, %o2 or %o0, %o1, %o0 movxtod %o0, %f0 - sllx %o2, 32, %o2 fzero ZERO - sllx %o3, 32, %o3 - fnegd ZERO, SIGN_BIT - movxtod %o2, %f16 fabsd %f0, %f14 - fcmpd %fcc3, %f14, %f16 - fmovduge %fcc3, ZERO, %f16 fand %f0, SIGN_BIT, SIGN_BIT - for %f16, SIGN_BIT, %f16 + siam (1 << 2) | 2 faddd %f0, %f16, %f18 + siam (1 << 2) | 0 fsubd %f18, %f16, %f18 - fcmpd %fcc2, %f18, %f0 - movxtod %o3, %f20 - - fmovduge %fcc2, ZERO, %f20 - faddd %f18, %f20, %f0 - fabsd %f0, %f0 + siam (0 << 2) retl - for %f0, SIGN_BIT, %f0 + for %f18, SIGN_BIT, %f0 END (__ceil_vis3) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S index 835703fb9..efc8d4936 100644 --- a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S @@ -1,7 +1,7 @@ #include <sparc-ifunc.h> #include <math_ldbl_opt.h> -SPARC_ASM_VIS3_IFUNC(ceil) +SPARC_ASM_VIS3_VIS2_IFUNC(ceil) weak_alias (__ceil, ceil) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis2.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis2.S new file mode 100644 index 000000000..bc516765f --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis2.S @@ -0,0 +1,58 @@ +/* Float ceil function, sparc32 v9 vis2 version. + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* 'siam' (Set Interval Arithmetic Mode) is used to quickly override + the rounding mode during this routine. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value and, + with suitable 'siam' initiated rouding mode settings, round + the final result in the proper direction. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__ceilf_vis2) + st %o0, [%sp + 68] + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + ld [%sp + 68], %f0 + fnegs ZERO, SIGN_BIT + st %o2, [%sp + 68] + fabss %f0, %f14 + ld [%sp + 68], %f16 + fcmps %fcc3, %f14, %f16 + fmovsuge %fcc3, ZERO, %f16 + fands %f0, SIGN_BIT, SIGN_BIT + fors %f16, SIGN_BIT, %f16 + siam (1 << 2) | 2 + fadds %f0, %f16, %f1 + siam (1 << 2) | 0 + fsubs %f1, %f16, %f1 + siam (0 << 2) + retl + fors %f1, SIGN_BIT, %f0 +END (__ceilf_vis2) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S index 7d30c0b84..0a6768ca1 100644 --- a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S @@ -19,27 +19,21 @@ #include <sysdep.h> - /* Since changing the rounding mode is extremely expensive, we - try to round up using a method that is rounding mode - agnostic. + /* 'siam' (Set Interval Arithmetic Mode) is used to quickly override + the rounding mode during this routine. We add then subtract (or subtract than add if the initial value was negative) 2**23 to the value, then subtract it back out. - This will clear out the fractional portion of the value. - One of two things will happen for non-whole initial values. - Either the rounding mode will round it up, or it will be - rounded down. If the value started out whole, it will be - equal after the addition and subtraction. This means we - can accurately detect with one test whether we need to add - another 1.0 to round it up properly. + This will clear out the fractional portion of the value and, + with suitable 'siam' initiated rouding mode settings, round + the final result in the proper direction. - VIS instructions are used to facilitate the formation of - easier constants, and the propagation of the sign bit. */ + We also use VIS3 moves to avoid using the stack to transfer + values between float and integer registers. */ #define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ -#define ONE_DOT_ZERO 0x3f800000 /* 1.0 */ #define ZERO %f10 /* 0.0 */ #define SIGN_BIT %f12 /* -0.0 */ @@ -47,28 +41,19 @@ ENTRY (__ceilf_vis3) movwtos %o0, %f0 sethi %hi(TWO_TWENTYTHREE), %o2 - sethi %hi(ONE_DOT_ZERO), %o3 fzeros ZERO - fnegs ZERO, SIGN_BIT - movwtos %o2, %f16 fabss %f0, %f14 - fcmps %fcc3, %f14, %f16 - fmovsuge %fcc3, ZERO, %f16 fands %f0, SIGN_BIT, SIGN_BIT - fors %f16, SIGN_BIT, %f16 + siam (1 << 2) | 2 fadds %f0, %f16, %f1 + siam (1 << 2) | 0 fsubs %f1, %f16, %f1 - fcmps %fcc2, %f1, %f0 - movwtos %o3, %f9 - - fmovsuge %fcc2, ZERO, %f9 - fadds %f1, %f9, %f0 - fabss %f0, %f0 + siam (0 << 2) retl - fors %f0, SIGN_BIT, %f0 + fors %f1, SIGN_BIT, %f0 END (__ceilf_vis3) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S index 3047dd8fa..1c72a5728 100644 --- a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S @@ -1,6 +1,6 @@ #include <sparc-ifunc.h> -SPARC_ASM_VIS3_IFUNC(ceilf) +SPARC_ASM_VIS3_VIS2_IFUNC(ceilf) weak_alias (__ceilf, ceilf) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdim-vis3.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdim-vis3.S new file mode 100644 index 000000000..5e011a121 --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdim-vis3.S @@ -0,0 +1,34 @@ +/* Compute positive difference, sparc 32-bit+v9+vis3. + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY(__fdim_vis3) + movwtos %o0, %f0 + movwtos %o1, %f1 + movwtos %o2, %f2 + movwtos %o3, %f3 + fcmpd %f0, %f2 + fbug 1f + nop + fzero %f0 + fnegd %f0, %f2 +1: retl + fsubd %f0, %f2, %f0 +END(__fdim_vis3) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdim.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdim.S new file mode 100644 index 000000000..4b1340824 --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdim.S @@ -0,0 +1,19 @@ +#include <sparc-ifunc.h> +#include <math_ldbl_opt.h> + +SPARC_ASM_VIS3_IFUNC(fdim) + +weak_alias (__fdim, fdim) + +#if LONG_DOUBLE_COMPAT(libm, GLIBC_2_1) +compat_symbol (libm, __fdim, fdiml, GLIBC_2_1); +#endif + +# undef weak_alias +# define weak_alias(a, b) +# undef compat_symbol +# define compat_symbol(a, b, c, d) + +#define __fdim __fdim_generic + +#include "../s_fdim.S" diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdimf-vis3.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdimf-vis3.S new file mode 100644 index 000000000..c6d571297 --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdimf-vis3.S @@ -0,0 +1,32 @@ +/* Compute positive difference, sparc 32-bit+v9+vis3. + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY(__fdimf_vis3) + movwtos %o0, %f0 + movwtos %o1, %f1 + fcmps %f0, %f1 + fbug 1f + nop + fzeros %f0 + fnegs %f0, %f1 +1: retl + fsubs %f0, %f1, %f0 +END(__fdimf_vis3) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdimf.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdimf.S new file mode 100644 index 000000000..30381d6a5 --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdimf.S @@ -0,0 +1,12 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(fdimf) + +weak_alias (__fdimf, fdimf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __fdimf __fdimf_generic + +#include "../s_fdimf.S" diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis2.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis2.S new file mode 100644 index 000000000..3b5e8fd7c --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis2.S @@ -0,0 +1,61 @@ +/* floor function, sparc32 v9 vis2 version. + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* 'siam' (Set Interval Arithmetic Mode) is used to quickly override + the rounding mode during this routine. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value and, + with suitable 'siam' initiated rouding mode settings, round + the final result in the proper direction. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__floor_vis2) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o0, 32, %o0 + or %o0, %o1, %o0 + stx %o0, [%sp + 72] + sllx %o2, 32, %o2 + fzero ZERO + ldd [%sp + 72], %f0 + fnegd ZERO, SIGN_BIT + stx %o2, [%sp + 72] + fabsd %f0, %f14 + ldd [%sp + 72], %f16 + fcmpd %fcc3, %f14, %f16 + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + for %f16, SIGN_BIT, %f16 + siam (1 << 2) | 3 + faddd %f0, %f16, %f18 + siam (1 << 2) | 0 + fsubd %f18, %f16, %f18 + siam (0 << 2) + retl + for %f18, SIGN_BIT, %f0 +END (__floor_vis2) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S index 8445f1d7a..41fdfac3b 100644 --- a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S @@ -19,27 +19,21 @@ #include <sysdep.h> - /* Since changing the rounding mode is extremely expensive, we - try to round up using a method that is rounding mode - agnostic. + /* 'siam' (Set Interval Arithmetic Mode) is used to quickly override + the rounding mode during this routine. We add then subtract (or subtract than add if the initial value was negative) 2**23 to the value, then subtract it back out. - This will clear out the fractional portion of the value. - One of two things will happen for non-whole initial values. - Either the rounding mode will round it up, or it will be - rounded down. If the value started out whole, it will be - equal after the addition and subtraction. This means we - can accurately detect with one test whether we need to add - another 1.0 to round it up properly. + This will clear out the fractional portion of the value and, + with suitable 'siam' initiated rouding mode settings, round + the final result in the proper direction. - VIS instructions are used to facilitate the formation of - easier constants, and the propagation of the sign bit. */ + We also use VIS3 moves to avoid using the stack to transfer + values between float and integer registers. */ #define TWO_FIFTYTWO 0x43300000 /* 2**52 */ -#define ONE_DOT_ZERO 0x3ff00000 /* 1.0 */ #define ZERO %f10 /* 0.0 */ #define SIGN_BIT %f12 /* -0.0 */ @@ -47,32 +41,22 @@ ENTRY (__floor_vis3) sethi %hi(TWO_FIFTYTWO), %o2 sllx %o0, 32, %o0 - sethi %hi(ONE_DOT_ZERO), %o3 + sllx %o2, 32, %o2 or %o0, %o1, %o0 movxtod %o0, %f0 - sllx %o2, 32, %o2 fzero ZERO - sllx %o3, 32, %o3 - fnegd ZERO, SIGN_BIT - movxtod %o2, %f16 fabsd %f0, %f14 - fcmpd %fcc3, %f14, %f16 - fmovduge %fcc3, ZERO, %f16 fand %f0, SIGN_BIT, SIGN_BIT - for %f16, SIGN_BIT, %f16 + siam (1 << 2) | 3 faddd %f0, %f16, %f18 + siam (1 << 2) | 0 fsubd %f18, %f16, %f18 - fcmpd %fcc2, %f18, %f0 - movxtod %o3, %f20 - - fmovdule %fcc2, ZERO, %f20 - fsubd %f18, %f20, %f0 - fabsd %f0, %f0 + siam (0 << 2) retl - for %f0, SIGN_BIT, %f0 + for %f18, SIGN_BIT, %f0 END (__floor_vis3) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S index 37aeb43b9..1fe4b95ea 100644 --- a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S @@ -1,7 +1,7 @@ #include <sparc-ifunc.h> #include <math_ldbl_opt.h> -SPARC_ASM_VIS3_IFUNC(floor) +SPARC_ASM_VIS3_VIS2_IFUNC(floor) weak_alias (__floor, floor) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis2.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis2.S new file mode 100644 index 000000000..4f731212e --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis2.S @@ -0,0 +1,58 @@ +/* Float floor function, sparc32 v9 vis2 version. + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* 'siam' (Set Interval Arithmetic Mode) is used to quickly override + the rounding mode during this routine. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value and, + with suitable 'siam' initiated rouding mode settings, round + the final result in the proper direction. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__floorf_vis2) + st %o0, [%sp + 68] + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + ld [%sp + 68], %f0 + fnegs ZERO, SIGN_BIT + st %o2, [%sp + 68] + fabss %f0, %f14 + ld [%sp + 68], %f16 + fcmps %fcc3, %f14, %f16 + fmovsuge %fcc3, ZERO, %f16 + fands %f0, SIGN_BIT, SIGN_BIT + fors %f16, SIGN_BIT, %f16 + siam (1 << 2) | 3 + fadds %f0, %f16, %f1 + siam (1 << 2) | 0 + fsubs %f1, %f16, %f1 + siam (0 << 2) + retl + fors %f1, SIGN_BIT, %f0 +END (__floorf_vis2) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S index 133a0a4a9..fe2d2da20 100644 --- a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S @@ -19,27 +19,21 @@ #include <sysdep.h> - /* Since changing the rounding mode is extremely expensive, we - try to round up using a method that is rounding mode - agnostic. + /* 'siam' (Set Interval Arithmetic Mode) is used to quickly override + the rounding mode during this routine. We add then subtract (or subtract than add if the initial value was negative) 2**23 to the value, then subtract it back out. - This will clear out the fractional portion of the value. - One of two things will happen for non-whole initial values. - Either the rounding mode will round it up, or it will be - rounded down. If the value started out whole, it will be - equal after the addition and subtraction. This means we - can accurately detect with one test whether we need to add - another 1.0 to round it up properly. + This will clear out the fractional portion of the value and, + with suitable 'siam' initiated rouding mode settings, round + the final result in the proper direction. - VIS instructions are used to facilitate the formation of - easier constants, and the propagation of the sign bit. */ + We also use VIS3 moves to avoid using the stack to transfer + values between float and integer registers. */ #define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ -#define ONE_DOT_ZERO 0x3f800000 /* 1.0 */ #define ZERO %f10 /* 0.0 */ #define SIGN_BIT %f12 /* -0.0 */ @@ -47,28 +41,19 @@ ENTRY (__floorf_vis3) movwtos %o0, %f0 sethi %hi(TWO_TWENTYTHREE), %o2 - sethi %hi(ONE_DOT_ZERO), %o3 fzeros ZERO - fnegs ZERO, SIGN_BIT - movwtos %o2, %f16 fabss %f0, %f14 - fcmps %fcc3, %f14, %f16 - fmovsuge %fcc3, ZERO, %f16 fands %f0, SIGN_BIT, SIGN_BIT - fors %f16, SIGN_BIT, %f16 + siam (1 << 2) | 3 fadds %f0, %f16, %f1 + siam (1 << 2) | 0 fsubs %f1, %f16, %f1 - fcmps %fcc2, %f1, %f0 - movwtos %o3, %f9 - - fmovsule %fcc2, ZERO, %f9 - fsubs %f1, %f9, %f0 - fabss %f0, %f0 + siam (0 << 2) retl - fors %f0, SIGN_BIT, %f0 + fors %f1, SIGN_BIT, %f0 END (__floorf_vis3) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S index 31cda385b..d2a83cb9b 100644 --- a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S @@ -1,6 +1,6 @@ #include <sparc-ifunc.h> -SPARC_ASM_VIS3_IFUNC(floorf) +SPARC_ASM_VIS3_VIS2_IFUNC(floorf) weak_alias (__floorf, floorf) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint-vis3.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint-vis3.S new file mode 100644 index 000000000..b509500ed --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint-vis3.S @@ -0,0 +1,65 @@ +/* Round float to int floating-point values without generating + an inexact exception, sparc32 v9 vis3 version. + + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <math_ldbl_opt.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__nearbyint_vis3) + st %fsr, [%sp + 88] + sethi %hi(TWO_FIFTYTWO), %o2 + sethi %hi(0xf8003e0), %o5 + ld [%sp + 88], %o4 + sllx %o0, 32, %o0 + or %o5, %lo(0xf8003e0), %o5 + or %o0, %o1, %o0 + movxtod %o0, %f0 + andn %o4, %o5, %o4 + fzero ZERO + st %o4, [%sp + 80] + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + ld [%sp + 80], %fsr + movxtod %o2, %f16 + fabsd %f0, %f14 + fcmpd %fcc3, %f14, %f16 + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + for %f0, SIGN_BIT, %f0 + retl + ld [%sp + 88], %fsr +END (__nearbyint_vis3) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint.S new file mode 100644 index 000000000..47da9eaaf --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint.S @@ -0,0 +1,19 @@ +#include <sparc-ifunc.h> +#include <math_ldbl_opt.h> + +SPARC_ASM_VIS3_IFUNC(nearbyint) + +weak_alias (__nearbyint, nearbyint) + +#if LONG_DOUBLE_COMPAT(libm, GLIBC_2_1) +compat_symbol (libm, __nearbyint, nearbyintl, GLIBC_2_1) +#endif + +# undef weak_alias +# define weak_alias(a, b) +# undef compat_symbol +# define compat_symbol(a, b, c, d) + +#define __nearbyint __nearbyint_generic + +#include "../s_nearbyint.S" diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf-vis3.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf-vis3.S new file mode 100644 index 000000000..336126dee --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf-vis3.S @@ -0,0 +1,61 @@ +/* Round float to int floating-point values without generating + an inexact exception, sparc32 v9 vis3 version. + + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__nearbyintf_vis3) + st %fsr, [%sp + 88] + movwtos %o0, %f1 + sethi %hi(TWO_TWENTYTHREE), %o2 + sethi %hi(0xf8003e0), %o5 + ld [%sp + 88], %o4 + fzeros ZERO + or %o5, %lo(0xf8003e0), %o5 + fnegs ZERO, SIGN_BIT + andn %o4, %o5, %o4 + st %o4, [%sp + 80] + ld [%sp + 80], %fsr + movwtos %o2, %f16 + fabss %f1, %f14 + fcmps %fcc3, %f14, %f16 + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + fors %f0, SIGN_BIT, %f0 + retl + ld [%sp + 88], %fsr +END (__nearbyintf_vis3) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf.S new file mode 100644 index 000000000..95100c1bf --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf.S @@ -0,0 +1,12 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(nearbyintf) + +weak_alias (__nearbyintf, nearbyintf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __nearbyintf __nearbyintf_generic + +#include "../s_nearbyintf.S" diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_trunc-vis3.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_trunc-vis3.S new file mode 100644 index 000000000..72ec2826e --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_trunc-vis3.S @@ -0,0 +1,57 @@ +/* Truncate argument to nearest integral value not larger than + the argument, sparc32 v9 vis3 version. + + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <math_ldbl_opt.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__trunc_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o0, 32, %o0 + or %o0, %o1, %o0 + fzero ZERO + movxtod %o0, %f0 + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + movxtod %o2, %f16 + fabsd %f0, %f14 + fcmpd %fcc3, %f14, %f16 + fmovduge %fcc3, ZERO, %f14 + fand %f0, SIGN_BIT, SIGN_BIT + fdtox %f14, %f14 + fxtod %f14, %f14 + faddd %f0, ZERO, %f18 + fmovduge %fcc3, %f18, %f14 + retl + for %f14, SIGN_BIT, %f0 +END (__trunc_vis3) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_trunc.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_trunc.S new file mode 100644 index 000000000..3787fa1f1 --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_trunc.S @@ -0,0 +1,19 @@ +#include <sparc-ifunc.h> +#include <math_ldbl_opt.h> + +SPARC_ASM_VIS3_IFUNC(trunc) + +weak_alias (__trunc, trunc) + +#if LONG_DOUBLE_COMPAT(libm, GLIBC_2_1) +compat_symbol (libm, __trunc, truncl, GLIBC_2_1) +#endif + +# undef weak_alias +# define weak_alias(a, b) +# undef compat_symbol +# define compat_symbol(a, b, c, d) + +#define __trunc __trunc_generic + +#include "../s_trunc.S" diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_truncf-vis3.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_truncf-vis3.S new file mode 100644 index 000000000..60445dfaa --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_truncf-vis3.S @@ -0,0 +1,53 @@ +/* Truncate argument to nearest integral value not larger than + the argument, sparc32 v9 vis3 version. + + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__truncf_vis3) + movwtos %o0, %f1 + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + fnegs ZERO, SIGN_BIT + movwtos %o2, %f16 + fabss %f1, %f14 + fcmps %fcc3, %f14, %f16 + fmovsuge %fcc3, ZERO, %f14 + fands %f1, SIGN_BIT, SIGN_BIT + fstoi %f14, %f14 + fitos %f14, %f14 + fadds %f1, ZERO, %f18 + fmovsuge %fcc3, %f18, %f14 + retl + fors %f14, SIGN_BIT, %f0 +END (__truncf_vis3) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_truncf.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_truncf.S new file mode 100644 index 000000000..2ca251733 --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_truncf.S @@ -0,0 +1,12 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(truncf) + +weak_alias (__truncf, truncf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __truncf __truncf_generic + +#include "../s_truncf.S" diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_fdim.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_fdim.S new file mode 100644 index 000000000..6f26ab7af --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_fdim.S @@ -0,0 +1,40 @@ +/* Compute positive difference, sparc 32-bit+v9. + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <math_ldbl_opt.h> + +ENTRY(__fdim) + std %o0, [%sp + 72] + std %o2, [%sp + 80] + ldd [%sp + 72], %f0 + ldd [%sp + 80], %f2 + fcmpd %f0, %f2 + fbug 1f + nop + fzero %f0 + fnegd %f0, %f2 +1: retl + fsubd %f0, %f2, %f0 +END(__fdim) +weak_alias (__fdim, fdim) + +#if LONG_DOUBLE_COMPAT(libm, GLIBC_2_1) +compat_symbol (libm, __fdim, fdiml, GLIBC_2_1); +#endif diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_fdimf.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_fdimf.S new file mode 100644 index 000000000..fc55867cd --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_fdimf.S @@ -0,0 +1,35 @@ +/* Compute positive difference, sparc 32-bit+v9. + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY(__fdimf) + st %o0, [%sp + 72] + st %o1, [%sp + 76] + ld [%sp + 72], %f0 + ld [%sp + 76], %f1 + fcmps %f0, %f1 + fbug 1f + nop + fzeros %f0 + fnegs %f0, %f1 +1: retl + fsubs %f0, %f1, %f0 +END(__fdimf) +weak_alias (__fdimf, fdimf) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyint.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyint.S new file mode 100644 index 000000000..ee6a575e1 --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyint.S @@ -0,0 +1,72 @@ +/* Round float to int floating-point values without generating + an inexact exception, sparc32 v9 version. + + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <math_ldbl_opt.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__nearbyint) + st %fsr, [%sp + 88] + sethi %hi(TWO_FIFTYTWO), %o2 + sethi %hi(0xf8003e0), %o5 + ld [%sp + 88], %o4 + sllx %o0, 32, %o0 + or %o5, %lo(0xf8003e0), %o5 + or %o0, %o1, %o0 + andn %o4, %o5, %o4 + fzero ZERO + st %o4, [%sp + 80] + stx %o0, [%sp + 72] + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + ldd [%sp + 72], %f0 + ld [%sp + 80], %fsr + stx %o2, [%sp + 72] + fabsd %f0, %f14 + ldd [%sp + 72], %f16 + fcmpd %fcc3, %f14, %f16 + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + for %f0, SIGN_BIT, %f0 + retl + ld [%sp + 88], %fsr +END (__nearbyint) +weak_alias (__nearbyint, nearbyint) + +#if LONG_DOUBLE_COMPAT(libm, GLIBC_2_1) +compat_symbol (libm, __nearbyint, nearbyintl, GLIBC_2_1) +#endif diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyintf.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyintf.S new file mode 100644 index 000000000..4225b5449 --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyintf.S @@ -0,0 +1,64 @@ +/* Round float to int floating-point values without generating + an inexact exception, sparc32 v9 version. + + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__nearbyintf) + st %fsr, [%sp + 88] + st %o0, [%sp + 68] + sethi %hi(TWO_TWENTYTHREE), %o2 + sethi %hi(0xf8003e0), %o5 + ld [%sp + 88], %o4 + fzeros ZERO + or %o5, %lo(0xf8003e0), %o5 + fnegs ZERO, SIGN_BIT + andn %o4, %o5, %o4 + st %o4, [%sp + 80] + ld [%sp + 68], %f1 + ld [%sp + 80], %fsr + st %o2, [%sp + 68] + fabss %f1, %f14 + ld [%sp + 68], %f16 + fcmps %fcc3, %f14, %f16 + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + fors %f0, SIGN_BIT, %f0 + retl + ld [%sp + 88], %fsr +END (__nearbyintf) +weak_alias (__nearbyintf, nearbyintf) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_trunc.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_trunc.S new file mode 100644 index 000000000..c451d1d99 --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_trunc.S @@ -0,0 +1,64 @@ +/* Truncate argument to nearest integral value not larger than + the argument, sparc32 v9 version. + + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <math_ldbl_opt.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__trunc) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o0, 32, %o0 + or %o0, %o1, %o0 + fzero ZERO + stx %o0, [%sp + 72] + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + ldd [%sp + 72], %f0 + stx %o2, [%sp + 72] + fabsd %f0, %f14 + ldd [%sp + 72], %f16 + fcmpd %fcc3, %f14, %f16 + fmovduge %fcc3, ZERO, %f14 + fand %f0, SIGN_BIT, SIGN_BIT + fdtox %f14, %f14 + fxtod %f14, %f14 + faddd %f0, ZERO, %f18 + fmovduge %fcc3, %f18, %f14 + retl + for %f14, SIGN_BIT, %f0 +END (__trunc) +weak_alias (__trunc, trunc) + +#if LONG_DOUBLE_COMPAT(libm, GLIBC_2_1) +compat_symbol (libm, __trunc, truncl, GLIBC_2_1) +#endif diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_truncf.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_truncf.S new file mode 100644 index 000000000..4e6e25b26 --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_truncf.S @@ -0,0 +1,56 @@ +/* Truncate argument to nearest integral value not larger than + the argument, sparc32 v9 version. + + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__truncf) + st %o0, [%sp + 68] + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + ld [%sp + 68], %f1 + fnegs ZERO, SIGN_BIT + st %o2, [%sp + 68] + fabss %f1, %f14 + ld [%sp + 68], %f16 + fcmps %fcc3, %f14, %f16 + fmovsuge %fcc3, ZERO, %f14 + fands %f1, SIGN_BIT, SIGN_BIT + fstoi %f14, %f14 + fitos %f14, %f14 + fadds %f1, ZERO, %f18 + fmovsuge %fcc3, %f18, %f14 + retl + fors %f14, SIGN_BIT, %f0 +END (__truncf) +weak_alias (__truncf, truncf) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/unix/sysv/linux/multiarch/Implies b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/unix/sysv/linux/multiarch/Implies deleted file mode 100644 index a380d8a73..000000000 --- a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/unix/sysv/linux/multiarch/Implies +++ /dev/null @@ -1,4 +0,0 @@ -# We must list this here to move it ahead of the ldbl-opt code. -sparc/sparc32/sparcv9/fpu/multiarch -sparc/sparc32/sparcv9/fpu -sparc/sparc32/fpu diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/mul_1.S b/libc/sysdeps/sparc/sparc32/sparcv9/mul_1.S index 42284eada..e9a537196 100644 --- a/libc/sysdeps/sparc/sparc32/sparcv9/mul_1.S +++ b/libc/sysdeps/sparc/sparc32/sparcv9/mul_1.S @@ -1 +1,70 @@ -#include <sparcv8/mul_1.S> +! SPARC v9 32-bit __mpn_mul_1 -- Multiply a limb vector with a single +! limb and store the product in a second limb vector. +! +! Copyright (C) 2013 Free Software Foundation, Inc. +! This file is part of the GNU C Library. +! Contributed by David S. Miller <davem@davemloft.net> +! +! The GNU C Library is free software; you can redistribute it and/or +! modify it under the terms of the GNU Lesser General Public +! License as published by the Free Software Foundation; either +! version 2.1 of the License, or (at your option) any later version. +! +! The GNU C Library is distributed in the hope that it will be useful, +! but WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! Lesser General Public License for more details. +! +! You should have received a copy of the GNU Lesser General Public +! License along with the GNU C Library; if not, see +! <http://www.gnu.org/licenses/>. + +#include <sysdep.h> + +#define res_ptr %o0 +#define s1_ptr %o1 +#define sz %o2 +#define s2_limb %o3 +#define carry %o5 +#define tmp1 %g1 +#define tmp2 %g2 +#define tmp3 %g3 +#define tmp4 %o4 + +ENTRY(__mpn_mul_1) + srl sz, 0, sz + srl s2_limb, 0, s2_limb + subcc sz, 1, sz + be,pn %icc, .Lfinal_limb + clr carry + +.Lloop: + lduw [s1_ptr + 0x00], tmp1 + lduw [s1_ptr + 0x04], tmp2 + mulx tmp1, s2_limb, tmp3 + add s1_ptr, 8, s1_ptr + mulx tmp2, s2_limb, tmp4 + sub sz, 2, sz + add res_ptr, 8, res_ptr + add carry, tmp3, tmp3 + stw tmp3, [res_ptr - 0x08] + srlx tmp3, 32, carry + add carry, tmp4, tmp4 + stw tmp4, [res_ptr - 0x04] + brgz sz, .Lloop + srlx tmp4, 32, carry + + brlz,pt sz, .Lfinish + nop + +.Lfinal_limb: + lduw [s1_ptr + 0x00], tmp1 + mulx tmp1, s2_limb, tmp3 + add carry, tmp3, tmp3 + stw tmp3, [res_ptr + 0x00] + srlx tmp3, 32, carry + +.Lfinish: + retl + mov carry, %o0 +END(__mpn_mul_1) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/submul_1.S b/libc/sysdeps/sparc/sparc32/sparcv9/submul_1.S index de69533f6..8985e2a4c 100644 --- a/libc/sysdeps/sparc/sparc32/sparcv9/submul_1.S +++ b/libc/sysdeps/sparc/sparc32/sparcv9/submul_1.S @@ -1 +1,82 @@ -#include <sparcv8/submul_1.S> +! SPARC v9 32-bit __mpn_submul_1 -- Multiply a limb vector with a limb +! and subtract the result from a second limb vector. +! +! Copyright (C) 2013 Free Software Foundation, Inc. +! This file is part of the GNU C Library. +! Contributed by David S. Miller <davem@davemloft.net> +! +! The GNU C Library is free software; you can redistribute it and/or +! modify it under the terms of the GNU Lesser General Public +! License as published by the Free Software Foundation; either +! version 2.1 of the License, or (at your option) any later version. +! +! The GNU C Library is distributed in the hope that it will be useful, +! but WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! Lesser General Public License for more details. +! +! You should have received a copy of the GNU Lesser General Public +! License along with the GNU C Library; if not, see +! <http://www.gnu.org/licenses/>. + +#include <sysdep.h> + +#define res_ptr %i0 +#define s1_ptr %i1 +#define sz_arg %i2 +#define s2l_arg %i3 +#define sz %o4 +#define carry %o5 +#define s2_limb %g1 +#define tmp1 %l0 +#define tmp2 %l1 +#define tmp3 %l2 +#define tmp4 %l3 +#define tmp64_1 %g3 +#define tmp64_2 %o3 + +ENTRY(__mpn_submul_1) + save %sp, -96, %sp + srl sz_arg, 0, sz + srl s2l_arg, 0, s2_limb + subcc sz, 1, sz + be,pn %icc, .Lfinal_limb + subcc %g0, 0, carry + +.Lloop: + lduw [s1_ptr + 0x00], tmp1 + lduw [res_ptr + 0x00], tmp3 + lduw [s1_ptr + 0x04], tmp2 + lduw [res_ptr + 0x04], tmp4 + mulx tmp1, s2_limb, tmp64_1 + add s1_ptr, 8, s1_ptr + mulx tmp2, s2_limb, tmp64_2 + sub sz, 2, sz + add res_ptr, 8, res_ptr + addx carry, tmp64_1, tmp64_1 + srlx tmp64_1, 32, carry + subcc tmp3, tmp64_1, tmp64_1 + stw tmp64_1, [res_ptr - 0x08] + addx carry, tmp64_2, tmp64_2 + srlx tmp64_2, 32, carry + subcc tmp4, tmp64_2, tmp64_2 + brgz sz, .Lloop + stw tmp64_2, [res_ptr - 0x04] + + brlz,pt sz, .Lfinish + nop + +.Lfinal_limb: + lduw [s1_ptr + 0x00], tmp1 + lduw [res_ptr + 0x00], tmp3 + mulx tmp1, s2_limb, tmp64_1 + addx carry, tmp64_1, tmp64_1 + srlx tmp64_1, 32, carry + subcc tmp3, tmp64_1, tmp64_1 + stw tmp64_1, [res_ptr + 0x00] + +.Lfinish: + addx carry, 0, carry + jmpl %i7 + 0x8, %g0 + restore carry, 0, %o0 +END(__mpn_submul_1) |