Merge branch 'john/erts/instruction-synchronization-barriers/OTP-18418' into john/erts/merge-isb-26

* john/erts/instruction-synchronization-barriers/OTP-18418:
  jit: Clear instruction cache ourselves
  jit: Refactor breakpoints
  jit: Issue ISBs on all schedulers when modifying code
  jit: Remove an eyesore

1 files changed, 117 insertions, 0 deletions

diff --git a/erts/configure b/erts/configure
index f6a2ac1b49..c42972cf43 100755
--- a/erts/configure
+++ b/erts/configure
@@ -14071,6 +14071,7 @@ printf "%s\n" "#define ETHR_HAVE___atomic_compare_exchange_n $have_atomic_ops" >
     ethr_arm_dbm_sy_instr_val=0
     ethr_arm_dbm_st_instr_val=0
     ethr_arm_dbm_ld_instr_val=0
+    ethr_arm_isb_sy_instr_val=0
     case "$GCC-$host_cpu" in #(
   yes-arm*|yes-aarch*) :
 
@@ -14178,6 +14179,111 @@ printf "%s\n" "$ethr_cv_arm_dbm_ld_instr" >&6; }
 	    if test $ethr_cv_arm_dbm_ld_instr = yes; then
 		ethr_arm_dbm_ld_instr_val=1
 	    fi
+	    { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for ARM 'isb sy' instruction" >&5
+printf %s "checking for ARM 'isb sy' instruction... " >&6; }
+if test ${ethr_cv_arm_isb_sy_instr+y}
+then :
+  printf %s "(cached) " >&6
+else $as_nop
+
+				ethr_cv_arm_isb_sy_instr=no
+				cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main (void)
+{
+
+						__asm__ __volatile__("isb sy" : : : "memory");
+
+  ;
+  return 0;
+}
+_ACEOF
+if ac_fn_c_try_link "$LINENO"
+then :
+  ethr_cv_arm_isb_sy_instr=yes
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.beam \
+    conftest$ac_exeext conftest.$ac_ext
+
+fi
+{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ethr_cv_arm_isb_sy_instr" >&5
+printf "%s\n" "$ethr_cv_arm_isb_sy_instr" >&6; }
+	    if test $ethr_cv_arm_isb_sy_instr = yes; then
+		ethr_arm_isb_sy_instr_val=1
+	    fi
+
+	    { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for ARM 'dc cvau' instruction" >&5
+printf %s "checking for ARM 'dc cvau' instruction... " >&6; }
+if test ${ethr_cv_arm_dc_cvau_instr+y}
+then :
+  printf %s "(cached) " >&6
+else $as_nop
+
+				ethr_cv_arm_dc_cvau_instr=no
+				cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main (void)
+{
+  char data[512];
+						__asm__ __volatile__("dc cvau, %0" : "r" (data) : : "memory");
+
+  ;
+  return 0;
+}
+_ACEOF
+if ac_fn_c_try_link "$LINENO"
+then :
+  ethr_cv_arm_dc_cvau_instr=yes
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.beam \
+    conftest$ac_exeext conftest.$ac_ext
+
+fi
+{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ethr_cv_arm_dc_cvau_instr" >&5
+printf "%s\n" "$ethr_cv_arm_dc_cvau_instr" >&6; }
+	    if test $ethr_cv_arm_dc_cvau_instr = yes; then
+		ethr_arm_dc_cvau_instr_val=1
+	    fi
+
+	    { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for ARM 'ic ivau' instruction" >&5
+printf %s "checking for ARM 'ic ivau' instruction... " >&6; }
+if test ${ethr_cv_arm_ic_ivau_instr+y}
+then :
+  printf %s "(cached) " >&6
+else $as_nop
+
+				ethr_cv_arm_ic_ivau_instr=no
+				cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main (void)
+{
+  char data[512];
+						__asm__ __volatile__("ic ivau, %0" : "r" (data) : : "memory");
+
+  ;
+  return 0;
+}
+_ACEOF
+if ac_fn_c_try_link "$LINENO"
+then :
+  ethr_cv_arm_ic_ivau_instr=yes
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.beam \
+    conftest$ac_exeext conftest.$ac_ext
+
+fi
+{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ethr_cv_arm_ic_ivau_instr" >&5
+printf "%s\n" "$ethr_cv_arm_ic_ivau_instr" >&6; }
+	    if test $ethr_cv_arm_ic_ivau_instr = yes; then
+		ethr_arm_dc_cvau_instr_val=1
+	    fi
+
        ;; #(
   *) :
      ;;
@@ -14192,6 +14298,17 @@ printf "%s\n" "#define ETHR_HAVE_GCC_ASM_ARM_DMB_ST_INSTRUCTION $ethr_arm_dbm_st
 
 printf "%s\n" "#define ETHR_HAVE_GCC_ASM_ARM_DMB_LD_INSTRUCTION $ethr_arm_dbm_ld_instr_val" >>confdefs.h
 
+
+printf "%s\n" "#define ETHR_HAVE_GCC_ASM_ARM_ISB_SY_INSTRUCTION $ethr_arm_isb_sy_instr_val" >>confdefs.h
+
+
+printf "%s\n" "#define ETHR_HAVE_GCC_ASM_ARM_DC_CVAU_INSTRUCTION $ethr_arm_dc_cvau_instr_val" >>confdefs.h
+
+
+printf "%s\n" "#define ETHR_HAVE_GCC_ASM_ARM_IC_IVAU_INSTRUCTION $ethr_arm_ic_ivau_instr_val" >>confdefs.h
+
+
+
     test $ethr_cv_32bit___sync_val_compare_and_swap = yes &&
     	ethr_have_gcc_native_atomics=yes
     test $ethr_cv_64bit___sync_val_compare_and_swap = yes &&