diff options
author | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2010-07-21 15:12:07 +0000 |
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committer | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2010-07-21 15:12:07 +0000 |
commit | afed9219b702fbaddb220fe022abfe84a48a5459 (patch) | |
tree | d0401ebf7a46d22d6b52d59d6c7f6f4ac4cbed4b | |
parent | 620d2e7f6ff68efb07efad0ffa7bfc32e5e3a471 (diff) | |
download | flashrom-afed9219b702fbaddb220fe022abfe84a48a5459.tar.gz |
Add nicnatsemi to print.c and print_wiki.c.
Change the nicnatsemi address mask to use MA0-MA16 and set the maximum
decode size to 128KB.
Signed-off-by: Andrew Morgan <ziltro@ziltro.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r-- | nicnatsemi.c | 12 | ||||
-rw-r--r-- | print.c | 5 | ||||
-rw-r--r-- | print_wiki.c | 3 |
3 files changed, 17 insertions, 3 deletions
diff --git a/nicnatsemi.c b/nicnatsemi.c index c3b93d9..89a0bf4 100644 --- a/nicnatsemi.c +++ b/nicnatsemi.c @@ -43,6 +43,14 @@ int nicnatsemi_init(void) buses_supported = CHIP_BUSTYPE_PARALLEL; + /* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15 + * in another. My NIC has MA16 connected to A16 on the boot ROM socket + * so I'm assuming it is accessible. If not then next line wants to be + * max_rom_decode.parallel = 65536; and the mask in the read/write + * functions below wants to be 0x0000FFFF. + */ + max_rom_decode.parallel = 131072; + return 0; } @@ -55,7 +63,7 @@ int nicnatsemi_shutdown(void) void nicnatsemi_chip_writeb(uint8_t val, chipaddr addr) { - OUTL((uint32_t)addr & 0x0000FFFF, io_base_addr + BOOT_ROM_ADDR); + OUTL((uint32_t)addr & 0x0001FFFF, io_base_addr + BOOT_ROM_ADDR); /* * The datasheet requires 32 bit accesses to this register, but it seems * that requirement might only apply if the register is memory mapped. @@ -69,7 +77,7 @@ void nicnatsemi_chip_writeb(uint8_t val, chipaddr addr) uint8_t nicnatsemi_chip_readb(const chipaddr addr) { - OUTL(((uint32_t)addr & 0x0000FFFF), io_base_addr + BOOT_ROM_ADDR); + OUTL(((uint32_t)addr & 0x0001FFFF), io_base_addr + BOOT_ROM_ADDR); /* * The datasheet requires 32 bit accesses to this register, but it seems * that requirement might only apply if the register is memory mapped. @@ -228,7 +228,7 @@ void print_supported(void) print_supported_boards_helper(boards_known, "boards"); print_supported_boards_helper(laptops_known, "laptops"); #endif -#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT >= 1 +#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT >= 1 printf("\nSupported PCI devices flashrom can use " "as programmer:\n\n"); #endif @@ -239,6 +239,9 @@ void print_supported(void) print_supported_pcidevs(nics_realtek); print_supported_pcidevs(nics_realteksmc1211); #endif +#if CONFIG_NICNATSEMI == 1 + print_supported_pcidevs(nics_natsemi); +#endif #if CONFIG_GFXNVIDIA == 1 print_supported_pcidevs(gfx_nvidia); #endif diff --git a/print_wiki.c b/print_wiki.c index d688530..8c0e06d 100644 --- a/print_wiki.c +++ b/print_wiki.c @@ -280,6 +280,9 @@ void print_supported_wiki(void) print_supported_pcidevs_wiki(nics_realtek); print_supported_pcidevs_wiki(nics_realteksmc1211); #endif +#if CONFIG_NICNATSEMI == 1 + print_supported_pcidevs_wiki(nics_natsemi); +#endif #if CONFIG_GFXNVIDIA == 1 print_supported_pcidevs_wiki(gfx_nvidia); #endif |