Delay between probe and subsequent operations.

Some flash chips need time to exit ID mode, and while we take care of
correct timing for the matching probe, subsequent probes may have
totally different timing, and that can lead to garbage responses from
the flash chip during the first accesses after the probe sequence is
done.
Delay 100 ms between the last probe and any subsequent operation.
To ensure maximum correctness, we would have to reset the chip first in
case the last probe function left the chip in an undefined (non-read)
state. That will be possible once struct flashchip has a .reset
function.

This fixes unstable erase/read/write for some flahs chips on nic3com and
possible other use cases as well.

Thanks to Maciej Pijanka for reporting the issue and testing patches.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>


git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1172 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 5 insertions, 0 deletions

diff --git a/cli_classic.c b/cli_classic.c
index d78c575..09504d7 100644
--- a/cli_classic.c
+++ b/cli_classic.c
@@ -456,5 +456,10 @@ int cli_classic(int argc, char *argv[])
 	if (write_it && !dont_verify_it)
 		verify_it = 1;
 
+	/* FIXME: We should issue an unconditional chip reset here. This can be
+	 * done once we have a .reset function in struct flashchip.
+	 * Give the chip time to settle.
+	 */
+	programmer_delay(100000);
 	return doit(flash, force, filename, read_it, write_it, erase_it, verify_it);
 }