Add Intel Gigabit NIC SPI flashing support.

Tested on a 82541PI (0x8086, 0x107c) using 32-bit hardware.

The last line in nicintel_request_spibus() could be changed so that FL_BUSY
is used instead.

Shortened sample log:
[...]
Found "Intel 82541PI Gigabit Ethernet Controller" (8086:107c, BDF 01:03.0).
Found chip "ST M25P10.RES" (128 KB, SPI) at physical address 0xfffe0000.
Multiple flash chips were detected: M25P05.RES M25P10.RES
Please specify which chip to use with the -c <chipname> option.
[...]

Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 9 insertions, 0 deletions

diff --git a/spi.c b/spi.c
index ebacd60..e892e74 100644
--- a/spi.c
+++ b/spi.c
@@ -136,6 +136,15 @@ const struct spi_programmer spi_programmer[] = {
 	},
 #endif
 
+#if CONFIG_NICINTEL_SPI == 1
+	{ /* SPI_CONTROLLER_NICINTEL */
+		.command = bitbang_spi_send_command,
+		.multicommand = default_spi_send_multicommand,
+		.read = bitbang_spi_read,
+		.write_256 = bitbang_spi_write_256,
+	},
+#endif
+
 	{}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */
 };