This is a workaround for a bug in SB600 and SB700. If we only send an

opcode and no additional data/address, the SPI controller will read one
byte too few from the chip. Basically, the last byte of the chip
response is discarded and will not end up in the FIFO. It is unclear if
the CS# line is set high too early as well.
That hardware bug is undocumented as of now, but I'm working with AMD to
add a detailed description of it to the errata.

Add loads of additional debugging to SB600/SB700 init.

Add explanatory comments for unintuitive code flow.

Thanks go to Uwe for testing quite a few iterations of the patch.

Kill the SB600 flash chip status register special case, which was a
somewhat misguided workaround for that hardware erratum.

Note for future added features in the SB600 SPI driver: It may be
possible to read up to 15 bytes of command response with overlapping
reads due to the ring buffer design of the FIFO if the command can be
repeated without ill effects. Same for skipping up to 7 bytes between
command and response.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 0 insertions, 4 deletions

diff --git a/spi.c b/spi.c
index 8d82c4e..c177fb0 100644
--- a/spi.c
+++ b/spi.c
@@ -367,10 +367,6 @@ uint8_t spi_read_status_register(void)
 	int ret;
 
 	/* Read Status Register */
-	if (spi_controller == SPI_CONTROLLER_SB600) { /* FIXME */
-		/* Workaround for SB600 hardware bug. Can be killed later. */
-		return sb600_read_status_register();
-	}
 	ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr);
 	if (ret)
 		fprintf(stderr, "RDSR failed!\n");