ICH SPI can enforce address restrictions for all accesses which take an

address (well, it could if the chipset implementation was not broken).
Since exploiting the broken implementation is harder than conforming to
the address restrictions wherever possible, conform to the address
restrictions instead.
This patch eliminates a lot of transaction errors people were seeing
on chip probe.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 16 insertions, 2 deletions

diff --git a/spi.c b/spi.c
index 24696fb..0d501c0 100644
--- a/spi.c
+++ b/spi.c
@@ -207,8 +207,22 @@ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf)
 	return spi_programmer[spi_controller].write_256(flash, buf);
 }
 
+/*
+ * Get the lowest allowed address for read accesses. This often happens to
+ * be the lowest allowed address for all commands which take an address.
+ * This is a programmer limitation.
+ */
 uint32_t spi_get_valid_read_addr(void)
 {
-	/* Need to return BBAR for ICH chipsets. */
-	return 0;
+	switch (spi_controller) {
+#if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
+	case SPI_CONTROLLER_ICH7:
+		/* Return BBAR for ICH chipsets. */
+		return ichspi_bbar;
+#endif
+#endif
+	default:
+		return 0;
+	}
 }