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author | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2010-05-28 17:07:57 +0000 |
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committer | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2010-05-28 17:07:57 +0000 |
commit | 47888ffa98a2cc77cf93ea7a9f5df9ddad289545 (patch) | |
tree | f7d7123a8b474227d45bd9f0eae5b819d499b3a8 /spi.h | |
parent | c8bd93d08baccee3715ad418fc18a0d9f54bf3e0 (diff) | |
download | flashrom-47888ffa98a2cc77cf93ea7a9f5df9ddad289545.tar.gz |
Some chips implement the RES (0xab) opcode, but they use a non-standard
two byte response instead of the usual one byte response.
A two-byte response has the accuracy of REMS and RDID, so don't check
for REMS/RDID availability before running a two-byte RES.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'spi.h')
-rw-r--r-- | spi.h | 2 |
1 files changed, 2 insertions, 0 deletions
@@ -27,6 +27,7 @@ /* Read Electronic ID */ #define JEDEC_RDID 0x9f #define JEDEC_RDID_OUTSIZE 0x01 +/* INSIZE may be 0x04 for some chips*/ #define JEDEC_RDID_INSIZE 0x03 /* AT25F512A has bit 3 as don't care bit in commands */ @@ -42,6 +43,7 @@ /* Read Electronic Signature */ #define JEDEC_RES 0xab #define JEDEC_RES_OUTSIZE 0x04 +/* INSIZE may be 0x02 for some chips*/ #define JEDEC_RES_INSIZE 0x01 /* Write Enable */ |