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| author | stefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2012-12-29 15:04:12 +0000 |
|---|---|---|
| committer | stefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2012-12-29 15:04:12 +0000 |
| commit | baf53a1e3972310eab38b0062a192f2e4c076227 (patch) | |
| tree | b394950b3bd52b2490e1da77a1c497516d6bfd06 /spi.h | |
| parent | a89c7d9422f46ea1d9e6bd6b660c52b5015fdb2a (diff) | |
| download | flashrom-baf53a1e3972310eab38b0062a192f2e4c076227.tar.gz | |
Add support for Intel S33 series flash chips.
This includes:
Bottom boot block:
* 16Mb/2MB:
QB25F160S33B8, QB25F016S33B8, QH25F160S33B8, QH25F016S33B8
* 32Mb/4MB:
QB25F320S33B8, QH25F320S33B8
* 64Mb/8MB:
QB25F640S33B8, QH25F640S33B8
Top boot block:
* 16Mb/2MB:
QB25F160S33T8, QB25F016S33T8, QH25F160S33T8, QH25F016S33T8
* 32Mb/4MB:
QB25F320S33T8, QH25F320S33T8
* 64Mb/8MB:
QB25F640S33T8, QH25F640S33T8
At least some seem to be marketed by other vendors (too?) but also with
Intel's vendor ID.
Besides a 0xC7 chip erase and a 0xD8 uniform 64kB block erase they
support also erasing the top/bottom 8 8kB blocks with opcode 0x40.
But since this command fails for all addresses outside those ranges,
it is not easily implemented with flashrom's current code base and
hence left out.
Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'spi.h')
0 files changed, 0 insertions, 0 deletions