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* Add support for SST SST25WF020A, SST25WF040B, SST25WF080B.stefanct2015-11-221-0/+1
| | | | | | | | | | | | | | | | Apart from the strange ID (using Sanyo's vendor ID 0x62) the main difference from the plain SST25WF series is that they lack op codes 0xAD (AAI Word program) and 0x52 (32K erase). The smallest version does not support dual I/O operations either. SST25WF080B was tested under Linux with spidev. Tested-by: Ben Gardner <bgardner@wabtec.com> Signed-off-by: Ben Gardner <bgardner@wabtec.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1901 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix handling of write protection at register space address +2.stefanct2014-12-201-1/+0
| | | | | | | | | | | | | | | Since r1833 we added the offset of the virtual register in several functions, which produced segfaults. This patch renames a few parameters and reorganizes/fixes various parts of the changelock_regspace2_block() function - hence the rather big diff. Thanks to Roman Lebedev for reporting this issue and testing numerous revisions of this patch. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Unify non-shifted and shifted JEDEC access.stefanct2014-08-081-6/+0
| | | | | | | | | | | | | | | | | | Some Parallel bus chips have a 16-bit mode and an 8-bit mode. They use normal JEDEC addresses for 16-bit mode and shifted addresses (by 1 bit) for 8-bit mode. Some programmers can access them in 16-bit mode, but on all flashrom-supported programmers so far, we access them in 8-bit mode. This means we have to shift the addresses but apart from the addresses we can share the code. This patch makes this possible by checking the chip's FEATURE_ADDR_SHIFTED flag in common JEDEC functions and applying the right addresses respectively. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1840 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add a bunch of new/tested stuff and various small changes 21.stefanct2014-08-061-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested mainboards: OK: - ASUS F2A85-M Reported by various corebooters - ASUS M2N-MX SE Plus Reported by Antonio - ASUS P5LD2 Reported by François Revol - Lenovo ThinkPad T530 Reported and partially authored by Edward O'Callaghan - MSI MS-7502 (Medion MD8833) Reported by naq on IRC - Shuttle AB61 Reported by olofolleola4 - ZOTAC IONITX-F-E Reported by Bernardo Kuri Flash chips: - Atmel AT45DB021D to PREW (+PREW) Reported by The Raven - Atmel AT25F4096 to PREW (+PREW) Reported by 공준혁 - GigaDevice GD25Q16(B) to PREW (+PREW) Reported by luxflow@live.com using a GD25Q16BSIG - Catalyst CAT28F512 Mark erase and write as known bad (not implemented) Miscellaneous: - Various spelling corrections by Daniele Forsi. - Added and refined a bunch of chips originally investigated by Carl-Daniel. - Marked the ARM-USB-OCD-H programmer as tested (reported by Ruud Schramp). - Tiny other stuff. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for a bunch of 29GL parallel flash chips.stefanct2014-08-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | 29GL chips use a new 3-Byte device ID probing function at addresses 0x01, 0x0E, 0x0F. Flash chip families supported by this method include... - EON EN29GL - Gigadevice GD29GL (if they really exist) - ISSI (PMC) IS29GL - Macronix MX29GL (+MX68GL1G0F) - Spansion S29GL (+S70GL02G) - Winbond W29GL This patch adds respective flash chip definitions for chips up to 16 MB from Eon, ISSI, Macronix and Winbond. Bigger chips as well as those from Gigadevice and Spansion are left out. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1835 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Refactor unlocking of many chips with locking at register space address +2.stefanct2014-08-031-10/+9
| | | | | | | | | | | This includes PMC Pm49*, SST 49LF00*, ST M50* and Winbond W39* families. The erase and write test status bits of all affected chips have been reset. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Sanyo LE25FW106.stefanct2014-06-041-0/+1
| | | | | | | | | | | Also, add spi_disable_blockprotect_bp1_srwd(). Originally written and tested by The Raven <originalraven@hotmail.com>. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Combine block_erase*_en29lv640b and block_erase*_m29f400bt respectively.stefanct2014-06-011-4/+2
| | | | | | | | | | | | | | | This patch combines two identical block and chip erase functions respectively: - Merge block_erase_m29f400bt and block_erase_en29lv640b into erase_block_shifted_jedec. - Merge block_erase_chip_m29f400bt and block_erase_chip_en29lv640b into erase_chip_block_shifted_jedec. Leave their implementations in en29lv640b.c for now. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1808 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* jedec.c: constify a bit more.stefanct2014-05-291-4/+2
| | | | | | | | | | Also, include chipdrivers.h to find conflicting types between exported declarations and actual implementations. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1805 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Rename some spi_prettyprint_status_register_* functions.stefanct2014-05-271-4/+4
| | | | | | | | | | | | spi_prettyprint_status_register_default_bpX -> spi_prettyprint_status_register_bpX_srwd Why was the default in there anyway? :) Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1802 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for ESMT F25L32PA.stefanct2014-05-271-0/+1
| | | | | | | Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1801 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add 'const' keyword to chip write and other function prototypes.stefanct2014-05-091-13/+13
| | | | | | | | | | Inspired by and mostly based on a patch Signed-off-by: Mark Marshall <mark.marshall@omicron.at> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1789 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Cleanup ST M50 driver.stefanct2013-09-121-3/+4
| | | | | | | | | | | | | | | There are two locking strategies used by this umbrella family, one uniform and one that matches the sector layout of the chip. Refactor the functions involved and rename the overly complicated file to just stm50.c and the functions accordingly. This fixes unlocking of some of the non-uniform chips and gets rid of the abuse of page_size. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for AT45CS1282.stefanct2013-08-271-0/+1
| | | | | | | | | | | This one is even more strange than the AT45DB chips. Like the AT45DB321C it does not support any power-of-2 page sizes. There is only one asymmetrical eraser and that uses two opcodes. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1725 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for AT45DB321C.stefanct2013-08-271-0/+1
| | | | | | | | | | It seems like this model is one-of-a-kind... it shares some properties with the older versions of the AT45DB series as well as with new ones. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1724 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Atmel AT45DB* chips.stefanct2013-08-271-0/+12
| | | | | | | | Signed-off-by: Aidan Thornton <makosoft@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1723 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for remaining Numonyx (Micron) N25Q chips.stefanct2013-06-281-0/+3
| | | | | | | | | | | | | | | | | | | | Add... - N25Q128..3E - N25Q128..1E - N25Q256..1E (defunct due to addressing) - N25Q256..3E (defunct due to addressing) - N25Q512..1E (defunct due to addressing) - N25Q512..3E (defunct due to addressing) - N25Q00A..3G (defunct due to addressing) Also, refine existing family members. Signed-off-by: Nikolay Nikolaev <evrinoma@gmail.com> Reviewed-by: Steven Zakulec <spzakulec@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Spansion S25FL...S chips.stefanct2013-06-281-2/+2
| | | | | | | | | | | | | | | Add... - S25FL128S - S25FL256S uniform version (defunct due to addressing) - S25FL512S uniform version (defunct due to addressing) Merge Intel S33 status register functions with this one's. Signed-off-by: Nikolay Nikolaev <evrinoma@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1692 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Eon EN25S series.stefanct2013-06-281-0/+1
| | | | | | | | | | | | | | | | | | Add... - EN25S10 - EN25S20 - EN25S40 - EN25S80 - EN25S16 - EN25S32 - EN25S64 Signed-off-by: Nikolay Nikolaev <evrinoma@gmail.com> Reviewed-by: Steven Zakulec <spzakulec@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1687 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Introduce spi_block_erase_db().stefanct2013-06-281-0/+1
| | | | | | | | | | | | Used for page erase on some chips (e.g. Numonyx M45PE and Sanyo LF25FW series). Signed-off-by: Nikolay Nikolaev <evrinoma@gmail.com> Reviewed-by: Steven Zakulec <spzakulec@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Introduce additional SPI status register helpers.stefanct2013-06-281-1/+5
| | | | | | | | | | | | | | | | | | - spi_prettyprint_status_register_default_welwip(): It just prettyprints the plain hex value and the welwip bits. - spi_prettyprint_status_register_default_bp4(): Prints the hex value, welwip, bp0-5 and srwd bits. - spi_disable_blockprotect_bp2_srwd(), - spi_disable_blockprotect_bp3_srwd() and spi_disable_blockprotect_bp4_srwd(): Three new common block unprotection functions for the frequent cases where there is a status register lock bit at bit #7 and some block protection bits at bits #2-#4, #2-#5 and #2-#6 respectively. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix unlocking function for most Atmel AT2[56]D* chips.stefanct2013-06-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | I broke unlocking them correctly in r1635 while refactoring (NB: the commit log including the overly selfconfident statement about the "bug in spi_disable_blockprotect_at25df()"). Affected chips have per sector protection bits and the write protection bits in the status register do indicate if none, some or all sectors are protected. It is possible to globally (un)lock all sectors at once but in a way that was not anticipated when refactoring the spi25 unlocking functions into spi_disable_blockprotect_generic(). To globally unprotect not only the protection bits (2 and 3) have 0 to be written to them but also bits 4 and 5 which normally would not be touched by spi_disable_blockprotect_generic(). Some of the chips also support a permanent lockdown with fuses which we do not handle yet. To fix this without copying the whole method I introduce another mask parameter to spi_disable_blockprotect_generic() namely unprotect_mask. See verbose comments inline for details. Also, prettyprint the status register after trying to disable the block protection fails. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Tested-by: Chi Zhang <zhangchi866@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1679 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Update spi_get_erasefn_from_opcode().stefanct2013-05-011-3/+3
| | | | | | | | | | We forgot to add a few SPI erase functions to the helper function that is used for SFDP. Also, sort the declarations in the header. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1672 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Refine PMC Pm25LV series.stefanct2013-04-191-0/+1
| | | | | | | | | | | | | | | | | | | - Add missing bits and resort chips - Refine Pm25LV512(A) and Pm25LV010 Due to manufacturer ID continuation this one needs a new probing function: probe_spi_res3() which should be refactored in the future. The datasheet describes a very weird order of ID bytes: Vendor byte, model byte, vendor continuation byte. Let's pretend we did not read that or the datasheet is bogus (although the datasheet of the successor series describes the same but luckily additionally to RDID). - Add Pm25LV010A This was tested by Chi Zhang: http://paste.flashrom.org/view.php?id=1573 Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1670 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Atmel's AT25F series of SPI flash chips.stefanct2012-12-291-0/+7
| | | | | | | | | | | | | | | | | | This adds support for the following chips: - AT25F512, AT25F512A, AT25F512B - AT25F1024, AT25F1024A - AT25F2048 - AT25F4096 Besides the definitions of the the chips in flashchips.c this includes - a dedicated probing method (probe_spi_at25f) - pretty printing methods (spi_prettyprint_status_register_at25f*), and - unlocking methods (spi_disable_blockprotect_at25f*) Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Intel S33 series flash chips.stefanct2012-12-291-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This includes: Bottom boot block: * 16Mb/2MB: QB25F160S33B8, QB25F016S33B8, QH25F160S33B8, QH25F016S33B8 * 32Mb/4MB: QB25F320S33B8, QH25F320S33B8 * 64Mb/8MB: QB25F640S33B8, QH25F640S33B8 Top boot block: * 16Mb/2MB: QB25F160S33T8, QB25F016S33T8, QH25F160S33T8, QH25F016S33T8 * 32Mb/4MB: QB25F320S33T8, QH25F320S33T8 * 64Mb/8MB: QB25F640S33T8, QH25F640S33T8 At least some seem to be marketed by other vendors (too?) but also with Intel's vendor ID. Besides a 0xC7 chip erase and a 0xD8 uniform 64kB block erase they support also erasing the top/bottom 8 8kB blocks with opcode 0x40. But since this command fails for all addresses outside those ranges, it is not easily implemented with flashrom's current code base and hence left out. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Improve SPI status register pretty printing.stefanct2012-12-291-24/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Move all functions related to SPI status registers to a new file spi25_statusreg.c. This includes the generic as well as the SST-specific functions from spi25.c and the chip-specific functions from a25.c and at25.c. - introduce helper functions * spi_prettyprint_status_register_hex() * spi_prettyprint_status_register_bpl() * spi_prettyprint_status_register_plain() Use the latter on every compatible flash chip that has no better printlock function set and get rid of the implicit pretty printing in the SPI probing functions. - remove * spi_prettyprint_status_register_common() * spi_prettyprint_status_register_amic_a25lq032() because it can be fully substituted with spi_prettyprint_status_register_amic_a25l032(). * spi_prettyprint_status_register() (old switch, no longer needed) - promote and export * spi_prettyprint_status_register_amic_a25l05p() as spi_prettyprint_status_register_default_bp1(). * spi_prettyprint_status_register_amic_a25l40p() as spi_prettyprint_status_register_default_bp2(). * spi_prettyprint_status_register_st_m25p() as spi_prettyprint_status_register_default_bp3(). - add #define TEST_BAD_REW and use it for a number of Atmel chips which had only TEST_BAD_READ set even though they dont have erasers or a write function set. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Winbond W39F010/W39L010/W39L020.stefanct2012-10-281-0/+3
| | | | | | | | | | | | | | | | W39F010 is a 128kB parallel 5V flash chip, 16k bootblocks. W39L010 is a 128kB parallel 3.3V flash chip, 8k bootblocks. W39L020 is a 256kB parallel 3.3V flash chip, 64k/16k bootblocks. The W39F010 code was tested with a satasii programmer. The first write attempt after an erase returned with verify failure, but the second write attempt was succesful: http://paste.flashrom.org/view.php?id=1418 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1620 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Atmel AT26DF041.stefanct2012-10-271-0/+2
| | | | | | | | | | | | | | | | | | Wicked chip: No WRSR, no write enable command (but swallows our default one without a problem), supports an auto-erasing page write (but even without that page writes are recommended to write the whole page i.e. operate on a completely erased page), mad requirements on block refreshments if only partly written. Found on my Intel D946GZIS and tested with my serprog in situ. Using the page write by setting JEDEC_BYTE_PROGRAM to 0x11 and using the spi_chip_write_256 command greatly improves performance and works flawlessly. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Generify a25.c's SRWD printing function and move it to spi25.c.stefanct2012-09-221-0/+1
| | | | | | | Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1602 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add a bunch of new/tested stuff and various small changes 14.stefanct2012-09-211-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested Mainboards: OK: - ASUS M3A78-EH http://www.flashrom.org/pipermail/flashrom/2010-October/005297.html - ASUS P2B-LS http://www.flashrom.org/pipermail/flashrom/2010-November/005506.html - Biostar TA790GX A3+ http://paste.flashrom.org/view.php?id=1350 - ECS 848P-A7 http://www.flashrom.org/pipermail/flashrom/2011-January/005781.html - GIGABYTE GA-G41MT-S2PT Reported on IRC - GIGABYTE GA-H77-D3H Reported and tested by Alexander Gordeev on IRC. - Gigabyte GA-X79-UD5 http://www.flashrom.org/pipermail/flashrom/2012-August/009811.html - Shuttle FN78S http://www.flashrom.org/pipermail/flashrom/2012-August/009714.html - VIA EITX-3000 Reported on IRC by Tuju NOT OK: - Dell PowerEdge C6220 (0HYFFG) http://www.flashrom.org/pipermail/flashrom/2012-September/009900.html - Foxconn Q45M http://www.flashrom.org/pipermail/flashrom/2012-September/009923.html - MSI MS-7309 (K9N6SGM-V) http://www.flashrom.org/pipermail/flashrom/2012-August/009712.html - Supermicro X9QRi-F+ http://www.flashrom.org/pipermail/flashrom/2012-September/009887.html - ZOTAC H61-ITX WiFi (H61ITX-A-E) http://www.flashrom.org/pipermail/flashrom/2012-August/009649.html ASUS CUSL2-C has been tested to be working with the board enable once implemented for the TUSL2-C board. They seem to have the same PCI IDs as shown in the links below. Since only the CUSL2-C board enable has been tested yet, we distinguish the two by DMI strings. http://paste.flashrom.org/view.php?id=1393 http://www.flashrom.org/pipermail/flashrom/attachments/20091206/ddca2c6c/attachment-0002.eml Tested flash chips: - Set EMST F25L008A to PREW (+PREW) http://www.flashrom.org/pipermail/flashrom/2012-August/009714.html - Set GigaDevice GD25Q64 to PREW (+PREW) http://git.chromium.org/gitweb/?p=chromiumos/third_party/flashrom.git;a=commit;h=9e8ef49b1f626c2197e131fba6c5b65c8af4eeea - Set Macronix MX25L12805 to P (+P) http://www.flashrom.org/pipermail/flashrom/2012-September/009887.html - Set SST SST49LF003A/B to PREW (+EW) http://paste.flashrom.org/view.php?id=467 - Set Winbond W49V002FA to PREW (+EW) http://www.flashrom.org/pipermail/flashrom/2011-January/005781.html Tested chipsets: - Intel X79 (0x1d41) http://www.flashrom.org/pipermail/flashrom/2012-August/009811.html Board enables: - add ASUS P4P800-X Created by Idwer Vollering and tested by Mingsen Bao: http://paste.flashrom.org/view.php?id=467 - add DMI string to P4P800-VM Miscellaneous: - Add remaining Intel 7 series chipset (LPC) PCI IDs - Add generic SPI detection for chips from Winbond - Minor manpage changes - Minor other cleanups - Escape full stops after abbreviations in the manpage. - Add ICH9 and successors to spi_get_valid_read_addr Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add spi_block_erase_62.stefanct2012-09-211-0/+1
| | | | | | | | | | | | This is used by the AT25F series (only?), but is generic enough to reside in spi25.c. The only currently supported chip is the AT25F512B. Other members of that series need some additional infrastructure code, hence this patch adds the erase function to the AT25F512B only. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Rename AT25F512B-specific code.stefanct2012-08-261-2/+2
| | | | | | | | | | | The AT25F512B is quite different from the other (older and yet unsupported) chips in the AT25F* familiy, hence rename 512B-specific stuff to make room for the generic AT25F* code. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Clean up a25.c, at25.c, spi25.c.stefanct2012-08-021-1/+1
| | | | | | | | | | | - introduce spi_prettyprint_status_register_atmel_at25_wpen() - use spi_prettyprint_status_register_bit() where possible - generify spi_prettyprint_status_register_bp3210 and use it in at25.c too Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for for the Atmel AT49F040 chip.uwe2012-04-151-0/+1
| | | | | | | | | | | | Chip features an optional permanent boot block write protection. Signed-off-by: David Borg <borg.db@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1522 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for the Eon EN29LV640B chip.uwe2012-04-141-0/+6
| | | | | | | | | | | | | | This chip needs special command sequences in 8 bit mode. Also, 8 bit programming needs actually 16bit double byte program. The chip is found on the Bifferos Bifferboard, for example. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1521 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for SFDP (JESD216).stefanct2012-02-171-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Similar to modules using the opaque programmer framework (e.g. ICH Hardware Sequencing) this uses a template struct flashchip element in flashchips.c with a special probe function that fills the obtained values into that struct. This allows yet unknown SPI chips to be supported (read, erase, write) almost as if it was already added to flashchips.c. Documentation used: http://www.jedec.org/standards-documents/docs/jesd216 (2011-04) W25Q32BV data sheet Revision F (2011-04-01) EN25QH16 data sheet Revision F (2011-06-01) MX25L6436E data sheet Revision 1.8 (2011-12-26) Tested-by: David Hendricks <dhendrix@google.com> on W25Q64CV + dediprog Tested-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> on a 2010 MX25L6436E with preliminary (i.e. incorrect) SFDP implementation + serprog Thanks also to Michael Karcher for his comments and preliminary review! Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1500 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add struct flashctx * parameter to all functions accessing flash chips.hailfinger2011-12-181-10/+10
| | | | | | | | | | | | | | | | | All programmer access function prototypes except init have been made static and moved to the respective file. A few internal functions in flash chip drivers had chipaddr parameters which are no longer needed. The lines touched by flashctx changes have been adjusted to 80 columns except in header files. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1474 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use struct flashctx instead of struct flashchip for flash chip accesshailfinger2011-12-141-84/+84
| | | | | | | | | | | | | | | | | | | | | | | struct flashchip is used only for the flashchips array and for operations which do not access hardware, e.g. printing a list of supported flash chips. struct flashctx (flash context) contains all data available in struct flashchip, but it also contains runtime information like mapping addresses. struct flashctx is expected to grow additional members over time, a prime candidate being programmer info. struct flashctx contains all of struct flashchip with identical member layout, but struct flashctx has additional members at the end. The separation between struct flashchip/flashctx shrinks the memory requirement of the big flashchips array and allows future extension of flashctx without having to worry about bloat. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Unsignify lengths and addresses in chip functions and structsstefanct2011-11-231-16/+16
| | | | | | | | | | Push those changes forward where needed to prevent new sign conversion warnings where possible. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1470 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add opaque programmer registration infrastructurehailfinger2011-11-041-0/+6
| | | | | | | | | | | | | An opaque programmer does not allow direct flash access and only offers abstract probe/read/erase/write methods. Due to that, opaque programmers need their own infrastructure and registration framework. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Revert "Unsignify lengths and addresses in chip functions and structs"stefanct2011-09-181-14/+14
| | | | | | | | | | | | | | | | | | | | - probe_timing was changed to unsigned although we use negative values for special cases - some code was not changed along hence did no longer compile: * dediprog's read and write functions * linux_spi's read and write functions - it introduced a number of new sign conversion warnings (http://paste.flashrom.org/view.php?id=832) To be safe this patch reverts all changes made in r1448, a corrected patch will follow later. Thanks to idwer for pointing out the problem first! Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1450 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Unsignify lengths and addresses in chip functions and structsstefanct2011-09-181-14/+14
| | | | | | | Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1448 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for the Sharp LH28F008BJT-BTLZ1 chip.uwe2011-08-251-0/+1
| | | | | | | | | | | | Tested by Mattias Mattsson <vitplister@gmail.com> on a PowerPC box. Signed-off-by: Mattias Mattsson <vitplister@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1420 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Remove unneeded inclusions of chipdrivers.hstefanct2011-08-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | this is related to the spi split patch as discussed in: http://www.flashrom.org/pipermail/flashrom/2010-February/thread.html#2364 the old commit (r914) log notes: "Some of the spi programmer drivers required chipdrivers.h, needs fixing later: it87spi.c ichspi.c sb600spi.c wbsio_spi.c buspirate_spi.c ft2232spi.c bitbang_spi.c dediprog.c" there still remain a few cases where chipdrivers.h is needed: dediprog.c (spi_read_chunked and spi_write_chunked) it87spi.c (due to spi_write_enable and spi_read_status_register) wbsio_spi.c (spi_programmer registration only) besides that, there are also non-spi files that do not need it. also, add flash.h to chipdrivers.h because it uses some types of it and remove flashchips.h from print.c Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1414 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add lock printing for AMIC A25L05PT, A25L05PU, A25L10PT, A25L10PU,hailfinger2011-05-191-7/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | A25L20PT, A25L20PU, A25L40PT, A25L40PU, A25L80P, A25L16PT, A25L16PU, A25L512, A25L010, A25L020, A25L040, A25L080, A25L016, A25L032, A25LQ032 to a25.c. Add lock printing for Atmel AT26DF081A, AT26DF161, AT26DF161A, AT26DF321. Move Atmel AT25*/AT26* lock related functions originally added in r1115 from spi25.c to at25.c. For SPI chips the lock printing was handled by one common function, but sharing a common function which only is a big switch() statement doesn't make sense, especially if we can define lock printing functions per flash chip anyway. The printlock function pointer in struct flashchip is used to print status register and locking information, and serves as replacement for implicit status register and lock printing during probe. That code will later be changed to store locking info in a machine- accessible data structure so flashrom can handle locked regions correctly. Signed-off-by: Carl-Daniel Hailfinger<c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Remove erase_chip_stm50flw0x0xmkarcher2011-04-141-1/+0
| | | | | | | | | | | | | | | | As the comment indicates, that function is not a chip erase function at all, but a function calling a block eraser in a loop. So it adds no extra value to what we already have in the block_eraser infrastructure. Furthermore, that function assumes a uniform sector size layout, but is referenced from flash chip with non-uniform sector size layout, which is just wrong. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add W39L040mkarcher2011-03-061-0/+1
| | | | | | | Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* enable unlocking (erasing/writing) W39V040FB chipsmkarcher2010-12-261-0/+1
| | | | | | | | | | Add code for the unlocking (erasing/writing) of Winbond W39V040FB chips, enabling erasing/writing this type of chip. Signed-off-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Winbond W39V040FB and W39V040FC.hailfinger2010-12-051-4/+10
| | | | | | | | | | | | | | | | | | | | | Print lock status for all supported Winbond W39* chips: W39V040A, W39V040B, W39V040C, W39V040FA, W39V040FB, W39V040FC, W39V080A, W39V080FA, W39V080FA (dual mode). Fill in correct probe timing for Winbond W39V040C and W39V080FA. Please note that the W39V040B/W39V040FB pair has identical IDs, identical read/write/erase, but locking differs. Same applies to W39V040C/W39V040FC. This causes double detection on chipsets which support LPC and FWH, making flashing more difficult because the user has to select the correct chip. This is called the evil twin problem. A better evil twin handling (patch available) will resolve that problem. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1245 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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