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* Constify parameters and globals.stefanct2012-12-301-2/+2
| | | | | | | | | | | This makes some stuff const (partially to get a more convenient libflashrom interface). Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1639 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Improve SPI status register pretty printing.stefanct2012-12-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Move all functions related to SPI status registers to a new file spi25_statusreg.c. This includes the generic as well as the SST-specific functions from spi25.c and the chip-specific functions from a25.c and at25.c. - introduce helper functions * spi_prettyprint_status_register_hex() * spi_prettyprint_status_register_bpl() * spi_prettyprint_status_register_plain() Use the latter on every compatible flash chip that has no better printlock function set and get rid of the implicit pretty printing in the SPI probing functions. - remove * spi_prettyprint_status_register_common() * spi_prettyprint_status_register_amic_a25lq032() because it can be fully substituted with spi_prettyprint_status_register_amic_a25l032(). * spi_prettyprint_status_register() (old switch, no longer needed) - promote and export * spi_prettyprint_status_register_amic_a25l05p() as spi_prettyprint_status_register_default_bp1(). * spi_prettyprint_status_register_amic_a25l40p() as spi_prettyprint_status_register_default_bp2(). * spi_prettyprint_status_register_st_m25p() as spi_prettyprint_status_register_default_bp3(). - add #define TEST_BAD_REW and use it for a number of Atmel chips which had only TEST_BAD_READ set even though they dont have erasers or a write function set. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Do not read the flash chip twice in verification mode.stefanct2012-10-271-1/+1
| | | | | | | | | | | | | | | | | | Kyösti Mälkki noticed that we unnecessarily read the flash chip twice when called with --verify. The first one is the mandatory read before everything (to be able to detect the seriousness of errors), but the second one is not necessary because we can just use the former for the comparison. This introduces a small output change: previously we printed ERASE or VERIFY depending on the callee. This special case has been dropped because it is unnecessary to print it (and wrong for the verification function to need to know why it is verifying exactly). If an erase fails we mention that fact explicitly already, similar for verify. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Remove exit calls from print_supported_chips.stefanct2012-10-231-1/+1
| | | | | | | | | | | | Propagate the error code using return values instead, but let cli_classic.c still decide the ultimate return value of the process. Also, remove setting the ret value again after print_supported_wiki() - success is the default. Signed-off-by: Niklas Söderlund <niso@kth.se> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1614 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add a bunch of new/tested stuff and various small changes 14.stefanct2012-09-211-5/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested Mainboards: OK: - ASUS M3A78-EH http://www.flashrom.org/pipermail/flashrom/2010-October/005297.html - ASUS P2B-LS http://www.flashrom.org/pipermail/flashrom/2010-November/005506.html - Biostar TA790GX A3+ http://paste.flashrom.org/view.php?id=1350 - ECS 848P-A7 http://www.flashrom.org/pipermail/flashrom/2011-January/005781.html - GIGABYTE GA-G41MT-S2PT Reported on IRC - GIGABYTE GA-H77-D3H Reported and tested by Alexander Gordeev on IRC. - Gigabyte GA-X79-UD5 http://www.flashrom.org/pipermail/flashrom/2012-August/009811.html - Shuttle FN78S http://www.flashrom.org/pipermail/flashrom/2012-August/009714.html - VIA EITX-3000 Reported on IRC by Tuju NOT OK: - Dell PowerEdge C6220 (0HYFFG) http://www.flashrom.org/pipermail/flashrom/2012-September/009900.html - Foxconn Q45M http://www.flashrom.org/pipermail/flashrom/2012-September/009923.html - MSI MS-7309 (K9N6SGM-V) http://www.flashrom.org/pipermail/flashrom/2012-August/009712.html - Supermicro X9QRi-F+ http://www.flashrom.org/pipermail/flashrom/2012-September/009887.html - ZOTAC H61-ITX WiFi (H61ITX-A-E) http://www.flashrom.org/pipermail/flashrom/2012-August/009649.html ASUS CUSL2-C has been tested to be working with the board enable once implemented for the TUSL2-C board. They seem to have the same PCI IDs as shown in the links below. Since only the CUSL2-C board enable has been tested yet, we distinguish the two by DMI strings. http://paste.flashrom.org/view.php?id=1393 http://www.flashrom.org/pipermail/flashrom/attachments/20091206/ddca2c6c/attachment-0002.eml Tested flash chips: - Set EMST F25L008A to PREW (+PREW) http://www.flashrom.org/pipermail/flashrom/2012-August/009714.html - Set GigaDevice GD25Q64 to PREW (+PREW) http://git.chromium.org/gitweb/?p=chromiumos/third_party/flashrom.git;a=commit;h=9e8ef49b1f626c2197e131fba6c5b65c8af4eeea - Set Macronix MX25L12805 to P (+P) http://www.flashrom.org/pipermail/flashrom/2012-September/009887.html - Set SST SST49LF003A/B to PREW (+EW) http://paste.flashrom.org/view.php?id=467 - Set Winbond W49V002FA to PREW (+EW) http://www.flashrom.org/pipermail/flashrom/2011-January/005781.html Tested chipsets: - Intel X79 (0x1d41) http://www.flashrom.org/pipermail/flashrom/2012-August/009811.html Board enables: - add ASUS P4P800-X Created by Idwer Vollering and tested by Mingsen Bao: http://paste.flashrom.org/view.php?id=467 - add DMI string to P4P800-VM Miscellaneous: - Add remaining Intel 7 series chipset (LPC) PCI IDs - Add generic SPI detection for chips from Winbond - Minor manpage changes - Minor other cleanups - Escape full stops after abbreviations in the manpage. - Add ICH9 and successors to spi_get_valid_read_addr Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Make struct flashchip a field in struct flashctx instead of a complete copy.hailfinger2012-08-251-23/+3
| | | | | | | | | | | | | All the driver conversion work and cleanup has been done by Stefan. flashrom.c and cli_classic.c are a joint work of Stefan and Carl-Daniel. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1579 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Introduce enum test_state.stefanct2012-07-281-2/+5
| | | | | | | | | | | | | | | | Previously boards in the wiki were tagged either as working or as known bad. But we added support to various boards via board enables that were then never tested because the owners have not reported back. This can now be tagged with NT and is shown appropriately. Also, the underlying data structure indicating state was converted from macros to an enum while preserving original integer values and is used for programmers and chipsets too. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1555 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Hide hwaccess.h from public API.hailfinger2012-07-201-1/+0
| | | | | | | | | | | | | | Move hwaccess.h #include from flash.h to individual drivers. libflashrom users need flash.h, but they do not care about hwaccess.h and should not see its definitions because they may conflict with other hardware access functions and #defines used by the libflashrom user. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1549 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Bus Pirate buffer management revamphailfinger2012-06-081-0/+1
| | | | | | | | | | | | | | The buffer management of the Bus Pirate driver has been revamped to use grow-only buffers with a reasonable initial default size so realloc() will not have to be called in normal operation. A side effect is the ability to switch to a static buffer without major hassle. Handle OOM gracefully. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1541 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add logfile support to flashromhailfinger2012-06-061-1/+8
| | | | | | | | | | | | | | Usage: flashrom --output logfile.txt Logfile output has at least dbg2 verbosity or screen verbosity, whichever is greater. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested on Linux, Windows and FreeBSD. Acked-by: Idwer Vollering <vidwer@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1540 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Convert printf to msg_* where appropriate.hailfinger2012-05-141-9/+11
| | | | | | | | | | | | | | | | Clean up cli_output.c to be more readable. Use enum instead of #define for message levels. Kill a few exit(0) calls. Print the command line arguments in verbose mode. Move actions (--list-supported etc.) after argument sanity checks. Reduce the number of code paths which have their own programmer_shutdown(). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for SFDP (JESD216).stefanct2012-02-171-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Similar to modules using the opaque programmer framework (e.g. ICH Hardware Sequencing) this uses a template struct flashchip element in flashchips.c with a special probe function that fills the obtained values into that struct. This allows yet unknown SPI chips to be supported (read, erase, write) almost as if it was already added to flashchips.c. Documentation used: http://www.jedec.org/standards-documents/docs/jesd216 (2011-04) W25Q32BV data sheet Revision F (2011-04-01) EN25QH16 data sheet Revision F (2011-06-01) MX25L6436E data sheet Revision 1.8 (2011-12-26) Tested-by: David Hendricks <dhendrix@google.com> on W25Q64CV + dediprog Tested-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> on a 2010 MX25L6436E with preliminary (i.e. incorrect) SFDP implementation + serprog Thanks also to Michael Karcher for his comments and preliminary review! Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1500 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Warn of one-time programmable (OTP) memorystefanct2012-02-151-0/+1
| | | | | | | | | | | | | | | | | | Some flash chips contain OTP memory that we cannot read or write (yet). This prohibits us from cloning them, hence warn the user if we detect it. Not all variations of the tagged chips contain OTP memory. They are often only enabled on request or have there own ordering numbers. There is usually no way to distinguish them. Because this is a supposedly seldomly used feature the warning is shown in with dbg verbosity. The manpage is extended to describe the backgrounds a bit. This patch is based on the idea and code of Daniel Lenski. Signed-off-by: Daniel Lenski <dlenski@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1493 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add deferred --image processingstefanct2011-12-251-1/+2
| | | | | | | | | | | | | | | | | | | | | | | The general idea and most of the code are based on the following commits in the chromiumos flashrom tree: 8fc0740356ca15d02fb1c65ab43b10844f148c3b bb9049c66ca55e0dc621dd2c70b5d2cb6e5179bf Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> and the main part: d0ea9ed71e7f86bb8e8db2ca7c32a96de25343d8 Signed-off-by: David Hendricks <dhendrix@chromium.org> This implementation does not defer the processing until doit(), but after the argument parsing loop only (doit() should not contain argument checks). This allows to specify -i and -l parameters in any order. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: David Hendricks <dhendrix@google.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Have all programmer init functions register bus masters/programmershailfinger2011-12-201-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | All programmer types (Parallel, SPI, Opaque) now register themselves into a generic programmer list and probing is now programmer-centric instead of chip-centric. Registering multiple SPI/... masters at the same time is now possible without any problems. Handling multiple flash chips is still unchanged, but now we have the infrastructure to deal with "dual BIOS" and "one flash behind southbridge and one flash behind EC" sanely. A nice side effect is that this patch kills quite a few global variables and improves the situation for libflashrom. Hint for developers: struct {spi,par,opaque}_programmer now have a void *data pointer to store any additional programmer-specific data, e.g. hardware configuration info. Note: flashrom -f -c FOO -r forced_read.bin does not work anymore. We have to find an architecturally clean way to solve this. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1475 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add struct flashctx * parameter to all functions accessing flash chips.hailfinger2011-12-181-12/+12
| | | | | | | | | | | | | | | | | All programmer access function prototypes except init have been made static and moved to the respective file. A few internal functions in flash chip drivers had chipaddr parameters which are no longer needed. The lines touched by flashctx changes have been adjusted to 80 columns except in header files. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1474 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use struct flashctx instead of struct flashchip for flash chip accesshailfinger2011-12-141-16/+40
| | | | | | | | | | | | | | | | | | | | | | | struct flashchip is used only for the flashchips array and for operations which do not access hardware, e.g. printing a list of supported flash chips. struct flashctx (flash context) contains all data available in struct flashchip, but it also contains runtime information like mapping addresses. struct flashctx is expected to grow additional members over time, a prime candidate being programmer info. struct flashctx contains all of struct flashchip with identical member layout, but struct flashctx has additional members at the end. The separation between struct flashchip/flashctx shrinks the memory requirement of the big flashchips array and allows future extension of flashctx without having to worry about bloat. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Unsignify lengths and addresses in chip functions and structsstefanct2011-11-231-9/+11
| | | | | | | | | | Push those changes forward where needed to prevent new sign conversion warnings where possible. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1470 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add opaque programmer registration infrastructurehailfinger2011-11-041-1/+1
| | | | | | | | | | | | | An opaque programmer does not allow direct flash access and only offers abstract probe/read/erase/write methods. Due to that, opaque programmers need their own infrastructure and registration framework. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Revert "Unsignify lengths and addresses in chip functions and structs"stefanct2011-09-181-7/+7
| | | | | | | | | | | | | | | | | | | | - probe_timing was changed to unsigned although we use negative values for special cases - some code was not changed along hence did no longer compile: * dediprog's read and write functions * linux_spi's read and write functions - it introduced a number of new sign conversion warnings (http://paste.flashrom.org/view.php?id=832) To be safe this patch reverts all changes made in r1448, a corrected patch will follow later. Thanks to idwer for pointing out the problem first! Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1450 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Unsignify lengths and addresses in chip functions and structsstefanct2011-09-181-7/+7
| | | | | | | Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1448 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Introduce ERROR_FATAL, abort upon failed chipset enables.uwe2011-09-031-1/+4
| | | | | | | | | Signed-off-by: Tadas Slotkus <devtadas@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Move the main() function from flashrom.c to cli_classic.c.uwe2011-08-201-3/+0
| | | | | | | | | | | | | | | | | The file flashrom.c is part of libflashrom and should thus not contain a main() function, that would break compilation of all frontends using libflashrom. Also, cli_classic.c is the right place anyway, as it's the main() of the CLI tool. Rename the simple wrapper cli_classic() in cli_classic.c to main(), as it's not really needed. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1417 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Introduce msg_*dbg2stefanct2011-08-041-1/+5
| | | | | | | Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1404 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Rename CHIP_BUSTYPE_FOO to BUS_FOO.hailfinger2011-07-271-7/+7
| | | | | | | | | | It's shorter to type, and we have less problems with the 80 column limit. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* constify (a few) parameters in flashrom.c where possiblestefanct2011-06-261-6/+6
| | | | | | | Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1354 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Erase functions are no longer called from chip drivers and thus theirhailfinger2011-06-261-1/+0
| | | | | | | | | | | | | internal erase verification can be moved to generic code. This also makes it easier to skip the verify step if desired and to differentiate between failed command submission and failed erase verification. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use shutdown callback mechanism to shutdown programmersdhendrix2011-06-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch attempts to resolve some programmer shutdown ordering issues by having the programmer init functions register shutdown callbacks explicitly wherever it makes most sense. Before, assumptions were made that could lead to the internal programmer's state changing before the external programmer could be shut down properly. Now, each programmer cleans up after itself and (hopefully) performs each operation in the correct order. As a side-effect, this patch gives us a better usage model for reverse operations such as rpci_* and rmmio_*. In the long-run, this should make reversing the initialization process easier to understand, less tedious, and less error-prone. In short, this patch does the following: - Registers a shutdown callback during initialization for each programmer. - Kills the .shutdown function pointer from programmer_entry struct. Also, make most shutdown functions static. - Adds a few minor clean-ups and corrections (e.g. missing physunmap() calls). TODO: Remove forward declaration of serprog_shutdown() (added to simplify diff) Signed-off-by: David Hendricks <dhendrix@google.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1338 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* add a bunch of new/tested motherboards, board/chipset enables and flash ↵stefanct2011-06-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | chips etc 3 - mark AT25DF321 as fully tested http://www.flashrom.org/pipermail/flashrom/attachments/20110527/01f1868b/attachment-0001.log - mark 82802AB as fully tested http://www.flashrom.org/pipermail/flashrom/2011-April/006145.html - mark Pm49FL002 as fully tested http://pastebin.com/pb5NTCmW - add Supermicro X8DT3 to boards_known http://www.flashrom.org/pipermail/flashrom/attachments/20110527/01f1868b/attachment-0001.log - add Supermicro X5DP8-G2 to boards_known http://www.flashrom.org/pipermail/flashrom/2011-April/006145.html - add Supermicro X8SIE as NOT WORKING to boards_known http://www.flashrom.org/pipermail/flashrom/2011-May/006554.html - add a DMI search pattern for the ASUS A8N-SLI Deluxe board enable to mitigate misdetections http://www.flashrom.org/pipermail/flashrom/2010-August/004379.html http://www.flashrom.org/pipermail/flashrom/2011-May/006570.html also, fix some random white space errors and comments/strings Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add voltage ranges to the flashchipsstefanct2011-06-031-0/+4
| | | | | | | | Signed-off-by: Steven Zakulec <spzakulec@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1323 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* small fixesstefanct2011-05-281-0/+2
| | | | | | | | | | | - missing spaces in code and output - improved documentation/naming/output - missing line breaks in spi probing functions Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1321 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* whitespace, documentation and other small stuffstefanct2011-05-191-0/+5
| | | | | | | | | | | | | | | this patch combines three previously posted patches in a revised form. one is even stolen from Stefan Reinauer (remove umlauts from man page). Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Signed-off-by: Stefan Reinauer <reinauer@google.com> some parts are Acked-by: Carl-Daniel Hailfinger<c-d.hailfinger.devel.2006@gmx.net> the rest is Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1317 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Constify flashchips array.hailfinger2011-05-041-2/+2
| | | | | | | | | | This moves 99.5% of the .data section to .rodata (which ends up in .text). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This patch reduces the stack usage by declaring 'const' stack variableskrause2011-01-171-1/+1
| | | | | | | | | | | | | | as 'static const' so they end up in the .rodata section instead of being copied from there to the stack for every invocation of the corresponding function. As a plus we end up in having a smaller binary as the "copy from .rodata to stack" code isn't emitted by the compiler any more (roughly -100 bytes). Signed-off-by: Mathias Krause <mathias.krause@secunet.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Support setting the Dediprog SF100 SPI voltage.hailfinger2010-11-091-0/+1
| | | | | | | | | | | | Add a generic voltage parameter parser. Move tolower_string() from dummyflasher.c to flashrom.c to make it available everywhere. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1226 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add SPI flash emulation capability to the dummy programmer.hailfinger2010-11-011-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | You have to choose between - no emulation - ST M25P10.RES SPI flash chip (RES, page write) - SST SST25VF040.REMS SPI flash chip (REMS, byte write) - SST SST25VF032B SPI flash chip (RDID, AAI write) Example usage: flashrom -p dummy:emulate=SST25VF032B Flash image persistence is available as well. Example usage: flashrom -p dummy:image=dummy_simulator.rom Allow setting the max chunksize for page write with the dummy programmer. Example usage: flashrom -p dummy:spi_write_256_chunksize=5 Flash emulation is compiled in by default. This code helped me find and fix various bugs in the SPI write code as well as in the testsuite. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: David Hendricks <dhendrix@google.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add a reset to probe_jedec before we read the Chip's IDs.hailfinger2010-10-201-0/+1
| | | | | | | | | | | | | | | | | | | Previous probes might have had too short delays for entering ID mode, so the chip may still be in the process of entering the ID mode. Due to that, an additional delay before the reset makes sense. Add FEATURE_RESET_MASK to deal cleanly with those feature bits. Maciej Pijanka tested the patch and it fixes probing for him with some old Atmel chips. Signed-off-by: Sean Nelson <audiohacked@gmail.com> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Anders Juel Jensen <andersjjensen@gmail.com> Tested-by: Maciej Pijanka <maciej.pijanka@gmail.com> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1216 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Always read the flash chip before writing. This will allow flashrom tohailfinger2010-10-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | skip erase of already-erased blocks and to skip write of blocks which already have the wanted contents. Avoid emergency messages by checking if the chip contents after a failed write operation (erase/write) are unchanged. Keep the emergency messages after a failed pure erase. That part is debatable because if someone wants erase, he pretty sure doesn't care about the flash contents anymore. Please note that this introduces additional overhead of a full chip read before write. This is frowned upon by people with slow programmers. A followup patch will make this configurable. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1215 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Switch all flash chips to partial write.hailfinger2010-10-131-1/+1
| | | | | | | | | | | | | | | | The inner write functions which handle partial write are renamed to the original name of their wrappers. The write wrappers are removed. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Maciej Pijanka <maciej.pijanka@gmail.com> Tested-by: Andrew Morgan <ziltro@ziltro.com> Tested-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Idwer Vollering <vidwer@gmail.com> Tested-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1211 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* SPI write status register (WRSR) may take longer than 100 ms, and ithailfinger2010-10-081-0/+3
| | | | | | | | | | | makes sense to poll for completion in 10 ms steps until 5 s are over. This patch complements r1115. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Joshua Roys <roysjosh@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* flashrom -L output did not contain a list of programmers nor were allhailfinger2010-10-061-0/+1
| | | | | | | | | | | | programmers listed. Fix it and mention at least the name of each programmer. Wiki output is unchanged, and will need separate fixups. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Implement libpayload support and improve life for DOShailfinger2010-09-251-0/+2
| | | | | | | | | | | | | | | | | based flashrom, too: Change the physmap* behaviour to use (void*)-1 as error code instead of NULL. That way, 1:1 mapped memory can be supported properly because (void*)0 is not a magic pointer anymore. (void*)-1 on the other hand is a rather unlikely memory offset, so that should be safe. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1181 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add detailed status register printing and unlocking for all ATMEL AT25*hailfinger2010-07-291-1/+5
| | | | | | | | | | | | | | | | | chips. Add support for Atmel AT25DF081A and AT25DQ161. Some chips require EWSR before WRSR, others require WREN before WRSR, and some support both variants. Add feature_bits to select the correct SPI command, and default to EWSR. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Steven Rosario Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Split off programmer.h from flash.h.hailfinger2010-07-271-525/+0
| | | | | | | | | | | | | | | | | | | | | | Programmer specific functions are of absolutely no interest to any file except those dealing with programmer specific actions (special SPI commands and the generic core). The new header structure is as follows (and yes, improvements are possible): flashchips.h flash chip IDs chipdrivers.h chip-specific read/write/... functions flash.h common header for all stuff that doesn't fit elsewhere hwaccess.h hardware access functions programmer.h programmer specific functions coreboot_tables.h header from coreboot, internal programmer only spi.h SPI command definitions Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Convert all PCI-based external programmers to use special little-endianhailfinger2010-07-271-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | accessors for all MMIO regions of PCI devices. This patch does _not_ touch the internal programmer (which is PCI-based as well). Huge thanks go to Misha Manulis who worked with me to create a first version of this patch for the satasii programmer based on modification of generic code. Huge thanks also go to Segher Boessenkool for suggesting the pci_mmio_ prefix for the abstraction layer. NOTE to package maintainers: With this patch, compilation and usage of flashrom should be safe on x86, x86_64, MIPS (little and big endian) and PowerPC (big endian). The internal programmer is disabled on non-x86/x86_64 (but it compiles). The atahpt, nic3com, nicnatsemi, nicrealtek and rayer_spi can not be compiled on non-x86/x86_64 because port space I/O is not (yet) supported. Please compile with default settings on x86/x86_64 and with the following settings on all other architectures: make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no CONFIG_NICNATSEMI=no CONFIG_RAYER_SPI=no Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Misha Manulis <misha@manulis.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix compilation for CONFIG_INTERNAL=nomkarcher2010-07-241-0/+6
| | | | | | | | | broken by r1098 Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1104 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Move SB600 SPI initialization to sb600spi.cmkarcher2010-07-221-1/+1
| | | | | | | Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Move Intel SPI initialisation to ichspi.cmkarcher2010-07-221-3/+6
| | | | | | | | | | | Smarter version could decide whether SPI is vital or not depending on straps. Straps are currently implemented for ICH7. EP80579 is in the comment, PCH of 5 Series/3400 Series has "LPC, reserved, PCI, SPI". Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for RayeR SPIPGM hardware as described inhailfinger2010-07-211-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | http://rayer.ic.cz/elektro/spipgm.htm To use the RayeR driver, run flashrom -p rayer_spi -V Known bugs/limitations: - Won't compile/work on non-x86 architectures. - Will always use direct port I/O access. Log follows: flashrom v0.9.2-r1039 on MS-DOS 7 (i686), built with libpci 3.1.5, GCC 4.3.2, little endian Calibrating delay loop... OK. Initializing rayer_bitbang_spi programmer Using port 0x378 as I/O base for parallel port access. ... Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 ... Found chip "Macronix MX25L1605" (2048 KB, SPI) at physical address 0xffe00000. ... No operations were specified. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Martin Rehak <rayer@seznam.cz> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Check during SPI bitbang init that SPI bitbang master configuration ishailfinger2010-07-181-1/+1
| | | | | | | | | | correct. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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