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* Add a bunch of new/tested stuff and various small changes 21.stefanct2014-08-061-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested mainboards: OK: - ASUS F2A85-M Reported by various corebooters - ASUS M2N-MX SE Plus Reported by Antonio - ASUS P5LD2 Reported by François Revol - Lenovo ThinkPad T530 Reported and partially authored by Edward O'Callaghan - MSI MS-7502 (Medion MD8833) Reported by naq on IRC - Shuttle AB61 Reported by olofolleola4 - ZOTAC IONITX-F-E Reported by Bernardo Kuri Flash chips: - Atmel AT45DB021D to PREW (+PREW) Reported by The Raven - Atmel AT25F4096 to PREW (+PREW) Reported by 공준혁 - GigaDevice GD25Q16(B) to PREW (+PREW) Reported by luxflow@live.com using a GD25Q16BSIG - Catalyst CAT28F512 Mark erase and write as known bad (not implemented) Miscellaneous: - Various spelling corrections by Daniele Forsi. - Added and refined a bunch of chips originally investigated by Carl-Daniel. - Marked the ARM-USB-OCD-H programmer as tested (reported by Ruud Schramp). - Tiny other stuff. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add new programmer for SPI EEPROMs attached to Intel 82580 NICs.stefanct2014-07-281-3/+13
| | | | | | | | | | | | | | | | This patch lets you read and write the EEPROM on 82580-based gigabit NIC cards. So far it has been tested on copper NICs only, but other variants employing this controller should work too. It is a nice substitution for the official eeupdate tool. Speed is quite decent: less than 4 seconds for erases or writes of 32 kB. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Tested-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1832 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add IT8212F as programmer.stefanct2014-06-011-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | This PCI PATA controller can use 3V parallel flash up to 128 kB. My card was identified as: PCI 1283:8212, subsystem 1283:0001. and labelled as: Innovision Multimedia LTD. EIO ATA133 RAID (DM-8401 Ver A) This particular card did not require setting of any GPIO signals to enable flash writing. My card has Pm39LV512 in PLCC32 package without socket. Rebased by Stefan (automatic cleanup, some PCI changes, changed enable bit handling). Committed with test state NT because the rebased version was not tested on real hardware (yet). Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* atavia: Fix a few problems overlooked/introduced while rebasing.stefanct2014-06-011-1/+1
| | | | | | | Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1811 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add VIA VT6421A LPC programmer driver.stefanct2014-06-011-4/+21
| | | | | | | | | | | | | | | Due to the mysterious address handling of this chip the user can specify a base address with the offset parameter, e.g.: flashrom -p atavia:offset=0xFFF00000 Thanks to Idwer Vollering for his iterative testing of this code, as well as to Martijn Bastiaan who did the last tests before merging. Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* sbxxx: Add spispeed parameter.stefanct2014-05-161-0/+21
| | | | | | | | | | | | | | | | | Allow to set the SPI clock frequency on AMD chipsets with a programmer parameter. If the parameter is given (and matches a possible value), the SPI clock is set temporarily. Both registers are restored on programmer shutdown. Example: ./flashrom -p internal:spispeed="33 MHz" -V Possible values for spispeed are "16.5 MHz", "22 MHz", "33 MHz", "66 MHz", "100 MHZ" and "800 kHz" depending on the chipset generation. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add a bunch of new/tested stuff and various small changes 20.stefanct2014-05-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested mainboards: OK: - abit BX6 2.0 Reported by Stefan Tauner - Acer EM61SM/EM61PM (used in Acer Aspire T180) Reported by Benjamin Bellec - ADLINK Express-HR Reported by Obermair Thomas - ASUS M3N-H/HDMI Reported by Franc Serres - Attro G5G100-P Reported by Christoph Grenz - ASRock 960GM-GS3 FX Reported by Fuley Istvan - Elitegroup P6BAP-A+ (V2.2) Reported by Arnaldo Pirrone - Elitegroup GeForce7050M-M (V2.0) Reported by Leif Middelschulte - Fujitsu D3041-A1 (used in ESPRIMO P2560) Reported by Daggi Duck - GIGABYTE GA-8S648 Reported by TeslaBIOS - GIGABYTE GA-970A-D3P (rev. 1.0) Reported by Jean-Francois Pirus - GIGABYTE GA-B85M-D3H Reported by Mladen Milinković - GIGABYTE GA-X79-UD3 Reported by Jeff O'Neil - GIGABYTE GA-X79-UP4 (rev. 1.0) Reported by George Spelvin - GIGABYTE GA-Z68MA-D2H-B3 (rev. 1.3) Reported by Vangelis Skarmoutsos - GIGABYTE GA-Z87-HD3 Reported by virii5 - Lenovo Tilapia CRB Reported by jenkins56 on IRC - MSI GT60-2OD (notebook, only with layout patches) Reported by Vasiliy Vylegzhanin - MSI MS-6704 (845PE Max2 PCB 1.0) (Pure Version w/o raid) Reported by professorll - MSI MS-7399 1.1 (used in Acer Aspire M5640/M3640) Reported by Koen Rousseau - MSI MS-7125 (K8N Neo4(-F/FI/FX)) We had a board enable for that one for years, but it was not (and still is not) completely clear which boards are covered. - MSI MS-7522 (MSI X58 Pro-E) Reported by Gianluigi Tiesi - PCWARE APM80-D3 Reported by César Augusto Jakoby - Pegatron IPP7A-CP Reported by Илья Шипко - Supermicro H8QME-2 Reported by Greg Tippitt - Supermicro X7SPA-H Reported by Kyle Bentley - Supermicro X7SPE-HF-D525 Reported by Micah Anderson - Supermicro X8DTE Reported by Mark Nipper - Supermicro X8SIL-F Reported by Peter Samuelson - ZOTAC IONITX-A (-E) version Reported by Maciej Wroniecki NOT OK: - Supermicro X10SLM-F Reported by Micah Anderson Flash chips: - Atmel AT29C020 to PREW (+PREW) It was marked like that in the past, but I could not find the reason why the test bits were reset. Urja Rannikko tested it again and it still works. - Eon EN25F10 to PREW (+PREW) Reported by Stolmár Tamás - Eon EN25QH64 to PR (+PR) Reported by Vladimir 'φ-coder' Serbinenko - GigaDevice GD25Q32(B) to PREW (+PREW) Reported by mrnuke - Macronix MX25L512(E)/MX25V512(C) to PREW (+PREW) Reported by Jamie Nichol - Macronix MX25L2005(C) to PREW (+PREW) Reported by Давыдов Дмитрий - Micron/Numonyx/ST N25Q064..1E to PREW (+PREW) Reported by Paolo Zambotti - Pmc Pm25LD010(C) to PREW (+PREW) Reported by Vasile Ceteras - Micron/Numonyx/ST M25P16 to PREW (+EW) Reported by raven - Micron/Numonyx/ST M25PX64 to PREW (+W) Reported by Zaolin - SST SST25VF020B to PREW (+PREW) Reported by Michaël Zweers - SST SST49LF040 to PREW (+W) Reported by Oskar Enoksson - Add support for MX25L3273E (evil twin of MX25L3205 et al.) Also, add MX25L1673 and MX25L6473E to the names of their twins and add a note about MX25L8073E. - Winbond W25X32 to PREW (+REW) Reported by The Raven - Winbond W29C010 etc. to PREW (+W) Reported by san Chipsets tested OK: - Intel NM70 (8086:1e5f) Reported by mrnuke - Intel C204 (8086:1c54) Reported by Vasiliy Vylegzhanin - Intel QM67 (8086:1c4f) Reported by Obermair Thomas - Intel HM77 (8086:1e57) Reported by Vasiliy Vylegzhanin - Intel B85 (8086:8c50) Reported by Mladen Milinković - Intel HM87 (8086:8c4b) Reported by Vasiliy Vylegzhanin - Intel Z87 (8086:8c44) Reported by virii5 - NVIDIA MCP51 (10de:0261) Reported by Marcin Kościelnicki - SiS 648 (1039:0648) Reported by TeslaBIOS Miscellaneous: - Mark ARM-USB-TINY-H as tested in ft2232_spi (reported by _nanodev_). - getrevision.sh: Ignore failing date calls. - getrevision.sh: Fix -u and -l for older git versions which require = for the git log grep parameter. - Corrected K8T Neo2-F entries due to a report from Stelios Tsampas. - Add "-p internal" to output that requests users to send flashrom -V logs. - Add Macbook2,1, Thinkpad X230, EasyNote LM85 to laptop whitelist. - Tiny other stuff. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ft2232_spi: Add support for TUMPA Lite.stefanct2014-04-271-2/+2
| | | | | | | | | | | http://www.tiaowiki.com/w/TIAO_USB_Multi_Protocol_Adapter_Lite_User's_Manual Initial patch from Jadran Puharic <jpuharic@gmail.com>. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1781 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* rayer_spi: Add pinout for Wiggler LPT.stefanct2013-10-021-1/+4
| | | | | | | | | Signed-off-by: Maksim Kuleshov <mmcx@mail.ru> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: Maksim Kuleshov <mmcx@mail.ru> Acked-by: Kyösti Mälkki <kyosti.malkki@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1756 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* rayer_spi: Add pinout for Atmel STK200/300.stefanct2013-10-021-2/+2
| | | | | | | | Signed-off-by: Maksim Kuleshov <mmcx@mail.ru> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Acked-by: Kyösti Mälkki <kyosti.malkki@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* rayer_spi: Add pinout for Altera ByteBlasterMV.stefanct2013-10-021-2/+5
| | | | | | | | | | | | | There is a ByteBlasterII product that is only almost compatible. Signed-off-by: Maksim Kuleshov <mmcx@mail.ru> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: Maksim Kuleshov <mmcx@mail.ru> Acked-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* rayer_spi: Improve support for different pinouts.stefanct2013-10-021-4/+3
| | | | | | | | | | | | | | | Create a list of programmer types with names, test state and linked layouts. This list could be listed with flashrom -L in follow-up patches. Handle a bit in status register that is inverted, this will be used in different future programmer types. Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: Maksim Kuleshov <mmcx@mail.ru> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1753 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Enable fwh_idsel parameter for C-ICH and ICH2/3/4/5 chipsets.stefanct2013-09-141-1/+1
| | | | | | | | | | Register locations are different from ICH6, but otherwise appear to have identical bit specifications and defaults. Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1748 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Remove exit call from sys_physmap_*.stefanct2013-09-131-2/+1
| | | | | | | | | | All callers are prepared to handle error if ERROR_PTR is returned. The Manpage mentioning the respective return code is readapted. Signed-off-by: Niklas Söderlund <niso@kth.se> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Automatically add version and date to the manpage.stefanct2013-08-291-0/+1046
To avoid funny effects of ever changing files tracked by the VCS this patch moves the manpage data to flashrom.8.tmpl and generates the actual manpage with a new makefile target if needed. Signed-Off-By: Joerg Mayer <jmayer@loplof.de> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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