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The vendor sold different designs under that name, the patch works with
the one that has an Actel FPGA as PCI-to-Flash bridge.
The Flash chip is a "Macronix MX29F001B" (128 KB, parallel) soldered
directly to the PCB.
Flash operations (PROBE, READ, ERASE, WRITE) work as expected.
Signed-off-by: TURBO J <turboj@gmx.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Reported by Mark Panajotovic <panajotovic.marko@gmail.com>.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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reduce #ifdef clauses a lot if we compile out some programmers
completely.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@679 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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abstraction.
Kill unneeded #include statements.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@672 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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this in the last commit. Also do some random cleanups while I'm at it.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Also, add Atmel AT29C512 support.
Both are tested on hardware by Maciej Pijanka.
Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@566 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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It doesn't make sense to probe for SPI chips on a LPC host, nor does it
make sense to probe for LPC chips on a Parallel host.
This change is backwards compatible, but adding host protocol info to
chipset init functions will speed up probing.
Once all chipset init functions are updated and the Winbond W29EE011 and
AMIC A49LF040A chip definitions are updated, the W29EE011 workaround can
be deleted as the W29/A49 conflict magically disappears.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested on real hardware and
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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and special handling here (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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(the 3C90xC ones don't). This is tested on hardware.
Also, add initial support for the Atmel AT29C010A chip (which I inserted
in a 3COM 3C90xB card for testing). It can be detected, read works, erase
works, but write will need some additional code (will post in another
patch later).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@520 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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chips in external flashers, they are not accessed via pointers at all.
Benefits:
This allows us to differentiate between volatile machine memory accesses
and flash chip accesses.
It also enforces usage of chip_{read,write}[bwl] to access flash chips,
so nobody will unintentionally use pointers to access chips anymore.
Some unneeded casts are removed as well.
Grepping for chip operations and machine memory operations doesn't yield
any false positives anymore.
Compile tested on 32 bit and 64 bit Linux.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@519 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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flasher infrastructure. The emulation works by splitting 32 bit accesses
into 16 bit accesses and 16 bit accesses into to 8 bit accesses.
That way, external flashers can mix and match the amount of emulation
they need.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@517 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Move the reusable PCI specific parts into pcidev.c, they'll be usable
for other NIC code (Realtek, VIA, ...) and also for SATA/IDE controller
cards as external programmers (for every PCI device which can program
EEPROMs basically).
Also add print_supported_pcidevs() to show the supported PCI devices
(currently only NICs, soon more) in the 'flashrom -L' output.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@515 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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multiple ones, abort with a message to the user, suggesting to use the
flashrom -p nic3com=bb:dd.f
syntax. If exactly one supported NIC is found, use it. If none is found,
abort with an error.
Print the bb:dd.f numbers for all supported NICs we find, so the user
doesn't have to poke around in lspci output to find the desired bb:dd.f.
Also, drop one pci_read_long() in favor of using the already existing
base_addr[0] struct field.
Drop the BAR in user messages, it's not really useful for us. Instead,
explain the BDF syntax a bit more verbosely.
While I'm at it, update the manpage some more to mention and fully document
the external programmer support we have (or will have soon).
The patch is tested on hardware:
$ flashrom -p nic3com
flashrom v0.9.0-r512
Found NIC "3COM 3C905C: EtherLink 10/100 PCI (TX)" (10b7:9200, BDF 05:04.0)
Found NIC "3COM 3C905C: EtherLink 10/100 PCI (TX)" (10b7:9200, BDF 05:03.0)
Error: Multiple supported NICs found. Please use 'flashrom -p nic3com=bb:dd.f'
to explicitly select the card with the given BDF (PCI bus, device, function).
$ flashrom -p nic3com=05:04.0
flashrom v0.9.0-r512
Found NIC "3COM 3C905C: EtherLink 10/100 PCI (TX)" (10b7:9200, BDF 05:04.0)
Calibrating delay loop... OK.
Found chip "Atmel AT49BV512" (64 KB) at physical address 0xffff0000.
No operations were specified.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@512 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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which all programmers can use, add missing close() call (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@511 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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notation, in case there are multiple NICs in one system.
Usage: flashrom -p nic3com=bb:ss.f
Signed-off-by: Christian Ruppert <spooky85@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@510 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@501 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This allows flashrom to identify, read, write, erase and verify flash chips
on (some) 3COM network cards. The patch uses the external programmer
infrastructure, the network card is basically treated as an external
flash programmer.
Usage:
$ ./flashrom -p nic3com
flashrom v0.9.0-r498
Found NIC "3COM 3C905C: EtherLink 10/100 PCI (TX)" (10b7:9200), addr = 0xa400
Calibrating delay loop... OK.
Found chip "Atmel AT49BV512" (64 KB) at physical address 0xffff0000.
No operations were specified.
$ ./flashrom -p nic3com -E
flashrom v0.9.0-r498
Found NIC "3COM 3C905C: EtherLink 10/100 PCI (TX)" (10b7:9200), addr = 0xa400
Calibrating delay loop... OK.
Found chip "Atmel AT49BV512" (64 KB) at physical address 0xffff0000.
Erasing flash chip... SUCCESS.
$ ./flashrom -p nic3com -wv backup.bin
flashrom v0.9.0-r498
Found NIC "3COM 3C905C: EtherLink 10/100 PCI (TX)" (10b7:9200), addr = 0xa400
Calibrating delay loop... OK.
Found chip "Atmel AT49BV512" (64 KB) at physical address 0xffff0000.
Flash image seems to be a legacy BIOS. Disabling checks.
Programming page: 1023 at address: 0x0000ffc0
Verifying flash... VERIFIED.
$ ./flashrom -p nic3com -r backup.bin
flashrom v0.9.0-r498
Found NIC "3COM 3C905C: EtherLink 10/100 PCI (TX)" (10b7:9200), addr = 0xa400
Calibrating delay loop... OK.
Found chip "Atmel AT49BV512" (64 KB) at physical address 0xffff0000.
Reading flash... done.
I have tested this on actual hardware (see PCI IDs above) and all
operations worked fine.
Support for other 3COM cards will follow (I added some more which should
be supportable by this code, but they're untested so far), as well as
support for NICs from other vendors.
The patch also adds support for the Atmel AT49BV512 which is soldered
onto the 3COM NIC I used for testing.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Mateusz Murawski <matowy@tlen.pl>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@499 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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