diff options
| author | Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com> | 2023-04-03 12:58:42 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-04-03 12:58:42 +0530 |
| commit | aba448be9c9c93c2435203fc0a970bb062561451 (patch) | |
| tree | 8bf39889a5ab711e98380eb8aa4259c35db80fd4 | |
| parent | 4408d7430e814364fd9f89b318a623e4ecaf9f12 (diff) | |
| download | freertos-git-aba448be9c9c93c2435203fc0a970bb062561451.tar.gz | |
Add register tests to H743ZI2 demo project (#977)
Add register tests to H743ZI2 demo project.
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: kar-rahul-aws <karahulx@amazon.com>
20 files changed, 8947 insertions, 1615 deletions
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/.gitignore b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/.gitignore index 09653aa29..4e9d49973 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/.gitignore +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/.gitignore @@ -11,8 +11,11 @@ EventRecorderStub.scvd # STM32CubeIDE autogenerated files. .settings/ +*.launch # Build Artifacts Debug/ Listings/ Objects/ +BrowseInfo/ +BuildLogs/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Config/FreeRTOSConfig.h index ab45ee9da..bbfb3caf6 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Config/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Config/FreeRTOSConfig.h @@ -139,4 +139,6 @@ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ * used. TEX=0, S=0, C=1, B=1. */ #define configTEX_S_C_B_SRAM ( 0x03UL ) +/* Do not allow critical sections from unprivileged tasks. */ +#define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 0 #endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/GCC/reg_tests_asm.c b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/GCC/reg_tests_asm.c new file mode 100644 index 000000000..3c02e6921 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/GCC/reg_tests_asm.c @@ -0,0 +1,988 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * "Reg test" tasks - These fill the registers with known values, then check + * that each register maintains its expected value for the lifetime of the + * task. Each task uses a different set of values. The reg test tasks execute + * with a very low priority, so get preempted very frequently. A register + * containing an unexpected value is indicative of an error in the context + * switching mechanism. + */ +/*-----------------------------------------------------------*/ + +/* Functions that implement reg tests. */ +void vRegTest1Asm( void ) __attribute__( ( naked ) ); +void vRegTest2Asm( void ) __attribute__( ( naked ) ); +void vRegTest3Asm( void ) __attribute__( ( naked ) ); +void vRegTest4Asm( void ) __attribute__( ( naked ) ); +/*-----------------------------------------------------------*/ + +void vRegTest1Asm( void ) /* __attribute__( ( naked ) ) */ +{ + __asm volatile + ( + ".extern ulRegTest1LoopCounter \n" + ".syntax unified \n" + " \n" + " /* Fill the core registers with known values. */ \n" + " movs r0, #100 \n" + " movs r1, #101 \n" + " movs r2, #102 \n" + " movs r3, #103 \n" + " movs r4, #104 \n" + " movs r5, #105 \n" + " movs r6, #106 \n" + " movs r7, #107 \n" + " mov r8, #108 \n" + " mov r9, #109 \n" + " mov r10, #110 \n" + " mov r11, #111 \n" + " mov r12, #112 \n" + " \n" + " /* Fill the FPU registers with known values. */ \n" + " vmov.f32 s1, #1.5 \n" + " vmov.f32 s2, #2.5 \n" + " vmov.f32 s3, #3.5 \n" + " vmov.f32 s4, #4.5 \n" + " vmov.f32 s5, #5.5 \n" + " vmov.f32 s6, #6.5 \n" + " vmov.f32 s7, #7.5 \n" + " vmov.f32 s8, #8.5 \n" + " vmov.f32 s9, #9.5 \n" + " vmov.f32 s10, #10.5 \n" + " vmov.f32 s11, #11.5 \n" + " vmov.f32 s12, #12.5 \n" + " vmov.f32 s13, #13.5 \n" + " vmov.f32 s14, #14.5 \n" + " vmov.f32 s15, #1.0 \n" + " vmov.f32 s16, #2.0 \n" + " vmov.f32 s17, #3.0 \n" + " vmov.f32 s18, #4.0 \n" + " vmov.f32 s19, #5.0 \n" + " vmov.f32 s20, #6.0 \n" + " vmov.f32 s21, #7.0 \n" + " vmov.f32 s22, #8.0 \n" + " vmov.f32 s23, #9.0 \n" + " vmov.f32 s24, #10.0 \n" + " vmov.f32 s25, #11.0 \n" + " vmov.f32 s26, #12.0 \n" + " vmov.f32 s27, #13.0 \n" + " vmov.f32 s28, #14.0 \n" + " vmov.f32 s29, #1.5 \n" + " vmov.f32 s30, #2.5 \n" + " vmov.f32 s31, #3.5 \n" + " \n" + "reg1_loop: \n" + " \n" + " /* Verify that core registers contain correct values. */ \n" + " cmp r0, #100 \n" + " bne reg1_error_loop \n" + " cmp r1, #101 \n" + " bne reg1_error_loop \n" + " cmp r2, #102 \n" + " bne reg1_error_loop \n" + " cmp r3, #103 \n" + " bne reg1_error_loop \n" + " cmp r4, #104 \n" + " bne reg1_error_loop \n" + " cmp r5, #105 \n" + " bne reg1_error_loop \n" + " cmp r6, #106 \n" + " bne reg1_error_loop \n" + " cmp r7, #107 \n" + " bne reg1_error_loop \n" + " cmp r8, #108 \n" + " bne reg1_error_loop \n" + " cmp r9, #109 \n" + " bne reg1_error_loop \n" + " cmp r10, #110 \n" + " bne reg1_error_loop \n" + " cmp r11, #111 \n" + " bne reg1_error_loop \n" + " cmp r12, #112 \n" + " bne reg1_error_loop \n" + " \n" + " /* Verify that FPU registers contain correct values. */ \n" + " vmov.f32 s0, #1.5 \n" /* s0 = 1.5. */ + " vcmp.f32 s1, s0 \n" /* Compare s0 and s1. */ + " vmrs APSR_nzcv, FPSCR \n" /* Copy floating point flags (FPSCR flags) to ASPR flags - needed for next bne to work. */ + " bne reg1_error_loop \n" + " vmov.f32 s0, #2.5 \n" + " vcmp.f32 s2, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #3.5 \n" + " vcmp.f32 s3, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #4.5 \n" + " vcmp.f32 s4, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #5.5 \n" + " vcmp.f32 s5, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #6.5 \n" + " vcmp.f32 s6, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #7.5 \n" + " vcmp.f32 s7, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #8.5 \n" + " vcmp.f32 s8, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #9.5 \n" + " vcmp.f32 s9, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #10.5 \n" + " vcmp.f32 s10, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #11.5 \n" + " vcmp.f32 s11, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #12.5 \n" + " vcmp.f32 s12, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #13.5 \n" + " vcmp.f32 s13, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #14.5 \n" + " vcmp.f32 s14, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #1.0 \n" + " vcmp.f32 s15, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #2.0 \n" + " vcmp.f32 s16, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #3.0 \n" + " vcmp.f32 s17, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #4.0 \n" + " vcmp.f32 s18, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #5.0 \n" + " vcmp.f32 s19, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #6.0 \n" + " vcmp.f32 s20, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #7.0 \n" + " vcmp.f32 s21, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #8.0 \n" + " vcmp.f32 s22, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #9.0 \n" + " vcmp.f32 s23, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #10.0 \n" + " vcmp.f32 s24, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #11.0 \n" + " vcmp.f32 s25, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #12.0 \n" + " vcmp.f32 s26, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #13.0 \n" + " vcmp.f32 s27, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #14.0 \n" + " vcmp.f32 s28, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #1.5 \n" + " vcmp.f32 s29, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #2.5 \n" + " vcmp.f32 s30, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #3.5 \n" + " vcmp.f32 s31, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " \n" + " /* Everything passed, inc the loop counter. */ \n" + " push { r0, r1 } \n" + " ldr r0, =ulRegTest1LoopCounter \n" + " ldr r1, [r0] \n" + " adds r1, r1, #1 \n" + " str r1, [r0] \n" + " \n" + " /* Yield to increase test coverage. */ \n" + " movs r0, #0x01 \n" + " ldr r1, =0xe000ed04 \n" /* NVIC_ICSR */ + " lsls r0, #28 \n" /* Shift to PendSV bit */ + " str r0, [r1] \n" + " dsb \n" + " pop { r0, r1 } \n" + " \n" + " /* Start again. */ \n" + " b reg1_loop \n" + " \n" + "reg1_error_loop: \n" + " /* If this line is hit then there was an error in \n" + " * a core register value. The loop ensures the \n" + " * loop counter stops incrementing. */ \n" + " b reg1_error_loop \n" + " nop \n" + ".ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +void vRegTest2Asm( void ) /* __attribute__( ( naked ) ) */ +{ + __asm volatile + ( + ".extern ulRegTest2LoopCounter \n" + ".syntax unified \n" + " \n" + " /* Fill the core registers with known values. */ \n" + " movs r0, #0 \n" + " movs r1, #1 \n" + " movs r2, #2 \n" + " movs r3, #3 \n" + " movs r4, #4 \n" + " movs r5, #5 \n" + " movs r6, #6 \n" + " movs r7, #7 \n" + " mov r8, #8 \n" + " mov r9, #9 \n" + " movs r10, #10 \n" + " movs r11, #11 \n" + " movs r12, #12 \n" + " \n" + " /* Fill the FPU registers with known values. */ \n" + " vmov.f32 s1, #1.0 \n" + " vmov.f32 s2, #2.0 \n" + " vmov.f32 s3, #3.0 \n" + " vmov.f32 s4, #4.0 \n" + " vmov.f32 s5, #5.0 \n" + " vmov.f32 s6, #6.0 \n" + " vmov.f32 s7, #7.0 \n" + " vmov.f32 s8, #8.0 \n" + " vmov.f32 s9, #9.0 \n" + " vmov.f32 s10, #10.0 \n" + " vmov.f32 s11, #11.0 \n" + " vmov.f32 s12, #12.0 \n" + " vmov.f32 s13, #13.0 \n" + " vmov.f32 s14, #14.0 \n" + " vmov.f32 s15, #1.5 \n" + " vmov.f32 s16, #2.5 \n" + " vmov.f32 s17, #3.5 \n" + " vmov.f32 s18, #4.5 \n" + " vmov.f32 s19, #5.5 \n" + " vmov.f32 s20, #6.5 \n" + " vmov.f32 s21, #7.5 \n" + " vmov.f32 s22, #8.5 \n" + " vmov.f32 s23, #9.5 \n" + " vmov.f32 s24, #10.5 \n" + " vmov.f32 s25, #11.5 \n" + " vmov.f32 s26, #12.5 \n" + " vmov.f32 s27, #13.5 \n" + " vmov.f32 s28, #14.5 \n" + " vmov.f32 s29, #1.0 \n" + " vmov.f32 s30, #2.0 \n" + " vmov.f32 s31, #3.0 \n" + " \n" + "reg2_loop: \n" + " \n" + " /* Verify that core registers contain correct values. */ \n" + " cmp r0, #0 \n" + " bne reg2_error_loop \n" + " cmp r1, #1 \n" + " bne reg2_error_loop \n" + " cmp r2, #2 \n" + " bne reg2_error_loop \n" + " cmp r3, #3 \n" + " bne reg2_error_loop \n" + " cmp r4, #4 \n" + " bne reg2_error_loop \n" + " cmp r5, #5 \n" + " bne reg2_error_loop \n" + " cmp r6, #6 \n" + " bne reg2_error_loop \n" + " cmp r7, #7 \n" + " bne reg2_error_loop \n" + " cmp r8, #8 \n" + " bne reg2_error_loop \n" + " cmp r9, #9 \n" + " bne reg2_error_loop \n" + " cmp r10, #10 \n" + " bne reg2_error_loop \n" + " cmp r11, #11 \n" + " bne reg2_error_loop \n" + " cmp r12, #12 \n" + " bne reg2_error_loop \n" + " \n" + " /* Verify that FPU registers contain correct values. */ \n" + " vmov.f32 s0, #1.0 \n" + " vcmp.f32 s1, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #2.0 \n" + " vcmp.f32 s2, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #3.0 \n" + " vcmp.f32 s3, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #4.0 \n" + " vcmp.f32 s4, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #5.0 \n" + " vcmp.f32 s5, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #6.0 \n" + " vcmp.f32 s6, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #7.0 \n" + " vcmp.f32 s7, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #8.0 \n" + " vcmp.f32 s8, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #9.0 \n" + " vcmp.f32 s9, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #10.0 \n" + " vcmp.f32 s10, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #11.0 \n" + " vcmp.f32 s11, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #12.0 \n" + " vcmp.f32 s12, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #13.0 \n" + " vcmp.f32 s13, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #14.0 \n" + " vcmp.f32 s14, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #1.5 \n" + " vcmp.f32 s15, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #2.5 \n" + " vcmp.f32 s16, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #3.5 \n" + " vcmp.f32 s17, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #4.5 \n" + " vcmp.f32 s18, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #5.5 \n" + " vcmp.f32 s19, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #6.5 \n" + " vcmp.f32 s20, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #7.5 \n" + " vcmp.f32 s21, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #8.5 \n" + " vcmp.f32 s22, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #9.5 \n" + " vcmp.f32 s23, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #10.5 \n" + " vcmp.f32 s24, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #11.5 \n" + " vcmp.f32 s25, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #12.5 \n" + " vcmp.f32 s26, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #13.5 \n" + " vcmp.f32 s27, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #14.5 \n" + " vcmp.f32 s28, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #1.0 \n" + " vcmp.f32 s29, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #2.0 \n" + " vcmp.f32 s30, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #3.0 \n" + " vcmp.f32 s31, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " \n" + " /* Everything passed, inc the loop counter. */ \n" + " push { r0, r1 } \n" + " ldr r0, =ulRegTest2LoopCounter \n" + " ldr r1, [r0] \n" + " adds r1, r1, #1 \n" + " str r1, [r0] \n" + " pop { r0, r1 } \n" + " \n" + " /* Start again. */ \n" + " b reg2_loop \n" + " \n" + "reg2_error_loop: \n" + " /* If this line is hit then there was an error in \n" + " * a core register value. The loop ensures the \n" + " * loop counter stops incrementing. */ \n" + " b reg2_error_loop \n" + " nop \n" + ".ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +void vRegTest3Asm( void ) /* __attribute__( ( naked ) ) */ +{ + __asm volatile + ( + ".extern ulRegTest3LoopCounter \n" + ".syntax unified \n" + " \n" + " /* Fill the core registers with known values. */ \n" + " movs r0, #100 \n" + " movs r1, #101 \n" + " movs r2, #102 \n" + " movs r3, #103 \n" + " movs r4, #104 \n" + " movs r5, #105 \n" + " movs r6, #106 \n" + " movs r7, #107 \n" + " mov r8, #108 \n" + " mov r9, #109 \n" + " mov r10, #110 \n" + " mov r11, #111 \n" + " mov r12, #112 \n" + " \n" + " /* Fill the FPU registers with known values. */ \n" + " vmov.f32 s0, #1.5 \n" + " vmov.f32 s2, #2.0 \n" + " vmov.f32 s3, #3.5 \n" + " vmov.f32 s4, #4.0 \n" + " vmov.f32 s5, #5.5 \n" + " vmov.f32 s6, #6.0 \n" + " vmov.f32 s7, #7.5 \n" + " vmov.f32 s8, #8.0 \n" + " vmov.f32 s9, #9.5 \n" + " vmov.f32 s10, #10.0 \n" + " vmov.f32 s11, #11.5 \n" + " vmov.f32 s12, #12.0 \n" + " vmov.f32 s13, #13.5 \n" + " vmov.f32 s14, #14.0 \n" + " vmov.f32 s15, #1.5 \n" + " vmov.f32 s16, #2.0 \n" + " vmov.f32 s17, #3.5 \n" + " vmov.f32 s18, #4.0 \n" + " vmov.f32 s19, #5.5 \n" + " vmov.f32 s20, #6.0 \n" + " vmov.f32 s21, #7.5 \n" + " vmov.f32 s22, #8.0 \n" + " vmov.f32 s23, #9.5 \n" + " vmov.f32 s24, #10.0 \n" + " vmov.f32 s25, #11.5 \n" + " vmov.f32 s26, #12.0 \n" + " vmov.f32 s27, #13.5 \n" + " vmov.f32 s28, #14.0 \n" + " vmov.f32 s29, #1.5 \n" + " vmov.f32 s30, #2.0 \n" + " vmov.f32 s31, #3.5 \n" + " \n" + "reg3_loop: \n" + " \n" + " /* Verify that core registers contain correct values. */ \n" + " cmp r0, #100 \n" + " bne reg3_error_loop \n" + " cmp r1, #101 \n" + " bne reg3_error_loop \n" + " cmp r2, #102 \n" + " bne reg3_error_loop \n" + " cmp r3, #103 \n" + " bne reg3_error_loop \n" + " cmp r4, #104 \n" + " bne reg3_error_loop \n" + " cmp r5, #105 \n" + " bne reg3_error_loop \n" + " cmp r6, #106 \n" + " bne reg3_error_loop \n" + " cmp r7, #107 \n" + " bne reg3_error_loop \n" + " cmp r8, #108 \n" + " bne reg3_error_loop \n" + " cmp r9, #109 \n" + " bne reg3_error_loop \n" + " cmp r10, #110 \n" + " bne reg3_error_loop \n" + " cmp r11, #111 \n" + " bne reg3_error_loop \n" + " cmp r12, #112 \n" + " bne reg3_error_loop \n" + " \n" + " /* Verify that FPU registers contain correct values. */ \n" + " vmov.f32 s1, #1.5 \n" + " vcmp.f32 s0, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #2.0 \n" + " vcmp.f32 s2, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #3.5 \n" + " vcmp.f32 s3, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #4.0 \n" + " vcmp.f32 s4, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #5.5 \n" + " vcmp.f32 s5, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #6.0 \n" + " vcmp.f32 s6, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #7.5 \n" + " vcmp.f32 s7, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #8.0 \n" + " vcmp.f32 s8, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #9.5 \n" + " vcmp.f32 s9, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #10.0 \n" + " vcmp.f32 s10, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #11.5 \n" + " vcmp.f32 s11, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #12.0 \n" + " vcmp.f32 s12, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #13.5 \n" + " vcmp.f32 s13, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #14.0 \n" + " vcmp.f32 s14, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #1.5 \n" + " vcmp.f32 s15, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #2.0 \n" + " vcmp.f32 s16, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #3.5 \n" + " vcmp.f32 s17, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #4.0 \n" + " vcmp.f32 s18, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #5.5 \n" + " vcmp.f32 s19, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #6.0 \n" + " vcmp.f32 s20, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #7.5 \n" + " vcmp.f32 s21, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #8.0 \n" + " vcmp.f32 s22, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #9.5 \n" + " vcmp.f32 s23, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #10.0 \n" + " vcmp.f32 s24, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #11.5 \n" + " vcmp.f32 s25, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #12.0 \n" + " vcmp.f32 s26, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #13.5 \n" + " vcmp.f32 s27, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #14.0 \n" + " vcmp.f32 s28, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #1.5 \n" + " vcmp.f32 s29, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #2.0 \n" + " vcmp.f32 s30, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #3.5 \n" + " vcmp.f32 s31, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " \n" + " /* Everything passed, inc the loop counter. */ \n" + " push { r0, r1 } \n" + " ldr r0, =ulRegTest3LoopCounter \n" + " ldr r1, [r0] \n" + " adds r1, r1, #1 \n" + " str r1, [r0] \n" + " \n" + " /* Yield to increase test coverage. */ \n" + " movs r0, #0x01 \n" + " ldr r1, =0xe000ed04 \n" /* NVIC_ICSR */ + " lsls r0, #28 \n" /* Shift to PendSV bit */ + " str r0, [r1] \n" + " dsb \n" + " pop { r0, r1 } \n" + " \n" + " /* Start again. */ \n" + " b reg3_loop \n" + " \n" + "reg3_error_loop: \n" + " /* If this line is hit then there was an error in \n" + " * a core register value. The loop ensures the \n" + " * loop counter stops incrementing. */ \n" + " b reg3_error_loop \n" + " nop \n" + ".ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +void vRegTest4Asm( void ) /* __attribute__( ( naked ) ) */ +{ + __asm volatile + ( + ".extern ulRegTest4LoopCounter \n" + ".syntax unified \n" + " \n" + " /* Fill the core registers with known values. */ \n" + " movs r0, #0 \n" + " movs r1, #1 \n" + " movs r2, #2 \n" + " movs r3, #3 \n" + " movs r4, #4 \n" + " movs r5, #5 \n" + " movs r6, #6 \n" + " movs r7, #7 \n" + " mov r8, #8 \n" + " mov r9, #9 \n" + " movs r10, #10 \n" + " movs r11, #11 \n" + " movs r12, #12 \n" + " \n" + " /* Fill the FPU registers with known values. */ \n" + " vmov.f32 s0, #1.5 \n" + " vmov.f32 s2, #2.0 \n" + " vmov.f32 s3, #3.0 \n" + " vmov.f32 s4, #4.5 \n" + " vmov.f32 s5, #5.0 \n" + " vmov.f32 s6, #6.0 \n" + " vmov.f32 s7, #7.5 \n" + " vmov.f32 s8, #8.0 \n" + " vmov.f32 s9, #9.0 \n" + " vmov.f32 s10, #10.5 \n" + " vmov.f32 s11, #11.0 \n" + " vmov.f32 s12, #12.0 \n" + " vmov.f32 s13, #13.5 \n" + " vmov.f32 s14, #14.0 \n" + " vmov.f32 s15, #1.0 \n" + " vmov.f32 s16, #2.5 \n" + " vmov.f32 s17, #3.0 \n" + " vmov.f32 s18, #4.0 \n" + " vmov.f32 s19, #5.5 \n" + " vmov.f32 s20, #6.0 \n" + " vmov.f32 s21, #7.0 \n" + " vmov.f32 s22, #8.5 \n" + " vmov.f32 s23, #9.0 \n" + " vmov.f32 s24, #10.0 \n" + " vmov.f32 s25, #11.5 \n" + " vmov.f32 s26, #12.0 \n" + " vmov.f32 s27, #13.0 \n" + " vmov.f32 s28, #14.5 \n" + " vmov.f32 s29, #1.0 \n" + " vmov.f32 s30, #2.0 \n" + " vmov.f32 s31, #3.5 \n" + " \n" + "reg4_loop: \n" + " \n" + " /* Verify that core registers contain correct values. */ \n" + " cmp r0, #0 \n" + " bne reg4_error_loop \n" + " cmp r1, #1 \n" + " bne reg4_error_loop \n" + " cmp r2, #2 \n" + " bne reg4_error_loop \n" + " cmp r3, #3 \n" + " bne reg4_error_loop \n" + " cmp r4, #4 \n" + " bne reg4_error_loop \n" + " cmp r5, #5 \n" + " bne reg4_error_loop \n" + " cmp r6, #6 \n" + " bne reg4_error_loop \n" + " cmp r7, #7 \n" + " bne reg4_error_loop \n" + " cmp r8, #8 \n" + " bne reg4_error_loop \n" + " cmp r9, #9 \n" + " bne reg4_error_loop \n" + " cmp r10, #10 \n" + " bne reg4_error_loop \n" + " cmp r11, #11 \n" + " bne reg4_error_loop \n" + " cmp r12, #12 \n" + " bne reg4_error_loop \n" + " \n" + " /* Verify that FPU registers contain correct values. */ \n" + " vmov.f32 s1, #1.5 \n" + " vcmp.f32 s0, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #2.0 \n" + " vcmp.f32 s2, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #3.0 \n" + " vcmp.f32 s3, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #4.5 \n" + " vcmp.f32 s4, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #5.0 \n" + " vcmp.f32 s5, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #6.0 \n" + " vcmp.f32 s6, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #7.5 \n" + " vcmp.f32 s7, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #8.0 \n" + " vcmp.f32 s8, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #9.0 \n" + " vcmp.f32 s9, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #10.5 \n" + " vcmp.f32 s10, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #11.0 \n" + " vcmp.f32 s11, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #12.0 \n" + " vcmp.f32 s12, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #13.5 \n" + " vcmp.f32 s13, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #14.0 \n" + " vcmp.f32 s14, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #1.0 \n" + " vcmp.f32 s15, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #2.5 \n" + " vcmp.f32 s16, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #3.0 \n" + " vcmp.f32 s17, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #4.0 \n" + " vcmp.f32 s18, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #5.5 \n" + " vcmp.f32 s19, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #6.0 \n" + " vcmp.f32 s20, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #7.0 \n" + " vcmp.f32 s21, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #8.5 \n" + " vcmp.f32 s22, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #9.0 \n" + " vcmp.f32 s23, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #10.0 \n" + " vcmp.f32 s24, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #11.5 \n" + " vcmp.f32 s25, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #12.0 \n" + " vcmp.f32 s26, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #13.0 \n" + " vcmp.f32 s27, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #14.5 \n" + " vcmp.f32 s28, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #1.0 \n" + " vcmp.f32 s29, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #2.0 \n" + " vcmp.f32 s30, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #3.5 \n" + " vcmp.f32 s31, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " \n" + " /* Everything passed, inc the loop counter. */ \n" + " push { r0, r1 } \n" + " ldr r0, =ulRegTest4LoopCounter \n" + " ldr r1, [r0] \n" + " adds r1, r1, #1 \n" + " str r1, [r0] \n" + " pop { r0, r1 } \n" + " \n" + " /* Start again. */ \n" + " b reg4_loop \n" + " \n" + "reg4_error_loop: \n" + " /* If this line is hit then there was an error in \n" + " * a core register value. The loop ensures the \n" + " * loop counter stops incrementing. */ \n" + " b reg4_error_loop \n" + " nop \n" + ".ltorg \n" + ); +} +/*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/IAR/reg_tests_asm.s b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/IAR/reg_tests_asm.s new file mode 100644 index 000000000..8e3345994 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/IAR/reg_tests_asm.s @@ -0,0 +1,956 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * "Reg test" - These fill the registers with known values, then check + * that each register maintains its expected value for the lifetime of the + * task. Each task uses a different set of values. The reg test tasks execute + * with a very low priority, so get preempted very frequently. A register + * containing an unexpected value is indicative of an error in the context + * switching mechanism. + */ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB + + EXTERN ulRegTest1LoopCounter + EXTERN ulRegTest2LoopCounter + EXTERN ulRegTest3LoopCounter + EXTERN ulRegTest4LoopCounter + + PUBLIC vRegTest1Asm + PUBLIC vRegTest2Asm + PUBLIC vRegTest3Asm + PUBLIC vRegTest4Asm +/*-----------------------------------------------------------*/ + +vRegTest1Asm: + /* Fill the core registers with known values. */ + movs r0, #100 + movs r1, #101 + movs r2, #102 + movs r3, #103 + movs r4, #104 + movs r5, #105 + movs r6, #106 + movs r7, #107 + movs r8, #108 + movs r9, #109 + movs r10, #110 + movs r11, #111 + movs r12, #112 + + vmov.f32 s1, #1.5 + vmov.f32 s2, #2.5 + vmov.f32 s3, #3.5 + vmov.f32 s4, #4.5 + vmov.f32 s5, #5.5 + vmov.f32 s6, #6.5 + vmov.f32 s7, #7.5 + vmov.f32 s8, #8.5 + vmov.f32 s9, #9.5 + vmov.f32 s10, #10.5 + vmov.f32 s11, #11.5 + vmov.f32 s12, #12.5 + vmov.f32 s13, #13.5 + vmov.f32 s14, #14.5 + vmov.f32 s15, #1.0 + vmov.f32 s16, #2.0 + vmov.f32 s17, #3.0 + vmov.f32 s18, #4.0 + vmov.f32 s19, #5.0 + vmov.f32 s20, #6.0 + vmov.f32 s21, #7.0 + vmov.f32 s22, #8.0 + vmov.f32 s23, #9.0 + vmov.f32 s24, #10.0 + vmov.f32 s25, #11.0 + vmov.f32 s26, #12.0 + vmov.f32 s27, #13.0 + vmov.f32 s28, #14.0 + vmov.f32 s29, #1.5 + vmov.f32 s30, #2.5 + vmov.f32 s31, #3.5 + + reg1_loop: + cmp r0, #100 + bne reg1_error_loop + cmp r1, #101 + bne reg1_error_loop + cmp r2, #102 + bne reg1_error_loop + cmp r3, #103 + bne reg1_error_loop + cmp r4, #104 + bne reg1_error_loop + cmp r5, #105 + bne reg1_error_loop + cmp r6, #106 + bne reg1_error_loop + cmp r7, #107 + bne reg1_error_loop + cmp r8, #108 + bne reg1_error_loop + cmp r9, #109 + bne reg1_error_loop + cmp r10, #110 + bne reg1_error_loop + cmp r11, #111 + bne reg1_error_loop + cmp r12, #112 + bne reg1_error_loop + + /* Verify that FPU registers contain correct values. */ + vmov.f32 s0, #1.5 + vcmp.f32 s1, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #2.5 + vcmp.f32 s2, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #3.5 + vcmp.f32 s3, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #4.5 + vcmp.f32 s4, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #5.5 + vcmp.f32 s5, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #6.5 + vcmp.f32 s6, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #7.5 + vcmp.f32 s7, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #8.5 + vcmp.f32 s8, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #9.5 + vcmp.f32 s9, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #10.5 + vcmp.f32 s10, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #11.5 + vcmp.f32 s11, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #12.5 + vcmp.f32 s12, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #13.5 + vcmp.f32 s13, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #14.5 + vcmp.f32 s14, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #1.0 + vcmp.f32 s15, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #2.0 + vcmp.f32 s16, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #3.0 + vcmp.f32 s17, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #4.0 + vcmp.f32 s18, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #5.0 + vcmp.f32 s19, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #6.0 + vcmp.f32 s20, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #7.0 + vcmp.f32 s21, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #8.0 + vcmp.f32 s22, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #9.0 + vcmp.f32 s23, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #10.0 + vcmp.f32 s24, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #11.0 + vcmp.f32 s25, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #12.0 + vcmp.f32 s26, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #13.0 + vcmp.f32 s27, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #14.0 + vcmp.f32 s28, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #1.5 + vcmp.f32 s29, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #2.5 + vcmp.f32 s30, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #3.5 + vcmp.f32 s31, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + + /* Everything passed, inc the loop counter. */ + push { r0, r1 } + ldr r0, =ulRegTest1LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + + /* Yield to increase test coverage. */ + movs r0, #0x01 + ldr r1, =0xe000ed04 /* NVIC_ICSR. */ + lsls r0, r0, #28 /* Shift to PendSV bit. */ + str r0, [r1] + dsb + pop { r0, r1 } + + /* Start again. */ + b reg1_loop + + reg1_error_loop: + b reg1_error_loop + nop + ltorg /* Create a literal pool to ensure that the constants accessed in the above + * code are not out of range. */ + +/*-----------------------------------------------------------*/ + +vRegTest2Asm: + /* Fill the core registers with known values. */ + movs r0, #0 + movs r1, #1 + movs r2, #2 + movs r3, #3 + movs r4, #4 + movs r5, #5 + movs r6, #6 + movs r7, #7 + mov r8, #8 + mov r9, #9 + movs r10, #10 + movs r11, #11 + movs r12, #12 + + /* Fill the FPU registers with known values. */ + vmov.f32 s1, #1.0 + vmov.f32 s2, #2.0 + vmov.f32 s3, #3.0 + vmov.f32 s4, #4.0 + vmov.f32 s5, #5.0 + vmov.f32 s6, #6.0 + vmov.f32 s7, #7.0 + vmov.f32 s8, #8.0 + vmov.f32 s9, #9.0 + vmov.f32 s10, #10.0 + vmov.f32 s11, #11.0 + vmov.f32 s12, #12.0 + vmov.f32 s13, #13.0 + vmov.f32 s14, #14.0 + vmov.f32 s15, #1.5 + vmov.f32 s16, #2.5 + vmov.f32 s17, #3.5 + vmov.f32 s18, #4.5 + vmov.f32 s19, #5.5 + vmov.f32 s20, #6.5 + vmov.f32 s21, #7.5 + vmov.f32 s22, #8.5 + vmov.f32 s23, #9.5 + vmov.f32 s24, #10.5 + vmov.f32 s25, #11.5 + vmov.f32 s26, #12.5 + vmov.f32 s27, #13.5 + vmov.f32 s28, #14.5 + vmov.f32 s29, #1.0 + vmov.f32 s30, #2.0 + vmov.f32 s31, #3.0 + + reg2_loop: + /* Verify that core registers contain correct values. */ + cmp r0, #0 + bne reg2_error_loop + cmp r1, #1 + bne reg2_error_loop + cmp r2, #2 + bne reg2_error_loop + cmp r3, #3 + bne reg2_error_loop + cmp r4, #4 + bne reg2_error_loop + cmp r5, #5 + bne reg2_error_loop + cmp r6, #6 + bne reg2_error_loop + cmp r7, #7 + bne reg2_error_loop + cmp r8, #8 + bne reg2_error_loop + cmp r9, #9 + bne reg2_error_loop + cmp r10, #10 + bne reg2_error_loop + cmp r11, #11 + bne reg2_error_loop + cmp r12, #12 + bne reg2_error_loop + + /* Verify that FPU registers contain correct values. */ + vmov.f32 s0, #1.0 + vcmp.f32 s1, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #2.0 + vcmp.f32 s2, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #3.0 + vcmp.f32 s3, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #4.0 + vcmp.f32 s4, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #5.0 + vcmp.f32 s5, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #6.0 + vcmp.f32 s6, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #7.0 + vcmp.f32 s7, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #8.0 + vcmp.f32 s8, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #9.0 + vcmp.f32 s9, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #10.0 + vcmp.f32 s10, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #11.0 + vcmp.f32 s11, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #12.0 + vcmp.f32 s12, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #13.0 + vcmp.f32 s13, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #14.0 + vcmp.f32 s14, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #1.5 + vcmp.f32 s15, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #2.5 + vcmp.f32 s16, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #3.5 + vcmp.f32 s17, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #4.5 + vcmp.f32 s18, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #5.5 + vcmp.f32 s19, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #6.5 + vcmp.f32 s20, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #7.5 + vcmp.f32 s21, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #8.5 + vcmp.f32 s22, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #9.5 + vcmp.f32 s23, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #10.5 + vcmp.f32 s24, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #11.5 + vcmp.f32 s25, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #12.5 + vcmp.f32 s26, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #13.5 + vcmp.f32 s27, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #14.5 + vcmp.f32 s28, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #1.0 + vcmp.f32 s29, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #2.0 + vcmp.f32 s30, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #3.0 + vcmp.f32 s31, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + + /* Everything passed, inc the loop counter. */ + push { r0, r1 } + ldr r0, =ulRegTest2LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r0, r1 } + + /* Start again. */ + b reg2_loop + + reg2_error_loop: + b reg2_error_loop + nop + ltorg /* Create a literal pool to ensure that the constants accessed in the above + * code are not out of range. */ + +/*-----------------------------------------------------------*/ + +vRegTest3Asm: + /* Fill the core registers with known values. */ + movs r0, #100 + movs r1, #101 + movs r2, #102 + movs r3, #103 + movs r4, #104 + movs r5, #105 + movs r6, #106 + movs r7, #107 + mov r8, #108 + mov r9, #109 + mov r10, #110 + mov r11, #111 + mov r12, #112 + + /* Fill the FPU registers with known values. */ + vmov.f32 s0, #1.5 + vmov.f32 s2, #2.0 + vmov.f32 s3, #3.5 + vmov.f32 s4, #4.0 + vmov.f32 s5, #5.5 + vmov.f32 s6, #6.0 + vmov.f32 s7, #7.5 + vmov.f32 s8, #8.0 + vmov.f32 s9, #9.5 + vmov.f32 s10, #10.0 + vmov.f32 s11, #11.5 + vmov.f32 s12, #12.0 + vmov.f32 s13, #13.5 + vmov.f32 s14, #14.0 + vmov.f32 s15, #1.5 + vmov.f32 s16, #2.0 + vmov.f32 s17, #3.5 + vmov.f32 s18, #4.0 + vmov.f32 s19, #5.5 + vmov.f32 s20, #6.0 + vmov.f32 s21, #7.5 + vmov.f32 s22, #8.0 + vmov.f32 s23, #9.5 + vmov.f32 s24, #10.0 + vmov.f32 s25, #11.5 + vmov.f32 s26, #12.0 + vmov.f32 s27, #13.5 + vmov.f32 s28, #14.0 + vmov.f32 s29, #1.5 + vmov.f32 s30, #2.0 + vmov.f32 s31, #3.5 + + reg3_loop: + /* Verify that core registers contain correct values. */ + cmp r0, #100 + bne reg3_error_loop + cmp r1, #101 + bne reg3_error_loop + cmp r2, #102 + bne reg3_error_loop + cmp r3, #103 + bne reg3_error_loop + cmp r4, #104 + bne reg3_error_loop + cmp r5, #105 + bne reg3_error_loop + cmp r6, #106 + bne reg3_error_loop + cmp r7, #107 + bne reg3_error_loop + cmp r8, #108 + bne reg3_error_loop + cmp r9, #109 + bne reg3_error_loop + cmp r10, #110 + bne reg3_error_loop + cmp r11, #111 + bne reg3_error_loop + cmp r12, #112 + bne reg3_error_loop + + /* Verify that FPU registers contain correct values. */ + vmov.f32 s1, #1.5 + vcmp.f32 s0, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s2, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #3.5 + vcmp.f32 s3, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #4.0 + vcmp.f32 s4, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #5.5 + vcmp.f32 s5, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #6.0 + vcmp.f32 s6, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #7.5 + vcmp.f32 s7, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #8.0 + vcmp.f32 s8, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #9.5 + vcmp.f32 s9, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #10.0 + vcmp.f32 s10, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #11.5 + vcmp.f32 s11, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #12.0 + vcmp.f32 s12, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #13.5 + vcmp.f32 s13, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #14.0 + vcmp.f32 s14, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #1.5 + vcmp.f32 s15, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s16, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #3.5 + vcmp.f32 s17, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #4.0 + vcmp.f32 s18, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #5.5 + vcmp.f32 s19, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #6.0 + vcmp.f32 s20, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #7.5 + vcmp.f32 s21, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #8.0 + vcmp.f32 s22, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #9.5 + vcmp.f32 s23, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #10.0 + vcmp.f32 s24, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #11.5 + vcmp.f32 s25, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #12.0 + vcmp.f32 s26, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #13.5 + vcmp.f32 s27, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #14.0 + vcmp.f32 s28, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #1.5 + vcmp.f32 s29, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s30, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #3.5 + vcmp.f32 s31, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + + /* Everything passed, inc the loop counter. */ + push { r0, r1 } + ldr r0, =ulRegTest3LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + + /* Yield to increase test coverage. */ + movs r0, #0x01 + ldr r1, =0xe000ed04 /* NVIC_ICSR. */ + lsl r0, r0, #28 /* Shift to PendSV bit. */ + str r0, [r1] + dsb + pop { r0, r1 } + + /* Start again. */ + b reg3_loop + + reg3_error_loop: + b reg3_error_loop + nop + ltorg /* Create a literal pool to ensure that the constants accessed in the above + * code are not out of range. */ + +/*-----------------------------------------------------------*/ + +vRegTest4Asm: + /* Fill the core registers with known values. */ + movs r0, #0 + movs r1, #1 + movs r2, #2 + movs r3, #3 + movs r4, #4 + movs r5, #5 + movs r6, #6 + movs r7, #7 + mov r8, #8 + mov r9, #9 + movs r10, #10 + movs r11, #11 + movs r12, #12 + + /* Fill the FPU registers with known values. */ + vmov.f32 s0, #1.5 + vmov.f32 s2, #2.0 + vmov.f32 s3, #3.0 + vmov.f32 s4, #4.5 + vmov.f32 s5, #5.0 + vmov.f32 s6, #6.0 + vmov.f32 s7, #7.5 + vmov.f32 s8, #8.0 + vmov.f32 s9, #9.0 + vmov.f32 s10, #10.5 + vmov.f32 s11, #11.0 + vmov.f32 s12, #12.0 + vmov.f32 s13, #13.5 + vmov.f32 s14, #14.0 + vmov.f32 s15, #1.0 + vmov.f32 s16, #2.5 + vmov.f32 s17, #3.0 + vmov.f32 s18, #4.0 + vmov.f32 s19, #5.5 + vmov.f32 s20, #6.0 + vmov.f32 s21, #7.0 + vmov.f32 s22, #8.5 + vmov.f32 s23, #9.0 + vmov.f32 s24, #10.0 + vmov.f32 s25, #11.5 + vmov.f32 s26, #12.0 + vmov.f32 s27, #13.0 + vmov.f32 s28, #14.5 + vmov.f32 s29, #1.0 + vmov.f32 s30, #2.0 + vmov.f32 s31, #3.5 + + reg4_loop: + /* Verify that core registers contain correct values. */ + cmp r0, #0 + bne reg4_error_loop + cmp r1, #1 + bne reg4_error_loop + cmp r2, #2 + bne reg4_error_loop + cmp r3, #3 + bne reg4_error_loop + cmp r4, #4 + bne reg4_error_loop + cmp r5, #5 + bne reg4_error_loop + cmp r6, #6 + bne reg4_error_loop + cmp r7, #7 + bne reg4_error_loop + cmp r8, #8 + bne reg4_error_loop + cmp r9, #9 + bne reg4_error_loop + cmp r10, #10 + bne reg4_error_loop + cmp r11, #11 + bne reg4_error_loop + cmp r12, #12 + bne reg4_error_loop + + /* Verify that FPU registers contain correct values. */ + vmov.f32 s1, #1.5 + vcmp.f32 s0, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s2, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #3.0 + vcmp.f32 s3, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #4.5 + vcmp.f32 s4, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #5.0 + vcmp.f32 s5, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #6.0 + vcmp.f32 s6, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #7.5 + vcmp.f32 s7, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #8.0 + vcmp.f32 s8, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #9.0 + vcmp.f32 s9, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #10.5 + vcmp.f32 s10, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #11.0 + vcmp.f32 s11, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #12.0 + vcmp.f32 s12, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #13.5 + vcmp.f32 s13, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #14.0 + vcmp.f32 s14, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #1.0 + vcmp.f32 s15, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #2.5 + vcmp.f32 s16, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #3.0 + vcmp.f32 s17, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #4.0 + vcmp.f32 s18, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #5.5 + vcmp.f32 s19, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #6.0 + vcmp.f32 s20, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #7.0 + vcmp.f32 s21, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #8.5 + vcmp.f32 s22, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #9.0 + vcmp.f32 s23, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #10.0 + vcmp.f32 s24, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #11.5 + vcmp.f32 s25, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #12.0 + vcmp.f32 s26, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #13.0 + vcmp.f32 s27, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #14.5 + vcmp.f32 s28, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #1.0 + vcmp.f32 s29, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s30, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #3.5 + vcmp.f32 s31, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + + /* Everything passed, inc the loop counter. */ + push { r0, r1 } + ldr r0, =ulRegTest4LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r0, r1 } + + /* Start again. */ + b reg4_loop + + reg4_error_loop: + b reg4_error_loop + nop + ltorg /* Create a literal pool to ensure that the constants accessed in the above + * code are not out of range. */ + +/*-----------------------------------------------------------*/ + + END diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/RVDS/reg_tests_asm.s b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/RVDS/reg_tests_asm.s new file mode 100644 index 000000000..7bf441fdf --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/RVDS/reg_tests_asm.s @@ -0,0 +1,956 @@ +;/* +; * FreeRTOS V202212.00 +; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + +;/* +; * "Reg test" tasks - These fill the registers with known values, then check +; * that each register maintains its expected value for the lifetime of the +; * task. Each task uses a different set of values. The reg test tasks execute +; * with a very low priority, so get preempted very frequently. A register +; * containing an unexpected value is indicative of an error in the context +; * switching mechanism. +; */ +;/*-----------------------------------------------------------*/ + + IMPORT ulRegTest1LoopCounter + IMPORT ulRegTest2LoopCounter + IMPORT ulRegTest3LoopCounter + IMPORT ulRegTest4LoopCounter + + EXPORT vRegTest1Asm + EXPORT vRegTest2Asm + EXPORT vRegTest3Asm + EXPORT vRegTest4Asm + + AREA REG_TESTS_ASM, CODE, READONLY +;/*-----------------------------------------------------------*/ + +vRegTest1Asm + + PRESERVE8 + + ;/* Fill the core registers with known values. */ + movs r0, #100 + movs r1, #101 + movs r2, #102 + movs r3, #103 + movs r4, #104 + movs r5, #105 + movs r6, #106 + movs r7, #107 + mov r8, #108 + mov r9, #109 + mov r10, #110 + mov r11, #111 + mov r12, #112 + + ;/* Fill the FPU registers with known values. */ + vmov.f32 s1, #1.5 + vmov.f32 s2, #2.5 + vmov.f32 s3, #3.5 + vmov.f32 s4, #4.5 + vmov.f32 s5, #5.5 + vmov.f32 s6, #6.5 + vmov.f32 s7, #7.5 + vmov.f32 s8, #8.5 + vmov.f32 s9, #9.5 + vmov.f32 s10, #10.5 + vmov.f32 s11, #11.5 + vmov.f32 s12, #12.5 + vmov.f32 s13, #13.5 + vmov.f32 s14, #14.5 + vmov.f32 s15, #1.0 + vmov.f32 s16, #2.0 + vmov.f32 s17, #3.0 + vmov.f32 s18, #4.0 + vmov.f32 s19, #5.0 + vmov.f32 s20, #6.0 + vmov.f32 s21, #7.0 + vmov.f32 s22, #8.0 + vmov.f32 s23, #9.0 + vmov.f32 s24, #10.0 + vmov.f32 s25, #11.0 + vmov.f32 s26, #12.0 + vmov.f32 s27, #13.0 + vmov.f32 s28, #14.0 + vmov.f32 s29, #1.5 + vmov.f32 s30, #2.5 + vmov.f32 s31, #3.5 + +reg1_loop + ;/* Verify that core registers contain correct values. */ + cmp r0, #100 + bne.w reg1_error_loop + cmp r1, #101 + bne.w reg1_error_loop + cmp r2, #102 + bne.w reg1_error_loop + cmp r3, #103 + bne.w reg1_error_loop + cmp r4, #104 + bne.w reg1_error_loop + cmp r5, #105 + bne.w reg1_error_loop + cmp r6, #106 + bne.w reg1_error_loop + cmp r7, #107 + bne.w reg1_error_loop + cmp r8, #108 + bne.w reg1_error_loop + cmp r9, #109 + bne.w reg1_error_loop + cmp r10, #110 + bne.w reg1_error_loop + cmp r11, #111 + bne.w reg1_error_loop + cmp r12, #112 + bne.w reg1_error_loop + + ;/* Verify that FPU registers contain correct values. */ + vmov.f32 s0, #1.5 ;/* s0 = 1.5. */ + vcmp.f32 s1, s0 ;/* Compare s0 and s1. */ + vmrs APSR_nzcv, FPSCR ;/* Copy floating point flags (FPSCR flags) to ASPR flags - needed for next bne.w to work. */ + bne.w reg1_error_loop + vmov.f32 s0, #2.5 + vcmp.f32 s2, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #3.5 + vcmp.f32 s3, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #4.5 + vcmp.f32 s4, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #5.5 + vcmp.f32 s5, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #6.5 + vcmp.f32 s6, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #7.5 + vcmp.f32 s7, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #8.5 + vcmp.f32 s8, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #9.5 + vcmp.f32 s9, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #10.5 + vcmp.f32 s10, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #11.5 + vcmp.f32 s11, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #12.5 + vcmp.f32 s12, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #13.5 + vcmp.f32 s13, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #14.5 + vcmp.f32 s14, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #1.0 + vcmp.f32 s15, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #2.0 + vcmp.f32 s16, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #3.0 + vcmp.f32 s17, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #4.0 + vcmp.f32 s18, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #5.0 + vcmp.f32 s19, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #6.0 + vcmp.f32 s20, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #7.0 + vcmp.f32 s21, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #8.0 + vcmp.f32 s22, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #9.0 + vcmp.f32 s23, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #10.0 + vcmp.f32 s24, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #11.0 + vcmp.f32 s25, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #12.0 + vcmp.f32 s26, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #13.0 + vcmp.f32 s27, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #14.0 + vcmp.f32 s28, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #1.5 + vcmp.f32 s29, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #2.5 + vcmp.f32 s30, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + vmov.f32 s0, #3.5 + vcmp.f32 s31, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg1_error_loop + + ;/* Everything passed, inc the loop counter. */ + push { r0, r1 } + ldr r0, =ulRegTest1LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + + ;/* Yield to increase test coverage. */ + movs r0, #0x01 + ldr r1, =0xe000ed04 ;/* NVIC_ICSR. */ + lsls r0, #28 ;/* Shift to PendSV bit. */ + str r0, [r1] + dsb + pop { r0, r1 } + + ;/* Start again. */ + b reg1_loop + +reg1_error_loop + b reg1_error_loop + LTORG +;/*-----------------------------------------------------------*/ + +vRegTest2Asm + + PRESERVE8 + + ;/* Fill the core registers with known values. */ + movs r0, #0 + movs r1, #1 + movs r2, #2 + movs r3, #3 + movs r4, #4 + movs r5, #5 + movs r6, #6 + movs r7, #7 + mov r8, #8 + mov r9, #9 + movs r10, #10 + movs r11, #11 + movs r12, #12 + + ;/* Fill the FPU registers with known values. */ + vmov.f32 s1, #1.0 + vmov.f32 s2, #2.0 + vmov.f32 s3, #3.0 + vmov.f32 s4, #4.0 + vmov.f32 s5, #5.0 + vmov.f32 s6, #6.0 + vmov.f32 s7, #7.0 + vmov.f32 s8, #8.0 + vmov.f32 s9, #9.0 + vmov.f32 s10, #10.0 + vmov.f32 s11, #11.0 + vmov.f32 s12, #12.0 + vmov.f32 s13, #13.0 + vmov.f32 s14, #14.0 + vmov.f32 s15, #1.5 + vmov.f32 s16, #2.5 + vmov.f32 s17, #3.5 + vmov.f32 s18, #4.5 + vmov.f32 s19, #5.5 + vmov.f32 s20, #6.5 + vmov.f32 s21, #7.5 + vmov.f32 s22, #8.5 + vmov.f32 s23, #9.5 + vmov.f32 s24, #10.5 + vmov.f32 s25, #11.5 + vmov.f32 s26, #12.5 + vmov.f32 s27, #13.5 + vmov.f32 s28, #14.5 + vmov.f32 s29, #1.0 + vmov.f32 s30, #2.0 + vmov.f32 s31, #3.0 + +reg2_loop + ;/* Verify that core registers contain correct values. */ + cmp r0, #0 + bne.w reg2_error_loop + cmp r1, #1 + bne.w reg2_error_loop + cmp r2, #2 + bne.w reg2_error_loop + cmp r3, #3 + bne.w reg2_error_loop + cmp r4, #4 + bne.w reg2_error_loop + cmp r5, #5 + bne.w reg2_error_loop + cmp r6, #6 + bne.w reg2_error_loop + cmp r7, #7 + bne.w reg2_error_loop + cmp r8, #8 + bne.w reg2_error_loop + cmp r9, #9 + bne.w reg2_error_loop + cmp r10, #10 + bne.w reg2_error_loop + cmp r11, #11 + bne.w reg2_error_loop + cmp r12, #12 + bne.w reg2_error_loop + + ;/* Verify that FPU registers contain correct values. */ + vmov.f32 s0, #1.0 + vcmp.f32 s1, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #2.0 + vcmp.f32 s2, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #3.0 + vcmp.f32 s3, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #4.0 + vcmp.f32 s4, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #5.0 + vcmp.f32 s5, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #6.0 + vcmp.f32 s6, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #7.0 + vcmp.f32 s7, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #8.0 + vcmp.f32 s8, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #9.0 + vcmp.f32 s9, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #10.0 + vcmp.f32 s10, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #11.0 + vcmp.f32 s11, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #12.0 + vcmp.f32 s12, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #13.0 + vcmp.f32 s13, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #14.0 + vcmp.f32 s14, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #1.5 + vcmp.f32 s15, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #2.5 + vcmp.f32 s16, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #3.5 + vcmp.f32 s17, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #4.5 + vcmp.f32 s18, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #5.5 + vcmp.f32 s19, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #6.5 + vcmp.f32 s20, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #7.5 + vcmp.f32 s21, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #8.5 + vcmp.f32 s22, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #9.5 + vcmp.f32 s23, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #10.5 + vcmp.f32 s24, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #11.5 + vcmp.f32 s25, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #12.5 + vcmp.f32 s26, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #13.5 + vcmp.f32 s27, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #14.5 + vcmp.f32 s28, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #1.0 + vcmp.f32 s29, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #2.0 + vcmp.f32 s30, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + vmov.f32 s0, #3.0 + vcmp.f32 s31, s0 + vmrs APSR_nzcv, FPSCR + bne.w reg2_error_loop + + ;/* Everything passed, inc the loop counter. */ + push { r0, r1 } + ldr r0, =ulRegTest2LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r0, r1 } + + ;/* Start again. */ + b reg2_loop + +reg2_error_loop + b reg2_error_loop + LTORG +;/*-----------------------------------------------------------*/ + +vRegTest3Asm + + PRESERVE8 + + ;/* Fill the core registers with known values. */ + movs r0, #100 + movs r1, #101 + movs r2, #102 + movs r3, #103 + movs r4, #104 + movs r5, #105 + movs r6, #106 + movs r7, #107 + mov r8, #108 + mov r9, #109 + mov r10, #110 + mov r11, #111 + mov r12, #112 + + ;/* Fill the FPU registers with known values. */ + vmov.f32 s0, #1.5 + vmov.f32 s2, #2.0 + vmov.f32 s3, #3.5 + vmov.f32 s4, #4.0 + vmov.f32 s5, #5.5 + vmov.f32 s6, #6.0 + vmov.f32 s7, #7.5 + vmov.f32 s8, #8.0 + vmov.f32 s9, #9.5 + vmov.f32 s10, #10.0 + vmov.f32 s11, #11.5 + vmov.f32 s12, #12.0 + vmov.f32 s13, #13.5 + vmov.f32 s14, #14.0 + vmov.f32 s15, #1.5 + vmov.f32 s16, #2.0 + vmov.f32 s17, #3.5 + vmov.f32 s18, #4.0 + vmov.f32 s19, #5.5 + vmov.f32 s20, #6.0 + vmov.f32 s21, #7.5 + vmov.f32 s22, #8.0 + vmov.f32 s23, #9.5 + vmov.f32 s24, #10.0 + vmov.f32 s25, #11.5 + vmov.f32 s26, #12.0 + vmov.f32 s27, #13.5 + vmov.f32 s28, #14.0 + vmov.f32 s29, #1.5 + vmov.f32 s30, #2.0 + vmov.f32 s31, #3.5 + +reg3_loop + ;/* Verify that core registers contain correct values. */ + cmp r0, #100 + bne.w reg3_error_loop + cmp r1, #101 + bne.w reg3_error_loop + cmp r2, #102 + bne.w reg3_error_loop + cmp r3, #103 + bne.w reg3_error_loop + cmp r4, #104 + bne.w reg3_error_loop + cmp r5, #105 + bne.w reg3_error_loop + cmp r6, #106 + bne.w reg3_error_loop + cmp r7, #107 + bne.w reg3_error_loop + cmp r8, #108 + bne.w reg3_error_loop + cmp r9, #109 + bne.w reg3_error_loop + cmp r10, #110 + bne.w reg3_error_loop + cmp r11, #111 + bne.w reg3_error_loop + cmp r12, #112 + bne.w reg3_error_loop + + ;/* Verify that FPU registers contain correct values. */ + vmov.f32 s1, #1.5 + vcmp.f32 s0, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s2, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #3.5 + vcmp.f32 s3, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #4.0 + vcmp.f32 s4, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #5.5 + vcmp.f32 s5, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #6.0 + vcmp.f32 s6, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #7.5 + vcmp.f32 s7, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #8.0 + vcmp.f32 s8, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #9.5 + vcmp.f32 s9, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #10.0 + vcmp.f32 s10, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #11.5 + vcmp.f32 s11, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #12.0 + vcmp.f32 s12, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #13.5 + vcmp.f32 s13, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #14.0 + vcmp.f32 s14, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #1.5 + vcmp.f32 s15, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s16, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #3.5 + vcmp.f32 s17, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #4.0 + vcmp.f32 s18, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #5.5 + vcmp.f32 s19, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #6.0 + vcmp.f32 s20, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #7.5 + vcmp.f32 s21, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #8.0 + vcmp.f32 s22, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #9.5 + vcmp.f32 s23, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #10.0 + vcmp.f32 s24, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #11.5 + vcmp.f32 s25, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #12.0 + vcmp.f32 s26, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #13.5 + vcmp.f32 s27, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #14.0 + vcmp.f32 s28, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #1.5 + vcmp.f32 s29, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s30, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + vmov.f32 s1, #3.5 + vcmp.f32 s31, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg3_error_loop + + ;/* Everything passed, inc the loop counter. */ + push { r0, r1 } + ldr r0, =ulRegTest3LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + + ;/* Yield to increase test coverage. */ + movs r0, #0x01 + ldr r1, =0xe000ed04 ;/* NVIC_ICSR. */ + lsls r0, #28 ;/* Shift to PendSV bit. */ + str r0, [r1] + dsb + pop { r0, r1 } + + ;/* Start again. */ + b reg3_loop + +reg3_error_loop + b reg3_error_loop + LTORG +;/*-----------------------------------------------------------*/ + +vRegTest4Asm + + PRESERVE8 + + ;/* Fill the core registers with known values. */ + movs r0, #0 + movs r1, #1 + movs r2, #2 + movs r3, #3 + movs r4, #4 + movs r5, #5 + movs r6, #6 + movs r7, #7 + mov r8, #8 + mov r9, #9 + movs r10, #10 + movs r11, #11 + movs r12, #12 + + ;/* Fill the FPU registers with known values. */ + vmov.f32 s0, #1.5 + vmov.f32 s2, #2.0 + vmov.f32 s3, #3.0 + vmov.f32 s4, #4.5 + vmov.f32 s5, #5.0 + vmov.f32 s6, #6.0 + vmov.f32 s7, #7.5 + vmov.f32 s8, #8.0 + vmov.f32 s9, #9.0 + vmov.f32 s10, #10.5 + vmov.f32 s11, #11.0 + vmov.f32 s12, #12.0 + vmov.f32 s13, #13.5 + vmov.f32 s14, #14.0 + vmov.f32 s15, #1.0 + vmov.f32 s16, #2.5 + vmov.f32 s17, #3.0 + vmov.f32 s18, #4.0 + vmov.f32 s19, #5.5 + vmov.f32 s20, #6.0 + vmov.f32 s21, #7.0 + vmov.f32 s22, #8.5 + vmov.f32 s23, #9.0 + vmov.f32 s24, #10.0 + vmov.f32 s25, #11.5 + vmov.f32 s26, #12.0 + vmov.f32 s27, #13.0 + vmov.f32 s28, #14.5 + vmov.f32 s29, #1.0 + vmov.f32 s30, #2.0 + vmov.f32 s31, #3.5 + +reg4_loop + ;/* Verify that core registers contain correct values. */ + cmp r0, #0 + bne.w reg4_error_loop + cmp r1, #1 + bne.w reg4_error_loop + cmp r2, #2 + bne.w reg4_error_loop + cmp r3, #3 + bne.w reg4_error_loop + cmp r4, #4 + bne.w reg4_error_loop + cmp r5, #5 + bne.w reg4_error_loop + cmp r6, #6 + bne.w reg4_error_loop + cmp r7, #7 + bne.w reg4_error_loop + cmp r8, #8 + bne.w reg4_error_loop + cmp r9, #9 + bne.w reg4_error_loop + cmp r10, #10 + bne.w reg4_error_loop + cmp r11, #11 + bne.w reg4_error_loop + cmp r12, #12 + bne.w reg4_error_loop + + ;/* Verify that FPU registers contain correct values. */ + vmov.f32 s1, #1.5 + vcmp.f32 s0, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s2, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #3.0 + vcmp.f32 s3, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #4.5 + vcmp.f32 s4, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #5.0 + vcmp.f32 s5, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #6.0 + vcmp.f32 s6, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #7.5 + vcmp.f32 s7, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #8.0 + vcmp.f32 s8, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #9.0 + vcmp.f32 s9, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #10.5 + vcmp.f32 s10, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #11.0 + vcmp.f32 s11, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #12.0 + vcmp.f32 s12, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #13.5 + vcmp.f32 s13, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #14.0 + vcmp.f32 s14, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #1.0 + vcmp.f32 s15, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #2.5 + vcmp.f32 s16, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #3.0 + vcmp.f32 s17, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #4.0 + vcmp.f32 s18, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #5.5 + vcmp.f32 s19, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #6.0 + vcmp.f32 s20, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #7.0 + vcmp.f32 s21, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #8.5 + vcmp.f32 s22, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #9.0 + vcmp.f32 s23, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #10.0 + vcmp.f32 s24, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #11.5 + vcmp.f32 s25, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #12.0 + vcmp.f32 s26, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #13.0 + vcmp.f32 s27, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #14.5 + vcmp.f32 s28, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #1.0 + vcmp.f32 s29, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s30, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + vmov.f32 s1, #3.5 + vcmp.f32 s31, s1 + vmrs APSR_nzcv, FPSCR + bne.w reg4_error_loop + + ;/* Everything passed, inc the loop counter. */ + push { r0, r1 } + ldr r0, =ulRegTest4LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r0, r1 } + + ;/* Start again. */ + b reg4_loop + +reg4_error_loop + b reg4_error_loop + LTORG +;/*-----------------------------------------------------------*/ + + END
\ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/app_main.c b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/app_main.c index 2677c86f0..761b1ba23 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/app_main.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/app_main.c @@ -32,12 +32,16 @@ /* Demo includes. */ #include "mpu_demo.h" +#include "reg_tests.h" void app_main( void ) { /* Start the MPU demo. */ vStartMPUDemo(); + /* Start register tests. */ + vStartRegTests(); + /* Start the scheduler. */ vTaskStartScheduler(); diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/reg_tests.c b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/reg_tests.c new file mode 100644 index 000000000..d4efebfb6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/reg_tests.c @@ -0,0 +1,376 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Reg test includes. */ +#include "reg_tests.h" + +/* Hardware includes. */ +#include "main.h" + +/* + * Functions that implement reg test tasks. + */ +static void prvRegTest1Task( void * pvParameters ); +static void prvRegTest2Task( void * pvParameters ); +static void prvRegTest3Task( void * pvParameters ); +static void prvRegTest4Task( void * pvParameters ); + +/* + * Check task periodically checks that reg tests tasks + * are running fine. + */ +static void prvCheckTask( void * pvParameters ); + +/* + * Functions implemented in assembly. + */ +extern void vRegTest1Asm( void ); +extern void vRegTest2Asm( void ); +extern void vRegTest3Asm( void ); +extern void vRegTest4Asm( void ); +/*-----------------------------------------------------------*/ + +/* + * Priority of the check task. + */ +#define CHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) + +/* + * Frequency of check task. + */ +#define NO_ERROR_CHECK_TASK_PERIOD ( pdMS_TO_TICKS( 5000UL ) ) +#define ERROR_CHECK_TASK_PERIOD ( pdMS_TO_TICKS( 200UL ) ) + +/* + * Parameters passed to reg test tasks. + */ +#define REG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 ) +#define REG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 ) +#define REG_TEST_TASK_3_PARAMETER ( ( void * ) 0x12348765 ) +#define REG_TEST_TASK_4_PARAMETER ( ( void * ) 0x43215678 ) +/*-----------------------------------------------------------*/ + +/* + * The following variables are used to communicate the status of the register + * test tasks to the check task. If the variables keep incrementing, then the + * register test tasks have not discovered any errors. If a variable stops + * incrementing, then an error has been found. + */ +volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; +volatile unsigned long ulRegTest3LoopCounter = 0UL, ulRegTest4LoopCounter = 0UL; + +/** + * Counter to keep a count of how may times the check task loop has detected + * error. + */ +volatile unsigned long ulCheckTaskLoops = 0UL; +/*-----------------------------------------------------------*/ + +void vStartRegTests( void ) +{ +static StackType_t xRegTest1TaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ) ) ); +static StackType_t xRegTest2TaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ) ) ); +static StackType_t xRegTest3TaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ) ) ); +static StackType_t xRegTest4TaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ) ) ); +static StackType_t xCheckTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ) ) ); + +TaskParameters_t xRegTest1TaskParameters = +{ + .pvTaskCode = prvRegTest1Task, + .pcName = "RegTest1", + .usStackDepth = configMINIMAL_STACK_SIZE, + .pvParameters = REG_TEST_TASK_1_PARAMETER, + .uxPriority = tskIDLE_PRIORITY | portPRIVILEGE_BIT, + .puxStackBuffer = xRegTest1TaskStack, + .xRegions = { + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 } + } +}; +TaskParameters_t xRegTest2TaskParameters = +{ + .pvTaskCode = prvRegTest2Task, + .pcName = "RegTest2", + .usStackDepth = configMINIMAL_STACK_SIZE, + .pvParameters = REG_TEST_TASK_2_PARAMETER, + .uxPriority = tskIDLE_PRIORITY | portPRIVILEGE_BIT, + .puxStackBuffer = xRegTest2TaskStack, + .xRegions = { + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 } + } +}; +TaskParameters_t xRegTest3TaskParameters = +{ + .pvTaskCode = prvRegTest3Task, + .pcName = "RegTest3", + .usStackDepth = configMINIMAL_STACK_SIZE, + .pvParameters = REG_TEST_TASK_3_PARAMETER, + .uxPriority = tskIDLE_PRIORITY | portPRIVILEGE_BIT, + .puxStackBuffer = xRegTest3TaskStack, + .xRegions = { + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 } + } +}; +TaskParameters_t xRegTest4TaskParameters = +{ + .pvTaskCode = prvRegTest4Task, + .pcName = "RegTest4", + .usStackDepth = configMINIMAL_STACK_SIZE, + .pvParameters = REG_TEST_TASK_4_PARAMETER, + .uxPriority = tskIDLE_PRIORITY | portPRIVILEGE_BIT, + .puxStackBuffer = xRegTest4TaskStack, + .xRegions = { + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 } + } +}; + +TaskParameters_t xCheckTaskParameters = +{ + .pvTaskCode = prvCheckTask, + .pcName = "Check", + .usStackDepth = configMINIMAL_STACK_SIZE, + .pvParameters = NULL, + .uxPriority = ( CHECK_TASK_PRIORITY | portPRIVILEGE_BIT ), + .puxStackBuffer = xCheckTaskStack, + .xRegions = { + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 }, + { 0, 0, 0 } + } +}; + + xTaskCreateRestricted( &( xRegTest1TaskParameters ), NULL ); + xTaskCreateRestricted( &( xRegTest2TaskParameters ), NULL ); + xTaskCreateRestricted( &( xRegTest3TaskParameters ), NULL ); + xTaskCreateRestricted( &( xRegTest4TaskParameters ), NULL ); + xTaskCreateRestricted( &( xCheckTaskParameters ), NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvRegTest1Task( void * pvParameters ) +{ + /* Although the reg tests are written in assembly, its entry + * point is written in C for convenience of checking that the + * task parameter is being passed in correctly. */ + if( pvParameters == REG_TEST_TASK_1_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest1Asm(); + } + + /* The following line will only execute if the task parameter + * is found to be incorrect. The check task will detect that + * the reg test loop counter is not being incremented and flag + * an error. */ + vTaskDelete( NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvRegTest2Task( void * pvParameters ) +{ + /* Although the reg tests are written in assembly, its entry + * point is written in C for convenience of checking that the + * task parameter is being passed in correctly. */ + if( pvParameters == REG_TEST_TASK_2_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest2Asm(); + } + + /* The following line will only execute if the task parameter + * is found to be incorrect. The check task will detect that + * the reg test loop counter is not being incremented and flag + * an error. */ + vTaskDelete( NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvRegTest3Task( void * pvParameters ) +{ + /* Although the reg tests are written in assembly, its entry + * point is written in C for convenience of checking that the + * task parameter is being passed in correctly. */ + if( pvParameters == REG_TEST_TASK_3_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest3Asm(); + } + + /* The following line will only execute if the task parameter + * is found to be incorrect. The check task will detect that + * the reg test loop counter is not being incremented and flag + * an error. */ + vTaskDelete( NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvRegTest4Task( void * pvParameters ) +{ + /* Although the reg tests are written in assembly, its entry + * point is written in C for convenience of checking that the + * task parameter is being passed in correctly. */ + if( pvParameters == REG_TEST_TASK_4_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest4Asm(); + } + + /* The following line will only execute if the task parameter + * is found to be incorrect. The check task will detect that + * the reg test loop counter is not being incremented and flag + * an error. */ + vTaskDelete( NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void * pvParameters ) +{ +TickType_t xDelayPeriod = NO_ERROR_CHECK_TASK_PERIOD; +TickType_t xLastExecutionTime; +unsigned long ulErrorFound = pdFALSE; +static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; +static unsigned long ulLastRegTest3Value = 0, ulLastRegTest4Value = 0; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + /* Initialize xLastExecutionTime so the first call to vTaskDelayUntil() + * works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + * operating without error. The onboard LED is toggled on each iteration. + * If an error is detected then the delay period is decreased from + * mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has + * the effect of increasing the rate at which the onboard LED toggles, and + * in so doing gives visual feedback of the system status. */ + for( ;; ) + { + /* Delay until it is time to execute again. */ + vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound |= 1UL << 0UL; + } + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound |= 1UL << 1UL; + } + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Check that the register test 3 task is still running. */ + if( ulLastRegTest3Value == ulRegTest3LoopCounter ) + { + ulErrorFound |= 1UL << 2UL; + } + ulLastRegTest3Value = ulRegTest3LoopCounter; + + /* Check that the register test 4 task is still running. */ + if( ulLastRegTest4Value == ulRegTest4LoopCounter ) + { + ulErrorFound |= 1UL << 3UL; + } + ulLastRegTest4Value = ulRegTest4LoopCounter; + + + /* Toggle the green LED to give an indication of the system status. + * If the LED toggles every NO_ERROR_CHECK_TASK_PERIOD milliseconds + * then everything is ok. A faster toggle indicates an error. */ + HAL_GPIO_TogglePin( LD1_GPIO_Port, LD1_Pin ); + + if( ulErrorFound != pdFALSE ) + { + /* An error has been detected in one of the tasks - flash the LED + * at a higher frequency to give visible feedback that something has + * gone wrong (it might just be that the loop back connector required + * by the comtest tasks has not been fitted). */ + xDelayPeriod = ERROR_CHECK_TASK_PERIOD; + + /* Turn on Red LED to indicate error. */ + HAL_GPIO_WritePin( LD3_GPIO_Port, LD3_Pin, GPIO_PIN_SET ); + + /* Increment error detection count. */ + ulCheckTaskLoops++; + } + } +} +/*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/reg_tests.h b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/reg_tests.h new file mode 100644 index 000000000..0837aad72 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/reg_tests.h @@ -0,0 +1,35 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef REG_TESTS_H +#define REG_TESTS_H + +/** + * @brief Creates all the tasks for reg tests. + */ +void vStartRegTests( void ); + +#endif /* REG_TESTS_H */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/.cproject b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/.cproject index 852a26954..55f883f97 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/.cproject +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/.cproject @@ -10,6 +10,7 @@ <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/> <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> </extensions> </storageModule> <storageModule moduleId="cdtBuildSystem" version="4.0.0"> @@ -18,9 +19,9 @@ <toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug.373300876" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug"> <option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.type.1979309715" name="Internal Toolchain Type" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.type" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32" valueType="string"/> <option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.version.852833658" name="Internal Toolchain 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superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.244662906"/> + <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.682816493" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.1305239222"/> + <tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.890016239" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.938552426"/> + </toolChain> + </folderInfo> <folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.512177861.1706837772" name="/" resourcePath="ST_Code/Drivers/STM32H7xx_HAL_Driver/Src"> <toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug.1089770149" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug" unusedChildren=""> <option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.type.1979309715.1796819406" name="Internal Toolchain Type" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.type.1979309715"/> @@ -122,6 +149,7 @@ <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Config"/> <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Demo"/> <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="FreeRTOS"/> + <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="RegTests"/> <entry excluding="Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_utils.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="ST_Code"/> <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Startup"/> </sourceEntries> @@ -152,4 +180,4 @@ <resource resourceType="PROJECT" workspacePath="/FreeRTOSDemo"/> </configuration> </storageModule> -</cproject> +</cproject>
\ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/.project b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/.project index 21d9ba2d4..23501c2b0 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/.project +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/.project @@ -54,6 +54,15 @@ </linkedResources> <filteredResources> <filter> + <id>1680067487361</id> + <name>Demo</name> + <type>9</type> + <matcher> + <id>org.eclipse.ui.ide.multiFilter</id> + <arguments>1.0-name-matches-false-false-GCC</arguments> + </matcher> + </filter> + <filter> <id>1594591511105</id> <name>FreeRTOS</name> <type>5</type> diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/IAR/FreeRTOSDemo.ewd b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/IAR/FreeRTOSDemo.ewd index 926cc66f8..e380c1f25 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/IAR/FreeRTOSDemo.ewd +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/IAR/FreeRTOSDemo.ewd @@ -1,1419 +1,1546 @@ <?xml version="1.0" encoding="UTF-8"?> <project> - <fileVersion>3</fileVersion> - <configuration> - <name>FreeRTOSDemo</name> - <toolchain> - <name>ARM</name> - </toolchain> - <debug>1</debug> - <settings> - <name>C-SPY</name> - <archiveVersion>2</archiveVersion> - <data> - <version>29</version> - <wantNonLocal>1</wantNonLocal> - <debug>1</debug> - <option> - <name>CInput</name> - <state>1</state> - </option> - <option> - <name>CEndian</name> - <state>1</state> - </option> - <option> - <name>CProcessor</name> - <state>1</state> - </option> - <option> - <name>OCVariant</name> - <state>0</state> - </option> - <option> - <name>MacOverride</name> - <state>0</state> - </option> - <option> - <name>MacFile</name> - <state /> - </option> - <option> - <name>MemOverride</name> - <state>0</state> - </option> - <option> - <name>MemFile</name> - <state /> - </option> - <option> - <name>RunToEnable</name> - <state>1</state> - </option> - <option> - <name>RunToName</name> - <state>main</state> - </option> - <option> - <name>CExtraOptionsCheck</name> - <state>0</state> - </option> - <option> - <name>CExtraOptions</name> - <state /> - </option> - <option> - <name>CFpuProcessor</name> - <state>1</state> - </option> - <option> - <name>OCDDFArgumentProducer</name> - <state /> - </option> - <option> - <name>OCDownloadSuppressDownload</name> - <state>0</state> - </option> - <option> - <name>OCDownloadVerifyAll</name> - <state>1</state> - </option> - <option> - <name>OCProductVersion</name> - <state>7.10.3.6927</state> - </option> - <option> - <name>OCDynDriverList</name> - <state>STLINK_ID</state> - </option> - <option> - <name>OCLastSavedByProductVersion</name> - <state>8.20.1.14181</state> - </option> - <option> - <name>UseFlashLoader</name> - <state>1</state> - </option> - <option> - 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<version>0</version> + <state>0</state> + </option> + <option> + <name>CCMSPFetInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetTargetVccTypeDefault</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetTargetVoltage</name> + <state>###Uninitialized###</state> + </option> + <option> + <name>CCMSPFetVCCDefault</name> + <state>1</state> + </option> + <option> + <name>CCMSPFetTargetSettlingtime</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetRadioJtagSpeedType</name> + <state>1</state> + </option> + <option> + <name>CCMSPFetConnection</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCMSPFetUsbComPort</name> + <state>Automatic</state> + </option> + <option> + <name>CCMSPFetAllowAccessToBSL</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CCMSPFetLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCMSPFetRadioEraseFlash</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>XDS100_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>9</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>TIPackageOverride</name> + <state>0</state> + </option> + <option> + <name>TIPackage</name> + <state></state> + </option> + <option> + <name>BoardFile</name> + <state></state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCXds100BreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CCXds100DoUpdateBreakpoints</name> + <state>0</state> + </option> + <option> + <name>CCXds100UpdateBreakpoints</name> + <state>_call_main</state> + </option> + <option> + <name>CCXds100CatchReset</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchUndef</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSWI</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchData</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchPrefetch</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchIRQ</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchFIQ</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchMMERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchNOCPERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchCHRERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSTATERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchBUSERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchINTERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchSFERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchHARDERR</name> + <state>0</state> + </option> + <option> + <name>CCXds100CatchDummy</name> + <state>0</state> + </option> + <option> + <name>CCXds100CpuClockEdit</name> + <state></state> + </option> + <option> + <name>CCXds100SwoClockAuto</name> + <state>0</state> + </option> + <option> + <name>CCXds100SwoClockEdit</name> + <state>1000</state> + </option> + <option> + <name>CCXds100HWResetDelay</name> + <state>0</state> + </option> + <option> + <name>CCXds100ResetList</name> + <version>1</version> + <state>0</state> + </option> + <option> + <name>CCXds100UsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCXds100UsbSerialNoSelect</name> + <state>0</state> + </option> + <option> + <name>CCXds100JtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCXds100InterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>CCXds100InterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCXds100ProbeList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCXds100SWOPortRadio</name> + <state>0</state> + </option> + <option> + <name>CCXds100SWOPort</name> + <state>1</state> + </option> + <option> + <name>CCXDSTargetVccEnable</name> + <state>0</state> + </option> + <option> + <name>CCXDSTargetVoltage</name> + <state>###Uninitialized###</state> + </option> + <option> + <name>OCXDSDigitalStatesConfigFile</name> + <state>1</state> + </option> + <option> + <name>OCSelectedCoreName</name> + <state>1</state> + </option> + </data> + </settings> + <debuggerPlugins> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + </debuggerPlugins> + </configuration> </project> diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/IAR/FreeRTOSDemo.ewp b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/IAR/FreeRTOSDemo.ewp index 22a161f08..e7f646ee7 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/IAR/FreeRTOSDemo.ewp +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/IAR/FreeRTOSDemo.ewp @@ -11,10 +11,14 @@ <name>General</name> <archiveVersion>3</archiveVersion> <data> - <version>31</version> + <version>34</version> <wantNonLocal>1</wantNonLocal> <debug>1</debug> <option> + <name>BrowseInfoPath</name> + <state>BrowseInfo</state> + </option> + <option> <name>ExePath</name> <state>Debug</state> </option> @@ -66,15 +70,7 @@ </option> <option> <name>OGLastSavedByProductVersion</name> - <state>8.50.4.26131</state> - </option> - <option> - <name>GeneralEnableMisra</name> - <state>0</state> - </option> - <option> - <name>GeneralMisraVerbose</name> - <state>0</state> + <state>9.20.4.46976</state> </option> <option> <name>OGChipSelectEditMenu</name> @@ -97,26 +93,12 @@ <state>0</state> </option> <option> - <name>GeneralMisraRules98</name> - <version>0</version> - <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state> - </option> - <option> - <name>GeneralMisraVer</name> - <state>0</state> - </option> - <option> - <name>GeneralMisraRules04</name> - <version>0</version> - <state>011111111111111110111111111111011111111111111011110100111111111111111111111111111111111111111111101111111111111011111111111111111111111111111</state> - </option> - <option> <name>RTConfigPath2</name> <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Full.h</state> </option> <option> <name>GBECoreSlave</name> - <version>28</version> + <version>31</version> <state>41</state> </option> <option> @@ -133,7 +115,7 @@ </option> <option> <name>CoreVariant</name> - <version>28</version> + <version>31</version> <state>41</state> </option> <option> @@ -156,7 +138,7 @@ </option> <option> <name>GFPUCoreSlave2</name> - <version>28</version> + <version>31</version> <state>41</state> </option> <option> @@ -209,13 +191,25 @@ <version>0</version> <state>0</state> </option> + <option> + <name>OGAarch64Abi</name> + <state>0</state> + </option> + <option> + <name>OG_32_64Device</name> + <state>0</state> + </option> + <option> + <name>BuildFilesPath</name> + <state>BuildLogs</state> + </option> </data> </settings> <settings> <name>ICCARM</name> <archiveVersion>2</archiveVersion> <data> - <version>36</version> + <version>37</version> <wantNonLocal>1</wantNonLocal> <debug>1</debug> <option> @@ -345,10 +339,6 @@ <state></state> </option> <option> - <name>CompilerMisraOverride</name> - <state>0</state> - </option> - <option> <name>CCIncludePath2</name> <state>$PROJ_DIR$\..\..\ST_Code\Core\Inc</state> <state>$PROJ_DIR$\..\..\ST_Code\Drivers\STM32H7xx_HAL_Driver\Inc</state> @@ -386,16 +376,6 @@ <state>0</state> </option> <option> - <name>CompilerMisraRules98</name> - <version>0</version> - <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state> - </option> - <option> - <name>CompilerMisraRules04</name> - <version>0</version> - <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state> - </option> - <option> <name>CCPosIndRopi</name> <state>0</state> </option> @@ -486,7 +466,7 @@ <name>AARM</name> <archiveVersion>2</archiveVersion> <data> - <version>10</version> + <version>11</version> <wantNonLocal>1</wantNonLocal> <debug>1</debug> <option> @@ -643,6 +623,10 @@ <name>AsmNoLiteralPool</name> <state>0</state> </option> + <option> + <name>PreInclude</name> + <state></state> + </option> </data> </settings> <settings> @@ -682,14 +666,10 @@ <extensions></extensions> <cmdline></cmdline> <hasPrio>0</hasPrio> + <buildSequence>inputOutputBased</buildSequence> </data> </settings> <settings> - <name>BICOMP</name> - <archiveVersion>0</archiveVersion> - <data /> - </settings> - <settings> <name>BUILDACTION</name> <archiveVersion>1</archiveVersion> <data> @@ -701,7 +681,7 @@ <name>ILINK</name> <archiveVersion>0</archiveVersion> <data> - <version>23</version> + <version>26</version> <wantNonLocal>1</wantNonLocal> <debug>1</debug> <option> @@ -709,10 +689,6 @@ <state>1</state> </option> <option> - <name>XLinkMisraHandler</name> - <state>0</state> - </option> - <option> <name>IlinkInputFileSlave</name> <state>0</state> </option> @@ -1037,6 +1013,34 @@ <name>IlinkRawBinaryAlign2</name> <state></state> </option> + <option> + <name>IlinkLogCrtRoutineSelection</name> + <state>0</state> + </option> + <option> + <name>IlinkLogFragmentInfo</name> + <state>0</state> + </option> + <option> + <name>IlinkLogInlining</name> + <state>0</state> + </option> + <option> + <name>IlinkLogMerging</name> + <state>0</state> + </option> + <option> + <name>IlinkDemangle</name> + <state>0</state> + </option> + <option> + <name>IlinkWrapperFileEnable</name> + <state>0</state> + </option> + <option> + <name>IlinkWrapperFile</name> + <state></state> + </option> </data> </settings> <settings> @@ -1060,11 +1064,6 @@ </option> </data> </settings> - <settings> - <name>BILINK</name> - <archiveVersion>0</archiveVersion> - <data /> - </settings> </configuration> <group> <name>Config</name> @@ -1074,6 +1073,12 @@ </group> <group> <name>Demo</name> + <group> + <name>IAR</name> + <file> + <name>$PROJ_DIR$\..\..\Demo\IAR\reg_tests_asm.s</name> + </file> + </group> <file> <name>$PROJ_DIR$\..\..\Demo\app_main.c</name> </file> @@ -1086,6 +1091,12 @@ <file> <name>$PROJ_DIR$\..\..\Demo\mpu_demo.h</name> </file> + <file> + <name>$PROJ_DIR$\..\..\Demo\reg_tests.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\Demo\reg_tests.h</name> + </file> </group> <group> <name>FreeRTOS</name> diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil/FreeRTOSDemo.uvoptx b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil/FreeRTOSDemo.uvoptx index c6e38d3ca..fce0ba11e 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil/FreeRTOSDemo.uvoptx +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil/FreeRTOSDemo.uvoptx @@ -10,7 +10,7 @@ <aExt>*.s*; *.src; *.a*</aExt> <oExt>*.obj; *.o</oExt> <lExt>*.lib</lExt> - <tExt>*.txt; *.h; *.inc</tExt> + <tExt>*.txt; *.h; *.inc; *.md</tExt> <pExt>*.plm</pExt> <CppX>*.cpp</CppX> <nMigrate>0</nMigrate> @@ -103,7 +103,7 @@ <bEvRecOn>1</bEvRecOn> <bSchkAxf>0</bSchkAxf> <bTchkAxf>0</bTchkAxf> - <nTsel>5</nTsel> + <nTsel>6</nTsel> <sDll></sDll> <sDllPa></sDllPa> <sDlgDll></sDlgDll> @@ -275,6 +275,42 @@ <RteFlg>0</RteFlg> <bShared>0</bShared> </File> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>6</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\Demo\GCC\reg_tests_asm.c</PathWithFileName> + <FilenameWithoutPath>reg_tests_asm.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>7</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\Demo\reg_tests.c</PathWithFileName> + <FilenameWithoutPath>reg_tests.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>8</FileNumber> + <FileType>5</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\Demo\reg_tests.h</PathWithFileName> + <FilenameWithoutPath>reg_tests.h</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> </Group> <Group> @@ -285,7 +321,7 @@ <RteFlg>0</RteFlg> <File> <GroupNumber>3</GroupNumber> - <FileNumber>6</FileNumber> + <FileNumber>9</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -297,7 +333,7 @@ </File> <File> <GroupNumber>3</GroupNumber> - <FileNumber>7</FileNumber> + <FileNumber>10</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -309,7 +345,7 @@ </File> <File> <GroupNumber>3</GroupNumber> - <FileNumber>8</FileNumber> + <FileNumber>11</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -321,7 +357,7 @@ </File> <File> <GroupNumber>3</GroupNumber> - <FileNumber>9</FileNumber> + <FileNumber>12</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -333,7 +369,7 @@ </File> <File> <GroupNumber>3</GroupNumber> - <FileNumber>10</FileNumber> + <FileNumber>13</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -345,7 +381,7 @@ </File> <File> <GroupNumber>3</GroupNumber> - <FileNumber>11</FileNumber> + <FileNumber>14</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -357,7 +393,7 @@ </File> <File> <GroupNumber>3</GroupNumber> - <FileNumber>12</FileNumber> + <FileNumber>15</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -369,7 +405,7 @@ </File> <File> <GroupNumber>3</GroupNumber> - <FileNumber>13</FileNumber> + <FileNumber>16</FileNumber> <FileType>5</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -381,7 +417,7 @@ </File> <File> <GroupNumber>3</GroupNumber> - <FileNumber>14</FileNumber> + <FileNumber>17</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -393,7 +429,7 @@ </File> <File> <GroupNumber>3</GroupNumber> - <FileNumber>15</FileNumber> + <FileNumber>18</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -413,7 +449,7 @@ <RteFlg>0</RteFlg> <File> <GroupNumber>4</GroupNumber> - <FileNumber>16</FileNumber> + <FileNumber>19</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -425,7 +461,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>17</FileNumber> + <FileNumber>20</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -437,7 +473,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>18</FileNumber> + <FileNumber>21</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -449,7 +485,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>19</FileNumber> + <FileNumber>22</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -461,7 +497,7 @@ </File> <File> <GroupNumber>4</GroupNumber> - <FileNumber>20</FileNumber> + <FileNumber>23</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -481,7 +517,7 @@ <RteFlg>0</RteFlg> <File> <GroupNumber>5</GroupNumber> - <FileNumber>21</FileNumber> + <FileNumber>24</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -493,7 +529,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>22</FileNumber> + <FileNumber>25</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -505,7 +541,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>23</FileNumber> + <FileNumber>26</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -517,7 +553,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>24</FileNumber> + <FileNumber>27</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -529,7 +565,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>25</FileNumber> + <FileNumber>28</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -541,7 +577,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>26</FileNumber> + <FileNumber>29</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -553,7 +589,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>27</FileNumber> + <FileNumber>30</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -565,7 +601,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>28</FileNumber> + <FileNumber>31</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -577,7 +613,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>29</FileNumber> + <FileNumber>32</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -589,7 +625,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>30</FileNumber> + <FileNumber>33</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -601,7 +637,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>31</FileNumber> + <FileNumber>34</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -613,7 +649,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>32</FileNumber> + <FileNumber>35</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -625,7 +661,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>33</FileNumber> + <FileNumber>36</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -637,7 +673,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>34</FileNumber> + <FileNumber>37</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -649,7 +685,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>35</FileNumber> + <FileNumber>38</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -661,7 +697,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>36</FileNumber> + <FileNumber>39</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -673,7 +709,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>37</FileNumber> + <FileNumber>40</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -685,7 +721,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>38</FileNumber> + <FileNumber>41</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -697,7 +733,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>39</FileNumber> + <FileNumber>42</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -709,7 +745,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>40</FileNumber> + <FileNumber>43</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -721,7 +757,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>41</FileNumber> + <FileNumber>44</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -733,7 +769,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>42</FileNumber> + <FileNumber>45</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -745,7 +781,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>43</FileNumber> + <FileNumber>46</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -757,7 +793,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>44</FileNumber> + <FileNumber>47</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -769,7 +805,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>45</FileNumber> + <FileNumber>48</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -781,7 +817,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>46</FileNumber> + <FileNumber>49</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -793,7 +829,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>47</FileNumber> + <FileNumber>50</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -805,7 +841,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>48</FileNumber> + <FileNumber>51</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -817,7 +853,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>49</FileNumber> + <FileNumber>52</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -829,7 +865,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>50</FileNumber> + <FileNumber>53</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -841,7 +877,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>51</FileNumber> + <FileNumber>54</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -853,7 +889,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>52</FileNumber> + <FileNumber>55</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -865,7 +901,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>53</FileNumber> + <FileNumber>56</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -877,7 +913,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>54</FileNumber> + <FileNumber>57</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -889,7 +925,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>55</FileNumber> + <FileNumber>58</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -901,7 +937,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>56</FileNumber> + <FileNumber>59</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -913,7 +949,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>57</FileNumber> + <FileNumber>60</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -925,7 +961,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>58</FileNumber> + <FileNumber>61</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -937,7 +973,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>59</FileNumber> + <FileNumber>62</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -949,7 +985,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>60</FileNumber> + <FileNumber>63</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -961,7 +997,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>61</FileNumber> + <FileNumber>64</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -973,7 +1009,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>62</FileNumber> + <FileNumber>65</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -985,7 +1021,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>63</FileNumber> + <FileNumber>66</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -997,7 +1033,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>64</FileNumber> + <FileNumber>67</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1009,7 +1045,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>65</FileNumber> + <FileNumber>68</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1021,7 +1057,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>66</FileNumber> + <FileNumber>69</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1033,7 +1069,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>67</FileNumber> + <FileNumber>70</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1045,7 +1081,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>68</FileNumber> + <FileNumber>71</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1057,7 +1093,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>69</FileNumber> + <FileNumber>72</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1069,7 +1105,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>70</FileNumber> + <FileNumber>73</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1081,7 +1117,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>71</FileNumber> + <FileNumber>74</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1093,7 +1129,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>72</FileNumber> + <FileNumber>75</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1105,7 +1141,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>73</FileNumber> + <FileNumber>76</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1117,7 +1153,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>74</FileNumber> + <FileNumber>77</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1129,7 +1165,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>75</FileNumber> + <FileNumber>78</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1141,7 +1177,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>76</FileNumber> + <FileNumber>79</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1153,7 +1189,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>77</FileNumber> + <FileNumber>80</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1165,7 +1201,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>78</FileNumber> + <FileNumber>81</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1177,7 +1213,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>79</FileNumber> + <FileNumber>82</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1189,7 +1225,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>80</FileNumber> + <FileNumber>83</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1201,7 +1237,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>81</FileNumber> + <FileNumber>84</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1213,7 +1249,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>82</FileNumber> + <FileNumber>85</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1225,7 +1261,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>83</FileNumber> + <FileNumber>86</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1237,7 +1273,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>84</FileNumber> + <FileNumber>87</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1249,7 +1285,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>85</FileNumber> + <FileNumber>88</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1261,7 +1297,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>86</FileNumber> + <FileNumber>89</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1273,7 +1309,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>87</FileNumber> + <FileNumber>90</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1285,7 +1321,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>88</FileNumber> + <FileNumber>91</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1297,7 +1333,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>89</FileNumber> + <FileNumber>92</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1309,7 +1345,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>90</FileNumber> + <FileNumber>93</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1321,7 +1357,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>91</FileNumber> + <FileNumber>94</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1333,7 +1369,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>92</FileNumber> + <FileNumber>95</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1345,7 +1381,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>93</FileNumber> + <FileNumber>96</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1357,7 +1393,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>94</FileNumber> + <FileNumber>97</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1369,7 +1405,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>95</FileNumber> + <FileNumber>98</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1381,7 +1417,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>96</FileNumber> + <FileNumber>99</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1393,7 +1429,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>97</FileNumber> + <FileNumber>100</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1405,7 +1441,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>98</FileNumber> + <FileNumber>101</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1417,7 +1453,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>99</FileNumber> + <FileNumber>102</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1429,7 +1465,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>100</FileNumber> + <FileNumber>103</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1441,7 +1477,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>101</FileNumber> + <FileNumber>104</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1453,7 +1489,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>102</FileNumber> + <FileNumber>105</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1465,7 +1501,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>103</FileNumber> + <FileNumber>106</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1477,7 +1513,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>104</FileNumber> + <FileNumber>107</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1489,7 +1525,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>105</FileNumber> + <FileNumber>108</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1501,7 +1537,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>106</FileNumber> + <FileNumber>109</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1513,7 +1549,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>107</FileNumber> + <FileNumber>110</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1525,7 +1561,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>108</FileNumber> + <FileNumber>111</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1537,7 +1573,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>109</FileNumber> + <FileNumber>112</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1549,7 +1585,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>110</FileNumber> + <FileNumber>113</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1561,7 +1597,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>111</FileNumber> + <FileNumber>114</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1573,7 +1609,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>112</FileNumber> + <FileNumber>115</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1585,7 +1621,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>113</FileNumber> + <FileNumber>116</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1597,7 +1633,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>114</FileNumber> + <FileNumber>117</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1609,7 +1645,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>115</FileNumber> + <FileNumber>118</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1621,7 +1657,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>116</FileNumber> + <FileNumber>119</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1633,7 +1669,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>117</FileNumber> + <FileNumber>120</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1645,7 +1681,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>118</FileNumber> + <FileNumber>121</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1657,7 +1693,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>119</FileNumber> + <FileNumber>122</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1669,7 +1705,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>120</FileNumber> + <FileNumber>123</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1681,7 +1717,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>121</FileNumber> + <FileNumber>124</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1693,7 +1729,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>122</FileNumber> + <FileNumber>125</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1705,7 +1741,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>123</FileNumber> + <FileNumber>126</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1717,7 +1753,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>124</FileNumber> + <FileNumber>127</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1729,7 +1765,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>125</FileNumber> + <FileNumber>128</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1741,7 +1777,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>126</FileNumber> + <FileNumber>129</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1753,7 +1789,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>127</FileNumber> + <FileNumber>130</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1765,7 +1801,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>128</FileNumber> + <FileNumber>131</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1777,7 +1813,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>129</FileNumber> + <FileNumber>132</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1789,7 +1825,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>130</FileNumber> + <FileNumber>133</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1801,7 +1837,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>131</FileNumber> + <FileNumber>134</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1813,7 +1849,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>132</FileNumber> + <FileNumber>135</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1825,7 +1861,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>133</FileNumber> + <FileNumber>136</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1837,7 +1873,7 @@ </File> <File> <GroupNumber>5</GroupNumber> - <FileNumber>134</FileNumber> + <FileNumber>137</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1857,7 +1893,7 @@ <RteFlg>0</RteFlg> <File> <GroupNumber>6</GroupNumber> - <FileNumber>135</FileNumber> + <FileNumber>138</FileNumber> <FileType>1</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> @@ -1869,7 +1905,7 @@ </File> <File> <GroupNumber>6</GroupNumber> - <FileNumber>136</FileNumber> + <FileNumber>139</FileNumber> <FileType>2</FileType> <tvExp>0</tvExp> <tvExpOptDlg>0</tvExpOptDlg> diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil/FreeRTOSDemo.uvprojx b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil/FreeRTOSDemo.uvprojx index d3c763b3d..ab02655a8 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil/FreeRTOSDemo.uvprojx +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil/FreeRTOSDemo.uvprojx @@ -10,14 +10,14 @@ <TargetName>FreeRTOSDemo</TargetName> <ToolsetNumber>0x4</ToolsetNumber> <ToolsetName>ARM-ADS</ToolsetName> - <pCCUsed>6130001::V6.13.1::.\ARMCLANG</pCCUsed> + <pCCUsed>6180000::V6.18::ARMCLANG</pCCUsed> <uAC6>1</uAC6> <TargetOption> <TargetCommonOption> <Device>STM32H743ZITx</Device> <Vendor>STMicroelectronics</Vendor> - <PackID>Keil.STM32H7xx_DFP.2.4.0</PackID> - <PackURL>https://www.keil.com/pack/</PackURL> + <PackID>Keil.STM32H7xx_DFP.3.0.0</PackID> + <PackURL>http://www.keil.com/pack/</PackURL> <Cpu>IRAM(0x20000000-0x2001FFFF) IRAM2(0x24000000-0x2407FFFF) IROM(0x8000000-0x81FFFFF) CLOCK(12000000) FPU3(DFPU) CPUTYPE("Cortex-M7") ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> <StartupFile></StartupFile> @@ -185,6 +185,8 @@ <uocXRam>0</uocXRam> <RvdsVP>3</RvdsVP> <RvdsMve>0</RvdsMve> + <RvdsCdeCp>0</RvdsCdeCp> + <nBranchProt>0</nBranchProt> <hadIRAM2>1</hadIRAM2> <hadIROM2>0</hadIROM2> <StupSel>8</StupSel> @@ -351,7 +353,7 @@ <NoWarn>0</NoWarn> <uSurpInc>0</uSurpInc> <useXO>0</useXO> - <uClangAs>0</uClangAs> + <ClangAsOpt>4</ClangAsOpt> <VariousControls> <MiscControls></MiscControls> <Define></Define> @@ -412,6 +414,21 @@ <FileType>5</FileType> <FilePath>..\..\Demo\mpu_demo.h</FilePath> </File> + <File> + <FileName>reg_tests_asm.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\Demo\GCC\reg_tests_asm.c</FilePath> + </File> + <File> + <FileName>reg_tests.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\Demo\reg_tests.c</FilePath> + </File> + <File> + <FileName>reg_tests.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\Demo\reg_tests.h</FilePath> + </File> </Files> </Group> <Group> diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/FreeRTOSDemo.sct b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/FreeRTOSDemo.sct new file mode 100644 index 000000000..333a44cc2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/FreeRTOSDemo.sct @@ -0,0 +1,45 @@ +; Flash Layout +; +; --------------------- +; | Privileged Code | +; --------------------- +; | Unprivileged Code | +; --------------------- +; +; RAM Layout +; +; --------------------- +; | Privileged Data | +; --------------------- +; | Unprivileged Data | +; --------------------- + +LR_APP 0x08000000 0x00200000 ; load region size_region +{ + ER_IROM_PRIVILEGED 0x08000000 + { + *.o (RESET, +First) + *(InRoot$$Sections) + *(privileged_functions) + } + + ER_IROM_FREERTOS_SYSTEM_CALLS 0x08008000 FIXED + { + *(freertos_system_calls) + } + + ER_IROM_UNPRIVILEGED +0 + { + .ANY (+RO) + } + + RW_IRAM_PRIVILEGED 0x20000000 + { + *(privileged_data) + } + + RW_IRAM_UNPRIVILEGED 0x20008000 + { + .ANY (+RW +ZI) + } +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/FreeRTOSDemo.uvoptx b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/FreeRTOSDemo.uvoptx new file mode 100644 index 000000000..5d0b06c3e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/FreeRTOSDemo.uvoptx @@ -0,0 +1,1928 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd"> + + <SchemaVersion>1.0</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <Extensions> + <cExt>*.c</cExt> + <aExt>*.s*; *.src; *.a*</aExt> + <oExt>*.obj; *.o</oExt> + <lExt>*.lib</lExt> + <tExt>*.txt; *.h; *.inc; *.md</tExt> + <pExt>*.plm</pExt> + <CppX>*.cpp</CppX> + <nMigrate>0</nMigrate> + </Extensions> + + <DaveTm> + <dwLowDateTime>0</dwLowDateTime> + <dwHighDateTime>0</dwHighDateTime> + </DaveTm> + + <Target> + <TargetName>FreeRTOSDemo</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>64000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>0</RunSim> + <RunTarget>1</RunTarget> + <RunAbUc>0</RunAbUc> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\Listings\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>1</IsCurrentTarget> + </OPTFL> + <CpuCode>18</CpuCode> + <DebugOpt> + <uSim>0</uSim> + <uTrg>1</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>1</tLdApp> + <tGomain>1</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>1</tRfunc> + <tRbox>1</tRbox> + <tRtrace>1</tRtrace> + <sRSysVw>1</sRSysVw> + <tRSysVw>1</tRSysVw> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <bEvRecOn>1</bEvRecOn> + <bSchkAxf>0</bSchkAxf> + <bTchkAxf>0</bTchkAxf> + <nTsel>6</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile></sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile></tIfile> + <pMon>STLink\ST-LINKIII-KEIL_SWO.dll</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMRTXEVENTFLAGS</Key> + <Name>-L70 -Z18 -C0 -M0 -T1</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGTARM</Key> + <Name>(1010=1611,104,2061,661,0)(6017=1641,137,1830,473,0)(1008=-1,-1,-1,-1,0)(6016=-1,-1,-1,-1,0)(1012=1671,169,2148,484,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMDBGFLAGS</Key> + <Name></Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGUARM</Key> + <Name>(105=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2CM3</Key> + <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC8000 -FN1 -FF0STM32H7x_2048 -FS08000000 -FL0200000 -FP0($$Device:STM32H743ZITx$CMSIS\Flash\STM32H7x_2048.FLM))</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>ST-LINKIII-KEIL_SWO</Key> + <Name>-U-O142 -O2254 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(6BA02477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32H7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H743ZITx$CMSIS\Flash\STM32H7x_2048.FLM)</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>1</periodic> + <aLwin>1</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>1</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>0</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>0</aSer4> + <StkLoc>0</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>0</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + <bLintAuto>0</bLintAuto> + <bAutoGenD>0</bAutoGenD> + <LntExFlags>0</LntExFlags> + <pMisraName></pMisraName> + <pszMrule></pszMrule> + <pSingCmds></pSingCmds> + <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> + <DebugDescription> + <Enable>1</Enable> + <EnableFlashSeq>0</EnableFlashSeq> + <EnableLog>0</EnableLog> + <Protocol>2</Protocol> + <DbgClock>10000000</DbgClock> + </DebugDescription> + </TargetOption> + </Target> + + <Group> + <GroupName>Config</GroupName> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>0</RteFlg> + <File> + <GroupNumber>1</GroupNumber> + <FileNumber>1</FileNumber> + <FileType>5</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\Config\FreeRTOSConfig.h</PathWithFileName> + <FilenameWithoutPath>FreeRTOSConfig.h</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + </Group> + + <Group> + <GroupName>Demo</GroupName> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>0</RteFlg> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>2</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\Demo\app_main.c</PathWithFileName> + <FilenameWithoutPath>app_main.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>3</FileNumber> + <FileType>5</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\Demo\app_main.h</PathWithFileName> + <FilenameWithoutPath>app_main.h</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>4</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\Demo\mpu_demo.c</PathWithFileName> + <FilenameWithoutPath>mpu_demo.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>5</FileNumber> + <FileType>5</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\Demo\mpu_demo.h</PathWithFileName> + <FilenameWithoutPath>mpu_demo.h</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>6</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\Demo\reg_tests.c</PathWithFileName> + <FilenameWithoutPath>reg_tests.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>7</FileNumber> + <FileType>5</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\Demo\reg_tests.h</PathWithFileName> + <FilenameWithoutPath>reg_tests.h</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>8</FileNumber> + <FileType>2</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\Demo\RVDS\reg_tests_asm.s</PathWithFileName> + <FilenameWithoutPath>reg_tests_asm.s</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + </Group> + + <Group> + <GroupName>FreeRTOS</GroupName> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + 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<SchemaVersion>2.1</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <Targets> + <Target> + <TargetName>FreeRTOSDemo</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <pCCUsed>5060960::V5.06 update 7 (build 960)::.\ARM_Compiler_5.06u7</pCCUsed> + <uAC6>0</uAC6> + <TargetOption> + <TargetCommonOption> + <Device>STM32H743ZITx</Device> + <Vendor>STMicroelectronics</Vendor> + <PackID>Keil.STM32H7xx_DFP.3.0.0</PackID> + <PackURL>http://www.keil.com/pack/</PackURL> + <Cpu>IRAM(0x20000000-0x2001FFFF) IRAM2(0x24000000-0x2407FFFF) IROM(0x8000000-0x81FFFFF) CLOCK(12000000) FPU3(DFPU) CPUTYPE("Cortex-M7") ELITTLE</Cpu> + <FlashUtilSpec></FlashUtilSpec> + <StartupFile></StartupFile> + <FlashDriverDll></FlashDriverDll> + <DeviceId></DeviceId> + <RegisterFile></RegisterFile> + <MemoryEnv></MemoryEnv> + <Cmp></Cmp> + <Asm></Asm> + <Linker></Linker> + <OHString></OHString> + <InfinionOptionDll></InfinionOptionDll> + <SLE66CMisc></SLE66CMisc> + <SLE66AMisc></SLE66AMisc> + <SLE66LinkerMisc></SLE66LinkerMisc> + <SFDFile>$$Device:STM32H743ZITx$CMSIS\SVD\STM32H743.svd</SFDFile> + <bCustSvd>0</bCustSvd> + <UseEnv>0</UseEnv> + <BinPath></BinPath> + <IncludePath></IncludePath> + <LibPath></LibPath> + <RegisterFilePath></RegisterFilePath> + <DBRegisterFilePath></DBRegisterFilePath> + <TargetStatus> + <Error>0</Error> + <ExitCodeStop>0</ExitCodeStop> + <ButtonStop>0</ButtonStop> + <NotGenerated>0</NotGenerated> + <InvalidFlash>1</InvalidFlash> + </TargetStatus> + <OutputDirectory>.\Debug\</OutputDirectory> + <OutputName>FreeRTOSDemo</OutputName> + <CreateExecutable>1</CreateExecutable> + <CreateLib>0</CreateLib> + <CreateHexFile>1</CreateHexFile> + <DebugInformation>1</DebugInformation> + <BrowseInformation>1</BrowseInformation> + <ListingPath>.\Listings\</ListingPath> + <HexFormatSelection>1</HexFormatSelection> + <Merge32K>0</Merge32K> + <CreateBatchFile>0</CreateBatchFile> + <BeforeCompile> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopU1X>0</nStopU1X> + <nStopU2X>0</nStopU2X> + </BeforeCompile> + <BeforeMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopB1X>0</nStopB1X> + <nStopB2X>0</nStopB2X> + </BeforeMake> + <AfterMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopA1X>0</nStopA1X> + <nStopA2X>0</nStopA2X> + </AfterMake> + <SelectedForBatchBuild>0</SelectedForBatchBuild> + <SVCSIdString></SVCSIdString> + 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</IROM> + <XRAM> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </XRAM> + <OCR_RVCT1> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT1> + <OCR_RVCT2> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT2> + <OCR_RVCT3> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT3> + <OCR_RVCT4> + <Type>1</Type> + <StartAddress>0x8000000</StartAddress> + <Size>0x200000</Size> + </OCR_RVCT4> + <OCR_RVCT5> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT5> + <OCR_RVCT6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT6> + <OCR_RVCT7> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT7> + <OCR_RVCT8> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT8> + <OCR_RVCT9> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x20000</Size> + </OCR_RVCT9> + <OCR_RVCT10> + <Type>0</Type> + <StartAddress>0x24000000</StartAddress> + <Size>0x80000</Size> + </OCR_RVCT10> + </OnChipMemories> + <RvctStartVector></RvctStartVector> + </ArmAdsMisc> + <Cads> + <interw>1</interw> + <Optim>4</Optim> + <oTime>0</oTime> + <SplitLS>0</SplitLS> + <OneElfS>1</OneElfS> + <Strict>0</Strict> + <EnumInt>0</EnumInt> + <PlainCh>0</PlainCh> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <wLevel>2</wLevel> + <uThumb>0</uThumb> + <uSurpInc>0</uSurpInc> + <uC99>1</uC99> + <uGnu>0</uGnu> + <useXO>0</useXO> + <v6Lang>3</v6Lang> + <v6LangP>3</v6LangP> + <vShortEn>1</vShortEn> + <vShortWch>1</vShortWch> + <v6Lto>0</v6Lto> + <v6WtE>0</v6WtE> + <v6Rtti>0</v6Rtti> + <VariousControls> + <MiscControls></MiscControls> + <Define>USE_HAL_DRIVER,STM32H743xx</Define> + <Undefine></Undefine> + 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<FileName>stm32h7xx_ll_swpmi.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\ST_Code\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_swpmi.c</FilePath> + </File> + <File> + <FileName>stm32h7xx_ll_tim.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\ST_Code\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_tim.c</FilePath> + </File> + <File> + <FileName>stm32h7xx_ll_usart.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\ST_Code\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_usart.c</FilePath> + </File> + <File> + <FileName>stm32h7xx_ll_usb.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\ST_Code\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_usb.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>Startup</GroupName> + <Files> + <File> + <FileName>memfault_handler.c</FileName> + <FileType>1</FileType> + <FilePath>.\memfault_handler.c</FilePath> + </File> + <File> + <FileName>startup_stm32h743xx.s</FileName> + <FileType>2</FileType> + <FilePath>.\startup_stm32h743xx.s</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>::CMSIS</GroupName> + </Group> + </Groups> + </Target> + </Targets> + + <RTE> + <apis/> + <components> + <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.6.0" condition="ARMv6_7_8-M Device"> + <package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/> + <targetInfos> + <targetInfo name="FreeRTOSDemo"/> + </targetInfos> + </component> + </components> + <files/> + </RTE> + +</Project> diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/memfault_handler.c b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/memfault_handler.c new file mode 100644 index 000000000..6c14c6ff0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/memfault_handler.c @@ -0,0 +1,66 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include <stdint.h> + +extern uint32_t Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Base; +extern uint32_t Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Limit; + +/* Memory map needed for MPU setup. Must must match the one defined in + * the scatter-loading file (FreeRTOSDemo.sct). */ +const uint32_t * __FLASH_segment_start__ = ( uint32_t * ) 0x08000000; +const uint32_t * __FLASH_segment_end__ = ( uint32_t * ) 0x08200000; +const uint32_t * __SRAM_segment_start__ = ( uint32_t * ) 0x20000000; +const uint32_t * __SRAM_segment_end__ = ( uint32_t * ) 0x20020000; + +const uint32_t * __privileged_functions_start__ = ( uint32_t * ) 0x08000000; +const uint32_t * __privileged_functions_end__ = ( uint32_t * ) 0x08008000; +const uint32_t * __privileged_data_start__ = ( uint32_t * ) 0x20000000; +const uint32_t * __privileged_data_end__ = ( uint32_t * ) 0x20008000; + +const uint32_t * __syscalls_flash_start__ = ( uint32_t * ) &( Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Base ); +const uint32_t * __syscalls_flash_end__ = ( uint32_t * ) &( Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Limit ); +/*-----------------------------------------------------------*/ + +/** + * @brief Mem fault handler. + */ +void MemManage_Handler( void ); +/*-----------------------------------------------------------*/ + +__asm void MemManage_Handler( void ) +{ + extern vHandleMemoryFault; + + PRESERVE8 + + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vHandleMemoryFault +} +/*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/startup_stm32h743xx.s b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/startup_stm32h743xx.s new file mode 100644 index 000000000..266479eef --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/startup_stm32h743xx.s @@ -0,0 +1,611 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32h743xx.s +;* @author MCD Application Team +;* Description : STM32H7xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2017 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out + DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts + DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt + DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt + DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt + DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt + DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt + DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD SAI3_IRQHandler ; SAI3 global Interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD JPEG_IRQHandler ; JPEG global Interrupt + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_AVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT FDCAN1_IT0_IRQHandler [WEAK] + EXPORT FDCAN2_IT0_IRQHandler [WEAK] + EXPORT FDCAN1_IT1_IRQHandler [WEAK] + EXPORT FDCAN2_IT1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT FDCAN_CAL_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMAMUX1_OVR_IRQHandler [WEAK] + EXPORT HRTIM1_Master_IRQHandler [WEAK] + EXPORT HRTIM1_TIMA_IRQHandler [WEAK] + EXPORT HRTIM1_TIMB_IRQHandler [WEAK] + EXPORT HRTIM1_TIMC_IRQHandler [WEAK] + EXPORT HRTIM1_TIMD_IRQHandler [WEAK] + EXPORT HRTIM1_TIME_IRQHandler [WEAK] + EXPORT HRTIM1_FLT_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT SAI3_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT MDIOS_WKUP_IRQHandler [WEAK] + EXPORT MDIOS_IRQHandler [WEAK] + EXPORT JPEG_IRQHandler [WEAK] + EXPORT MDMA_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT HSEM1_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT DMAMUX2_OVR_IRQHandler [WEAK] + EXPORT BDMA_Channel0_IRQHandler [WEAK] + EXPORT BDMA_Channel1_IRQHandler [WEAK] + EXPORT BDMA_Channel2_IRQHandler [WEAK] + EXPORT BDMA_Channel3_IRQHandler [WEAK] + EXPORT BDMA_Channel4_IRQHandler [WEAK] + EXPORT BDMA_Channel5_IRQHandler [WEAK] + EXPORT BDMA_Channel6_IRQHandler [WEAK] + EXPORT BDMA_Channel7_IRQHandler [WEAK] + EXPORT COMP1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT LPTIM3_IRQHandler [WEAK] + EXPORT LPTIM4_IRQHandler [WEAK] + EXPORT LPTIM5_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT ECC_IRQHandler [WEAK] + EXPORT SAI4_IRQHandler [WEAK] + EXPORT WAKEUP_PIN_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_AVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +FDCAN1_IT0_IRQHandler +FDCAN2_IT0_IRQHandler +FDCAN1_IT1_IRQHandler +FDCAN2_IT1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +FDCAN_CAL_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +SAI2_IRQHandler +QUADSPI_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler +OTG_FS_EP1_OUT_IRQHandler +OTG_FS_EP1_IN_IRQHandler +OTG_FS_WKUP_IRQHandler +OTG_FS_IRQHandler +DMAMUX1_OVR_IRQHandler +HRTIM1_Master_IRQHandler +HRTIM1_TIMA_IRQHandler +HRTIM1_TIMB_IRQHandler +HRTIM1_TIMC_IRQHandler +HRTIM1_TIMD_IRQHandler +HRTIM1_TIME_IRQHandler +HRTIM1_FLT_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +DFSDM1_FLT3_IRQHandler +SAI3_IRQHandler +SWPMI1_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +MDIOS_WKUP_IRQHandler +MDIOS_IRQHandler +JPEG_IRQHandler +MDMA_IRQHandler +SDMMC2_IRQHandler +HSEM1_IRQHandler +ADC3_IRQHandler +DMAMUX2_OVR_IRQHandler +BDMA_Channel0_IRQHandler +BDMA_Channel1_IRQHandler +BDMA_Channel2_IRQHandler +BDMA_Channel3_IRQHandler +BDMA_Channel4_IRQHandler +BDMA_Channel5_IRQHandler +BDMA_Channel6_IRQHandler +BDMA_Channel7_IRQHandler +COMP1_IRQHandler +LPTIM2_IRQHandler +LPTIM3_IRQHandler +LPTIM4_IRQHandler +LPTIM5_IRQHandler +LPUART1_IRQHandler +CRS_IRQHandler +ECC_IRQHandler +SAI4_IRQHandler +WAKEUP_PIN_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/lexicon.txt b/lexicon.txt index f3574d543..fe87f51d0 100644 --- a/lexicon.txt +++ b/lexicon.txt @@ -64,6 +64,7 @@ ascii asf asm asn +aspr ast async atmega @@ -818,6 +819,7 @@ fpga fpidiv fprintf fpu +fpscr fr framming france @@ -1235,6 +1237,7 @@ lsb lserialputstring lsize lsl +lsls lsr lstringlength ltd @@ -3130,6 +3133,7 @@ vbuttonisrhandler vcellularconnecttask vcellulardemotask vclearemactxbuffer +vcmp vconfiguretimerforruntimestats vcore vcreatesuicidaltask @@ -3183,6 +3187,7 @@ vmaindeleteme vmainpoststopprocessing vmemchecktask vmov +vmrs vodafone votademotask vpartestinitialise |