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-rw-r--r--sim/testsuite/sim/fr30/div0s.cgs64
1 files changed, 0 insertions, 64 deletions
diff --git a/sim/testsuite/sim/fr30/div0s.cgs b/sim/testsuite/sim/fr30/div0s.cgs
deleted file mode 100644
index 84d76c4bfb9..00000000000
--- a/sim/testsuite/sim/fr30/div0s.cgs
+++ /dev/null
@@ -1,64 +0,0 @@
-# fr30 testcase for div0s $Ri
-# mach(): fr30
-
- .include "testutils.inc"
-
- START
-
- .text
- .global div0s
-div0s:
- ; Test div0s $Rj,$Ri
- ; example from the manual - negative dividend
- mvi_h_gr 0x0fffffff,r2
- mvi_h_dr 0x00000000,mdh
- mvi_h_dr 0xfffffff0,mdl
- set_dbits 0x0 ; Set opposite of expected
- set_cc 0x0f ; Condition codes should not change
- div0s r2
- test_cc 1 1 1 1
- test_h_gr 0x0fffffff,r2
- test_h_dr 0xffffffff,mdh
- test_h_dr 0xfffffff0,mdl
- test_dbits 0x3
-
- ; negative divisor
- mvi_h_gr 0xffffffff,r2
- mvi_h_dr 0xffffffff,mdh
- mvi_h_dr 0x7fffffff,mdl
- set_dbits 0x1 ; Set opposite of expected
- set_cc 0x0f ; Condition codes should not change
- div0s r2
- test_cc 1 1 1 1
- test_h_gr 0xffffffff,r2
- test_h_dr 0x00000000,mdh
- test_h_dr 0x7fffffff,mdl
- test_dbits 0x2
-
- ; Both sign bits 0
- mvi_h_gr 0x0fffffff,r2
- mvi_h_dr 0xffffffff,mdh
- mvi_h_dr 0x7ffffff0,mdl
- set_dbits 0x3 ; Set opposite of expected
- set_cc 0x0f ; Condition codes should not change
- div0s r2
- test_cc 1 1 1 1
- test_h_gr 0x0fffffff,r2
- test_h_dr 0x00000000,mdh
- test_h_dr 0x7ffffff0,mdl
- test_dbits 0x0
-
- ; Both sign bits 1
- mvi_h_gr 0xffffffff,r2
- mvi_h_dr 0x00000000,mdh
- mvi_h_dr 0xffffffff,mdl
- set_dbits 0x2 ; Set opposite of expected
- set_cc 0x0f ; Condition codes should not change
- div0s r2
- test_cc 1 1 1 1
- test_h_gr 0xffffffff,r2
- test_h_dr 0xffffffff,mdh
- test_h_dr 0xffffffff,mdl
- test_dbits 0x1
-
- pass