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| author | Shea Levy <shea@shealevy.com> | 2018-02-25 20:34:39 -0500 |
|---|---|---|
| committer | Mark H Weaver <mhw@netris.org> | 2018-03-15 23:17:23 -0400 |
| commit | d6e669b8cb26f870ea6611a54788b75fbad67bbe (patch) | |
| tree | 1f1f9a2f181ef62eef299ccb69531939960af029 | |
| parent | 72d80a1ea39455fb0e2b005be53bd83f7ce61f16 (diff) | |
| download | guile-stable-2.0.tar.gz | |
Recognize RISC-V compilation targets.stable-2.0
* module/system/base/target.scm (cpu-endianness): Add case for "riscv" variants.
Signed-off-by: Shea Levy <shea@shealevy.com>
Signed-off-by: Mark H Weaver <mhw@netris.org>
| -rw-r--r-- | module/system/base/target.scm | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/module/system/base/target.scm b/module/system/base/target.scm index fbead44aa..105c581b5 100644 --- a/module/system/base/target.scm +++ b/module/system/base/target.scm @@ -80,6 +80,8 @@ (endianness big)) ((string=? "aarch64" cpu) (endianness little)) + ((string-match "riscv[1-9][0-9]*" cpu) + (endianness little)) (else (error "unknown CPU endianness" cpu))))) |