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author | Henrik Gramner <henrik@gramner.com> | 2020-06-16 01:07:19 +0200 |
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committer | H. Peter Anvin (Intel) <hpa@zytor.com> | 2020-06-27 16:12:37 -0700 |
commit | bca6b26a7ec580f2d99deb3d8c0254f98c09c0a9 (patch) | |
tree | 8c6febb393996114cfecbabdfdf736817a84d8e8 /x86/insns.dat | |
parent | 57c375305cf14265bb5ef468bef25cf465a4382a (diff) | |
download | nasm-bca6b26a7ec580f2d99deb3d8c0254f98c09c0a9.tar.gz |
insns.dat: Add Intel Control-Flow Enforcement Technology (CET) instructions
Add instructions for Intel Control Flow Enforcement Technology (CET).
Signed-off-by: Henrik Gramner <henrik@gramner.com>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Diffstat (limited to 'x86/insns.dat')
-rw-r--r-- | x86/insns.dat | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/x86/insns.dat b/x86/insns.dat index a59c5306..980c5943 100644 --- a/x86/insns.dat +++ b/x86/insns.dat @@ -5983,6 +5983,22 @@ ENCLS void [ np 0f 01 cf] SGX,FUTURE ENCLU void [ np 0f 01 d7] SGX,FUTURE ENCLV void [ np 0f 01 c0] SGX,FUTURE +;# Intel Control-Flow Enforcement Technology (CET) +CLRSSBSY mem64 [m: f3 0f ae /6] CET,FUTURE +ENDBR32 void [ f3 0f 1e fb] CET,FUTURE +ENDBR64 void [ f3 0f 1e fa] CET,FUTURE +INCSSPD reg32 [m: o32 f3 0f ae /5] CET,FUTURE +INCSSPQ reg64 [m: o64 f3 0f ae /5] CET,FUTURE,X64 +RDSSPD reg32 [m: o32 f3 0f 1e /1] CET,FUTURE +RDSSPQ reg64 [m: o64 f3 0f 1e /1] CET,FUTURE,X64 +RSTORSSP mem64 [m: f3 0f 01 /5] CET,FUTURE +SAVEPREVSSP void [ f3 0f 01 ea] CET,FUTURE +SETSSBSY void [ f3 0f 01 e8] CET,FUTURE +WRUSSD mem,reg32 [mr: o32 66 0f 38 f5 /r] CET,FUTURE +WRUSSQ mem,reg64 [mr: o64 66 0f 38 f5 /r] CET,FUTURE,X64 +WRSSD mem,reg32 [mr: o32 0f 38 f6 /r] CET,FUTURE +WRSSQ mem,reg64 [mr: o64 0f 38 f6 /r] CET,FUTURE,X64 + ;# Systematic names for the hinting nop instructions ; These should be last in the file HINT_NOP0 rm16 [m: o16 0f 18 /0] P6,UNDOC |