summaryrefslogtreecommitdiff
path: root/drm/nouveau/nvkm/engine/device/base.c
diff options
context:
space:
mode:
Diffstat (limited to 'drm/nouveau/nvkm/engine/device/base.c')
-rw-r--r--drm/nouveau/nvkm/engine/device/base.c138
1 files changed, 69 insertions, 69 deletions
diff --git a/drm/nouveau/nvkm/engine/device/base.c b/drm/nouveau/nvkm/engine/device/base.c
index 3734d1fb7..04895322d 100644
--- a/drm/nouveau/nvkm/engine/device/base.c
+++ b/drm/nouveau/nvkm/engine/device/base.c
@@ -85,7 +85,7 @@ nv4_chipset = {
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
-// .timer = nv04_timer_new,
+ .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv04_fifo_new,
@@ -105,7 +105,7 @@ nv5_chipset = {
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
-// .timer = nv04_timer_new,
+ .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv04_fifo_new,
@@ -126,7 +126,7 @@ nv10_chipset = {
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
-// .timer = nv04_timer_new,
+ .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .gr = nv10_gr_new,
@@ -145,7 +145,7 @@ nv11_chipset = {
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
-// .timer = nv04_timer_new,
+ .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv10_fifo_new,
@@ -166,7 +166,7 @@ nv15_chipset = {
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
-// .timer = nv04_timer_new,
+ .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv10_fifo_new,
@@ -187,7 +187,7 @@ nv17_chipset = {
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
-// .timer = nv04_timer_new,
+ .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
@@ -208,7 +208,7 @@ nv18_chipset = {
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
-// .timer = nv04_timer_new,
+ .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
@@ -229,7 +229,7 @@ nv1a_chipset = {
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
-// .timer = nv04_timer_new,
+ .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv10_fifo_new,
@@ -250,7 +250,7 @@ nv1f_chipset = {
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
-// .timer = nv04_timer_new,
+ .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
@@ -271,7 +271,7 @@ nv20_chipset = {
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
-// .timer = nv04_timer_new,
+ .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
@@ -292,7 +292,7 @@ nv25_chipset = {
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
-// .timer = nv04_timer_new,
+ .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
@@ -313,7 +313,7 @@ nv28_chipset = {
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
-// .timer = nv04_timer_new,
+ .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
@@ -334,7 +334,7 @@ nv2a_chipset = {
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
-// .timer = nv04_timer_new,
+ .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
@@ -355,7 +355,7 @@ nv30_chipset = {
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
-// .timer = nv04_timer_new,
+ .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
@@ -376,7 +376,7 @@ nv31_chipset = {
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
-// .timer = nv04_timer_new,
+ .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
@@ -398,7 +398,7 @@ nv34_chipset = {
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
-// .timer = nv04_timer_new,
+ .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
@@ -420,7 +420,7 @@ nv35_chipset = {
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
-// .timer = nv04_timer_new,
+ .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
@@ -441,7 +441,7 @@ nv36_chipset = {
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
-// .timer = nv04_timer_new,
+ .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
@@ -464,7 +464,7 @@ nv40_chipset = {
.mc = nv40_mc_new,
.mmu = nv04_mmu_new,
.therm = nv40_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv40_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@@ -489,7 +489,7 @@ nv41_chipset = {
.mc = nv40_mc_new,
.mmu = nv41_mmu_new,
.therm = nv40_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@@ -514,7 +514,7 @@ nv42_chipset = {
.mc = nv40_mc_new,
.mmu = nv41_mmu_new,
.therm = nv40_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@@ -539,7 +539,7 @@ nv43_chipset = {
.mc = nv40_mc_new,
.mmu = nv41_mmu_new,
.therm = nv40_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@@ -564,7 +564,7 @@ nv44_chipset = {
.mc = nv44_mc_new,
.mmu = nv44_mmu_new,
.therm = nv40_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@@ -589,7 +589,7 @@ nv45_chipset = {
.mc = nv40_mc_new,
.mmu = nv04_mmu_new,
.therm = nv40_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@@ -614,7 +614,7 @@ nv46_chipset = {
.mc = nv44_mc_new,
.mmu = nv44_mmu_new,
.therm = nv40_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@@ -639,7 +639,7 @@ nv47_chipset = {
.mc = nv40_mc_new,
.mmu = nv41_mmu_new,
.therm = nv40_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@@ -664,7 +664,7 @@ nv49_chipset = {
.mc = nv40_mc_new,
.mmu = nv41_mmu_new,
.therm = nv40_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@@ -689,7 +689,7 @@ nv4a_chipset = {
.mc = nv44_mc_new,
.mmu = nv44_mmu_new,
.therm = nv40_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@@ -714,7 +714,7 @@ nv4b_chipset = {
.mc = nv40_mc_new,
.mmu = nv41_mmu_new,
.therm = nv40_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@@ -739,7 +739,7 @@ nv4c_chipset = {
.mc = nv4c_mc_new,
.mmu = nv44_mmu_new,
.therm = nv40_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@@ -764,7 +764,7 @@ nv4e_chipset = {
.mc = nv4c_mc_new,
.mmu = nv44_mmu_new,
.therm = nv40_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@@ -792,7 +792,7 @@ nv50_chipset = {
.mmu = nv50_mmu_new,
.mxm = nv50_mxm_new,
.therm = nv50_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .disp = nv50_disp_new,
// .dma = nv50_dma_new,
@@ -817,7 +817,7 @@ nv63_chipset = {
.mc = nv4c_mc_new,
.mmu = nv44_mmu_new,
.therm = nv40_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@@ -842,7 +842,7 @@ nv67_chipset = {
.mc = nv4c_mc_new,
.mmu = nv44_mmu_new,
.therm = nv40_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@@ -867,7 +867,7 @@ nv68_chipset = {
.mc = nv4c_mc_new,
.mmu = nv44_mmu_new,
.therm = nv40_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@@ -895,7 +895,7 @@ nv84_chipset = {
.mmu = nv50_mmu_new,
.mxm = nv50_mxm_new,
.therm = g84_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .bsp = g84_bsp_new,
// .cipher = g84_cipher_new,
@@ -926,7 +926,7 @@ nv86_chipset = {
.mmu = nv50_mmu_new,
.mxm = nv50_mxm_new,
.therm = g84_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .bsp = g84_bsp_new,
// .cipher = g84_cipher_new,
@@ -957,7 +957,7 @@ nv92_chipset = {
.mmu = nv50_mmu_new,
.mxm = nv50_mxm_new,
.therm = g84_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .bsp = g84_bsp_new,
// .cipher = g84_cipher_new,
@@ -988,7 +988,7 @@ nv94_chipset = {
.mmu = nv50_mmu_new,
.mxm = nv50_mxm_new,
.therm = g84_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .bsp = g84_bsp_new,
// .cipher = g84_cipher_new,
@@ -1015,7 +1015,7 @@ nv96_chipset = {
.devinit = g84_devinit_new,
.mc = g94_mc_new,
.bus = g94_bus_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
.fb = g84_fb_new,
.imem = nv50_instmem_new,
.mmu = nv50_mmu_new,
@@ -1046,7 +1046,7 @@ nv98_chipset = {
.devinit = g98_devinit_new,
.mc = g98_mc_new,
.bus = g94_bus_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
.fb = g84_fb_new,
.imem = nv50_instmem_new,
.mmu = nv50_mmu_new,
@@ -1081,7 +1081,7 @@ nva0_chipset = {
.mmu = nv50_mmu_new,
.mxm = nv50_mxm_new,
.therm = g84_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .bsp = g84_bsp_new,
// .cipher = g84_cipher_new,
@@ -1113,7 +1113,7 @@ nva3_chipset = {
.mxm = nv50_mxm_new,
.pmu = gt215_pmu_new,
.therm = gt215_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gt215_ce_new,
// .disp = gt215_disp_new,
@@ -1146,7 +1146,7 @@ nva5_chipset = {
.mxm = nv50_mxm_new,
.pmu = gt215_pmu_new,
.therm = gt215_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gt215_ce_new,
// .disp = gt215_disp_new,
@@ -1178,7 +1178,7 @@ nva8_chipset = {
.mxm = nv50_mxm_new,
.pmu = gt215_pmu_new,
.therm = gt215_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gt215_ce_new,
// .disp = gt215_disp_new,
@@ -1209,7 +1209,7 @@ nvaa_chipset = {
.mmu = nv50_mmu_new,
.mxm = nv50_mxm_new,
.therm = g84_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .disp = g94_disp_new,
// .dma = nv50_dma_new,
@@ -1240,7 +1240,7 @@ nvac_chipset = {
.mmu = nv50_mmu_new,
.mxm = nv50_mxm_new,
.therm = g84_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .disp = g94_disp_new,
// .dma = nv50_dma_new,
@@ -1272,7 +1272,7 @@ nvaf_chipset = {
.mxm = nv50_mxm_new,
.pmu = gt215_pmu_new,
.therm = gt215_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gt215_ce_new,
// .disp = gt215_disp_new,
@@ -1306,7 +1306,7 @@ nvc0_chipset = {
.mxm = nv50_mxm_new,
.pmu = gf100_pmu_new,
.therm = gt215_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gf100_ce0_new,
// .ce[1] = gf100_ce1_new,
@@ -1341,7 +1341,7 @@ nvc1_chipset = {
.mxm = nv50_mxm_new,
.pmu = gf100_pmu_new,
.therm = gt215_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gf100_ce0_new,
// .disp = gt215_disp_new,
@@ -1375,7 +1375,7 @@ nvc3_chipset = {
.mxm = nv50_mxm_new,
.pmu = gf100_pmu_new,
.therm = gt215_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gf100_ce0_new,
// .disp = gt215_disp_new,
@@ -1409,7 +1409,7 @@ nvc4_chipset = {
.mxm = nv50_mxm_new,
.pmu = gf100_pmu_new,
.therm = gt215_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gf100_ce0_new,
// .ce[1] = gf100_ce1_new,
@@ -1444,7 +1444,7 @@ nvc8_chipset = {
.mxm = nv50_mxm_new,
.pmu = gf100_pmu_new,
.therm = gt215_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gf100_ce0_new,
// .ce[1] = gf100_ce1_new,
@@ -1479,7 +1479,7 @@ nvce_chipset = {
.mxm = nv50_mxm_new,
.pmu = gf100_pmu_new,
.therm = gt215_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gf100_ce0_new,
// .ce[1] = gf100_ce1_new,
@@ -1514,7 +1514,7 @@ nvcf_chipset = {
.mxm = nv50_mxm_new,
.pmu = gf100_pmu_new,
.therm = gt215_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gf100_ce0_new,
// .disp = gt215_disp_new,
@@ -1547,7 +1547,7 @@ nvd7_chipset = {
.mmu = gf100_mmu_new,
.mxm = nv50_mxm_new,
.therm = gf119_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .ce[0] = gf100_ce0_new,
// .disp = gf119_disp_new,
// .dma = gf119_dma_new,
@@ -1580,7 +1580,7 @@ nvd9_chipset = {
.mxm = nv50_mxm_new,
.pmu = gf119_pmu_new,
.therm = gf119_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gf100_ce0_new,
// .disp = gf119_disp_new,
@@ -1614,7 +1614,7 @@ nve4_chipset = {
.mxm = nv50_mxm_new,
.pmu = gk104_pmu_new,
.therm = gf119_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gk104_ce0_new,
// .ce[1] = gk104_ce1_new,
@@ -1650,7 +1650,7 @@ nve6_chipset = {
.mxm = nv50_mxm_new,
.pmu = gk104_pmu_new,
.therm = gf119_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gk104_ce0_new,
// .ce[1] = gk104_ce1_new,
@@ -1686,7 +1686,7 @@ nve7_chipset = {
.mxm = nv50_mxm_new,
.pmu = gf119_pmu_new,
.therm = gf119_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gk104_ce0_new,
// .ce[1] = gk104_ce1_new,
@@ -1716,7 +1716,7 @@ nvea_chipset = {
.mc = gk20a_mc_new,
.mmu = gf100_mmu_new,
.pmu = gk20a_pmu_new,
-// .timer = gk20a_timer_new,
+ .timer = gk20a_timer_new,
// .volt = gk20a_volt_new,
// .ce[2] = gk104_ce2_new,
// .dma = gf119_dma_new,
@@ -1746,7 +1746,7 @@ nvf0_chipset = {
.mxm = nv50_mxm_new,
.pmu = gk110_pmu_new,
.therm = gf119_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gk104_ce0_new,
// .ce[1] = gk104_ce1_new,
@@ -1782,7 +1782,7 @@ nvf1_chipset = {
.mxm = nv50_mxm_new,
.pmu = gk110_pmu_new,
.therm = gf119_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gk104_ce0_new,
// .ce[1] = gk104_ce1_new,
@@ -1818,7 +1818,7 @@ nv106_chipset = {
.mxm = nv50_mxm_new,
.pmu = gk208_pmu_new,
.therm = gf119_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gk104_ce0_new,
// .ce[1] = gk104_ce1_new,
@@ -1853,7 +1853,7 @@ nv108_chipset = {
.mxm = nv50_mxm_new,
.pmu = gk208_pmu_new,
.therm = gf119_therm_new,
-// .timer = nv04_timer_new,
+ .timer = nv41_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gk104_ce0_new,
// .ce[1] = gk104_ce1_new,
@@ -1888,7 +1888,7 @@ nv117_chipset = {
.mxm = nv50_mxm_new,
.pmu = gm107_pmu_new,
.therm = gm107_therm_new,
-// .timer = gk20a_timer_new,
+ .timer = gk20a_timer_new,
// .ce[0] = gk104_ce0_new,
// .ce[2] = gk104_ce2_new,
// .disp = gm107_disp_new,
@@ -1916,7 +1916,7 @@ nv124_chipset = {
.mmu = gf100_mmu_new,
.mxm = nv50_mxm_new,
.pmu = gm107_pmu_new,
-// .timer = gk20a_timer_new,
+ .timer = gk20a_timer_new,
// .ce[0] = gm204_ce0_new,
// .ce[1] = gm204_ce1_new,
// .ce[2] = gm204_ce2_new,
@@ -1945,7 +1945,7 @@ nv126_chipset = {
.mmu = gf100_mmu_new,
.mxm = nv50_mxm_new,
.pmu = gm107_pmu_new,
-// .timer = gk20a_timer_new,
+ .timer = gk20a_timer_new,
// .ce[0] = gm204_ce0_new,
// .ce[1] = gm204_ce1_new,
// .ce[2] = gm204_ce2_new,
@@ -1969,7 +1969,7 @@ nv12b_chipset = {
.mc = gk20a_mc_new,
.mmu = gf100_mmu_new,
.mmu = gf100_mmu_new,
-// .timer = gk20a_timer_new,
+ .timer = gk20a_timer_new,
// .ce[2] = gm204_ce2_new,
// .dma = gf119_dma_new,
// .fifo = gm20b_fifo_new,
View Lorry Controller Status