diff options
Diffstat (limited to 'drm/nouveau/nvkm/engine')
| -rw-r--r-- | drm/nouveau/nvkm/engine/device/base.c | 138 | ||||
| -rw-r--r-- | drm/nouveau/nvkm/engine/device/gf100.c | 9 | ||||
| -rw-r--r-- | drm/nouveau/nvkm/engine/device/gk104.c | 8 | ||||
| -rw-r--r-- | drm/nouveau/nvkm/engine/device/gm100.c | 4 | ||||
| -rw-r--r-- | drm/nouveau/nvkm/engine/device/nv04.c | 2 | ||||
| -rw-r--r-- | drm/nouveau/nvkm/engine/device/nv10.c | 8 | ||||
| -rw-r--r-- | drm/nouveau/nvkm/engine/device/nv20.c | 4 | ||||
| -rw-r--r-- | drm/nouveau/nvkm/engine/device/nv30.c | 5 | ||||
| -rw-r--r-- | drm/nouveau/nvkm/engine/device/nv40.c | 16 | ||||
| -rw-r--r-- | drm/nouveau/nvkm/engine/device/nv50.c | 14 | ||||
| -rw-r--r-- | drm/nouveau/nvkm/engine/device/user.c | 3 | ||||
| -rw-r--r-- | drm/nouveau/nvkm/engine/gr/nv50.c | 4 |
12 files changed, 72 insertions, 143 deletions
diff --git a/drm/nouveau/nvkm/engine/device/base.c b/drm/nouveau/nvkm/engine/device/base.c index 3734d1fb7..04895322d 100644 --- a/drm/nouveau/nvkm/engine/device/base.c +++ b/drm/nouveau/nvkm/engine/device/base.c @@ -85,7 +85,7 @@ nv4_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv04_fifo_new, @@ -105,7 +105,7 @@ nv5_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv04_fifo_new, @@ -126,7 +126,7 @@ nv10_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .gr = nv10_gr_new, @@ -145,7 +145,7 @@ nv11_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv10_fifo_new, @@ -166,7 +166,7 @@ nv15_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv10_fifo_new, @@ -187,7 +187,7 @@ nv17_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv17_fifo_new, @@ -208,7 +208,7 @@ nv18_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv17_fifo_new, @@ -229,7 +229,7 @@ nv1a_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv10_fifo_new, @@ -250,7 +250,7 @@ nv1f_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv17_fifo_new, @@ -271,7 +271,7 @@ nv20_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv17_fifo_new, @@ -292,7 +292,7 @@ nv25_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv17_fifo_new, @@ -313,7 +313,7 @@ nv28_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv17_fifo_new, @@ -334,7 +334,7 @@ nv2a_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv17_fifo_new, @@ -355,7 +355,7 @@ nv30_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv17_fifo_new, @@ -376,7 +376,7 @@ nv31_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv17_fifo_new, @@ -398,7 +398,7 @@ nv34_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv17_fifo_new, @@ -420,7 +420,7 @@ nv35_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv17_fifo_new, @@ -441,7 +441,7 @@ nv36_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv17_fifo_new, @@ -464,7 +464,7 @@ nv40_chipset = { .mc = nv40_mc_new, .mmu = nv04_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv40_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -489,7 +489,7 @@ nv41_chipset = { .mc = nv40_mc_new, .mmu = nv41_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -514,7 +514,7 @@ nv42_chipset = { .mc = nv40_mc_new, .mmu = nv41_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -539,7 +539,7 @@ nv43_chipset = { .mc = nv40_mc_new, .mmu = nv41_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -564,7 +564,7 @@ nv44_chipset = { .mc = nv44_mc_new, .mmu = nv44_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -589,7 +589,7 @@ nv45_chipset = { .mc = nv40_mc_new, .mmu = nv04_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -614,7 +614,7 @@ nv46_chipset = { .mc = nv44_mc_new, .mmu = nv44_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -639,7 +639,7 @@ nv47_chipset = { .mc = nv40_mc_new, .mmu = nv41_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -664,7 +664,7 @@ nv49_chipset = { .mc = nv40_mc_new, .mmu = nv41_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -689,7 +689,7 @@ nv4a_chipset = { .mc = nv44_mc_new, .mmu = nv44_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -714,7 +714,7 @@ nv4b_chipset = { .mc = nv40_mc_new, .mmu = nv41_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -739,7 +739,7 @@ nv4c_chipset = { .mc = nv4c_mc_new, .mmu = nv44_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -764,7 +764,7 @@ nv4e_chipset = { .mc = nv4c_mc_new, .mmu = nv44_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -792,7 +792,7 @@ nv50_chipset = { .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .therm = nv50_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv50_disp_new, // .dma = nv50_dma_new, @@ -817,7 +817,7 @@ nv63_chipset = { .mc = nv4c_mc_new, .mmu = nv44_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -842,7 +842,7 @@ nv67_chipset = { .mc = nv4c_mc_new, .mmu = nv44_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -867,7 +867,7 @@ nv68_chipset = { .mc = nv4c_mc_new, .mmu = nv44_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -895,7 +895,7 @@ nv84_chipset = { .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .therm = g84_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .bsp = g84_bsp_new, // .cipher = g84_cipher_new, @@ -926,7 +926,7 @@ nv86_chipset = { .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .therm = g84_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .bsp = g84_bsp_new, // .cipher = g84_cipher_new, @@ -957,7 +957,7 @@ nv92_chipset = { .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .therm = g84_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .bsp = g84_bsp_new, // .cipher = g84_cipher_new, @@ -988,7 +988,7 @@ nv94_chipset = { .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .therm = g84_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .bsp = g84_bsp_new, // .cipher = g84_cipher_new, @@ -1015,7 +1015,7 @@ nv96_chipset = { .devinit = g84_devinit_new, .mc = g94_mc_new, .bus = g94_bus_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, .fb = g84_fb_new, .imem = nv50_instmem_new, .mmu = nv50_mmu_new, @@ -1046,7 +1046,7 @@ nv98_chipset = { .devinit = g98_devinit_new, .mc = g98_mc_new, .bus = g94_bus_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, .fb = g84_fb_new, .imem = nv50_instmem_new, .mmu = nv50_mmu_new, @@ -1081,7 +1081,7 @@ nva0_chipset = { .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .therm = g84_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .bsp = g84_bsp_new, // .cipher = g84_cipher_new, @@ -1113,7 +1113,7 @@ nva3_chipset = { .mxm = nv50_mxm_new, .pmu = gt215_pmu_new, .therm = gt215_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gt215_ce_new, // .disp = gt215_disp_new, @@ -1146,7 +1146,7 @@ nva5_chipset = { .mxm = nv50_mxm_new, .pmu = gt215_pmu_new, .therm = gt215_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gt215_ce_new, // .disp = gt215_disp_new, @@ -1178,7 +1178,7 @@ nva8_chipset = { .mxm = nv50_mxm_new, .pmu = gt215_pmu_new, .therm = gt215_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gt215_ce_new, // .disp = gt215_disp_new, @@ -1209,7 +1209,7 @@ nvaa_chipset = { .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .therm = g84_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = g94_disp_new, // .dma = nv50_dma_new, @@ -1240,7 +1240,7 @@ nvac_chipset = { .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .therm = g84_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = g94_disp_new, // .dma = nv50_dma_new, @@ -1272,7 +1272,7 @@ nvaf_chipset = { .mxm = nv50_mxm_new, .pmu = gt215_pmu_new, .therm = gt215_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gt215_ce_new, // .disp = gt215_disp_new, @@ -1306,7 +1306,7 @@ nvc0_chipset = { .mxm = nv50_mxm_new, .pmu = gf100_pmu_new, .therm = gt215_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gf100_ce0_new, // .ce[1] = gf100_ce1_new, @@ -1341,7 +1341,7 @@ nvc1_chipset = { .mxm = nv50_mxm_new, .pmu = gf100_pmu_new, .therm = gt215_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gf100_ce0_new, // .disp = gt215_disp_new, @@ -1375,7 +1375,7 @@ nvc3_chipset = { .mxm = nv50_mxm_new, .pmu = gf100_pmu_new, .therm = gt215_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gf100_ce0_new, // .disp = gt215_disp_new, @@ -1409,7 +1409,7 @@ nvc4_chipset = { .mxm = nv50_mxm_new, .pmu = gf100_pmu_new, .therm = gt215_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gf100_ce0_new, // .ce[1] = gf100_ce1_new, @@ -1444,7 +1444,7 @@ nvc8_chipset = { .mxm = nv50_mxm_new, .pmu = gf100_pmu_new, .therm = gt215_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gf100_ce0_new, // .ce[1] = gf100_ce1_new, @@ -1479,7 +1479,7 @@ nvce_chipset = { .mxm = nv50_mxm_new, .pmu = gf100_pmu_new, .therm = gt215_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gf100_ce0_new, // .ce[1] = gf100_ce1_new, @@ -1514,7 +1514,7 @@ nvcf_chipset = { .mxm = nv50_mxm_new, .pmu = gf100_pmu_new, .therm = gt215_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gf100_ce0_new, // .disp = gt215_disp_new, @@ -1547,7 +1547,7 @@ nvd7_chipset = { .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, .therm = gf119_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .ce[0] = gf100_ce0_new, // .disp = gf119_disp_new, // .dma = gf119_dma_new, @@ -1580,7 +1580,7 @@ nvd9_chipset = { .mxm = nv50_mxm_new, .pmu = gf119_pmu_new, .therm = gf119_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gf100_ce0_new, // .disp = gf119_disp_new, @@ -1614,7 +1614,7 @@ nve4_chipset = { .mxm = nv50_mxm_new, .pmu = gk104_pmu_new, .therm = gf119_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gk104_ce0_new, // .ce[1] = gk104_ce1_new, @@ -1650,7 +1650,7 @@ nve6_chipset = { .mxm = nv50_mxm_new, .pmu = gk104_pmu_new, .therm = gf119_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gk104_ce0_new, // .ce[1] = gk104_ce1_new, @@ -1686,7 +1686,7 @@ nve7_chipset = { .mxm = nv50_mxm_new, .pmu = gf119_pmu_new, .therm = gf119_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gk104_ce0_new, // .ce[1] = gk104_ce1_new, @@ -1716,7 +1716,7 @@ nvea_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .pmu = gk20a_pmu_new, -// .timer = gk20a_timer_new, + .timer = gk20a_timer_new, // .volt = gk20a_volt_new, // .ce[2] = gk104_ce2_new, // .dma = gf119_dma_new, @@ -1746,7 +1746,7 @@ nvf0_chipset = { .mxm = nv50_mxm_new, .pmu = gk110_pmu_new, .therm = gf119_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gk104_ce0_new, // .ce[1] = gk104_ce1_new, @@ -1782,7 +1782,7 @@ nvf1_chipset = { .mxm = nv50_mxm_new, .pmu = gk110_pmu_new, .therm = gf119_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gk104_ce0_new, // .ce[1] = gk104_ce1_new, @@ -1818,7 +1818,7 @@ nv106_chipset = { .mxm = nv50_mxm_new, .pmu = gk208_pmu_new, .therm = gf119_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gk104_ce0_new, // .ce[1] = gk104_ce1_new, @@ -1853,7 +1853,7 @@ nv108_chipset = { .mxm = nv50_mxm_new, .pmu = gk208_pmu_new, .therm = gf119_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gk104_ce0_new, // .ce[1] = gk104_ce1_new, @@ -1888,7 +1888,7 @@ nv117_chipset = { .mxm = nv50_mxm_new, .pmu = gm107_pmu_new, .therm = gm107_therm_new, -// .timer = gk20a_timer_new, + .timer = gk20a_timer_new, // .ce[0] = gk104_ce0_new, // .ce[2] = gk104_ce2_new, // .disp = gm107_disp_new, @@ -1916,7 +1916,7 @@ nv124_chipset = { .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, .pmu = gm107_pmu_new, -// .timer = gk20a_timer_new, + .timer = gk20a_timer_new, // .ce[0] = gm204_ce0_new, // .ce[1] = gm204_ce1_new, // .ce[2] = gm204_ce2_new, @@ -1945,7 +1945,7 @@ nv126_chipset = { .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, .pmu = gm107_pmu_new, -// .timer = gk20a_timer_new, + .timer = gk20a_timer_new, // .ce[0] = gm204_ce0_new, // .ce[1] = gm204_ce1_new, // .ce[2] = gm204_ce2_new, @@ -1969,7 +1969,7 @@ nv12b_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mmu = gf100_mmu_new, -// .timer = gk20a_timer_new, + .timer = gk20a_timer_new, // .ce[2] = gm204_ce2_new, // .dma = gf119_dma_new, // .fifo = gm20b_fifo_new, diff --git a/drm/nouveau/nvkm/engine/device/gf100.c b/drm/nouveau/nvkm/engine/device/gf100.c index dcaa480cd..28421e6f1 100644 --- a/drm/nouveau/nvkm/engine/device/gf100.c +++ b/drm/nouveau/nvkm/engine/device/gf100.c @@ -28,7 +28,6 @@ gf100_identify(struct nvkm_device *device) { switch (device->chipset) { case 0xc0: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; @@ -43,7 +42,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xc4: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; @@ -58,7 +56,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xc3: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; @@ -72,7 +69,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xce: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; @@ -87,7 +83,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xcf: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; @@ -101,7 +96,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xc1: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; @@ -115,7 +109,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass; break; case 0xc8: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; @@ -130,7 +123,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xd9: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; @@ -144,7 +136,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass; break; case 0xd7: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; diff --git a/drm/nouveau/nvkm/engine/device/gk104.c b/drm/nouveau/nvkm/engine/device/gk104.c index 048f1beab..25d909245 100644 --- a/drm/nouveau/nvkm/engine/device/gk104.c +++ b/drm/nouveau/nvkm/engine/device/gk104.c @@ -28,7 +28,6 @@ gk104_identify(struct nvkm_device *device) { switch (device->chipset) { case 0xe4: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; @@ -44,7 +43,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; break; case 0xe7: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; @@ -60,7 +58,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; break; case 0xe6: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; @@ -76,7 +73,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; break; case 0xea: - device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; @@ -86,7 +82,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass; break; case 0xf0: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; @@ -102,7 +97,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; break; case 0xf1: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; @@ -118,7 +112,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; break; case 0x106: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; @@ -133,7 +126,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; break; case 0x108: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; diff --git a/drm/nouveau/nvkm/engine/device/gm100.c b/drm/nouveau/nvkm/engine/device/gm100.c index e2d00b465..4b570a27e 100644 --- a/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drm/nouveau/nvkm/engine/device/gm100.c @@ -28,7 +28,6 @@ gm100_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x117: - device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; #if 0 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -54,7 +53,6 @@ gm100_identify(struct nvkm_device *device) /* looks to be some non-trivial changes */ /* priv ring says no to 0x10eb14 writes */ #endif - device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; #if 0 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; #endif @@ -77,7 +75,6 @@ gm100_identify(struct nvkm_device *device) /* looks to be some non-trivial changes */ /* priv ring says no to 0x10eb14 writes */ #endif - device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; #if 0 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; #endif @@ -97,7 +94,6 @@ gm100_identify(struct nvkm_device *device) break; case 0x12b: - device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gm20b_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; diff --git a/drm/nouveau/nvkm/engine/device/nv04.c b/drm/nouveau/nvkm/engine/device/nv04.c index 99e837f48..1b2ebda82 100644 --- a/drm/nouveau/nvkm/engine/device/nv04.c +++ b/drm/nouveau/nvkm/engine/device/nv04.c @@ -28,7 +28,6 @@ nv04_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x04: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; @@ -36,7 +35,6 @@ nv04_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x05: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; diff --git a/drm/nouveau/nvkm/engine/device/nv10.c b/drm/nouveau/nvkm/engine/device/nv10.c index 6f106f632..c5ecdddfb 100644 --- a/drm/nouveau/nvkm/engine/device/nv10.c +++ b/drm/nouveau/nvkm/engine/device/nv10.c @@ -28,13 +28,11 @@ nv10_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x10: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x15: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -42,7 +40,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x16: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -50,7 +47,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x1a: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -58,7 +54,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x11: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -66,7 +61,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x17: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -74,7 +68,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x1f: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -82,7 +75,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x18: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; diff --git a/drm/nouveau/nvkm/engine/device/nv20.c b/drm/nouveau/nvkm/engine/device/nv20.c index 2a84c3ff8..104ed4f09 100644 --- a/drm/nouveau/nvkm/engine/device/nv20.c +++ b/drm/nouveau/nvkm/engine/device/nv20.c @@ -28,7 +28,6 @@ nv20_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x20: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -36,7 +35,6 @@ nv20_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x25: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -44,7 +42,6 @@ nv20_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x28: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -52,7 +49,6 @@ nv20_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x2a: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; diff --git a/drm/nouveau/nvkm/engine/device/nv30.c b/drm/nouveau/nvkm/engine/device/nv30.c index b03249099..5ea263c85 100644 --- a/drm/nouveau/nvkm/engine/device/nv30.c +++ b/drm/nouveau/nvkm/engine/device/nv30.c @@ -28,7 +28,6 @@ nv30_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x30: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -36,7 +35,6 @@ nv30_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x35: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -44,7 +42,6 @@ nv30_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x31: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -53,7 +50,6 @@ nv30_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x36: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -62,7 +58,6 @@ nv30_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x34: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; diff --git a/drm/nouveau/nvkm/engine/device/nv40.c b/drm/nouveau/nvkm/engine/device/nv40.c index 5aa4cac00..31df1b8ae 100644 --- a/drm/nouveau/nvkm/engine/device/nv40.c +++ b/drm/nouveau/nvkm/engine/device/nv40.c @@ -28,7 +28,6 @@ nv40_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x40: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -39,7 +38,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x41: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -50,7 +48,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x42: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -61,7 +58,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x43: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -72,7 +68,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x45: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -83,7 +78,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x47: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -94,7 +88,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x49: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -105,7 +98,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4b: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -116,7 +108,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x44: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -127,7 +118,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x46: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -138,7 +128,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4a: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -149,7 +138,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4c: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -160,7 +148,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4e: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -171,7 +158,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x63: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -182,7 +168,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x67: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -193,7 +178,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x68: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; diff --git a/drm/nouveau/nvkm/engine/device/nv50.c b/drm/nouveau/nvkm/engine/device/nv50.c index 8cc924046..e01add48c 100644 --- a/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drm/nouveau/nvkm/engine/device/nv50.c @@ -28,7 +28,6 @@ nv50_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x50: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass; @@ -39,7 +38,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass; break; case 0x84: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -53,7 +51,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x86: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -67,7 +64,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x92: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -81,7 +77,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x94: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -95,7 +90,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x96: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -109,7 +103,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x98: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -123,7 +116,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0xa0: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -137,7 +129,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass; break; case 0xaa: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -151,7 +142,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0xac: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -165,7 +155,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0xa3: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -180,7 +169,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; break; case 0xa5: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -194,7 +182,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; break; case 0xa8: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -208,7 +195,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; break; case 0xaf: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; diff --git a/drm/nouveau/nvkm/engine/device/user.c b/drm/nouveau/nvkm/engine/device/user.c index c5da091c0..a9df61bf3 100644 --- a/drm/nouveau/nvkm/engine/device/user.c +++ b/drm/nouveau/nvkm/engine/device/user.c @@ -118,14 +118,13 @@ static int nvkm_udevice_time(struct nvkm_udevice *udev, void *data, u32 size) { struct nvkm_device *device = udev->device; - struct nvkm_timer *tmr = device->timer; union { struct nv_device_time_v0 v0; } *args = data; int ret; if (nvif_unpack(args->v0, 0, 0, false)) { - args->v0.time = tmr->read(tmr); + args->v0.time = nvkm_timer_read(device->timer); } return ret; diff --git a/drm/nouveau/nvkm/engine/gr/nv50.c b/drm/nouveau/nvkm/engine/gr/nv50.c index 403d2c9af..2a5bc9270 100644 --- a/drm/nouveau/nvkm/engine/gr/nv50.c +++ b/drm/nouveau/nvkm/engine/gr/nv50.c @@ -218,7 +218,7 @@ g84_gr_tlb_flush(struct nvkm_engine *engine) spin_lock_irqsave(&gr->lock, flags); nvkm_mask(device, 0x400500, 0x00000001, 0x00000000); - start = tmr->read(tmr); + start = nvkm_timer_read(tmr); do { idle = true; @@ -237,7 +237,7 @@ g84_gr_tlb_flush(struct nvkm_engine *engine) idle = false; } } while (!idle && - !(timeout = tmr->read(tmr) - start > 2000000000)); + !(timeout = nvkm_timer_read(tmr) - start > 2000000000)); if (timeout) { nvkm_error(subdev, "PGRAPH TLB flush idle timeout fail\n"); |