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* Update to use bitmask instead of bit for parked configurationHEADmasterSowjanya Komatineni2019-07-014-150/+154
| | | | | | | | | | | | | | Parked bits for SDMMC2 and SDMMC4 are part of CFGPAD register rather than pinmux registers and contains bit for each of their pins. So updating pinctrl Tegra driver to use bitmask for parked configuration rather than bit. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> [treding@nvidia.com: reshuffle fields to match driver order] [treding@nvidia.com: use bitmask 0 for unsupported] Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Rename jetson-nano-sd to p3450-porgStephen Warren2019-07-011-0/+0
| | | | | | | | | This matches the downstream L4T U-Boot port, which allows the files generated by tegra-pinmux-scripts to be used directly without editing. The mandate to use name jetson-nano-sd in these scripts has been removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
* Add Jetson Nano Developer Kit (SD) BoardStephen Warren2019-06-171-0/+173
| | | | | | | v1.0 downloaded from the following URL on 2019/06/17: https://developer.nvidia.com/embedded/downloads Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add Colorado Engineering TK1-SOM boardPeter.Chubb@data61.csiro.au2016-08-301-0/+202
| | | | | | | | The TK1 SOM from Colorado Engineering is a small form-factor board similar to the Jetson TK1. Signed-off-by: Peter Chubb <peter.chubb@data61.csiro.au> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* soc: Avoid parked_reg and parked_bankLaxman Dewangan2016-05-034-4/+0
| | | | | | | | | | | | | | | | | | | | NVIDIA's Tegra210 support the park bit to make pinmux configuration enable/disable. If parked bit is 1 then configuration does not apply and if it is 0 then pinmux configuration applies. This is to support to avoid any glitch in pinmux configurations. The parked bit is part of mux register and mux bank and hence it is not required to have member for the parked_reg and parked bank very similar to other bit field of the same register. Remove the need of the parked register and parked bank and get whether parked function supported or not by parked_bit. This is to make the parked bit handling same as other fields of mux registers. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Import latest Jetson TK1 spreadsheetStephen Warren2016-04-211-1/+5
| | | | | | | | | | | | | This imports v11 of "Jetson TK1 Development Platform Pin Mux" from https://developer.nvidia.com/embedded/downloads. The new version defines the mux option for the MIPI pad ctrl selection. The OWR pin no longer has an entry in the configuration table because the only mux option it support is OWR, that feature isn't supported, and hence can't conflict with any other pin. This pin can only usefully be used as a GPIO. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* soc: Add support for Parked bits for Tegra210Rhyland Klein2016-04-074-0/+12
| | | | | | | | | Tegra210 has a parked bit for each pin. Add code to express this by updating the kernel driver MACROs to add in parked_* fields so that the kernel can handle them as it sees fit. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add the Tegra210-smaug boardRhyland Klein2016-04-071-0/+173
| | | | | | | Tegra210-smaug is the name for the Google Pixel C platform. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* remove invalid uses of rsvd1 from beaver configLucas Stach2016-02-241-15/+15
| | | | | | | Replace by actual function names of pinmux option 1. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* p2371-2180: import latest spreadsheetStephen Warren2015-09-211-19/+19
| | | | | | | | | In order to avoid any assumptions about any device connected to P2371-2180's expansion connector, the latest pinmux spreadsheet configures all muxable pins on that connector to be GPIO inputs, with on-chip pulls where appropriate. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add P2371-2180 boardStephen Warren2015-07-301-0/+173
| | | | | | P2371-2180 is a Tegra210 reference board. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add P2371-0000 boardStephen Warren2015-07-241-0/+173
| | | | | | P2371-0000 is a Tegra210 development board. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add E2220-1170 boardStephen Warren2015-07-241-0/+173
| | | | | | | | | | | | | | E2220-1170 is a Tegra210 reference board. The following pins have missing gpio_init_val data in the spreadsheet, and were manually fixed to be out0 per discussion with the systems engineering team: lcd_bl_en_pv1 lcd_rst_pv2 usb_vbus_en1_pcc5 Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add support for P2571 boardStephen Warren2015-06-191-0/+173
| | | | | | P2571 is an NVIDIA reference board for the Tegra210 Soc. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Support TPM on nyan boardsSimon Glass2015-05-142-4/+4
| | | | | | | There is a TPM on I2C3, so set up the pinmux for that. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add support for MIPI pad ctrl groups in U-Boot driver generatorStephen Warren2015-03-251-0/+1
| | | | Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Support Tegra210Stephen Warren2015-02-254-2/+863
| | | | | | | | | | | | | | | | | | | | | | | | | Tegra210 changes the pinmux HW in a few ways; at least: - The set of drive groups is much more 1:1 with the set of pins. Most pins have an associated drive group register as well as an associated pinmux register, and most drive groups cover a single pin. - Some register fields have moved from the drive group registers into the pinmux registers. - The set of available options for each pin and group varies relative to previous chips, and hence the register layouts vary a bit too. This patch updates tegra-pinmux-scripts minimally to handle these changes, to a level equivalent to the support for previous chips. For example, some new options such as per-pin schmitt aren't handled since the syseng-supplied pinmux spreadsheets don't provide a value for this option. csv-to-board-tegra124-xlsx.py is renamed to csv-to-board.py since it now supports boards using different SoCs, and it's not worth encoding all supported SoCs in the filename (Tegra30/114 aren't supported by it, hence the previous naming). Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: import latest Jetson TK1 pinmuxStephen Warren2015-02-171-120/+120
| | | | | | | | | | | | | | | | | | syseng has revamped the Jetson TK1 pinmux spreadsheet, basing the content completely on correct configuration for the board/schematic, rather than the previous version which was based on the bare minimum changes relative to another reference board. The new spreadsheet sets TRISTATE for any input-only pins. This only works correctly if the global CLAMP bit is not set, so any code importing this updated version will need to be adjusted accordingly. Apparently syseng have changed their mind since the previous advice that this needed to be set:-/ This content comes from Jetson_TK1_customer_pinmux.xlsm (v09) downloaded from https://developer.nvidia.com/hardware-design-and-development. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add support for MIPI Pad Ctrl groups on Tegra124Stephen Warren2015-02-111-0/+30
| | | | | | | | | This aligns the output with what's check into the kernel. There are now only minor white-space/formatting differences. I'll fix those in the kernel soon, when I send patched to add Tegra210 SoC support. Cc: Sean Paul <seanpaul@chromium.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add support for Nyan-bigSimon Glass2015-02-031-0/+198
| | | | | | | | | | Add support for Tegra124 Nyan-big. Pinmux is based on norrin with a single change for the reset GPIO. Signed-off-by: Simon Glass <sjg@chromium.org> [tomeu.vizoso@collabora.com: remove pull from dp_hpd_pff0] Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add support for Nyan-blazeTomeu Vizoso2015-01-221-0/+198
| | | | | | | Add support for Tegra124 Nyan-blaze, very similar to Nyan-big. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* add support for Beaver boardLucas Stach2015-01-091-0/+248
| | | | | | | | | This leaves some pins unconfigured, but is all I could work out from the existing U-Boot and Kernel code/DTs. Signed-off-by: Lucas Stach <dev@lynxeye.de> [added not about the data source] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Jetson TK1: add missing PCIe-related pin configurationStephen Warren2014-08-221-0/+5
| | | | | | | | | | | | | The Jetson TK1 spreadsheet is missing configuration for the PCIe clk_req, rst, and wake pins. This causes the generated pinmux tables to also omit any configuration for these pins, which in turn causes U-Boot's and the Linux Kernel's PCIe support to fail. Manually add configuration for these pins. The values here match the values found in the downstream L4T kernel, and common sense based on the usage of these pins. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Add support for NorrinAllen Martin2014-08-041-0/+198
| | | | | | | | | Add support for Tegra124 Norrin FFD reference board (PM370). Pinmux is based on PM370_T124_customer_pinmux_1.1 spreadsheet. Signed-off-by: Allen Martin <amartin@nvidia.com> [swarren, kept supported_boards[] sorted] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Import latest Venice2 spreadsheetStephen Warren2014-07-011-4/+4
| | | | | | | A few fixes were made to the spreadsheet, including one that removes the need for the special-case in the import script. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Initial set of scriptsStephen Warren2014-04-225-0/+2073
A set of scripts to generate Linux kernel and U-Boot pinmux drivers and board pinmux configuration tables. Also included are scripts to convert existing Linux kernel pinmux drivers and NV-internal spreadsheets to the internal data representation. SoC configuration files are included for Tegra30, Tegra114, and Tegra124. Board configuration files are included for Jetson TK1 and Venice2. configs/tegra30.soc configs/tegra114.soc configs/tegra124.soc SoC pin definitions configs/jetson-tk1.board configs/venice2.board Board configurations soc-to-kernel-pinctrl-driver.py soc-to-uboot-driver.py Generate Linux kernel and U-Boot pinmux drivers board-to-kernel-dt.py board-to-uboot.py Generate board configuration tables for the Linux kernel (DT) and U-Boot. kernel-pinctrl-driver-to-soc.py Convert an existing Linux kernel pinmux driver to the internal representation of an SoC used by this project. csv-to-board-tegra124-xlsx.py Convert an NV-internal board configuration spreadsheet to the internal representation of a board configuration used by this project. tegra_pmx_board_parser.py tegra_pmx_parser_utils.py tegra_pmx_soc_parser.py tegra_pmx_utils.py Internal Python modules used to parse the internal data representations, and various other utilities. Signed-off-by: Stephen Warren <swarren@nvidia.com>
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